yusuke1997/dblp-id-title huggingface dataset:
A Capacitor-Saver Redundant SAR ADC to Optimize Readout in Compute In-Memory Systems
Biometric-Aware Pixel Fused Crossbars
Simulation of Switched-Current Systems
CMOS High Power SPDT Switch using Multigate Structure
Low-Voltage Low-Power Fully-Integratable Automatic Gain Controls
Widely-Tunable RF Receiver Employing Synthetic Diversity for Interference Mitigation
0.65V sigma-delta modulators
GDFT types mapping algorithms and structured regular FPGA implementation
Segmented mismatch-shaping D/A conversion
An Efficient Intra Mode Selection Algorithm For H.264 Based On Fast Edge Classification
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile
Steady-state analysis for hybrid AC/DC microgrids
Analysis of hardlimiting parallel interference cancellation (PIC) for synchronous CDMA communication
Spatial varying filtering for color filter array interpolation in digital still cameras
ROFD: Event-based 5k-fps Real-Time Optical Flow Detector for Transient Radiant Expanding Flares
Fine-grain thermal profiling and sensor insertion for FPGAs
Motion Mapping for MPEG-2 to H.264/AVC Transcoding
Transmit architectures and power control schemes for low cost highly integrated transceivers for GSM/EDGE applications
VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization
Battery state-of-charge estimation prototype using EMF voltage prediction
Collaborative Localization Based on Traffic Landmarks for Autonomous Driving
Autonomous Monitoring of Fat, Water, and Sodium Content in Cheese Products using Low-Field NMR
A new technique for automatic error correction in Sigma-Delta modulators
A high-throughput LDPC decoder architecture for high-rate WPAN systems
A hybrid system for automatic fingerprint identification
Residue arithmetic circuits using a signed-digit number representation
Full digital implementation of a chaotic time-delay sampled-data system
A linear phase detector for arbitrary clock signals
Intelligent cage for remotely powered freely moving animal telemetry systems
Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC
A wide linear range four quadrant multiplier in subthreshold CMOS
USR-LUT: A High-Efficient Universal Super Resolution Accelerator with Lookup Table
A 70.8 dB 0.0045 mm 2 Low-power Continuous-Time Incremental Delta-Sigma Modulator for Multi-Site Neural Recording Interfaces
Performance bound of multiple hypotheses classification in compressed sensing
An approach to behavioral synthesis for loop-based BIST
A Class of Linear Cyclic-Invariant Filter for Parallel Filtering of Discrete-Time Signals
Hardware efficient approximative matrix inversion for linear pre-coding in massive MIMO
An effective phase detector for phase-locked loops with wide capture range and fast acquisition time
A LP/HP UMTS/GSM ΣΔ ADC suited for a Zero-IF/Low-IF receiver
An Expandable Digital Delay Line using Phase Interpolator with Duty Cycle Correction Capability
An IIR architecture for BSS in strong nonlinear convolutive environments
Delay Locked Loop Modulation Driver with Optimal Current Spreading: an Enabler for Megapixel iToF Sensors
A low current consumption CMOS latched comparator for body-implanted chip
Two stage, least squares design of biorthogonal filter banks
EEG-Based Emotion Classification Using Joint Adaptation Networks
Flexible electrical circuits printed on polymers using graphene-cellulose inks
Terminal attractor based back propagation learning for feedforward neural networks
Low-power comb decimation filter for RF Sigma-Delta ADCs
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS
Enabling Embedded Learning and Classification implemented on SoC FPAA devices
Designing Efficient Inductive Power Links for Implantable Devices
Web search steganalysis: some challenges and approaches
Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product
IP based reconfigurable digital platform for satellite communications
Symbolic analysis and optimization of piezo-electromechanical systems
A compact linearly tunable low voltage triode OTA using self-cascodes
A Fast Convergence Algorithm for L2-Sensitivity Minimization of 2-D Separable-Denominator State-Space Digital Filters
Below-ground injection of floating-gate transistors for programmable analog circuits
Peak noise prediction in loosely coupled interconnect [VLSI circuits]
Some two-transistor circuits possess more than three operating points
A Two-Stage Digital Predistortion Method for Quadrature Digital Power Amplifiers
Quantitative comparison of the power reduction techniques for samsung reconfigurable processor
Exploration of energy requirements at the output of an LNA from a thermodynamic perspective
A 1.575GHz, 1.63mW CMOS Injection-Locked Ring Oscillator Powered by FBAR-Based PLL Reference
Graph QMF with flatness constraints
Modified Compressed Sparse Row Format for Accelerated FPGA-Based Sparse Matrix Multiplication
Reconstruction of non-uniformly sampled signal using transposed Farrow structure
Design of analog audio classifiers with AdaBoost-Based feature selection
Feature extraction and analysis using memristor networks
A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter
Problem dimensionality reduction in design of optimal IIR filters
Pespectives of TFET devices in ultra-low power charge pumps for thermo-electric energy sources
Optimizing Sparse/Dense VEGETA Accelerator Performance with Microscaling Quantization
HeNCoG: A Heterogeneous Near-memory Computing Architecture for Energy Efficient GCN Acceleration
Combined LNA and Mixer Circuits for 2.4 GHz ISM Band
A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing
Pipeline Signal Process Scheme for Saving Power Module Controllers in Power Management Unit
Design of composite filters with equiripple passbands and least-squares stopbands
Tensor-product wavelet vs. Mallat decomposition: a comparative analysis
Audio source separation based on independent component analysis
An efficient multidimensional decimation-in-frequency FHT algorithm based on the radix-2/4 approach
VLSI circuits with fractal layout for spatial image decorrelation
Convergent regions of Newton homotopy methods for nonlinear systems: theory and computational applications
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip
Design and optimization of two motion detection circuits for video monitoring system
A study of floating-point architectures for pipelined RISC processors
A self-calibrated bandgap voltage reference with 0.5 ppm/°C temperature coefficient
CMOS circuit design and implementation of the discrete time chaotic chip
Dynamic ADC and Equalizer Adaptation with Background SNR Monitoring for a DSP-Based PAM-4 Receiver
An Artifact-Resilient Neural Recording Front-end with Rail-to-Rail DM and CM Offset Correction
Configurable conduction delay circuits for high spiking rates
Automated Placement for a Leaf Cell Generator
A robust background calibration technique for switched-capacitor pipelined ADCs
Modified SDF Architecture for Mixed DIF/DIT FFT
An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings
Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects
A novel approach of adaptive feedback cancellation for hearing aids
Design considerations of a floating-point ADC with embedded S/H
Orthogonal space time code based partial rank affine projection adaptive filtering algorithm
Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits
Mismatch Shaping for Binary-Coded DAC
Recognition of power quality events using wavelet-based dynamic structural neural networks
Video coding for Internet and push-pull communication
A 20-Bit Sigma-Delta D/A for Audio Applications in 0.13um CMOS
A new Maxnet
Aliasing probability calculations in nonlinear compactors
On the Control of an Array of Chua's Systems
Rate Control for Hierarchical B-picture Coding with Scaling-factors
Background Calibration of Time-Interleaved ADC for Optical Coherent Receivers using Error Backpropagation Techniques
A 88%-Peak-Efficiency 10-mV-Voltage-Ripple Dual-Mode Switched-Capacitor DC-DC Converter for Ultra-Low-Power Battery Management
Implementation of pseudo linear feedback shift register physical unclonable function on silicon
Faster elliptic curve point multiplication based on a novel greedy base-2, 3 method
An improved speaker identification technique employing multiple representations of the linear prediction coefficients
Application resource management for exploitation of non-volatile memory in many-core systems
High performance MIMO detector based on bidirectional path preserving trellis search
Live Demonstration: Bioimpedance-Based Interaction for Virtual Reality
Discriminative learning strategy for efficient neural decision feedback equalizers
CMOS transimpedance amplifier for DVD applications
A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion
Live Demonstration: Phase Tracking Based Ultrasonic Tidal Breathing Monitor
A 36V biphasic stimulator with electrode monitoring circuit
Memory impact on the lifetime of a Wireless Sensor Node using a Semi-Markov model
An analytical, transistor-level energy model for SRAM-based caches
Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation
Two-level configuration for FPGA: A new design methodology based on a computing fabric
A task allocation method for the DTTR scheme based on task scheduling of fault patterns
A circuit implementation for dynamic thermal management techniques
An Architecture for Real-Time Wavelet Image Decomposition
Energy Efficient Voltage-Mode Simultaneous Bidirectional Transceiver for Serial Links
A 2KSPS 123dB Dynamic-Range SPAD-based Optical Sensor SoC with On-chip Auto-Gain-Control and FFT Processor for 100 μlux Light Illuminance and Flicker Detection
A low power battery management system for rechargeable wireless implantable electronics
Digitally controlled fully differential current conveyor: CMOS realization and applications
A new predictive method for all-pole modelling of speech spectra with a compressed set of parameters
Embedded RF switch for implantable telemetry systems designed in 130nm CMOS
Joint rate-distortion optimization for H.264/AVC intra coding based on cluster computing
A General Claws of Current Mode Filters
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost
A robust shot change detection method for content-based retrieval
Multi-Viewpoint Patterns and Occlusions Handling Using Hybrid Features for Vehicle Tracking
Multi-Phase Frequency Measurement Exploiting FPGA Mixed-Mode Clock Management for QCM-D Technology
Implementation oriented theory design issues on the DTCNN template generation
A simulation-based study for DRAM power reduction strategies in GPGPUs
Effective modeling of CT functions for fast simulations using MATLAB-Simulink and VHDLAMS applied to Sigma-Delta architectures
A 40 Gbps optical receiver analog front-end in 65 nm CMOS
Theoretical bases of convolution technique in gradient estimation of average quality index of electronic circuits
Lossless image coding based on lifting wavelet using discrete-time cellular neural network with multi-templates
Fast simulation techniques for phase noise analysis of oscillators
A Mini-Living Lab Project as a Pedagogical Approach to AI-driven Autonomous Systems in Undergraduate Engineering and CS+[X] Education
Steady state and dynamic security assessment in composite power systems
A Combined ISFET-Electric Field Actuation System for Enhanced Detection of DNA: A Proof-of-Concept
H infty control of DC-to-DC switching converters
A 0.6V CMOS Image Sensor with in-pixel biphasic current driver for biomedical application
Advanced Learning-Based Coding Tools for ECM: Intra Prediction and In-Loop Filtering
Multiple-description video coding based on JPEG 2000 MQ-coder registers
Design of Low-Cost Ground Penetrating Radar Receiving Circuit Based on Equivalent Sampling
A 2.4-GHz CMOS monolithic VCO based on an MOS varactor
Multiple sub-pixel interpolation filters with adaptive symmetry for high-resolution video coding
Area efficient CMOS charge pump circuits
A bipolar 2-GSample/s track-and-hold amplifier (THA) in 0.35 μm SiGe technology
Use or Produce - Carbon Impact of a Video Streaming Device
A pulse-based memristor programming circuit
Design flow of robust routed power distribution for low power ASIC
Physical synthesis for ASIC datapath circuits
Design of clock generation circuitry for high-speed subranging time-interleaved ADCs
A Scalable MIMO Detection Architecture with Non-sorted Multiple-candidate Selection
An adaptive Space-Time Coding / Spatial Multiplexing detector on FPGA
A novel pH-to-time ISFET pixel architecture with offset compensation
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform
PrefIQA: Human Preference Learning for AI-generated Image Quality Assessment
Near-Field WPT System Design for Concurrent Charging of Two Independent Loads
A 17.5 fJ/bit energy-efficient analog SRAM for mixed-signal processing
Area-effcient re-encoding scheme for NAND Flash Memory with multimode BCH Error correction
Improved-Booth encoding for low-power multipliers
Multi agent systems for circuit tolerance and sensitivity analysis
Solutions for image rejection CMOS LNA
Power efficient scalable precision rational digital to analogue converters
A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor
Recursive architectures for 2DLNS multiplication
Novel MIMO 4-DOF position control for Capsule Endoscope
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter
System-level design of low complexity CVNS feed forward neural network
Highly parallel image coding for many cores
Variability of supercapacitor fractional-order parameters extracted from discharging behavior using least squares optimization
Introduction of system level architecture exploration using the SpecC methodology
Segmentation of Vascular Regions in Ultrasound Images: A Deep Learning Approach
Performance analysis in chaotic-iteration-based ADCs
Binary image rotation using cellular neural networks
A low-power and high-speed equalizer for magnetic storage read channels
A simple class-AB transconductor in CMOS
Object-based multiresolution watermarking of images and video
A practical hardware design for the keypoint detection in the SIFT algorithm with a reduced memory requirement
Fortifying Strong PUFs: A Modeling Attack-Resilient Approach Using Weak PUF for IoT Device Security
Routing algorithms: architecture driven rerouting enhancement for FPGAs
Analog networks for mixed domain spatiotemporal filtering
AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem
Two microphones speech enhancement system based on a double affine projection algorithm
Energy-aware cache assessment of HEVC decoding
A VLSI architecture design of VLC encoder for high data rate video/image coding
A data driven circuit model for rechargeable batteries
A CMOS general-purpose sampled-data analogue microprocessor
An Ultra-low-power 10-Bit 100-kS/s Successive-approximation Analog-to-digital Converter
High-gain common-mode feedback circuits for differential log-domain filters
A 8-µW, 0.3-mm 2 RF-powered transponder with temperature sensor for wireless environmental monitoring
Circulant Matrices and the Stability of Ring CNNs
A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs
A Charge-Pump-Based SIMO Buck-Boost DC-DC Converter with Three Operation Modes
A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals
A low-power and high-frequency CMOS transceiver for chip-to-chip interconnection
Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach
A novel memoryless AES cipher architecture for networking applications
Voltage-clamped class E amplifier with a Zener diode across the choke coil
Weight Based Current Assisted Photonic Demodulator (WBCAPD) - Expansion towards Neuromorphic Applications
An improved Q-tuning scheme and a fully symmetric OTA
A programmable VLSI architecture for 2-D discrete wavelet transform
A design of orthogonal interleavers for multimodes turbo en-decoders
Multi-layer Public Transport Network Analysis
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells
Fault modeling and fault sampling for isolating faults in analog and mixed-signal circuits
A Mixed Precision, Multi-GPU Design for Large-scale Top-K Sparse Eigenproblems
Adaptive EMG neutralization using the modified QT
MIMO interconnects order reductions by using the global Arnoldi algorithm
An Implementation of a Low Complexity Integer Carrier Frequency Offset estimator for OFDM
A Switched Capacitor DC-DC Buck Converter for a Wide Input Voltage Range
Lp-Stability of a Class of Volterra Systems
Quantitative estimation of biological cell surface receptors by segmenting conventional fluorescence microscopy images
Architectures for analog motion estimation processors: a comparison
A Self-Compensated, Low-Offset Voltage Buffer for Input Impedance Boosting in Chopped Neural Front-Ends
On the AER convolution processors for FPGA
An Area-Efficient, Differential Resonant Ultrasound Pulser with 69% fCV 2 Dynamic Power Reduction
An Energy-Efficient Multi-Sensor Compressed Sensing System Employing Time-Mode Signal Processing Techniques
Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation
Closed-Loop Input Impedance of PWM Buck-Derived DC-DC Converters
A 77.8-dB DR, 114.2 fJ/Step Amplifier-Less Current-to-Digital Converter
A triple port RAM based low power commutator architecture for a pipelined FFT processor
Logic-in-Memory architecture made real
Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip
Conventional CMOS OTAs Driving nF-Range Capacitive Loads
Automatic adaptive constrast enhancement for radiological imaging
Multiplier-less real-valued FFT-like transformation (ML-RFFT) and related real-valued transformations
CMOS for high-speed nanopore DNA basecalling
Bandpass sampling Rx system design issues and architecture comparison for low power RF standards
The generalized adatron algorithm
VLSI architecture of digital matched filter and prime interleaver for W-CDMA
Selector devices for 3-D cross-point ReRAM
A micro-hotplate-based monolithic CMOS gas sensor array
An improved analog computation cell for Paris II, a programmable vision chip
An efficient 0-1 linear programming for optimal PLA folding
A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
Two-channel microphone array processing for speech enhancement
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop
Sample and hold effect in PWM DC-DC converters with peak current-mode control
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI
High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons
DC-AC: Deep Correlation-Based Adaptive Compression of Feature Map Planes in Convolutional Neural Networks
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing
Statistical properties of a memoryless nonlinear gradient algorithm for an adaptive constrained IIR notch filter
Explicit characterization of bandgap references
A novel technique for low-power D/A conversion based on PAPR reduction
Power and Data Integrity in Monolithic 3D Integrated SIMON Core
A Resonator-optimized 15mW 18-50GHz Quad-core-six-mode VCO with 204dBc/Hz FoMT and 0.058mm 2 Compact Area in 40nm CMOS
Design of a Wireless Multiple-Mode Human Behavior Evaluation System
Design of low-jitter 1-GHz phase-locked loops for digital clock generation
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique
Maximum likelihood parameter estimation of a spiking silicon neuron
Tree-Structure Architecture and VLSI Implementation for Vector Quantization Algorithms
Fast characterization of the noise bounds derived from coefficient and signal quantization
A high-speed single-phase-clocked CMOS priority encoder
A subtle link in switched dynamical systems: saddle-node bifurcation meets border collision
Towards Memristive Deep Learning Systems for Real-Time Mobile Epileptic Seizure Prediction
Design of resistive non-volatile memories for rad-hard applications
A geometrical study on voltage collapse mechanisms of power systems
A Low-Power Predictive Sampling PPG Sensor
MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV
A 900 MHz to 5.2 GHz Dual-loop Feedback Multi-band LNA
Efficient video summarization based on a fuzzy video content representation
Chaos in the Chua's Circuit Double-Hook Attractor
A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector
Towards fast solid state DNA sequencing
A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline
Bilinear transformed switched-current ladder interpolators
A 20-dB CMOS IF amplifier with embedded single-to-differential input converter
Trellis-Based Deconvolution of Ultrasonic Echoes
Live and low energy VVC Video Decoding powered by the OpenVVC Decoder on ARM Platform
Reduced order RLS polynomial predistortion
Lightweight Cryptographic Instruction Set Extension on Xtensa Processor
A New Normalized Minimum-error Entropy Algorithm with Reduced Computational Complexity
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme
Modeling and diagnosis of analog circuits with probabilistic graphical models
Low power datapath design using transformation similar to temporal localization of SFGs
A Multiplying Digital to Analog Converter Insensitive to Component Mismatch
Design and Realization of Analog Phi-Function for LDPC Decoder
A 0.13µm CMOS 1.5-to-2.15GHz low power transmitter front-end for SDR applications
Blind resampling parameter estimation for doubly selective underwater acoustic channels (Invited Paper)
Area, power, and pin efficient bus transceiver using multi-bit-differential signaling
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid
Live Demonstration: Development of LED-Based Stego-Panel for New Smartphone Usage
A convolutional neural network approach for half-pel interpolation in video coding
Simple improvement stage for low voltage WTA and Rank Order circuits
A 0.9 g Battery-Free Wireless Stimulator with Infrared Communication for Applications in Neural Repair and Regeneration
On thermally-induced mechanical stress in high resistivity polysilicon resistors
Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers
An independent bandwidth reduction device for HEVC VLSI video system
Influence of parasitic inductance on serial fixed type switched-capacitor transformer
Super Microscaling: Enhancing Precision and Hardware Efficiency in Deep Learning Quantization
A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem
Efficient loop accelerator for Motion Estimation Specific Instruction-set Processor
Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits
Unconventional computing with diffusive memristors
Digital forensics for printed source identification
A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications
Information and image processing through bio-inspired oscillatory cellular nonlinear networks
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees
Estimation of Unmeasurable Variables in a Dynamical System by Resource Allocating Networks
Algorithms for generation of quaternary fixed polarity arithmetic spectra
Charge redistribution loss consideration in optimal charge pump design