yusuke1997/dblp-id-title huggingface dataset:
PWM-Based Test Stimuli Generation for BIST of High Resolution ADCs
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
STT MRAM-Based PUFs
FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGA
Library-free Structure Recognition for Analog Circuits
Challenges in designing high speed memory subsystem for mobile applications
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
Home Energy Simulation for Non-Intrusive Load Monitoring Applications
ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates
Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics
An ADC-BiST scheme using sequential code analysis
TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction
Efficient inductance extraction via windowing
On-chip communication architecture exploration for processor-pool-based MPSoC
Compositional Memory Systems for Multimedia Communicating Tasks
Co-UP: Comprehensive Core and Uncore Power Management for Latency-Critical Workloads
COTS-based applications in space avionics
Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis
Retraining-based timing error mitigation for hardware neural networks
High-performance imaging subsystems and their integration in mobile devices
A Probabilistic Method for the Computation of Testability of RTL Constructs
Design Automation for Quantum Computing: Intermediate Stage Report of the ERC Consolidator Grant "DAQC"
Smart systems for internet of things
Soft-error classification and impact analysis on real-time operating systems
Implementation-aware design of image-based control with on-line measurable variable-delay
Enabling efficient post-silicon debug by clustering of hardware-assertions
Benefits of asynchronous control for analog electronics: Multiphase buck case study
Integrated Hardware Annealing Based on Langevin Dynamics for Ising Machines
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration
RGHT-Q: Reconfigurable GEMM Unit for Heterogeneous-Homogeneous Tensor Quantization
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes
Workload-aware harmonic partitioned scheduling for probabilistic real-time systems
Adaptive Word Reordering for Low-Power Inter-Chip Communication
Task implementation of synchronous finite state machines
Test Quality and Fault Risk in Digital Filter Datapath BIST
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments
Designing tightly-coupled extension units for the STxP70 processor
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms
On-the-fly layout generation for PTL macrocells
FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning
Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks
Using cubes of non-state variables with property directed reachability
A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC
Analyzing testability from behavioral to RT level
Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection
Adaptive Filesystem Compression for Embedded Systems
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits
Technology Transfer in computing systems: The TETRACOM approach
Performance improvement of multi-processor systems cosimulation based on SW analysis
Compiler-driven error analysis for designing approximate accelerators
Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks
Hardware Accelerated Collision Detection - An Architecture and Simulation Results
Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development
LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks
DeepCAM: A Fully CAM-based Inference Accelerator with Variable Hash Lengths for Energy-efficient Deep Neural Networks
Optimal Transistor Tapering for High-Speed CMOS Circuits
AxPIKE: Instruction-level Injection and Evaluation of Approximate Computing
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write V MIN
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures
Implementation of the ATI flipper chip
Towards a Reliable and Context-Based System Architecture for Autonomous Vehicles
Rewiring for threshold logic circuit minimization
What if you could design tomorrow's system today?
Enabling multi-threaded applications on hybrid shared memory manycore architectures
Illegal State Space Identification for Sequential Circuit Test Generation
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks
Perpetual and low-cost power meter for monitoring residential and industrial appliances
Scandalee: a side-channel-based disassembler using local electromagnetic emanations
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
Bloom filter-based dynamic wear leveling for phase-change RAM
DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed Inference
Optimization for Multiple Patterning Lithography with cutting process and beyond
PATS: Taming Bandwidth Contention between Persistent and Dynamic Memories
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing
Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars
Application Adaptation at Runtime through Dynamic Knobs Autotuning
A GPU -accelerated Deep Stereo- LiDAR Fusion for Real-time High-precision Dense Depth Sensing
2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany
Concurrent focal-plane generation of compressed samples from time-encoded pixel values
SAPPHIRE: an always-on context-aware computer vision system for portable devices
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture
Off-path leakage power aware routing for SRAM-based FPGAs
O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands
Comparative study of test generation methods for simulation accelerators
Power-aware online testing of manycore systems in the dark silicon era
Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio
Cross-Layer Approaches for an Aging-Aware Design Space Exploration for Microprocessors
Partial-SET: Write speedup of PCM main memory
A resilience roadmap
An on-line framework for improving reliability of real-time systems on "big-little" type MPSoCs
ASLAN: Synthesis of approximate sequential circuits
A First Step Towards Hw/Sw Partitioning of UML Specifications
Fault modeling in controllable polarity silicon nanowire circuits
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing
Fast prototyping platform for navigation systems with sensors fusion
PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions
Rescuing memristor-based computing with non-linear resistance levels
On-line scheduling of target sensitive periodic tasks with the gravitational task model
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet
ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks
High quality behavioral verification using statistical stopping criteria
Verifying information flow properties of firmware using symbolic execution
Dynamic Voltage and Cache Reconfiguration for Low Power
DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling
Compositional specification of behavioral semantics
Design and validation of fault-tolerant embedded controllers
Lightspeed Binary Neural Networks using Optical Phase-Change Materials
Device-Aware Diagnosis for Yield Learning in RRAMs
Time-triggered implementations of mixed-criticality automotive software
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
Communication and co-simulation infrastructure for heterogeneous system integration
Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique
Efficient bit error rate estimation for high-speed link by Bayesian model fusion
Multi-token resource sharing for pipelined asynchronous systems
Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex
Applications for ubiquitous computing and communications
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces
Impact of NBTI Aging on Self-Heating in Nanowire FET
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems
Iddq Testing for High Performance CMOS - The Next Ten Years
Efficient SMT-based ATPG for interconnect open defects
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration
The Next Era for Chiplet Innovation
Performance Analysis and Optimizations of Matrix Multiplications on ARMv8 Processors
An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing Constraints
Verification Runtime Analysis: Get the Most Out of Partial Verification
Verifying dynamic aspects of UML models
Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU
A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications
An extremely compact JPEG encoder for adaptive embedded systems
A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing
Sensitivity analysis for arbitrary activation patterns in real-time systems
Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Detecting State Coding Conflicts in STGs Using Integer Programming
BIST hardware generator for mixed test scheme
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors
Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated Circuits
Designing MRF based error correcting circuits for memory elements
An architecture for self-organization in pervasive systems
Simultaneous transistor pairing and placement for CMOS standard cells
Life begins at 65: unless you are mixed signal?
Design of a Reliable Power Delivery Network for Monolithic 3D ICs *
Testbench qualification for SystemC-AMS timed data flow models
Polynomial Methods for Allocating Complex Components
Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience
Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation
Class-based Quantization for Neural Networks
LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND Flash
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications
Stochastic Computing with Integrated Optics
NoC Performance Model for Efficient Network Latency Estimation
Parallel VHDL Simulation
Research and innovation on Advanced Computing - an EU perspective
Reliability-aware thermal management for hard real-time applications on multi-core processors
Reuse of IP and virtual components
Soft Faults and the Importance of Stresses in Memory Testing
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach
Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving
UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents
Programmable decoder and shadow threads: Tolerate remote code injection exploits with diversified redundancy
Ouessant: Flexible integration of dedicated coprocessors in Systems on Chip
An Autonomic Resource Allocating SSD
Model Refinement for Hardware-Software Codesign
Project Overview for Step-Up!CPS - Process, Methods and Technologies for Updating Safety-critical Cyber-physical Systems
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-drones
Root-cause analysis for memory-locked errors
A Machine Learning Based Write Policy for SSD Cache in Cloud Block Storage
Cache aging reduction with improved performance using dynamically re-sizable cache
System Level Online Power Management Algorithms
TTW: A Time-Triggered Wireless design for CPS
Optimized buffer allocation in multicore platforms
Shared last-level cache management for GPGPUs with hybrid main memory
Data mining diagnostics and bug MRIs for HW bug localization
MCM Interconnect Design Using Two-Pole Approximation
Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project
Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse
An antenna-filter codesign for cardiac implants
Behavioral modeling of timing slack variation in digital circuits due to power supply noise
SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching
LSP: Collective Cross-Page Prefetching for NVM
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components
Speeding up SAT for EDA
A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)
An Efficient Persistency and Recovery Mechanism for SGX-style Integrity Tree in Secure NVM
Compiler Support for Reducing Leakage Energy Consumption
Latency criticality aware on-chip communication
MCXplore: An automated framework for validating memory controller designs
Enhancing analog yield optimization for variation-aware circuits sizing
Simple interpolants for linear arithmetic
Analysis and modeling of power grid transmission lines
Quantum Circuit Simplification Using Templates
On linewidth-based yield analysis for nanometer lithography
A fast leakage aware thermal simulator for 3D chips
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI
Efficient synthesis of fault-tolerant controllers
HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration
Tuning the ISA for increased heterogeneous computation in MPSoCs
Towards exascale computing with heterogeneous architectures
A Coprocessor for Accelerating Visual Information Processing
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs
An Efficient Programming Framework for Memristor-based Neuromorphic Computing
Workshop on Autonomous Systems Design, ASD 2019, Florence, Italy, March 29, 2019
GALS networks on chip: a new solution for asynchronous delay-insensitive links
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits
TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration
Fading memory effects in a memristor for Cellular Nanoscale Network applications
Self-Adaptive Ising Machines for Constrained Optimization
Bounding the shared resource load for the performance analysis of multiprocessor systems
Recovery-based resilient latency-insensitive systems
Quantitative timing analysis of UML activity diagrams using statistical model checking
ImpactTracer: Root Cause Localization in Microservices Based on Fault Propagation Modeling
Design-Manufacturing Interface: Part II - Applications
Empowering study of delay bound tightness with simulated annealing
Power-Aware Testing and Test Strategies for Low Power Devices
From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance
Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs
Processing in 3D memories to speed up operations on complex data structures
Abstraction and refinement techniques in automated design debugging
Formal analysis of sporadic bursts in real-time systems
ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers
Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters
Quantitative Evaluation in Embedded System Design: Trends in Modeling and Analysis Techniques
Design automation and design space exploration for quantum computers
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design
Testing DSP Cores Based on Self-Test Programs
Logic Simulation Using Networks of State Machines
Cellular automata for generating deterministic test sequences
Simulation of the steady state of oscillators in the time domain
MATIC: Learning around errors for efficient low-voltage neural network accelerators
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Algorithm to Technology Co-Optimization for CiM-Based Hyperdimensional Computing
Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems
SDCNN: An Efficient Sparse Deconvolutional Neural Network Accelerator on FPGA
Rhychee-FL: Robust and Efficient Hyperdimensional Federated Learning with Homomorphic Encryption
GTN-Cell: Efficient Standard Cell Characterization Using Graph Transformer Network
Online heuristic for the Multi-Objective Generalized traveling salesman problem
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs
Reliability challenges of real-time systems in forthcoming technology nodes
New simulation methodology of 3D surface roughness loss for interconnects modeling
Optimal FPGA module placement with temporal precedence constraints
Efficient code generation for in-house DSP-cores
A novel TSV topology for many-tier 3D power-delivery networks
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications
A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation
InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions
Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks
Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal Imaging
EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications
Challenges in Embedded Memory Design and Test
SheLL: Shrinking eFPGA Fabrics for Logic Locking
A specialized low-cost vectorized loop buffer for embedded processors
A real-time application design methodology for MPSoCs
Reducing the Configuration Overhead of the Distributed Two-level Control System
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
Extended Subspace Identification of Improper Linear Systems
Diagnosing scan chain timing faults through statistical feature analysis of scan images
RiskiM: Toward Complete Kernel Protection with Hardware Support
Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization
Trigonometric method to handle realistic error probabilities in logic circuits
Compiling control-intensive loops for CGRAs with state-based full predication
Early design stage thermal evaluation and mitigation: The locomotiv architectural case
Equivalence verification of arithmetic datapaths with multiple word-length operands
A new quaternary FPGA based on a voltage-mode multi-valued circuit
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices
Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing
Application-Aware Scheduling of Networked Applications over the Low-Power Wireless Bus
Logic synthesis and physical design: Quo vadis?
Composable, parameterizable templates for high-level synthesis
Low-power FinFET circuit synthesis using surface orientation optimization
Using RTL Statespace Information and State Encoding for Induction Based Property Checking
Trustworthy proofs for sensor data using FPGA based physically unclonable functions
Towards improving simulation of analog circuits using model order reduction
Automated Bus Generation for Multiprocessor SoC Design
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain
A lifetime-aware runtime mapping approach for many-core systems in the dark silicon era
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration
ElastiStore: An elastic buffer architecture for Network-on-Chip routers
A symbolic system synthesis approach for hard real-time systems based on coordinated SMT-solving
Methodology for Application-Dependent Degradation Analysis of Memory Timing
Fast cycle estimation methodology for instruction-level emulator
Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters
A Diode-Aware Model of PV Modules from Datasheet Specifications
High-Performance Feature Extraction for GPU -Accelerated ORB-SLAMx
Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis
A Fast Algorithm for the Layout Based Electro-Thermal Simulation
Accurate synthesis of integrated RF passive components using surrogate models
Memristor based computation-in-memory architecture for data-intensive applications
High level CAD melds microsystems with foundries
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
Application-specific memory partitioning for joint energy and lifetime optimization
Compact hardware design of Whirlpool hashing core
CMOS sizing rule for high performance long interconnects
Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems
Optimal Synthesis of Memristive Mixed-Mode Circuits
A New Formulation for SOC Floorplan Area Minimization Problem
OnlineHD: Robust, Efficient, and Single-Pass Online Learning Using Hyperdimensional System
Towards adaptive test of multi-core RF SoCs
RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systems
HARPA: Tackling physically induced performance variability
DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches
Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM
PUF-based secure test wrapper design for cryptographic SoC testing
Anomalies in scheduling control applications and design complexity
Spintronic normally-off heterogeneous system-on-chip design
Design of streaming applications on MPSoCs using abstract clocks
Real-Time Anomalous Branch Behavior Inference with a GPU-inspired Engine for Machine Learning Models