yusuke1997/dblp-id-title huggingface dataset:
Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio Transmitter
Can RF SoCs (Self)test their own RF?
Session 15 overview: Data-converter techniques: Data converters subcommittee
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur
10.7 A 0.26mm 2 DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS
A 0.02mm 2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology
10.6 A 4G/5G Cellular Transmitter in 12nm FinFET with Harmonic Rejection
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS
A Circuit for Reducing Large Transient Current Effects on Processor Power Grids
Session 23 overview: DRAM, MRAM & DRAM interfaces
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor
22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology
A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-Frame-Rate 3D Ultrasound Probes
High-Performance and Small Form-Factor mm-Wave CMOS Radars for Automotive and Industrial Sensing in 76-to-81GHz and 57-to-64GHz Bands
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network
Session 18 overview: High-bandwidth DRAM
Wireless sensor systems: Solution & technology
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
A 0.13µm CMOS SoC for all format blue and red laser DVD front-end digital signal processor
A 0.25mm 2 AC-biased MEMS microphone interface with 58dBA SNR
Signal and power integrity for SoCs
34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell
A 3.3V 6b 100kS/s current-steering D/A converter using organic thin-film transistors on glass
A 34dB SNDR instantaneously-companding baseband SC filter for 802.11a/g WLAN receivers
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s
34.2 1225-Channel Localized Temperature-Regulated Neuromorphic Retinal-Prosthesis SoC with 56.3nW/Channel Image Processor
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor
A Fractional-N Synthesizer with 110fsrms Jitter and a Reference Quadrupler for Wideband 802.11ax
A Micropower Chopper-Stabilized Operational Amplifier using a SC Notch Filter with Synchronous Integration inside the ContinuousTime Signal Path
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs
8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect
A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ΔΣ ADC and hybrid PWM generator
A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm 2 and 6T HBST-TRAM-Based 2D Data-Reuse Architecture
A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner
Session 23 overview: Low-power SoCs: High-performance digital subcommittee
Inverse Designed, Densely Integrated Classical and Quantum Photonics
A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS
6.1 An over 120dB simultaneous-capture wide-dynamic-range 1.6e- ultra-low-reset-noise organic-photoconductive-film CMOS image sensor
An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology
A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesis
A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration
A 0.03mm 2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface
3.7 A 620µW BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190fJ·K 2
28.2 A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End
2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007
A Microsystem for Time-Resolved Fluorescence Analysis using CMOS Single-Photon Avalanche Diodes and Micro-LEDs
A 128 x128 33mW 30frames/s single-chip stereo imager
Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications
A 0.52mJ/Frame 107fps Super-Resolution Processor Exploiting Pseudo-FP6 Sparsity for Mobile Applications
26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS
A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter
29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS
A 0.4V 13b 270kS/S SAR-ISDM ADC with an opamp-less time-domain integrator
10.1 A 1.1W/mm 2 -power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm 2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS
A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology
23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate
20.5 1.4THz, -13dBm-EIRP frequency multiplier chain using symmetric- and asymmetric-CV varactors in 65nm CMOS
A Multi-Band Multi-Mode CMOS DirectConversion DVB-H Tuner
5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology
25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier
A0.81 mm 2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS
30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills
A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL
A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET
A 1V 220MHz-Tuning-Range 2.2GHz VCO Using a BAW Resonator
A 7.2mW quadrature GPS receiver in 0.13µm CMOS
30.4 A 13.56MHz RFID tag with active envelope detection in an organic complementary TFT technology
Subtractive Photonic Waveguide-Coupled Photodetectors in 180nm Bulk CMOS
18.4 A matrix-multiplying ADC implementing a machine-learning classifier directly with data conversion
A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier
A Fully Integrated UWB PHY in 0.13µm CMOS
CMOS Imager Technologies for Biomedical Applications
A Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch with Temperature-compensated Fast Turn-on Technique for Improving Reliability
A Fully Integrated SoC for GSM/GPRS in 0.13µm CMOS
17.5 A 24V Mini-Coil Magnetic Neural Stimulator with Closed-Loop Deadtime Control and ZCS Control Achieving 99.76% Charge Recovery Efficiency
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology
A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes
Resonant clock design for a power-efficient high-volume x86-64 microprocessor
A 16-Core RISC Microprocessor with Network Extensions
17.8 A 170MHz-Lock-In-Range and -253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator
24.2 A 0.1-to-3.1GHz 4-element MIMO receiver array supporting analog/RF arbitrary spatial filtering
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS
24.1 Circuit challenges from cryptography
27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVpp
Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying 2 in 65nm CMOS
A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier
Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS
19.4 A 2.7-to-3.7GHz rapid interférer detector exploiting compressed sampling with a quadrature analog-to-information converter
F4: Mm-Wave advances for active safety and communication systems
A 0.024mm 2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS
A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor
Session 17 overview: Technologies for health and society: Technology directions subcommittee
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS
A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation
21.7 A 6.78MHz 6W wireless power receiver with a 3-level 1× / ½ × / 0× reconfigurable resonant regulating rectifier
19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers
A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management
13.8A 3.3V-supply 120mW differential ADC driver amplifier in 0.18μm SiGe BiCMOS with 108dBc IM3 at 100MHz
1.4 There's More to the Picture Than Meets the Eye*, and in the future it will only become more so
2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulator
22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications
15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory
A 0.28mΩ-sensitivity 105dB-dynamic-range electrochemical impedance spectroscopy soc for electrochemical gas detection
Session 19 overview: Digital PLLs
Dual-antenna phased-array UWB transceiver in 0.18µm CMOS
20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices
A 5.2mW self-configured wearable body sensor network controller and a 12µW 54.9% efficiency wirelessly powered sensor for continuous health monitoring system
19.3 A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique
4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur
Session 8 overview: Low-power digital techniques: Energy-efficient digital
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique
Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellular-Phone Applications
5.3 A 2-channel -83.2dB crosstalk 0.061mm 2 CCIA with an orthogonal frequency chopping technique
Session 15 overview: Innovations in technologies and circuits
25.3 Toward Exponential Growth of Therapeutic Neurotechnology
5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range
Class-G headphone driver in 65nm CMOS technology
A pattern-guided adaptive equalizer in 65nm CMOS
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die
A Compact 10b Source Driver IC with Delta-Sigma Pulse Width Modulation for Low-Voltage Digital Interpolation Achieving 1884μm 2 /Channel
11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power
A 20mw 3.24mm2 fully integrated gps radio for cell-phones
Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads
7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate
A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control
A Per-Pixel Pulse-FM Background Subtraction Circuit with 175ppm Accuracy for Imaging Applications
A 100Mphoton/s time-resolved mini-silicon photomultiplier with on-chip fluorescence lifetime estimation in 0.13μm CMOS imaging technology
26.6 A programmable receiver front-end achieving >17dBm IIP3 at <1.25×BW frequency offset
A multichannel DNA SoC for rapid point-of-care gene detection
A low-power integrated x86-64 and graphics processor for mobile computing devices
Session 17 overview: High-performance DRAM interfaces
Session 27 overview: Image sensors
28.3 A 5.2Mpixel 88.4dB-DR 12in CMOS X-Ray Detector with 16b Column-Parallel Continuous-Time ΔΣ ADCs
Transistor Variability in Nanometer-Scale Technologies (Forum)
A 100μW 64×128-Pixel Contrast-Based Asynchronous Binary Vision Sensor for Wireless Sensor Networks
Session 24 overview: 10GBase-T and optical front ends: Wireline subcommittee
29.5 Sub-THz CMOS Molecular Clock with 43ppt Long-Term Stability Using High-Order Rotational Transition Probing and Slot-Array Couplers
16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC
10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz
A CMOS Single-Chip Electronic Compass with Microcontroller
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS
Session 4 overview: Digital processors
27.4 Physically Unclonable Function in 28nm FD801 Technology Achieving High Reliability for AEC-Q100 Grade 1 and 1SO26262 ASIL-B
34.3 An 8.2mm 3 Implantable Neurostimulator with Magnetoelectric Power and Data Transfer
1.3 Computing in the Era of Generative AI
A 45nm 37.3GOPS/W heterogeneous multi-core SoC
22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS
A 220μW -85dBm Sensitivity BLE-Compliant Wake-up Receiver Achieving -60dB SIR via Single-Die Multi- Channel FBAR-Based Filtering and a 4-Dimentional Wake-Up Signature
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS
A 38.1Mb/mm 2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology
EP1: Moore's law challenges below 10nm: Technology, design and economic implications
29.3 Non-Magnetic 0.18µm SOI Circulator with Multi-Watt Power Handling Based on Switched-Capacitor Clock Boosting
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS
Session 3 overview: Processors
An Outphasing Power Amplifier for a Software-Defined Radio Transmitter
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching
37.8 A 13.5µW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS
Session 16 overview: Innovations in circuits and systems enabled by novel technologies
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing
27.3 A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS
17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme
1.2 Racing Down the Slopes of Moore's Law
Filterless integrated class-D audio amplifier achieving 0.0012% THD+N and 96dB PSRR when supplying 1.2W
10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient response
A 20Gb/s 40mW equalizer in 90nm CMOS technology
A Programmable Wireless EEG Monitoring SoC with Open/Closed-Loop Optogenetic and Electrical Stimulation for Epilepsy Control
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells
A side-channel and fault-attack resistant AES circuit working on duplicated complemented values
2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration
A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
An Asynchronous 160×90 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Background-Light-Adaptive Threshold
A mostly digital variable-rate continuous-time ADC ΔΣ modulator
A Continuously Scalable-Conversion-Ratio SC Converter with Reconfigurable VCF Step for High Efficiency over an Extended VCR Range
1.2 Dynamics of exponentials in circuits and systems
A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier Aggregation
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping
A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE
18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMs DT Zoom PPD ΔΣM with Gain-Embedded Bootstrapped Sampler
28.1 A Capacitive Touch Chipset with 33.9dB Charge-Overflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation and Wireless Power and Data Transfer to an Active Stylus
A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator
A Wireless Dual-Link System for Sensor Network Applications
A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS
An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
A QVGA 143dB dynamic range asynchronous address-event PWM dynamic image sensor with lossless pixel-level video compression
A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology
A 4.1 W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in 28nm Bulk CMOS
Session 14 overview: Digital clocking and PLLs: High-performance digital subcommittee
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C
An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiency
A SAW-less multiband WEDGE receiver
Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond
A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI
A 58mW 1.2mm 2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS
A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMs with Progressive Conversion and Floating-Charge-Transfer Amplifier
7.1 A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme
An Enhanced-Frequency-Splitting-Based Wireless Power and Data Transfer System Achieving 60.2% End-to-End Efficiency and 1 Mb/s Data Rate with a Sub-cm RX Coil for Miniaturized Implants
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD
8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor
A 3.6Mb 10.1Mb/mm 2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V
Session 32 Overview: Frequency Synthesizers Rf Subcommittee
Session 14 overview: Digital PLLs and SoC building blocks: High-performance digital subcommittee
A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter With Greater than 90% Peak Efficiency for the Entire 0.4~1.2V Output Range
A multimedia semantic analysis SoC (SASoC) with machine-learning engine
16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS
25.3 A 65nm Edge-Chasing Quantizer-Based Digital LDO Featuring 4.58ps-FoM and Side-Channel-Attack Resistance
14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data
A 0.13µm CMOS power amplifier with ultra-wide instantaneous bandwidth for imaging applications