yusuke1997/dblp-id-title huggingface dataset:
11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA
SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling
Abstracting Network Characteristics and Locality Properties of Parallel Systems
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators
A Scalable, Non-blocking Approach to Transactional Memory
Programming the cloud
SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution
LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling
Performance Enhancement Techniques for InfiniBand? Architecture
Deadline-Aware Offloading for High-Throughput Accelerators
VVQ: Virtualizing Virtual Channel for Cost-Efficient Protocol Deadlock Avoidance
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces
Reconsidering Complex Branch Predictors
Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory
Automated microprocessor stressmark generation
NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture
Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction
GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks
Routerless Network-on-Chip
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
iCFP: Tolerating all-level cache misses in in-order processors
A Comparison of Entry Consistency and Lazy Release Consistency Implementations
Speeding up the Memory Hierarchy in Flat COMA Multiprocessors
Reducing the cost of persistence for nonvolatile heaps in end user devices
Decoupled dynamic cache segmentation
Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems
Exploitation of Security Vulnerability on Retirement
Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management
Reducing the Communication Overhead of Dynamic Applications on Shared Memory Multiprocessors
WarpDrive: GPU-Based Fully Homomorphic Encryption Acceleration Leveraging Tensor and CUDA Cores
Early Experiences with Saving Energy in Direct Interconnection Networks
Leveraging Domain Information for the Efficient Automated Design of Deep Learning Accelerators
Power Aware Heterogeneous Node Assembly
Overcoming far-end congestion in large-scale networks
Architectural Issues in Java Runtime Systems
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform
Improving GPGPU resource utilization through alternative thread block scheduling
Multicast on Irregular Switch-Based Networks with Wormhole Routing
Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects
Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs
Protected, User-Level DMA for the SHRIMP Network Interface
Dynamic Data Replication: An Approach to Providing Fault-Tolerant Shared Memory Clusters
Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations
Temporal-Based Procedure Reordering for Improved Instruction Cache Performance
Zebra: Efficient Redundant Array of Zoned Namespace SSDs Enabled by Zone Random Write Area (ZRWA)
Mitigating GPU Core Partitioning Performance Effects
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems
Usas: A Sustainable Continuous-Learning' Framework for Edge Servers
Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime
Memory Hierarchy for Web Search
Elastic Instruction Fetching
Multiple Branch and Block Prediction
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files
PruneGNN: Algorithm-Architecture Pruning Framework for Graph Neural Network Acceleration
Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism
Deep Learning Acceleration with Neuron-to-Memory Transformation
FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators
25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, Washington, DC, USA, February 16-20, 2019
A Scalable Cache Coherent Scheme Exploiting Wormhole Routing Networks
FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction
Modeling cache performance beyond LRU
Improving Performance by Cache Driven Memory Management
WildFire: A Scalable Path for SMPs
Balancing DRAM locality and parallelism in shared memory CMP systems
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures
20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014
Lightweight predication support for out of order processors
Power balanced pipelines
Are Randomized Caches Truly Random? Formal Analysis of Randomized-Partitioned Caches
ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM
LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs
SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures
Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee
DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency
InstAttention: In-Storage Attention Offloading for Cost-Effective Long-Context LLM Inference
Searching for Potential gRNA Off-Target Sites for CRISPR/Cas9 Using Automata Processing Across Different Platforms
RpcNIC: Enabling Efficient Datacenter RPC Offloading on PCIe-attached SmartNICs
KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores
AutoRFM: Scaling Low-Cost in-DRAM Trackers to Ultra-Low Rowhammer Thresholds
Enhancing Server Efficiency in the Face of Killer Microseconds
POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities
RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases
SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers
Adaptive Reliability Chipkill Correct (ARCC)
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
Control Speculation in Multithreaded Processors through Dynamic Loop Detection
Software-Managed Address Translation
SNNAP: Approximate computing on programmable SoCs via neural acceleration
Two Adaptive Hybrid Cache Coherency Protocols
Efficient Distributed Secure Memory with Migratable Merkle Tree
FLOWER and FaME: A Low Overhead Bit-Level Fault-map and Fault-Tolerance Approach for Deeply Scaled Memories
Supporting Address Translation for Accelerator-Centric Architectures
MERCURY: Accelerating DNN Training By Exploiting Input Similarity
Remote GPU Virtualization: Is It Useful?
Adyna: Accelerating Dynamic Neural Networks with Adaptive Scheduling
Application Performance Impact on Trimming of a Full Fat Tree InfiniBand Fabric
Filesystem Encryption or Direct-Access for NVM Filesystems? Let's Have Both!
Overcoming the challenges of crossbar resistive memory architectures
NOMAD: Enabling Non-blocking OS-managed DRAM Cache via Tag-Data Decoupling
Architectural Support for Task Dependence Management with Flexible Software Scheduling
CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM
Self-Tuned Congestion Control for Multiprocessor Networks
13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA
Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management
GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerators
Amdahl's law for lifetime reliability scaling in heterogeneous multicore processors
Exploiting Prediction to Reduce Power on Buses
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001
Fast Barrier Synchronization in Wormhole k-ary n-cube Networks with Multidestination Worms
Roughness of microarchitectural design topologies and its implications for optimization
Fast thread migration via cache working set prediction
Performance Study of a Multithreaded Superscalar Microprocessor
Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA
Modeling performance variation due to cache sharing
Voltage emergency prediction: Using signatures to reduce operating margins
Active-Routing: Compute on the Way for Near-Data Processing
Approximating warps with intra-warp operand value similarity
QULATIS: A Quantum Error Correction Methodology toward Lattice Surgery
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques
Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis
CMP network-on-chip overlaid with multi-band RF-interconnect
Concord: Rethinking Distributed Coherence for Software Caches in Serverless Environments
S2TA: Exploiting Structured Sparsity for Energy-Efficient Mobile CNN Acceleration
Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency
Recycling Data Slack in Out-of-Order Cores
Optimizing Google's warehouse scale computers: The NUMA experience
Transparent and Efficient CFI Enforcement with Intel Processor Trace
Modified LRU Policies for Improving Second-Level Cache Behavior
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors
Breaking the on-chip latency barrier using SMART
Reducing Branch Misprediction Penalty via Selective Branch Recovery
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery
A Hybrid Systolic-Dataflow Architecture for Inductive Matrix Algorithms
HeatViT: Hardware-Efficient Adaptive Token Pruning for Vision Transformers
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
Colorama: Architectural Support for Data-Centric Synchronization
ATM and Fast Ethernet Network Interfaces for User-Level Communication
Interval simulation: Raising the level of abstraction in architectural simulation
Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking
A group-commit mechanism for ROB-based processors implementing the X86 ISA
GSSA: A Resource Allocation Scheme Customized for 3D NAND SSDs
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Combining OpenFabrics Software and Simulation Tools for Modeling InfiniBand-Based Interconnection Networks
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
Calvin: Deterministic or not? Free will to choose
QuCloud: A New Qubit Mapping Mechanism for Multi-programming Quantum Computing in Cloud Environment
Rapper: A Parameter-Aware Repair-in-Memory Accelerator for Blockchain Storage Platform
Probabilistic counter updates for predictor hysteresis and stratification
Impact of Heterogeneity on DSM Performance
Interactions Between Compression and Prefetching in Chip Multiprocessors
Architecture exploration for ambient energy harvesting nonvolatile processors
Efficient Caching with A Tag-enhanced DRAM
Flexible register management using reference counting
Dynamically heterogeneous cores through 3D resource pooling
The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing
Achieving uniform performance and maximizing throughput in the presence of heterogeneity
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
ESD: An ECC-assisted and Selective Deduplication for Encrypted Non-Volatile Main Memory
Improving GPU Multi-tenancy with Page Walk Stealing
ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging
QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers
Uncovering hidden loop level parallelism in sequential applications
Low-Complexity Distributed Issue Queue
Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence
Dynamic Prediction of Critical Path Instructions
Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling
On the Performance of Hand vs. Automatically Optimized Numerical Codes
VAQEM: A Variational Approach to Quantum Error Mitigation
On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects
Amdahl's Law in the Datacenter Era: A Market for Fair Processor Allocation
Distributing the Frontend for Temperature Reduction
Improving the Throughput of Synchronization by Insertion of Delays
VR-Pipe: Streamlining Hardware Graphics Pipeline for Volume Rendering
Software DSM Protocols that Adapt between Single Writer and Multiple Writer
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture
LightTrader: A Standalone High-Frequency Trading System with Deep Learning Inference Accelerators and Proactive Scheduler
Q-GPU: A Recipe of Optimizations for Quantum Circuit Simulation Using GPUs
A first-order fine-grained multithreaded throughput model
CoopMC: Algorithm-Architecture Co-Optimization for Markov Chain Monte Carlo Accelerators
Are Coherence Protocol States Vulnerable to Information Leakage?
MOPED: Efficient Motion Planning Engine with Flexible Dimension Support
TILT: Achieving Higher Fidelity on a Trapped-Ion Linear-Tape Quantum Computing Architecture
A comprehensive approach to DRAM power management
Bridging the computation gap between programmable processors and hardwired accelerators
R.I.P. Geomean Speedup Use Equal-Work (Or Equal-Time) Harmonic Mean Speedup Instead
Architecting Value Prediction around In-Order Execution
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM
Data-triggered threads: Eliminating redundant computation
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
MGC: Multiple-Gray-Code for 3D NAND Flash based High-Density SSDs
UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs
Memory Access Reordering in Vector Processors
COMIC++: A software SVM system for heterogeneous multicore accelerator clusters
High performance network virtualization with SR-IOV
ECM: Effective Capacity Maximizer for high-performance compressed caching
Exploring the VLSI Scalability of Stream Processors
DRAM Energy Management Using Software and Hardware Directed Power Mode Control
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices
Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers
Architectural Support for Inter-Stream Communication in a MSIMD System
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
SIF: Overcoming the limitations of SIMD devices via implicit permutation
Virtual-Physical Registers
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
EMSim: A Microarchitecture-Level Simulation Tool for Modeling Electromagnetic Side-Channel Signals
FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications
Home-Based SVM Protocols for SMP Clusters: Design and Performance
ACIC: Admission-Controlled Instruction Cache
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
An Effective Queuing Scheme to Provide Slim Fly Topologies with HoL Blocking Reduction and Deadlock Freedom for Minimal-Path Routing
CAMEL: Co-Designing AI Models and eDRAMs for Efficient On-Device Learning
FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy
PVCoherence: Designing flat coherence protocols for scalable verification
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family
Datapath Design for a VLIW Video Signal Processor
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
Criticality-Aware Instruction-Centric Bandwidth Partitioning for Data Center Applications
Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound
SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction
Signature Buffer: Bridging Performance Gap between Registers and Caches
GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support
AVGI: Microarchitecture-Driven, Fast and Accurate Vulnerability Assessment
Two level bulk preload branch prediction
FACIL: Flexible DRAM Address Mapping for SoC-PIM Cooperative On-device LLM Inference
Malware-aware processors: A framework for efficient online malware detection
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir Computing
Exploring Wakeup-Free Instruction Scheduling
15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA
Efficient Supernet Training Using Path Parallelism
DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance
Core tunneling: Variation-aware voltage noise mitigation in GPUs
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture
Warp Scheduling for Fine-Grained Synchronization
Mithril: A Scalable System for Deep GNN Training
Enterprise IT Trends and Implications for Architecture Research
MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets
Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks
Fine-Grain Multi-Thread Processor Architecture for Massively Parallel Processing
DMA++: on the fly data realignment for on-chip memories
Chasing Carbon: The Elusive Environmental Footprint of Computing
KRISP: Enabling Kernel-wise RIght-sizing for Spatial Partitioned GPU Inference Servers
A Study of Control Independence in Superscalar Processors
Software Cache Coherence for Large Scale Multiprocessors
System-level implications of disaggregated memory
The runahead network-on-chip
The Architectural Costs of Streaming I/O: A Comparison of Workstations, Clusters, and SMPs
A VLSI Architecture for Computer the Tree-to-Tree Distance
System level analysis of fast, per-core DVFS using on-chip switching regulators
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models
Deterministic Clock Gating for Microprocessor Power Reduction
Performance Study of a Concurrent Multithreaded Processor
Understanding the virtualization "Tax" of scale-out pass-through GPUs in GaaS clouds: An empirical study
A new server I/O architecture for high speed networks
iPAWS: Instruction-issue pattern-based adaptive warp scheduling for GPGPUs
Understanding the impact of gate-level physical reliability effects on whole program execution
Distributed Modulo Scheduling
Exploiting criticality to reduce bottlenecks in distributed uniprocessors
Turbo: SmartNIC-enabled Dynamic Load Balancing of µs-scale RPCs
Performance Characterization of the Pentium(r) Pro Processor
Missing the Forest for the Trees: End-to-End AI Application Performance in Edge Data Centers
Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors
TCP: Tag Correlating Prefetchers
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning
Scalable communication architecture for network-attached accelerators
Soft error vulnerability aware process variation mitigation
Loose Loops Sink Chips
Adaptive Memory Fusion: Towards Transparent, Agile Integration of Persistent Memory
Delinquent Loop Pre-execution Using Predicated Helper Threads
High-performance and energy-efficient mobile web browsing on big/little systems
TidalMesh: Topology-Driven AllReduce Collective Communication for Mesh Topology
BulkSMT: Designing SMT processors for atomic-block execution
Hardware-Based Address-Centric Acceleration of Key-Value Store
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Industrial perspectives panel
Understanding GPU errors on large-scale HPC systems and the implications for system design and operation
Navigating heterogeneous processors with market mechanisms
SCRAP: Architecture for signature-based protection from Code Reuse Attacks
PIMCloud: QoS-Aware Resource Management of Latency-Critical Applications in Clouds with Processing-in-Memory
Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors
The Impact of Link Arbitration on Switch Performance
Graphite: A distributed parallel simulator for multicores
12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006
LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs
The Soft Error Problem: An Architectural Perspective
Hydra: Scale-out FHE Accelerator Architecture for Secure Deep Learning on FPGA
Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre Attacks
CiDRA: A cache-inspired DRAM resilience architecture
Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks
High performance file I/O for the Blue Gene/L supercomputer
Understanding and Optimizing Power Consumption in Memory Networks
HRL: Efficient and flexible reconfigurable logic for near-data processing
EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing
MEGA: A Memory-Efficient GNN Accelerator Exploiting Degree-Aware Mixed-Precision Quantization
Celeritas: Out-of-Core Based Unsupervised Graph Neural Network via Cross-Layer Computing 2024
DIMM-Link: Enabling Efficient Inter-DIMM Communication for Near-Memory Processing
On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems
Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA
Accurate microarchitecture-level fault modeling for studying hardware faults