yusuke1997/dblp-id-title huggingface dataset:
FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT
An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis
An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
A Runtime Environment for Reconfigurable Hardware Operating Systems
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
High-level programming of coarse-grained reconfigurable architectures
Continuous Interconnect Provides Solution to Density/Performance Trade-Off in Programmable Logic
Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis
Hardware implementation of MRF map inference on an FPGA platform
Towards domain-specific Instruction-Set Generation
FPGA Routing Structures from Real Circuits
Compact dual block AES core on FPGA for CCM Protocol
Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC
TransPar: Transformation based dynamic Parallelism for low power CGRAs
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression
Overcoming resource underutilization in spatial CNN accelerators
FPGA-Based Hardware/Software CoDesign of an Expert System Shell
Polymorphic wavelet architectures using reconfigurable hardware
Approximate Frequent Itemset Mining for streaming data on FPGA
SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions
Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams
FPGA Technology Mapping for Power Minimization
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis
An Evolvable Hardware Tutorial
A Dynamic NoC Approach for Communication in Reconfigurable Devices
Pipelined reconfigurable multiplication with constants on FPGAs
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA
Model-based optimization of High Level Synthesis directives
Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications
Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms
FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
Implementing Sigma Delta Modulator Prototype Designs on an FPGA
Hardware Implementation Techniques for Recursive Calls and Loops
Bitwise Optimised CAM for Network Intrusion Detection Systems
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural Topologies
Enhanced gradient-based motion vector coprocessor
Evaluation Strategies for Coarse Grained Reconfigurable Architectures
Implementation and outcomes of FPGA-based system design in Mongolian education
FPGA Implementation of a Rational Adder
Prototyping for the Concurrent Development
Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures
Optimizing Deep Learning Decoders for FPGA Implementation
Next Generation Architectures and CAD for Power Aware Programmable Fabrics
Serial Hardware Libraries for Reconfigurable Designs
Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system
Secure Configuration of Field Programmable Gate Arrays
Coarse-grained reconfiguration
Improving Pipelined Soft Processors with Multithreading
Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping
Fast On-line Task Placement and Scheduling on Reconfigurable Devices
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS
A highly scalable Restricted Boltzmann Machine FPGA implementation
ADAS and Video Surveillance Analytics System Using Deep Learning Algorithms on FPGA
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs
A Compilation Framework for a Dynamically Reconfigurable Architecture
MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks
Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot
Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space
A self-adaptive image processing application based on evolvable and scalable hardware
HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem
Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis
Distributed embedded systems design using Petri nets
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems
Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs
PGR: A Software Package for Reconfigurable Super-Computing
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System
FPGA Design of A H.264/AVC Main Profile Decoder for HDTV
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs
Integrated Iterative Approach to FPGA Placement
A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic
A pythonic approach for rapid hardware prototyping and instrumentation
Automatic support for multi-module parallelism from computational patterns
Challenges and Opportunities for FPGA Platforms
Analytical placement for heterogeneous FPGAs
Better Together: Combining Analytical and Annealing Methods for FPGA Placement
Deep-pipelined FPGA implementation of ellipse estimation for eye tracking
An NTSC and PAL closed caption processor
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes
Hardware implementation of MPI_Barrier on an FPGA cluster
A Laboratory for a Digital Design Course Using FPGAs
Token-based dictionary pattern matching for text analytics
A Job Dispatcher-Collector Made of FPGAs for a Centralized Voice server
Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
Bubble Partitioning for LUT-Based Sequential Circuits
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs
Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs
Using Novel Configuration Techniques for Accelerated FPGA Aging
Power Wasting Circuits for Cloud FPGA Attacks
Energy-Efficient Matrix Multiplication on FPGAs
OpenCL computing on FPGA using multiported shared memory
FPGA Based Engines for Genetic and Memetic Algorithms
Technology mapping of LUT based FPGAs for delay optimisation
SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems
Implementation and Performance Evaluation of an Image Pre-Processing Chain on FPGA
Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
Signature Testability of PLA
A VHDL Design Methodology for FPGAs
IOPT-tools - A Web based tool framework for embedded systems controller development using Petri nets
GraphScale: Scalable Bandwidth-Efficient Graph Processing on FPGAs
FPL Demo: FPGA Bitstream Virus Scanning
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures
Trident: An FPGA Compiler Framework for Floating-Point Algorithms
Transparent FPGA flow
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA
FPGA Viruses
Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory
FPGA: The future platform for transforming, transporting and computing data
Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices
SoftSONIC: A Customisable Modular Platform for Video Applications
FPGA interconnect sizing using extended logical effort model
Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology
Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes
FPGA Interconnect Architecture Exploration Based on a Statistical Model
Molecular Docking on FPGA and GPU Platforms
Artificial Neural Network Implementation on a Fine-Grained FPGA
Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems
Using Consensusless Covers for Fast Operating on Boolean Functions
Comparing soft and hard vector processing in FPGA-based embedded systems
High Speed / Low Power Architectures for the Finite Radon Transform
Adaptive FPGAs: High-Level Architecture and a Synthesis Method
PushPush: Seamless integration of hardware and software objects via function calls over AXI
Real-Time Classification of Multimedia Traffic Using FPGA
Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems
FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences
CAD-oriented FPGA and dedicated CAD system for telecommunications
A Dynamically Reconfigurable Bluetooth Base Band Unit
Data coding functions for Software Defined Radios implemented on R3TOS
Accelerating Random Forest training process using FPGA
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic
System#: High-level synthesis of physical simulations for FPGA-based real-time execution
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture
A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices
Performance evaluation of Sparse Matrix-Matrix Multiplication
A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware
Floating point datapath synthesis for FPGAs
HyperLogLog Sketch Acceleration on FPGA
Network Intrusion Detection Using Neural Networks on FPGA SoCs
Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities
Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation
MAPC: Memory access pattern based controller
Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices
Dynamic Voltage Scaling in a FPGA-based System-on-Chip
The Age of Adaptive Computing Is Here
FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach
Hashing + Memory = Low Cost, Exact Pattern Matching
On-The-Fly Parallel Data Shuffling for Graph Processing on OpenCL-Based FPGAs
FPGA-based implementation and comparison of recursive and iterative algorithms
A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs
Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms
SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors
Rapid estimation of power consumption for hybrid FPGAs
Trends of CPU, GPU and FPGA for high-performance computing
Compiler assisted runtime task scheduling on a reconfigurable computer
Logic Circuit Speeding up through Multiplexing
RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC
Minimal Overhead Optical Time-Domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmable Voltage Offset
A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)
Extending BORPH for shared memory reconfigurable computers
SoPC architecture for a Key Point Detector
Implementation of pipelined multipliers on Xilinx FPGAs
Use of Reconfigurability in Variable-Length Code Detection at Video Rates
DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs
A high-performance IPV6 lookup engine on FPGA
Real-Time Video Pixel Matching
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project
Requested-QoS Driven Runtime Reconfiguration of Mobile Devices
Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time
An Open-Source Framework for Efficient Numerically-Tailored Computations
Multidimensional Dynamic Programming for Homology Search
Reliable SEU monitoring and recovery using a programmable configuration controller
Reconfigurable circuit for implementation of family of 4-phase latch protocols
Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs
Adaptive Optics Real-Time Control Using FPGA
Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems
Design of a Fault Tolerant FPGA
Data parallel FPGA workloads: Software versus hardware
An Application-Specific Field-Programmable Tree Ensemble Architecture
Dense FPGA Compute Using Signed Byte Tuples
On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware
A FPGA design for high speed feature extraction from a compressed measurement stream
Efficient Realtime FPGA Implementation of the Trace Transform
Soft IP core implementation of recursive least squares filter using only multplicative and additive operators
Hierarchical library based power estimator for versatile FPGAs
RAID 6 Hardware Acceleration
FPGA-Based Prototyping for Product Definition
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks
On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults
Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study
An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs
Decision tree based hardware power monitoring for run time dynamic power management in FPGA
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips
Generating infrastructure for FPGA-accelerated applications
Multifunctional Programmable Single-Board CAN Monitoring Module
A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays
Optimising designs by combining model-based and pattern-based transformations
Novel Multi-Layer floorplanning for Heterogeneous FPGAs
Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
A reconfigurable FIR/FFT unit for wireless telecommunication systems
Configurable Hardware Architecture for Real-Time Window-Based Image Processing
Self-Aware Adaptation in FPGA-based Systems
Reconfigurable Hardware from Programmable Logic Devices
C++ based design flow for reconfigurable image processing systems
Mems optically reconfigurable gate array
Embedded Reconfigurable Logic Core for DSP Applications
Towards a many-core architecture for HPC
An FPGA Based SHA-256 Processor
Real-Time Feature Extraction for High Speed Networks
Energy optimization of FPGA-based stream-oriented computing with power gating
Run-time parameterised circuits for the Xilinx XC6200
A Dynamic Reconfigurable Fabric for Platform SoCs
Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution
Methods and Tools for High-Resolution Imaging
A Time-Triggered Network-on-Chip
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure
A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm
Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption
A Deep-Learning Framework for Predicting Congestion During FPGA Placement
A TCP/IP Based Multi-device Programming Circuit
Ultra Low Latency Machine Learning for Scientific Edge Applications
Exploration of ring oscillator design space for temperature measurements on FPGAs
Design Space Exploration for Distributed Hardware Reconfigurable Systems
An LZ77-style bit-level compression for trace data compaction
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs
Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction
A reconfigurable architecture for the Phylogenetic Likelihood Function
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks
Secret Sharing MPC on FPGAs in the Datacenter
Evaluating the Hardware Cost of the Posit Number System
Post-Placement BDD-Based Decomposition for FPGAs
AdaBoost Engine
SVM speaker verification system based on a low-cost FPGA
An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors
A resource optimized SoC Kit for FPGAs
Efficient Cell Designs for Systolic Smith-Waterman Implementations
A fast and high quality stereo matching algorithm on FPGA
ReconOS: An RTOS supporting Hard- and Software Threads
2D and 3D Computer Graphics Algorithms under MORPHOSYS
OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors
Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor
Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs
An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique
Reconfigurable Computer Array: The Bridge between High Speed Sensors and Low Speed Computing
Multi-layer Floorplanning on a Sequence of Reconfigurable Designs
Assessing the Effectiveness of Active Fences Against SCAs for Multi-Tenant FPGAs
FPGA Implementation and Power Modelling of the Fast Walsh Transform
Run-Time Optimized Reconfiguration Using Instruction Forecasting
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
Accelerating Microblaze Floating Point Operations
Revealing Untapped DSP Optimization Potentials for FPGA-Based Systolic Matrix Engines
Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing
Accelerating Physics Engine Components with Embedded FPGAs
SAT-based resource binding for reducing critical path delays
Performance Penalty for Fault Tolerance in Roving STARs
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links
Vivado design interface: An export/import capability for Vivado FPGA designs
Area-optimized montgomery multiplication on IGLOO 2 FPGAs
Exploring FPGA Acceleration for Distributed Serverless Computing
Implementation of a NURBS to Bézier Conversor with Constant Latency
A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAs
HPC-gSpan: An FPGA-based parallel system for frequent subgraph mining
SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor
An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs
Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs
Fast Prototyping Using System Emulators
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
Boosting convergence of timing closure using feature selection in a Learning-driven approach
Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device
Bio-inspired walking: A FPGA multicore system for a legged robot
A Self-reconfiguring Platform
High-level aging estimation for FPGA-mapped designs
A Dual-V DD Low Power FPGA Architecture
Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory
Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits
Ultra-fast NoC emulation on a single FPGA
An open-source multi-FPGA modular system for fair benchmarking of True Random Number Generators
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices
The CSYN Verilog Compiler and Other Tools
A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support
Creating unique identifiers on field programmable gate arrays using natural processing variations
Design and Implementation of the Memory Scheduler for the PC-Based Router
A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool
Astra: An Advanced Space-Time Reconfigurable Architecture
Design and FPGA implementation of a 100 Gbit/s optical transport network processor
Influence of operating conditions on ring oscillator-based entropy sources in FPGAs
Fast and accurate SEU-tolerance characterization method for Zynq SoCs
A novel states recovery technique for the TMR softcore processor
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis
Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs
Architecture-Adaptive Routability-Driven Placement for FPGAs
PulseDSP - A Signal Processing Oriented Programmable Architecture
Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor
An FPGA Implementation of a Multi-comparand Multi-search Associative Processor
Neural Network Overlay Using FPGA DSP Blocks
Implementing Converters in FPLD
A high-performance overlay architecture for pipelined execution of data flow graphs
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring
Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs
Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip
Java Technology in an FPGA
FPGASwarm: High Throughput Model Checking on FPGAs
SL - A Structural Hardware Design Language
Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs
Reconfigurable Computing in Remote and Harsh Environments
Memory Access Schemes for Configurable Processors
An area-efficient alternative to adaptive median filtering in FPGAs
Validating optimisations for chaotic simulations
Accelerating Image Analysis for Localization Microscopy with FPGAs
Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System
Reducing FPGA Router Run-Time through Algorithm and Architecture
Bringing High-Performance Reconfigurable Computing to Exact Computations
SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs
A Flexible K-Means Operator for Hybrid Databases
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures
On some Limits of XILINX Based Control Logic Implementations
An Integrated Online Scheduling and Placement Methodology
Accelerating maximum likelihood estimation for Hawkes point processes
Accelerating Database Systems Using FPGAs: A Survey
FPGA-accelerated retinal vessel-tree extraction
Run-Time Reconfiguration Management for Adaptive High-Performance Computing Systems
Methods for implementation of feedback loops in high speed FPGA applications
A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow
Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020
On the automatic integration of hardware accelerators into FPGA-based embedded systems
Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs