yusuke1997/dblp-id-title huggingface dataset:
Voltage-based wideband measurement of transmission characteristics using an integrated receiver IC
Papoulis-Gerchberg Hybrid Filter Bank receiver for cognitive-/Software-Defined Radio systems
A new motion compensation design for H.264/AVC decoder
Exploring Possibilities of BFV-based Homomorphic Encryption for Privacy-Preserving Image Processing
A CMOS impulse generator for UWB wireless communication systems
Power-saving nano-scale DRAMs with an adaptive refreshing clock generator
A Reliable Physical Unclonable Function Based on Differential Charging Capacitors
Evidence of the lateral collection significance in small CMOS photodiodes
Efficiency Model of Fully-Integrated Boost DC-DC Converters
Non-Ideal Effects of Memristor-CMOS Hybrid Circuits for Realizing Multiple-Layer Neural Networks
Hardware Implementation of a Smart Camera with Keypoint Detection and Description
Instantaneously companding baseband SC low-pass filter and ADC for 802.1 la/g WLAN receiver
Improving energy efficiency of functional units by exploiting their data-dependent latency
Study of subjective and objective quality assessment of retargeted images
Design and simulation of miniaturized communication systems employing symmetrical lossless two-ports constructed with two kinds of elements
Identification and Control of Chaotic Systems: An Artificial Neural Network Approach
On the design of IIR bandpass filters with an adjustable bandwidth and centre frequency
A 0.5V fully differential OTA with local common feedback
Simple design equations of gain compression and distortion spectrum in broadband RF transceivers
A Low-Power and Area-Efficient 14-bit SAR ADC with Hybrid CDAC for Array Sensors
Error Correction Algorithm for Folding/Interpolation ADC
DAC compensation for continuous-time delta-sigma modulators
Low cost floating-point unit design for audio applications
Switched-current ΣΔ modulator for baseband channel applications
The design of high-performance 128×128 CMOS image sensors using new current-readout techniques
A joint block diagonalization approach to convolutive blind source separation
Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven technique
Combinational circuit fault diagnosis using logic emulation
Transceiver circuits for pulse-based ultra-wideband
Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs
Channel coding for H.264 video in constant bit rate transmission context over 3G mobile systems
A hierarchical fast encoding algorithm for vector quantization with PSNR equivalent to full search
Live Demonstration: A Reconfigurable, Energy-efficient and High-frame-rate EKF-SLAM Accelerator Based SoC Design for Autonomous Mobile Robot Applications
Uplink Power Control Approach Based on Adaptive Chaotic Simulated Annealing
A New BiCMOS Low-Voltage and Low-Distortion OTA for Continuous-Time Filters
Improved logarithmic converter based on a transconductance feedback amplifier
An Efficient Coding Method for Intra Prediction Mode Information
AER tools for communications and debugging
Low cost mobile EEG for characterization of cortical auditory responses
Experimental Demonstration of Dual Camera Receivers in M-PAM Rolling Shutter Based Visible Light Communication
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors
An Exhaustive Search Algorithm for Checking Limit Cycle Behavior of Digital Filters
Self-timed MOS current mode logic for digital applications
Detecting Phishing Scams on Ethereum Based on Transaction Records
Noise-mediated cooperative behavior in a system of coupled DC SQUIDs
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
A CAD simulator based on loop gain measurement for switching converters
Design of encoders for linear-coded D/A converters
Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter
Analysis of Bilinear Digital Ladder Filters
Tongue drive: a tongue operated magnetic sensor based wireless assistive technology for people with severe disabilities
Class-D Audio Amplifiers in Mobile Applications
Convolutional Neural Network-Based Motion Compensation Refinement for Video Coding
An adaptive offset cancellation mixer for direct conversion receivers in 2.4 GHz CMOS
A new visual cryptography using natural images
A comparison of various low-pass filter architectures for sigma-delta demodulators
A DC-DC Converter using a high speed soft-start control circuit
Floorplanning driven Network-on-Chip synthesis for 3-D SoCs
Board-level prototype validation: a built-in controller and extended BST architecture
A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters
Resource allocation for audio and video streaming over the Internet
A 40 Gb/s transimpedance amplifier in 65 nm CMOS
Modelling differential pairs for low-distortion amplifier design
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks
A scalable pipelined complex valued matrix inversion architecture
Experimental Characterisation of Drift on ISFET Arrays and its pH Dependence
Neural network training using ant algorithm in ATM traffic control
Constraint Generation & Placement for Automatic Layout Design of Analog Integrated Circuits
Estimating the locking range of analog dividers through a phase-domain macromodel
A Robust Quasi-Newton Adaptive Filtering Algorithm
Optimal adaptive parallel diagnosis for arrays
A Method for Identifying Combinations of Transistors that can be Replaced with a Single Transistor when Applying the Nielsen-Willson Theorem
Efficient architecture for FPGA-based microcontrollers
A Reconfigurable Passive Voltage Multiplier for Wireless Mobile IoT Applications
A novel approach for automated model generation
Bidirectional Independently Recurrent Neural Network for Skeleton-Based Hand Gesture Recognition
Arithmetic module generator with algorithm optimization capability
Application of probabilistic Tabu Search to distribution system service restoration
Deep CNNs for microscopic image classification by exploiting transfer learning and feature concatenation
RO PUF design in FPGAs with new comparison strategies
A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters
5-GHz SiGe linearity power amplifier using integrated feedforward architecture for WLAN applications
A Low Complexity Real-valued Kernel DHT-based OFDM Modulator/Demodulator Design
Improving the Precision of SORN Arithmetic by Introducing Fused Operations
High-speed FPGA-implementation of multidimensional binary morphological operations
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p)
Precision-Factored Systolic Arrays: Balancing Accuracy and Efficiency in Floating-Point Computations for CNNs
A Low-Distortion Power-Efficient Feedforward Technique for DT Delta-Sigma ADCs
The left edge algorithm in block test scheduling under power constraints
PWL approximation of dynamical systems: an example
A new robust Kalman filter algorithm under outliers and system uncertainties
A 5.9μW Ultra-Low-Power Dual-Resolution CIS Chip of Sensing-with-Computing for Always-on Intelligent Visual Devices
Stego-signature at logic synthesis level for digital design IP protection
ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge
An ROI image coding based on switching wavelet transform
A Fold-back Current-limit Circuit with Load-insensitive Quiescent Current for CMOS Low Dropout Regulator
FPGA-based 3D median filtering using word-parallel systolic arrays
A configurable multi-band GNSS receiver for Compass/GPS/Galileo applications
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process
A Current-Mode Temperature Sensor with a ±1.56 °C Raw Error and Duty-Cycle Output in 16nm FinFET
A 110dB dynamic range continuous-time IF-to-baseband Sigma Delta modulator for AM/FM/IBOC receivers
Design of an Area-Efficient Differential Distributed Amplifier Based on the Theory of Differential Transmission Lines
A 75.3 pJ/b Ultra-Low Power MEMS-Based FSK Transmitter in ISM-915 MHz Band for Pico-IoT Applications
Design of Bilinear Digital Ladder Filters
A Convolutional Neural Network Based Calibration Scheme for Pipelined ADC
A Comprehensive Parasitic Component Model for Spiral Air-core Coils in MHz Load-Independent Single-input Multiple-output Wireless Power Transfer System
Nonlinear dynamics of first-order DPLL with FM input
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity
Adaptive combined bispectrum-filtering signal processing in radar systems with low SNR
Knowledge Graph Embedding and Visualization for Pre-Silicon Detection of Hardware Trojans
Interconnect model reductions by using the AORA algorithm with considering the adjoint network
A Low Power UWB-LNA using Active Dual Loop Negative Feedback in CMOS 0.13µm
Glitching power reduction through supply voltage adaptation mechanism for low power array structure design
Evolution Strategy and Controlled Residual Convolutional Neural Networks for ADC Calibration in the Absence of Ground Truth
Two-electrode impedance-sensing cardiac rhythm monitor for charge-aware shock delivery in cardiac arrest
Stability study of the TCP-RED system using detrended fluctuation analysis
Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination
SIFT-based image super-resolution
Quality-progressive coding for high bit-rate background frames on surveillance videos
Generalized partially adaptive concentric ring array
A full-custom design of AES SubByte module with signal independent power consumption
Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulses
Optimal distance estimation for the spectral efficiency of an hybrid cellular DS/SFH CDMA system
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation
Correlation learning rule in floating-gate pFET synapses
Digital background calibration of pipeline ADC with open-loop gain stage
A fully integrated wide-band PID controller with capacitor-less compensation for step-down DC-DC converter
A 0.8-µW switched-capacitor sigma-delta modulator using a class-C inverter
Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks
Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling
Probabilistic Viewport Adaptive Streaming for 360-degree Videos
Memristors as radiofrequency switches
S-sequence: a new floorplan representation method preserving room abutment relationships
Directional-edge-based object tracking employing on-line learning and regeneration of multiple candidate locations
Blind channel estimation based robust physical layer key generation in MIMO networks
Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge
Linearity enhancement in Digital-to-Analog Converters using a modified decoding architecture
A 70dB Gain Low-Power Band-Pass Amplifier for Bio-Signals Sensing Applications
Design, double sided post-processing, and packaging of CMOS compatible bio-MEMS device arrays
Robust adaptive beamforming for large steering angle error
On Three-Way Graph Partitioning
A clock recovery circuit for blind equalization multi-Gbps serial data links
Closed loop inverse load modulation power control by magnetic field diminishment in inductively powered biomedical implants
A Heterogeneous FPGA-based Accelerator Design for Efficient and Low-cost Point Clouds Deep Learning Inference
A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications
Signal Denoising Technique Employing Detrended Fluctuation Thresholding and Stationary Wavelet Transform in the Framework of Data-driven Multiresolution Analysis
Color Correction of Multiview Video with Average Color as Reference
SONICmole: a debugging environment for the UltraSONIC reconfigurable computer
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code
Feature based compression of vector quantized codebooks and data for optimal image compression
Accurate time domain extraction of supercapacitor fractional-order model parameters
Maximum entropy and maximum likelihood criteria for feature selection from multivariate data
Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology
Sampling-rate optimization of an interleaved-sampling front-end
An alternating variable approach to FIR filter design with power-of-two coefficients using the frequency-response masking technique
An integral image and text processing system for automatic generation of 3D sign-language animations
A frequency domain approach for blind identification with filter bank precoders
Enhanced bus invert encodings for low-power
TWavefussion: Wavelet-based Diffusion with Transformer for Multivariate Time Series Anomaly Detection
Algebraic methods for the analysis and design of time-frequency signal processing algorithms
A highly-efficient multi-band multi-mode digital quadrature transmitter with 2D pre-distortion
A combined TDA/FDA adaptive schema for stereophonic acoustic echo cancellation
Co-occurrence features of multi-scale directional filter bank for texture characterization
2-level FIFO architecture design for switch fabrics in network-on-chip
Characterization of a 16-bit threshold logic single-electron technology adder
A digital background correction technique combined with DWA for DAC mismatch errors in multibit ΣΔ ADCs
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers
A Closer Look at the Delay-Chain based TRNG
A signal-specific successive-approximation analog-to-digital converter
Biorthonormal filter banks: Some necessary conditions, and orthonormalization
Design and simulation of a cooperative communication system based on DCSK/FM-DCSK
Modeling and Simulation of Power-Electronic Inverters in Analog Electronic Circuit Simulators
Realization of MIMO linear discrete-time systems with minimum L 2 -sensitivity and no overflow oscillations
Three-Level Analysis of Switched-Capacitor Converters Using Ladder Diagrams
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders
High performance DS-CDMA system using novel SC-I chip shaping
An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards
Reconfigurable Analog Array for Hardware Security
Analysis of series-parallel resonant converter with multipliers
Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning
An optimized 2.4 GHz CMOS LC-tank VCO with 0.55 %/V frequency pushing and 516 MHz tuning range
A Miniaturized 0.13-μm BiCMOS Reflective-Type Phase Shifter for K-Band Phased Arrarys (Invited)
Folded sums of chaotic trajectories distribute uniformly
A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs
Live demonstration: A sensor-processor array integrated circuit for high-speed real-time machine vision
PUFNet: A Deep Neural Network Based Modeling Attack for Physically Unclonable Function
Reduction of IBR-dominated Distribution Networks by Multi-port Synthesis and Clustering
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition
Learning Fine-Grained Semantics in Spoken Language Using Visual Grounding
Transform domain neural filters
Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling
Towards rate-distortion tradeoff in real-time color video coding
High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes
A Power-Efficient Attention-Infused CNN Hardware Accelerator for RF Spectrum Monitoring
AMUSD: Asynchronous Multi-Device Speculative Decoding for LLM Acceleration
A novel type-based group delay equalization technique
Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs
A direct synthesis method of cascaded continuous-time sigma-delta modulators
Application-Driven Synthesis of Energy-Efficient Reconfigurable-Precision Operators
A system verification strategy based on the BST infrastructure
An ECG measurement IC using driven-right-leg circuit
Efficient error recovery techniques in a novel multimedia streaming framework with peer-paired collaboration
A 0.9mA 95dB Sigma Delta Modulator for Digital RF Hearing Aid in 0.35µm CMOS
Tracking performance of an FDLMS near-end crosstalk canceller for xDSL systems
On Using Partial Reset for Pseudo-Random Testing
Autonomous CMOS image sensor for real time target detection and tracking
Bounds for Distributed Parameter Trees
Area and throughput efficient IDCT/IDST architecture for HEVC standard
Binning algorithm for accurate computer aided device modeling
A Novel Design of Ergodic Sequential Logic Integrated Cochlear Model for Reproduction of Nonlinear Compression Characteristics of Mammalian Cochlea and Efficient Implementation
A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware
A 28mW 10b 80MS/s pipelined ADC in 0.13µm CMOS
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders
High power factor of metal halide lamp with dimming control
Nonvolatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors
A Stacked 4×25 Gb/s Optical Receiver in 28 nm CMOS with 0.154 mW/Gb/s Power Efficiency
An algorithm for the optimization of adjustable fractional-delay all-pass filters
New hyperbolic source density models for blind source recovery score functions
A multi-path ring amplifier with dynamic biasing
Wide-range, reference free, on-chip voltage sensor for variable Vdd operations
Phase analysis of DNA genomic signals
Elimination of power line interference and noise in electrocardiogram using constrained eigenfilter
A Total Noise Power Based Digital Calibration Method for Continuous-Time Delta-Sigma Modulators
Design Automation for Charge Recovery Logic
A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs
Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors
Symmetrical predictor structure based integrated lossy, near lossless/lossless coding of images
Removing of blocking artefacts using error-compensation interpolation and fast adaptive spatial-varying filtering
Verification of Desynchronized Circuits
Low Complexity and High Throughput VLSI Architecture for AVC/H.264 CAVLC Decoding
Algorithm derivation and its embedded system realization of speed limit detection for multiple countries
Fast intra mode decision algorithm based on refinement in HEVC
FPGA based system for the generation of noise with programmable power spectrum
Low-Complexity 4-D IIR Filters for Multi-Depth Filtering and Occlusion Suppression in Light Fields
Efficient deblocking filter architecture for H.264 video coders
Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems
A New Design for A Frame Sampling Synchronizer
Analog Neuromorphic System Based on Multi Input Floating Gate MOS Neuron Model
Adaptive downsampling/upsampling for better video compression at low bit rate
Direct Design of Orthogonal Filter Banks and Wavelets
Adaptive contrast adjustment for postprocessing of tone mapped high dynamic range images
IoT in the Agribusiness, a Power Consumption View
New mode-domain representation of transmission line for power system studies-comparing with existing models
MSE filter design and spectrum parameterization by orthogonal FAM transform
Multi-Split-Row Threshold Decoding Implementations for LDPC Codes
A Low-Power BJT-Based Temperature Sensor with Wide Range and High Resolution
Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation
A 16Kb 10T-SRAM with 4x read-power reduction
Multiple description image transmission for diversity systems using block-based DC separation
Adaptive bandwidth PLL with compact current mode filter
Efficient memory management for FFT processors
ISCAS 2011 special sessions on education innovations and experiences
Slovenian text-to-speech system
Design and Implementation of a Machine Learning Based EEG Processor for Accurate Estimation of Depth of Anesthesia
Partial video encryption based on alternative integer transforms
Asymptotic behaviour of FIR filters
Optimization of Analog Accelerators for Deep Neural Networks Inference
Multitasking in hardware-software codesign for reconfigurable computer
Analog Emulation of a Reconfigurable Tap Changing Transformer
A 142MOPS/mW integrated programmable array accelerator for smart visual processing
Modified Taylor-series method for source and receiver localization using TDOA measurements with erroneous receiver positions
An Amplifier-Free 0-2 SAR-VCO MASH ΔΣ ADC
Neurosearch: a program library for neural network driven search meta-heuristics
Physical unclonable function with tristate buffers
Current mode radic X-domain Palmo technique cell for programmable analog VLSI
A statistical analysis of the dual-mode CMA
Analog neural network building blocks based on current mode subthreshold operation
Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder
Low-Latency Image Acquisition and Processing with a Programmable Vision-System-on-Chip
A structured DC analysis methodology for accurate verification of analog circuits
Using SoC FPAA and integrated simulator for implementation of circuits and systems in education
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
A real-time setup for multisite signal recording and processing in living neural networks
Period-doubling bifurcation and its boundary study of DFIGWind turbine connected with local interacting unbalanced loads in micro-grid
Physics-based modeling of a bi-layer Al₂O₃/Nb₂O₅ analog memristive device
Estimation of inertia in power grids with turbine governors
A sub GHz mostly digital BPSK IR UWB transceiver
CheckSyC: an efficient property checker for RTL SystemC designs
Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processor
Programmable Ring Oscillator PUF Based on Switch Matrix
A 2MHz CMOS Active Rectifier With PWM Mode Adaptive On/Off Delay Compensation for Wireless Power Transfer Systems
A Realization Method of the Transfer Functions Containing Variable Parameter
A Fully Integrated Architecture for Fast Programming of Floating Gates
Evaluation of the response of nonlinear systems to asymptotically almost periodic inputs
A Robust, Real-Time and Calibration-Free Lane Departure Warning System
A Prototyping Co-design Platform with A Simplified Architecture for Video Codec Implementation
Signal waveform characterization in RLC trees
Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes
Experimental Body-Input Three-Stage DC Offset Calibration Scheme for Memristive Crossbar
High performance scalable elliptic curve cryptosystem processor in GF(2 m )
Three-phase power factor corrector based on capacitor-clamped topology
VAMP: A Hierarchical Framework for Design for Manufacturability
A novel timing-error based approach for high speed highly linear Mixing-DAC architectures
Resynthesis and Retiming of Synchronous Sequential Cirucits
Evaluating a blind channel estimation technique that uses a hardware efficient equalizer
PHIroute: A Parallel Hierarchical Sea-of-Gates Router
Multihop hello guided routing-reactive for mobile ad hoc networks
Adaptive QOS control for MPEG-4 video communication over wireless channels
High performance data acquisition system for IRFPA testing
Quadrature generation techniques for frequency multiplication based oscillators
Delta discrete-time operator based realization procedure for low sensitivity sampled-data and digital ladder filters