yusuke1997/dblp-id-title huggingface dataset:
IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation: work-in-progress
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Power aware SID-based simulator for embedded multicore DSP subsystems
Security wrappers and power analysis for SoC technologies
Optimal memory controller placement for chip multiprocessor
A formal approach to robustness maximization of complex heterogeneous embedded systems
Towards scalable symbolic routing for multi-objective networked embedded system design and optimization
Co-design tool construction using APICES
Source-level execution time estimation of C programs
Exploiting quality-energy tradeoffs with arbitrary quantization: special session paper
Mapping of applications to MPSoCs
A low power scheduler using game theory
Compiler-directed selection of dynamic memory layouts
A Flexible Model for Evaluating the Behavior of Hardware/Software Systems
Linking codesign and reuse in embedded systems design
A DRAM-flash index for native flash file systems
A Case Study in Co-Design of Communication Controllers
A study of transistor degradation in cyber-physical system control devices: work-in-progress
Constraint-driven synthesis and tool-support for FlexRay-based automotive control systems
Improving security and maintainability in modular embedded systems with hardware support: work-in-progress
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors
Implications of Codesign as a Natural Constituent of a Systems Engineering Discipline for Computer Based Systems
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Dynamic overlay of scratchpad memory for energy minimization
DHeating: Dispersed heating repair for self-healing NAND flash memory
Process Partitioning for Distributed Embedded Systems
Synthesis of real-time embedded software with local and global deadlines
Modeling micro-controller peripherals for high-level co-simulation and synthesis
Heterogeneous multiprocessor implementations for JPEG: : a case study
Software controlled power management
VL-CDRAM: variable line sized cached DRAMs
An ASIP design methodology for embedded systems
Resource constrained dataflow retiming heuristics for VLIW ASIPs
Dynamic scheduling of stream programs on embedded multi-core processors
The analysis and design of architecture systems for speech recognition on modern handheld-computing devices
A PCM translation layer for integrated memory and storage management
Exploring models of computation with ptolemy II
A data protection unit for NoC-based architectures
Application-specific workload shaping in multimedia-enabled personal mobile devices
Low-power task scheduling for multiple devices
Automated technique for design of NoC with minimal communication latency
System level synthesis of hardware for DSP applications using pre-characterized function implementations
Heap data management for limited local memory (LLM) multi-core processors
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators
CODES/ISSS 2021, International Conference on Hardware/Software Codesign and System Synthesis, Virtual Event, October 10-13, 2021
Compiler-directed customization of ASIP cores
System-level power and timing variability characterization to compute thermal guarantees
CPU scheduling for statistically-assured real-time performance and improved energy efficiency
Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs
Worst-case analysis of discrete systems based on conditional abstractions
Self-aware systems for the internet-of-things
Dynamically utilizing computation accelerators for extensible processors in a software approach
Critical-weight based locking scheme for DNN IP protection in edge computing: work-in-progress
B 2 Sim: : a fast micro-architecture simulator based on basic block characterization
Fuzzy decision making in embedded system design
Asynchronous transient resilient links for NoC
Synthesis of communication schedules for TTEthernet-based mixed-criticality systems
Performance and resource optimization of NoC router architecture for master and slave IP cores
Shift buffering technique for automatic code synthesis from synchronous dataflow graphs
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Taming extreme heterogeneity via machine learning based design of autonomous manycore systems
On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC)
SHAPES: : a tiled scalable software hardware architecture platform for embedded systems
Interface Optimization During Hardware-Software Partitioning
Energy efficient FFT implementation through stage skipping and merging
Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design
WHISK: An uncore architecture for Dynamic Information Flow Tracking in heterogeneous embedded SoCs
Dimensioning and configuration of EES systems for electric vehicles with boundary-conditioned adaptive scalarization
dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations
Scratchpad allocation for concurrent embedded software
A low-cost and low-power multi-standard video encoder
Techniques for Design Analysis and Modification Based on ASAP Model: Work-in-Progress
Minimizing power supply noise through harmonic mappings in networks-on-chip
The shift to multicores in real-time and safety-critical systems
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
Increasing hardware efficiency with multifunction loop accelerators
Cost-effective design of a hybrid electrical energy storage system for electric vehicles
Benchmark-based design strategies for single chip heterogeneous multiprocessors
Modeling and evaluation of hardware/software designs
How to improve the space utilization of dedup-based PCM storage devices?
Satisfying real-time constraints with custom instructions
Challenges in exploitation of loop parallelism in embedded applications
Compile-time decided instruction cache locking using worst-case execution paths
Timing-driven HW/SW codesign based on task structuring and process timing simulation
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
Towards a declarative framework for hardware-software codesign
Event-based re-training of statistical contention models for heterogeneous multiprocessors
Processor frequency setting for energy minimization of streaming multimedia application
Automatic synthesis of system on chip multiprocessor architectures for process networks
Fast co-simulation of transformative systems with OS support on SMP computer
EAST-DNN: Expediting architectural SimulaTions using deep neural networks: work-in-progress
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs
A scalable parallel H.264 decoder on the cell broadband engine architecture
System canvas: a new design environment for embedded DSP and telecommunication systems
Embedded neuromorphic vision systems
Towards a new standard for system-level design
Time in cyber-physical systems
System-level design exploration for 3-D stacked memory architectures
Network-aware design-space exploration of a power-efficient embedded application
Parameterised system design based on genetic algorithms
Quantized NNs as the definitive solution for inference on low-power ARM MCUs?: work-in-progress
Realizing erase-free SLC flash memory with rewritable programming design
A chip-level security framework for assessing sensor data integrity: work-in-progress
Timing coverification of concurrent embedded real-time systems
High durability in NAND flash memory through effective page reuse mechanisms
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor
Drama: A high efficient neural network accelerator on FPGA using dynamic reconfiguration: work-in-progress
An efficient technique for computing importance measures in automatic design of dependable embedded systems
Optimization and synthesis for complex reactive embedded systems by incremental collapsing
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Integrated analysis of communicating tasks in MPSoCs
Modeling and analyzing real-time multiprocessor systems
Online adaptive utilization control for real-time embedded multiprocessor systems
Parameterized system design
Slack analysis in the system design loop
Retargetable code optimization with SIMD instructions
Phase guided sampling for efficient parallel application simulation
A testbench specification language for SystemC verification
Policy-based message scheduling using FlexRay
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture
High-level synthesis for large bit-width multipliers on FPGAs: a case study
Panappticon: Event-based tracing to measure mobile application and platform performance
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet
Dynamic phase analysis for cycle-close trace generation
System-level reliability modeling for MPSoCs
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications
Automatic test bench generation for simulation-based validation
Generating mixing hardware/software systems from SDL specifications
Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era
Rank based dynamic voltage and frequency scaling fortiled graphics processors
Multi-processor system design with ESPAM
Software energy optimization through fine-grained function-level voltage and frequency scaling
IVaM: Implicit variant modeling and management for automotive embedded systems
Communication Synthesis for Embedded Systems with Global Considerations
Decision-theoretic exploration of multiProcessor platforms
Applying network calculus for performance analysis of self-similar traffic in on-chip networks
Multi-objective design space exploration using genetic algorithms
A cyber-physical system approach to artificial pancreas design
Automated firmware testing using firmware-hardware interaction patterns
Power reduction via macroblock prioritization for power aware H.264 video applications
Dark silicon as a challenge for hardware/software co-design
Performance modeling of embedded applications with zero architectural knowledge
COSMOS: a codesign approach for communicating systems
Worst-case throughput analysis of real-time dynamic streaming applications
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures
Synthesis of optimized hardware transactors from abstract communication specifications
ESWEEK industry keynote: embedding the cloud
A bursty multi-port memory controller with quality-of-service guarantees
Extended quasi-static scheduling for formal synthesis and code generation of embedded software
Designing a residential hybrid electrical energy storage system based on the energy buffering strategy
An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking
Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment
Automated HW/SW co-design for edge AI: state, challenges and steps ahead
Layout aware design of mesh based NoC architectures
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures
Instruction set extensions for Dynamic Time Warping
Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994
Future processors: flexible and modular
Domain-specific interface generation from dataflow specifications
Don't burn your mobile!: safe computational re-sprinting via model predictive control
Transaction level modeling: flows and use models
HW/SW co-design for Esterel processing
A framework of awareness for artificial subjects
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
Performance modeling for early analysis of multi-core systems
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Grand challenges in embedded systems
Area-efficient buffer binding based on a novel two-port FIFO structure
An automated exploration framework for FPGA-based soft multiprocessor systems
Program slicing for codesign
Scheduling garbage collection in real-time systems
Computing without processors
Distributed flit-buffer flow control for networks-on-chip
Extending open core protocol to support system-level cache coherence
Developing design tools for biological and biomedical applications of micro- and nano-technology
Designing parameterized signal processing ips for high level synthesis in a model based design environment
SPaC: a symbolic pareto calculator
A flexible code generation framework for the design of application specific programmable processors
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
GraphPage: RDF Graph in SSD Pages: Work-in-Progress
Symbolic design space exploration for multi-mode reconfigurable systems
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
Scalable and retargetable simulation techniquesfor multiprocessor systems
Dynamic property mining for embedded software
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
Highly-cited ideas in system codesign and synthesis
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, Montreal, QC, Canada, September 29 - October 4, 2013
Types of computational self-awareness and how we might implement them
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Detecting overflow detection
Accelerating Queries of MongoDB by an FPGA-based Storage Engine: Work-in-Progress
Improved response time analysis of tasks scheduled under preemptive Round-Robin
Constrained software generation for hardware-software systems
A language for multiple models of computation
Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking
Modeling industrial embedded systems with UML
Design space exploration of a hardware-software co-designed GF(2 m ) galois field processor for forward error correction and cryptography
Prediction and control of bursty cloud workloads: A fractal framework
Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress
Fast model-based test case classification for performance analysis of multimedia MPSoC platforms
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors
New architectures for smart cards: the OCEAN approach
Big data analytics on heterogeneous accelerator architectures
Organic computing: on the feasibility of controlled emergence
WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress)
Run-DMC: Runtime dynamic heterogeneous multicore performance and power estimation for energy efficiency
Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints
Cycle count accurate memory modeling in system level design
Combining multiple models of computation for scheduling and allocation
Compilation techniques for CGRAs: exploring all parallelization approaches
Native MPSoC co-simulation environment for software performance estimation
Communication optimization for thermal reliable many-core systems: work-in-progress
HDL code restructuring using timed decision tables
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Automatic refinement of requirements for verification throughout the SoC design flow
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache
SARA: StreAm register allocation
A study of CodePack: optimizing embedded code space
Meta-Chain: User-Aware Cross-Layer Space Allocation Strategy for Blockchain Storage Systems: Work-in-Progress
Scheduling-based code size reduction in processors with indirect addressing mode
Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms
Using minimal minterms to represent programmability
The system verification methodology for advanced TLM verification
A physically realizable backdoor attack on 3D point cloud deep learning: work-in-progress
Heuristic tradeoffs between latency and energy consumption in register assignment
Hypnos: An ultra-low power sleep mode with SRAM data retention for embedded microcontrollers!
ESL power analysis of embedded processors for temperature and reliability estimations
Simulation bridge: a framework for multi-processor simulation
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs
An evolutionary approach to system-level synthesis
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
Hardware/software co-design of an ATM network interface card: a case study
Industry best practices in embedded software
Conflict analysis in multiprocess synthesis for optimized system integration
Critical path driven cosynthesis for heterogeneous target architectures
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems
Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress
Verification of design decisions in ForSyDe
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002
Fast performance prediction for periodic task systems
Flexible design of SPARC cores: a quantitative study
Iterational retiming: maximize iteration-level parallelism for nested loops
Automatic Generation of a Real-Time Operating System for Embedded Systems
SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networks
A constraint-based application model and scheduling techniques for power-aware systems
Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996
Towards effective embedded processors in codesigns: customizable partitioned caches
An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the "Design for Monitorability" Project - Work-in-Progress
A high-level virtual platform for early MPSoC software development
Communication estimation for hardware/software codesign
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling
SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories
FPGA resource and timing estimation from Matlab execution traces
Multilanguage design of heterogeneous systems
Pruning-based energy-optimal device scheduling for hard real-time systems
CMSM: An efficient and effective Code Management for Software Managed Multicores
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
A design framework to efficiently explore energy-delay tradeoffs
Automatic network generation for system-on-chip communication design
Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging
Communication refinement in video systems on chip
Dynamic transient fault detection and recovery for embedded processor datapaths
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
Scalable NoC-based architecture of neural coding for new efficient associative memories
Embedded UML: a merger of real-time UML and co-design
ESL design and HW/SW co-verification of high-end software defined radio platforms
Synchronization after design refinements with sensitive delay elements
Generic netlist representation for system and PE level design exploration
Speculative DMA for architecturally visible storage in instruction set extensions
Hardware/software optimization of error detection implementation for real-time embedded systems
System synthesis utilizing a layered functional model
Programming embedded networked sensor systems
Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors
Software performance estimation strategies in a system-level design tool
Exploring design space of parallel realizations: MPEG-2 decoder case study
A SIMD-aware pruning technique for convolutional neural networks with multi-sparsity levels: work-in-progress
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
Energy-efficient mapping of real-time applications on heterogeneous MPSoCs using task replication
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems
Combined approach to system level performance analysis of embedded systems
Algorithmic transformation techniques for efficient exploration of alternative application instances
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Register file management for PRET machines: work-in-progress
The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routers
Development cost and size estimation starting from high-level specifications
Redesigning hardware-software systems
COOL: control-based optimization of load-balancing for thermal behavior
Web browser workload characterization for power management on HMP platforms
STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems
Beyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processing
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000
Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Keynote: cellular handset technology system requirements and integration trends
An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips
A novel deadlock avoidance algorithm and its hardware implementation
An Approach to Mixed Systems Co-Synthesis
Optimistic distributed timed cosimulation based on thread simulation model
Managing latency in embedded streaming applications under hard-real-time scheduling
Embedded system synthesis under memory constraints
Exploiting temporal decoupling to accelerate trace-driven NoC emulation
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999
The TACO protocol processor simulation environment
Overhead effects in real-time preemptive schedules
A bus architecture for crosstalk elimination in high performance processor design
Internet-of-energy: combining embedded computing and communication for the smart grid