yusuke1997/dblp-id-title huggingface dataset:
J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
One-for-All: An Unified Learning-based Framework for Efficient Cross-Corner Timing Signoff
BIST-PUF: online, hardware-based evaluation of physically unclonable circuit identifiers
NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times
Efficient coupled noise estimation for on-chip interconnects
VERILAT: verification using logic augmentation and transformations
Fast analog layout prototyping for nanometer design migration
Technology mapping for standard-cell generators
Graphene nanoribbon FETs: technology exploration and CAD
Constrained interpolation for guided logic synthesis
Unveiling the Mask: Trusted Semiconductor Manufacturing through Wafer-Level Mask-Set Attestation
Towards efficient hierarchical designs by ratio cut partitioning
Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing
Efficient Uncertainty Modeling for System Design via Mixed Integer Programming
Discrete-event simulation on hypercube architectures
An efficient compaction algorithm for test vectors of microprocessors and microcontrollers
Restricted symbolic evaluation is fast and useful
Sensor Security: Current Progress, Research Challenges, and Future Roadmap (Invited Paper)
Uncertainty quantification of electronic and photonic ICs with non-Gaussian correlated process variations
ATRIUM: Runtime attestation resilient under memory attacks
Shedding Light on LLMs: Harnessing Photonic Neural Networks for Accelerating LLMs
Majority logic synthesis
Allocation of multi-bit flip-flops in logic synthesis for power optimization
Effective CAD Research in the Sea of Papers
CDMA/FDMA-interconnects for future ULSI communications
Useful-skew clock optimization for multi-power mode designs
On properties of algebraic transformation and the multifault testability of multilevel logic
Tree-based mapping of algorithms to predefined structures
COPA: A Congestion-Oriented Pin Assignment Framework for Intra-Block Physical Design Optimization
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors
Scheduling with soft constraints
Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques
Improving over-the-cell channel routing in standard cell design
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper
Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
BugMD: automatic mismatch diagnosis for bug triaging
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data
DATC RDF-2019: Towards a Complete Academic Reference Design Flow
Unified complete MOSFET model for analysis of digital and analog circuits
TorchQuantum Case Study for Robust Quantum Circuits
Activity-driven clock design for low power circuits
Clock Aware Low Power Placement
Invited Paper: Feature-to-Classifier Co-Design for Mixed-Signal Smart Flexible Wearables for Healthcare at the Extreme Edge
Scalable and efficient analog parametric fault identification
Analysis of VLSI Microconductor Systems by Bi-Level Waveform Relaxation
Sound Source Localization Using Stochastic Computing
Perturbation-efficient Zeroth-order Optimization for Hardware-friendly On-device Training
System level design and debug of high-performance embedded media systems (tutorial)
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration
Synchronous equivalence for embedded systems: a tool for design exploration
NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures
Noise margin analysis for dynamic logic circuits
Deep reinforcement learning: Framework, applications, and embedded implementations: Invited paper
A universal ordered NoC design platform for shared-memory MPSoC
Reliable Machine Learning for Wearable Activity Monitoring: Novel Algorithms and Theoretical Guarantees
An analytic placer for mixed-size placement and timing-driven placement
On error modeling and analysis of approximate adders
Optimizing SFQ Circuit Design: A Timing-Driven Framework for Performance-Constrained Area Minimization
Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation
Misleading energy and performance claims in sub/near threshold digital systems
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools
Overview of the 2015 CAD Contest at ICCAD
An Algorithm for Component Selection in Performance Optimized Scheduling
A succinct memory model for automated design debugging
An efficient procedure for the synthesis of fast self-testable controller structures
A delay fault model for at-speed fault simulation and test generation
On error correction in macro-based circuits
Robust Time-Sensitive Networking with Delay Bound Analyses
Performance Enhancement through the Generalized Bypass Transform
A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA
Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges
Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effects
FDT-a design tool for switched capacitor filters
Sequential logic to transform probabilities
Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning
A powerful global router: based on Steiner min-max trees
A multithreaded initial detailed routing algorithm considering global routing guides
2019 CAD Contest: LEF/DEF Based Global Routing
A hierarchical matrix inversion algorithm for vectorless power grid verification
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning
HLSPredict: cross platform performance prediction for FPGA high-level synthesis
3D integrated circuits: Designing in a new dimension: Designer track
Numerical integration algorithms and asymptotic waveform evaluation (AWE)
Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models
Leakage control through fine-grained placement and sizing of sleep transistors
ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite
Using standardized quantization for multi-party PPUF matching: Foundations and applications
New methods for parallel pattern fast fault simulation for synchronous sequential circuits
MAGNet: A Modular Accelerator Generator for Neural Networks
Verification of Flow-Based Computing Systems Using Bounded Model Checking
Efficient diagnosis of path delay faults in digital logic circuits
Simulating 3-D retarded interconnect models using complex frequency hopping (CFH)
SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction
A capacitance solver for incremental variation-aware extraction
Power Exploration for Embedded VLIW Architectures
DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance
HISA: hardware isolation-based secure architecture for CPU-FPGA embedded systems
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints
FACT-a testability analysis methodology
Leveraging recovery effect to reduce electromigration degradation in power/ground TSV
A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAM
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters
Cross-layer error resilience for robust systems
Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN Accelerator
An Optimal Algorithm for Splitter and Buffer Insertion in Adiabatic Quantum-Flux-Parametron Circuits
Congestion Aware Layout Driven Logic Synthesis
Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices
Java as a specification language for hardware-software systems
Accelerating functional timing analysis with encoding duplication removal and redundant state propagation
Simulation and sensitivity analysis of transmission line circuits by the characteristics method
Generation of BDDs from hardware algorithm descriptions
Length-Matching Routing for High-Speed Printed Circuit Boards
An efficient multi-view design model for real-time interactive synthesis
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects
A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems
Synthesis of application specific instructions for embedded DSP software
SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes
Embracing Graph Neural Networks for Hardware Security
Balor: HLS Source Code Evaluator Based on Custom Graphs and Hierarchical GNNs
MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management
Timing analysis considering spatial power/ground level variation
Approximate Computing and the Efficient Machine Learning Expedition
Simulation-based bug trace minimization with BMC-based refinement
Testing oriented analysis of CMOS ICs with opens
BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems
AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge
A sequential quadratic programming approach to concurrent gate and wire sizing
Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications
ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs
Minimization of Symbolic Relations
TAU 2014 contest on removing common path pessimism during timing analysis
A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration
Minimizing expected energy consumption through optimal integration of DVS and DPM
Temperature aware statistical static timing analysis
Towards Verification-Aware Knowledge Distillation for Neural-Network Controlled Systems: Invited Paper
Performance optimization using separator sets
Layout Driven Logic Restructuring/Decomposition
CRIS: a test cultivation program for sequential VLSI circuits
Digital logic with molecular reactions
Provably good algorithm for low power consumption with dual supply voltages
Efficient Conflict Driven Learning in Boolean Satisfiability Solver
ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance Counters
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs
High-level synthesis with timing-sensitive information flow enforcement
A streaming clustering approach using a heterogeneous system for big data analysis
An Efficient Routing Optimization Framework for Silicon-Based Spin-Qubit Devices
A scalable decision procedure for fixed-width bit-vectors
An Optimal Channel Pin Assignment Algorithm
An efficient approach to simultaneous transistor and interconnect sizing
P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture
Fredkin/Toffoli Templates for Reversible Logic Synthesis
A formal basis for design process planning and management
A logic synthesis system for VHDL design descriptions
A New Test Generation Method for Sequential Circuits
PYRAMID-a hierarchical waveform relaxation-based circuit simulation program
Studying a GALS FPGA architecture using a parameterized automatic design flow
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
VLSI circuit partitioning by cluster-removal using iterative improvement techniques
Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow
Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines
Invited Paper: 2023 ICCAD CAD Contest Problem C: Static IR Drop Estimation Using Machine Learning
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
Linear analysis of random process variability
Routing for chip-package-board co-design considering differential pairs
A Framework for Constrained Functional Verification
A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems
Verification of Integer Multipliers on the Arithmetic Bit Level
Routing for symmetric FPGAs and FPICs
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability
Accurate, Yet Scalable: A SPICE-based Design and Optimization Framework for eNVM based Analog In-memory Computing
An incremental learning framework for estimating signal controllability in unit-level verification
Layout decomposition for triple patterning lithography
The Inversion Algorithm for digital simulation
A new approach to sea-of-gates global routing
Dynamic power management using machine learning
A method for net representation with polygon decomposition
VecPAC: A Vectorizable and Precision-Aware CGRA
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL
Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
PowerRush : Efficient transient simulation for power grid analysis
Differentiated handling of physical scenes and virtual objects for mobile augmented reality
Analytical delay models for VLSI interconnects under ramp input
Challenges in Physical Chip Design
Exploiting Randomness in Stochastic Computing
DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives
LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture
Don't Care Minimization of Multi-Level Sequential Logic Networks
When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing
CHASE: A Configurable Hardware-Assisted Security Extension for Real-Time Systems
A unified approach to topology generation and area optimization of general floorplans
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors
Congestion minimization during placement without estimation
A bounded delay race model
Compact modeling of variational waveforms
Robust passive hardware metering
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Bus Encoding to Prevent Crosstalk Delay
Adaptive power management using reinforcement learning
A systematic approach for analyzing and optimizing cell-internal signal electromigration
A diagnosis method using pseudo-random vectors without intermediate signatures
Design space exploration of drone infrastructure for large-scale delivery services
Path-RO: a novel on-chip critical path delay measurement under process variations
On logic synthesis for timing speculation
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines
Exploring heterogeneous NoC design space
IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers
ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement
Wire Reconnections Based on Implication Flow Graph
Checking equivalence of quantum circuits and states
Integrating Exact Simulation into Sweeping for Datapath Combinational Equivalence Checking
Who are the variables in your neighborhood
Switch module design with application to two-dimensional segmentation design
Early-stage Automated Accelerator Identification Tool for Embedded Systems with Limited Area
Fault emulation: a new approach to fault grading
Synthesis of BIST hardware for performance testing of MCM interconnections
Storage assignment during high-level synthesis for configurable architectures
Exploiting hierarchy and structure to efficiently solve graph coloring as SAT
GRASP - a new search algorithm for satisfiability
Boolean factorization using multiple-valued minimization
On the Efficiency of the Transition Fault Model for Delay Faults
A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints
Battery allocation for wireless sensor network lifetime maximization under cost constraints
Improved reachability analysis of large finite state machines
TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations
Progress and outlook for STT-MRAM
Sequential synthesis using S1S
Self-Aware Cyber-Physical Systems-on-Chip
An analog SAT solver based on a deterministic dynamical system: (Invited paper)
Analytically Modeling Power and Performance of a CNN System
SeGen: Automatic Topology Generator for Sequencing Elements
An FPGA-based Key-Switching Accelerator with Ultra-High Throughput for FHE
TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators
Post global routing RLC crosstalk budgeting
Symbolic Algebra and Timing Driven Data-flow Synthesis
Parameter Setting Heuristics Make the Quantum Approximate Optimization Algorithm Suitable for the Early Fault-Tolerant Era
Automatic generation and verification of sufficient correctness properties for synchronous processors
Dynamic Data-bit Memory Built-In Self- Repair
A novel sequential circuit optimization with clock gating logic
Power-aware microsensor design
Post-routing redundant via insertion and line end extension with via density consideration
On Relaxing Page Program Disturbance over 3D MLC Flash Memory
Simulated annealing: a fast heuristic for some generic layout problems
Total power-optimal pipelining and parallel processing under process variations in nanometer technology
Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
Performance enhancements in BOLD using 'implications'
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators
Determination of worst-case aggressor alignment for delay calculation
Adaptive sampling for efficient failure probability analysis of SRAM cells
A High-level Interconnect Power Model for Design Space Exploration
Approximate logic synthesis under general error magnitude and frequency constraints
Noise considerations in circuit optimization
Optimizing Supply Chain Management using Permissioned Blockchains
Exploring Boolean and non-Boolean computing with spin torque devices
An Exact Algorithm for Single-Layer Wire-Length Minimization
A wire-length minimization algorithm for single-layer layouts
DOMINO: Domain-Invariant Hyperdimensional Classification for Multi-Sensor Time Series Data
Incremental synthesis
ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite
Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks
MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package Integration
Speeding up crossbar resistive memory by exploiting in-memory data patterns
Modern Big Data Analytics for "Old-fashioned" Semiconductor Industry Applications
A multiple-dominance switch-level model for simulation of short faults
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering
HF-Dedupe: Hierarchical Fingerprint Scheme for High Efficiency Data Deduplication on Flash-based Storage Systems
Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the Edge
A linear-time approach for static timing analysis covering all process corners
FastStamp: Accelerating Neural Steganography and Digital Watermarking of Images on FPGAs
TIGER: testability insertion guidance expert system
An "Effective" Capacitance Based Delay Metric for RC Interconnect
High Level Synthesis of RDF Queries for Graph Analytics
A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structures
Testing delay faults in asynchronous handshake circuits
Novel wire density driven full-chip routing for CMP variation control
Facilitating Deployment Of A Wafer-Based Analytic Software Using Tensor Methods: Invited Paper
Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells
Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision
Accelerating Fault Injection for Validating Processor RTL Implementations
Improvements to combinational equivalence checking
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic
Modeling and optimization of magnetic core TSV-inductor for on-chip DC-DC converter
Scan power reduction in linear test data compression scheme
RIMI: Instruction-level Memory Isolation for Embedded Systems on RISC-V
An algorithm for identifying dominant-edge metabolic pathways
Scaling the "Memory Wall": Designer track
Wafer Packing for Full Mask Exposure Fabrication
Automatic layout of custom analog cells in ANAGRAM
Reducing cache misses by application-specific re-configurable indexing
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
BAG: a designer-oriented integrated framework for the development of AMS circuit generators
Redistribution layer routing for integrated fan-out wafer-level chip-scale packages
Machine learning for design space exploration and optimization of manycore systems
Dali: A Gridded Cell Placement Flow
Where formal verification can help in functional safety analysis
Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design
A soft error rate analysis (SERA) methodology
GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method
Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping
A new generalized row-based global router
From biochips to quantum circuits: computer-aided design for emerging technologies
An efficient pre-assignment routing algorithm for flip-chip designs
Invited Paper: Rapid Performance Evaluation and Optimized AI Inference for Heterogeneous Automotive Chiplets
Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate Comparison
Backend CAD flows for "restrictive design rules"
Optimal wire retiming without binary search
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
Color Permutation: An Iterative Algorithm for Memory Packing
Distributed Methodology Management for Design-in-the-Large
From Specification to Topology: Automatic Power Converter Design via Reinforcement Learning
MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor Network
Agile SoC Development with Open ESP : Invited Paper
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks