yusuke1997/dblp-id-title huggingface dataset:
Design of transport triggered architectures
Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack
Reconfigurable repetitive padding unit
Modular Design of Communication Node Prototypes
CADOSys: Cache Aware Design Space Optimization for Spatial ML Accelerators
Modeling stuck-open faults in CMOS iterative circuits
Properties of on-chip inductive current loops
Bounding the efforts on congestion optimization for physical synthesis
On the Vulnerability of Hardware Masking in Practical Implementations
Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection
On the Adversarial Robustness of Quantized Neural Networks
'NCHIPSIM'-a microcomputer simulator of NMOS chip performance indicators
TASecure: Temperature-Aware Secure Deletion Scheme for Solid State Drives
Statistical estimation of delay fault detectabilities and fault grading
PeerCollate: A Peer-Centered Team Learning Approach to Digitized STEM Lab Activities and Assessments
Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings
STI stress aware placement optimization based on geometric programming
On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chips
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers
Logic synthesis for integrated optics
Low Power Driven Scheduling and Binding
Low Power Techniques for Digital GaAs VLSI
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits
Co-evolutionary high-level test synthesis
Reliable logic mapping on Nano-PLA architectures
FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiency
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology
Navigating SoC Security Landscape on LLM-Guided Paths
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications
A Fully Pipelined, 700MBytes/s DES Encryption Core
RT-level vector selection for realistic peak power simulation
Clock tree regeneration
A systematic approach for designing systolic arrays
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
A Pixel Histogram-Based Safety Mechanism and Fault Detection Methodology for a Robust Image Signal Processor
DIP: a double-interval-based dynamic voltage scaling scheme for dynamic priority-based task scheduling systems
An on-chip solution for static ADC test and measurement
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)
Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections
NBTI resilient circuits using adaptive body biasing
Low-power circuits using dynamic threshold devices
Comparative Study of Approximate Multipliers
Overcoming Training Data Scarcity in Routing Demand Prediction via Ensemble Learning
Design Issues in Synthesis of Reusable Cores
Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count
Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits
QCA channel routing with wire crossing minimization
An efficient approach for designing and minimizing reversible programmable logic arrays
Self-checking sequential circuits with self-healing ability
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
FPGA-based synthesis of FSMs through decomposition
RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits
Corner stitching for L-shaped tiles
Resistorless Grounded Memristor Emulator Using OTA-OTRA for low power edge computing
OCV-aware top-level clock tree optimization
Dominator-based partitioning for delay optimization
A Methodology for High Level Power Estimation and Exploration
A decoupling method for analysis of coupled RLC interconnects
Automation of Biological Model Learning, Design and Analysis
A Comparative Review and Evaluation of Approximate Adders
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture
A Web-based Remote FPGA Laboratory for Computer Organization Course
Leveraging RF Power for Intelligent Tag Networks
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing
Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits
Combinational equivalence checking for threshold logic circuits
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines
An Efficient and Robust Algorithm for Common Path Pessimism Removal In Static Timing Analysis
An efficient algorithm for the realizability analysis of signal transition graphs
Functional ATPG for Delay Faults
RDTA: An Efficient Routability-Driven Track Assignment Algorithm
A reconstructive approach to automated design synthesis
Design of a Low-Overhead Random Number Generator Using CMOS-based Cascaded Chaotic Maps
Session details: Session 2B: Computer-Aided Design (CAD)
Anomaly Detection Method based on Discrete Particle Swarm Optimization for Continuous-Flow Microfluidic Biochips
Battery-aware Design Exploration of Scheduling Policies for Multi-sensor Devices
An integrated thermal estimation framework for industrial embedded platforms
Definition and application of approximate necessary assignments
Guiding Power/Quality Exploration for Communication-Intense Stream Processing
Floorplan repair using dynamic whitespace management
CMOS flash analog-to-digital converter for high speed and low voltage applications
An effective and efficient ATPG-based combinational equivalence checker
Modified booth truncated multipliers
Analyzing and modeling process balance for sub-threshold circuit design
New GPR System Integration with Augmented Reality Based Positioning
Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned
Some Issues in Gray Code Addressing
ToEFL: A Novel Approach for Training on Edge in Smart Agriculture
Physically unclonable functions: manufacturing variability as an unclonable device identifier
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips
Robust wiring networks for DfY considering timing constraints
FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications
A complete methodology for an accurate static noise analysis
Efficient algorithms for acceptable design exploration
A novel multi-objective instruction synthesis flow for application-specific instruction set processors
Throughput Optimization for Lifetime Budgeting in Many-Core Systems
DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural Networks
A sensitivity analysis of low-power repeater insertion
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA
GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing
Design of Dynamic Range Approximate Logarithmic Multipliers
Low Voltage Low power CMOS AGC circuit for wireless communication
Design of a Flash-based Circuit for Multi-valued Logic
ASIC design for robust signal and image processing
Designing VLSI systolic arrays with complex processing elements
Efficient Softmax Hardware Architecture for Deep Neural Networks
Designing Really Big Value Ideas
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
Bus minimization and scheduling of multi-chip systems
HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard System
Modeling symmetrical independent gate FinFET using predictive technology model
Simulated annealing based yield enhancement of layouts
Design of Error-Resilient Logic Gates with Reinforcement Using Implications
Exploring Main Memory Design Based on Racetrack Memory Technology
CMOS output buffer waveshaping
A new look at the conditions for the synthesis of speed-independent circuits
RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers
Invisible Leaks: Covert Channel Exploitation in In-Sensor Computing System
Physical design exploration of 3D tree-based FPGA architecture
Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems
Evaluation of the Complexity of Automated Trace Alignment using Novel Power Obfuscation Methods
Fortified-Edge 4.0: A ML-Based Error Correction Framework for Secure Authentication in Collaborative Edge Computing
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults
Information Hiding behind Approximate Computation
Hardware Accelerated Quantized Hand Written Digit Recognition via High Level Synthesis
Real-Time Hardware Stereo Matching Using Guided Image Filter
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping
Improved ber performance in intra-chip rf/wireless interconnect systems
A Radix-16 SRT Division Unit with Speculation of the Quotient Digits
Coefficient-based parametric faults detection in analog circuits
Thermal analysis of a 3D die-stacked high-performance microprocessor
Dynamically resizable binary decision diagrams
STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms
EPIC: Efficient and Proactive Instruction-level Cyberdefense
Formal Verification of Tree-Structured Carry-Lookahead Adders
The Design of Residue Number System Arithmetic Units for A VLSI Adaptive Equalizer
Design of Energy Efficient Posit Multiplier
A new methodology for reduced cost of resilience
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs
A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient Applications
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC
Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling
Efficient parallel beamforming for 3D ultrasound imaging
NBTI-aware sleep transistor design for reliable power-gating
ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System
LEGO: A 12nm FinFET Analog Cell Library for Analog/Mixed-Signal Applications
Fast Thermal Simulation using SystemC-AMS
Reinforcement Learning for Thermal-aware Many-core Task Allocation
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Don't Cares in Quantum Circuits: A Security Perspective
PixelPrune: Optimizing AIoT Vision Systems via In-Sensor Segmentation and Adaptive Data Transfer
Quick supply current waveform estimation at gate level using existed cell library information
A parallel algorithm for logic simulation on transputer networks
An algebraic approach to test generation for sequential circuits
Power-time flexible architecture for GF(2 k ) elliptic curve cryptosystem computation
Low power and high performance design challenges in future technologies
SINMEF - A Decomposition Based Synthesis Tool for Large FSMs
IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube
Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994
Fast composite field S-box architectures for advanced encryption standard
Reconvergent Path-aware Simulation of Bit-stream Processing
RAFeL - Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) Networks
On legalization of row-based placements
Latency Variation Aware Read Performance Optimization on 3D High Density NAND Flash Memory
Gate level representation of ECL circuits for fault modeling
Low power and high performance sram design using bank-based selective forward body bias
A New Methodology for Noise Sensor Placement Based on Association Rule Mining
Top-down-based symmetrical buffered clock routing
High-throughput low-complexity MIMO detector based on K-best algorithm
Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories
Better than optimum?: register reduction using idle pipelined functional units
Parallel pipelined FFT architectures with reduced number of delays
A symmetric mos current-mode logic universal gate for high speed applications
Automated system partitioning for synthesis of multi-chip modules
RF CMOS circuit optimizing procedure and synthesis tool
On equivalence checking and logic synthesis of circuits with a common specification
The G 4 -FET: a universal and programmable logic gate
N3XT Monolithic 3D Energy-Efficient Computing Systems
Models for bit-true simulation and high-level synthesis of DSP applications
A picosecond TDC architecture for multiphase PLLs
Multi-voltage low power convolvers using the polynomial residue number system
Novel interconnect modeling by using high-order compact finite difference methods
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications
New 2 Gbit/s CMOS I/O pads
A CMOS Low Power 4 th -Order Delta-Sigma Modulator with One Reconfigurable Amplifier
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh
A simple method for noise tolerance characterization of digital circuits
DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital Circuits
ParaHDC: Leveraging GPU Acceleration for Scalable Hyperdimensional Learning
GeckOpt: LLM System Efficiency via Intent-Based Tool Selection
A coefficient optimization and architecture selection tool for SD modulators considering component non-idealities
Estimating detection probability of interconnect opens using stuck-at tests
Bus via reduction based on floorplan revising
New & improved models for SAT-based bi-decomposition
Increasing design space of the instruction queue with tag coding
Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis
A memory mapping approach based on network customization to design conflict-free parallel hardware architectures
Information storage capacity of crossbar switching networks
Low-power cache organization through selective tag translation for embedded processors with virtual memory support
Low jitter audio range PLL with ultra low power dissipation
Crosslink insertion for variation-driven clock network construction
Test application time reduction for scan based sequential circuits
An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique
BLADE: A BitLine Accelerator for Devices on the Edge
VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection
Maximum effective distance of on-chip decoupling capacitors in power distribution grids
Combining wire swapping and spacing for low-power deep-submicron buses
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor
Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement
PUFchain 4.0: Integrating PUF-based TPM in Distributed Ledger for Security-by-Design of IoT
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time
A Hybrid Synthesis Methodology for Approximate Circuits
Reversible synthesis of symmetric boolean functions based on unate decomposition
Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages
A low-power all-digital GFSK demodulator with robust clock data recovery
Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support
LEAD: Logarithmic Exponent Approximate Divider For Image Quantization Application
Low-Cost Wearable Edge-AI Device for Diabetes Management
A Dictionary Machine Emulation on a VLSI Computing Tree System
Challenges for non-volatile memory & logic manufacturing utilizing magnetic tunnel junction on 300 mm wafer
Accelerating Deterministic Stochastic Computing with Context-Aware Bit-stream Generator
Research and development for seamless mobility
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Robust Sparse Regularization: Defending Adversarial Attacks Via Regularized Sparse Network
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion
A new conflict resolving switchbox router
Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCs
Technology mapping algorithms for sequential circuits using look-up table based FPGAS
Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems
A Combined Interval and Floating Point Multiplier
DA-GC: A Dynamic Adjustment Garbage Collection Method Considering Wear-leveling for SSD
Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs
Mapping tensor products onto VLSI networks with reduced I/O
Bitwise Neural Network Acceleration Using Silicon Photonics
Communication-aware Partitioning for Energy Optimization of Large FPGA Designs
On Test Generation with A Limited Number of Tests
Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance Computing
Reconfigurable Mapping Algorithm based Stuck-At-Fault Mitigation in Neuromorphic Computing Systems
Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices
Co-Exploration of Graph Neural Network and Network-on-Chip Design Using AutoML
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement
A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation
Adversarial Attack Mitigation Approaches Using RRAM-Neuromorphic Architectures
Proving finite state machines correct with an automaton-based method
A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs
FPGA-based high performance page layout segmentation
A design methodology for the automatic sizing of standard-cell libraries
An Air Force Perspective on the Application of Machine Learning for Microelectronics Design and Security
Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis
Security Challenges Toward In-Sensor Computing Systems
FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games
WriteSmoothing: improving lifetime of non-volatile caches using intra-set wear-leveling
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures
Power-efficient, reliable microprocessor architectures: modeling and design methods
Assertion-based automated functional vectors generation using constraint logic programming
Polynomial Arithmetic Using Sequential Stochastic Logic
IMAC-Sim: : A Circuit-level Simulator For In-Memory Analog Computing Architectures
Improvements for constraint solving in the systemc verification library
Mitigating static power in current-sensed interconnects
PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis
Topology impact on the room temperature performance of THz-range ballistic deflection transistors
Recursion flattening
High resolution MASH 2-2 Sigma Delta interface for capacitive accelerometers
A new extension method of retention time for memory cell on dynamic random access memory
Low-power clock distribution in a multilayer core 3d microprocessor
A Composable Glitch-Aware Delay Model
A fully integrated switched-capacitor DC-DC converter with dual output for low power application
Residue to Binary Number Converters for (2 n -1, 2 n , 2 n +1)
Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs
Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement
Provably Accurate Memory Fault Detection Method for Deep Neural Networks
Temperature-insensitive synthesis using multi-vt libraries
Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory
Efficient implementation of a complex ±1 multiplier
Statistical timing analysis of flip-flops considering codependent setup and hold times
Diagnosing multiple transition faults in the absence of timing information
An architecture design using VLSI building blocks for dynamic programming neural networks
Integrated circuits metering for piracy protection and digital rights management: an overview
Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs
Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security
An alternative algorithm for high speed multiplication and addition using growing technique
ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board
Robust Data Processing for Vector Symbolic Computing
The State of Simulation Frameworks for Evaluating Emerging LLM Accelerators
Coverage-driven automatic test generation for uml activity diagrams
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects
Constructing exact octagonal steiner minimal trees
A unified processor architecture for RISC & VLIW DSP
An Event Based Gesture Recognition System Using a Liquid State Machine Accelerator
Spatial and temporal design debug using partial MaxSAT
Macro-models for high level area and power estimation on FPGAs
A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated Systems
Density-reduction-oriented layer assignment for rectangle escape routing
Power efficient tree-based crosslinks for skew reduction
Sliding-Window Scheduling to Exploit Hybrid-Bonding-Based Accelerators for Fully Homomorphic Encryption
Distributed sensor data processing for many-cores
An efficient CPI stack counter architecture for superscalar processors
Facial Expression Recognition at the Edge: CPU vs GPU vs VPU vs TPU
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]
A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures
A P&R Co- Optimization Engine for Reducing Congestion
The Need for Declarative Properties in Digital IC Security
Energy-efficient wireless network-on-chip architecture with log-periodic on-chip antennas
RCRS: A Framework for Loop Scheduling with Limited Number of Registers
Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers
A fast clock scheduling for peak power reduction in LSI
Context-aware TLB preloading for interference reduction in embedded multi-tasked systems
Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study
Evaluation of heuristic techniques for test vector ordering
VICTOR: A three-layer over-the-cell router
High level energy modeling of controller logic in data caches
Forward-scaling, serially equivalent parallelism for FPGA placement
Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers
A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM