yusuke1997/dblp-id-title huggingface dataset:
Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors
Experimental Polyprocessor System (EPOS) - Operating System
Building Quantum Wires: The Long and the Short of It
uBrain: a unary brain computer interface
Asymmetry-Aware Work-Stealing Runtimes
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Simulation Experiments on a Tree Organized Minicomputer
The Impact of Synchronization and Granularity on Parallel Systems
A Pipelined Processing Unit for On-Line Division
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability
Active Pages: A Computation Model for Intelligent Memory
Selection Schemes for Dynamically Microcoding Fortran Programs
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias
Boosting Beyond Static Scheduling in a Superscalar Processor
Measuring Experimental Error in Microprocessor Simulation
Characteristics of Performance-Optimal Multi-Level Cache Hierarchies
Complexity-Effective Superscalar Processors
Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom
HLL architectures: Pitfalls and predilections
REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute
A fault tolerant, area efficient architecture for Shor's factoring algorithm
Drowsy Caches: Simple Techniques for Reducing Leakage Power
Do-It-Yourself Virtual Memory Translation
A scalable processing-in-memory accelerator for parallel graph processing
MnnFast: a fast and scalable system architecture for memory-augmented neural networks
Intel® Software Guard Extensions (Intel® SGX) Software Support for Dynamic Memory Allocation inside an Enclave
Architecture of a Massively Parallel Processor
A System Architecture for the Concurrent Evaluation of Applicative Program Expressions
Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering
Parallel electro-optical rule-based system for fast execution of expert systems
S-SYNC: Shuttle and Swap Co-Optimization in Quantum Charge-Coupled Devices
Deconstructing Commodity Storage Clusters
Scalable interconnects for reconfigurable spatial architectures
Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers
Instruction Level Profiling and Evaluation of the IBM/6000
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
Connection Principles for Multipath Packet Switching Networks
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Genesis: A Compiler for Hamiltonian Simulation on Hybrid CV-DV Quantum Computers
A Versatile Systolic Array for Matrix Computations
The Performance Analysis of Partitioned Circuit Switched Multistage Interconnection Networks
Cache Evaluation and the Impact of Workload Choice
On the semantic structure of information - A proposal of the abstract storage architecture
FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
A Performance Comparison of Contemporary DRAM Architectures
Single Spike Artificial Neural Networks
Microarchitecture of a High-Radix Router
Designing Calibration and Expressivity-Efficient Instruction Sets for Quantum Computing
AccQOC: Accelerating Quantum Optimal Control Based Pulse Generation
AutoPilot: message passing parallel programming for a cache incoherent embedded manycore processor
Late-binding: enabling unordered load-store queues
HASP 2013, The Second Workshop on Hardware and Architectural Support for Security and Privacy, Tel-Aviv, Israel, June 23-24, 2013
Path Building in Cellular Partitioning Networks
Architecture of a Message-Driven Processor
Combined Performance Gains of Simple Cache Protocol Extensions
On the Relevance of Architectural Awareness for Efficient Fork/Join Support on Cluster-Based Manycores
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design
Revisiting hardware-assisted page walks for virtualized systems
Probable cause: the deanonymizing effects of approximate DRAM
The DASH Prototype: Implementation and Performance
Benefits and limitations of tapping into stored energy for datacenters
DeepAttest: an end-to-end attestation framework for deep neural networks
MoPAC: Efficiently Mitigating Rowhammer with Probabilistic Activation Counting
Multi-Threaded Vectorization
Alternative Implementations of Two-Level Adaptive Branch Prediction
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product
Skewed Associativity Enhances Performance Predictability
Modeling Program Predictability
INSPIRE: in-storage private information retrieval via protocol and architecture co-design
A case for heterogeneous on-chip interconnects for CMPs
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, IL, USA, April 1994
A Tree Based Router Search Engine Architecture with Single Port Memories
A Pragmatic View of Distributed Processing Systems
MetaNMP: Leveraging Cartesian-Like Product to Accelerate HGNNs with Near-Memory Processing
Multiple clone row DRAM: a low latency and area optimized DRAM
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs
SODA: A Low-power Architecture For Software Radio
Packet Switching in Banyan Networks
Opportunistic Transient-Fault Detection
sNPU: Trusted Execution Environments on Integrated NPUs
A Distributed Function Computer for Real-Time Control
System Design of a Grammar-Programmable High-Level Language Machine
Can traditional programming bridge the Ninja performance gap for parallel computing applications?
SMTp: An Architecture for Next-generation Scalable Multi-threading
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore
Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio
PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer
Tempest and Typhoon: User-Level Shared Memory
The Architecture of an ALGOL 60 Computer Implemented with Distributed Processors
Experiences with VI Communication for Database Storage
GenAx: A Genome Sequencing Accelerator
Analysis of Bus Hierarchies for Multiprocessors
The Impact of Code Density on Instruction Cache Performance
Warp Architecture and Implementation
A first-order mechanistic model for architectural vulnerability factor
The BlackWidow High-Radix Clos Network
The Honeywell Modular Microprogram Machine: M3
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Hardware Acceleration of Neural Graphics
Towards more hardware-friendly deep learning
HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality
A Data Flow Processor Array System: Design and Analysis
The Impact of Unresolved Branches on Branch Prediction Scheme Performance
Fast Prolog with an Extended General Purpose Architecture
Dynamic global adaptive routing in high-radix networks
Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA
PipeRench: A Coprocessor for Streaming multimedia Acceleration
A variable warp size architecture
TVARAK: Software-Managed Hardware Offload for Redundancy in Direct-Access NVM Storage
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
A case for core-assisted bottleneck acceleration in GPUs: enabling flexible data compression with assist warps
The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow
HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols
High-Bandwidth Address Translation for Multiple-Issue Processors
Structure of Digital System Description Languages
Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240
Energy Optimization of Subthreshold-Voltage Sensor Network Processors
A Taxonomy of Display Processors
The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013
Odd Memory Systems May be Quite Interesting
High Level Language Oriented Hardware and the Post-Von Neumann Era
A Hardware Support Mechanism for Scheduling Resources in a Parallel Machine Environment
Architecture of a graphics processor
The dynamic granularity memory system
Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: A Case Study on Shared-Memory Multiprocessor
Stored Data Structures on the Manchester Dataflow Machine
Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989
FATE: Boosting the Performance of Hyper-Dimensional Computing Intelligence with Flexible Numerical DAta TypE
Stream-based memory access specialization for general purpose processors
HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing
Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers
Retrospective: Evaluation of Directory Dchemes for Cache Coherence
A class of prefetch schemes for on-chip data caches
Position Paper: Progressive Memory Safety for WebAssembly
Transactional Memory Coherence and Consistency
A reconfigurable fabric for accelerating large-scale datacenter services
Concepts of the MATHILDA System
MITTS: Memory Inter-arrival Time Traffic Shaping
Dynamic Dependency Analysis of Ordinary Programs
Overview of the ARCADE System
Sampling + DMR: practical and low-overhead permanent fault detection
AT2=O(N log4 N), T=O(log N) Fast Fourier Transform in a Light Connected 3-Dimensional VLSI
A case for an interleaving constrained shared-memory multi-processor
Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors
iWatcher: Efficient Architectural Support for Software Debugging
Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2019, June 23, 2019
Single Instruction Stream Parallelism is Greater Than Two
The de Bruijn Multiprocessor Network: A Versatile Sorting Network
High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs Industrial Product
Parallel Automata Processor
Decoupled Access/Execute Computer Architectures
Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes
DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory
Tradeoffs in Supporting Two Page Sizes
Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
Triad-NVM: persistency for integrity-protected and encrypted non-volatile memories
Insights into DeepSeek-V3: Scaling Challenges and Reflections on Hardware for AI Architectures
The Turn Model for Adaptive Routing
Bosehedral: Compiler Optimization for Bosonic Quantum Computing
A Performance Study of Software and Hardware Data Prefetching Schemes
Flagship: A Parallel Architecture for Declarative Programming
Practical Memory Safety with REST
The Architecture of CASSM: A Cellular System for Non-numeric Processing
Analysis of Multiprocessor Cache Organizations with Alternative Main Memory Update Policies
Transparent control independence (TCI)
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
A Large Scale, Homogeneous, Fully Distributed Parallel Machine, II
Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation
A Vector and Array Multiprocessor Extension of the Sylvan Architecture
BulkSC: bulk enforcement of sequential consistency
Mitigating Wordline Crosstalk Using Adaptive Trees of Counters
Measurement and analysis of instruction use in the VAX-11/780
Core fusion: accommodating software diversity in chip multiprocessors
Dynamic prediction of architectural vulnerability from microarchitectural state
CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process
Energy Efficiency Boost in the AI-Infused POWER10 Processor
V10: Hardware-Assisted NPU Multi-tenancy for Improved Resource Utilization and Fairness
Overcoming the Limitations of Conventional Vector Processors
ALPHA: A High-Performance LISP Machine Equipped with a New Stack Structure and Garbage Collection System
Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads
NASGuard: A Novel Accelerator Architecture for Robust Neural Architecture Search (NAS) Networks
Non-race concurrency bug detection through order-sensitive critical sections
Unraveling timewarp: what all the fuzz is about?
Aquacore: a programmable architecture for microfluidics
Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?
On the Performance of Loosely Coupled Multiprocessors
An Architecture for Efficient Lisp List Access
Reduction of Memory Interference in Multiprocessor Systems
Indirect adaptive routing on large scale interconnection networks
On the Inclusion Properties for Multi-Level Cache Hierarchies
NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator
A Large Scale, Homogeneous, Fully Distributed Parallel Machine, I
Retrospective: Banyan Networks for Partitioning Multiprocessor Systems
Performance analysis of the Alpha 21264-based Compaq ES40 system
ACT: designing sustainable computer systems with an architectural carbon modeling tool
Simultaneous Subordinate Microthreading (SSMT)
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
A RISC-V in-network accelerator for flexible high-performance low-power packet processing
The MIT Alewife Machine: Architecture and Performance
Phase Tracking and Prediction
Techniques for Multicore Thermal Management: Classification and New Exploration
Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks
Pipeline Gating: Speculation Control for Energy Reduction
A Comparison Connection Assignment for Diagnosis of Multiprocessor Systems
Rotating Memory Processors for the Matching of Complex Textual Patterns
Store Buffer Design in First-Level Multibanked Data Caches
Synchronization with Multiprocessor Caches
Virtual hierarchies to support server consolidation
NvMR: non-volatile memory renaming for intermittent computing
A Concurrent Computer Architecture and a Ring Based Implementation
Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results
The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-D
Guarded Power Gating in a Multi-core Setting
Learning to co-design
Task Migration in Hypercube Multiprocessors
The Difference-bit Cache
ScoRD: A Scoped Race Detector for GPUs
*T: A Multithreaded Massively Parallel Architecture
The SNAP-1 Parallel AI Prototype
25 Years of the International Symposia on Computer Architecture (Selected Papers)
Models for Use in the Design of Macro-Pipelined Parallel Processors
The rebirth of neural networks
DyLeCT: Achieving Huge-page-like Translation Performance for Hardware-compressed Memory
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation
The Jrpm System for Dynamically Parallelizing Java Programs
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication
FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2015 in conjunction with the 42nd International Symposium on Computer Architecture (ISCA'2015), Portland, OR, USA
Improving memory scheduling via processor-side load criticality information
Compact Leakage-Free Support for Integrity and Reliability
A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor
Microcoded Architectures for Ion-Tap Quantum Computers
QR-Map: A Map-Based Approach to Quantum Circuit Abstraction for Qubit Reuse Optimization
Design of a High-speed Prolog Machine (HPM)
Parallelism in the Front-End
ArchRanker: A ranking approach to design space exploration
Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion
Evaluation of Memory System Extensions
FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response
A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization
Proceedings of the 52nd Annual International Symposium on Computer Architecture, ISCA 2025, Tokyo, Japan, June 21-25, 2025
Strategies for Achieving Improved Processor Throughput
Firefly: illuminating future network-on-chip with nanophotonics
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms
FaultHound: value-locality-based soft-fault tolerance
Futurebus+ as an I/O Bus: Profile B
Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product
Rigel: an architecture and scalable programming interface for a 1000-core accelerator
OneQ: A Compilation Framework for Photonic One-Way Quantum Computation
Increasing TLB Reach Using Superpages Backed by Shadow Memory
The Performance Impact of Block Sizes and Fetch Strategies
Poly-Processor System Analysis and Design
Implicit Sensor-based Authentication of Smartphone Users with Smartwatch
WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses
The NEBULA RPC-Optimized Architecture
Transitive Array: An Efficient GEMM Accelerator with Result Reuse
A Type Driven Hardware Engine for Prolog Clause Retrieval over a Large Knowledge Base
Performance Analysis and Design of a Logic Simulation Machine
TEA: Time-Proportional Event Analysis
Mechanisms for Cooperative Shared Memory
NISQ+: Boosting quantum computing power by approximating quantum error correction
RoboX: An End-to-End Solution to Accelerate Autonomous Control in Robotics
Hi-fi playback: tolerating position errors in shift operations of racetrack memory
Reliable Synchronization of Redundant Systems
Callback: efficient synchronization without invalidation with a directory just for spin-waiting
Switching Strategies in a Class of Packet Switching Networks
DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference
Banyan Networks for Partitioning Multiprocessor Systems
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis
Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
RENO - A Rename-Based Instruction Optimizer
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory
Modular Matrix Multiplication on a Linear Array
29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA
Towards fast hardware memory integrity checking with skewed Merkle trees
SC 2 : A statistical compression cache scheme
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes
An Analysis of the Cray-1 Computer
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability
Architecting Noisy Intermediate-Scale Trapped Ion Quantum Computers
TPShare: a time-space sharing scheduling abstraction for shared cloud via vertical labels
Heliostat: Harnessing Ray Tracing Accelerators for Page Table Walks
Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996
DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration
OO-VR: NUMA friendly object-oriented VR rendering framework for future NUMA-based multi-GPU systems
High Performance Interprocessor Communication through Optical Wavelength Division Multiple Access Channels
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Intelligent Magnetic Bubble Memories
Modeling the Performance of Limited Pointers Directories for Cache Coherence
Microprogrammed Architecture for Front End Processing
LightPC: hardware and software co-design for energy-efficient full system persistence
Zombie memory: extending memory lifetime by reviving dead blocks
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes
Shogun: A Task Scheduling Framework for Graph Mining Accelerators
Statistical assertions for validating patterns and finding bugs in quantum programs
MP/C: A Multiprocessor/Computer Architecture
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Fault-tolerant wafer-scale architectures for VLSI
Memory Ordering: A Value-Based Approach
Dynamic Speculation and Synchronization of Data Dependences
Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation
Resource Analysis of Low-Overhead Transversal Architectures for Reconfigurable Atom Arrays
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
Rapid detection of rowhammer attacks using dynamic skewed hash tree
A Cache Coherence Scheme With Fast Selective Invalidation
Traffic Analysis of Rectangular SW-Banyan Networks
9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982
Resilient die-stacked DRAM caches
HiPER: Hierarchically-Composed Processing for Efficient Robot Learning-Based Control
Proceedings of the 50th Annual International Symposium on Computer Architecture, ISCA 2023, Orlando, FL, USA, June 17-21, 2023
The PDP-11: A Case Study of How Not to Design Condition Codes
ETTE: Efficient Tensor-Train-based Computing Engine for Deep Neural Networks
System/370 Extended Architecture: A Program View of the Channel Subsystem
Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
Resource Requirements of Dataflow Programs
On the Effectiveness of Buffered and Multiple Arm Disks
Expanded delta networks for very large parallel computers
Instruction Design To Minimize Program Size
Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their Impact
A Processor for a High-Performance Personal Computer
A Multimicroprocessor Approach to Numerical Analysis: An Application to Gaming Problems
Low Load Latency Through Sum-Addressed Memory (SAM)
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
The Synapse N+1 System: Architectural Characteristics and Performance Data of a Tightly-Coupled Multiprocessor System
EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching
The Performance of Cache-Coherent Ring-based Multiprocessors
Examining ACE analysis reliability estimates using fault-injection
ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity
Data Structure Architectures - A Major Operational Principle
Instruction path coprocessors
The Design and Evaluation of the Array Machine: A High-Level Language Processor
Detecting Global Stride Locality in Value Streams
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy
Hiding the Long Latency of Persist Barriers Using Speculative Execution
Base-Victim Compression: An Opportunistic Cache Compression Architecture
Fusion: design tradeoffs in coherent cache hierarchies for accelerators
Design and Evaluation of Hybrid Fault-Detection Systems