yusuke1997/dblp-id-title huggingface dataset:
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems
PowerYOLO: Mixed Precision Model for Hardware Efficient Object Detection with Event Data
C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell
Low Power Encoding in NoCs Based on Coupling Transition Avoidance
Real-Time Digital Video Stabilization on an FPGA
Memory Aware Packet Matching Architecture for High-Speed Networks
A hardware architecture for Multiscale Retinex with Chromacity Preservation on an FPGA
PhysioEdge: Multimodal Compressive Sensing Platform for Wearable Health Monitoring
On the Design of a Processor Working Over Encrypted Data
Designing a Synthetic Aperture Radar's Data Formatting and Antenna Gyro Stabilizing Module
Enhanced Reusability for SoC-Based HW/SW Co-Design
A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism
How Primitive but How Effective: Fault-Injection Attack on Cryptographic Accelerator of Microchip CEC 1702 Microcontroller
Dynamic Branch Prediction Using Neural Networks
Hardware-Secured Configuration and Two-Layer Attestation Architecture for Smart Sensors
X25519 Hardware Implementation for Low-Latency Applications
ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic
Unified Dual Data Caches
Verifying Liveness and Real-Time of OS-Based Embedded Software
Exploration of Network Alternatives for Middleware-centric Embedded System Design
Application Study of Hardware-Based Security for Future Industrial IoT
Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective
A Power-Aware Technique for Functional Units in High-Performance Processors
Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs
SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems
On network-on-chip comparison
Two Architectures of a General Digit-Serial Normal Basis Multiplier
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
Design Optimization of Cyber-Physical Systems by Partitioning and Coordination: A Study on Mechatronic Systems
Pulsed ElectroMagnetic Fault Injection Attack on a Time Measurement-based Arbiter-PUF
Adaptive Power Management for the On-Chip Communication Network
Low Complexity Background Subtraction for Wireless Vision Sensor Node
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA
Lab on Chip: Portable Optical Device for On-site Multi-parametric Analysis
Safe Drive Map Concept for Road Curve Monitoring
Side-channel analysis of Chacha20 implemented in software
KETCube - The Universal Prototyping IoT Platform
Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations
Development and Validation of a Low-Cost LEDbased Multispectral Imaging System
Design Without Borders
Container Scheduling Under ARINC 653 Scheduler Constraints
Cyber-Physical Systems Design for Electric Vehicles
Voltage Spikes on the Substrate to Obtain Timing Faults
Acceleration of Smith-Waterman using Recursive Variable Expansion
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs
CAPE - European Open Compute Architecture for Powerful Edge
Is the Whole lesser than its Parts? Breaking an Aggregation based Privacy aware Metering Algorithm
A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs
Teaching Agile Hardware Design with Chisel
Improving the Efficiency of Transformers for Resource-Constrained Devices
Parameterizable Ethernet Network-on-Chip Architecture on FPGA
FPGA Based Real-Time Tracking Approach with Validation of Precision and Performance
Secure and dependable: Area-efficient masked and fault-tolerant architectures
NMPO: Near-Memory Computing Profiling and Offloading
Leveraging the Analysis for Invariant Independence in Formal System Models
Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor Platform
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification
Evaluation of Time Series Clustering on Embedded Sensor Platform
Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures
A Reliable MAC for Energy-Efficient WSNs in the Era of IoT
On the Use of Mutations in Boolean Minimization
Enabling Cognitive Autonomy on Small Drones by Efficient On-Board Embedded Computing: An ORB-SLAM2 Case Study
An Efficient Exponential Algorithm with Exponential Convergence Rate
MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities
Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany
Multiobjective Optimization of Cost, Performance and Thermal Reliability in 3DICs
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs
Evaluation of Hyperspectral Imaging Fusion for in-vivo Brain Tumor Identification and Delineation
A Framework for Evaluating Connected Vehicle Security against False Data Injection Attacks
Integrated Mapping and Scheduling Optimization with Genetic Algorithms Based on a Novel Encoding Scheme
Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland
Non-Homogeneous Continuous Time Markov Chains Calculations
System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments
Vision-Based Multi-Size Object Positioning
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs
An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern
TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities
A Scalable Cloud Computing Infrastructure for Geospatial Data Analytics for Change Detection
Electromagnetic Analysis on RSA Algorithm Based on RNS
Evaluating Cryptographic Extensions On A RISC-V Simulation Environment
A Multi-Channel Threshold-Based Seizure Detection Algorithm for Low-Complexity Hardware Implementation
RL-ALMS: Reinforcement Learning-based Adaptive and Lightweight Model Selection Framework for Energy-Efficient Lane Detection in Electric Vehicles
Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design
D-AWSIM: Distributed Autonomous Driving Simulator for Dynamic Map Generation Framework
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems
Towards an Efficient NoC Topology through Multiple Injection Ports
An Improved Hardware Implementation of the Grain Stream Cipher
An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems
The EMC2 Project on Embedded Microcontrollers: Technical Progress after Two Years
Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency Reduction
Vulnerability Analysis for Custom Instructions
Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring
Novel Approach for AI-Based Risk Calculator Development Using Transfer Learning Suitable for Embedded Systems
How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis
Nexus: Hardware Support for Task-Based Programming
Novel Modulo 2 n + 1 Multipliers
CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management
A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack Machines
Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers
A Proposal of New Join Operators for Sensor Network Databases
Simulation Alternatives for Modeling Networked Cyber-Physical Systems
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications
A Framework for Dynamic Real-Time Reconfiguration
Generation of Verified Programs for In-Memory Computing
A Static Analysis Approach for Verification of Synchronization Correctness of SystemC Designs
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path
Model Based Design of FMCW Radar Processing Systems on FPGA Platforms
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder
AEx: Automated Customization of Exposed Datapath Soft-Cores
Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project
A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors
Very High (Over 40 Gb/s) Speed Circuits for Optical Communications - Design Methodolgy and Application Examples
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis
ComCoS: Enhanced Cache Partitioning Technique for Integrated Modular Avionics
Morphone.OS: Context-Awareness in Everyday Life
Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract)
CaW-NAS: Compression Aware Neural Architecture Search
Design and Validation of Digital Channels for a Galileo Receiver Prototype
On-Chip Verification of NoCs Using Assertion Processors
Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?
Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets
DRedSOP: Synthesis of a New Class of Regular Functions
Transient Fault Tolerant QDI Interconnects Using Redundant Check Code
Energy-Efficient Use of an Embedded Heterogeneous SoC for the Inference of CNNs
On Failure Rate Assessment Using an Executable Model of the System
Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip
The Seat Adaptation System of REFLECT Project: Implementation of a Biocybernetic Loop in an Automotive Environment
Improved Fault Emulation for Synchronous Sequential Circuits
Multiple Voltage and Frequency Scheduling for Power Minimization
A Locality Aware Convolutional Neural Networks Accelerator
Enabling Unit Testing of Already-Integrated AI Software Systems: The Case of Apollo for Autonomous Driving
DYNORA: A New Caching Technique
Soft Error Analysis on Communication Channels in On-Chip Communication Networks
Towards a More Flexible IoT SAFE Implementation
Trusted SMEs for Sustainable Growth of Europeans Economical Backbone to Strengthen the Digital Sovereignty: The KDT Resilient Trust Project
High Performance Bitwise OR Based Submesh Allocation for 2D Mesh-Connected CMPs
Using Formal Tools to Study Complex Circuits Behaviour
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
WirelessUSB - Performance Analysis of an Embedded System in a Peer-to-Peer Application
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Design of Transport Triggered Architecture Processors for Wireless Encryption
Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication
Unum: Adaptive Floating-Point Arithmetic
Investigation of Commercial Off-The-Shelf ReRAM Modules for Use as Runtime-Accessible TRNG
High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming
Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs
A Simple Micro-Threaded Data-Driven Processor
Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions
A Distributed Feedback Control Mechanism for Quality-of-Service Maintenance in Wireless Sensor Networks
A Majority-Based Reliability-Aware Task-Mapping in High-Performance Homogenous NoC Architectures
The METASAT Modelling and Code Generation Toolchain for XtratuM and Hardware Accelerators
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC
A Low-Cost Cache Coherence Verification Method for Snooping Systems
Internet-Router Buffered Crossbars Based on Networks on Chip
Buffer Sizes Reduction for Memory-efficient CNN Inference on Mobile and Embedded Devices
Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores
Wind Energy Harvesting for Autonomous Wireless Sensor Networks
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
VPSA: A Vectored Processing Element configured Systolic Array Architecture Generator
High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based Computation
The LoLiPoP-IoT Project: Long Life Power Platforms for Internet of Things
TOT-Net: An Endeavor Toward Optimizing Ternary Neural Networks
Capturing Processor Architectures from Protocol Processing Applications: a Case Study
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
A Markov Model for Low-Power High-Fidelity Design-Space Exploration
A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip
AxE: An Approximate-Exact Multi-Processor System-on-Chip Platform
Analysis of Modern Memory Management Unit Functioning for Critical Systems
A Structured Approach to Verification of Digital Hardware in Scala
High Speed Implementation of the Deformable Shape Tracking Face Alignment Algorithm
Integrated Design and Test Generation Under Internet Based Environment MOSCITO
A resolution method in case of air congestion: rerouting and/or ground holding approach
A Graph Based Algorithm for Data Path Optimization in Custom Processors
Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves
Networks on Silicon: Blessing or Nightmare?
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes
Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays
FPGA PUF Based on Programmable LUT Delays
RAPIDITAS: RAPId Design-Space-Exploration Incorporating Trace-Based Analysis and Simulation
Network Interface Sharing Techniques for Area Optimized NoC Architectures
A Heuristic for Wiring-Aware Built-In Self-Test Synthesis
Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip
Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures
Latency Minimization for Synchronous Data Flow Graphs
Streamlined Models of CMOS Image Sensors Carbon Impacts
Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations
Open Problems in Verification and Refinement of Autonomous Robotic Systems
Laser-Induced Fault Simulation
Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3
Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications
On Analyzing Memory Latency for Embedded CPS Platforms
Simulation of High-Performance Memory Allocators
A Mixed Language Fault Simulation of VHDL and SystemC
A Heuristic for Variable Re-Entrant Scheduling Problems
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers
A Complete Methodology for Memory Optimization in DSP Applications
Efficient MLP Digital Implementation on FPGA
Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor Networks
Optimisation of PPMC Model for Hardware Implementation
Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder
Embedded Diagnostic Logic Test Exploiting Regularity
Network on Privacy-Aware Audio-and Video-Based Applications for Active and Assisted Living: GoodBrother Project
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder
Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation
A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform
Optimizing Lattice-based Post-Quantum Cryptography Codes for High-Level Synthesis
Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
Information Coding and Hardware Architecture of Spiking Neural Networks
DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
A RISC Processor with Redundant LNS Instructions
Ultra-Small Designs for Inversion-Based S-Boxes
Scenario Patterns and Trace-Based Temporal Verification of Reactive Embedded Systems
Hardware Reuse in Modern Application-Specific Processors and Accelerators
Going to the Edge - Bringing Internet of Things and Artificial Intelligence Together
Leveraging Design Static Analysis for Vertical Reuse in Functional Verification
FPGA/DSP-based Configurable Multi-Channel Counter
Analytical Bounds on the Threads in IXP1200 Network Processor
High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output
SEMIAH: An Aggregator Framework for European Demand Response Programs
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder
Generating Efficient Parallel Code from the RVC-CAL Dataflow Language
A DRAM Precharge Policy Based on Address Analysis
Dynamic Split: Flexible Border Between Instruction and Data Cache
A Distributed Arithmetic Online Rotator for Signal Processing Applications
Hardware Design Space Exploration with a New Dimension - IP Protection Robustness
Scan Based Tests via Standard Interfaces
Logic Transformations by Multiple Wire Network Addition
An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs
Improving Single-Thread Fetch Performance on a Multithreaded Processor
Optimization of CCOs with Implantable MEMS Pressure Sensors for Cardiovascular Applications
AIDA4Edge: Twinning for Excellence in Adaptive Edge Artificial Intelligence
Technology Library Modelling for Information-driven Circuit Synthesis
Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space Exploration
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
Iterative Algorithm for Compound Instruction Selection with Register Coalescing
FPGA-based Neural Network for Nonuniformity Correction on Infrared Focal Plane Arrays
Co-simulation Framework for Control, Communication and Traffic for Vehicle Platoons
Cost-Efficient Implementation of Adaptive Finite State Machines
A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning
Thermal Sensor Based Hardware Trojan Detection in FPGAs
Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures
Probing Approximate TMR in Error Resilient Applications for Better Design Tradeoffs
Breaking (and Fixing) Channel-based Cryptographic Key Generation: A Machine Learning Approach
Towards a Mobile Health Platform with Parallel Processing and Multi-sensor Capabilities
Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+
Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation
An Hardware Recurrent Neural Network for Wearable Devices
Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition Systems
A Physical-Aware Abstraction Flow for Efficient Design-Space Exploration of a Wireless Body Area Network Application
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA
A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures
An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-Chip
Reliability of Task Execution During Safe Software Processing
Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems
Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model
Improving mW/MHz Ratio in FPGAs Pipelined Designs
FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
Pipeline-Level Control of Self-Resetting Pipelines
Precision and Power Efficient Piece-Wise-Linear Implementation of Transcendental Functions
An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs
Re-NUCA: Boosting CMP Performance Through Block Replication
A Fast Additive Normalization Method for Exponential Computation
A Boolean Heuristic for Disjoint SOP Synthesis
A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA
An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDAR
Setup for an Experimental Study of Radiation Effects in 65nm CMOS
SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Minimization Method of Finite State Machines for Low Power Design
SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks
Breaking Hitag2 with Reconfigurable Hardware
IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis
High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC
FPGA Placement Improvement Using a Genetic Algorithm and the Routing Algorithm as a Cost Function
Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks
A New Rounding Algorithm for Variable Latency Division and Square Root Implementations
Addressing architecture for Brain-like Massively Parallel Computers
Packetizing OCP Transactions in the MANGO Network-on-Chip
12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece
Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing
Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications
Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 Processor
ARROW - A Generic Hardware Fault Injection Tool for NoCs
A Wireless Interconnection Network for Parallel Processing
Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software
On-Package Scalability of RF and Inductive Memory Controllers
Generation of Structural VHDL Code with Library Components from Formal Event-B Models
FPGA Accelerator for RNA Secondary Structure Prediction
Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?
Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds
Exploration of Slot Allocation for On-Chip TDM Virtual Circuits
Self-Checking Carry Select Adder with Fault Localization
Building a Side-Channel Attack Scheme on SipHash FPGA Implementation
Noodle: A Heuristic Algorithm for Task Scheduling in MPSoC Architectures
You Shall Not Stall: Achieving RISC-V On-Demand Runtime-Reconfiguration using SCAIE-V
Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
Rapid Prototyping of Mixed Hardware and Software Systems
Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud
Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations
FPGA Implementation of Addition as a Part of the Convolution