yusuke1997/dblp-id-title huggingface dataset:
IO Clock Network Skew & Performance Analysis: A Pentium-D Case Study
Session 24-Milimeter-wave communication circuits
Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor array
3D multi-gesture sensing system for large areas based on pixel self-capacitance readout using TFT scanning and frequency-conversion circuits
A high voltage Dickson charge pump in SOI CMOS
An 85MHz-BW 68.5dB-SNDR ASAR-assisted CT 4-0 MASH ΔΣ modulator with half-range dithering-based DAC calibration in 28nm CMOS
Model topology formulation for nonlinear dynamic behavioral modeling
Biomedical and sensors
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor
Artificially Intelligent Closed-Loop Neurostimulators: Trade-Offs between Local and Remote Computing
Stacked inductors and 1-to-2 transformers in CMOS technology
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS
A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS
Integrated-Circuit Node for Time-Domain Near-infrared Diffuse Optical Tomography Imaging Arrays with On-chip Histogramming and Integrated VCSELs
MEMS wafer-level vacuum packaging with transverse interconnects for CMOS integration
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops
Design of a monolithic CMOS image sensor integrated focal plane wire-grid polarizer filter mosaic
A Fully In-Package 4-Phase Fixed-Frequency DAB Hysteretic Controlled DC-DC Converter with Enhanced Efficiency, Load Regulation and Transient Response
1 GHz programmable analog phase shifter for adaptive antennas
VLSI implementation of a realtime wavelet video coder
Noise analysis methodology for partially depleted SOI circuits
Three stage amplifier with positive feedback compensation scheme
An Inductor-First Hybrid Buck-Boost Converter Featuring Seamless Single-Mode Operation, 97.2% Peak Efficiency, and 565mAlmm 3 Current Density with Ultra-Compact 1 mm 3 -Volume Inductor
A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs
A 200-MHz continuous-time CMOS delta-sigma modulator featuring nonlinear feedback control
A 6µW ECG-Recording ΔΣ Modulator with Internal-Capacitor-Flipping Technique for 34Vpp Common-Mode-Interference (CMI) Tolerance and 1Vpp Input Range
Efficient Frequency-Domain Simulation of Massive Clock Meshes Using Parallel Harmonic Balance
Session 2 - Wireline techniques for advanced modulation schemes
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration
Obtaining Frequency Sensitivities to Variations Analytically from Parameterized Nonlinear Oscillator Phase Macromodels
Mixed-Signal Electrical Interfaces
A BiCMOS preamplifier/write-driver IC for tape drive
Nanoscale power and performance optimizations
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics
Interconnect in the Era of 3DIC
A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB
A 1.6Gbps Digital Clock and Data Recovery Circuit
A low-power CMOS super-regenerative receiver at 1 GHz
From pistons and gears to electronics and software: The coming transportation technology disruption
Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter
A 20.1-μW 1.8 -GHz Near-Field Dielectric Plethysmography (NF-DPG) Heart-Rate Sensor with Time-based Edge Sampling
A low power high spectral purity frequency translational loop for wireless applications
Substrate and phase noise characterization
A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile Terminals
Digital signal processing in read channels
A fully integrated highly linear receiver with automatic IP2 calibration schemes for multi-standard applications
A Multi-Standard Low Power 1.5-3.125 Gb/s Serial Transceiver in 90nm CMOS
A novel readout IC with high noise immunity for charge-based touch screen panels
A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR
Electric power generation using piezoelectric resonator for power-free sensor node
Design and modeling challenges for 90 NM and 50 NM
A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm 2 / Channel by Noise-Orthogonalizing and Pad-Sharing Techniques
A 3.9kHz bandwidth and 2μV offset current sensor analog front-end with a capacitively coupled amplifier using a dual frequency conversion technique
A 52-67GHz Ultra-Compact Bi-directional Gate-switching Cascode Amplifier with Tri-coil Broadband Matching in 40-nm CMOS
An 84dB-SNDR 1-0 Quasi-MASH NS SAR with LSB Repeating and 12-bit Bridge-Crossing Segmented CDAC
An overview of automated macromodelling techniques for mixed-signal systems
Design for manufacturability characterization and optimization of mixed-signal IP
A calibrated pathfinding model for signal integrity analysis on interposer
A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop
A 2.4GHz mixed-signal polar power amplifier with low-power integrated filtering in 65nm CMOS
Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator
IEEE Custom Integrated Circuits Conference, CICC 2025, Boston, MA, USA, April 13-17, 2025
A retinal prosthesis device based on an 80×40 hybrid microelectronic-microwire glass array
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations
Testability and reliability enhancement techniques
A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications
A noise circulating cross-coupled VCO with a 195.6dBc/Hz FoM and 50kHz 1/f 3 noise corner
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application
Paths to terahertz CMOS integrated circuits
A dual-channel QAM/QPSK receiver IC with integrated cable set-top box functionality
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer
Design solutions for 3D integration and signal integrity
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process
1.5 V 5.0 MHz switched capacitor circuits in 1.2 μm CMOS without voltage bootstrapper
A 1.58-nA CEPE-Based Hill-Climbing MPPT Technique with Compensated Ton Achieving 67.3% Efficiency at 10-nA Lload and > 97% MPPT Efficiency at VCR from 2 to 6
A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression
A 94.5%-Peak-Efficiency Dual-Path Single-Inductor Dual-Output Converter with Reduced Inductor Current and Output Voltage Ripple
A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications
Wideband Inductive-coupling Interface for High-performance Portable System
A distributed crossbar switch scheduler for on-chip networks
Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times
A 1 GHz, low-phase-noise CMOS frequency synthesizer with integrated LC VCO for wireless communications
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator
Three-dimensional impedance engineering for mixed-signal system-on-chip applications
Session 15 - Energy-efficient wireless for 5G and IoT
Silicon millimeter wave ICs, VCOs, and dividers
A High-Order-Temperature-Compensated 328kHz On Chip RC Timer Using Time-Interleaved Resistors Achieving 1.5pJ/Cycle and 5.86ppm°C
High voltage devices in advanced CMOS technologies
A 1.2-V 15-bit 2.5-MS/s oversampling ADC with reduced integrator swings
Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC
The impact of device type and sizing on phase noise mechanisms [MOS VCOs]
Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices
A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne
AI SoC Design Challenges in the Foundation Model Era
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, CICC 2002, Orlando, FL, USA, May 12-15, 2002
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines
The challenges of analog circuits on nanoscale technologies
A 325 MHz 3.3 V 10-bit CMOS D/A converter core with novel latching driver circuit
A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters
A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6
A power electronics unit to drive piezoelectric actuators for flying microrobots
Silicon radio integration: architectures and technology: from cartesian zero IF receive & transmit to polar zero I and Q, from silicon bipolar to bulk and SOI CMOS
Foundries, EDA vendors, and designers: who shoulders the blame when a design doesn't work in the nano-scale and wireless era?
A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications
Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end
Notice of Violation of IEEE Publication Principles9.953-12.5GHz 0.13μm CMOS LC VCO using a high resolution calibration and a constant gain varactor
Lithography options for the 32nm half pitch node and beyond
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS
Managing soft errors in ASICs
A deterministic scan-BIST architecture with application to field testing of high-availability systems
A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]
A Reconfigurable Potts Machine with Successive Boundary Approximation Annealing for Solving Combinatorial Optimization Problems
A study of error sources in current steering digital-to-analog converters
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL
Noise in short channel MOSFETs
Balanced CMOS LC-tank analog frequency dividers for quadrature LO generation
A 10V Compliant 16-Channel Stimulator ASIC with sub-10nA Mismatch and Simultaneous ETI Sensing for Selective Vagus Nerve Stimulation
A 0.9mm 2 SDR Receiver in 40-nm CMOS Covering 10-72GHz Using Inductor-Less Based LO Quintupler
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation
Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validation
A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry
A 0.008mm 2 2.4GHz type-I sub-sampling ring-oscillator-based phase-locked loop with a -239.7dB FoM and -64dBc reference spurs
Analysis of jitter due to power-supply noise in phase-locked loops
Three dimensional CMOS devices and integrated circuits
A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance
A low-power mixed-signal baseband system design for wireless sensor networks
Wafer-specific centering of compact transistor model parameters for advanced technologies and models
A 105dBA SNR, 0.0031% THD+N filterless class-D amplifier with discrete time feedback control in 55nm CMOS
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP
Sub-session: Data converter techniques
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area
Regular logic fabrics for a via patterned gate array (VPGA)
Efficient and reusable time-sharing architectures for equalizer structures
Broadband compact model for on-chip mm-wave transformers and baluns with emphasis on capacitive coupling effects
A dual channel IF-digitizing IC with 117dB dynamic range at 300Mhz IF for EDGE/GSM base-stations [receiver]
A mm-sized implantable device with ultrasonic energy transfer and RF data uplink for high-power applications
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique
A 98.5% Peak Efficiency 2/3-Phase Buck-or-Boost Converter With VCR-Independent Loss Optimization and Unconditional RHP Zero Elimination Achieving 2.76A/mm 2 -Current-Density and 6.5µs Recovery
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector
O w /L: An interface description language for IP reuse
An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS
Automated macromodelling of "nonlinear" wireless blocks
Estimation of Iddq for early chip and technology design decisions
Compensation of systematic variations through optimal biasing of SRAM wordlines
From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing
Jitter And Signaling Test For High-Speed Links
Fractional-N PLL with 90° phase shift lock and active switched-capacitor loop filter
Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes
Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generation
Integrating magnetics for on-chip power: Challenges and opportunities
A 99.4 dB SFDR 91.9 dB DR Continuous-Time Incremental Delta-Sigma ADC with a Noise-Shaping SAR Quantizer and a Passive Input Feedforward Stabilization Path
16 Arrays of 32 All-to-All Coupled CMOS Oscillators for AI Inference and Combinatorial Optimization
A continuous-time input pipeline ADC
A sliding IF receiver for mm-wave WLANs in 65nm CMOS
45nm high-k + metal gate strain-enhanced CMOS transistors
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory
A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS
A Parallel-Input Energy-Recycling Power Management Unit with Continuous MPPT for Magnetoelectrically Powered mm-Scale Bio-Implants
Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling
Practical design and simulation techniques for continuous-time ΔΣ converters
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS
A 0.8V 140nW low-noise energy harvesting CMOS APS imager with fully digital readout
Reliability Trends with Advanced CMOS Scaling and The Implications for Design
A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs
An ultra low power non-volatile memory in standard CMOS process for passive RFID tags
IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI
Future wireless systems
A 12b 50MSPS 34mW pipelined ADC
Memory trends
A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array
2.488 Gb/s silicon bipolar clock and data recovery IC for SONET (OC-48)
An Equalized Ultra-Wideband Channel-Select Filter with a Discrete-Time Charge-Domain Band-Pass IIR Filter
A mm-wave class-E 1-bit power modulator
Design guideline for resistive termination of on-chip high-speed interconnects
Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments
A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain
RPG-HBC: Reconfigurable Passive Galvanic Human Body Communication for Bioelectronic Implants Under Varying Channel Conditions
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction
A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs
A 1.8 GHz highly-tunable low-phase-noise CMOS VCO
Design of high-Q varactors for low-power wireless applications using a standard CMOS process
A 110nA synchronous boost regulator with autonomous bias gating for energy harvesting
A novel OTA-based fast lock PLL
A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI
A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis
An accurate DAC modeling technique based on wavelet theory
A new analytical model for high frequency MOSFET noise
Dual mixer downconversion architecture using complex mixing signals: enabling solutions for software defined radios
Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process
An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology
A hybrid electrical-behavioral modeling approach for pre- and post-silicon electrical validation
Near-field communication using phase-locking and pulse signaling for millimeter-scale systems
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems
dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering
A noninvasive channel-select filter for a CMOS Bluetooth receiver
Analog behavioral modeling: fantasy, fad, or foundation for the future?
Active deskew in injection-locked clocking
A capacitorless twin-transistor random access memory (TTRAM) on SOI
A yield and speed enhancement scheme under within-die variations on 90nm LUT array
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET
Parameter-specific ring oscillator for process monitoring at the 45 nm node
A Dual-Loop 4-Phase Switching LDO with Scalable Load Capability and Tunable Active Voltage Positioning for Microprocessors
Session 12-Analog techniques I
Manufacturability analysis of standard cell libraries
Circuits for on-chip sub-nanosecond signal capture and characterization
A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator
Digital Control of Switching and Linear Integrated Voltage Regulators
A 2.7 V CMOS GSM/WCDMA continuous-time filter with automatic tuning
Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial
Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system
A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis
A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs
Circuit reliability simulation using TMI2
A Review of Silicon Photonics LiDAR
An ultra low power 1V, 220nW temperature sensor for passive wireless applications
A highly-integrated CMOS analog baseband transceiver with 180MSPS 13b pipelined CMOS ADC and dual 12b DACs
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links
Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories
Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors
A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation
Nonlinear behavior study in digital bang-bang PLL
A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 μm CMOS
A 0.073-mm 2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM
A reconfigurable 2× / 2.5× / 3× / 4× SC DC-DC regulator for enhancing area and power efficiencies in transcutaneous power transmission
An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems
Session 15 - IC Technology - more Moore and more than Moore
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce
Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus
A 31.5-GHz BW 6.4-b ENOB 56-GS/s ADC in 28nm CMOS for 224-Gb/s DP-16QAM coherent receivers
A 37.5fs-rms Jitter and -254.1dB FoM Fractional-N Sampling PLL with Reference-Phase-Selection and Complementary-DTC Achieving 8× DTC Range Reduction and Zero DTC Delay Offset
A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation
A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine
Low Power Approaches to High Speed CMOS Current Steering DACs
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier
A CMOS Array Sensor for Sub-800-ps Time-Resolved Fluorescence Detection
A 9.2mW 528/66/50MHz monolithic clock synthesizer for mobile μP platforms
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation
A 5μW-5mW input power range, 0-3.5V output voltage range RF energy harvester with power-estimator-enhanced MPPT controller
Nonlinear macromodels of large coupled interconnect networks
Smart Threads for Tissue-Embedded Bioelectronics
Session 3 - Optical interconnect and reliability enhancement techniques
A 6.87W 3.7-5V Input 12.6-24V Output Switched-Capacitor Sigma Converter with Multiple Voltage Domains
A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation
A 50-GHz Phase-Locked Loop in 130-nm CMOS
Integrated Regulation for Energy-Efficient Digital Circuits
A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuning
A Battery-Connected Symmetric Modified Multilevel Ladder Converter Achieving 0.45W/mm 2 Power Density and 90% Peak Efficiency
A Wearable Real-time CMOS Dosimeter with Integrated Zero-bias Floating-Gate Sensor and an 861nW 18-bit Energy-Resolution Scalable Time-based Radiation to Digital Converter
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs
A 3 V linear input range tunable CMOS transconductor and its application to a 3.3 V 1.1 MHz Chebyshev low-pass Gm-C filter for ADSL
Single-stage dual-output AC-DC converter for wireless power transmission
A high gain operational amplifier via an efficient conductance cancellation technique
CMOS in the new millennium
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache
A 1.2 V, 433 MHz, 10 dBm, 38% global efficiency FSK transmitter integrated in a standard digital CMOS process
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS
A single chip 155 Mbps/140 Mbps SDH/PDH transceiver