yusuke1997/dblp-id-title huggingface dataset:
Reduced dynamic swing domino logic
Boolean Decomposition for AIG Optimization
Mixed spanning trees: a technique for performance-driven routing
An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic Workloads
A methodology for application-specific NoC architecture generation in a dynamic task structure environment
Design Issues of LC Tuned Oscillators for Integrated Transceivers
An evaluation of an AES implementation protected against EM analysis
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC
Clock skew bounds estimation under power supply and process variations
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction
SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform
Untestable fault identification through enhanced necessary value assignments
BrIM: A Branching In-Memory Accelerator
Scaling power/ground solvers on multi-core with memory bandwidth awareness
Application Mapping Method based on Particle Swarm Optimization for Continuous-Flow Microfluidic Biochips
Design Methodology for Embedded Approximate Artificial Neural Networks
Routability crossing distribution and floating terminal assignment of T-type junction region
AxR-NN: Approximate Computation Reuse for Energy-Efficient Convolutional Neural Networks
A semi-formal approach for analog circuits behavioral properties verification
Effective algorithms for cache-level compression
Security Analysis of Hardware Trojans on Approximate Circuits
Co-DTC: Concentric Trench-Based Integrated Capacitors for Advanced Chiplet-Based Platforms
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary
Built-in generation of functional broadside tests considering primary input constraints
A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level models
Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication
Distributed data-path synthesis on a network of workstations
Efficient tree topology for FPGA interconnect network
Low-power differential CML and ECL BiCMOS circuit techniques
An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors
Efficient space-time noc path allocation based on mutual exclusion and pre-reservation
Protecting Communication in Many-Core Systems against Active Attackers
A Low Power Charge-Recycling CMOS Clock Buffer
The Design of a Register Renaming Unit
Stochastic Computing for Reliable Memristive In-Memory Computation
Link breaking methodology: mitigating noise within power networks
Proceedings of the Great Lakes Symposium on VLSI 2024, GLSVLSI 2024, Clearwater, FL, USA, June 12-14, 2024
ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment
Numerical Tools for Fracture of MEMS Devices
Lightweight Authenticated Encryption for Network-on-Chip Communications
Regulator-gating: adaptive management of on-chip voltage regulators
A new DRAM architecture and its control method for the system power consumption
Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Inter-Layer Hybrid Quantization Scheme for Hardware Friendly Implementation of Embedded Deep Neural Networks
Dual-threshold pass-transistor logic design
MAPLE: Flexible-Precision Processing-In-Memory Architecture for Efficient On-Device ML
The Fuzz Odyssey: A Survey on Hardware Fuzzing Frameworks for Hardware Design Verification
Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning
Learning-Enabled Denial-of-Service (DoS) Attack Detection and Mitigation for Chiplet-Based Hybrid Interconnection Network
A generic implementation of a quantified predictor on FPGAs
A hierarchical multi-level test generation system
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling
Physical limitations on the bit-rate of on-chip interconnects
An improved direct boundary element method for substrate coupling resistance extraction
On Attacking Locking SIB based IJTAG Architecture
Energy-efficient redundant execution for chip multiprocessors
Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs
Future trends for wireless communication frontends in nanometer CMOS
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems
Handling intra-die variations in PSTA
In-memory Processing based on Time-domain Circuit
DNN Intellectual Property Protection: Taxonomy, Attacks and Evaluations (Invited Paper)
Ordered coloring-based resource binding for datapaths with improved skew-adjustability
Multi-port FinFET SRAM design
Partial parallel factorization in soft-decision Reed-Solomon decoding
Efficient transistor-level design of CMOS gates
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit
GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters
Adaptive bounded time windows in an optimistically synchronized simulator
GPU-Accelerated Simulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems
A Majority Logic Synthesis Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
Energy estimation of peripheral devices in embedded systems
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors
A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays
Washing Optimization Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits
A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology
Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories
Test set enhancement for quality transition faults using function-based methods
GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021
PruningQC: Boosting the Quantum Computation Fidelity by Pruning Redundant Gates
A Multilevel Cache Memory Architecture for Nanoelectronics
Towards Programmable All-Digital True Random Number Generator
Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic
Quality-of-service and error control techniques for network-on-chip architectures
Bitmask-based control word compression for NISC architectures
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
IR drop Prediction Based on Machine Learning and Pattern Reduction
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits
Hardware-accelerated gradient noise for graphics
Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge
Graph Neural Network Assisted Quantum Compilation for Qubit Allocation
Benchmarking Spiking Network Partitioning Methods on Loihi 2
Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory
Leveraging On-Chip Voltage Regulators Against Fault Injection Attacks
Tile-based design of a serial memory in QCA
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
GALS SoC interconnect bus for wireless sensor network processor platforms
Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits
Compaction of Compressed Bounded Transparent-Scan Test Sets
The role of photonics in future data centers
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield
Analyzing throughput of power and thermal-constraint multicore processor under NBTI effect
A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects
Load elimination for low-power embedded processors
A sensitivity based placer for standard cells
Memristor: the illusive device
An algorithm for embedding a class of non-even routing problems in even routing problems
Fast bus waveform estimation at the presence of coupling noise
Deterministic broadside test generation for transition path delay faults
Low-Power Optical Interconnects based on Resonant Silicon Photonic Devices: Recent Advances and Challenges
Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM
Noise tolerant low voltage XOR-XNOR for fast arithmetic
CHEQ: Towards Enabling Circuit Integrity Checking in Quantum Controllers
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers
3D-PLANE: A 3D-stacked DRAM-based Programmable SLM Accelerator Capable of Near-Memory and Energy-Efficient Parallel Processing
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration
On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
A Continuous-Time Switched-Current Sigma-Delta Modulator with Reduced Loop Delay
Forward image computation with backtracing ATPG and incremental state-set construction
Fast, Transparent and Accurate Simulation of Thousand Processing-in-Memory Cores
Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks
Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing
Adaptive gate biasing: a new solution for body-driven current mirrors
Language emptiness checking using MDGs
Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design
Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching
Effective heuristics for counterexample-guided abstraction refinement
InFormer: A High-throughput, Ultra-efficient In-memory Compute-based Floating-point Arithmetic Accelerator for Transformers
Blurring Boundaries: A New Way to Secure Approximate Computing Systems
Minimizing resources in a repeating schedule for a split-node data-flow graph
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic
General and efficient multiple list traversal for concurrent fault simulation
Application of Quantum Tensor Networks for Protein Classification
Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective
HydraRoute: A Novel Approach to Circuit Routing
Performance and energy models for memristor-based 1T1R RRAM cell
Sparsifying Graph Neural Networks with Compressive Sensing
A linear-time heuristic for rectilinear Steiner trees
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture
Hardware security in VLSI
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures
Transistor Level Synthesis for Static CMOS Combinational Circuits
FPGA based implementation of a genetic algorithm for ARMA model parameters identification
SACI: statistical static timing analysis of coupled interconnects
Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization
Self-timed pipeline with adder
Board-level multiterminal net assignment
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits
Write activity reduction on flash main memory via smart victim cache
VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder
A Multiple-Input Single-Phase Clock Flip-Flop Family
Sensitivity evaluation of global resonant H-tree clock distribution networks
HyperEncoding: Spiking Neural Networks with Hyperdimensional Encoding for Robust Edge Intelligence
Low-overhead state-retaining elements for low-leakage MTCMOS design
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems
Boosting Entropy Extraction of PDL-based RO PUF by High-order Difference Method
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction
On the complexity of a fault-tolerance model for multicomputer systems
A novel test-data compression technique using application-aware bitmask and dictionary selection methods
Improving FSM evolution with progressive fitness functions
Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs
Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O (1) with RRAM-based In-Memory Accelerator
On residue removal in digital microfluidic biochips
A Low-Cost GPS Spoofing Detector Design for Internet of Things (IoT) Applications
Improving FPGA routability using network coding
On Feasibility of Decision Trees for Edge Intelligence in Highly Constrained Internet-of-Things (IoT)
Verifying start-up conditions for a ring oscillator
An Approximate Carry Estimating Simultaneous Adder with Rectification
A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop
General transistor-level methodology on VLSI low-power design
Communication based multilevel synthesis for multi-output Boolean functions
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors
An FPGA implementation of an elliptic curve processor GF(2 m )
A Novel Low Power Energy Recovery Full Adder Cell
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Stepwise sleep depth control for run-time leakage power saving
Examining routing solutions
MRAM-based Analog Sigmoid Function for In-memory Computing
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming
RBGC: Repurpose the Buffer of Fixed Graphics Pipeline to Enhance GPU Cache
Fast algorithm for performance-oriented Steiner routing
DINGO - A Distributed & Intelligent Graph Based Memory for IoT
DM-TEE: Trusted Execution Environment for Disaggregated Memory
SIAR: splitting-graph-based interactive analog router
Design of Clock Distribution Networks in Presence of Process Variations
Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells
Efficient formal verification of pipelined processors with instruction queues
I/O bound binary tree layout
Orthogonal hypergraph routing for improved visibility
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
Random Forest Architectures on FPGA for Multiple Applications
A Global Mode Instruction Minimization Technique for Embedded DSPs
Minmax-cut graph partitioning problems
Extending symmetric variable-pair transitivities using state-space transformations
A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range
Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices
Optimizing finfet technology for high-speed and low-power design
Enhancing Parallelism in Commercial PIM DRAM with LUT-Based Design
An accurate evaluation of routing density for symmetrical FPGAs
An innovative user interface for fault simulation systems
Address generation for nanowire decoders
Generalized segmented channel routing
On-chip power supply noise and its implications on timing
Approximate Differential Encoding for Energy-Efficient Serial Communication
PWAM signalling scheme for high speed serial link transceiver design
Fast Timing Analysis of Non-Tree Clock Network with Shorted Wires
Energy optimization in memory address bus structure for application-specific systems
MC3A: Markov Chain Monte Carlo ManyCore Accelerator
PBD: packet buffer DVFs
Strategic Rip-Up and Reroute
NBTI mitigation in microprocessor designs
A Second-Order Sigma-Delta Modulator with Built-in VGA to Improve SNR and Harmonic Distortion
A design flow to optimize circuit delay by using standard cells and PLAs
Octilinear redistributive routing in bump arrays
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits
A Memory Design in QCAs using the SQUARES Formalism
System-level reliability exploration framework for heterogeneous MPSoC
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design
Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs
RandEye: On-Sensor Stochastic Image Transformation for Backdoor-Resistant Edge Inference
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems
CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection
A Minimum-Area Floorplanning Algorithm for MBC Designs
Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants
FORCE: a fast and easy-to-implement variable-ordering heuristic
Next-Generation Narrowband RF Front-Ends in Silicon IC Technology
Enhancing bug hunting using high-level symbolic simulation
Evaluation of on-chip networks using deflection routing
A Machine Learning-Assisted Placement Flow with Pin Accessibility Awareness
Optimal Region-based Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints
HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature Extraction
Inductance-aware Clock Network Synthesis Considering Hierarchical Interconnects in 3D ICs
Comparison of redundant architectures for two-step ADCs
Delay driven AIG restructuring using slack budget management
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath
Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding
Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments
FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual Inspection
Optimal test set for stuck-at faults in VLSI
Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic Neurons
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis
Trust Issues in COTS: The Challenges and Emerging Solution
A Cryptographic Hardware Engineering Course based on FPGA and Security Analysis Equipment
Mesh-of-tree deterministic routing for network-on-chip architecture
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking
Mitigating electromigration of power supply networks using bidirectional current stress
Design challenges in 45nm and below: DFM, low-power and design for reliability
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation
An area efficient low power high speed S-Box implementation using power-gated PLA
Axiomatic semantics of a hardware specification language
TinyML Enabled Real-Time Bearing Fault Classification in Motors Using Vibration Signals
Concurrent Error Detection for Reliable SHA-3 Design
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs
A New Model for General Connectivity and its Application to Placement
RDL pre-assignment routing for flip-chip designs
A test controller board for TSS
Fortified-Edge: Secure PUF Certificate Authentication Mechanism for Edge Data Centers in Collaborative Edge Computing
Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation Computing
Sequence invariant state machine compiler
Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses
A compact FPGA-based montgomery multiplier over prime fields
A memory aware behavioral synthesis tool for real-time VLSI circuits
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks
Bit-Wise Iterative Decoding of Polar Codes using Stochastic Computing
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
On the design of modulo 2 n -1 cubing units
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
Constructive benchmarking for placement
DRAM energy reduction by prefetching-based memory traffic clustering
Fault Coverage Estimation for Early Stage of VLSI Design
A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics
A 191μW BPSK demodulator for data and power telemetry in biomedical implants
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders
Reduced-complexity mimo detector with close-to ml error rate performance
A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection
GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development
Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays?
Digital Neural Processing Unit for Electronic Nose
Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots
Graphene tunneling FET and its applications in low-power circuit design
AQUASUN : adaptive window query processing in CAD applications for physical design and verification
Test generation using SAT-based bounded model checking for validation of pipelined processors
Hardware architecture for matrix factorization in mimo receivers
A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers
Using EDIF for software generation
Considering possible opens in non-tree topology wire delay calculation
HWFixBench: Benchmarking Tools for Hardware Understanding and Fault Repair
MCM placement using a realistic thermal model
Modeling of Shift Register-based ATM Switch
The challenges of implementing fine-grained power gating
Coding a terminated bus for low power
3D module placement for congestion and power noise reduction
Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications
Hands-On Teaching of Hardware Security for Machine Learning
Adaptive digital techniques to suppress quantization noise of Sigma Delta analog to digital converters
Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS
Unified Gravity Loss for Robust Neural Networks Through Feature Space Optimization
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems
Study of quaternary logic versus binary logic
PUFshield: A Hardware-Assisted Approach for Deepfake Mitigation Through PUF-Based Facial Feature Attestation
Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level
Challenges and methodologies for efficient power budgeting across the die
StateCharts to systemc: a high level hardware simulation approach
Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage
An Effective and Efficient Qubit Mapping Approach for Trapped-Ion Quantum Computers
NAND Flash Memory Scaling and Process Technology Modeling
Preferred direction Steiner trees
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories
Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic
A framework for high-level synthesis of heterogeneous MP-SoC