yusuke1997/dblp-id-title huggingface dataset:
AdNoC case-study for Mpeg4 benchmark: improving performance and saving energy with an adaptive NoC
A 915 MHz UHF low power RFID tag
A Dual-Kernel Size-Configurable Gaussian Filter Architecture
Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors
Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture
A custom processor for an FPGA-based platform for automatic license plate recognition
Improved IDEA
A Programmable Gain Amplifier for Load Demodulation Channel in an NFC Reader Chip
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS
Trim range limited by noise in bandgap voltage references
Multiple-objective Management based on a Distributed SDN Architecture for Many-cores
NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications
Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems
A digitally tunable 4th-order Gm-C low-pass filter for multi-standards receivers
Improving Software Productivity and Performance Through a Transparent SIMD Execution
SystemC and the Future of Design Languages: Opportunities for Users and Research
Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication
A new code compression algorithm and its decompressor in FPGA-based hardware
New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering
A Low-Voltage CMOS Exponential Function Circuit for AGC Applications
Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate Arrays
Area and performance optimization of a generic network-on-chip architecture
A modular CNF-based SAT solver
Self-adaptable slew rate control output buffer for embedded microcontroller port applications
Simplified model for automatic QCA circuitry verification
A Quantum-Dot Cellular Automata Processor Design
Hardware support in a middleware for distributed and real-time embedded applications
Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set Extensions
An FPGA Implementation of the ATM Layer
Power consumption reduction in MPSoCs through DFS
Number conversions between RNS and mixed-radix number system based on Modulo (2 p - 1 ) signed-digit arithmetic
A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4
Application-Specific Network-on-Chip synthesis with topology-aware floorplanning
A 40mhz 70db gain variable gain amplifier design using the gm/id design method
Reliability Analysis of a 130nm Charge Redistribution SAR ADC under Single Event Effects
Design of a low power MPEG-1 motion vector reconstructor
A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2000, Manaus, Brazil, September 18-24, 2000
A coloured petri net based approach for estimating execution time and energy consumption in embedded systems
A self-protected integrated switch in a HV technology
A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation
SwitchCraft: a framework for transistor network design
Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic Behavior
A Non-Linear Adaptive Filter for Sensor and Amplifier Linearization
The use of the analog wavelet filter to generate a sinusoidal signal and decompose the TEB signal into its cardiac and respiratory components in implantable cardiac pacemaker systems
Architectural Synthesis of Finite Impulse Response Digital Filters
Proceedings of the 12th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 1999, Natal, Brazil, September 29 - October 1, 1999
An evolutionary search for energy recovery opportunities in partially reversible FCN circuits
Designing ultra-low power systems with non-uniform sampling and event-driven logic
Asynchronous circuit design on reconfigurable devices
Improving the methodology to build non-series-parallel transistor arrangements
Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO
Quadratic placement with single-iteration linear system solver
Designing working systems with imperfect chips
Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVC
Soft-well digital circuit design
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates
CMOS 2.45GHz RF power amplifier for RFID reader
Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection Methods
New Modified 4:2 Approximate Compressors for Low-Power Applications
Power Consumption in Point-to-Point Interconnect Architectures
A Petri Net Based Method for Resource Estimation: An Approach Considering Data-Dependency, Casual and Temporal Precedences
Variable block size motion estimation architecture with a fast bottom-up decision mode and an integrated motion compensation targeting the H.264/AVC video coding standard
Self-Adaptive Network On Chips
Energy and Computing Assessment of Video Processing Kernels on CPU and FPGA platforms
Accurate Dependability Analysis of CAN-Based Networked Systems
A time petri net based approach for embedded hard real-time software synthesis with multiple operational modes
The re-definition of low power design for HPC: a paradigm shift
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration
An Overview of Radio Frequency Technologies and Their Influence on the Power Efficiency of Wireless Communication Systems
Impact of Register Reservation on the Reliability of Arm Cortex-M Processors under Neutrons
A new algorithm for an incremental sigma-delta converter reconstruction filter
Sub-1 V Supply Nano-Watt MOSFET-Only Threshold Voltage Extractor Circuit
FPGA design for real time flaw detection on edges using the LEDges technique
Encountering gate oxide breakdown with shadow transistors to increase reliability
An IP of an Advanced Encryption Standard for Altera" Devices
Limits to Voltage Scaling from the Low Power Perspective
Hybrid latch Flip-Flop with Improved Power Efficiency
Three-dimensional on-chip inductance and resistance extraction
Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers
Modeling the impact of RTS on the reliability of ring oscillators
A software-based methodology for the generation of peripheral test sets based on high-level descriptions
A Methodology for CMOS Low Noise Ampli.er Design
A Machine Learning Approach for Traffic Anomaly Detection in NoC-based Manycores
Physical Implementation of the NoX RISC-V Core Using an Open PDK
A methodology to improve yield in analog circuits by using geometric programming
A switch architecture and signal synchronization for GALS system-on-chips
A programmable cellular neural network circuit
Aspect-oriented design in systemC: implementation and applications
An ultra wide band analog-to-digital converter based on a Delta-Riemann architecture
A merged RF CMOS LNA-Mixer design using geometric programming
A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard
Layout techniques for radiation hardening of standard CMOS active pixel sensors
Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm
A time petri net-based approach for hard real-time systems scheduling considering dynamic voltage scaling, overheads, precedence and exclusion relations
Lithography friendly routing: from construct-by-correction to correct-by-construction
Efficient Hardware Implementation of the Fast Hybrid Morphological Reconstruction Algorithm
Adding mechanisms for QoS to a network-on-chip
Time Assisted SAR ADC with Bit-guess and Digital Error Correction
Effect of Unique Table Implementation in the Performance of BDD Packages
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
System-level design technologies for heterogeneous distributed systems
A 5.4 GHz fully-integrated low-noise mixer
Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of Experiments
Configurable Systems-on-Chip (CSoC)
A novel hardware architecture design for binary arithmetic decoder engines based on bitstream flow analysis
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V
Design of 28 nm CMOS integrated transformers for a 60 GHz power amplifier
Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment
A CMOS AM demodulator for instrumentation applications
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing
Integrating Machine-Learning Probes into the VTR FPGA Design Flow
An Offset Self-Correction Sample and Hold Circuit for Precise Applications in Low Voltage CMOS
A LEGAL Algorithm Following Global Routing
RASC: A Low-Power Reconfigurable 4-2 Adder-Subtractor-Compressor
Designing the Dispatch Stage of a Superscalar Microprocessor
Approximate interpolation filters for the fractional motion estimation in HEVC encoders and their VLSI design
Evaluation and Comparison of Offset Compensation Techniques for a Multi-Stage Comparator
MogaMap and DynPack: Multi-Objective Mapping and Packing Algorithms for Optimization of Area, Performance and Power Consumption in FPGAs
An SVM-based hardware accelerator for onboard classification of hyperspectral images
A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping
Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown
Synthesis of Multi-Burst Controllers as Modified Huffman Machines
T-shaped association of transistors: modeling of multiple channel lengths and regular associations
Revisiting Hamiltonian Decomposition of the Hypercube
Improvements on the detection of false paths by using unateness and satisfiability
From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project
Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing
A novel methodology for robustness analysis of QCA circuits
A quasi-differential quantizer based on SMOBILE
Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks
Current-mode analog integrated circuit for focal-plane image compression
Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture
Designing VLSI Circuit Masks with the Software Agents2
SoCIN: A Parametric and Scalable Network-on-Chip
An Environment to Aid the Synthesis of ThreePhase Analogue Waveform Using AHDL
Functional verification of power gate design in SystemC RTL
PPA Evaluation of Hardware Accelerated AES Algorithm Using RISC-V ISE
Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching
Efficient hardware implementation of morphological reconstruction based on sequential reconstruction algorithm
Automatic Generation of Digital Cell Libraries
Wideband ring VCO for cognitive radio five-port receiver
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool
Hardware pipelining of runtime-detected loops
Estimation methods for static noise margins in CMOS subthreshold logic circuits
Delay model for static CMOS complex gates
On evaluating the signal reliability of self-checking arithmetic circuits
High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV
Adaptive Systems-on-Chip: Architectures, Technologies and Applications
An UHD 4K@60fps Dual Self-Guided Filter Targeting the AV1 Decoder
A sub-1mA highly linear inductorless wideband LNA with low IP3 sensitivity to variability for IoT applications
An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking
A 450 mV supply self-biased wideband inductorless balun LNA for sub-GHz applications
A Switched-MOSFET Programmable Low-Voltage Filter
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism
Improving Energy Efficiency on Partially Reversible Pipelined QCA Circuits
On the Importance, Problems and Solutions of Pointer Synthesis
Validating SystemC Implementations Against Their Formal Specifications
An Automated Tool for Analysis and Design of MVL Digital Circuits
A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020
Secure Environment Architecture for MPSoCs
Energy-Efficient Hadamard-Based SATD Architectures
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing
Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet Forwarding
VHDL Models for High Level Synthesis of Fuzzy Logic Controllers
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures
4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor
Ultra-low power CMOS cells for temperature sensors
Data Encription in an Electronic Ballot Box
HdSC: a fast and preemptive modeling for on host HdS development
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
29th Symposium on Integrated Circuits and Systems Design, SBCCI 2016, Belo Horizonte, Brazil, August 29 - September 3, 2016
ATPG for fault diagnosis on analog electrical networks using evolutionary techniques
Sleep convention logic isochronic fork: an analysis
A Compact and Power-Efficient CMOS Battery Charger for Implantable Devices
Automated Synthesis of Cell Libraries for Asynchronous Circuits
Minimizing the mismatch errors at the VCO and cascode buffer connections in front end of BiCMOS RFICs operating on S band
RBF circuits based on folded cascode differential pairs
A custom interconnection multi-FPGA framework for distributed processing applications
A soft error robust and power aware memory design
Design and characterization of a 0.35 micron CMOS voltage-to-current converter
Design of low complexity digital FIR filters
Open-Source Verification IP for AXI-Stream
Verification of Hardware Implementations through Correctness of their Recursive Definitions in PVS
Communication software synthesis from UML-ESL models
Finding optimal qubit permutations for IBM's quantum computer architectures
Amplifier-based MOS analog neural network implementation and weights optimization
High-impedance multi-conductor transmission-lines for integrated applications at millimeter-wave frequency
Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
Low-power dual V th pseudo dual V dd domino circuits
Implementation comparisons of the QR decomposition for MIMO detection
Improving Logic Density of QCL Masterslices by using Universal Logic Gates
Boolean Technology Mapping Based on Logic Decomposition
31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018
Zero quiescent current startup circuit with automatic turning-off for low power current and voltage reference
CMOS analog four-quadrant multiplier free of voltage reference generators
Runtime QoS Support for MPSoC: a Processor Centric Approach
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
What is the Appropriate Model for Crosstalk Control?
A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures
Bandgap voltage reference with low susceptibility to electromagnetic interference (EMI)
AI-Driven Optimization of Sigma-Delta ADCs for Space Applications
Design of a class D amplifier for hearing aid devices
An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms
Digital Correction of Residue Amplifier Gain Error in a Two-Stage Pipeline-SAR ADC
Fitting the router characteristics in NoCs to meet QoS requirements
ATG-Based Timing Analysis of Circuits Containing Complex Gates
Minimizing the Number of Paths in BDDs
Fast VVC Affine Motion Estimation Using a Hardware-Friendly Machine Learning Method
Low power design techniques for nanometer design processes: 65 nm and smaller
Current mask generation: a transistor level security against DPA attacks
A Novel Method for Improving the Operation Autonomy of SIMD Processing Elements
A Design Procedure for Sizing Comparators in Active Rectifiers using $g_{m}/I_{D}$ Technique
A Comprehensive Analysis of Wire Performance in Silicon Dangling Bonds
2PSA: An Optimized and Flexible Power-Precision Scalable Adder
A 4.1 GHz prescaler using double data throughput E-TSPC structures
A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions
4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion
Hardware module for low-resource and real-time stereo vision engine using semi-global matching approach
Testability Properties of Vertex Precedent BDDs
Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications
16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach
An Adaptive Closed-Loop Verification Approach in UVM-SystemC for AMS Circuits
A constraint-based solution for on-line testing of processors embedded in real-time applications
WiMAX: a competing or complementary technology to 3G?
Total ionizing dose effects in switched-capacitor filters using oscillation-based test
A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous Architectures
Energy-Efficient Forwarding Routing Algorithm with bidirectional link quality estimator for Wireless Sensor Networks
Parameterizable floating-point library for arithmetic operations in FPGAs
DNAr-logic: a constructive DNA logic circuit design library in R language for molecular computing
Low power gate-level design with mixed-V th (MVT) techniques
24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011
Successful prototyping of complex integrated circuits with focused ion beam
Development of microtransformers using MCM and electronic packaging technologies
Evaluating the impact of circuit legalization on incremental optimization techniques
Jezz: An Effective Legalization Algorithm for Minimum Displacement
Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto
Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
Dynamic task binding for hardware/software reconfigurable networks
Design of a fully-integrated BiCMOS/FBAR reconfigurable RF receiver front-end
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005
ATMR design by construction based on two-level ALS
Ultra Low Power Tunable Filter for a Low Phase Shift on Electrocardiogram QRS-Complex Acquisition
Extracting Packet Dependence from NoC Simulation Traces Using Association Rule Mining
Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation
Standalone Rate-Distortion FME Architecture
Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4
When reconfigurable architecture meets network-on-chip
Power management techniques for very low consumption and EMI reduction in automotive applications
Block matching hardware architecture for SATD-based successive elimination
A comparison of two embedded systems to detect electrical disturbances using decision tree algorithm
A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits
Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity
Statistical Design of a Multiplier using a Low Power Square-Law CMOS Analog Cell
Multi-Terminal PiezoMOSFET Sensor for Stress Measurements in Silicon
Secure Communication with Peripherals in NoC-based Many-cores
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation
A 0.8 mum CMOS switched-capacitor video filter
A 34fJ/conversion-step 10-bit 6.66MS/s SAR ADC with built-in digital calibration in 130nm CMOS
Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding
Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic
Behavioral modeling of a control module for an energy-investing piezoelectric harvester
A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design
Limits for Low Supply Voltage Operation of a 5 GHz VCO to Drive a 4-Path Mixer
Automatic Synthesis of Hashing Function Circuits using Evolutionary Techniques
A temperature compensated CMOS relaxation oscillator for low power applications
Robust Implementation and Statistical Modeling of a VI-Converter
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA
Cache-tuning-aware scratchpad allocation from binaries
Buffer sizing for QoS flows in wormhole packet switching NoCs
Hardware-Software Codesign of Embedded Systems
An Embedded Converter from RS232 to Universal Serial Bus
A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS
Low-power CMOS transceivers with on-chip antennas for short-range radio-frequency communication
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers
Analytic boundaries for 6T-SRAM design in standby mode
Design of a Reusable Rail-to-Rail Operational Amplifier
Viability of analog inner product operations in CMOS imagers
All-GaN Integrated Overcurrent Protection Circuit Using Only Enhancement-mode p-GaN Devices
An improved synthesis method for low power hardwired FIR filters
Comparative Analysis of Hardware Implementations of a Convolutional Neural Network
Fundamentals of next generation compact MOSFET models
Power consumption analysis in static CMOS gates
CDFG -Petri Net Temporal Partitioning for Switching Context Applications
System on a Chip for Petroleum Pipeline Inspection
A Continuous-Time Incremental Analog to Digital Converter
Real-time digital modulation classification based on Support Vector Machines
An efficient FPGA implementation in quantum-dot cellular automata
Testing Mixed-Signal Cores
The ALFA-HUERTA Project
APU: Specification and Design of a Multi Algorithm ATM Policing Unit IP
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations
Performance and Variability Trade-offs of CMOS PTAT Generator Topologies for Voltage Reference Applications
Highly integrated Active Dual Response Filter
IC design requirements for automotive applications
Design for Stability of Active Inductor with Feedback Resistance
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019
Direct Feedback Topology for Reducing Residual Voltage in Functional Electrical Stimulation
Generating power-hungry test programs for power-aware validation of pipelined processors
Reliability aware yield improvement technique for nanotechnology based circuits
CMOS smart temperature sensors for RFID applications
Reducing and smoothing power consumption of ROM-based controller implementations
A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits