yusuke1997/dblp-id-title huggingface dataset:
Learned Critical Probabilistic Roadmaps for Robotic Motion Planning
Spatial Attention and Saccadic Camera Motion
An adaptive learning control method for constrained motion of uncertain robotic systems
Passive Bilateral Teleoperation with Constant Time Delays
Subject-Independent Data Pooling in Classification of Gait Intent Using Mechanomyography on a Transtibial Amputee
Learning Camera Miscalibration Detection
Fun with Robots: a Student-taught Undergraduate Robotics Course
POAQL: A Partially Observable Altruistic Q-Learning Method for Cooperative Multi-Agent Reinforcement Learning
The optimal swing-leg retraction rate for running
Reactive inclinometer-based mobile robot navigation
Human Symbiotic Robot Design Based on Division and Unification of Functional Requirements
Grasping objects with holes: A topological approach
T-Net for Navigating a Vision-Guided Robot in Real World
Control Pre-Imaging for Multifmgered Grasp Synthesis
Validation and Explanation of Waterhammer-based Locomotion
A study of the clash detection problem in robotics
Pose Estimation for Vehicle-mounted Cameras via Horizontal and Vertical Planes
Reproducing physical dynamics with hardware-in-the-loop simulators: A passive and explicit discrete integrator
From Cognition to Precognition: A Future-Aware Framework for Social Navigation
AZTR: Aerial Video Action Recognition with Auto Zoom and Temporal Reasoning
Object Transfer Point Estimation for Fluent Human-Robot Handovers
A discrete-time filter for the on-line generation of trajectories with bounded velocity, acceleration, and jerk
Effective Self-Righting Strategies for Elongate Multi-Legged Robots
A micro-manipulator vision in IC Manufacturing
Robust adaptive formation control of fully actuated marine vessels using local potential functions
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching
Verification of low-level crypto-protocol implementations using automated theorem proving
Formal validation and verification of a medical software critical component
Verification of Transaction-Level SystemC models using RTL Testbenches
Modeling resource sharing using FSM-SADF
8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), Grenoble, France, 26-28 July 2010
A design flow based on modular refinement
Executable Analysis using Abstract Interpretation with Circular Linear Progressions
MaLT: Machine-Learning-Guided Test Case Design and Fault Localization of Complex Software Systems
Towards verification of hybrid systems in a foundational proof assistant
Improving design verifiability by early RTL coverability analysis
Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest
Formal Analysis and Verification of DDS in ROS2
Assertion-Based Design with Horus
2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 23-25 June 2004, San Diego, California, USA, Proceedings
Deterministic receptive processes are Kahn processes
Verification of an industrial SystemC/TLM model using LOTOS and CADP
Step revision in hybrid Co-simulation with FMI
Establishing a refinement relation between binaries and abstract code
Formal Analysis of Fault Propagation in Complex Digital Systems
Finding Good Counter-Examples to Aid Design Verification
Property templates for checking source code security
A formal executable semantics of Verilog
MEMOCODE 2012 hardware/software codesign contest: DNA sequence aligner
Refinement-based synthesis of correct contract model decompositions
Design and formal verification of a copland-based attestation protocol
Efficient Coordination for Distributed Discrete-Event Systems
Robust hardware-software Co-simulation framework for design and validation of Hybrid Systems
Further sub-cycle and multi-cycle schedulling support for Bluespec Verilog
Keynote talk II: Accelerating data centers using reconfigurable logic
Optimal Real-time Inter-zone Message Communication via Ethernet Backbone in Software Defined Vehicles
GPU-based NoC simulator
A methodology for abstracting RTL designs into TL descriptions
Hierarchical Behavior Annex: Towards an AADL Functional Specification Extension
Stochastic contracts for cyber-physical system design under probabilistic requirements
Thunderstriking constraints with JUPITER
Cephalopode: A custom processor aimed at functional language execution for IoT devices
Sampling of shape expressions with ShapEx
Pragmatic Action Charts
Verified functional programming of an IoT operating system's bootloader
Efficient implementation of continuous skyline computation on a multi-core processor
Robust System Design with Uncertain Information
Lattice-based SMT for program verification
Performance estimation for task graphs combining sequential path profiling and control dependence regions
H.264 Decoder: A Case Study in Multiple Design Points
On the decidability of shared memory consistency verification
SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC
Formal verification of SystemC by automatic hardware/software partitioning
Analyzing tabular requirements specifications using infinite state model checking
Compositional design of asynchronous circuits from behavioural concepts
Survival strategies for synthesized hardware systems
Higher-order Hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor
Risk and Mitigation of Nondeterminism in Distributed Cyber-Physical Systems
A case study of hardware software co-design in a consumer ASIC
Keynote talk I: Security and privacy in implantable medical devices: An ongoing concern
Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation
Synchronous extensions to operation centric hardware description languages
22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design, MEMOCODE 2024, Raleigh, NC, USA, October 3-4, 2024
Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments
20th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2022, Shanghai, China, October 13-14, 2022
MEMOCODE '21: 19th ACM-IEEE International Conference on Formal Methods and Models for System Design, Virtual Event, China, November 20 - 22, 2021
Extended abstract: formal verification of architectural patterns in support of dependable distributed systems
Minimizing back pressure for latency insensitive system synthesis
Multicore power management: Ensuring robustness via early-stage formal verification
Robust Testing for Cyber-Physical Systems using Reinforcement Learning
Equivalence checking: a rule-based approach
PyPBS design and methodologies
Tutorial I: Efficient symbolic execution for software testing
Distributed computing on bittide systems
Polynomial Formal Verification of KFDD Circuits
Latency-Insensitive Hardware/Software Interfaces
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models
Controller synthesis for pipelined circuits using uninterpreted functions
Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications
Timestamp Peripherals for Precise Real-Time Programming
Automotive software and systems engineering (Panel)
Compilation of imperative synchronous programs with refined clocks
Can we computerize an elephant?
Modern constraint solving by propagation
Methods for exploiting SAT solvers in unbounded model checking
Keynote talk II: Multiform logical time for Me/Mo-codesign
Formal modelling of attack scenarios and mitigation strategies in IEEE 1588
Security of Pacemakers using Runtime Verification
A general technique for deterministic model-cycle-level debugging
Engineering Changes in Field Modifiable Architectures
Bounded Dataflow Networks and Latency-Insensitive circuits
Automated Power Domain Insertion and Control in Dataflow Circuits
How to Compute the Refinement Relation for Parameterized Systems
Using invariants to optimize formal specifications before code synthesis
Reliable design with multiple clock domains
Accelerating schedule space exploration of multi-threaded programs with GPUs
Real-Time Scheduling of Machine Learning Operations on Heterogeneous Neuromorphic SoC
Back to basics: Homogeneous representations of multi-rate synchronous dataflow graphs
Parallel assertions for debugging parallel programs
Reachability analysis for incomplete networks of Markov decision processes
Games for formal design and verification of reactive systems
From non-zenoness verification to termination
Mitigation of Cyber-physical Attacks in Industry 4.0 using Secure Function Blocks
Classes and subclasses in actor-oriented design
Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPN
Towards a Basis for Endochronous Functions in Dataflow Process Networks
A Verification Methodology for Infinite-State Message Passing Systems
Quotient for Assume-Guarantee Contracts
Formal verification in Intel CPU design
Metric interval temporal logic specification elicitation and debugging
TESL: A language for reconciling heterogeneous execution traces
Formal methods for checking realizability of coalitions in 3-party systems
Simulation of cyber-physical systems using IEC61499
Compositional construction of bounded error over-approximations of acyclic interconnected continuous dynamical systems
Efficient realization of logical execution times in legacy embedded software
Panel on design for verification
Symbolic software model validation
Configuring Safe Spiking Neural Controllers for Cyber-Physical Systems through Formal Verification
Type Inference for IP Composition
Scheduling as Rule Composition
Automatic generation of assertions from system level design using data mining
Hierarchical reconfiguration of dataflow models
SCEst: Sequentially constructive esterel
Static Deadlock Detection for the SHIM Concurrent Language
Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification
Predictive analysis for detecting serializability violations through Trace Segmentation
A small, but important, concurrency problem in Verilog's semantics? (Work in progress)
A reactive specification formalism for enhancing system development, analysis and adaptivity
Controller verification meets controller code: a case study
Designing a reorder buffer in Bluespec
Automatic evaluation of complex design decisions in component-based software architectures
Verifying Absence of Hardware-Software Data Races using Counting Abstraction
Generation of inductive invariants from register transfer level designs of communication fabrics
Software/Hardware Engineering with the Parallel Object-Oriented Specification Language
Enhancing the assertion-based verification of TLM designs with reentrancy
R-SHIM: deterministic concurrency with recursion and shared variables
Specification-guided Software Fault Localization for Autonomous Mobile Systems
Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?
Extended abstract: evaluation of delay queues for a Ravenscar HW kernel
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays
Verification of parameterized hierarchical state machines using action language verifier
Systematic testing for control applications
Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann Architectures
Static priority scheduling of event triggered real time embedded systems
Physics-Aware Mixed-Criticality Systems Design via End-to-End Verification of CPS
Scalable program analysis using Boolean satisfiability
A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations
11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMCODE 2013, Portland, OR, USA, October 18-20, 2013
Keynote talk II: Designing tomorrow's chips
More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models
Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems
Static data-flow analysis of synchronous programs
A compositional semantics of Simulink/Stateflow based on quantized state hybrid automata
A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design
Tuning into my heart through wearables: Towards a formal cardiac digital twin
Translating structured sequential programs to dataflow graphs
Verification of SpecC using predicate abstraction
Mining assumptions for synthesis
Compiler-directed memory hierarchy design for low-energy embedded systems
Monitoring temporal SystemC properties
Buffer sharing in CSP-like programs
Using the coq theorem prover to verify complex data structure invariants
Verification of microarchitectural refinements in rule-based systems
Panel: given that hardware verification has been an uphill battle, what is the future of software verification?
Analyzing Concurrency in Computational Networks
Quantifying the information leak in cache attacks via symbolic execution
Clearing the clutter: Unified modeling and verification methodology for system level hardware design
Mechanization of a Large DSML: An Experiment with AADL and Coq
Proceedings of the International Symposium on Formal Methods and Models for System Design, MEMOCODE 2025, Taipei International Convention Center (TICC), Taipei, Taiwan, 28 September 2025 - 3 October 2025
Curing schizophrenia by program rewriting in Esterel
Run-time Requirement Enforcement for Loop Programs on Processor Arrays
Probabilistic Reachability for Uncertain Stochastic Hybrid Systems via Gaussian Processes
Bluespec System Verilog: efficient, correct RTL from high level specifications
Verification of Control Properties in the Polyhedral Model
From Data to Events: Checking Properties on the Control of a System
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays
A secure insulin infusion system using verification monitors
Online monitoring of spatio-temporal properties for imprecise signals
Using SSDE for USB2.0 conformance co-verification
Safe and efficient collision avoidance control for autonomous vehicles
Optimizations for Faster Execution of Esterel Programs
Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware Implementation
Formal verification of an optimizing compiler
21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, MEMOCODE 2023, Hamburg, Germany, September 21-22, 2023
A synchronous language at work: the story of Lustre
Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract)
Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk
Modelling and proving the monotonicity of processor pipelines in Coq
Specifying and proving properties of timed I/O automata in the TIOA toolkit
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
Estimating the Performance of Cache Replacement Policies
Translating Fusion/UML to Object-Z
Translating synchronous guarded actions to interleaved guarded actions
From signal temporal logic to FPGA monitors
Formal verification of pipelined processors with precise exceptions
Efficient code generation from synchronous programs
APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study
MoDe: A Method for System-Level Architecture Evaluation
Easier and More Informative Vacuity Checks
A verified development of hardware using CSP∥B
Creating a Language for Writing Real-Time Applications for the Internet of Things
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
Goal-Oriented Requirements Analysis for Process Control Systems Design
Lifecycle-Based View on Cyber-Physical System Models Using Extended Hidden Markov Models
Logical specification and uniform synthesis of robust controllers
Compositional dataflow circuits
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers
Proving What Programs Do Not
Optimal Self-Routing Split Modules for Radix-based Interconnection Networks
Contract Replaceability for Ensuring Independent Design using Assume-Guarantee Contracts
Hierarchical multi-formalism proofs of cyber-physical systems
Efficient deadlock detection for concurrent systems
Bang for the buck: Improvising and scheduling verification engines for effective resource utilization
Specification, verification, and synthesis using extended state machines with callbacks
PROBMELA: a modeling language for communicating probabilistic processes
Improving SystemC simulation through Petri net reductions
Fast scalable FPGA-based Network-on-Chip simulation models
Control-flow guided property directed reachability for imperative synchronous programs
Design and verification of multi-rate distributed systems
Check and simulate: a case for incorporating model checking in network simulation
On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications
Latency-insensitive design and central repetitive scheduling
VT Matrix Multiply Design for MEMOCODE '07
A fast emulator for ARM-based embedded systems
Execution semantics and formalisms for multi-abstraction TLM assertions
A high throughput parallel architecture for category specific Deep Packet Inspection
Building faithful high-level models and performance evaluation of manycore embedded systems
Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded Systems
Safe CCSL specifications and marked graphs
C-to-Verilog translation validation
Polychronous controller synthesis from MARTE CCSL timing specifications
A scenario-aware data flow model for combined long-run average and worst-case performance analysis
Transforming SystemC Transaction Level Models into UPPAAL timed automata
Real-time Property Preservation in Approximations of Timed Systems
Cycle-accurate 8080 emulation using an ARM11 processor with dynamic binary translation
Verification of component architectures using mode-based contracts
Simplification of numeric variables for PLC model checking
A refinement-based compiler development for synchronous languages
Model-based availability analysis for automated production systems: a case study
Bayesian Statistical Model Checking for Continuous Stochastic Logic
On the use of a high-level fault model to analyze logical consequence of properties
Exploring Compositional Neural Networks for Real-Time Systems
Synthesis of synchronous assertions with guarded atomic actions
Modeling of time in discrete-event simulation of systems-on-chip
Monitoring mobile and spatially distributed cyber-physical systems
Checkers for SystemC designs
Towards Efficient Input Space Exploration for Falsification of Input Signal Class Augmented STL
Towards refinement types for time-dependent data-flow networks
SMT based false causal loop detection during code synthesis from Polychronous specifications
Translation-based co-verification
A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines
Coherence-Aware Task Graph Modeling for Realistic Application
Power emulation: Methodology and applications for HW/SW power optimization
Formal verification as a technology transfer problem
Layering RTL, SAFL, Handel-C and Bluespec constructs on Chisel HCL
ORIGAMI: Folding Data Structures to Reduce Timing Side-Channel Leakage
Asynchrony-aware static analysis of Android applications
Implementing latency-insensitive dataflow blocks
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2 m and algebraic techniques
An introduction to implementation attacks and countermeasures
Explaining Unsolvability of Planning Problems in Hybrid Systems with Model Reconciliation
Approximate computing for multithreaded programs in shared memory architectures
Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs
Runtime Interchange of Enforcers for Adaptive Attacks: A Security Analysis Framework for Drones
Model-based diagnosis versus error explanation
Formal Design of Safety-critical Embedded Systems
18th ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2020, Jaipur, India, December 2-4, 2020
Arithmetic Circuits Verification without Looking for Internal Equivalences
Optimized distributed implementation of timed component-based systems
Optimized distribution of synchronous programs via a polychronous model
2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2016, Kanpur, India, November 18-20, 2016
Making PVS do what you want
A core calculus for secure hardware: its formal semantics and proof system
Extended abstract: transition traversal coverage estimation for symbolic model checking
EFSM-based model-driven approach to concolic testing of system-level design
Refining schizophrenia via graph reachability in Esterel
Frame conditions in symbolic representations of UML/OCL models
From bold idea to product - a case study
16th ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2018, Beijing, China, October 15-18, 2018
Elastic systems
Compositional performance verification of NoC designs
Directed-Logical Testing for Functional Verification of Microprocessors
Automated, compositional and iterative deadlock detection
Direct generation of invariants for reactive models
Keynote Talk III: A formal methods perspective on product line engineering
Fast prototyping from assertions: A pragmatic approach
Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages
Reach-Avoid Verification for Time-varying Systems with Uncertain Disturbances
A generic synthesisable test bench
The role of mutation analysis for property qualification
Robustness Contracts for Scalable Verification of Neural Network-Enabled Cyber-Physical Systems
Programming models and languages for SoC-implemented architectures
Specification and Verification of LambdaRAM: A Wide-area Distributed Cache for High Performance Computing
Executable Computational Logics: Combining Formal Methods and Programming Language Based System Design
LION: real-time I/O transfer control for massively parallel processor arrays
Performance analysis of the Disrupted Static Priority scheduling for AFDX
Preservation of LTL properties in desynchronized systems
Using hardware-software codesign language to implement CANSCID
Neuro-symbolic Generative AI Assistant for System Design
Security Types for Synchronous Data Flow Systems
CANSCID-CUDA
MEMOCODE 2014 design contest: k-Nearest Neighbors with Mahalanobis distance metric
Compositional interaction specifications for SystemC
A computer-algebraic approach to formal verification of data-centric low-level software
Multi-Level Assertion-Based Design
9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11-13 July, 2011
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
Translation of continuous function charts to imperative synchronous quartz programs
Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest
MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simulator
3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings
Parallel reachability analysis for hybrid systems
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs
2009 MEMOCODE Co-Design Contest
Formal Fault Injection in Digital Blocks with Mined Assertions
Fast Robust Monitoring for Signal Temporal Logic with Value Freezing Operators (STL * )
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Profiling and optimizations for embedded systems
Assertion checking of control dominated systems with nonlinear solvers
Model Checking Time Window Temporal Logic for Hyperproperties
Implementing a fast cartesian-polar matrix interpolator