yusuke1997/dblp-id-title huggingface dataset:
A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only
A Case for Work-stealing on FPGAs with OpenCL Atomics
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only)
Unleashing the Power of FPGAs as Programmable Switches
A Unified Framework for Automated Code Transformation and Pragma Insertion
Finding and Understanding Bugs in FPGA Synthesis Tools
Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only)
Periodic licensing of FPGA based intellectual property
Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing (Abstract Only)
HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)
FPGA-based design of an evolutionary controller for collision-free robot navigation
3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only)
High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems
Hierarchical LUT structures for leakage power reduction (abstract only)
The VTR project: architecture and CAD for FPGAs from verilog to routing
Building FPGA State Machines from Sequential Code
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration
Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs
Hardware Assists for High Performance Computing Using a Mathematics of Arrays
Rent's rule based FPGA packing for routability optimization
Unified Access to Heterogeneous Module Generators
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver
Evaluating heuristics in automatically mapping multi-loop applications to FPGAs
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS 5 )(Abstract Only)
A Novel Method for Enabling FPGA Context-Switch (Abstract Only)
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design
R2CNN: Recurrent Residual Convolutional Neural Network on FPGA
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Large-scale wire-speed packet classification on FPGAs
On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure
Rapid prototyping of a test harness for forward error correcting codes (abstract only)
A 3d-audio reconfigurable processor
Voter insertion algorithms for FPGA designs using triple modular redundancy
Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract)
Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)
A Highly Parallel FPL-Based Machine and Its Formal Verification
FPGA Design Experiences Using the CSELT VIP (TM) Library
The SFRA: a corner-turn FPGA architecture
PAI-FCNN: FPGA Based CNN Inference System
Design of a fingerprint system using a hardware/software environment
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only)
Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only)
Limit study of energy & delay benefits of component-specific routing
Bit-level optimization for high-level synthesis and FPGA-based acceleration
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits
A faster distributed arithmetic architecture for FPGAs
A Framework for Optimizing GCN Inference on FPGA
Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only)
A single-FPGA implementation of image connected component labelling
Scalable network virtualization using FPGAs
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine
Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform
Optimal Circuits for Streamed Linear Permutations Using RAM
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs
Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays
Making good points: application-specific pareto-point generation for design space exploration using statistical methods
Detailed routing architectures for embedded programmable logic IP cores
A monte-carlo floating-point unit for self-validating arithmetic
Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only)
An FPGA prototype for the experimental evaluation of a multizone network cache
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only)
High performance architecture for object detection in streamed video (abstract only)
Diagonal tracks in FPGAs: a performance evaluation
Run-Time Parameterizable Cores
Implementation of elliptic curve cryptosystems over GF(2 n ) in optimal normal basis on a reconfigurable computer
Cycle-Free FPGA Routing Graphs
Thermal and Voltage Side and Covert Channels and Attacks in Cloud FPGAs
A 90nm low-power FPGA for battery-powered applications
LambdaRank acceleration for relevance ranking in web search engines (abstract only)
Area and delay trade-offs in the circuit and architecture design of FPGAs
Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs
Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting
Architecture evaluation for power-efficient FPGAs
Breaking the Trust Dependence on Third Party Processes for Reconfigurable Secure Hardware
Thermal and power characterization of field-programmable gate arrays
FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting
Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only)
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)
Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only)
The Stratix™ 10 Highly Pipelined FPGA Architecture
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only)
A lean FPGA soft processor built using a DSP block
Multiplier architectures for FPGA double precision functions (abstract only)
Automated Accelerator Optimization Aided by Graph Neural Networks
Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only)
JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores
C is for circuits: capturing FPGA circuits as sequential code for portability
Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-Optimizations
Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic
Hardware Description Beyond Register-Transfer Level Languages
Fast and scalable packet classification using perfect hash functions
Efficiently Supporting Fault-Tolerance in FPGAs
Improving the security and the scalability of the AES algorithm (abstract only)
Predicting the performance of application-specific NoCs implemented on FPGAs
Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs
Scientific Applications of FPGAs at the LHC
A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only)
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping
Probabilistic Optimization for High-Level Synthesis
A practical FPGA-based framework for novel CMP research
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center
A New Approach to Automatic Memory Banking using Trace-Based Address Mining
Impact of FPGA architecture on resource sharing in high-level synthesis
Active leakage power optimization for FPGAs
HSC-FPGA
OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory Platform
Accelerating parameter estimation for multivariate self-exciting point processes
REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs
Scalable multi-access flash store for big data analytics
FPGA-based front-end electronics for positron emission tomography
Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems
ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development
HGum: Messaging Framework for Hardware Accelerators (Abstact Only)
A mixed precision Monte Carlo methodology for reconfigurable accelerator systems
Reconfigurable Processing for Robust Navigation and Control (Abstract)
SPR: an architecture-adaptive CGRA mapping tool
FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only)
Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD Algorithms
The effect of reconfigurable units in superscalar processors
Accelerating massive short reads mapping for next generation sequencing (abstract only)
A hardware framework for the fast generation of multiple long-period random number streams
Intel Acquires Altera: How Will the World of FPGAs be Affected?
Extending High-Level Synthesis for Task-Parallel Programs
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only)
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA
Resource Scheduling for Real-Time Machine Learning
A Study of Early Aggregation in Database Query Processing on FPGAs
FPGA-based biophysically-meaningful modeling of olivocerebellar neurons
Reliability of a softcore processor in a commercial SRAM-based FPGA
Evaluation of granularity on threshold voltage control in flex power FPGA
Design and implementation of an FPGA based processor for compressed images (poster abstract)
The Stratix II logic and routing architecture
Logic Gates in the routing network of FPGAs (Abstract Only)
LPAC: A Low-Precision Accelerator for CNN on FPGAs
Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only)
A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)
Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA
Transformations for throughput optimization in high-level synthesis (abstract only)
Hardware Synthesis of Weakly Consistent C Concurrency
Resolving implicit barrier synchronizations in FPGA HLS (abstract only)
A Computational Intelligence Based Coarse-Grained Reconfigurable Element
Stream-HLS: Towards Automatic Dataflow Acceleration
HybridOS: runtime support for reconfigurable accelerators
FPGA Mux Usage and Routability Estimates without Explicit Routing
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System
FPGA implementation of a fast Hadamard transformer for WCDMA
A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only)
Special Arithmetic Operations on FPGAs
A compact FPGA implementation of the hash function whirlpool
Soft multiprocessor systems for network applications (abstract only)
FPGA switch block layout and evaluation
FPGA test time reduction through a novel interconnect testing scheme
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems
Scheduling Designs into a Time-Multiplexed FPGA
Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only)
Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power
HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs
Soft vector processors with streaming pipelines
Run-Time defect tolerance using JBits
HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs
Generation of Synthetic Sequential Benchmark Circuits
Customizable bit-width in an OpenMP-based circuit design tool
High-Performance Carry Chains for FPGAs
CASK: Open-Source Custom Architectures for Sparse Kernels
A high resolution diagnosis technique for open and short defects in FPGA interconnects
Simultaneous Placement and Clock Tree Construction for Modern FPGAs
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis
FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract)
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller
Acceleration of an analytical approach to collateralized debt obligation pricing
The Stratix TM routing and logic architecture
Online placement infrastructure to support run-time reconfiguration
Design Issues in the Development of a JAVA-Processor for Small Embedded Applications
Bridging Fault Detection in FPGA Interconnects Using I DDQ
A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)
A high performance fpga-based implementation of position specific iterated blast
Hierarchical FPGA Fabrics using 2D-Benes-BFT-Pyramid Network Layouts with Optimizations
Reconfigurable custom floating-point instructions (abstract only)
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis
Automatic generation of FPGA routing architectures from high-level descriptions
The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 Years
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping
Time and area efficient pattern matching on FPGAs
The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013
S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks
Xilinx Vitis Unified Software Platform
Measuring the gap between FPGAs and ASICs
Design of a logic element for implementing an asynchronous FPGA
C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs
Revisiting PathFinder Routing Algorithm
Emerging application domains: research challenges and opportunities for FPGAs
The gigahertz FPGA: design consideration and applications
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only)
A 1 cycle-per-byte XML parsing accelerator
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits
120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board
Fingerprinting Cloud FPGA Infrastructures
Enhancing Hardware Design Flows with MyHDL
Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)
FPGA-accelerated 3D reconstruction using compressive sensing
An FPGA memcached appliance
DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP
Programmable memory blocks supporting content-addressable memory
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs
Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs
Hyper customized processors for bio-sequence database scanning on FPGAs
Intel® atom TM processor core made FPGA-synthesizable
Magnetic tunnelling junction based FPGA
Towards scalable placement for FPGAs
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs
Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs (Abstract Only)
Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA
HyperPipelining of High-Speed Interface Logic
FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction
An FPGA-based genetic algorithm machine (poster abstract)
Self-Checking Logic Design for LUT-Based FPGAs
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
An embedded true random number generator for FPGAs
Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning
Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck
Structured Design Implementation: A Strategy for Implementing Regular Datapaths on FPGAs
Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract)
Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience (Abstract Only)
An FPGA implementation of a sparse quadratic programming solver for constrained predictive control
300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only)
Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA
FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10
High-performance, cost-effective heterogeneous 3D FPGA architectures
Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)
A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design
Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains
Jaguar: a compiler infrastructure for Java reconfigurable computing
Synthesis of an application-specific soft multiprocessor system
Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs)
CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time
High level area, delay and power estimation for FPGAs
Energy Efficient Scientific Computing on FPGAs using OpenCL
Early timing estimation for system-level design using FPGAs (abstract only)
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
Accelerating Monte Carlo based SSTA using FPGA
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only)
A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only)
TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms
Module Generation of Complex Macros for Logic-Emulation Applications
Vector processing as a soft-core CPU accelerator
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025, Monterey, CA, USA, 27 February 2025 - 1 March 2025
MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs
Modeling the data-dependent performance of pattern-matching architectures
Fine-Grained Interconnect Synthesis
Technology Mapping for FPGAs with Embedded Memory Blocks
Sparse Matrix-Vector multiplication on FPGAs
A logic based approach to hardware abstraction
FPGA side-channel receivers
FPGA Circuit Optimization Based on Block Integration (Abstract)
A prototype FPGA for subthreshold-optimized CMOS (abstract only)
Is marriage in the cards for programmable logic, microprocessors and ASICs?
Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only)
Dynamic power consumption in Virtex[tm]-II FPGA family
CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center
Indirect connection aware attraction for FPGA clustering (abstract only)
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002
Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements
Prototyping Board and Development Environment for Rapid Prototyping of Real Time and Regular Digital Signal Processing Application
FPGA prototyping of an amba-based windows-compatible SoC
An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing
Memory Interfacing and Instruction Specification for Reconfigurable Processors
Minimum energy operation for clustered island-style FPGAs
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996
Base64 Encoding on OpenCL FPGA Platform
A Methodology for Fast FPGA Floorplanning
N-port memory mapping for LUT-based FPGAs
DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only)
EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access
High-throughput bayesian computing machine with reconfigurable hardware
A Real-Time Kernel - Rapid Prototyping with VHDL and FPLs
Routing algorithms: enhancing routability & enabling ECO (abstract only)
High Level Synthesis of Complex Applications: An H.264 Video Decoder
Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only)
Torc: towards an open-source tool flow
Implementation of the reconfiguration port scheduling on the erlangen slot machine
Universal Switch Blocks for Three-Dimensional FPGA Design
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs
An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only)
HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only)
High Performance Linkage Disequilibrium: FPGAs Hold the Key
Measuring the Minimum Power Requirement of FPGA Architectural Specifications
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The effect of LUT and cluster size on deep-submicron FPGA performance and density
The Role of FPGAs in Deep Learning
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
On Data Forwarding in Deeply Pipelined Soft Processors
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)
Enhancing FPGAs with Analog In-Memory Computing Macros
A real-time implementation of Richardson-Lucy deconvolution
FPGA-optimised high-quality uniform random number generators
Versal: The Xilinx Adaptive Compute Acceleration Platform (ACAP)
Implementing high-speed string matching hardware for network intrusion detection systems
Patching Method for Lookup-Table Type FPLs
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation
Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs
HMLib: Efficient Data Transfer for HLS Using Host Memory
New Application of FPLs to Programmable Digital Communication Cirucits
Reconfigurable computers: an empirical analysis (abstract only)
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only)
Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA
Signal Processing at 250 MHz Using High-Performance FPGA's
Using BDDs to Design ULMs for FPGAs
Hardware-assisted simulated annealing with application for fast FPGA placement
Rapid Prototyping of Multi-Recommendation Modem (Abstract)
MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only)