yusuke1997/dblp-id-title huggingface dataset:
Fehlertolerante Rechnerarchitekturen für Kraftfahrzeuganwendungen
HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors
GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization
Evaluating CMPs and Their Memory Architecture
Einsatz eines integrierten Visualisierungstools für Ingenieuranwendungen auf der Basis von CORBA
High Performance Multigrid on Current Large Scale Parallel Computers
Lipsi: Probably the Smallest Processor in the World
Leveraging Application-Specific Knowledge for Energy-Efficient Deep Learning Accelerators on Resource-Constrained FPGAs
Xputers: An Open Family of Non-Von Neumann Architectures
Resource-Aware Harris Corner Detection Based on Adaptive Pruning
Techniques and Visualization Approaches for Analyzing Local and Global Pareto Optimal Sets in Multi-Objective Design Space Exploration
PASCOM: Power Model for Supercomputers
Accurate Energy Consumption Evaluation of Preamble Sampling MAC Protocols for WSN
Controller Synthesis for Mapping Partitioned Programs on Array Architectures
Entwurf eines portablen Realzeit-Betriebssystems für Kleinrechner-Konfigurationen
Self-Explanation of System Behaviour in Organic Computing Systems
Self-organized Parallel Cooperation for Solving Optimization Problems
Effects of Approximate Computing on Workload Characteristics
Fehlermaskierende verteilte Systeme zur Erfüllung hoher Zuverlässigkeit-Anforderungen in Prozeßrechner-Netzen
Towards Tight Interaction of ASP and SMT Solving for System-Level Decision Making
Sub-word Handling in Data-parallel Mapping
Layer-Centric Testing
Ein Zwischenformat-Profiler für das RECAST-Framework
Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms
Revisiting Gradient Direction Algorithms in Electrostatic Placers
A Measurement Framework at Global and Local Levels for Hybrid Organic Computing Systems
Exzess: Hardware-Based RAM Encryption Against Physical Memory Disclosure
An efficient on-line Approach for on-chip HW/SW partitioner and scheduler
Computer Architecture, Workshop of the Gesellschaft für Informatik, Erlangen, May 22-23, 1995, Proceedings
MEMPower: Data-Aware GPU Memory Power Model
Aktivierung und Zuordnung von kooperierenden Prozessen im ASSKO-Mehrprozessorsystem
Vertical Link On/Off Control Methods for Wireless 3-D NoCs
Ist der Parallelrechner tot?
Improving Reliability and Endurance Using End-to-End Trust in Distributed Low-Power Sensor Networks
Organic Computing to Improve the Dependability of an Automotive Environment
A Minimal Network Interface for a Simple Network-on-Chip
A Case Study on Error Resilient Architectures for Wireless Communication
Probleme der Emulation unkonventioneller Rechnerarchitekturen: pseudoassoziative Verarbeitung im Projekt EGPA
Laborautomation und Prozeßrechensysteme
Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology
Deep Reinforcement Learning with a Classifier System - First Steps
Virtualized Communication Controllers in Safety-Related Automotive Embedded Systems
Applying the Concept of Artificial DNA and Hormone System to a Low-Performance Automotive Environment
Eine objektorientierte Architektur für paralleles LISP
Parallel coding for storage systems - An OpenMP and OpenCL capable framework
Root Cause Analysis as a Guide to SRE Methods
Untersuchungen zu Prepaging-Verfahren
Dynamically Reconfigurable CORDIC Coprocessor for Trigonometric
Almost Optimal Schedules with a Simple Protocol
Assessing and Improving the Suitability of Model-Based Design for GPU-Accelerated Railway Control Systems
SAMP: A General Purpose Processor Based on a Self-Timed VLIW Structure
Marketplace-Oriented Behavior in Semantic Multi-Criteria Decision Making Autonomous Systems
A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces
A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs
Promoting Power to a First Class Metric in Network Simulations
Features of optical interconnects in distributed-shared memory organized MIMD architectures: the ultimate goal
An Effective Multi-hop Broadcast in Vehicular Ad-Hoc Network
Trust as a Design Aspect of Context Aware Systems
ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering
High-Availability and Standards - The Wag to Go!
Hot Topic Detection in Local Areas Using Twitter and Wikipedia
Die virtuelle Netzwerkmaschine - Ein Werkzeug zur Entwicklung verteilter Betriebssysteme
Online-Prozessor für ein Echtzeit-Bildverarbeitungssystem
Energy Consumption Estimation and Profiling in Wireless Sensor Networks
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
Flagorientierte Arithmetik-Logik-Einheiten für Inhaltsadressierbare Daten
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks
Parallel-Operation-Oriented Optically Reconfigurable Gate Array
An Optimized Timing and Control Flow Checker for Hard Real-Time Systems
A Tool Chain for a Lightweight, Robust and Uncertainty-based Context Classification System (CCS)
Architecture of Computing Systems - ARCS 2020 - 33rd International Conference, Aachen, Germany, May 25-28, 2020, Proceedings
Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOV
Structural Aware Quantitative Interprocedural Dataflow Analysis
The Architecture of the BIRLIX Operating System
SgInt: Safeguarding Interrupts for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non Transparent Bridges
On Automated Feedback-Driven Data Placement in Multi-tiered Memory
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA
Beschreibung eines synthetischen Jobmix für verschiedene Benmark- Test
Organic Architectures for Large-Scale Environment-Aware Sensor Networks
An Effective Video Streaming Method for Video on Demand Services in Vertical Handoff
Das System CTM9032 - ein leistungsfähiger Verbund intelligenter Bildschirmarbeitsplätze
Processing-in-Memory: Exploring the Design Space
Evaluating Adaptive Systems: A Comparative Study of XCS and Established Reinforcement Learning Algorithms in Noisy Multi-step Environments
Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings
Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa
FTRFS: A Fault-Tolerant Radiation-Robust Filesystem for Space Use
Ein Ansatz zur Standardisierung von Betriebssoftware
A Decision-Theoretic Approach for Prioritizing Maintenance Activities in Organic Computing Systems
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs
Fachtagung Struktur und Betrieb von Rechensystemen, GI-NTG, Braunschweig, 20.-22.3.1974, Proceedings
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN)
A Note on Certificate Path Verification in Next Generation Mobile Communications
Peripherieanschluß über Vorprozessoren: Auswirkungen auf Struktur und Verhalten von HW/SW-Systemen
A concept for hardwired main storage management
Error and Flow Control in Terabit Intelligent Optical Backplanes
Ein Modularisierungskonzept für parallele Systeme
Energy Efficient Multi Channel Design for ClusteredWireless Sensor Networks
Life-Inspired Systems and Their Quality-Driven Design
Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling
MUTABOR, ein Co-Prozessor zur objektorientierten Speicherverwaltung
Bluetooth Scatternet Formation - State of the Art and a New Approach
Application Specific Reconfigurable SoC Interconnection Network Architecture
Accelerating WebAssembly Interpreters in Embedded Systems Through Hardware-Assisted Dispatching
Detecting Compromised Programs for Embedded System Applications
On-the-Fly CT Image Pre-processing on MPSoC-FPGAs
Evaluating Dynamic Task Scheduling with Priorities and Adaptive Aging in a Task-Based Runtime System
Energy Management System as an Embedded Service: Saving Energy Consumption of ICT
Cryptonite - A Programmable Crypto Processor Architecture for High-Bandwidth Applications
Evaluation of Run-Time Reconfiguration for General-Purpose Computing
Magnetic bubbles as a computer technology
A Concept for the Dependable Operation of Autonomous Robots by Means of Adaptive Fuzzy Rules
An Architecture for the Integration of Physical and Informational Spaces
Alternative Recherarchitektur für Datenübertragungs-Controller mit hohen Datenraten
Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings
Leistungsanalyse für lokale dateiorientierte Massenspeicher auf der Basis des linearen Dateisystems
Self-Organizing, Adaptive Data Fusion for 3d Object Tracking
Cache Write-Back Schemes for Embedded Destructive-Read DRAM
The Organic Features of the AMIDAR Class of Processors
Background Data Acquisition and Carrying: The BlueDACS Project
Reflection Processes Help Integrate Simultaneous Self-Optimization Processes
Leistungsfähigkeit von Mehrrechnerprozessorsystemen mit iAPX 432-Prozessoren, Kreuzzschienenverteiler und Pufferspeichern
Structured design for structured architecture
Über die EA-Programmierung bei einem Zweiprozessorsystem
Fast Scenario-Based Design Space Exploration using Feature Selection
Feedback-Based Admission Control for Hard Real-Time Task Allocation Under Dynamic Workload on Many-Core Systems
A Generic Tool Supporting Cache Designs and Optimisation on Shared Memory Systems
Programmierumgebung für Mobile Agenten in heterogenen Workstation-Clustern
Analyse eines LAN Netzverkehrs im Hinblick auf Modellierbarkeit von Protokollabläufen
Ein integriertes System zur Auftags-, Produktions- und Versandsteuerung von Aggregaten
Baumorientierte Kommuninkation in verteilten Systemen
UNIX-basierte Betriebssysteme für Multiprozessoren mit globalem Speicher
Adding Low-Cost Hardware Barrier Support to Small Commodity Clusters
Towards Multicore Performance with Configurable Computing Units
Reliability Modeling of Fault-tolerant Storage System - Covering MDS-Codes and Regenerating Codes
HOLOLINK: Ein konfliktfreies, holographisches Verbindungsnetzwerk hoher Übertragungsbandbreite für hochparallele Rechensysteme
Trustworthy Self-optimization in Organic Computing Environments
A Comparative Study of Neural Network Compilers on ARMv8 Architecture
Spend More to Save More (SM2): An Energy and Hardware-Aware Implementation of Successive Halving for Sustainable Hyperparameter Optimization
Reliability Considerations forMechatronic Systems on the Basis of a State Model
Redundancy Aware Clustering via Centroid Localization Technique
COLIBRI: Ein RISC-LISP-System
Ein Signalprozessor mit Wirt-Gast-Kopplung über gemeinsame Speicherbereiche
Definition of a Configurable Architecture for Implementation of Global Cellular Automaton
Efficient Parallel Fuzzy Dilation for Visual Reasoning on Edge: Leveraging ARM SIMD Extensions and Embedded GPUs Accelerators
Routing Based on Evolved Agents
Degrees of Single System Image
The Challenges of Multicore: Information and Mis-Information
A Network Perspective on Software Modularity
A RISC Processor with Extended Forwarding
Verkehrstheoretische Untersuchungen für die Zugriffe von Rechnerkernen auf einen verschränkten Arbeitsspeicher
Error-Correcting Codes in Steganography
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM
Improving Cache Locality for Ray Casting with CUDA
Architecture of Computing Systems - ARCS 2011 - 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings
Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables
Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
A Heterogeneous and Reconfigurable Embedded Architecture for Energy-Efficient Execution of Convolutional Neural Networks
M 2 E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors
Levels in Configurability for CRC Calculation
Kapselung mobiler Programme
Systems Aspects in Organic and Pervasive Computing - ARCS 2005, 18th International Conference on Architecture of Computing Systems, Innsbruck, Austria, March 14-17, 2005, Proceedings
Transaktionsorientierte Datenverwaltung in einem intelligenten Disk Controller
Cache Controller Design on Ultra Low Leakage Embedded Processors
Keynote: Microprocessor Architectures for the Mobile Internet Era
HeaRT: High Performance Routing Table Look up
Deadlock Problems in Computer Systems
Fail*: Towards a Versatile Fault Injection Experiment Framework
DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip
VIA2SISCI - A New Library that Provides the VIA Semantics for SCI Connected Clusters
Effective FPGA Architecture for General CRC
Modelling Cryptonite - On the Design of a Programmable High-Performance Crypto Processor
Scalability Evaluation of a Polymorphic Register File: A CG Case Study
Rechnerstrukturen und Betriebsprogrammierung
A Cache Design for a Security Architecture for Microprocessors (SAM)
The Bio-Chemical Information Processing Metaphor as a Programming Paradigm for Organic Computing
NDNET: A Unified Framework for Anomaly and Novelty Detection
A Multiprocessor Cache for Massively Parallel SoC Architectures
Recovery Management in a Transaction Oriented Distributed Operating System
X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs
Robust Scheduling in a Self-Organizing Hierarchy of Autonomous Virtual Power Plants
Task Variants with Different Scratchpad Memory Consumption in Multi-Task Environments
Colibri: Ein Testfall für die RISC-Philosophie
Dynamic Data Dissemination Technique for WSN
Reducing System Level Power Consumption for Mobile and Embedded Platforms
Towards the Online Reconfiguration of a Dependable Distributed On-Board Computer
Validation in Top Down Design Including Test Pattern Generation
Parallele Ausführung sequentieller Programme auf Multiple Processing Systems
Domänen und Lokalitäten im DAS-Betriebssystem
An Approach to Fault-Tolerant Clock Synchronization for Wireless Local Area Networks
Architecture of a Parallel MOSFET Parameter Extraction System
Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-Specific Multi-core SoCs
Compiler-Directed Performance Model Construction for Parallel Programs
Zur Parallelverarbeitung von arithmetischen Ausdrücken
Towards Unified Dependability Modeling and Analysis
Reduction of Average-Performance Degradation and Variance in Faulty CPU Cache Memories
CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms
Security in a Persistent Distributed Operating System
Power Monitoring for Mixed-Criticality on a Many-Core Platform
Apricot Agent Platform for User-Friendly Mobile Service Development
Quantum Computers and Their Simulation
Architekturkonzepte für massiv-parallele, opto-elektronische Rechnersysteme
Die Architektur einer parallelen Ausbildungsmaschine
Architecture of Computing Systems - ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 20-23, 2019, Proceedings
Evaluation and Refinement of a Tuning Tool for Grid Applications
AI-Based Computer Vision Methods to Monitor Emission-Relevant Parameters in Livestock Barns
FingerMouse - A Button Size Visual Hand Tracking and Segmentation Device
Architecture of Computing Systems - ARCS 2014 - 27th International Conference, Lübeck, Germany, February 25-28, 2014. Proceedings
Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems
Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors
Trade-Off Between Performance, Fault Tolerance and Energy Consumption in Duplication-Based Taskgraph Scheduling
System Architectures for Functional Programming Languages: Problems and Solutions(eingeladener Vortrag)
Efficient Transaction Nesting in Hardware Transactional Memory
Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting
Schrittweise Verfeinerung von Konzepten - Konstruktion Verteilter Systeme am Beispiel OlDiLa und Mach
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures
An Approach to Enhance Loop Performance for Multicluster VLIW DSP Processor
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration
A Context System for a Mobile Service Platform
Eine flexible Entwurfsumgebung für RISC-änliche Prozessorarchitekturen
Self-healing Execution of Business Processes Based on a Peer-to-Peer Service Architecture
Network-on-Chip basierende Laufzeitsysteme für dynamische rekonfigurierbare Hardware
Ternary Signed Digit Addition on Field Programmable Gate Arrays
Logic Self Repair
An Ad-Hoc Wireless Network Architecture for Face-to-Face Mobile Collaborative Applications
Anwendbarkeitsanalyse eines rechnerinternen Bussystems mit optisch parallelen Streifenleitern (OPSP)
A Systolic Algorithm for the Generalized Transitive Closure
Eine virtuelle Speicherorganisation für Prozeßrechner mit mittlerer Wortlänge
FALP: A Fault Adaptive and Low Power Method for Network on Chip Router
Platform-independent modeling of explicitly parallel programs
Error Codes in and for Network Steganography
Leistungsbewertung der Parallelrechner von Cray, IBM, Alliant und Convex
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3
A Two-Tier Design Space Exploration Algorithm to Construct a GPU Performance Predictor
Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator
Ein Assoziativspeicherfeld hoher Kapazität im Slice-Prozessor AM 3
Ein Transaktionskonzept für ein Betriebssystem mit virtuellem Speicher
Implementing Control Algorithms Within a Multithreaded Java Microcontroller
Compact and Testable Circuits for Regular Functions
A fast access algorithm for cellular dynamic memories
He..ro DB: A Concept for Parallel Data Processing on Heterogeneous Hardware
Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations
Adaptivity for Quality and Timeliness Flexible Real-Time Systems
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter
Design of Peripheral Interfaces for Embedded Control Systems
On the problem of fast random and sequential data access in shift register memories
Concurrent Phase Classification for Accelerating MPSoC Simulation
A Lightweight API for an Adaptive Software Fault Tolerance Using POSIX-Thread Replication
Konzepte der Mikroprogrammierung
MxGPU: A Case Study on OS-Controlled GPGPU Multiplexing
Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings
A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components
Exploiting Outer Loops Vectorization in High Level Synthesis
Funktionsorientierte Hardware für Datenbanksysteme
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs
Simultaneously Exploiting Dynamic Voltage Scaling, Execution Time Variations, and Multiple Methods in Energy-Aware Hard Real-Time Scheduling
Digital On-Demand Computing Organism for Real-Time Systems
Scheduling for a Modular Activity Recognition System to Reduce Energy Consumption on SmartPhones
Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning
Utility-Based Scheduling of (m, k) -Firm Real-Time Task Sets
Ant Colony Optimization for dynamic Traveling Salesman Problems
On Deadlocks and Fairness in Self-organizing Resource-Flow Systems
Trends in Local Communication Systems
Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur
DCMA-DSP: Ein fehlertolerantes Digitales Signalverarbeitung-System
Locality: The 3rd Wall and the Need for Innovation in Parallel Architectures
Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector
Efficient Acknowledgement and Retransmission Techniques for Bus-Systems
Instrumentenrechner für interplanetare Missionen
Simulation und Rechnung bei der Durchsatzoptimierung für gemessene, technisch-wissenschaftliche Aufgabenprofile
HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation
Non-preemptive Scheduling of Real-Time Software Transactional Memory
Post-Silicon Customization Using Deep Neural Networks
A Distributed SAT Solver for Microcontroller
Steuerung von Ein/Ausgabeschnittstellen in Zusammenarbeit mit mikroprogrammierten Ein/Ausgabeprozessoren
Software Shared Memory Communications with InfiniBand
Effective Performance Metrics for Evaluating Activity Recognition Methods
Minimising the Hardware Resources for a Cellular Automaton with Moving Creatures
A Perfomance Study of Parallel Cauchy Reed/Solomon Coding
Keynote: Autonomic Computing Initiative
Multiprozessoren für breite Anwendungsbereiche: Erlangen General Purpose Array
Ein Coprocessor Communication System als Basis für modulare Workstations
Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories
A Hardware Packet Re-Sequencer Unit for Network Processors
DIGORGAO - A Digital Problem Solution Concept
Concepts and Experiments for Optimizing Wide-Input Streaming CRC Circuits
Empirical Performance Models for Java Workloads
Delivering Guidance Information in Heterogeneous Systems
Activity Recognition Using Inertial Sensing for Healthcare, Wellbeing and Sports Applications: A Survey
Simplified Commissioning and Maintenance for Wireless Sensor Networks: a Novel Software Tool
HighRobot: Distributed Objekt-Oriented Real-Time Systems
Towards a Selforganized Control of Wireless Multihop Ad Hoc Communication Networks
Definition of a Regular and Configurable SIMD Architecture for Image Processing Accelerators
An Energy Consumption Model for an Embedded Java Virtual Machine
Integration von Multiprozessorarchitektur, Systemsoftware und Werkzeugumgebung
Context Source: A Smartphone Application for Serving Context to a Generic Context Provisioning System
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation
Choosing the best wireless protocol for typical applications
Evaluating a Priority-Based Task Distribution Strategy for an Artificial Hormone System
GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications
Extension of 2-Bit Error Correcting BCH Codes with Simple Decoding
Context-Based Storage Management for Wearable and Portable Devices
Software Architecture-Based Adaptation for Pervasive Systems
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model
A Novel Routing Architecture for Field-Programmable Gate-Arrays
Network Coding in Networks-on-Chip with Lossy Links
SCOPE - Sensor Mote Configuration and Operation Enhancement
Rediscovery of buried ideas from the pioneer age of computers
Security Improvements by Separating the Cryptographic Protocol from the Network Stack onto a Multi-MCU Architecture
Investigation of L2-Cache Interferences in a NXP QorIQ T4240 Multi-core Processor
Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution
Design Space Navigation for Neighboring Power-Performance Efficient Microprocessor Configurations
Conceptual Integration of Security Management in Designing Context-aware Environments
ART Networks as Flexible Means to Implement Dependability Properties in Autonomous Systems
Ein Transputer-System mit hybrider Kopplung als Kommunikationswerk für HSLAN-Anwendungen
Ein Hardware-Monitor zur Durchsetzung von Zugriffsschutz in objektorientierten Systemen
Eine Taskorganisation für reaktionsschnelle Prozeßrechensysteme
Fast Online Placement in FPGAs
CapLibrate: Self-Calibration of an Energy Harvesting Power Supply with Supercapacitors
Generation of Distributed Arithmetic Designs for Reconfigurable Application
Accurate Sample Time Reconstruction for Sensor Data Synchronization