yusuke1997/dblp-id-title huggingface dataset:
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture
Pseudo Kronecker Expressions for Symmetric Functions
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic
Hardware Accelerator for Capsule Network based Reinforcement Learning
Automatic Insertion of Gated Clocks at Register Transfer Level
Impact of Temperature on Test Quality
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access
An Acceleration and Optimization Method for Optical Reconfiguration
A CORDIC Based Programmable DXT Processor Array
Post Assembly Timing Closure for Multi Million Gate Chips
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications
Design and Simulation of Structurally Decoupled 4-DOF MEMS Vibratory Gyroscope
A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen Concentrators
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets
Applicability of General Purpose Processors to Network Applications
Formal Verification of Modules under Real Time Environment Constraints
Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI)
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems
An Adaptive Interconnect-Length Driven Placer
Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I DDQ Testing in BiCMOS and CMOS Circuits
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms
Extending Platform-Based Design to Network on Chip Systems
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors
Design Considerations for a Flat Panel Controller
Compact MOSFET Models for Low Power Analog CMOS Design
A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing Applications
FPGA Implementation of an Improved Watchdog Timer for Safety-Critical Applications
Set-Cover Heuristics for Two-Level Logic Minimization
Delay Fault Test Generation with Cellular Automata
A PLA-Based FSM Design Technique
Fpga Hardware Synthesis From Matlab
On the Detection of Reset Faults in Synchronous Sequential Circuits
Criticality based Reduction of Security Costs in a FPGA based Cloud Computing Farm
Generation of search state equivalence for automatic test pattern generation
Gateway to Chips: High Speed I/O Signalling and Interface
Fast computation of MISR signatures
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits
Embedded Complex Floating Point Hardware Accelerator
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic
Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata
A Comparison of Approaches to Carrier Generation for Zigbee Transceivers
Power Management of Interactive 3D Games Using Frame Structures
A Provably Good Algorithm for k -Layer Topological Planar Routing Problems
A Designer's Perspective on VLSI Tools and Methodology
A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design Tasks
Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors
Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design
Invited Address: Integrated Memory/Logic Architecture for Image Processing
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration
Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable Folded
On Test Compaction Objectives for Combinational and Sequential Circuits
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
SoC Design Methodology: A Practical Approach
A Cube-Aware Compaction Method for Scan ATPG
Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links
On Testability of Differential Split-Level CMOS Circuits
On Maximum Current Estimation in CMOS Digital Circuits
FAMAS: FAult Modeling via Adaptive Simulation
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Low-Power and Superior Performance Design of Ternary Logic Cells Using CNFET and MOSFET Devices for VLSI Applications
Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices
Routing on Switch Matrix Multi-FPGA Systems
Hardware/Software Co-design of a High-end Mixed Signal Microcontroller
Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints
Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier
A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation
Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques
Medium access control and air-interface subsystem for an indoor wireless ATM network
Linear Required-Arrival-Time Trees and their Construction
Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment
Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique
Delay-Aware Control for Autonomous Systems
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs
A Reduced Complexity Algorithm for Minimizing N-Detect Tests
DC-DC Converter for Powering Micro-system Load in Energy Harvesting Front-ends
A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta Modulator
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations
A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
Proceedings of the Seventh International Conference on VLSI Design, VLSI Design 1994, Calcutta, India, January 5-8, 1994
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
Ultra low power digital signal processing
Test Generation for Analog Circuits Using Partial Numerical Simulation
Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network
Transition Inversion Based Low Power Data Coding Scheme for Buffered Data Transfer
Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters
Cellular automata based architecture of a database query processor
Optimization Techniques for Pipelined Scheduling
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
Low Power Techniques for Portable Real-time DSP Applications
Power-aware Multimedia Systems using Run-time Prediction
Shake And Bake: A Method of Mapping Code to Irregular DSPs
Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment
Multi-Object Detection Through Meta-Training in Resource-Constrained UAV-Based Surveillance Applications
Rational ABCD Modeling of High-Speed Interconnects
Formal synthesis of circuits with a simple handshake protocol
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs
Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach
A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems
Two-Pattern ∆IDDQ Test for Recycled IC Detection
Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet Transform
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract)
Reconfigurable Computing
A Placement Methodology for Robust Clocking
At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies
High-Speed On-Chip Event Counters for Embedded Systems
Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips
Hot Spots and Zones in a Chip: A Geometrician's View
Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs
Minimization of Switching Activity of Graphene Based Circuits
Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA
Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications
An Embedded Processor for Integrated Navigation Receiver
A Novel SMT-Based Technique for LFSR Reseeding
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design
Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation
An improved output compaction technique for built-in self-test in VLSI circuits
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area
CAD Techniques for Embedded System Design
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization
Power Constraint Scheduling of Tests
Design, Fabrication, Testing and Simulation of Porous Silicon Based Smart MEMS Pressure Sensor
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors
An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design
At-speed Testing of Asynchronous Reset De-assertion Faults
Formal Verification of Power Management Logic with Mixed-Signal Domains
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design
The Design of A Digital IC for Thyristor Triggering
Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation
Substrate Bias Effect on Cycling Induced Performance Degradation of Flash EEPROMs
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays
DFX and Productivity
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation
Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing
26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013
Design of an Optimized CMOS ELM Accelerator
A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization
Analog Circuits for Wireless Communications
A 0.8V, Tri-State Inverter based SRAM Cell for SoC Applications
Interconnect Modeling for Copper/Low-k Technologies
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends
A method to accurately simulate and detect transition time instants in piecewise linear SMPS circuits
Efficient SAT-Based Circuit Initialization for Larger Designs
Efficient Heap Data Management on Software Managed Manycore Architectures
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias
Narrow Band Noise Suppression Scheme for improving Signal to Noise Ratio
A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors
A Real Time Multi-Bit DAC Mismatch Estimation & Correction Technique For Wideband Continuous Time Sigma Delta Modulators
Partitioning Routing Area into Zones with Distinct Pins
Extraction of Aspect Ratio for Non-Manhattan CMOS Devices
SoC - The Road Ahead
Design And Fabrication Of GaAs 2-input Nor Gate
Keynote Talk: The Variability Expeditions: Exploring the Software Stack for Underdesigned Computing Machines
On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules
An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load
A Low-Voltage Low Power CMOS Companding Filter
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems
A Method to Estimate Slew and Delay in Coupled Digital Circuits
Nanostructured Silicon Oxide Immunosensor Integrated with Noise Spectroscopy Electronics for POC Diagnostics
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay
Faster Fault Simulation Through Distributed Computing
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells
Obstacle Avoiding Rectilinear Clock Tree Construction with Skew Minimization
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory
An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach
Reusing Learned Information in SAT-based ATPG
Keynote: Technology directions for a bright semiconductor future
Optimum retiming of large sequential circuits
Embedded Systems Design Using FPGA
An Architecture for Motion Estimation in the Transform Domain
Choice of Tests for Logic Verification and Equivalence Checking
Behavioral Design and Prototyping of a Fail-Safe System
CASHIER: A Cache Energy Saving Technique for QoS Systems
Tutorial T2A: Scheduling Issues in Embedded Real-Time Systems
Inductive Noise Reduction at the Architectural Level
A Single Inductor, Single Input Dual Output (SIDO) Piezoelectric Energy Harvesting System
AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation
A Game-Theoretic Approach for Binding in Behavioral Synthesis
Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration
Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update
The Impact of Inductance on Transients Affecting Gate Oxide Reliability
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
CFSMcharts: A New Language for Microprocessor Based system Design
Technology CAD: Technology Modeling, Device Design and Simulation
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines
A simple yet effective genetic approach for the orientation assignment on cell-based layout
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits
An HOL based framework for design of correct high level synthesizers
Dataflow Analysis for Resource Contention and Register Leakage Properties
Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical Receivers
Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM
Design tradeoffs in high speed multipliers and FIR filters
Dynamic Noise Margin: Definitions and Model
Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis
Design and Implementation of a Parallel Verilog Simulator: PVSim
Comparative Study of Analog Matching Structures in 28FDSOI
Design Methodology of Low Phase Noise mmWave Oscillator with Partial Cancellation of Static Capacitance of High-Q On-chip MEMS Resonator
Negative Feedback System and Circuit Design
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management
Probabilistic Analysis of Rectilinear Steiner Trees
A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms
Distributed Logic Simulation Algorithm using Preemption of Inconsistent Events
Efficient Translation of Statecharts to Hardware Circuits
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSI Implementation of DSP Architectures
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques
Data-Driven Resiliency Solutions for Boards and Systems
Random Access Scan: A solution to test power, test data volume and test time
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability
Tunnel Magnetoresistance in Strained L10-FeAu Perpendicular Magnetic Tunnel Junction
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems
Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks
A Scalable and Reconfigurable Coprocessor for Image Composition
Analyzing Controllability of a Hardware Circuit for its Reuse
Efficient Trace Signal Selection for Post Silicon Validation and Debug
Screening of Hot Electron Effect During Plasma Processing
ACE: A VLSI Chip for Galois Field GF (2 m ) Based Exponentiation
Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader
Advancing Rehabilitation Through Low Weight Hand Assistive System: Design and Impact Analysis
Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels
ASPIRE: An Intermediate Representation for Abstract Security Policies
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops
Techniques for very low-voltage operation of continuous-time analog CMOS circuits
Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components
Floorplanning for Partial Reconfiguration in FPGAs
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware
Performance Driven Synthesis for Pass-Transistor Logic
Early Exploration of the Multi-Dimensional VLSI Design Space
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering
Scaling, Power and the Future of CMOS
Timing Analysis with Implicitly Specified False Paths
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units
Thermal Crosstalk Analysis in ReRAM Passive Crossbar Arrays
VLSI Design 2006 Conference Awards
Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory Cells
A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells
Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing
Minimum Partition for the Space Region of VLSI Layout
On-chip testing of embedded transducers
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks
Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA
The Future of Low Power Design is Here: IEEE P1801, aka, UPF 2.0
A Low-Power Circuit for Adaptive Dynamic Programming
Low Power Single Amplifier Voltage Regulator
Identifying Redundant Wire Replacements for Synthesis and Verification
A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology
Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits
Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles
A 1.8GHz Digital PLL in 65nm CMOS
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation
On Routing Demand and Congestion Estimation for FPGAs
Algorithmic Macromodelling Methods for Mixed-Signal Systems
QUICKRECALL: A Low Overhead HW/SW Approach for Enabling Computations across Power Cycles in Transiently Powered Computers
Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield
COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems
38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, VLSID 2025, Bangalore, India, January 4-8, 2025
Multiple Fault Testing in Analog Circuits
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect
Eliminating Performance Penalty of Scan
A Complete Characterization of Path Delay Faults through Stuck-at Faults
A SPICE Model of RLGC Transmission Line with Error Control
Application Specific Macro Based Synthesis
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors
Towards The Complete Elimination of Gate/Switch Level Simulations
Symmetry-Based Synthesis for Interpretable Boolean Evaluation
Using Dedicated Functional Simulator for ASIC Design in Indian Context
Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios
Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization
A Novel Low-Power Electronically Tunable Higher-Order Quadrature Oscillator using CDBA
Maximum Multiplicity Distributions for Length Prediction Driven Placement
A Low Power Reprogrammable Parallel Processing VLSI Architecture for Computation of B-Spline Based Medical Image Processing System for Fast Characterization of Tiny Objects Suspended in Cellular Fluid
A New Methodology for Concurrent Technology Development and Cell Library Optimization
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter
mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic
Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression
Secure Neural Circuits to Mitigate Correlation Power Analysis on SHA-3 Hash Function
Sequential Equivalence Checking
IP Reuse in System on a Chip Design
A Low-Power, Low-Noise, High-Performance Re-Convergent Clock Mesh Design for Large AI Compute Clusters
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation