yusuke1997/dblp-id-title huggingface dataset:
Asymmetric Prefetching Architecture for Multicore Processor
Perspectives on 3D ToF sensor SoC integration for user interface application
An Evaluation of Edge Computing Platform for Reliable Automated Drones
Elliptic OTA-C Low-Pass Filters for Analog Front-End of Biosignal Detection System
A Distance-Aware Technique for Object Detection Used in Self-Driving Vehicles
HDR Image Generator Focused on Saturated Region Restoration with Contextual Loss
Investigation of Synchronization Phenomena in Coupled Two-degrees-of-Freedom Chaotic Circuits
Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless Systems
Optimizing and Addressing Stitch Challenges in High-NA EUV Lithography for Large Die Designs
A 12.8-Gb/s/lane, 1.03-pJ/b Transmitter With Reconfigurable Charge-Injecting Crosstalk Cancellation For Capacitively Coupled High-Density Interconnects
Rewiring Effect of High Synchronization Edges in Complex Oscillator Networks
Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip
Performance Metrics of Inexact Multipliers Based on Approximate 5: 2 Compressors
Scheduling of Malleable Tasks with DMA-based Communication
A novel high precision SDR-based positioning system
Alleviating Deduplication-oriented Fragmentation of SSDs by Considering File Hotness and Popularity
Radio-frequency energy-harvesting IC with DC-DC converter
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges
Chaotic circuits network with scale-free coupling distribution
Equalization scheme analysis for high-density spin transfer torque random access memory
Low-Cost Dual-Band Active Transponder for SAR Satellites Calibration
A 8-bit DPWM-based Analog Bypass Circuit and System for LED Matrix Headlamp in High-Voltage 180-nm CMOS Technology
Motion vector smoothing of boundary of moving object for frame rate up-conversion
Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection
Low-Complexity High-Performance Method for Calculating Arbitrary Logarithm Function
Research activities on reconfigurable systems in Japan
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface
Recent Trend of Neuromorphic Computing Hardware: Intel's Neuromorphic System Perspective
Maximum Efficiency Tracking for Wireless Power Transfer with Multiple Receivers
A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver
A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits
Implementation of the XY2-100 protocol on low-cost microcontroller
Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy
A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique
A 28-GHz 28.5-dBm power amplifier using 0.15-µm InGaAs E-mode pHEMT technology
An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead
A 30-Gb/s PAM-8 Transmitter with a 2-Tap Feed-Forward Equalizer and Background Clock Calibration
Reconfigurable Cell-Based Systolic Array Architecture for CNN Training Accelerator for Mobile Applications
Low power consumption for detecting current zero of synchronous DC-DC buck converter
Lowering the Number of Live-Page Copies on Solid State Drives through Trim-Assisted Space Allocation
A Fast Eye Size Evaluation Method for High Speed Signal
Radio frequency energy harvesting technology
A 60GHz BiCMOS self-demodulator with injection locked oscillator
Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification
A low-cost architecture for multi-mode Reed-Solomon decoder
Low-complexity filter and interpolator design for ATSC DTV systems
Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset
Data Protection Method for Flash Memory in Serial Peripheral Interface
Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation
A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer
An EEG Analog Front-End Unit for Wearable Applications Implemented in 28nm FD-SOI
A Fast-Lock All-Digital PLL with a TDC-based FLL
Attack sensing against EM leakage and injection
Dynamic load balancing algorithm for system on chip
FPGA-Controlled High-Power Driving Design for High Intensity Focused Ultrasound Application
Peak Variation Detection Using Variable Length Moving Average Filter for Defects Inspection Systems
Computation of homoclinic points using particle swarm optimization in 2-dimensional discrete dynamical systems
PEMAC: A Posit EM AC with LDD and Logarithm Approximation
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test
ASIC Implementation of Magnetic Induction based Wireless Communication System
A 5.8 GHz RF-DC Based Energy-Harvesting Front-End with a Load-Lighting LC-Oscillator Based Voltage Booster for a SWIPT IC
A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator
Design of Bessel-like filter-based ESD protection I/O pad with improved eye performance
Beyond UVM for practical SoC verification
Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure
SiGe BiCMOS technology for mm-wave systems
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system
2T Neuromorphic Device based on oxide semiconductor with High Linearity and Symmetry for High-Precision Training
An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture
Development of SoC virtual platform for IoT terminals based on OneM2M
Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis
Design of Road Surface Lighting System for Rear Lamp using Automotive Ultrasonic Sensor
An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication
Feature Extraction of Neuron Group Composed of Two Different Firing Patterns Using Nonlinear Analysis
A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing
High-accuracy and Low-latency Hybrid Stochastic Computing for Artificial Neural Network
Load-Independent Inverse Class-E Oscillator with Armstrong-Oscillator Based Topology
High-throughput turbo decoder design with new interconnection network for LTE/LTE-A system
-23.5dBm senstivity, 900MHz differential-drive rectifier
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators
A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer
An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs
A design of dual-band smart tag
Alert Refresh System for Mitigating RowHammer
Hiding Precharge Operation For Improved SRAM Cycle Time
Ultra-low power and low voltage circuit design for next-generation power-aware LSI applications
An Effective Neural Network Model Protection Method Against Model Stealing Attacks for Image Classification Applications
An acquisition method of distance information in direction signs
3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent Equalization
Design of asynchronous SAR ADC for low power mixed signal applications
Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect
Communication Performance Depending on LED Installation Position in Image Sensor Communication Using Propeller LED Transmitter
Adaptive Granularity On-die ECC
Design of millimeter-wave CMOS frequency tripler
Integrated Passive Device based RF circuit design for low-cost System-in-Package transceivers
Signal-dependent analog-to-digital converter based on MINIMAX sampling
A Robust and Lightweight Environmental Sound Classification Technique with Adaptation to Microphone for AIoT Sound Sensing
A sub-threshold ultra-low power low-dropout regulator
Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits
Standard cell library establishment and simulation for scan D flip-flops based on 0.5 micron CMOS mixed-signal process
A wide dynamic range CMOS image sensor based on a new gamma correction technique
A Wideband Differential Low Noise Amplifier for TVWS Applications in 130 nm CMOS Technology
A leakage reduced HVIC with coarse-fine UVLO
A study on improvement of recognition accuracy by applying machine learning algorithms to the vision-based traffic condition analysis system
Low-power non-coherent data and power recovery circuit for implantable biomedical devices
Adaptive approximate adder (A 3 ) to reduce error distance for image processor
Nonlinear Time Series Analysis of Coupled Bursting Neuron Model Depending on Coupling Strength
A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain
A 12.5-Gb/s Switched Capacitor Based Two Tap DFE With High BER Performance
Continual Learning for Instance Segmentation to Mitigate Catastrophic Forgetting
MEMS resonator based thermometer SoC design in CMOS 0.18 μm standard process
A programmable ΔΣ SAR-ADC with charge shuttling technique
Self-Supervised Contrastive Representation Learning for Time-Series Classification
SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access
A High-Performance, Low-Power 8-Bit Full-Adder Using 8 + T Differential SRAM for Computation-inMemory
Enhancing circuits and systems supply noise sensitivity characterization using on-package droop inducers
A learnable network of analog electronic neuron models for brain prosthetic implant
Design of a configurable bit-resolution CMOS image sensor for the image depth extraction
Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology
Design of LED driver using digital up/down counter
Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory Design
A DLL-based FSK demodulator for 5.8GHz DSRC/ETC RF receiver
2-D Failure Bitmap Compression Using Line Fault Marking Method
The Effects of Timing Error Sources in Wireless Multi-Unit Off-Line Acquisition Systems
Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS
High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications
LightNet: A Lightweight Neural Network for Image Classification
Design of a 400-MHz 1-V 1.4-mW CMOS RF receiver for MICS applications
Nonlinearity Analysis of Resistive Ladder-Based Current-Steering Digital-to-Analog Converter
Multi-Channel Input Deep Convolutional Neural Network for Mammogram Diagnosis
Redundant-dictionary based adaptive sampling for transient ECG signal measurement
Robust AES circuit design for delay variation using suspicious timing error prediction
Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel
36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector
Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips
FPGA-based transceiver circuit for labeling signal transmission system
Human-Inspired Camera: A Novel Camera System for Computer Vision
A DC to 14GHz fully differential amplifier for wideband low power applications
A Neuromorphic SLAM Accelerator Supporting Multi-Agent Error Correction in Swarm Robotics
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector
Energy-efficient high-level synthesis for HDR architectures with clock gating
Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks
Real-Time Characteristics Identification for Partial Shaded Photovoltaic Strings
An Estimation Method for Controlling Unstable Periodic Orbit Without Using Poincaré Map
Real-time Implementation of l -key Pose Estimation for Driver Behavior Analysis
A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC
Design and Analysis of Compound Gates for Lightweight Multiplier
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer
Tcl-based Simulation Platform for Light-weight ResNet Implementation
Fast 3D Hand Pose Estimation for Real-time System
High-speed EEG-Based Brain-Computer Interface with Wide Dynamic-range ADC
An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOX
Memristor Circuits for Non-Backpropagation Training Algorithm
High density PCM(phase change memory) technology
13.56 MHz High-Efficiency Power Transmitter and Receiver for Wirelessly Powered Biomedical Implants
A Long-Term Synchronized System for Healthcare
Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator
Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems
20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023
Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy
A low cost soft mapper for turbo equalization with high order modulation
Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors
Integration of IP-Cores for the M 3 Architecture with Low Area Overhead: Accelerator Support Module
Infrared and Visible Image Fusion using Multi-Scale Decomposition and Visual Saliency Map
A Ka band FMCW Transmitter with a High Ratio Multiplier
The Influence Measures of Light Intensity on Machine Learning for Semantic Segmentation
Low-Complexity On-Device ECG Classifier using Binarized Neural Network
Area-efficient and high-speed binary divider architecture for bit-serial interfaces
A study on improvement of vision-based traffic condition analysis system by comparing feature data of images
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism
Power-efficient VCO-based ADCs for Wireless Communication Systems
Selective refresh to avoid read disturb errors in STT-RAM main memory
A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM
ISFET with built-in calibration registers through segmented eight-bit binary search in three-point algorithm using FPGA
The Impact of Coherent Signal Reception on Interferometric Angle of Arrival Estimation
Deep learning application trial to lung cancer diagnosis for medical sensor systems
A Reconfigurable Approximate Floating-Point Multiplier with kNN
Drivable Area Detection Method Capable of Distinguishing Vegetation Area on Country Road
Rethinking processor instruction fetch: Inefficiencies-cracking mechanism
Design of H.264 video encoder with C to RTL design tool
Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection
A 14-GHz-Band Low-Supply-Voltage Low-Phase-Noise LC-VCO IC with Harmonic Tuned LC Tank in 45-nm CMOS SOI
A Haar Classifier Accelerator with Reduced Multiplexer Usage
Enhanced Image Classification through Layer-Wise Feature Concatenation in Deep Neural Networks
A MDLL-based multi-phase clock multiplier
Implementation of a low-overhead processing-in-memory architecture
Long-Length Accumulation Unit with Efficient Biasing for Binary Weight CNNs
Pointing error effect in FSO satellite-to-ground under weak turbulence condition
Enhancement of Emulation Usage for NVMe Solid State Drive
An Analysis of Current-mode Drivers in 40-nm CMOS Technology
Kyber Accelerator on FPGA Using Energy-Efficient LUT-Based Barrett Reduction
Time-varying circuit approaches for software defined and cognitive radio applications
How to automate millions lines of top-level UVM testbench and handle huge register classes
High-speed transceiver network for in-vehicle communication system
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks
Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding
High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator
A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS
12 V PZE Harvesting Circuit For AUV Using Boost Converter with Resistor Matching Controller
Performance Optimization of Silicon Photonic Ring Switch with CMOS Driver
Channel-Wise Activation Map Pruning using Max-Pool for Reducing Memory Accesses
Review of low power image sensors for always-on imaging
Investigation on Synaptic Characteristics of Interfacial Phase Change Memory for Artificial Synapse Application
Analysis of Synchronization Phenomena in Complex Networks Consisting of van der Pol Oscillators
A selector-based FFT processor and its FPGA implementation
A flexible MCMC detector ASIC
Tone-based Measurement of Excess Group Delay in Programmable Gain Receiver Chains for RF Ranging
Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON Standard
Waveform Classification by Two-Layer Reservoir Computing with van der Pol Oscillators
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications
Design consideration for 60 GHz SiGe power amplifier with ESD protection
Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks
Design considerations for cognitive radio based CMOS TV white space transceivers
Design, analysis, tools and applications for programmable high-speed and power-aware 4G processors
A Wide-range Low Power Quarter Rate Single Loop CDR
A high-performance circuit design algorithm using data dependent approximation
Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSV
InP HBT voltage controlled oscillator for 300-GHz-band wireless communications
AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving
Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device
Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks
A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization
An Ultra-Low Power Wake-up Receiver Digital Controller for 5.8 GHz DSRC Applications
10-bit 250-KS/s M-2M Digital-to-Analog Converter with 4-4-2 Segmentation for Sonar System
Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications
A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE
Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)
Accurate Stochastic Computing Using a Wire Exchanging Unipolar Multiplier
A low-power, low-noise neural recording amplifier for implantable biomedical devices
Skin Deformation Deteciton Sensory System for AR Headset Hands-free Interface
Optical Receiver Front-end for Active Optical Cable in 180 nm CMOS
A High-Gain Transimpedance Amplifier Using Highly-Linear and Symmetric Multi-Stage Pseudo-Resistors
A Survey on Feature Point Extraction Techniques
Local and Global Activities of Izhikevich Neuron Model in Networks
Implementation of Real-time Simulation System for Li-ion Battery Protection Circuit Module
Optimization of clock mesh based on wire sizing variation
A 60GHz defected ground power divider using SiGe BiCMOS technology
Design of emotion recognition system using neuromorphic computing technique
IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization
Improved CAN compression algorithm by data reordering
An efficient JPEG decoding and scaling method for digital TV platforms
A Multiband Rectenna for Self-sustainable Devices
Power-efficiency estimation of exponential horn driver circuit for low-power optical link
16 x 10 Pressure Sensor CMOS Driver IC for Resistance Interfence Calibration of Cells
A 11mV single stage thermal energy harvesting regulator with effective control scheme for extended peak load
Low-Complexity DNN-Based End-to-End Automatic Speech Recognition using Low-Rank Approximation
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM
Hardware implementation of aggregated channel features for ADAS
Thermal-aware body bias modulation for high performance mobile core
Enhancing Event Extraction and Impact Analysis with Knowledge Graph Augmented Transformer
Implementation of Systolic Co-processor for Deep Neural Network Inference based on SoC
Real-Time Ultrasound Imaging System for Drone and Robotic Applications
Error-Resilient Binary Neural Network Inference with Selective Recompute-Based Error Correction
Design of filter tuning circuit to compensate band width change of band pass filter by process and temperature
A smart platform with cognitive techniques for narrowband power line communication
Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects
A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern
A CMOS buck converter with PFM / hysteretic mode
Comparative analysis of FinFET and Planar MOSFET SRAMs
Comparison of hardware-optimized CNN and SVM models for human activity recognition using the HARTH and HAR 70 + datasets
Front collision warning based on vehicle detection using CNN
Multi-carrier Signal Detection using Convolutional Neural Networks
Maintaining Images by Cellular Neural Networks with Switching Two Templates
Verification of an efficient Match-line Sense Amplifier for the High Frequency Search Operation
A Design of 5.8 GHz Ultralow-Power Wake-up Receiver: 14 kHz On Off Keying for DSRC Application
Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip Training
A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS
Current Mode Neuromorphic Implementation using Current Memory
Class Difficulty based Mixed Precision Quantization for Low Complexity CNN Training
Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs
Evaluating the Impact of In-band ECC on GPU Performance
Efficient Signal Processing Acceleration using OpenCL-based FPGA-GPU Hybrid Cooperation for Reconfigurable ECG Diagnosis
NP dynamic CMOS resurrection with carbon nanotube field effect transistors
Hardware implementation of fast high dynamic range processor for real-time 4K UHD video
Internal circuit offset auto compensation current sensor for wireless power systems
Power Consumption Analysis of a Fractional Approach to BANs Time Synchronization
A Review on Recent Development of Input Impedance Boosting for Bio-Potential Amplifiers
A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices
Sharpness-aware real-time haze removal for advanced driver assistance systems
Efficient and real-time stereo matching hardware architecture for high-resolution image
Image Radar Point Cloud Segmentation with Segment Anything Model
Spiking Neural Networks for digital hand-written number recognition
Redundancy Analysis Simplification Scheme for High-Speed Memory Repair
Design of CAN - CAN FD bridge for in-vehicle network
An Innovative I/O Budgeting Methodology for Hierarchical SoC Development
Design of high-speed support vector machine circuit for driver assistance system
WLAN transceiver for 802.11 a/b/g/n/ac with integrated power amplifier and harmonic LO frequency VCO
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition
A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process
LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography
High bandwidth memory(HBM) with TSV technique
Maximum Error-Aware Design of Approximate Array Multipliers
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications
TSV density-driven global placement for 3D stacked ICs
A novel radio propagation and radiation model of the wireless capsule endoscopy in human gastro-intestine (GI) tract