yusuke1997/dblp-id-title huggingface dataset:
Modeling and Evaluation of Substrate Noise Induced by Interconnects
Multi-clock Soc design using protocol conversion
Test Strategies for Low Power Devices
Analysis and Optimization of Worst-Case Time Disparity in Cause-Effect Chains
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks
SolarML: Optimizing Sensing and Inference for Solar-Powered TinyML Platforms
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture
Architecture Exploration of Parameterizable EPIC SOC Architectures
A wearable long-term single-lead ECG processor for early detection of cardiac arrhythmia
HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing
Operand size reconfiguration for big data processing in memory
SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells
Shared Memory Implementations of Synchronous Dataflow Specifications
HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable highly scaled FeFET
MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems
Extraction of Schematic Array Models for Memory Circuits
Design of low-complexity digital finite impulse response filters on FPGAs
Enabling Energy-Efficient Unsupervised Monocular Depth Estimation on ARMv7-Based Platforms
Creating 3D specific systems: Architecture, design and CAD
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors
Performance-driven dual-rail insertion for chip-level pre-fabricated design
Lightweight hardware support for selective coherence in heterogeneous manycore accelerators
Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware
A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform
LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling
Multi-Agent Reinforcement Learning for Thermally-Restricted Performance Optimization on Manycores
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction
High-speed C-testable systolic array design for Galois-field inversion
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack
Model checking of Scenario-Aware Dataflow with CADP
Formal consistency checking over specifications in natural languages
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction
Reducing Cache Access Energy in Array-Intensive Application
Instruction precomputation with memoization for fault detection
Design Optimization for Hardware-Based Message Filters in Broadcast Buses
Simulation of falling rain for robustness testing of video-based surround sensing systems
A low energy 2D adaptive median filter hardware
Post-placement temperature reduction techniques
Advanced Techniques for GA-based sequential ATPGs
Noise Figure Evaluation Using Low Cost BIST
High-speed clock recovery for low-cost FPGAs
Componentizing hardware/software interface design
Design-for-test methodology for non-scan at-speed testing
INTO-OA: Interpretable Topology Optimization for Operational Amplifiers
Neighbor-aware dynamic thermal management for multi-core platform
Mapping Applications to an FPFA Tile
NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA
Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar
Exploring Logic Block Granularity for Regular Fabrics
Scheduling under resource constraints using dis-equations
Inspiring trust in outsourced integrated circuit fabrication
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs
Design of voltage-scalable meta-functions for approximate computing
Tailored Solutions for Safety-Installations in the Loetschberg Tunnel - A Project with Importance for the Trans-European Rail Traffic
Thermal-aware datapath merging for coarse-grained reconfigurable processors
Acceptance and random generation of event sequences under real time calculus constraints
Electronic implants: power delivery and management
Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects
SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing
2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
A highly efficient full-system virtual prototype based on virtualization-assisted approach
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints
Design automation for quantum architectures
A Hardware-Assisted Approach for Non-Invasive and Fine-Grained Memory Power Management in MCUs
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Techniques to Evolve a C++ Based System Design Language
Optimization of FIR filter to improve eye diagram for general transmission line systems
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor
Multi-Partner Project: Shaping the Vehicle of the Future - How FEDERATE and HAL4SDV are Steering Europe's Software-Defined Vehicle Ecosystem
SigAttack: New High-level SAT-based Attack on Logic Encryptions
SKETCHILOG: Sketching combinational circuits
ACCLIB: Accelerators as libraries
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Architecture description language based retargetable symbolic execution
Triple Fixed-Point MAC Unit for Deep Learning
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
A tree arbiter cell for high speed resource sharing in asynchronous environments
New Techniques for Speeding-Up Fault-Injection Campaigns
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values
A new method to identify threshold logic functions
Hybrid simulation for extensible processor cores
Highly scalable parallel parametrizable architecture of the motion estimator
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example
Smart Knowledge Transfer-based Runtime Power Management
Automotive ethernet: in-vehicle networking and smart mobility
An extension of Cohn's sensitivity theorem to mismatch analysis of 1-port resistor networks
Automating processor customisation: optimised memory access and resource sharing
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors
An exact method for design exploration of quantum-dot cellular automata
Design of a low power, relative timing based asynchronous MSP430 microprocessor
Contract-based integration of automotive control software
Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns
Progress on carbon nanotube BEOL interconnects
Spinto: High-performance energy minimization in spin glasses
Statistical static timing analysis using Markov chain Monte Carlo
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design
A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC
Interactive presentation: Automatic model generation for black box real-time systems
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms
Prediction-based fast thermoelectric generator reconfiguration for energy harvesting from vehicle radiators
Floorplanning exploration and performance evaluation of a new Network-on-Chip
RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects
Analogue mixed signal simulation using spice and SystemC
Analog circuit test based on a digital signature
Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme
Integrating the Synchronous Dataflow Model with UML
A fast analog circuit yield estimation method for medium and high dimensional problems
Activity Packing in FPGAs for Leakage Power Reduction
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications
A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication
Buffering implications for the design space of streaming MEMS storage
FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators
Mission profile aware robustness assessment of automotive power devices
Frequent Access Pattern-based Prefetching Inside of Solid-State Drives
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip
Algorithms for the automatic extension of an instruction-set
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off
An open platform for mixed-criticality real-time ethernet
Two-level microprocessor-accelerator partitioning
Evaluating System Dependability in a Co-Design Framework
AdAM: Adaptive approximation management for the non-volatile memory hierarchies
Extending SSD Lifetime via Balancing Layer Endurance in 3D NAND Flash Memory
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
OLORAS: Online LOng Range Action Segmentation for Edge Devices
On Gate Flip Errors in Computing-In-Memory
Adaptive interference rejection in Human Body Communication using variable duty cycle integrating DDR receiver
On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers
Multispeculative additive trees in high-level synthesis
Energy-efficient scheduling of real-time tasks on cluster-based multicores
Side-channel attack on Rainbow post-quantum signature
Energy-aware cooling for hot-water cooled supercomputers
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm
ThingNet: A Lightweight Real-time Mirai IoT Variants Hunter through CPU Power Fingerprinting
An architecture-level approach for mitigating the impact of process variations on extensible processors
Fault-based attack of RSA authentication
Improving hamiltonian-based routing methods for on-chip networks: A turn model approach
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits
A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time
RTL Processor Synthesis for Architecture Exploration and Implementation
Routability Prediction using Deep Hierarchical Classification and Regression
LPSAT: a unified approach to RTL satisfiability
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
Testing PUF-based secure key storage circuits
JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits
Challenges of using on-chip performance monitors for process and environmental variation compensation
Demonstrating Post-Quantum Remote Attestation for RISC-V Devices
Vision for cross-layer optimization to address the dual challenges of energy and reliability
Slipstream: Semantic-Based Training Acceleration for Recommendation Models
III-V semiconductor nanowires for future devices
A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology
Task scheduling for many-cores with S-NUCA caches
Enhancing correlation electromagnetic attack using planar near-field cartography
Integration of orthogonal QBF solving techniques
Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration
Design Methodologies for System Level IP
Dr. Frankenstein's dream made possible: implanted electronic devices
Real-time anomaly detection for streaming data using burst code on a neurosynaptic processor
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs
Functional Coverage Metric Generation from Temporal Event Relation Graph
Group-caching for NoC based multicore cache coherent systems
Nanoelectromechanical Binary Comparator for Edge-Computing Applications
The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines
HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs
On-chip bus thermal analysis and optimization
Combining Formal Verification and Testing for Debugging of Arithmetic Circuits
Integrating symbolic and statistical methods for testing intelligent systems: Applications to machine learning and computer vision
Comfortable modeling of complex reactive systems
Post-Placement Residual-Overlap Removal with Minimal Movement
Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL
rACE: Reverse-Order Processor Reliability Analysis
Online workload monitoring with the feedback of actual execution time for real-time systems
Area optimization of multi-cycle operators in high-level synthesis
Holistic design parameter optimization of multiple periodic resources in hierarchical scheduling
Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems
Key-recovery attacks on various RO PUF constructions via helper data manipulation
PinT: Polynomial in Temperature Decode Weights in a Neuromorphic Architecture
The Use of Runtime Configuration Capabilities for Networked Embedded Systems
LAANT: A library to automatically optimize EDP for OpenMP applications
Resilience evaluation via symbolic fault injection on intermediate code
Correlating models and silicon for improved parametric yield
2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018
Towards a chip level reliability simulator for copper/low-k backend processes
Estimating delay differences of arbiter PUFs using silicon data
Automatic synthesis of compressor trees: reevaluating large counters
Dynamic partitioning strategy to enhance symbolic execution
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints
Impact of Test Point Insertion on Silicon Area and Timing during Layout
Evaluation of a new RFID system performance monitoring approach
Enhanced metamodeling techniques for high-dimensional IC design estimation problems
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network
MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications
Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance Sampling
An automated flow for integrating hardware IP into the automotive systems engineering process
A prototype VLSI chip architecture for JPEG image compression
Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs
On design of test structures for lithographic process corner identification
WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation
An Efficient Bit-Flip Resilience Optimization Method for Deep Neural Networks
Exploring specialized near-memory processing for data intensive operations
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs
Pushing the limits of voltage over-scaling for error-resilient applications
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits
Bounding Perception Neural Network Uncertainty for Safe Control of Autonomous Systems
Hardware-Assisted Ransomware Detection Using Automated Machine Learning
SUZANA: A 3D CAD Tool for Anisotropically Etched Silicon Microstructures
Automated test generation for Debugging arithmetic circuits
Profile Guided Management of Code Partitions for Embedded Systems
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints
Energy- and endurance-aware design of phase change memory caches
Properties of and improvements to time-domain dynamic thermal analysis algorithms
Quantum Measurement Discrimination using Cumulative Distribution Functions
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement
Hardware accelerator for analytics of sparse data
Q-learning Based Backup for Energy Harvesting Powered Embedded Systems
An algorithm to minimize leakage through simultaneous input vector control and circuit modification
Gemma in April: A matrix-like parallel programming architecture on OpenCL
Side channel analysis of the SHA-3 finalists
Grafted Trees Bear Better Fruit: An Improved Multiple-Valued Plaintext-Checking Side-Channel Attack Against Kyber
Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction
Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing
The concept of unschedulability core for optimizing priority assignment in real-time systems
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester
Internet-Based Collaborative Test Generation with MOSCITO
Thread-based software synthesis for embedded system design
Towards fully automated TLM-to-RTL property refinement
The Use of Microelectronics for Future Telecom and Multimedia Systems
A scalable GPU-based approach to accelerate the multiple-choice knapsack problem
Resistive Bridging Fault Simulation of Industrial Circuits
Accurate electrothermal modeling of thermoelectric generators
Interplay of loop unrolling and multidimensional memory partitioning in HLS
Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC
Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation
Adversarial Attack on Hyperdimensional Computing-based NLP Applications
A power-efficient migration mechanism for D-NUCA caches
A reconfigurable scan network based IC identification for embedded devices
Diagnosis, modeling and tolerance of scan chain hold-time violations
WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point
Towards an Embedded System for Failure Diagnosis in Drones Using AI and SAC-DM on FPGA
Pipette: Automatic Fine-Grained Large Language Model Training Configurator for Real-World Clusters
A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs
Modeling and integrating physical environment assumptions in medical cyber-physical system design
Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification
Cross disciplinary aspects (4G wireless special day)
A fast and resource efficient FPGA implementation of secret sharing for storage applications
A parallel Hamiltonian eigensolver for passivity characterization and enforcement of large interconnect macromodels
Odin: Learning to Optimize Operation Unit Configuration for Energy-efficient DNN Inferencing
Optically Interrogated Unique Object with Simulation Attack Prevention
Systematic Biasing of Negative Feedback Amplifiers
Statistical SRAM analysis for yield enhancement
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Using multifunctional standardized stack as universal spintronic technology for IoT
PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators
SegTransformer: Enhancing Softmax Performance Through Segmentation with a ReRAM-Based PIM Accelerator
Energy-Efficient Brain-Inspired Hyperdimensional Computing Using Voltage Scaling
A Method for the Efficient Development of Timed and Untimed Transaction-Level Models of Systems-on-Chip
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's
An efficient and portable scheduler for RTOS simulation and its certified integration to SystemC
Exploiting TLM and object introspection for system-level simulation
Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips
A Time Slice Based Scheduler Model for System Level Design
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD 3 )
FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support
FTApprox: A Fault-Tolerant Approximate Arithmetic Computing Data Format
LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-design
Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator
Who Owns the Platform?
An advanced embedded architecture for connected component analysis in industrial applications
Defect-tolerant logic hardening for crossbar-based nanosystems
An energy-efficient 3D CMP design with fine-grained voltage scaling
Modeling, implementation, and analysis of XRCE-DDS applications in distributed multi-processor real-time embedded systems
An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes
Runtime Code Parallelization for On-Chip Multiprocessors
CBTune: Contextual Bandit Tuning for Logic Synthesis
Overview of the state of the art in embedded machine learning
Rapid runtime estimation methods for pipelined MPSoCs
Exploiting DRAM restore time variations in deep sub-micron scaling
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip
Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels
Support for dynamic issue width in VLIW processors using generic binaries
An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface
Degradation analysis of high performance 14nm FinFET SRAM
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
Error resilience of intra-die and inter-die communication with 3D spidergon STNoC
A power optimization method for CMOS Op-Amps using sub-space based geometric programming
Reversible circuit technology mapping from non-reversible specifications
Analytical router modeling for networks-on-chip performance analysis
Distributed Multimedia System Design: A Holistic Perspective
On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes
Inversed Temperature Dependence aware clock skew scheduling for sequential circuits
Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes
Improving the efficiency of thermal covert channels in multi-/many-core systems
Serialized Asynchronous Links for NoC
Hardware Software Partitioning with Integrated Hardware Design Space Exploration
On Nanoscale Integration and Gigascale Complexity in the Post.Com World