yusuke1997/dblp-id-title huggingface dataset:
A Collaborative System for Designing Tele-Therapies
A High-Level Model for a Healthy Smart City
User Behavior Shift Detection in Intelligent Environments
Introducing Ambient Assisted Living Technology at the Home of the Elderly: Challenges and Lessons Learned
A Multi-sensor Mobile System Based on Agents for People Monitoring
Focus Group Evaluation of Scenarios for Fall Risk Assessment and Fall Prevention in Two Countries
A Hybrid HMM/ANN Model for Activity Recognition in the Home Using Binary Sensors
Automatic Emotion Recognition from Cochlear Implant-Like Spectrally Reduced Speech
Residential Care Home Awareness
Enhancing Social Interaction between Older Adults and Their Families
Identification of Ideal Contexts to Issue Reminders for Persons with Dementia
A Real-Time Insulin Injection System
Evaluation of Emerging Audio Description Systems for Broadcast TV
Do Technology-Related Stimuli Affect Age Estimation?
YOAPY: A Data Aggregation and Pre-processing Module for Enabling Continuous Healthcare Monitoring in the Internet of Things
Cloud-Based Remote Processing and Data-Mining Platform for Automatic Risk Assessment in Hypertensive Patients
Promoting Healthy Nutrition Behavior Using Mobile Devices and Ubiquitous Computing
Gait Quality Monitoring Using an Arbitrarily Oriented Smartphone
Personal Ambient Intelligent Reminder for People with Cognitive Disabilities
A Database-Centric Architecture for Home-Based Health Monitoring
Ambient Assisted Living. ICT-Based Solutions in Real Life Situations - 7th International Work-Conference, IWAAL 2015, Puerto Varas, Chile, December 1-4, 2015, Proceedings
To What Extent It Is Possible to Predict Falls due to Standing Hypotension by Using HRV and Wearable Devices? Study Design and Preliminary Results from a Proof-of-Concept Study
The HELICOPTER Project: A Heterogeneous Sensor Network Suitable for Behavioral Monitoring
X-Factor HMMs for Detecting Falls in the Absence of Fall-Specific Training Data
AngryEmail? Emotion-Based E-mail Tool Adaptation
An Android Telecare Prototype for a Low-SES Seniors Living Facility: A Case Study
Handling Displacement Effects in On-Body Sensor-Based Activity Recognition
Revisiting the User Experience of a Virtual Rehabilitation Tool for the Physical Activation and Cognitive Stimulation of Elders
Image Analysis for Crack Detection in Bone Cement
Acceptance of Selected Applications of Ambient Assisted Living in the Project A 2 LICE
A Low-Cost ZigBee-Based Gateway System for Indoor Localization and Identification of a Person
Improving Health Services Using Cloud Computing, Big Data and Wireless Sensors
MonAMI: Economic Impact of Mainstream AAL Open Platform in Home Care
The Impact of Introducing Therapeutic Robots in Hospital's Organization
An Approach for Agitation Detection and Intervention in Sufferers of Autism Spectrum Disorder
Evaluation of an Inclusive Smart Home Technology System
New Approaches for Alzheimer's Disease Diagnosis Based on Automatic Spontaneous Speech Analysis and Emotional Temperature
A Dual Approach for Quantitative Gait Analysis Based on Vision and Wearable Pressure Systems
Human Activity Recognition on Smartphones Using a Multiclass Hardware-Friendly Support Vector Machine
Ambient Assisted Living and Home Care - 4th International Workshop, IWAAL 2012, Vitoria-Gasteiz, Spain, December 3-5, 2012. Proceedings
eFisioTrack: A Telerehabilitation Platform for Monitoring Prescribed Therapeutic Exercises in Orthopaedic Injuries
Common-Sense Knowledge for a Computer Vision System for Human Action Recognition
Laterality of arm movement variability on copying and tracing
Proceedings of the Behavior Transformation by IoT International Workshop, BTIW 2024, Minato-ku, Tokyo, Japan, June 3-7, 2024
PInT: Person's Interruption Timing Sensor
PTAC: Personal Utterance Counter For Well-being
How is our mobility affected as we age? Findings from a 934 users field study of older adults conducted in an urban Asian city
Basic Study on Generation of Dopamine-Secretion-Promoting Intrinsic Motivational Messages Using ChatGPT
Exploring the Impact of Wearable Continuous Glucose Monitoring on Glucose Regulation and Eating Behavior in Healthy Individuals: A Pilot Study
Hybrid Stochastic Computing Circuits in Continuous Statistics Domain
Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder
Accelerating pattern matching for DPI
Exploring RISC-V Instruction-Level Optimization Through Macro-Operation Fusion for TensorFlow-based Models
Distributed On-Chip Power Supply for Security Enhancement in Multicore NoC
Tutorial 1B: Transistors: Past, present and future
Integrated routing and channel arbitration in overlaid mesh WiNoC
Current-Reuse LC Divide-by-8 Injection-Locked Frequency Divider
A unified HW/SW system-level simulation framework for next generation wireless system
VLSI passive switched capacitor signal processing circuits: Circuit architecture, closed form modeling and applications
A versatile content addressable memory architecture
A CMOS Low-Noise, Low-Dropout Regulator for Transceiver SOC Supply Management
Industrial experience with cycle error computation of cycle-accurate transaction level models
A Network on Chip Adapter for Real-Time and Safety-Critical Applications
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer
A Folding Strategy for SAT solvers based on Shannon's expansion theorem
MPT: Multiple Parallel Tempering for High-Throughput MCMC Samplers
Neuro-Inspired Multimodal Transistors for Advanced Analog Computation
Continuous-time single-symbol IR-UWB symbol detection
A unique non-intrusive approach to non-ATE Based cul-de-sac SoC debug
Network processors for access network (NP4AN): trends and challenges
A testability-aware low power architecture
A 72dBO 11.43mA novel CMOS regulated cascode TIA for 3.125Gb/s optical communications
Analog Content Addressable Memory using Ferroelectric: A Case Study of Search-in-Memory
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing
Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings
A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning
Development of advanced diagnostic functions in very high volume automotive sensor applications
Novel VLSI architecture of motion estimation for H.264 standard
EdgeVision SoC: PPA-Impact of RTL-level Modifications
Low power design for on-chip networking processing system
A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes
A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current Compensation
Consideration of Transition-Time Variability in Statistical Timing Analysis
High performance multi-engine regular expression processing
Achieving higher dynamic range in flash A/D converters
Monitor strategies for variability reduction considering correlation between power and timing variability
DG-SRAM: a low leakage memory circuit
Reconfigurable video motion estimation processor
Hybrid test data compression technique for SOC scan testing
Design of high-speed low-power polar BP decoder using emerging technologies
Efficient Interpolation Techniques and Realization Structures for Continuously Variable Bandwidth Filters
F2A: Low power design
Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study
Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM
T3B: Recent advancements in fiber optic transmission enabled by highly integrated mixed signal SoC and advanced digital signal processing
Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems
A novel design flow for a 3D heterogeneous system prototyping platform
Towards Hardware Trojan Resilient Design of Convolutional Neural Networks
FPGA-based CNN inference accelerator synthesized from multi-threaded C software
Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA
A memory allocation and assignment method using multiway partitioning
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs
Configurable workload generators for multicore architectures
Gray-level image recognition on a dynamically reconfigurable vision architecture
PRIDES: A Power Rising Descending Signature for Improving IoT Security
System management recovery protocol for MPSoCs
A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS
OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array
System-level simulator for process variation influenced synchronous and asynchronous NoCs
UWB receiver for breast cancer detection: Comparison between two different approaches
A holistic view on low power design
EDT dynamic bandwidth management (DBM) in SoC testing
Tutorial: "Design of high-speed wireline transceivers"
Energy-Efficient and Communication-Aware Architectures for Accelerating Deep Learning Workloads
Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAs
3-22GHz CMOS distributed single-balanced mixer
Design and implementation of novel source synchronous interconnection in modern GPU chips
Haar-based interconnect coding for energy effective medium/long range data transport
A BJT-Based Temperature Sensor in 40-nm CMOS With ±0.8°C(3σ) Untrimmed Inaccuracy
Tutorial: Methodology for designing reliable clock networks
A holistic design approach for systems on chip
Integrated Surround & CMS Automotive SoC
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC
Thin-Film Memristors and Memcapacitors for 3D Integration of Neuromorphic Systems
Toward more efficient scan data bandwidth utilization on modern SOCs
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist
FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration
The memory challenge in computing systems: A survey
Low-power real-time intelligent SoCs for smart machines
54-65 GHz six port demodulator
Low power 8T SRAM using 32nm independent gate FinFET technology
Power Efficient Attention Acceleration on CGLA
An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling
Low-power, Energy-efficient, Cardiologist-level Atrial Fibrillation Detection for Wearable Devices
Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability
DDR3 based lookup circuit for high-performance network processing
Introduction to hardware-oriented security for MPSoCs
Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture
Baseband design for passive semi-UWB wireless sensor and identification systems
Jitter transfer function model and VLSI jitter filter circuits
A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOS
Efficient Metal Inter-Layer Via Utilization Strategies for Three-dimensional Integrated Circuits
Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs
HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature
A Design Approach to Reduce Test Time on SOC Memories
Non-overlapping transition encoding for global on-chip interconnect
An FSK Transceiver for USB Power Delivery in 0.14-μm CMOS Technology
A prototype of a wireless-based test system
Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development
A novel thermal-aware structure of TSV cluster
High-Entropy LFSR-Based Random Number Generator (RNG) for Hardware Security
Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes
An A-SAR ADC circuit with adaptive auxiliary comparison scheme
An Energy-Efficient Low Power LSTM Processor for Human Activity Monitoring
Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching
Design and implementation of phase correlation based motion estimator
An improved implementation method of AHB BusMatrix
Efficient implementation of the AES algorithm for security applications
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology
Resistive Loss and Trans-Impedance Characterization of Nonlinear Transmission Lines on CMOS SOI Substrate
A wakeup rush current and charge-up time analysis method for programmable power-gating designs
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA
An efficient lossless embedded compression engine using compacted-FELICS algorithm
An energy efficient wireless Network-on-Chip using power-gated transceivers
Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits
A low-computation-complexity, energy-efficient, and high-performance linear program solver using memristor crossbars
Overcoming the power wall by exploiting inexactness and emerging COTS architectural features: Trading precision for improving application quality
Message from conference general chair
A Practical Man-in-the-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane
A low power wide tuning range VCO with coupled LC tanks
A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation
Self-Correcting Op-Amp Input Offset Using Analog Floating Gates
BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive Distillation
Tuning SoCs using the global dynamic critical path
Equal length routing
Design of a SIMD multimedia SoC platform
Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip
IoT and Data-Driven Acoustic Leak Detection Using Microcontroller and Fast Fourier Transform
An automated design method for chip power distribution
Power Swapper: Approximate Functional Block Assisted Cryptosystem Security
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range
W3B: Special session: Secure multi-processors systems-on-chip for critical applications
Tutorial: "Post silicon debug of SOC designs"
Power analysis for Asynchronous CLICHÉ Network-on-Chip
Power aware transformation of bandlimited signals
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration
An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management
Total Variation Reduction for Lossless Compression of HPC Applications
Variation aware low power buffered interconnect design
An optically differential reconfigurable gate array using a 0.18 μm CMOS process
A systematic methodology to design high power terahertz and submillimeter-wave amplifiers
FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation
Adaptive response surface modeling-based method for analog circuit sizing
SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor
Efficient Deployment of Large Language Model across Cloud-Device Systems
An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks
Leakage Reduction for Domino Circuits in Sub-65nm Technologies
On Enhancing the Security Against Memory Disclosure Attacks
Scalable and low power LDPC decoder design using high level algorithmic synthesis
A graph based synthesis procedure for linear analog function
Analysis of a serial link for power supply induced jitter
Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator
Pseudo-random clocking to enhance signal integrity
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications
Magneto-electric magnetic tunnel junction based analog circuit options
Tutorial 1B: AI Chip Technologies and DFT Methodologies
A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-hold
RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT
DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid Architecture
High-voltage low-power startup backup battery switch using low voltage devices in 28nm CMOS
"SOC challenges in the terabit networks era"
Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture
A CMOS self-powered monolithic light direction sensor with SAR ADC
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems
A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems
FPGA-based verification methodology of SoC-type CMOS image signal processor
Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC using Machine Learning
A 590MDE/s semi-global matching processor with lossless data compression
Improved write margin 6T-SRAM for low supply voltage applications
Instruction decoders based on pattern factorization
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs
The pending arrival of Phase Change Memory: The implications on the memory-storage hierarchy and on future systems development
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation
Digital spiking neuron cells for real-time reconfigurable learning networks
Multiple terminal reduction method
Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks
QuteIP: An IP qualification framework for System on Chip
Analog-Inspired Hardware Security: A Low-Energy Solution for IoT Trusted Communications
ReRAM Non-Volatile AES Encryption Engine for IoT Application
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator
A high-speed power and resolution adaptive flash analog-to-digital converter
A High Accuracy and Hardware Efficient Approximate Computing based Leaky integrate-and-fire Neuron Model
Synthesizable delay line architectures for digitally controlled voltage regulators
A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology
High-frequency and power-efficiency ultrasound beam-forming processor for handheld applications
An application-specific processor hard macro for real-time control
Generating interacting synchronous and asynchronous designs from simulink descriptions
Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm
Radar Transceivers for Inverse Synthetic Aperture Radar (ISAR) Imaging of Human Activity in 65nm CMOS
Signal integrity implications of inductor-to-circuit proximity
37th IEEE International System-on-Chip Conference, SOCC 2024, Dresden, Germany, September 16-19, 2024
In-situ self-aware adaptive power control system with multi-mode power gating network
Design and analysis of an advanced static blocked multithreading architecture
Coding algorithms for network on a chip
An Optimised on-Device Deep Learning Training: An fNIRS study
A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture
Interconnect compression and its benefits for multi-core systems
Application development flow for on-chip distributed architectures
Tuning instruction customisation for reconfigurable system-on-chip
Identifying Specious LUTs for Satisfiability Don't Care Trojan Detection
W1B: Application specific designs
Low-latency power-efficient adaptive router design for network-on-chip
A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000
Novel 7T sram cell for low power cache design
Reliability aware logic synthesis through rewriting
Workload and task characterization based on operation modes timing analysis
35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022
Power optimal Network-on-Chip interconnect design
REFLEX: Reconfigurable logic for entropy extraction
STT-MRAM memory cells with enhanced on/off ratio
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
Efficient, snoopless, System-on-Chip coherence
Retiming and clock scheduling to minimize simultaneous switching
FDSOI design experience and recommendations
Policy-Based Security Modelling and Enforcement Approach for Emerging Embedded Architectures
Synthesis and verification of cyclic combinational circuits
34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021
A Convolutional Neural Network on Chip Design Methodology for CNN Hardware Implementation
Bi-Partition Four-Branch Tree: Topologies for Sub-10ps Skew with Co-Optimized Latency Buffer
A High-Speed Architecture for the Reduction in VDF Based on a Class Group
Design of Adaptive Active Filter Using Operational Transconductance Amplifiers in 65nm CMOS
A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver
Hardened-TC: A Low-cost Reliability Solution for CNNs Run by Modern GPUs
"Free" Razor: A novel adaptive voltage scaling low power technique for data path SoC designs
Modelling control systems in SystemC AMS - Benefits and limitations
Adaptive driver with automatic sense and calibration in CMOS 40LP
Dynamic calibration of feedback DAC non-linearity for a 4 th order CT sigma delta for digital hearing aids
Architecture and circuit design of parallel processing elements for de novo sequence assembly
Supply voltage selection in Voltage Island based SoC design
A circuit-switched network architecture for network-on-chip
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration
High speed recursion-free CORDIC architecture
Wednesday keynote I: FDSOI and FINFET for SoC developments
Variation-and-aging aware low power embedded SRAM for multimedia applications
A high-resolution and fast-conversion readout circuit for differential capacitive sensors
JavaFlow - A Java dataflow machine
Neuro inspired reconfigurable architecture for hardware/software co-design
A novel phase detector for PAM-4 clock recovery in high speed serial links
Practical power consumption analysis with current smartphones
An Automated Hardware Design Framework for Various DNNs Based on ChatGPT
Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC
Improving the Performance of a NoC-based CNN Accelerator with Gather Support
On microarchitectural modeling for CNFET-based circuits
A Discontinuous Charging Technique with Programmable Duty-Cycle for Switched-Capacitor Based Energy Harvesting Circuits in IoT Applications
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines
Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA
A novel five-transistor (5T) sram cell for high performance cache
Energy and delay-aware mapping for real-time digital processing system on network on chip platforms
Design methodolgy for HD Photo compression algorithm targeting a FPGA
Support for multiprocessor synchronization and resource sharing in system-on-programmable chips with softcores
Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power- Performance Adaptation Beyond Voltage Scaling
Communication on a segmented bus
Optimizing Placement Legalization Utilizing Multiple Shapes of Standard Cells
Reconfigurable RRAM for LUT logic mapping: A case study for reliability enhancement
Cloud Motion Vector Estimation Using Scalable Wireless Sensor Networks
A timing methodology considering within-die clock skew variations
A new approach using symbolic analysis to compute path-dependent effective properties preserving hierarchy
Nanoscale on-chip decoupling capacitors
FPGA-Based Hardware Accelerator for LWE Encryption and Decryption with TFHE Scheme
Hardware Oriented Strip-wise Optimization (HOSO) Framework for Efficient Deep Neural Network
A Framework for Evaluation of Debug Path Performance in SoC
Single-ended D flip-flop with implicit scan mux for high performance mobile AP