yusuke1997/dblp-id-title huggingface dataset:
Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor
Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration
11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA
A distinctive O(mn) time algorithm for optimal buffer insertions
NetViz: A Tool for Netlist Security Visualization
Beta Oscillation Detector Design for Closed-Loop Deep Brain Stimulation of Parkinson's Disease with Memristive Spiking Neural Networks
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
Assertion-based verification for system-level designs
Derating for static timing analysis: Theory and practice
MC-MCF: A Multi-Capacity Model for Ordered Escape Routing
Performance validation through implicit removal of infeasible paths of the behavioral description
Specification and formal verification of power gating in processors
Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method
A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors
Tests on Symmetry and Continuity between BSIM4 and BSIM5
An Embedded IDDQ Testing Architecture and Technique
Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model
A novel virtual prototyping methodology for timing-accurate simulation of AMS circuits
Thermal-aware semi-dynamic power management for multicore systems with energy harvesting
Capacitor free phase locked loop design in 45nm
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs
CARE: Lightweight Attack Resilient Secure Boot Architecture with Onboard Recovery for RISC-V based SOC
On the Relation between SAT and BDDs for Equivalence Checking
Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation
Hierarchical Soft Error Estimation Tool (HSEET)
Method for efficient flash bit cell current compression in deeply erased bits
The Effect of Threshold Voltages on the Soft Error Rate
Using MUXs Network to Hide Bunches of Scan Chains
Deep Neural Network Based Speech Recognition Systems Under Noise Perturbations
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies
Toward Automated Potential Primary Asset Identification in Verilog Designs
Concurrency-oriented SoC re-certification by reusing block-level test vectors
Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures
Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions
5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA
Designing effective scan compression solutions for industrial circuits
Sharp-Edge: A Robust Edge Computing Solution Through Performance Monitoring Using Tiny Machine Learning
Analysis of power supply induced jitter in actively de-skewed multi-core systems
STA compatible backend design flow for TSV-based 3-D ICs
mTest: An Industry-Wide Database of VLSI Layouts for Quality Control
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
Enhancing efficiency and robustness of a photovoltaic power system under partial shading
Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks
Tunnel FET based ultra-low-leakage compact 2T1C SRAM
Exploring the Challenges in Creating a High-Quality Mainstream Design Solution for System-in-Package (SiP) Design
Measuring SET pulsewidths in logic gates using digital infrastructure
Probabilistic Congestion Prediction with Partial Blockages
Transistor-Level Optimization of Supergates
Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability
Multi-Gate MOSFET Design
Process variation aware system-level load assignment for total energy minimization using stochastic ordering
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
A Built-in Test and Characterization Method for Circuit Marginality Related Failures
Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models
Asymmetric issues of FinFET device after hot carrier injection and impact on digital and analog circuits
An analytical approach to system-level variation analysis and optimization for multi-core processor
Effect-cause intra-cell diagnosis at transistor level
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality
Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA
Calculation of stress probability for NBTI-aware timing analysis
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision
A High Frequency PWM Controller in HV Bi-CMOS Process Considering SOI Self-Heating
Uncertainty aware mapping of embedded systems for reliability, performance, and energy
Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance
A Design Model for Random Process Variability
Dilated Involutional Pyramid Network (DInPNet): A Novel Model for Printed Circuit Board (PCB) Components Classification
The IP Quality Revolution
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators
Accelerating jitter tolerance qualification for high speed serial interfaces
Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform
High-Quality Circuit Synthesis for Modern Technologies
Analysis of the Impact of LFSR Architecture on Accuracy of Stochastic Computing Processors
Energy-Minimization Model for Fill Synthesis
An EDA Perspective, "We Need it Yesterday!
Coupling Noise Analysis for VLIS and ULSI Circuits
Active protection against PCB physical tampering
A Three-dimensional (3D) Memristive Spiking Neural Network (M-SNN) System
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
A Thermal-Aware Superscalar Microprocessor (invited)
Innovative Test Solutions for Pin-Limited Microcontrollers
A comprehensive model for gate delay under process variation and different driving and loading conditions
Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect
Entropy-reduced hashing for physical IP management
SPRED: Spatially Distributed Laser Fault Injection Resilient Design
Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators
Verification of IP-Core Based SoC's
Stress-Aware Design Methodology
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process
NoC-based platform for embedded software design: An extension of the Hellfire Framework
Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation
Virtual Channels Planning for Networks-on-Chip
Structural Decomposition with Functional Considerations for Low Power
Meta-Heuristic Optimization for Designing Error Diluted Weight Stationary Approximate Systolic Array Architecture
Worst-case noise prediction with non-zero current transition times for early power distribution system verification
PhotoGAN: Generative Adversarial Neural Network Acceleration with Silicon Photonics
Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS
A Comprehensive Evaluation of Power Delivery Schemes for Modern Microprocessors
Decomposition technologies for advanced nodes
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
Parameterized Macrocells with Accurate Delay Models for Core-Based Designs
On the design of different concurrent EDC schemes for S-Box and GF(p)
Automatic Subnetwork Search Through Dynamic Differentiable Neuron Pruning
A design time simulator for computer architects
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network
An automated design methodology for yield aware analog circuit synthesis in submicron technology
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
Efficient K nearest neighbor algorithm implementations for throughput-oriented architectures
Sustainable dual-level DVFS-enabled NoC with on-chip wireless links
Clock tree optimization through selective airgap insertion
IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement
SUB-45nm Technology and Design Challenges
Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors
Design and analysis of novel SRAM PUFs with embedded latch for robustness
Upper/Lower Boundary Estimation of Package Interconnect Parasitics for Chip-Package Co-Design
Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approach
Successful IP Business Models
HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy-Efficient Classification
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels
Entropy-Shield: Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks
What You Don't Know CAN Hurt You: Designing for Survival in a Sub-wavelength Environment
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method
Impact of Double-Row Height Standard Cells on Placement and Routing
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
LEC Vulnerability on Constant Propagation
Functions for Quality Transition Fault Tests
Finite-Point Gate Model for Fast Timing and Power Analysis
Security and Reliability Challenges in Machine Learning for EDA: Latest Advances
Fast Crosstalk Repair by Quick Timing Change Estimation
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited)
An Efficient Method for Fast Delay and SI Calculation Using Current Source Models
Thermal hotspot reduction in mm-Wave wireless NoC architectures
A Transition Based BIST Approach for Passive Analog Circuits
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
Hierarchical dynamic goal management for IoT systems
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances
A 4-14 Gbps inductor-less adaptive linear equalizer using hybrid filter in 65 nm CMOS technology
Design for Testability of FPGA Blocks
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits
Analysis and reliability test to improve the data retention performance of EPROM circuits
Quantum Circuit Simulation with Fast Tensor Decision Diagram
Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design
Reinforcement Learning-Based Guidance of Autonomous Vehicles
Routability-aware Placement Guidance Generation for Mixed-size Designs
ISSAC: An Self-organizing and Self-healing MAC Design for Intermittent Communication Systems
VAR-TX: A variability-aware SRAM model for predicting the optimum architecture to achieve minimum access-time for yield enhancement in nano-scaled CMOS
EGAN: A Framework for Exploring the Accuracy vs. Energy Efficiency Trade-off in Hardware Implementation of Error Resilient Applications
Impact of Variability on Clock Skew in H-tree Clock Networks
SoC Engineering Trends as Impacted by New Applications and System Level Requirements
Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array
Hot peripheral thermal management to mitigate cache temperature variation
Program acceleration using nearest distance associative search
Via Distribution Model for Yield Estimation
A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company
An Improved Method for Identifying Linear Dependencies in Path Delay Faults
A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays
Low power clock gates optimization for clock tree distribution
Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware
Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield
Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices
The compatibility analysis of thread migration and DVFS in multi-core processor
Measuring the effectiveness of ISO26262 compliant self test library
Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL
Circuit Level Reliability Analysis of Cu Interconnects
Reducing impact of degradation on analog circuits by chopper stabilization and autozeroing
Design For Degradation : CAD Tools for Managing Transistor Degradation Mechanisms
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET
Cell-Based Semicustom Design of Zigzag Power Gating Circuits
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning
Exploration of Vulnerabilities of Fault-Tolerant Quantum Computing
Architecting STT Last-Level-Cache for performance and energy improvement
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping
ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing
Multilayered Triboelectric Energy Harvester as a Smart Floor Mat
Accurate buffer modeling with slew propagation in subthreshold circuits
Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network
Architectural reliability estimation using design diversity
Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs
Design of a fault-tolerant coarse-grained
High sigma statistical hold time analysis in FinFET sequential circuits
Neuromorphic architectures with electronic synapses
Secure High-Level Synthesis: Challenges and Solutions
A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans
Early Assessment of Leakage Power for System Level Design
Understanding, modeling, and detecting pooling hotspots in copper CMP
ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories
An efficient reliability evaluation approach for system-level design of embedded systems
Guardians of the Quantum GAN
Image-Based Zero-Day Malware Detection in IoMT Devices: A Hybrid AI-Enabled Method
Therunet-SP: 2.5D IC Thermal Simulation Using U-Net Convolution and Scaling Procedure
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm
Energy-Efficient Neuromorphic Closed-Loop Modulation System for Parkinson's Disease
Thermal flow sensors based on printed circuit board technology
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures
CAD Issues for CMOS VLSI Design in SOI
Embedded-Quality for Test
UM-BUS: An online fault-tolerant bus for embedded systems
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem
Variation-aware stochastic extraction with large parameter dimensionality: Review and comparison of state of the art intrusive and non-intrusive techniques
Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms
Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs
NAND Flash-Based Digital Fingerprinting for Robust and Secure Hardware Authentication
DFM Metrics for Standard Cells
Who is really responsible for quality throughout the design process?
Reliability-Centric Hardware/Software Co-Design
Statistical analysis of process variation induced SRAM electromigration degradation
Statistical quality modeling of approximate hardware
Strong PUF Security Metrics: Response Sensitivity to Small Challenge Perturbations
Charge recovery logic as a side channel attack countermeasure
High Performance Double-Gate Device Technology Challenges and Opportunities (invited)
Large-scale multi-corner leakage optimization under the sign-off timing environment
Validating physical access layer of WiMAX using SystemVerilog
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis
A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection
Fused Functional Units for Area-Efficient CGRAs
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification
DC-Model: A New Method for Assisting the Analog Circuit Optimization
Early clock prototyping for design analysis and quality entitlement
EDA to the Rescue of the Silicon Roadmap
In-situ Trojan authentication for invalidating hardware-Trojan functions
Process-Variation Statistical Modeling for VLSI Timing Analysis
Parameter tuning in SVM-based power macro-modeling
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries
FlexGuard: Dynamic Scoring & Stochastic Routing for Balanced Security-Performance in 3D NoCs
25th International Symposium on Quality Electronic Design, ISQED 2024, San Francisco, CA, USA, April 3-5, 2024
Efficient diagnosis algorithms for drowsy SRAMs
RL-Driven Fine-Grained Power Gating for Modern Processors Using Multi-Layer Perceptron Models
Electrical modeling and analysis of 3D synaptic array using vertical RRAM structure
Improving the process variation tolerability of flip-flops for UDSM circuit design
Evaluating LLM-Based Communicative Agents for Verilog Design
Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems
Layout-aware analog synthesis environment with yield consideration
Implementing self-testing and self-repairable analog circuits on field programmable analog array platforms
Hierarchical power network synthesis for multiple power domain designs
Application of Machine Learning in Hardware Trojan Detection
An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors
Constant Impedance Scaling Paradigm for Scaling LC transmission lines
Non-Homogeneous Composite Karatsuba Multipliers Factored Hardware-Efficient ECDSA Generation and Verification Accelerator Units
A TMR Scheme for SEU Mitigation in Scan Flip-Flops
Broadcast scan compression based on deterministic pattern generation algorithm
Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor
BMX-FPCA: 3D Beyond-Moore Flexible Field Programmable Crossbar Array Architecture
Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications
Evaluating tradeoffs in granularity and overheads in supporting nonvolatile execution semantics
Time-division multiple access based intra-body communication for wearable health tracker
An Objective Measure of Digital System Design Quality
Modeling of Substrate Noise Injected by Digital Libraries
23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022
Fine grained wearout sensing using metastability resolution time
Low power sensor for temperature compensation in molecular biosensing
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs
On SAT-Based Attacks On Encrypted Sequential Logic Circuits
A Pattern Matching System for Linking TCAD and EDA
Efficient region-aware P/G TSV planning for 3D ICs
Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation
Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC
Temperature aware refresh for DRAM performance improvement in 3D ICs
A "Design for Verification" Methodology
An Automated and Fast OPC Algorithm for OPC-Aware Layout Design
22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021
A new era of computing: Are you "ready now" to build a smarter and secured enterprise?
Switching constraint-driven thermal and reliability analysis of Nanometer designs
Efficient statistical analysis of read timing failures in SRAM circuits
New AC resistance calculation of printed spiral coils for wireless power transfer
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits
This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms
Model based double patterning lithography (DPL) and simulated annealing (SA)
Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor
The impact of BEOL lithography effects on the SRAM cell performance and yield
A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design
Process variation tolerant on-chip communication using receiver and driver reconfiguration
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees
Zero clock skew synchronization with rotary clocking technology
Low-energy digital filter design based on controlled timing error acceptance
Standard Cell Printability Grading and Hot Spot Detection
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
Formal Verification of a Custom Compiler for a Fully Homomorphic Encryption Accelerator
Scalability of PCMO-based resistive switch device in DSM technologies
Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper)
Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices
Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion
RFID indoor localization based on Doppler effect
A Statistical Model for Electromigration Failures
An Error-Resilient Compute-in-Memory 3D FPCA Architecture for High-Performance Floating-Point Operations
Design on ESD Protection Circuit with Very Low and Constant Input Capacitance
HiCTL: High Fan-in Differential Capacitive-Threshold-Logic Gate Implementation With an Offset-Compensated Comparator
An SSO Based Methodology for EM Emission Estimation from SoCs
Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits
Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node
40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU
New subthreshold concepts in 65nm CMOS technology