yusuke1997/dblp-id-title huggingface dataset:
Probabilistic CMOS Technology: A Survey and Future Directions
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources
Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability
A framework for Compiler Level statistical analysis over customized VLIW architecture
Exploiting guard band limits for energy gains in MPSoCs
VLSI Verification and Correction
Gate Sizing Under Uncertainty
Use of Gray Decoding for Implementation of Symmetric Functions
Template based synthesis for high performance computing
Assessment of Low-Budget Targeted Cyberattacks Against Power Systems
Post-placement technology mapping
3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System
Reliability enhancement of power gating transistor under time dependent dielectric breakdown
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication
FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs
Dynamic Scheduling for Event-Driven Embedded Industrial Applications
Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform
Efficient Depth Optimization in Quantum Addition and Modular Arithmetic with Ling Structure
ArchFP: Rapid prototyping of pre-RTL floorplans
Flexible Security and Privacy, System Architecture for IoT, in Healthcare
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors
Design and analysis of on-chip charge pumps for micro-power energy harvesting applications
Reliability study on system memories of an iterative MIMO-BICM system
A VLSI System Design for the Control of High Performance Combustion Engines
An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures
Improvement of dual rail logic as a countermeasure against DPA
On the Evaluation of SEEs on Open-Source Embedded Static RAMs
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors
Reduction of process variation effect on FPGAs using multiple configurations
Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom
Dynamic migratory selection strategy for adaptive routing in mesh NoCs
Inference of channel types in micro-architectural models of on-chip communication networks
A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the Edge
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS
22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014
Automated Conversion of SystemC Fixed-Point Data Types
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers
1-V ADPCM Processor for Low-Power Wireless Applications
A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platforms
Exploring the use of the finite element method for electromigration analysis in future physical design
Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories
A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration
Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs
Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack
An All-Digital ADC for Instrumentation within SOCs
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks
Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable Systems
A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections
Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion
Scalable Open-Source System-on-Chip Design: (Invited Talk - Extended Abstract)
Theoretical and Practical Issues in CMOS Wave Pipelining
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC
Power Macro-Modeling Using an Iterative LS-SVM Method
32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024, Tanger, Morocco, October 6-9, 2024
Introduction to panel discussion Probabilistic & statistical design - the wave of the future
Integrated Dynamic Memory Manager for a RISC-V Processor
Multi-Level FeFET-Based CAM Address Decoder
TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on Chip
Learning Based Timing Closure on Relative Timed Design
Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT Security
Load-aware stochastic feedback control for DVFS with tight performance guarantee
Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis
Redundant Via insertion in SADP process with cut merging and optimization
MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder
An adaptive bilateral motion estimation algorithm and its hardware architecture
On the in-field testing of spare modules in automotive microprocessors
Evaluating the ROCKY Countermeasure for Side-Channel Leakage
A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers
Power Analysis Attack on Locking SIB based IJTAG Achitecture
30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022
Adaptive checkpoint intervals in an optimistically synchronised parallel digital system simulator
Power-aware FPGA routing fabrics and design tools
Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs
Extending OpenVX for model-based design of embedded vision applications
TRAPDOOR: Repurposing neural network backdoors to detect dataset bias in machine learning-based genomic analysis
Unifying stream based and reconfigurable computing to design application accelerators
29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021
SNM-aware power reduction and reliability improvement in 45nm SRAMs
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing
A high performance and low energy hardware for intra prediction with Template Matching
BlockShield: A TPM-Integrated Blockchain-Based Framework for Shielding Against Deepfakes
Towards a Formal Model of VLSI Systems Compativle with VHDL
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence
A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques
Offset-Compensation Systems for Multi-Gbit/s Optical Receivers
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics
Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots
Properties of A1/BaTa2O6/GaN MIS Structure
Pass-Transistor Self-Clocked Asynchronous Sequential Circuits
A low-power ultra-fast capacitor-less LDO with advanced dynamic push-pull techniques
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing
Static energy reduction by performance linked dynamic cache resizing
Security evaluation of dual rail logic against DPA attacks
Traffic-aware buffer reconfiguration in on-chip networks
Modular performance analysis of Multicore SoC-based small cell LTE base station
Adaptive Sampling and Modeling of Analog Circuit Performance Parameters
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs
Design of asynchronous RISC CPU register-file Write-Back queue
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping
Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks
Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network
Early planning for RT-level delay insertion during clock skew-aware register binding
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding
The Design and Analysis of an Elliptic Curve Cryptosystem
Low-power high-speed current mode logic using Tunnel-FETs
Efficient Design-Time Flexible Hardware Architecture for Accelerating Homomorphic Encryption
Non-regression approach for the behavioral model generator in mixed-signal system verification
Low-Power High-Speed ADCs for ADC-Based Wireline Receivers in 22 nm FDSOI
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design
Reconfigurable photonic switching: Towards all-optical FPGAs
XbarGen: A memristor based boolean logic synthesis tool
High-efficiency voltage regulation stage in energy harvesting systems
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs
Validation of Asynchronous Circuit Specifications Using IF/CADP
Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator
Robust, self-timed power-on reset circuit for low-voltage applications
Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure
Reducing Depth of Quantum Adder using Ling Structure
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications
Radiation Tolerant 14T SRAM Cell for Avionics Applications
Understanding Transistor Aging Impact on the Behavior of RRAM Cells
Fully electronically programmable complex filter for multistandard applications
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
Low-budget Energy Sector Cyberattacks via Open Source Exploitation
A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth
Area Minimisation of IC Power/Ground Nets by Topology Optimisation
A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC
An Improved Circuit Design for Parallel Sequence Generation
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits
Low Power Java Processor for Embedded Applications
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis
Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability
FPGA power reduction by guarded evaluation considering physical information
Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods
Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design
FPGA-Based Variable Length Decoders
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions
An overview on memristor crossabr based neuromorphic circuit and architecture
Analyzing the Reliability of TCUs Through Micro-architecture and Structural Evaluations for Two Real Number Formats
A low-power analog front-end neural acquisition design for seizure detection
On the estimation of assertion interestingness
Study of on-chip vias of resonant rotary traveling wave oscillators
Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise Amplifier for Ultrasound Imaging
Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits
A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD
30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array Systems
Reducing the Hitting and the Cover Times of Random Walks on Finite Graphs by Local Topological Information
Performance of object caching for object-oriented systems
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures
Efficient DSP algorithm development for FPGA and ASIC technologies
Frequency domain characterization of batteries for the design of energy storage subsystems
Electronic Detection of DNA Adsorption and Hybridization
Configurable Low-Latency Interconnect for Multi-core Clusters
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4
In-Memory Mirroring: Cloning Without Reading
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems
A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties
Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
A generic clock controller for low power systems: Experimentation on an AXI bus
Ultra high speed CMOS design
Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs
Memory-Based Computing for Energy-Efficient AI: Grand Challenges
A pulsed decimal technique for single-channel, dynamic signaling for IoT applications
A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(p m )
Synthesis on switching lattices of Dimension-reducible Boolean functions
First order quasi-static SOI MOSFET channel capacitance model
A Fast SAT Solver Strategy Based on Negated Clauses
Compressed look-up-table based real-time rectification hardware
Energy aware multimodal embedded video surveillance
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
Faster-than-at-speed execution of functional programs: An experimental analysis
Three-dimensional stacking FPGA architecture using face-to-face integration
Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC
Impact of Process Variability and Single Event Transient on FinFET Technology
SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification
Architecture of an HDTV Intraframe Predictor for a H.264 Decoder
A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths
Diagnostic Coverage Estimation for Automotive SoCs Based on Colored Stochastic Petri Nets
Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip
Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference
Novel ultra low-voltage and high speed domino CMOS logic
Organic Computing at the System on Chip Level
A basic-block power annotation approach for fast and accurate embedded software power estimation
Towards CIM-friendly and Energy-Efficient DNN Accelerator via Bit-level Sparsity
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits
A low-loss rectifier unit for inductive-powering of biomedical implants
FOF: Functionally Observable Fault and its ATPG techniques
High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic
A high efficiency synchronous buck converter with adaptive dead time control for dynamic voltage scaling applications
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip
Use of gray decoding for implementation of symmetric functions
A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images
A Branch File for a Configurable DSP Core
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
PEDE (Plasma Edge Damage Effect) Curing by Various Heat Treatment
A low power, programmable bias inverter quantizer (BIQ) flash ADC
Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature
Measures to Reduce the Electromagnetic Emission of a SoC
Spin-electronics based logic fabrics
Impact of hardware emulation on the verification quality improvement
Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators
Trends and techniques for energy efficient architectures
On Distributed Logic Simulation Using Time Warp
A binary adaptable window SoC architecture for a stereo vision based depth field processor
Modelling Heterogeneous Interactions in SoC Verification
A novel wide frequency range 65nm CMOS VCO
Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-B
Fine grain word length optimization for dynamic precision scaling in DSP systems
Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers
A Study on Fault-Tolerant Circuits Using Redundancy
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction
A new reliability evaluation methodology and its application to network-on-chip routers
SWORD: A SAT like prover using word level information
Optimal layout recycling based on graph theoretic linear programming approach
Bounds on Net Delays for Physical Design of Fast Circuits
The single chip system era
Design challenges for the 45 nm node and below
Hardware/software partitioning of embedded System-on-Chip applications
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM
A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures
Putting Inner Loops Automatically in Silicon
Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware
Enhancing post-silicon processor debug with Incremental Cache state Dumping
Fortified-Edge 5.0: Federated Learning for Secure and Reliable PUF in Authentication Systems
Intelligent Device Parameter Extraction for Nanoscale MOSFETs Era
New 12-bit source-follower track-and-hold circuit suitable for high-speed applications
Confidential Inference in Decision Trees
Modular Functional Testing: Targeting the Small Embedded Memories in GPUs
Dynamic gates with hysteresis and configurable noise tolerance
Accurate real-time UAV flight-mode classification
Defect-aware synthesis for reconfigurable single-electron transistor arrays
A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder
Logic Synthesis of EXOR Projected Sum of Products
High-Resolution WTA-MAX Circuit for Large Networks
An MCTS-based Framework for Synthesis of Approximate Circuits
Hough Transform recursive evaluation using Distributed Arithmetic
Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem
An equilibrium partitioning method for multicast traffic in 3D NoC architecture
A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole
Simultaneous Switching Noise Estimation Including the Effects of the Driving Transistor Gate-Source Capacitance
Secure and Compact Full NTRU Hardware Implementation
Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration
ReCPU: A parallel and pipelined architecture for regular expression matching
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow
A low power keyword spotting algorithm for memory constrained embedded systems
Minimizing redundancy-based motion estimation design for high-definition
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors
Scalable algorithm for structural fault collapsing in digital circuits
Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory
Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices
Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs
Fast dynamic fault injection for virtual microcontroller platforms
Optimal scheduling to minimize non-volatile memory access time with hardware cache
An Open-source Framework for Autonomous SoC Design with Analog Block Generation
A quantum algorithm processor architecture based on register reordering
Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines
Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip
A new approach for constructing logic functions after ECO
Identification and Resynthesis of Pipelines in Sequential Networks
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications
Statistical and Numerical Approach for a Computer efficient circuit yield analysis
Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors
2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016
Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs
Single charge-pump generating high positive and negative voltages driving common load
Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems
A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI
Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping
Efficient timing closure with a transistor level design flow
Modeling, analysis and exploration of layers: A 3D computing architecture
A hybrid algorithm for the optimization of area and delay in linear DSP transforms
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation
A scalable model based RTL framework zamiaCAD for static analysis
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering
Trace signal selection methods for post silicon debugging
The WASP 2 Wafer Scale Integration Demonstrator
Logic Locking of Finite-State Machines Using Transition Obfuscation
High speed SOC design for blowfish cryptographic algorithm
Power-management high-level synthesis
A low-cost and high efficiency entropy encoder architecture for H.264/AVC
An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access
VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes
Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection
Design of a dedicated neural network on silicon: application to optical character recognition
Superconductive interconnections in multi-chip modules
A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms
Low power SoCs with resonant dynamic logic using inductors for energy recovery