yusuke1997/dblp-id-title huggingface dataset:
A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA
A Broadcast-Enabled Sensing System for Embedded Multi-core Processors
Random Microfluidic Chip Design with Diagonal Channels Using K-Means Clustering for Fluid Dilutions
A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors
A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme
Most Significant Digit First Multiply-and-Accumulate Unit for Neural Networks
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning
A MEMS Ultra-Stable Short Duration Current Pulse Generator
A Regular Layout Approach for ASICs
Minimum Area Cost for a 30 to 70 Gbits/s AES Processor
Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes
STA for Mixed Cyclic, Acyclic Circuits
Spintronic Device Based Non-volatile Low Standby Power SRAM
Approximate Redundant Booth Multiplier Based on Error Compensation Mechanism
Automating Versatile Time-Series Analysis with Tiny Transformers on Embedded FPGAs
Breaking Down Quantum Compilation: Profiling and Identifying Costly Passes
Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
PACE: MLP-Based Fast and Accurate Per-Cycle Chip Power Modelling
Energy-Efficient Design of Approximate VVC Interpolation Filters Units
ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator
Towards Artificial-Intelligence-Based Cybersecurity for Robustifying Automated Driving Systems Against Camera Sensor Attacks
Synthesis of Pipelined SRSL Circuits
Optimal shielding/spacing metrics for low power design
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses
On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks
Skyrmion-Based Ternary CPU Design
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions
Coupling Noise Mitigation using a Pass Transistor
A New Method for Defining Monotone Staircases in VLSI Floorplans
A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication Systems
Approximate Adder with Hybrid Prediction and Error Compensation Technique
An Asynchronous Analog to Digital Converter for Video Camera Applications
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory
Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC
In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber
A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array
Qubit and T-count Optimized Quantum Circuit Design for Fixed Precision Square Root
Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs
Design and Analysis of a Low Power VLIW DSP Core
Exploration on Routing Configuration of HNoC with Reasonable Energy Consumption
Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural Networks
Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits
A Hardware Architecture for Image Clustering Using Spiking Neural Networks
An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology
Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple
Built-In Self Optimization for Variation Resilience of Analog Filters
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption
ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters
Reliability and Security in Non-volatile Processors, Two Sides of the Same Coin
High-Performance and Energy-Efficient 256-Bit CMOS Priority Encoder
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators
Technology and Power-aware Investigation of Nanostructures for Molecular Field-Coupled Nanocomputing
Area and Delay Efficient Design of a Quantum Bit String Comparator
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES
Scheduling for an Embedded Architecture with a Flexible Datapath
Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints
Inserting Data Encoding Techniques into NoC-Based Systems
2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020
Interconnect Effort - A Unification of Repeater Insertion and Logical Effort
Comparative Analysis of QNN Architectures for Wind Power Prediction: Feature Maps and Ansatz Configurations
Unfolded SiBM BCH Decoders for High- Throughput Low-Latency Applications
Hardware Obfuscation Using Strong PUFs
Hardware-Application Co-Design to Evaluate the Performance of an STDP-based Reservoir Computer
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation
Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing
DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD
Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems
An Efficient Analytical Approach to Path-Based Buffer Insertion
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits
SPN-DPUF: Substitution-Permutation Network Based Secure Circuit for Digital PUF
Variance Optimization of CMOS OpAmp Performances Using Experimental Design Approach
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits
Logic Debugging of Arithmetic Circuits
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core
Petri Net Based Rapid Prototyping of Digital Complex System
MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures
FPGA-based Intruder Detection Systems for Aerial Robots
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
BatchSim: Parallel RTL Simulation Using Inter-Cycle Batching and Task Graph Parallelism
Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications
EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip
Synthesizing Asynchronous Circuits toward Practical Use
HIERA: High-Quality and High-Throughput Dehazing Hardware Accelerator with Reconfigurable Computing Unit
PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications
SCOC IP Cores for Custom Built Supercomputing Nodes
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration
R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques
FPGA Based Novel High Speed DAQ System Design with Error Correction
Terahertz Applications of Carbon Nanotubes and Graphene Nanoribbons
Where is the Achilles Heel under Circuit Aging
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics
Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices
Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration
ILP-Based Global Routing Optimization with Cell Movements
An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications
Force-Directed Performance-Driven Placement Algorithm for FPGAs
Minimized Region of Path-search Algorithm for ASIP-based Connection Allocator in NoCs
Reduction of Power and Test Time by Removing Cluster of Don't-Care from Test Data Set
Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation
VLSI Design and Implementation of Homophonic Security System
Associative Thread Compaction for Efficient Control Flow Handling in GPGPUs
A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network
Application - specific NoC platform design based on System Level Optimization
PUF-Based Secure Test Wrapper for SoC Testing
Molecular MUX-Based Physical Unclonable Functions
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis
MIDAS: Mutual Information Driven Approximate Synthesis
A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology
High Speed Parallel Architecture for Cyclic Convolution Based on FNT
2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018
Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach
A Novel Quantum Generalized Neighbor Interpolation Design for Image Transformations
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks
A Custom Computing System for Finding Similarties in Complex Networks
A Survey of Edge Computing Privacy and Security Threats and Their Countermeasures
EMspice 2.0: Multiphysics Electromigration Analysis Tool for Beyond Moore ICs
IP Security in Structured ASIC: Challenges and Prospects
Neuromorphic Image Sensor Design with Region-Aware Processing
CWAHA: Cluster-Wise Approximation for Hardware implementation of Arithmetic functions
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads
Design of Division Circuits for Stochastic Computing
Assessment of FPGA Implementations of One Sided Jacobi Algorithm for Singular Value Decomposition
High Speed Redundant Adder and Divider in Output Prediction Logic
Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies
A Scalable Parallel SoC Architecture for Network Processors
Reliability Analysis of Phase Change Memory-Based Neuromorphic Circuits
Photonic Convolution Engine Based on Phase-Change Materials and Stochastic Computing
eWatch: Context Sensitive System Design Case Study
Energy-Efficient Embedded Inference of SVMs on FPGA
A Novel Reconfigurable Computation Unit for DSP Applications
Hardware Emulation of FeFET On FPGA
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC
A CORDIC Based Configurable Activation Function for ANN Applications
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design
A 3-Segment Interpolating String DAC with Low-Cost Built-In-Self-Test Capabilities
Transparent Dataflow Execution for Embedded Applications
A Mesh-Buffer Displacement Optimization Strategy
Design-Space Exploration of Multiplier Approximation in CNNs
Synthesis of Self-Resetting Stage Logic Pipelines
On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA
A Parallel Architecture for Hardware Face Detection
Modulo 2n ± 1 Fused Add-Multiply Units
Quantum-Enhanced Classification of Brain Tumors Using DNA Microarray Gene Expression Profiles
Using Intra-Line Level Pairing for Graceful Degradation Support in PCMs
An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs
PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization
Defending the Citadel: Fault Injection Attacks Against Dynamic Information Flow Tracking and Related Countermeasures
A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes
Fault Resilience of DNN Accelerators for Compressed Sensor Inputs
Getting High-Performance Silicon from System-Level Design
Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields
Hardware Security Challenges Beyond CMOS: Attacks and Remedies
Parametric Fault Diagnosis of Analog Circuits using Adaptive Boosting
Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks
RFET-Based Dynamic Differential Logic Cells Against Power Side-Channel Attacks
Navigating the Challenges of Statistical Fault Injection in SRAM-FPGA
Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC)
Emotion Recognition in Older Adults with Quantum Machine Learning and Wearable Sensors
A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews
High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology
A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC
A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems
Slicing Floorplans with Handling Symmetry and General Placement Constraints
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
Synthesis, Technology Mapping and Optimization for Emerging Technologies
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA
Machine Learning-based Prediction for Phase-Based Dynamic Architectural Specialization
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
Message from the Technical Program Chairs; ISVLSI 2024
Mathematical Model for SWAP Gate Minimization on NISQ Hardware
Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function
3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems
Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS Project
FPGA Implementation of a Fixed-Point Arctangent Function Using Harmonized Parabolic Synthesis
Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers
Soft Error Assessment of UAV Control Algorithms Running in Resource-Constrained Microprocessors
Using guiding heuristics to improve the dynamic checking of temporal properties in data dominated high-level designs
VLSI Implementation of an Improved Multiplier for FFT Computation in Biomedical Applications
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond Test
Accelerating Layout Automation Using AI-Driven Smart Routing for Custom Circuit Design
Design of Prefix-Based Optimal Reversible Comparator
Efficient Utilization of Imprecise Blocks for Hardware Implementation of a Gaussian Filter
3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption Constraints
Customizing Skewed Trees for Fast Memory Integrity Verification in Embedded Systems
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells
Fast Evaluation of Analog Circuits Using Linear Programming
Embedding Environmental Intelligence in Low-Cost Drones
Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers
Gyrator-C Based Bandpass Filter with Improved Dynamic Range for Fully Integrated RF Front-End
Multi-Objective Neural Architecture Search for In-Memory Computing
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs
System Support for Environmentally Sustainable Computing in Data Centers
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System
A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling
zk -Sherlock: Exposing Hardware Trojans in Zero-Knowledge
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India
Towards Hardware-Assisted Security for IoT Systems
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees
Low Power Motion Estimation with Probabilistic Computing
Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT
Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits Using Wavelets
2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA
Fast Multi-level Test Generation at the RTL
Partial Product Reduction for Parallel Cubing
A Method for Integrating Network-on-Chip Topologies with 3D ICs
Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices
An Efficient Partitioning Algorithm of Combinational CMOS Circuits
High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis
On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
Variation Aware Routing for Three-Dimensional FPGAs
A DRAM Centric NoC Architecture and Topology Design Approach
Unveiling Proactive Recovery's Preventative Impact on NAND Flash Wearout
In-memory AES Implementation for Emerging Non-Volatile Main Memory
An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse Converter
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
A Network on Chip Architecture and Design Methodology
An Experimental Study of Dynamic Task Graph Parallelism for Large-Scale Circuit Analysis Workloads
Utilizing PCM for Energy Optimization in Embedded Systems
Securing Network-on-Chip Using Incremental Cryptography
Reliable, Secure, and Spectrally Efficient ISAC using Distributed Multiuser MIMO and Non-Orthogonal Waveform
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization
Optimisation of the SHA-2 Family of Hash Functions on FPGAs
A Data-Driven Approach for Embedded Security
Meta-Heuristic Optimization of CNNs with Approximate Error Distributed Multipliers
IR Drop and Ground Bounce Awareness Timing Model
Asymmetrically Banked Value-Aware Register Files
A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal Designs
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI
EXAMINER: IP Extraction Algorithm from MAGIC Logic-in-Memory
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip
An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment
HAJPAQUE: Hardware Accelerator for JSON Parsing, Querying and Schema Validation
Accelerating Equation Solvers using Gauss-Jacobi on Multi-FPGA Systems with Ring NoC
Multi-block APUF with 2-Level Voltage Supply
Bio-Inspired Computing with Emerging Devices: Bridging 2D Materials and Neuromorphic Architectures
Uncertain Model and Algorithm for Hardware/Software Partitioning
Optimization of Comparator Selection Algorithm for TIQ Flash ADC Using Dynamic Programming Approach
Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA
Improved Polygon Method for HIL Simulations in Real Time
A Workload Characterization for the Internet of Medical Things (IoMT)
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel
Resilient Cell-Based Architecture for Time-to-Digital Converter
A New Process Variation Monitoring Circuit
Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication
STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay
Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults
Robust Timing Attack Countermeasure on Virtual Hardware
MAT: A Multi-strength Adversarial Training Method to Mitigate Adversarial Attacks
Secure Energy-Efficient Implementation of CNN on FPGAs for Accuracy Dependent Real Time Task Processing
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM
HardObfSec: Measuring Hardware Obfuscation Security at RTL
A Novel System on Chip (SoC) Test Solution
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays
Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder
A Real Case of Significant Scan Test Cost Reduction
Fully-on-Chip Digitally Assisted LDO Regulator with Improved Regulation and Transient Responses
Accelerating Particle Filter on FPGA
A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation
A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults
Exploiting body biasing for leakage reduction: A case study
Designing Scalable Hybrid Wireless NoC for GPGPUs
A Tuneable CMOS Pulse Generator for Detecting the Cracks in Concrete Walls
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design
Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits
IDE Development, Logic Synthesis and Buffer/Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoC
Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays
Routing Performance Optimization for Homogeneous Droplets on MEDA-based Digital Microfluidic Biochips
Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs
Delay and Energy Efficient Data Transmission for On-Chip Buses
A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions
A New Low-Power Soft-Error Tolerant SRAM Cell
Formal Verification of Integer Dividers: Division by a Constant
Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators
Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization
A Security Architecture for Domain Isolation in Multi-Tenant Cloud FPGAs
New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories
Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model
A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato
Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs
Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios
An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip Multiprocessors
2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019