yusuke1997/dblp-id-title huggingface dataset:
Finite Set Model Predictive Control for PWM Rectifiers Based on Data-driven Neural Network Predictor
Optimal Transport Based and Softplus Loss Functions for Anomaly Detection
Memristive Cellular Automata for Modeling of Epileptic Brain Activity
Instruction buffering for nested loops in low power design
Development of the FES system with neural network + PID controller for the stroke
Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations
A Single Stage Boost Converter for Body Heat Energy Harvesting with Maximum Power Point Tracking and Output Voltage Regulation
An Efficient Algorithm for DTMF Decoding Using the Subband NDFT
Multi-Kernel Attention Encoder For Time-Domain Speech Separation
A new approach of hierarchical optimization to distribution system service restoration
An All Digital Highly Programable TAF-DPS Based True Random Number Generator Working on Principles of Frequency-Mixing and Frequency-Tracking
Parallel iterations for recursive median filter
A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration
Maximum achievable energy reduction using coding with applications to deep sub-micron buses
Design Considerations for Highly Linear Electronically Tunable Resistor
A compact analog active time delay line using SiGe BiCMOS technology
Autotuning LSTM for Accelerated Execution on Edge
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level
High-current clamp for fast-response load transitions of DC-DC converter
Salient object cutout using Google images
Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations
PhotoSaver: Group Photographing Guidance System Using Multi-Task Cascaded Convolutional Networks
What is the importance of selecting features for non-technical losses identification?
A flexible LUT-based carry chain for FPGAs
Low-power static and dynamic high-voltage CMOS level-shifter circuits
System on a Chip for Automated Cell Assays using a Lab-on-CMOS Platform
Improved Methods for the Design of 1-D and 2-D QMF Banks
A Novel Transconductance Block Eliminates the Need for Common-Mode Feedback in Fully Differential Circuits
Real-time H.263+ frame rate control for low bit rate VBR video
A fuzzy membership function circuit in SC technique
Stabilization of fast-scale instabilities in PCM boost PFC converter with dynamic slope compensation
Scan-controlled pulse flip-flops for mobile application processors
A CMOS Compatible Bistable Resistively-coupled Ising Machine-BRIM
Ground-bounce reduction in narrow-band RF front-ends
A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities
Efficient Deep Learning Approaches for Automated Tumor Detection, Classification, and Localization in Experimental Microwave Breast Imaging Data
Neural-Inspired Dendritic Multiplication Using a Reconfigurable Analog Integrated Circuit
Hybrid heterogeneous energy supply networks
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET
Finite element emulation-based solver for electromagnetic computations
Pinning impulsive synchronization in coupled delayed directed dynamical networks
A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array
Thai type style recognition
Image convolution using a probabilistic mapper on USB-AER board
Intellectual property authentication by watermarking scan chain in design-for-testability flow
A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders
Reliability Improvement in RRAM-based DNN for Edge Computing
Leakage power estimation and minimization in VLSI circuits
A low power sinusoidal clock
Video-based Activity Monitoring for Indoor Environments
A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing
A low power neural recording amplifier with programmable gain and bandwidth
Improved Cole-Cole parameter extraction from frequency response using least squares fitting
Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems
On the Usability of Practical Stable n-D Systems for Signal Processing Applications
A general method for sensor linearization based on neural networks
Error-resilience packet scheduling for low bit-rate video streaming over wireless channels
Synthesis of a translinear analog adaptive filter
Towards autonomous adaptive behavior in a bio-inspired CNN-controlled robot
Application-Specific Instruction Generation for SOC Processors
RemEduLa - Remote Education Laboratory for FPGA Design Technology
Development of water-soluble sono/photo-sensitive nanopartices for cancer treatment
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability
Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers
Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors
The design of 8-channel CMOS area-efficient low-power current-mode analog front-end amplifier for EEG signal recording
An Algebraic Construct Method for Cellular Neural Networks
The Capacitively Coupled Chopper Stabilized Amplifier with a DTPA based Demodulator
RF-Rate Hybrid CNN Accelerator Based on Analog-CMOS and Xilinx RFSoC
Effects of noise and jitter on algorithms for bandpass sampling in radio receivers
Rigorous analysis of quantization error of an A/D converter based on β-map
Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems
Anti-aliasing filter improvement in continuous-time feedback sigma-delta modulators
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints
A low complexity complex QR factorization design for signal detection in MIMO OFDM systems
A 5th Order Bilinear Switched-current Chebyshev Filter
A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms
A 16Gbps low power self-timed SerDes transceiver for multi-core communication
A non-uniform sampling approach for the reduction of capacitance spread in SC circuits
A low-power clock frequency multiplier
Coupling effects in an integrated beam-forming transmitter
A SPICE-Based Library for Mechatronic Systems
High-Precision Nano-Amp Current Sensor and Obfuscation based Analog Trojan Detection Circuit
Trace-path analysis and performance estimation for multimedia application in embedded system
A low-distortion and wide dynamic range CMOS imager for wireless capsule endoscopy
A pipelined VLSI architecture for a list sphere decoder
State Models of 2D Positive Systems
A compact and low power logic design for multi-pillar vertical MOSFETs
A discrete algorithm for the regularization of hierarchical VHDL-AMS models
High-Speed Phase-Based Computing
New multiple input fully differential variable gain CMOS instrumentation amplifier
Automatic Control and Management System for Tropical Hydroponic Cultivation
Machine vision using combined frame-based and event-based vision sensor
Current Mode Techniques for Multiple Valued Arithmetic and Logic
Towards Next Generation Video Coding: from Neural Network Based Predictive Coding to In-Loop Filtering
Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages
A reconfigurable video embedding transcoder based on H.264/AVC: Design tradeoffs and analysis
On the relation of circuit theory and signals, systems and communications
A 3-pin 1V 115µW 176×144 autonomous active pixel image sensor in 0.18µm CMOS
Low active-sensitivity allpole active-RC filters using impedance tapering
Applications of symbolic dynamics to UWB impulse radio
Analysis of Digital IIR Filters Processing Finite Numbers of Samples with Single Frequency Initialisation
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power
Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor Circuit
Compactified dynamics and peaking
Analysis and design of soft-switching power factor correction converter
Phase-locked loop based PWM wireless transmitter
A CNN Based Human Bowel Sound Segment Recognition Algorithm with Reduced Computation Complexity for Wearable Healthcare System
High-Q CMOS LC pseudo switched-capacitor bandpass filter with center frequency tuning
Design of a new sense amplifier flip-flop with improved power-delay-product
Creating hard problem instances in logic synthesis using exact minimization
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs
SNR-based frame-level video bit rate allocation
Multi-level successive elimination algorithm for motion estimation in video coding
Spiking Auto-Encoder for Static and Spatio-Temporal Neuromorphic Pattern Reconstruction
Design of an active-inductor-based termination circuit for high-speed I/O
Multi-reference object pose indexing and 3-D modeling from video using volume feedback
A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35µm SiGe BiCMOS
Portable biomarker detection with magnetic nanotags
Modeling of substrate noise block properties for early prediction
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition
Towards efficient polynomial multiplication for lattice-based cryptography
Multigrid-based substrate coupling model extraction
Neimark-Sacker bifurcation in DC-DC converter with photovoltaic module
Architectures for Intraoperative Image Fusion in Brain Surgery
Live Demonstration: A Wearable Multi-Sensory Platform for Closed-Loop Optical Stimulation Control in Treating Muscle Paralysis
Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic
An IF-sampling timing skew-insensitive parallel S/H circuit
Spatially-varying super-resolution for HDTV
Using the sensitivity analysis of the noise spectral density and the sensitivity analysis of the noise figure for practical circuit design
A 6.24-Gb/s wide-input-range serializer ASIC using fixed-data-rate scheme
Progressive Transmission of Motion Capture Data for Scalable Virtual Character Animation
Rate-distortion optimized video streaming with smooth quality constraint
Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing
A 5Gb/s pulse signaling interface for low power on-chip data communication
A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics
A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL
LMI-based synthesis for controlling periodic solutions in a class of nonlinear systems
Generalized n-dimensional k-order systems: computing the transfer function
A precise temperature-insensitive and linear-in-dB variable gain amplifier
Variation-Adaptive Negative Bitline and Skip Bitline Pre-charge Scheme for Low-Power SRAM
Stochastic resonance in an analog current-mode neuromorphic circuit
Modeling of cascade buck converters
Exploiting Weight-Level Sparsity in Channel Pruning with Low-Rank Approximation
On McClellan Transform and 2-D QMF Banks
A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS
A 70-nA 13-ppm/°C All-MOSFET Voltage Reference for Low-Power IoT Systems
Performance and complexity joint optimization for H.264 video coding
Minimizing power with flexible voltage islands
Dynamic coarse grain dataflow reconfiguration technique for real-time systems design
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
S-parameter based macro model of distributed-lumped networks using Pade approximation
A Low-Area, 0.18µm CMOS, 10Gb/s Optical Receiver Analog Front End
Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic Applications
Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems
Image enlargement using the giga-vision sensor model
A Pipelined Bit-Serial Complex Multiplier Using Distributed Arithmetic
Low-power StrongARM Comparator Exploration for Sub-3nm Technology Node
A waveform bounding algorithm for simulation of RLC circuits
Multiple description watermarking for lossy network
Minimax design of two-dimensional FIR digital filters by using an interior-point algorithm
Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions
Fault Attack Countermeasures for Error Samplers in Lattice-Based Cryptography
Data Path Testability Analysis Based on BDDs
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
Intersymbol and intercarrier interference canceller for multi-carrier modulation receivers
Implementation of Multinary Łukasiewicz Logic Using Memristive Devices
A generalized droop-control scheme for decentralized control of inverter-interfaced microgrids
VSCNN: Convolution Neural Network Accelerator with Vector Sparsity
Convolutional Neural Network Accelerator with Vector Quantization
CMOS oversampling Sigma-Delta magnetic to digital converters
Is more redundancy better for on-chip bus encoding
Electromigration aware circuits by using special signal non-default routing rules
Computational methods for analyzing bistability in biochemical reaction networks
Programmable spread spectrum clock generation based on successive phase selection technique
Low-power compact G m -C filters structures
Obstacle avoidance with LGMD neuron: Towards a neuromorphic UAV implementation
Stereo matching with pixel classification and reliable disparity propagation
A digital Class D amplifier design embodying a novel sampling process and pulse generator
Novel SRAM based Temporary Memory for PVT Variation Tolerant Analog In-Memory Computing
Lossy Transmission Line Response via Numerical Laplace Transform Inversion
Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation
A digital time skew calibration technique for time-interleaved ADCs
Dynamic Eccentric Error Compensation for Track Following Control of Optical Disk Driver
Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform
Live Demonstration: Accurate Time Synchronization for Industrial Wireless LAN Systems
Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture
A multi-output on-chip switched-capacitor DC-DC converter for near- and sub-threshold power modes
A 43.7 mW 94 fps CMOS image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation
A CMOS bandgap reference with correction for device-to-device variation
Dynamical analysis of novel Memristor Cellular Nonlinear Network cell topologies
A 188-Length Full Code Rate 333Mbps 1.08mm 2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A
Distributed Port Assignment for Extraction of Power Delivery Networks
Intermediate Signed-Digit Stage to Perform Residue to Binary Transformations Based on CRT
Reduction of gray level disturbances in plasma display panels
Novel µ-power log-domain integrators
Bit allocation for progressive fine granularity scalable video coding with temporal-SNR scalabilities
Timing analysis of tree-like RLC circuits
An efficient motion vector coding algorithm based on adaptive predictor selection
Learned Image Compression Using Adaptive Block-Wise Encoding and Reconstruction Network
Complex modulated critically sampled filter banks based on cosine and sine modulation
Complexity Reduction of FRM Filters via Multiplication-Free Prefilter-Equalizer Structures
Verilog-A modeling of Floating-Gate (FG)-based Multiple-Input Translinear Elements
Design of IIR frequency-response masking filters with near linear phase using constrained optimization
Scalable Complementary FeFET CAM Design
Error Accumulation of Repetitive Image Coding
A 70 pW Self-Compensated Subthreshold Voltage Reference Achieving 190 °C Temperature Range and 0.07%/V Line Sensitivity
Permutation optimization for SIMD devices
Interactive content-based image retrieval using Laplacian mixture model in the wavelet domain
Embedded Processing Pipeline Exploration For Neuromorphic Event Based Perceptual Systems
An implantable power and data receiver and neuro-stimulus chip for a retinal prosthesis system
Possible benefits of moderate inversion for MOSFET transconductors
Current-mode reference shifting solution for MDAC-based analog-to-digital converters
Comparison of Measurement and Readout Strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs
A Novel Hardware-Efficient Network of Ergodic Cellular Automaton Neuron Models and its On-FPGA Learning
Behavioral Modeling of SAR ADCs in Simulink
Efficient Post-Quantum Cryptographic Hardware for Healthcare Applications
Scalable MPEG video coding with improved B-frame prediction
Multi-granularity dynamic analysis of complex software networks
Network optimization problem in tie-set flow vector space and information network resource management
A Wide-Tunning-Range Low-Phase-Noise Colpitts Oscillator with Variable Capacitive Feedback
Designing synthetic biological networks
Increasing the locality of memory access patterns by low-overhead hardware address relocation
A Low Voltage Wave SI Filter Implementation using Improved Delay Elements
Dynamically Configurable FIR Filters Based on Serial MACs and Systolic Arrays
Efficient assignment of inter-die signals for die-stacking SiP design
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems
A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision
Mitigating bad data and measurement delay in nonlinear dynamic state estimation
Fine granularity scalability in MPEG-4 for streaming video
Task partitioning algorithm for intra-task dynamic voltage scaling
A Discrete-Time Delta-Sigma Modulator with Relaxed Driving Requirements And Improved Anti-Aliasing
High-quality texture compression using adaptive color grouping and selection algorithm
A Nonlinear Model for Phase Noise and Jitter in LC Oscillators
Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load
Identifying groups of preventive controls for a set of critical contingencies in the context of voltage stability
Subband blind source separation considering acoustic reverberation characteristics
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period
Design of Active Inductors for Minimizing Output Noise of LC-Simulation Type Filters
Biased Compressor Based Approximate Multiplier Design Using Genetic Algorithm
Design of a computer-aided visual system for Total Hip Replacement surgery
Reconfigurable Lab-on-Chip platform for algae cell manipulation
A bidirectional neural interface IC with high voltage compliance and spectral separation
CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing
Multirate double-sampling hybrid CT/DT sigma-delta modulators for wideband applications
Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators
A tunable, video-frequency, low-power, single-amplifier biquadratic filter in CMOS
Peaking reduced STF design for CT ΣΔ modulators with selective pole compensation
Harmonic vs. geometric mean Sinh integrators in weak inversion CMOS
Interference of Spread-Spectrum Switching-Mode Power Converters and Low-Frequency Digital Lines
Analysis of Tones in the Double Loop SigmaDelta Modulator with Unstable Filter Dynamics
Current-mode and voltage-mode quadrature oscillator employing multiple outputs CCIIs and grounded capacitors
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
A generalized signal reconstruction method for designing interpolation filters
An improved aVLSI axon with programmable delay using spike timing dependent delay plasticity
Analytical Transient Response and Propagation Delay Model for Nanoscale CMOS Inverter
Stability of two-dimensional discrete systems
Short Circuit Current of Induction Generators
Roundoff noise results on optimal and block-optimal digital filter structures
H.264 native video watermarking method
Boundary control of a bipolar square-wave generator using second-order switching surface
Network-on-chip quality-of-service through multiprotocol label switching
Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor
A VLSI-efficient signed magnitude comparator for { 2n-1, 2n, 2n +2n+1-1} RNS
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS
An SDRAM controller optimized for high definition video coding application
The development of bipolar log domain filters in a standard CMOS process
A tail-resonance calibration technique for wide tuning range LC VCOs
Towards Efficient Modular Adders based on Reversible Circuits
A Platform for Full-Stack Functional Programming
Effective hardware-oriented technique for the rate control of JPEG2000 encoding
CMOS image sensor readout employing in-pixel transistor current sensing
FPGA Implementation of X- and Heart-shapes Controllable Multi-Scroll Attractors
A design of source matched MAP receiver for image transmission
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array
AI-Based Optimization of a DC-DC Buck Converter Control Network Across DCM and CCM Operating Region
An adaptive algorithm for fast identification of FIR systems
Digital Implementation of a Spiking/Bursting Neuron Model with Low Resources
Low power reduced-complexity error-resilient MIMO detector
Implementation and analysis of microwave switch in CMOS-MEMS technology
Obstacle avoidance and target acquisition in mobile robots equipped with neuromorphic sensory-processing systems
A 0.5V time-domain instrumentation circuit with clocked and unclocked ΔΣ operation
A novel current mode winner-take-all circuit for artificial neural networks
Live Demonstration: Layer-wise Configurable CNN Accelerator with High PE Utilization
Neural network approach for estimation of load composition
Analysis of interleaved converters with WTA-based switching
An inductively tuned CMOS astable multivibrator
A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR
Resource adaptation based on MPEG-21 usage environment descriptions
A novel hybrid active-passive pixel with correlated double sampling CMOS readout circuit for medical x-ray imaging
A study for replacing CMOS gates by equivalent inverters
SPICE-simulation of Nonlinear Effects in Filed-Effect-Transistors Caused by Thermal Power Feedback
A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier
The Adiabatic Capacitive Neuron: A Cross CMOS Technology Performance Comparison
A Dual-Vt low leakage SRAM array robust to process variations
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation
Low-Complexity and High-Throughput Number Theoretic Transform Architecture for Polynomial Multiplication in Homomorphic Encryption
Experimental detection of bifurcations and sliding in DC-DC power converters
On the effects of motion on the quality of PAL signals
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system
Real-time, high-resolution simulation of the auditory pathway, with application to cell-phone noise reduction
An Efficient Finite Precision Realization of the Adaptive Decision Feedback Equalizer
Parallel pipelining configurable multi-port memory controller for multimedia applications
Open Source RFNoC-Based Testbed for Millimeter-Wave Experimentation using USRP Software Defined Radios
Overview: Memristive devices, circuits and systems
A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz
Power system on a chip (PSoC)
Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading