yusuke1997/dblp-id-title huggingface dataset:
VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers
Enhancing Performance of Computer Vision Applications on Low-Power Embedded Systems Through Heterogeneous Parallel Programming
A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation
Fast global interconnnect driven 3D floorplanning
VLSI-SoC: Internet of Things Foundations - 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended Selected Papers
A PLL-Based RF Synthesizer Test System
Design of a GaAs redundant divider
Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis
Trustworthy Hardware Design with Logic Locking
Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancing
Algebraic Techniques for Rectification of Finite Field Circuits
Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics
A Stochastic Limit Approach to the SAT Problem
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture
A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures
Gain Enhancement of Antenna-on-Chip at 94 GHz with an Integrated Artificial Magnetic Conductor for 6G System-on-Chip
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor
Topology-aware reliability optimization for multiprocessor systems
New parallel programming techniques for hardware design
High-Level Synthesis design approach for Number-Theoretic Multiplier
3-D integration and the limits of silicon computation
Lower Power Processor Design Issues
Efficient Implementation of Activation Functions for LSTM accelerators
Design and Analysis of Logic Locking Techniques
VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France
Graph-Based Design Specification of Parallel Computation
The system is really in the SoC : new investment opportunities
An Area-Efficient Bit-Serial Integer Multiplier
Hardware implementation of real-time multiple frame super-resolution
Mobile Phones Hematophagous Diptera Surveillance in the field using Deep Learning and Wing Interference Patterns
Exploiting Approximate Computing to Increase System Lifetime
Minimization of EP-SOPs via Boolean relations
Energy-Driven Precision Scaling for Fixed-Point ConvNets
IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018
Can Asynchronous Techniques Help the SoC Designer?
Filtering dirty data in DRAM to reduce PRAM writes
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors
Bondgraph execution as a new algorithm for circuit simulation
A broad strategy to detect crosstalk faults in network-on-chip interconnects
Complementary logic interface for high performan optical computing with OLUT
A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip
Micro CMOS image sensor for multi-area imaging
Efficient Dynamic Logic Magnitude Comparators
Enhancing the Security of IJTAG Network Using Inherently Secure SIB
Implementation of core coalition on FPGAs
Regression based circuit matrix models for accurate performance estimation of analog circuits
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017, Revised and Extended Selected Papers
A 1.62 µW 8-channel ultra-high input impedance EEG amplifier for dry and non-contact biopotential recording applications
Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression
Embedded TCP/IP Controller for a RISC-V SoC
MDCT IP Core Generator with Architectural Model Simulation
Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors
A reconfigurable MPSoC-based QAM modulation architecture
A novel low-leakage 8T differential SRAM cell
Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization
Software-Based Self-Test for Transition Faults: a Case Study
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator
Transformative Hardware Design Following the Model-Driven Architecture Vision
Advances in Digital Image Processing for Document Reproduction
A Novel MicroPhotonic Structure for Optical Header Recognition
Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees
PVT variation detection and compensation methods for high-speed systems
Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells
A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs
High-Level Synthesis design approach for Number-Theoretic Transform Implementations
Hardware integrated quantization solution for improvement of computational H.264 encoder module
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts
A Smart Memory Accelerated Computed Tomography Parallel Backprojection
An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unit
Single board image processing unit for vehicle guidance
Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz standards
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization
High-Performance Hardware Accelerators for Next Generation On-Board Data Processing
HLS Support for Polymorphic Parallel Memories
Improved read and write margins using a novel 8T-SRAM cell
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm
Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility
Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits
A high-driving class-AB buffer amplifier with a new pseudo source follower
Examining Thread Vulnerability analysis using fault-injection
New techniques for selecting test frequencies for linear analog circuits
Validation of asynchronous circuit specifications using IF/CADP
Stimuli generation through invariant mining for black-box verification
JAIP-MP: A four-core Java application processor
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study
A novel elementary memristive system
MCS-NTT: Multi-Chip System Design for NTT Acceleration
Meta VHDL for Higher Level Controller Modeling and Synthesis
Ultra low voltage and high speed CMOS flip-flop using floating-gates
28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults
A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency
Cyber-Physical Systems Integration in a Production Line Simulator
Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems
A DfT Strategy for Detecting Emerging Faults in RRAMs
Accelerating software radio: Iris on the Zynq SoC
Switchbox Routing by Pattern Matching
A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment
Context-aware compiled simulation of out-of-order processor behavior based on atomic traces
Safety oriented automotive MCU power management
Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures
A New Phase Noise Model for TSPC based divider
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
Incremental placement for structured ASICs using the transportation problem
PR-PUF: A Reconfigurable Strong RRAM PUF
Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto Analysis
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies
Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization
A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications
Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOS
Probabilistic power consumption estimation in digital circuits
High-Density Standard Cell Library for Sequential 3D Integrated Circuits
Optimistic clock adjustment for preventing Better-than-worst-case violations
Automated Synthesis of Multi-Port Memories and Control
Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization
Power-aware test optimization for core-based 3D-SOCs under TSV-constraints
IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq
A Bondwire Inductor Based Flash ADC Assisted DC-DC Buck Converter
Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting Applications
First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model
Laser-Induced Fault Effects in Security-Dedicated Circuits
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques
Power optimization for conditional task graphs in DVS enabled multiprocessor systems
VLSI-SoC: An Enduring Tradition
Secrecy Spectral Efficiency Optimization in RIS-Enabled MIMO Communication Systems
Enabling efficient system design using vertical nanowire transistor current mode logic
A complete over-current/short-circuit protection system for Low-Drop Out regulators
A self-powered IoT SoC platform for wearable health care
A Unity Feedback Length-Extend Delta-Sigma Modulator for Fractional-N Frequency Synthesizer
Energy impact in the design space exploration of loop buffer schemes in embedded systems
A low-power, high-speed DCT architecture for image compression: Principle and implementation
Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003
Lightweight Active Fences for FPGAs
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics
Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors
Hierarchical Retiming Including Pipelining
A Hybrid Power Estimation Technique to improve IP power models quality
A decimal squarer with efficient partial product generation
An Efficient Performance-Driven Analog IC Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance Regressors
A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic
Designing Routing and Message-Dependent Deadlock Free Networks on Chips
Synthesis of SFQ Circuits with Compound Gates
SyntHorus-2: Automatic prototyping from PSL
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
qCrop: An IoT Based Framework to Enhance Crop Productivity in Smart Agriculture
Exploration of Techniques to Assess Soft Errors in Multicore Architectures
Optimized active and power-down mode refresh control in 3D-DRAMs
ThruChip interface (TCI) for 3D networks on chip
Implementation of the volume rendering algorithm using a low-power design-style
Static Versus Dynamic Power Losses in CMOS VLSI Systems Considering Temperature
Digital Hardware Design Based on Metamodels and Model Transformations
Bio-Inspired Reconfigurable Architecture for Reliable Systems
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow
Prolog Interpreter and its Parallel Extension
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures
FPGA-implementation techniques to efficiently test application readiness of mixed-signal products
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs
A Wearable Neuro-Degenerative Diseases Classification System Using Human Gait Dynamics
Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation
Process-aware side channel monitoring for embedded control system security
An integrated SoC for science data processing in next-generation space flight instruments avionics
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure
Spatially-Varying Image Warping: Evaluations and VLSI Implementations
Cost-effective TSV redundancy configuration
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap
Hybrid multiplierless FIR filter architecture based on NEDA
Area- and throughput-optimized VLSI architecture of sphere decoding
Partitioning and hierarchical description of self-testable designs
Fast fixed-point optimization of DSP algorithms
A Fault Tolerant and High Speed Instruction Systolic Array
A transformational approach to asynchronous high-level synthesis
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method
On Test Generation for Microprocessors for Extended Class of Functional Faults
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation
Calculation Methodology for Flexible Arithmetic Processing
A center-aligned digital pulse-width modulator for envelope modulation of polar transmitters
A Novel Smart Power ASIC (SPIC) for Integrated Control of Cascaded Power Converters
Future Directions for VLSI and Software Engineering
Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization
Modeling frequency response of gm-boosted inductorless Common-Gate LNA
A Unified Functional Safety EDA Framework for Accurate Diagnostic Coverage Estimation
Multi-label HD Classification in 3D Flash
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Fault tolerant design for low power hierarchical search motion estimation algorithms
Robust FinFET Schmitt Trigger Designs for Low Power Applications
8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology
Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers Family
A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion
Automated Framework for Fast Synthesis of Approximate Hardware Accelerators
A Study on the 8bit Pipeline RISC Processor
An FPGA-based Hardware Accelerator for Scene Text Character Recognition
Exponential Challenges, Exponential Rewards - The future of Moore's Law
1.8V 0.18µm CMOS Novel Successive Approximation ADC
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
CMOS Implementation of Threshold Gates with Hysteresis
An analog programmable multi-dimensional radial basis function based classifier
An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems
Delay Testing Based on Multiple Faulty Behaviors
A Flexible Design Flow for a Low Power RFID Tag
Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring
A novel double floating-gate unified memory device
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes
On the Design and Development of a ReRAM-based Computational Memory Prototype
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing
Silicide Optimization for Electrostatic Discharge Protection Devices in Sub-100 nm CMOS Circuit Design
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes
Efficient Hardware/Software Co-design for NTRU
7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltage
Optimum IR drop models for estimation of metal resource requirements for power distribution network
Clockless asynchronous delta modulator based ADC for smart dust applications
A Low Power BIST Architecture for FPGA Look-Up Table Testing
Adaptation Strategies in Multiprocessors System on Chip
Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design
Testability of SPP Three-Level Logic Networks
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays
Improving post-silicon error detection with topological selection of trace signals
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks
Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration
ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching
An equation-based battery cycle life model for various battery chemistries
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing
Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits
Area-efficient 3-input decimal adders using simplified carry and sum vectors
AC-coupling strategy for high-speed transceivers of 10Gbps and beyond
Gate-controlled doping in carbon-based FETs
Physical Design Issues in 3-D Integrated Technologies
Learning Annealing Schedules for Channel Routing
Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras
A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process
Variation-aware and adaptive-latency accesses for reliable low voltage caches
DV-TSE: Difference Vector Based Test Set Embedding
Functional Verification of Hardware Dividers using Algebraic Model
From Informal Specifications to an ABV Framework for Industrial Firmware Verification
A low-power deblocking filter architecture for H.264 advanced video coding
Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures
A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA
27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019
Keynote 1 - VLSI 2.0: R&D Post Moore
Towards energy effective LDPC decoding by exploiting channel noise variability
Improved read voltage margins with alternative topologies for memristor-based crossbar memories
A high performance RISC microprocessor
Using SDN Strategies to Improve Resource Management On a NoC
Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips
Automatic Timing Closure for Relative Timed Designs
MIST: monitor generation from informal specifications for firmware verification
Analysis of Ring Oscillator structures to develop a design methodology for RO-PUF circuits
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013
SOC Debug Challenges and Tools
Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS
Hardware-Enabled Secure Firmware Updates in Embedded Systems
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers
Soft Error Reliability Analysis of Autonomous Vehicles Software Stack
ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference
Communication centric on-chip power grid models for networks-on-chip
1024-point pipeline FFT processor with pointer FIFOs based on FPGA
Implementing cellular automata modeled applications on network-on-chip platforms
MPEG-4 HVXC Real-Time Implementation on Floating Point DSP
Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices
Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process
Advanced Quality Assurance Platform for Robust Process Design Kits
A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs
Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations
High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor
A hybrid embedded compression codec engine for ultra HD video application
Subthreshold-Hybrid Solutions for Thermal Sensor and Reference Circuits in Advanced CMOS
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers
State-holding in Look-Up Tables: application to asynchronous logic
I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO)
Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design
DFS covert channels on multi-core platforms
A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM
Energy-efficient partitioning of hybrid caches in multi-core architecture
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture
VCTA: A Via-Configurable Transistor Array regular fabric
Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM
BIST Scheme for Low Heat Dissipation and Reduced Test Application Time
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs
Synthesis of multi-variate stochastic computing circuits
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking
A Two-Level Reconfigurable Architecture for Digital Signal Processing
Analyzing the behavior of FinFET SRAMs with resistive defects
Parallel Architecture and VLSI Implementation of a 80MHz 2D-DCT 80 MHz 2D-DCT/ICDT Processor
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis
STT-RAM based energy-efficiency hybrid cache for CMPs
A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs
Impact of technology scaling on performance of domino logic in nano-scale CMOS
Estimating design time for system circuits
A digital microfluidic biochip synthesis framework
An Integrated Environment for the Design and Simulation of Self-Timed Systems
A Statistical Wafer Scale Error and Redundancy Analysis Simulator
Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems
Signal Coverage Computation in Formal Verification
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners
A Rule-Based Software Testing Method for VHDL Models
Digital CMOS neuromorphic processor design featuring unsupervised online learning
High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation
Resource Management of Automotive Engine Control Units
A Distributed Body-Biasing Strategy for Asynchronous Circuits