yusuke1997/dblp-id-title huggingface dataset:
Improving SAT-based Combinational Equivalence Checking through circuit preprocessing
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
A flexible communication scheme for rationally-related clock frequencies
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCs
A Flash-based Digital to Analog Converter for Low Power Applications
Buffer Library Selection
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
Characterizing On-Chip Traffic Patterns in General-Purpose GPUs: A Deep Learning Approach
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
Don't-Care Identification on Specific Bits of Test Patterns
Advances and Challenges of Rank Metric Cryptography Implementations
Robust Design of High Fan-In/Out Subthreshold Circuits
The Augmint multiprocessor simulation toolkit for Intel x86 architectures
An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems
A Compiler-Assisted Data Prefetch Controller
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era
A Double-Latched Asynchronous Pipeline
Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matching
A high-performance, low-overhead microarchitecture for secure program execution
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
Cap: Exploiting Data Correlations to Improve the Performance and Endurance of SSD RAID
Fine-Grained Shared Cache Interference Analysis Using Basic Block's Execution Time
Statistical simulation of chip multiprocessors running multi-program workloads
AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
Trace-based automated logical debugging for high-level synthesis generated circuits
Big data on low power cores: Are low power embedded processors a good fit for the big data workloads?
About Set and Skewed Associativity on Second-Level Caches
RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache
Software Synthesis for Complex Reactive Embedded Systems
Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study
A wirelessly powered system with charge recovery logic
Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification
Strongly NP-Hard Discrete Gate Sizing Problems
Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays
Design methodology for a 1.0 GHz microprocessor
Persistent Spiral Storage
Power-Constrained Microprocessor Design
Silicon microsystems merging sensors, circuits and systems
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Process variations-aware resistive associative processor design
Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Loose-Ordering Consistency for persistent memory
Processors for Mobile Applications
Enhancing dual-Vt design with consideration of on-chip temperature variation
R-Cache: A Highly Set-Associative In-Package Cache Using Memristive Arrays
Modeling of Noisy Quantum Circuits using Random Matrix Theory
Trading Off Temperature Guardbands via Adaptive Approximations
Reading Between the Dies: Cross-SLR Covert Channels on Multi-Tenant Cloud FPGAs
A case for small row buffers in non-volatile main memories
Contention-aware application mapping for Network-on-Chip communication architectures
PlaidML-HE: Acceleration of Deep Learning Kernels to Compute on Encrypted Data
Universal Neural Network Acceleration via Real-Time Loop Blocking
An Efficient Hybrid Parallel Compression Approximate Multiplier
VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages
OME: An Optimized Modeling Engine for Disk Failure Prediction in Heterogeneous Datacenter
PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks
APAC: An Accurate and Adaptive Prefetch Framework with Concurrent Memory Access Analysis
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits
Timing-driven routing for symmetrical-array-based FPGAs
k-time Forced Simulation: A Formal Verification Technique for IP Reuse
Caching processor general registers
LAK: A Low-Overhead Lock-and-Key Based Schema for GPU Memory Safety
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams
AdaptBit-HD: Adaptive Model Bitwidth for Hyperdimensional Computing
FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing
Stochastic-HD: Leveraging Stochastic Computing on Hyper-Dimensional Computing
An Even Wiring Approach to the Ball Grid Array Package Routing
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits
Trace Cache Performance Parameters
Rapid prototyping of self-timed circuits
An Environment for Exploring Low Power Memory Configurations in System Level Design
An automated runtime power-gating scheme
Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family
The PowerPC TM 604 Microprocessor Design Methodology
ALMP: A Shifting Memory Architecture for Loop Pipelining
Technique to Eliminate Sorting in IP Packet Forwarding Devices
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
Efficient test response compaction for robust BIST using parity sequences
Mapping Design Knowledge from Multiple Representations
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
Boolean circuit design using emerging tunneling devices
SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships
Statistical analysis and modeling for error composition in approximate computation circuits
Timed Binary Decision Diagrams
System-level design verification in the AT&T Computer Division: tools
Write-Optimized and Consistent RDMA-based Non-Volatile Main Memory Systems
Power Driven Partial Scan
A Low Energy Set-Associative I-Cache with Extended BTB
MetaTableLite: An Efficient Metadata Management Scheme for Tagged-Pointer-Based Spatial Safety
Accurate Prediction of ReRAM Crossbar Performance Under I-V Nonlinearity and IR Drop
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs
Benefits and Costs of Power-Gating Technique
Practical Asynchronous Controller Design
High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques
An optimized scaled neural branch predictor
Hardware Cache Locking for All Memory Updates
Hardware Efficient FIR Filter Architectures Using Accurate Unary Stochastic Computing
Revisiting Capacitor-Based Trojan Design
Low power data format converter design using semi-static register allocation
Single Chip PCI Bridge and Memory Controller for PowerPC TM Microprocessors
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory
Scenario-based design space exploration of MPSoCs
Delay Models for Verifying Speed-Dependent Asynchronous Circuits
Test generation by fault sampling
Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis
Performance Driven Global Routing Through Gradual Refinement
Design Automation of Test for the EX/9000 TM Series Processors
Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder
Extending data prefetching to cope with context switch misses
Post-layout OPE-predicted redundant wire insertion for clock skew minimization
RTL Design Verification by Making Use of Datapath Information
Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability
Power-Sensitive Multithreaded Architecture
Hammering the Diagnosis: Rowhammer-Induced Stealthy Trojan Attacks on ViT-Based Medical Imaging
Multi-dimensional interleaving for time-and-memory design optimization
Formal Verification of an Industrial System-on-a-Chip
Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems
Cache replacement based on reuse-distance prediction
Twiddle factor transformation for pipelined FFT processing
A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211
Efficient mode changes in multi-mode systems
Power and Area Efficient Sorting Networks Using Unary Processing
Variability-Driven Buffer Insertion Considering Correlations
Partitioning in time: a paradigm for reconfigurable computing
Combined hardware selection and pipelining in high performance data-path design
High level profiling based low power synthesis technique
BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications
An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing
Conveyor: Towards Asynchronous Dataflow in Systolic Array to Exploit Unstructured Sparsity
Distributed thermal-aware task scheduling for 3D Network-on-Chip
Delay-Driven Physically-Aware Logic Synthesis with Informed Search
A Performance Analysis of the Active Memory System
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
Welcome to ICCD 2011!
Error tolerance in parallel simulated annealing techniques
Algorithms to simplify multi-clock/edge timing constraints
Masked Gadgets for Integer-Floating-Point Conversion with Applications to Falcon
Architecture implementation of an improved decimal CORDIC method
Theory and Design of Two-Rail Totally Self-Checking Basic Building Blocks
Minimizing Read Disturb via Localized Page Allocation for Modern NAND Flash-Based SSDs
Timing analysis considering IR drop waveforms in power gating designs
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks
Improved ZDN-arithmetic for Fast Modulo Multiplication
A fast and energy efficient branch and bound algorithm for NoC task mapping
Xtensa with User Defined DSP Coprocessor Microarchitectures
Ghidorah: Fast LLM Inference on Edge with Speculative Decoding and Hetero-Core Parallelism
Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor
A Test Processor Concept for Systems-on-a-Chip
Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow
Synthesis for testability of large complexity controllers
A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology
Tear Up the Bubble Boom: Lessons Learned From a Deep Learning Research and Development Cluster
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors
Efficient Linear System Solution Techniques in the Simulation of Large Dense Mutually Inductive Circuits
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing
An energy model for graphics processing units
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
Reduce Register Files Leakage Through Discharging Cells
Deep submicron design techniques for the 500 MHz IBM S/390 G5 custom microprocessor
Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators
Dynamic Heterogeneous Voltage Regulation for Systolic Array-Based DNN Accelerators
Dynamic front-end sharing in graphics processing units
Leveraging dynamic slicing to enhance indirect branch prediction
Testability analysis and insertion for RTL circuits based on pseudorandom BIST
Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives
30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012
Knowledge-based analog circuit synthesis with flexible architecture
Efficient Symbolic Support Manipulation
Power-state-aware buffered tree construction
Asynchronous 2-D discrete cosine transform core processor
Power-sensitive multithreaded architecture
Improved testability evaluations in combinational logic networks
Generic Universal Switch Blocks
TiLA: Twin-in-the-Loop Architecture for Cyber-Physical Production Systems
An FPGA based Configurable I/O System for AC Drive Controllers
Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991
Allocation and Data Arrival Design of Hard Real-time Systems
Exploring the interplay of yield, area, and performance in processor caches
Fast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications
ICON: An IR Drop Compensation Method at OU Granularity with Low Overhead for eNVM-based Accelerators
ATPG-Based Weighted Scan Chain Control for Programmable Low-Power LBIST
Improving GPU Robustness by making use of faulty parts
A file-based adaptive prefetch caching design
A Waveform Independent Gate Model for Accurate Timing Analysis
Defect-based test optimization for analog/RF circuits for near-zero DPPM applications
Phoenix NoC: A distributed fault tolerant architecture
Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division
PEPPER - a timing driven early floorplanner
ASOP: Arithmetic Sum-of-Products Generator
Re-examining cache replacement policies
UCLOCK: Automated Design of High-Peformance Unclocked State Machines
A low power buffer-aided vector register file for LTE baseband signal processing
A radix-10 digit recurrence division unit with a constant digit selection function
R 2 Hash: A Read-Optimized and Resize-Friendly Hashing Index for Persistent Memory
NexusCIM: High-Throughput Multi-CIM Array Architecture with C-Mesh NoC and Hub Cores
A comparative study of wearout mechanisms in state-of-art microprocessors
A Common Backend for Hardware Acceleration on FPGA
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures
Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology
3D stacked power distribution considering substrate coupling
On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond
Signal propagation in high-speed MCM circuits
Design-Space Exploration of Power-Aware On/Off Interconnection Networks
Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines
Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Mobile 3D Graphics Applications
VEA: An FPGA-Based Voxel Encoding Accelerator for 3D Object Detection with LiDAR
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
VLSI Design of On-Line Add/Multiply Algorithms
Automatic identification of assertions and invariants with small numbers of test vectors
Locating Tiny Sensors in Time and Space: A Case Study
Composable Template Attacks Using Templates for Individual Architectural Components
Discrete Drive Selection for Continuous Sizing
More Space may be Cheaper: Multi-Dimensional Resource Allocation for NVM-based Cloud Cache
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration
Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing
Critical Net Routing
AIG rewriting using 5-input cuts
PSACS: Highly-Parallel Shuffle Accelerator on Computational Storage
BNRV: A Lightweight SIMD Extension for Efficient BitNet Inference on RISC-V CPUs
Architectural Considerations for Energy Efficiency
Adaptable architectures for distributed visual target tracking
Efficient Microprocessor Design Space Exploration via Space Partitioning
Design and Test Automation-Gigascale Integration (GSI) in the 21st Century
Testability Considerations
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Scalable trace signal selection using machine learning
A New High Performance Field Programmable Gate Array Family
Energy-aware synthesis of application specific MPSoCs
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits
Characterizing the costs and benefits of hardware parallelism in accelerator cores
Enhanced Graphics Techniques for Improving Depth Perception Accuracy in Magnified Virtual Environments
An Experimental Study on The Unfairness in Adaptive Streaming with HTTP/2 Server Push
High Capacity Steganography on Float-Point Number with Single Precision
Epidemic Prevention System Based on Voice Recognition Combined with Intelligent Recognition of Mask and Helmet
Combined Classification of Hyperspectral and LiDAR Data based on Dual-Channel Cross-Transformer
A Multi-scale Framework for Visual Grounding
wganBCS: Block-wise Image Compressive Sensing: Model using Wasserstein GAN
Engineering Vehicle Recognition and Multi-Object Tracking System based on YOLOv5 and DeepSort Algorithm
Mixup Augmentation for Deep Hashing
Understanding Positive Impact of Game Interactivity in Education
Motor Imagery EEG Classification Based on CEEMDAN-CWT Characterization
LiDAR Aided Integrated Navigation System for Indoor Environments
Text Detection and Recognition in Natural Scenes Based on TWO-DIMENSIONAL Attention
Image-Based Fashion Recommendation with Attention to Users' Interests
Multi-Scale Spatial Temporal Graph Convolutional LSTM Network for Skeleton-Based Human Action Recognition
A Novel Approach for Concrete Crack and Spall Detection Based on Improved YOLOv8
Proceedings of the 4th International Conference on Video, Signal and Image Processing, VSIP 2022, Shanghai, China, November 25-27, 2022
VSIP 2021: 3rd International Conference on Video, Signal and Image Processing, Wuhan, China, November 19 - 21, 2021
Cross-modal and Semantics-Augmented Asymmetric CycleGAN for Data-Imbalanced Anime Style Face Translation
Design and Testing of a Corpus for Forensic Speaker Recognition Using MFCC, GMM and MLE
Frequency Hopping Signal Sorting of UAV Based on Image Noise Reduction Technology
Modulation Index Estimation of CPM Signals Based on First-Order Cyclic Moments
3D Visualization Scene Technology and the Application for the Planning of Channel Land Consolidation
Failure Mode Analysis and Infrared Image Recognition of Crystalline Silicon PV Module
Activity Recognition in Industrial Environment using Two Layers Learning
Third-order Volterra Model Based on DUPSO for EEG Signal Denoising
Pneumonia Detection on Chest X-rays With Attention Mask Data Augmentation
Interpretation Study of Unknown Oracle Bones Based on Self-training Learning
Blind Motion Deblurring Based on Generative Adversarial Networks
Freshness Recognition of Fruit and Vegetable Images using GANs Series Data Augmentation
An Efficient Convolution Network with Adaptive receptive field feature for High-Resolution Remote Sensing Change Detection
Interactive Intelligent 3D Surveying Vehicle Based on Deep Learning
Research on the Plant Leaf Disease Region Extraction
A No-reference Image Quality Assessment Algorithm Based on Human Visual Perception Process Reconstruction
Image Matching Research Based on Improved SIFT Algorithm
Future of the Electrical Engineering Education on the AR and VR Basis
Traffic Sign and Vehicle Classification based on Machine Learning
A Stacking Ensemble Approach for Supervised Video Summarization
A novel initialization method for monocular visual inertial navigation
Self-Supervised Visual Odometry with Ego-Motion Sampling
Research on Interactive Object Generation in VR Games Based on Grid Deformation
A Practice of Combining Game and Exercise using Virtual Reality
A Security Steganography Scheme Based On HDR Image
Deep Learning-based Experimental System Design for Fatigue Driving Detection
Novel Approaches of Abdominal Computed Tomography Image Super Resolution based on Deep Residual Learning
DeepPrism: Channel Convolution for Lightweight Generative Models
A Lightweight Anchor-Free Detector Using Cross-Dimensional Interactive Feature Balance for SAR Ship Detection
Research on hyperspectral image classification based on improved deep cross-domain few-shot learning
Skeleton-Based Action Recognition with UAV Views
Research on refrigeration simulation based on LNG cold energy recovery
Proceedings of the 5th International Conference on Video, Signal and Image Processing, VSIP 2023, Harbin, China, November 24-26, 2023
Channel estimation for massive MIMO systems based on adaptive angular domain compensation
Joint Classification of Multi-Source Remote Sensing Data Based on Multi-Scale Features and Attention Mechanism
Chip Surface Defect Detection Algorithm Based on Improved YOLOv3
Surface Rust Segmentation Based on Neighborhood Maximum Threshold
A Novel Demodulation Method for CPM Signals in Satellite Communications
Robust DOA Estimation in Strong Clutter Environment based on Subarray STAP
Semantic Computing Enhancement of Industrial Augmented Reality Solutions with Machine Learning
A Comparative Study of the Performance of Personnel Detection based on Visible and Infrared Images
The Influence of Accounting Information System Quality and Human Resource Competency on Information Quality
Scrum Based Framework for Teaching Software Engineering for Game Development
A Comparison of Three Swarm-Based Optimization Algorithms in Wind Turbine Radar Clutter Micro-Motion Parameters Estimation
Human Action Recognition using Pre-trained Convolutional Neural Networks
Multi-user Steerable Virtual Reality Cycling System with 3D Virtual Explorable Environment
Research on a transmission line fault detection method based on improved YOLOv7-Tiny
Attention-based Multi-View Stereo Network
Recapture Detection to Fight Deep Identity Theft
Binocular Gaze Estimation with Single Camera and Single Light Source
Multi-Object Detection and Classification in Construction Sites Based on YOLOv5
VSIP '20: 2020 2nd International Conference on Video, Signal and Image Processing, Jakarta Indonesia, December, 2020
Transmission line deformation monitoring based on saliency target
Research on a Hyperplane Decomposition NMF Algorithm Applied to Speech Signal Separation
Real Time Hand Gesture Recognition in Industry
Passive Sonar Particle Filter Tracking Method Based on Target Spectrum Features
Research on Layout Optimization of Ship Command Room Based on Dynamic Analysis of Visual Field of Virtual Ray
A Salient Object Detection Model Based on Local-region Contrast for Night Security and Assurance
A Model Based on Dense Connection 3D-2D-CNN for Hyperspectral Image Classification
Clustering Analysis and Visualization of Terrorist Attack Data
VSIP 2019: International Conference on Video, Signal and Image Processing, Wuhan, China, October, 2019
A New Method of Specific Emitter Feature Extraction Based on IQ Imbalance
CNN-based Image Super-Resolution and Deblurring
Measurement and Analysis of Electrophysiological Propagation on the Cardiac Slice-based Biosensor