yusuke1997/dblp-id-title huggingface dataset:
Verification of tree-based hierarchical read-copy update in the Linux kernel
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors
High speed ASIC implementations of leakage-resilient cryptography
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators
FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions
Bus access optimisation for FlexRay-based distributed embedded systems
A reconfigurable cache memory with heterogeneous banks
A machine-learning-guided framework for fault-tolerant DNNs
Hardware-assisted rootkit detection via on-line statistical fingerprinting of process execution
Profit maximization through process variation aware high level synthesis with speed binning
CircularScan: A Scan Architecture for Test Cost Reduction
Paper, pen and ink: an innovative system and software framework to assist writing rehabilitation
CLAST: Cross-Layer Approximate High-Level Synthesis with Configurable Approximate Three-Operand Adders
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip
Security in industrie 4.0 - challenges and solutions for the fourth industrial revolution
Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance
Data Flow Testing for SystemC-AMS Timed Data Flow Models
In-Field Detection of Small Delay Defects and Runtime Degradation Using On-Chip Sensors
On the relationship between stuck-at fault coverage and transition fault coverage
High performance reliable variable latency carry select addition
Liveness-Aware Checkpointing of Arrays for Efficient Intermittent Computing
A dynamically reconfigurable ECC decoder architecture
An energy-efficient virtual channel power-gating mechanism for on-chip networks
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery
Shock immunity enhancement via resonance damping in gyroscopes for automotive applications
Protecting Cyber-Physical Systems via Vendor-Constrained Security Auditing with Reinforcement Learning
PICBench: Benchmarking LLMs for Photonic Integrated Circuits Design
Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs
FPGA Architectures for Approximate Dense SLAM Computing
Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024
Synthesis of Reversible Logic
Scalable liveness verification for communication fabrics
Redundant via insertion in directed self-assembly lithography
Efficient high-performance ASIC implementation of JPEG-LS encoder
Temperature aware task scheduling in MPSoCs
TruLook: A Framework for Configurable GPU Approximation
Compact Non-Volatile Lookup Table Architecture Based on Ferroelectric FET Array Through In-Situ Combinatorial One-Hot Encoding for Reconfigurable Computing
Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems
GenPIM: Generalized processing in-memory to accelerate data intensive applications
Built-in Clock Skew System for On-line Debug and Repair
Hazard driven test generation for SMT processors
Network delay-aware energy management for mobile systems
Maximizing Yield for Approximate Integrated Circuits
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers
Internal power modelling and minimization in CMOS inverters
CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates
SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory Processing
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts
Live together or Die Alone: Block cooperation to extend lifetime of resistive memories
Fault simulation with parallel exact critical path tracing in multiple core environment
Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy
Lightweight authentication for secure automotive networks
Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques
ADD-based Spectral Analysis of Probing Security
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits
Worst-case end-to-end delay analysis of an avionics AFDX network
A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit
CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs
Fast eye diagram analysis for high-speed CMOS circuits
An Efficient Algorithm for Real-Time Symbolic Model Checking
A Resource-efficient Spiking Neural Network Accelerator Supporting Emerging Neural Encoding
Scheduling and optimization of genetic logic circuits on flow-based microfluidic biochips
Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs
RTL synthesis with physical and controller information
Inference of quantized neural networks on heterogeneous all-programmable devices
Trust, but verify: Why and how to establish trust in embedded devices
Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAs
Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM
Exploring the impact of functional test programs re-used for power-aware testing
Net and Pin Distribution for 3D Package Global Routing
Energy Efficient and High Speed On-Chip Ternary Bus
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Thermal management of batteries using a hybrid supercapacitor architecture
A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation
Automatic datapath tile placement and routing
Partitioned mixed-criticality scheduling on multiprocessor platforms
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
Verifying analog oscillator circuits using forward/backward abstraction refinement
Formal verification of analog circuit parameters across variation utilizing SAT
A Constraint Driven Approach to Loop Pipelining and Register Binding
ULSI Interconnect Length Distribution Model Considering Core Utilization
Architectural evaluations on TSV redundancy for reliability enhancement
De-elastisation: from asynchronous dataflows to synchronous circuits
Droplet routing in the synthesis of digital microfluidic biochips
Optimal Fixed Priority Scheduling in Multi-Stage Multi-Resource Distributed Real-Time Systems
Efficient and passive modeling of transmission lines by using differential quadrature method
Compositional Memory Systems for Data Intensive Applications
Powering and communicating with mm-size implants
Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis
A Contribution to Branch Prediction Modeling in WCET Analysi
Power neutral performance scaling for energy harvesting MP-SoCs
2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022
Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDES
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus
Design of Hardware-Friendly Memory Enhanced Neural Networks
Extremely Low-Power Logic
Directed-Binary Search in Logic BIST Diagnostics
Congestion-aware scheduling for NoC-based reconfigurable systems
Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores
Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption
Robust and extensible task implementations of synchronous finite state machines
Improving circuit size upper bounds using SAT-solvers
Embedded tutorial: Addressing critical power management verification issues in low power designs
ATPG power guards: On limiting the test power below threshold
Matlab to C compilation targeting Application Specific Instruction Set Processors
The Road to Better Reliability and Yield Embedded DfM Tools
Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector
Protocol attacks on advanced PUF protocols and countermeasures
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation
Optimal metastability-containing sorting networks
New foundry models - accelerations in transformations of the semiconductor industry
Long range wireless sensing powered by plant-microbial fuel cell
Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding
SoC infrastructures for predictable system integration
Test synthesis for DC test of switched-capacitors circuits
Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience
Design-flow Methodology for Secure Group Anonymous Authentication
A case study for using dynamic partitioning based solution in volume diagnosis
Game-theoretic analysis of decentralized core allocation schemes on many-core systems
A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling
Exploiting data forwarding to reduce the power budget of VLIW embedded processors
Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors
Reduce: A Framework for Reducing the Overheads of Fault-Aware Retraining
Tuning In-Sensor Data Filtering to Reduce Energy Consumption in Wireless Sensor Networks
Hardware Trojan detection for gate-level ICs using signal correlation based clustering
Customization of application specific heterogeneous multi-pipeline processors
Identifying redundant inter-cell margins and its application to reducing routing congestion
A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources
Online monitoring and adaptive routing for aging mitigation in NoCs
Semi-Autonomous Personal Care Robots Interface driven by EEG Signals Digitization
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals
An area optimized reconfigurable encryptor for AES-Rijndael
MSim: A general cycle accurate simulation platform for memcomputing studies
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy
Reliability-Driven Neuromorphic Computing Systems Design
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Few hints towards more sustainable Al
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach
As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation
Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Semiformal verification of temporal properties in automotive hardware dependent software
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing
A concurrent testing method for NoC switches
Optimal sizing of configurable devices to reduce variability in integrated circuits
Detection of illegitimate access to JTAG via statistical learning in chip
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet
A layered formal framework for modeling of cyber-physical systems
Efficient spatial variation modeling via robust dictionary learning
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems
Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading
Derailed: Arbitrarily Controlling DNN Outputs with Targeted Fault Injection Attacks
Device/circuit/architecture co-design of reliable STT-MRAM
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Test pin count reduction for NoC-based Test delivery in multicore SOCs
An architecture for secure software defined radio
Reducing energy consumption in microcontroller-based platforms with low design margin co-processors
A design methodology for fully reconfigurable Delta-Sigma data converters
eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor
LOEDAR: A low cost error detection and recovery scheme for ECC
Run time interpretation for creating custom accelerators
Panel: "will 3D-IC remain a technology of the future... even in the future?"
End-to-end latency analysis of cause-effect chains in an engine management system
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation
System-Level Performance Analysis in SystemC
Multi-story power distribution networks for GPUs
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking
Large signal simulation of integrated inductors on semi-conducting substrates
Software Protection Mechanisms for Dependable Systems
Interactive presentation: A process splitting transformation for Kahn process networks
Fault analysis and simulation of large scale industrial mixed-signal circuits
Availability and interpretability of optimal control for criticality estimation in vehicle active safety
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements
Leakage-power-aware clock period minimization
Impact of process variations on multicore performance symmetry
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits
A Versatile Built-In Self-Test Scheme for Delay Fault Testing
Energy-driven computing: Rethinking the design of energy harvesting systems
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications
Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG
Using Problem Symmetry in Search Based Satisfiability Algorithms
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
Optimizing high speed arithmetic circuits using three-term extraction
Clock domain crossing aware sequential clock gating
Automatically mapping applications to a self-reconfiguring platform
ADAPT-pNC: Mitigating Device Variability and Sensor Noise in Printed Neuromorphic Circuits with SO Adaptive Learnable Filters
tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications
Substrate Parasitic Extraction for RF Integrated Circuits
Panel session - Multicore, will Startups drive innovation?
A Cross-Platform Cache Timing Attack Framework via Deep Learning
Reduction of detected acceptable faults for yield improvement via error-tolerance
System-level scheduling on instruction cell based reconfigurable systems
Exact scheduling strategies based on bipartite graph matching
IEEE 1149.4 Compatible ABMs for Basic RF Measurements
Analyzing GEDF Scheduling for Parallel Real-Time Tasks with Arbitrary Deadlines
Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies
FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs
On applicability of symbolic techniques to larger scheduling problems
Efficient decision ordering techniques for SAT-based test generation
Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation
Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement
Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched Filter
A power-efficient reconfigurable architecture using PCM configuration technology
PRMDL: a machine description language for clustered VLIW architectures
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
Guarantees for runnable entities with heterogeneous real-time requirements
Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure?
Towards binary circuit models that faithfully capture physical solvability
An integrated test generation tool for enhanced coverage of Simulink/Stateflow models
From DFT to systems test - a model based cost optimization tool
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts
Leakage Power Analysis in Different S-Box Masking Protection Schemes
A one-shot configurable-cache tuner for improved energy and performance
Introducing Preemptive Scheduling in Abstract RTOS Models using Result Oriented Modeling
Retargeting of mixed-signal blocks for SoCs
A Methodology for Comparative Analysis of Collaborative Robots for Industry 4.0
Specification Mining Facing Generative AI
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
Modeling and Analysis of Heterogeneous Industrial Networks Architectures
Practical identity recognition using WiFi's Channel State Information
Autonomous UAV-Assisted IoT Systems with Deep Reinforcement Learning Based Data Ferry
Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up
Low cost permanent fault detection using ultra-reduced instruction set co-processors
Quantization-Aware Neural Architecture Search with Hyperparameter Optimization for Industrial Predictive Maintenance Applications
Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation
Double-via-driven standard cell library design
Pueblo: A Modern Pseudo-Boolean SAT Solver
Quo vadis, PUF?: Trends and challenges of emerging physical-disorder based security
A non-intrusive isolation approach for soft cores
Desieve the Attacker: Thwarting IP Theft in Sieve-Valve-based Biochips
Fault-Tolerance by Graceful Degradation for Car Platoons
Specification of Non-Functional Intellectual Property Components
eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection
Adaptive weight compression for memory-efficient neural networks
HLS-l: High-level synthesis of high performance latch-based circuits
Error recovery in digital microfluidics for personalized medicine
Online energy-aware I/O device scheduling for hard real-time systems
Standards for System-Level Design: Practical Reality or Solution in Search of a Question?
Improving the Efficiency of Memory Partitioning by Address Clustering
Ultra-high throughput string matching for Deep Packet Inspection
Panel: First commandment at least, do nothing well!
Accounting for systematic errors in approximate computing
Response Time Analysis of Lazy Round Robin
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system
Tool-support for the analysis of hybrid systems and models
Efficient Software Masking of AES through Instruction Set Extensions
AnytimeNet: Controlling Time-Quality Tradeoffs in Deep Neural Network Architectures
Adaptive delay monitoring for wide voltage-range operation
Heterogeneous Computing Systems for Complex Scientific Discovery Workflows
Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology
Real-time optimization of the battery banks lifetime in Hybrid Residential Electrical Systems
Automatic Selection of Application-Specific Reconfigurable Processor Extensions
SpecHD: Hyperdimensional Computing Framework for FPGA-Based Mass Spectrometry Clustering
Lifetime holes aware register allocation for clustered VLIW processors
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power
AIrchitect: Automating Hardware Architecture and Mapping Optimization
Efficient Symbolic Simulation of Low Level Software
BOiLS: Bayesian Optimisation for Logic Synthesis
Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation
System design challenges for next generation wireless and embedded systems
Mitigating Heterogeneities in Federated Edge Learning with Resource- independence Aggregation
Towards Automatic Design and Verification for Level 3 of the European Train Control System
Automatic construction of models for analytic system-level design space exploration problems
New testing procedure for finding insertion sites of stealthy hardware trojans
Code Selection for Media Processors with SIMD Instructions
A compression-based area-efficient recovery architecture for nonvolatile processors
Exploiting Parallelism with Vertex-Clustering in Processing-In-Memory-based GCN Accelerators
Novel circuit topology synthesis method using circuit feature mining and symbolic comparison
Program affinity performance models for performance and utilization
Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node
Architectures for efficient face authentication in embedded systems
Synthesizing Synchronous Elastic Flow Networks
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations
Capturing intrinsic parameter fluctuations using the PSP compact model
A Pluggable Vector Unit for RISC-V Vector Extension
An efficient mask optimization method based on homotopy continuation technique
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Multiple-fault diagnosis based on single-fault activation and single-output observation
SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel
A Generic Standard Cell Design Methodology for Differential Circuit Styles
Evaluation of runtime task mapping heuristics with rSesame - a case study
Towards a Qualifiable OpenMP Framework for Embedded Systems
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
HTnet: Transfer Learning for Golden Chip-Free Hardware Trojan Detection
Approximation Algorithm for Noisy Quantum Circuit Simulation
Test generation for clock-domain crossing faults in integrated circuits
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits
Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis