yusuke1997/dblp-id-title huggingface dataset:
Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees
2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France
Partitioned cache architectures for reduced NBTI-induced aging
TSV redundancy: Architecture and design issues in 3D IC
Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies
Low Cost Analog Testing of RF Signal Paths
Instruction trace compression for rapid instruction cache simulation
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision
On the cooperative automatic lane change: Speed synchronization and automatic "courtesy"
Efficient finite field digital-serial multiplier architecture for cryptography applications
Dynamic Tool Integration in Heterogeneous Computer Networks
Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems
WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal Effect
A wear-leveling-aware counter mode for data encryption in non-volatile memories
An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits
Accelerating complex brain-model simulations on GPU platforms
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors
Tunnel FET based refresh-free-DRAM
Analytical design optimization of sub-ranging ADC based on stochastic comparator
ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs
Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization
Designing Self-Testable Multi-Chip Modules
Reducing Test Application Time Through Test Data Mutation Encoding
Study of workload impact on BTI HCI induced aging of digital circuits
Quality configurable reduce-and-rank for energy efficient approximate computing
A scalable lane detection algorithm on COTSs with OpenCL
Co-design of signal, power, and thermal distribution networks for 3D ICs
Industrial IP Integration Flows based on IP-XACT Standards
Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators
Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process
Configurable links for runtime adaptive on-chip communication
Quasar, a high-level programming language and development environment for designing smart vision systems on embedded platforms
Implications of Technology Trends on System Dependability
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations
The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Congestion-Aware Logic Synthesis
Microprocessor power analysis by labeled simulation
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing
Cocktail: Chunk-Adaptive Mixed-Precision Quantization for Long-Context LLM Inference
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation
A high-speed design methodology for inductive coupling links in 3D-ICs
FlexRay switch scheduling - A networking concept for electric vehicles
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions
Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice
Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application
Verifying real-time properties of MOS-transistor circuits
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation
EasiMask-Towards Efficient, Automated, and Secure Implementation of Masking in Hardware
Multi-Partner Project: A Deep Learning Platform Targeting Embedded Hardware for Edge-AI Applications (NEUROKIT2E)
A deep learning methodology to proliferate golden signoff timing
Development and industrialisation
Optimal Code Placement of Embedded Software for Instruction Caches
GoldMine: Automatic assertion generation using data mining and static analysis
ESA Athena WFI Onboard Electronics - Distributed Control and Data Processing
D2Cyber: A design automation tool for dependable cybercars
SCAM: Secured content addressable memory based on homomorphic encryption
Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project
A Top-Down Microsystems Design Methodology and Associated Challenges
Gate delay fault test generation for non-scan circuits
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem
Conservative open-page policy for mixed time-criticality memory controllers
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices
Detecting/preventing information leakage on the memory bus due to malicious hardware
RETHINK big: European roadmap for hardware anc networking optimizations for big data
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
Design flow and run-time management for compressed FPGA configurations
An Effective BIST Architecture for Fast Multiplier Cores
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications
AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories
An accurate interconnect thermal model using equivalent transmission line circuit
LLM-Guided Formal Verification Coupled with Mutation Testing
Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions
A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design
VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting
Image progressive acquisition for hardware systems
Susceptibility of analog cells to substrate interference
Built-In Self-Test with an Alternating Output
Sequential logic synthesis using symbolic bi-decomposition
A hybrid packet-circuit switched on-chip network based on SDM
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces
Symbolic quick error detection using symbolic initial state for pre-silicon verification
Hydra: A near hybrid memory accelerator for CNN inference
Towards Approximate Computing for Achieving Energy vs. Accuracy Trade-offs
Emulation-based robustness assessment for automotive smart-power ICs
Runtime Energy Minimization of Distributed Many-Core Systems using Transfer Learning
Gait analysis for fall prediction using hierarchical textile-based capacitive sensor arrays
Using Formal Verification Methods for Optimization of Circuits Under External Constraints
Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics
Novel Physical Unclonable Function with process and environmental variations
A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes
The vector fixed point unit of the synergistic processor element of the cell architecture processor
One Fault is All it Needs: Breaking Higher-Order Masking with Persistent Fault Analysis
Design of oscillation-based test structures for active RC filters
A Discrete-Time Battery Model for High-Level Power Estimation
Industrial Evaluation of DRAM Tests
LaRED: Efficient IR Drop Predictor with Layout-Preserving Rebuilder-Encoder-Decoder Architecture
Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations
Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache
HyMM: A Hybrid Sparse-Dense Matrix Multiplication Accelerator for GCNs
HIPE: HMC instruction predication extension applied on database processing
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Temporal memoization for energy-efficient timing error recovery in GPGPUs
Modeling Event Stream Hierarchies with Hierarchical Event Models
Predicting Coupled Noise in RC Circuits
Hardware efficient architectures for Eigenvalue computation
HiQ-ProjectQ: Towards user-friendly and high-performance quantum computing on GPUs
Run-time power-gating in caches of GPUs for leakage energy savings
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures
Design of a real-time optimized emulation method
Operating System Controlled Processor-Memory Bus Encryption
3D integration for power-efficient computing
Unleashing the Power of T1-Cells in SFQ Arithmetic Circuits
Exploiting structure in an AIG based QBF solver
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling
Exploiting area/delay tradeoffs in high-level synthesis
Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks
Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics
Increasing Cellular Network Energy Efficiency for Railway Corridors
SCALES: Boost Binary Neural Network for Image Super-Resolution with Efficient Scalings
A future of customizable processors: are we there yet?
Adaptive chip-package thermal analysis for synthesis and design
BASTION: Board and SoC test instrumentation for ageing and no failure found
Near-threshold voltage design in nanoscale CMOS
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
Supporting runtime reconfigurable VLIWs cores through dynamic binary translation
Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0)
On the Design and Verification Methodology of the Look-Aside Interface
UMTS MPSoC design evaluation using a system level design framework
Approximate Logic Synthesis by Symmetrization
Evaluation of Error-Resilience for Reliable Compression of Test Data
Analogue Fault Modelling and Simulation for Supply Current Monitoring
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks
Breaking Instance-Independent Symmetries in Exact Graph Coloring
COMET: A Cross-Layer Optimized Optical Phase-Change Main Memory Architecture
Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models
Feature selection for alternate test using wrappers: application to an RF LNA case study
A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies
A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique
HygHD: Hyperdimensional Hypergraph Learning
Unbounded safety verification for hardware using software analyzers
Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints
Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips
Transistor-Specific Delay Modeling for SSTA
A non-intrusive, operating system independent spinlock profiler for embedded multicore systems
Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems
Computation and communication challenges to deploy robots in assisted living environments
Noise-sensitive feedback loop identification in linear time-varying analog circuits
Efficient program tracing and monitoring through power consumption - with a little help from the compiler
Adaptive DRAM Cache Division for Computational Solid-state Drives
Design methods for security and trust
Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using Coq
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array
Evaluating Assertion Set Completeness to Expose Hardware Trojans and Verification Blindspots
Architectural leakage-aware management of partitioned scratchpad memories
BIMAX: A Bitwise In-Memory Accelerator Using 6T-SRAM Structure
An inside job: Remote power analysis attacks on FPGAs
LookNN: Neural network with no multiplication
New Perspectives and Opportunities From the Wild West of Microelectronic Biochips
Robust and Low Complexity Rate Control for Solar Powered Sensors
RankMap: Priority-Aware Multi-DNN Manager for Heterogeneous Embedded Devices
Split Additive Manufacturing for Printed Neuromorphic Circuits
Voltage-controlled MRAM for working memory: Perspectives and challenges
Parallel Gröbner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification
Facilitating timing debug by logic path correspondence
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis
Hardware/Software Partitioning of Operating Systems
An efficient temperature-gradient based burn-in technique for 3D stacked ICs
Energy-adaptive scheduling of imprecise computation tasks for QoS optimization in real-Time MPSoC systems
Design of a low-energy data processing architecture for WSN nodes
A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors
Co-optimization of memory BIST grouping, test scheduling, and logic placement
Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators
HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope
Nanometer Design: What are the Requirements for Manufacturing Test?
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs
Testing microfluidic Fully Programmable Valve Arrays (FPVAs)
Accuracy and Compactness in Decision Diagrams for Quantum Computation
DEAR-PIM: Processing-in-Memory Architecture with Disaggregated Execution of All-bank Requests
Prediction of interconnect delay in logic synthesis
Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures
Systematic design of a programmable low-noise CMOS neural interface for cell activity recording
Metric Temporal Logic with Resettable Skewed Clocks
Buddy ECC: Making Cache Mostly Clean in CXL-Based Memory Systems for Enhanced Error Correction at Low Cost
An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimation
Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault
Enrichment of limited training sets in machine-learning-based analog/RF test
A Hybrid Approach to Reverse Engineering on Combinational Circuits
A new method for automated generation of compensation networks - The EDA Designer Finger
Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs
Detection of asymmetric aging-critical voltage conditions in analog power-down mode
Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation
Improving yield and reliability of chip multiprocessors
TPP: Accelerate Application Launch via Two-Phase Prefetching on Smartphone
Memory-aware NoC Exploration and Design
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications
High-level synthesis of analog sensor interface front-ends
RICH: Heterogeneous Computing for Real-Time Intelligent Control
High performance Time-of-Flight and color sensor fusion with image-guided depth super resolution
OPTIC: A Practical Quantum Binary Classifier for Near-Term Quantum Computers
An MILP-based aging-aware routing algorithm for NoCs
Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation
Towards Deep Learning-based Occupancy Detection Via WiFi Sensing in Unconstrained Environments
Speeding up model checking by exploiting explicit and hidden verification constraints
Smart sensor system application: an integrated compass
Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling
Reconfigurable system-on-chip data processing units for space imaging instruments
Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement
HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling
Improving Technology Mapping for And-Inverter-Cones
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement
Hybrid Sensing Approach For Coded Modulation Time-of-Flight Cameras
Power optimization in heterogenous datapaths
Managing the SoC design challenge with "Soft" hardware
Design space exploration for 3D-stacked DRAMs
High Speed and Highly Testable Parallel Two-Rail Code Checker
Circuit and Platform Design Challenges in Technologies beyond 90nm
Detecting Undetectable Controller Faults Using Power Analysis
On the development of a new countermeasure based on a laser attack RTL fault model
A high-performance dense block matching solution for automotive 6D-vision
Determining the Technical Complexity of Integrated Circuits
Management of complex automotive communication networks
Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times
Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors
Analysis and optimization of NBTI induced clock skew in gated clock trees
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression
Efficient Compilation and Execution of JVM-Based Data Processing Frameworks on Heterogeneous Co-Processors
Towards Generic and Scalable Word-Length Optimization
ApproxANN: an approximate computing framework for artificial neural network
Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh
Formal Refinement and Model Checking of an Echo Cancellation Unit
Design method for multiplier-less two-variable numeric function approximation
Testing in Nanometer Technologies
Universal Strong Encryption FPGA Core Implementation
Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications
LVS check for photonic integrated circuits: curvilinear feature extraction and validation
Macromodeling of Digital I/O Ports for System EMC Assessment
A decade of reconfigurable computing: a visionary retrospective
A New Task Model for Streaming Applications and Its Schedulability Analysis
A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching
Reliability-Centric High-Level Synthesis
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method
Constraint-Driven System Partitioning
Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows
Event Model Interfaces for Heterogeneous System Analysis
Testing TAPed cores and wrapped cores with the same test access mechanism
Layout Driven Decomposition with Congestion Consideration
Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes
A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system
Systematic application of ISO 26262 on a SEooC: Support by applying a systematic reuse approach
A Smart Fault Detection Scheme for Reliable Image Processing Applications
PoisonHD: Poison Attack on Brain-Inspired Hyperdimensional Computing
Refinement of Mixed-Signal Systems with SystemC
A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications
Variation-aware leakage power model extraction for system-level hierarchical power analysis
An ultra low-power TLB design
Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding
Simultaneous FU and Register Binding Based on Network Flow Method
A WCET-aware parallel programming model for predictability enhanced multi-core architectures
Late Breaking Results: Hyperdimensional Regression with Fine-Grained and Scalable Confidence-Based Learning
A smooth refinement flow for co-designing HW and SW threads
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications
May-happen-in-parallel analysis of ESL models using UPPAAL model checking
PTierDB: Building Better Read-Write Cost Balanced Key-Value Stores for Small Data on SSD
Customisable EPIC Processor: Architecture and Tools
Exploiting Boosting in Hyperdimensional Computing for Enhanced Reliability in Healthcare
Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation
Embedded Automotive System Development Process
On effective TSV repair for 3D-stacked ICs
The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512)
A re-entrant flowshop heuristic for online scheduling of the paper path in a large scale printer
Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches
Simultaneous budget and buffer size computation for throughput-constrained task graphs
Online analysis of debug trace data for embedded systems
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Generation of compact test sets with high defect coverage
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing
Virtual platforms: Breaking new grounds
A GPU-enabled Level Set Method for Mask Optimization
A self-adaptive system architecture to address transistor aging
Design of a time-predictable multicore processor: The T-CREST project
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor
Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design
Empowering Quantum Error Traceability with MoE for Automatic Calibration
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology
PARLAK: Parametrized Lock Cache Generator