yusuke1997/dblp-id-title huggingface dataset:
Generation and Relation of Quaternary and Binary Linearly Independent Transforms
A Study on Essentially Minimal Clones
An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator
Spectral Response of Ternary Logic Netlists
Verification of Multi-Valued Logic Networks
An Inexact Reasoning Technique Using Linguistic Rule Matrix Transformations
A Weak Propositional Calculus for Signal Processing with Thresholds
Optimization of Fuzzy Logic Implementation
Modal Operators on Non-commutative Residuated Lattices
L-fuzzy relations on residuated lattices
Fast Computation of the Discrete Pascal Transform
Fault Detection in Parity Preserving Reversible Circuits
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations
Multi-valued Decision Diagrams for k-Out-of-n Three-State Systems
24th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1994, Boston, Massachusetts, USA, May 25-27, 1994, Proceedings
Determining Minimized Galois Field Expressions for Ternary Functions
Many-Valuedness and Uncertainty
Minimization of Incompletely Specified Regular Ternary Logic Functions and its Application to Fuzzy Switching Functions
A Characterization of Kleenean Functions
Probabilistic Logic Programming with Well-Founded Negation
Regular Encodings from Max-CSP into Partial Max-SAT
On Natural Eight-Valued Reasoning
Cut-Free Systems for Restricted Bi-Intuitionistic Logic and Its Connexive Extension
Digital calculus: ss
Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images
On Fixed Points and Cycles in the Reed Muller Domain
Foulis m-semilattices and their modules
Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits
Bilattices in Logic Prograrnming
Non-deterministic Matrices for Semi-canonical Deduction Systems
Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits
Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers
An Efficient Heuristic for Linear Decomposition of Index Generation Functions
Generalized Discrete Hartley Transforms
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme
Some New Results for Multiple-Valued Genetic Algorithms
Remarks on Particular Properties of Ternary Bent Functions and Construction Algorithms
A Low-Voltage and Low-Power CMOS Temperature Sensor Circuit with Digital Output for Wireless Healthcare Monitoring System
Nomura Parameters for S-Threshold Functions
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic
A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding
Survey of Stochastic Computation on Factor Graphs
On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic
Concurrent Checking and Unidirectional Errors in Multiple-Valued Circuits
On Urquhart's C Logic
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding
43rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, May 22-24, 2013
A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs
Building Automated Theorem Provers for Infinitely-Valued Logics with Satisfiability Modulo Theory Solvers
Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs
Decimal Addition and Subtraction Units Using the p -Valued Decimal Signed-Digit Number Representation
Functional Completeness and Weak Completeness in Set Logic
The modular complexity of a tree structured higher radix multiplier
Representation of Uncertain Belief Using Interval Probability
Relational Characterization of Multilevel Threshold Functions
Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie
Finite Model Property for Modal Ideal Paraconsistent Four-Valued Logic
Alleviating Memory Bottlenecks Using Multi-Level Memory
Efficiency of Multi-Valued Encoding in SAT-based ATPG
Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs
A Fuzzy Logic Function Generator (FLUG) Implemented with Current Mode CMOS Circuits
On quotient algebras of normal eo-algebras by congruences
Multi-Valued DNA-Based Electronic Nanodevices
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions
An Application of Multiple-Valued Logic to Test Case Generation for Software System Functional Testing
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions
Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits
Multi-Valued Quantum Logic
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits
Factorization of Multi-Valued Logic Functions
Is Your Chip Leaking Secrets via RF Signals?
Automated Finding of the Willis Ring in MR Angiography Images Using Fuzzy Knowledge Base
Implementing a Multiple-Valued Decision Diagram Package
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI
Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control
Evolutionary Multi-Level Network Synthesis in Given Design Style
Logic Design Using Memristors: An Emerging Technology
A Testable Realization for Decimal Multipliers
The FPGA Challenge
Representations of Elementary Functions Using Binary Moment Diagrams
Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor
The Maiorana Method to Generate Multiple-Valued Bent Functions Revisited
Residue Arithmetic Based Multiple-Valued VLSI Image Processor
Use of an infinite-valued propositional calculus in a document retrieval system
Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs
Grading Evaluation Method in Character Drawing Study Support System
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer
A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic
Generalized Extended t-Norms as t-Norms of Type 2
Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware
A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction
Training Fuzzy Logic Based Software Components for Reuse
Recent Developments in DNA-Computing
ECG Signal Processing Using Fuzzy Classification for Sudden Cardiac Death Prediction
Maximally Asymmetric Multiple-Valued Functions
Multi-valued Problem Solvers
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control
Properties and Applications of Unified Complex Hadamard Transforms
Improving the Characterization of p-Valued Threshold Functions
Countable Intervals of Partial Clones
Optimization of Multi-Valued Multi-Level Networks
Design of Haar Wavelet Transforms and Haar Spectral Transform Decision Diagrams for Multiple-Valued Functions
A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block
A new aspect of Some Post algebras
Triple Representation Theorem for Homogeneous Effect Algebras
Multiple-Valued Logic Minimization using Universal Literals and Cost Tables
Amoeba-Inspired Electronic Solution-Searching System and Its Application to Finding Walking Maneuver of a Multi-legged Robot
System Probability Distribution Modeling Using MDDs
A Random Forest Using a Multi-valued Decision Diagram on an FPGA
Memory Circuits for Multiple-Valued Logic Voltage Signals
DT - An Automated Theorem Prover for Multiple-Valued First-Order Predicate Logics
Generating the Variety of SMV-Algebras
Minimization of Functions with Multiple-Valued Outputs: Theory and Applications
The Abnormality Predicate
Evaluation of Stochastic Cascaded IIR Filters
Wire-Free Computing Circuits Using Optical Wave-Casting
55th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2025, Montreal, QC, Canada, June 5-6, 2025
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network
Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS Realization
Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits
Fault Analysis on Two-Level (K+1)-Valued Logic Circuits
Clausal Form Transformation in MaxSAT
A Note on Intervals of Słupecki Partial Clones
Properties of Multiple-Valued Partition Functions
Fredkin-Enabled Transformation-Based Reversible Logic Synthesis
Clarifying the Axioms of Kleene Algebra based on the Method of Indeterminate Coefficients
Hardware to Compute Walsh Coefficients
An Energy-Efficient Quaternary Serial Adder for Nanoelectronics
Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques
Deep Learning for Autonomous Vehicles
Some Basic Ternary Operations Using Toffoli Gates Along with the Cost of Implementation
Four New Construction Methods on Residuated Monoids
Completeness problems for switching circuits constructed from delayed gates
An Algorithm for Constraint Satisfaction Problem
32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA
Experiments on FPRM Expressions for Partially Symmetric Logic Functions
A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms
Spectral Transforms of Mixed-radix MVL Functions
Autocorrelation Techniques for Multi-Bit Decoder PLAs
A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes
On the Synthesis of 4-Valued Current Mode CMOS Circuits
A Complete Tableau Calculus for Signed MaxSAT
Representation of Incompletely Specified Binary and Multiple-Valued Logic Functions by Compact Decision Diagrams
Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals
26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings
Ultrasonic Diagnosis for Bone Fracture Healing Process
Toward the Age of Beyond-Binary Electronics and Systems
Demonstration of ternary devices and circuits using dual channel graphene barristors
MDGs Reduction Technique Based on the HOL Theorem Prover
A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions
Automatic Uniform Quantum State Preparation Using Decision Diagrams
Synthesis of Reversible Circuits Based on Products of Exclusive OR Sums
On the Nonexistence of Minimal Strong Partial Clones
On the Detectability of Hardware Trojans Embedded in Parallel Multipliers
New MVL-PLA Structures Based on Current-Mode CMOS Technology
Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation
A Note on Finite Clones Containing All Permutations
Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions
Keynote II: Digital Annealer: A Stochastic Search for Global Optimum
Note on Construction of Probabilities on Many-Valued Events via Schauder Bases and Inverse Limits
On Decision Making under Interval Uncertainty: A New Justification of Hurwicz Optimism-Pessimism Approach and its Use in Group Decision Making
Weak Uninorm Based Logic and Its Filter Theory
Fast Interface with Ensemble Ternary Neural Network
Generating Hard Instances for MaxSAT
On the Minimization of Multiple-Valued Input Binary-Valued Output Functions
The Role of Super-Fast Transforms in Speeding Up Quantum Computations
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults
Composing Submonads
Energy-Efficient Automated Seizure Detection in Wearable/Implantable BCIs: Motivations, Methods, and Example Implementation
Synthesis of Balanced Ternary Reversible Logic Circuit
53rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2023, Matsue, Japan, May 22-24, 2023
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks
A Graded Inference Approach Based on Infinite-Valued Lukasiewicz Semantics
Design of Multiwave Computing Circuits Based on a Modle of Integrated Opto-Electronic Devices
Properties and Fast Algorithms for Ternary Walsh Transform
Hereditary rigidity, separation and density: In memory of Professor I.G. Rosenberg
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams
Algebras for Hazard Detection
Hereditary Clones of Mulitple Valued Logic Algebra
Approximating Propositional Calculi by Finite-Valued Logics
Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic
Maximal and Minimal Closed Classes in Multiple-Valued Logic
A Radix-4 Chrestenson Gate for Optical Quantum Computation
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms
Characterization Theorem of Lattice Implication Algebra
Decomposition of multiple-valued logic functions
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©
Message from the Co-Chairs
Improving Tableau Deductions in Multiple-Valued Logics
Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits
Voltage Comparator Circuits for Multiple-Valued CMOS Logic
A Method of Test Pattern Generation for Multiple-Valued PLA's
The Rough Powerset Monad
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation
On the Contributions to Multiple-Valued Logic by Prof. Kenneth C. Smith
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem
The Complexity of Lukasiewicz Logic
Mapping Many-Valued CNF Formulas to Boolean CNF Formulas
Some Types of Filters in Hoops
Advanced Circuit Technology to Realize Post Giga-bit DRAM
Linear Decompositions for Multi-Valued Input Classification Functions
An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope
Multiple Valued Logic: Current-Mode CMOS Circuits
From Pure to Approximate Logic
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions
Dynamic Reliability Indices for k-out-of-n Multi-State System
Model Checking with Multi-Valued Temporal Logics
Multiple-Valued Logic Interpretations of Analogical, Reverse Analogical, and Paralogical Proportions
Fault secure multiple-valued logic networks
Novel Quantized Transform for Ternary Systems
Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic
Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978
CML Current Mode Full Adders for 2.5-V Power Supply
Polynomial Expansions over GF(3) based on Fastest Transformation
On Axiomatization of Conditional Entropy of Functions Between Finite Sets
QuCode: A Novel Conceptual Description of Quantum Algorithms
Constant Geometry Algorithms for Galois Field Expressions and Their Implementation on GPUs
A Transfer Function Model for Ternary Switching Logic Circuits
Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics
Upper and Lower Bounds on the Number of Fuzzy/c Switching Functions
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes
REBEL-6: A 32-trit balanced ternary instruction set architecture with R2R compiler pipeline for C
Approach to Recommend Tourist Spots for Foreigners Visiting Himeji City
30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
Classes of Fastest Quaternary Linearly Independent Transformations
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-Valued Circuits
Determination of the fittest number of truth-values and canonical forms of logical functions for a many-valued axiom set by a computer
A Review of Multiple-Valued Memory Technology
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI
The Euler Characteristic of a Formula in Godel Logic
Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits
Planar Multiple-Valued Decision Diagrams
Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases
23rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1993, Sacramento, California, USA, May 24-27, 1993, Proceedings
Membership Functions in Automatic Harmonization System
Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS
29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings
Multi-Valued Logic: Wave of the Future or an Historical Anachronism
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
Fundamental Properties of Extended Kleene-Stone Logic Functions
Radix Converters: Complexity and Implementation by LUT Cascades
EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified Functions
Some Results on the Decision for Sheffer Functions in Partial K-Valued Logic(II)
Learning Multiple-Valued Logic Networks Based on Back Propagation
Normal Forms and Decompositions of Monotone Ternary Functions
Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm
Numeric Function Generators Using Piecewise Arithmetic Expressions
A tri-state logic family
Partial Hyperclones on a Finite Set
Transformations between Signed and Classical Clause Logic
Endoprimal Monoids and Witness Lemma in Clone Theory
A Conjunctive Canonical Expansion of Multiple-Valued Functions
Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation
A 4-Digit CMOS Quaternary to Analog Converter with Current Switch and Neuron MOS Down Literal Circuit
Standard Completeness for Uninorm-Based Logics
High-Speed Digital Circuits for a Josephson Computer
Some Observations on Minimal Clones
Phase & Power in Genomic Harmonic Analysis
Mapping Decision Diagrams for Multiple-Valued Logic Functions into Threshold Logic Networks
On 2-valued Majority Functions with their Relation to Minimal Clones
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time
Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors
Dramatically Low-Transistor-Count High-Speed Ternary Adders
Application of Fail-Safe Multiple-Valued Logic to Control of Power Press
Finite Algebraic Models for Residuated Logic
Integration of Information in Four-Valued Logics under Non-Uniform Assumptions
Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic
Multiple-Valued Hyperstructures
22nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1992, Sendai, Japan, May 27-29, 1992, Proceedings
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits
A CMOS Current-Mode High Speed Fuzzy Logic Microprocessor for a Real-Time Expert System
A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit
A proposed interpretation of lukasiewicz's four-valued system of modal logic
A Logical Method to Predict Outcomes After Coronary Artery Bypass Grafting
Waveform Shaping Transmitter Combining Digital and Analog Circuits for Multi - Valued Signaling
Gigantic Pairs of Minimal Clones
Quantum p-Valued Toffoli and Deutsch Gates with Conjunctive or Disjunctive Mixed Polarity Control
Application of Covering Codes for Reduced Representations of Logic Functions
Cut-Down Operations on Bilattices
Delta-sigma modulated noise-shaping bitstreams for multilayer perceptron
A Tableau Calculus for Signed Maximum Satisfiability
Optimized Density Matrix Representations : Improving the Basis for Noise-Aware Quantum Circuit Design Tools
List-Homomorphism Problems on Graphs and Arc Consistency
Fault Tolerant Computing Paradigm for Random Molecular Phenomena: Hopfield Gates and Logic Networks
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission
Approximate Synthesis for Classification Functions
Linear Transformations for Iterative Reduction of Variables
Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based Logic
Entropic Minimization of Multiple-Valued Functions
The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons
Design of High Performance Quaternary Adders
Simple Characterizations of Perfect Residuated Lattices
Multiple-Valued Time-Based Architecture for Serial Communication Links
Algebra of Transient States of Postan Signals
An extension of ternary majority function and its application to evolvable system
On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions
Direct Cover MVL Minimization with Cost-Tables
The Roots of the NOT Gate
A Weight Ternary Ensemble Vision Transformer Toward Memory Size Reduction
Communication Trade Offs in Intermediate Qudit Circuits
Optimization of Current-Mode MVD-ORNS Arithmetic Circuits
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
On Isomorphisms between the Lattice of Tolerance Relations and Lattices of Clusterings
Ternary Parametron Based on Subharmonic Oscillation of Order Three by Forcing
Optimal Quantum Circuits of Three Qubits
Efficient DFA-Resistant AES Hardware Based on Concurrent Fault Detection Scheme
On the compactification and enumeration of distinct fuzzy switching functions
A Josephson Ternary Memory Circuit
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture
On ternary symmetric bent functions
Self-extensional Paradefinite Four-valued Modal Logic Compatible with Standard Modal Logic
Probabilistic computing utilizing stochastic spintronic devices
Quantum Finite State Machines as Sequential Quantum Circuits
Centralising groups of semiprojections and near unanimity operations
A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter
A General-Purpose Inference Processor for Real-Time Intelligent Controllers Using Systolic Arrays
Contribution to the Study of Multiple-Valued Bent Functions
Design and implementation of a non-binary code for byte-organized memory with binary and quaternary logics
Decomposition of Multiple-Valued Functions
Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication
Identification of Linear Ternary Logic Functions and Its Algorithms
First-Order Logic Based on Set Approximation: A Partial Three-Valued Approach
Invitation to Clone Theory with Partial Clones and Hyperclones
Efficient Computation of Logic Derivatives Using Multi-valued Decision Diagrams
Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors
Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule
Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits
An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction