yusuke1997/dblp-id-title huggingface dataset:
Design and management of 3D-stacked NUCA cache for chip multiprocessors
A Unified Model of Power Sources for the Simulation of Electrical Energy Systems
Contradictory antecedent debugging in bounded model checking
Circuit architecture for low-power race-free programmable logic arrays
An error simulation based approach to measure error coverage of formal properties
Combating NBTI-induced aging in data caches
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization
ADMM-based Weight Pruning for Real-Time Deep Learning Acceleration on Mobile Devices
Carbon Efficiency of Natural Organic Honey-Memristor Based Neuromorphic Computing
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors
Overscaling-friendly timing speculation architectures
Mixing ATPG and property checking for testing HW/SW interfaces
InMnAs magnetoresistive spin-diode logic
Robust window-based multi-node technology-independent logic minimization
VarDroid: Online Variability Emulation in Android/Linux Platforms
Two dimensional reordering of functional test data for compression by ATE
Polynomial coefficient based DC testing of non-linear analog circuits
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs
Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage
Breaking Behavioral IPs Design Space Lock
Energy-optimal synchronization primitives for single-chip multi-processors
Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit
Terahertz sensing technology
Genetic synthesis: performance-driven logic synthesis using genetic evolution
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011
An efficient linearity test for on-chip high speed ADC and DAC using loop-back
Design of a package for a high-speed processor made with yield-limited technology
Switchbox routing with movable terminals
Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature
A Hierarchal Approach for Power Reduction in VLSI Chips
Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture
An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning
Routing in a rectangle with k-ary overlap
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005
GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking
A logic synthesis system based on global dynamic extraction and flexible cost
A signed hypergraph model of constrained via minimization
A path based modeling approach for dynamic power estimation
Microelectronics Security in CHIPS Era
A design kit for a fully working shared memory multiprocessor on FPGA
A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH Technique
Rarity based guided state space search
Stochastically Pruning Large Language Models Using Sparsity Regularization and Compressive Sensing
On-chip delay measurement for silicon debug
Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design
Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization
Increasing the energy efficiency of pipelined circuits via slack redistribution
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies
Linking fabrication and parametric testing to VLSI design courses
A distributed controller for system level integration
Supporting system-level power exploration for DSP applications
Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate
WeDBless: weighted deflection bufferless router for mesh NoCs
A linear programming formulation for security-aware gate sizing
Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry
A Processing-In-Memory Implementation of SHA-3 Using a Voltage-Gated Spin Hall-Effect Driven MTJ-based Crossbar
Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging
EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads
Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs
Fine-grain leakage optimization in SRAM based FPGAs
Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems
Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques
High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]
Defect-Tolerant Mapping of CMOL Circuits with Delay Optimization
MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D
Session details: Session 3A: VLSI Design + VLSI Circuits and Power Aware Design 1
Efficient minimization algorithms for fixed polarity AND/XOR canonical networks
beta-Driven Threshold Elements
LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations
A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs
Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload
DAG based library-free technology mapping
Computing with field-coupled nanomagnets
Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories
Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuse
Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing
Regression-based RTL power models for controllers
A formal approach for high level synthesis of linear analog systems
High-speed systolic architectures for finite field inversion and division
Shuttle mask floorplanning with modified alpha-restricted grid
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits
Session details: Session 1A: Hardware Security
Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications
Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate Circuits
Highly Efficient Load-Balanced Dataflow for SpGEMMs on Systolic Arrays
Efficiently Searching the Optimal Design Space
Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion
Transparent repeaters
Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects
Quasi-self-powered Infrastructural Internet of Things: The Mackinac Bridge Case Study
A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors
Timed Supersetting and the Synthesis of Telescopic Units
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data
Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems
Improvement of power distribution network using correlation-based regression analysis
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs
Securing the Systems of the Future - Techniques for a Shifting Attack Space
Crosstalk analysis in nanometer technologies
Protected ECC Still Leaks: A Novel Differential-Bit Side-channel Power Attack on ECDH and Countermeasures
Design approaches for hybrid CMOS/molecular memory based on experimental device data
Accuracy management for mixed-mode digital VLSI simulation
Quadtree interconnection network layout
A robust, fast pulsed flip-flop design
Double DIP: Re-Evaluating Security of Logic Encryption Algorithms
A novel ultra-fast heuristic for VLSI CAD steiner trees
Performance-constrained template-driven retargeting for analog and RF layouts
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables
A Self Timed Asynchronous Router for an Heterogeneous Parallel Machine
Improving the testability and reliability of sequential circuits with invariant logic
EDA for extreme scale systems: design abstractions, metrics, and benchmarks
Compressor trees for decimal partial product reduction
DELCA: DVFS Efficient Low Cost Multicore Architecture
Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation
Power density minimization for highly-associative caches in embedded processors
Analog vs. Digital In-Sensor Computing: A Tale of Two Paradigms
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Investigation and Optimization of Pin Multiplexing in High-Level Synthesis
ALPS: A Peak Power Estimation Tool for Sequential Circuits
Microarchitecture Evaluation Framework for Transient Execution Attack Vulnerability: Metrics, Fuzzing, and Sensitivity Analysis
An Incremental Floorplanner
Interconnected rings and oscillators as gigahertz clock distribution nets
Litho-NeuralODE: Improving Hotspot Detection Accuracy with Advanced Data Augmentation and Neural Ordinary Differential Equations
Aging effects of leakage optimizations for caches
Accelerating RRT Motion Planning Using TCAM
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks
Logic-level analysis of high-level faults
Domain Isolation in FPGA-Accelerated Cloud and Data Center Applications
A binary--search switched--current sensing scheme for 4-state MRAM
iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations
A fast and efficient heuristic ESOP minimization algorithm
An ADD-based algorithm for shortest path back-tracing of large graphs
A novel charge recycler for TFT-LCD source driver IC
Balanced Factorization and Rewriting Algorithms for Synthesizing Single Flux Quantum Logic Circuits
A low-power TCAM design using mask-aware match-line (MAML) technique
PIM lite: a multithreaded processor-in-memory prototype
Synthesis of irregular combinational functions with large don't care sets
Rotary traveling wave oscillator frequency division at nanoscale technologies
Multi-segment GF (2 m ) multiplication and its application to elliptic curve cryptography
MTJ Magnetization Switching Mechanisms for IoT Applications
Application of fast SOCP based statistical sizing in the microprocessor design flow
A hardware/software codesign approach for programmable IO devices
A Novel 1.5-V Cmos Mixer
Area efficient binary tree layout
Multicast routing with dynamic packet fragmentation
Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019
A portable high-frequency digitally controlled oscillator (DCO)
Optimum Steiner tree generation
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning
Solid state optical quantum memories
NMOS Energy Recovery Logic
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin
An ILP based approach to address code generation for digital signal processors
How does partitioning matter for 3D floorplanning?
New approach to CMOS current reference with very low temperature coefficient
Delay and peak power minimization for on-chip buses using temporal redundancy
A Robust C-element Design with Enhanced Metastability Performance
Skew spreading for peak current reduction
Mathematical model for routability analysis of FPGAs
Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect
Evaluation of using active circuitry for substrate noise suppression
Reducing bus transition activity by limited weight coding with codeword slimming
DCC: Double Capacity Cache Architecture for Narrow-Width Values
Electronic devices, structures and transport in carbon based materials: molecular electronics and quantum computing
Gate matrix layout based on hierarchical net-list representations
DroneBandit: Multi-armed contextual bandits for collaborative edge-to-cloud inference in resource-constrained nanodrones
PACAC: PYNQ Accelerated Cardiac Arrhythmia Classifier with secure transmission- A Deep Learning based Approach
A novel design framework for the design of reconfigurable systems based on NoCs
Using EM Side-Channels Near a Bluetooth Server Implementation to Monitor Bit-Level Leakages in BLE Communication Channels
SAFE-SiP: Secure Authentication Framework for System-in-Package Using Multi-party Computation
Enhancing Modern SAT Solver With Machine Learning Method
A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse
A VLSI peripheral system for monitoring and stimulating action potentials of cultured neurons
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components
Impolite High Speed Interfaces with Asynchronous Pulse Logic
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays
Generation of reduced analog circuit models using transient simulation traces
A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen Design
Interconnect capacitance extraction for system LCD circuits
Fitting standard cell performance to generalized Lambda distributions
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains
SNAC: Mitigation of Snoop-Based Attacks with Multi-Tier Security in NoC Architectures
A massively parallel and versatile architecture for computer vision
A practical repeater insertion flow
An Efficient Multiple Scan Chain Testing Scheme
Circuit design of a wide tuning range CMOS VCO with automatic amplitude control
Leakage current starved domino logic
Reducing Soft-error Vulnerability of Caches using Data Compression
An efficient power estimation methodology for complex RISC processor-based platforms
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches
HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems
Exploiting Test Resource Optimization in Data Path Synthesis for BIST
High level techniques for power-grid noise immunity
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication
Origami: A Convolutional Network Accelerator
A novel performance driven power gating based on distributed sleep transistor network
A novel reseeding technique for accumulator-based test pattern generation
Using Security Invariant To Verify Confidentiality in Hardware Design
Guided test generation for isolation and detection of embedded trojans in ics
Design and Evaluation of In-Exact Compressor based Approximate Multipliers
An optimized multicore cache coherence design for exploiting communication locality
A design for concurrent error detections in FPLAs
Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic
Design of fail-safe CMOS logic circuits
On Double Transition Faults as a Delay Fault Model
HADES-high-level architecture development and exploration system
Energy and Performance Efficient Computation Offloading for Deep Neural Networks in a Mobile Cloud Computing Environment
Generating decision regions in analog measurement spaces
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors
Practical low-cost CPL implementations threshold logic functions
Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow
Design and analysis of a low-power energy-recovery adder
Efficient Critical Path Selection Under a Probabilistic Delay Model
Buffer design and optimization for lut-based structured ASIC design styles
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems
MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems
SEPUFSoC: Using PUFs for Memory Integrity and Authentication in Multi-Processors System-on-Chip
Improved multilevel routing with redundant via placement for yield and reliability
A novel hybrid FIFO asynchronous clock domain crossing interfacing method
Unlocking High-Performance Low-Power Adiabatic Logic Computing with Modern FinFET Technology Node
600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications
Analysis and design of soft-error hardened latches
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA
Physical Protection of Lattice-Based Cryptography: Challenges and Solutions
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits
An Efficient Residue to Weighted Converter for a New Residue Number System
FP-SMR: A Fully Digital Floating-Point Processing-in-SAS-MRAM for Session-based Recommender System
TimingCamouflage+ Decamouflaged
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems
Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs
Equivalence Checking for Superconducting RSFQ Logic Circuits
Scalable Hybrid CMOS-Diamond Quantum Magnetometers
A revisit to voltage partitioning problem
Design and optimization of MOS current mode logic for parameter variations
A Review of In-Memory Computing Architectures for Machine Learning Applications
A new test pattern generator for high defect coverage in a BIST environment
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
Hardware/software partitioning of operating systems: a behavioral synthesis approach
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007
Ferroelectric-based Accelerators for Computationally Hard Problems
Acceleration of random-walk-based linear circuit analysis using importance sampling
OTFT Based Biosensor for Detection of Breast Cancer Biomarker (C-erbB-2)
Evaluating Efficacy of Model Stealing Attacks and Defenses on Quantum Neural Networks
High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001
A gridless multi-layer area router
Reliable and Robust RRAM-based Neuromorphic Computing
How to Generate Robust Keys from Noisy DRAMs?
Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration
Layout aware retiming
On Hardware Trojan Detection using Oracle-Guided Circuit Learning
Towards Memory-Efficient and Sustainable Machine Unlearning on Edge using Zeroth-Order Optimizer
A Genetic Algorithm for Register Allocation
HOOVER: Hardware Object-Oriented Verification
A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial links
Enhancing Hardware Security with Emerging Transistor Technologies
Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices
Interlocked test generation and digital hardware synthesis
Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits
Cycle-accurate power analysis for multiprocessor systems-on-a-chip
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems
A Comparative Study of Local Net Modeling Using Machine Learning
The Improved COTD Technique for Hardware Trojan Detection in Gate-level Netlist
Bounding Algorithms for Design Space Exploration
The Steiner tree problem with minimum number of vertices in graphs
Transient analysis of gate inside junctionless transistor (GI-JLT)
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units
An experimental environment for design and analysis of global routing heuristics
Integrated logic synthesis using simulated annealing
A system-level methodology for fast multi-objective design space exploration
SET-based nano-circuit simulation and design method using HSPICE
Exact minimum-width transistor placement without dual constraint for CMOS cells
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors
VHDL-based EDA Tool Implementation with Java
Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology
Privacy Threats and Protection in Machine Learning
RESTA: a robust and extendable symbolic timing analysis tool
On Custom LUT-based Obfuscation
Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems
The effect of temperature on cache size tuning for low energy embedded systems
When Transformer Meets Layout Hotspot: An End-to-End Transformer-based Detector with Prior Lithography
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength
On-Demand Device Authentication using Zero-Knowledge Proofs for Smart Systems
Analog Circuit Model of Lamprey Unit Pattern Generator
Stochastic Evolution Algorithm For Technology Mapping
Cost aware fault tolerant logic synthesis in presence of soft errors
A VLSI array processing oriented fast fourier transform algorithm and hardware implementation
Unpaired Image-to-Image Translation Network for Semantic-based Face Adversarial Examples Generation
Toward Fair Ultrasound Computing Tomography: Challenges, Solutions and Outlook
Energy-Efficient Hardware for Language Guided Reinforcement Learning
FFCL: Forward-Forward Net with Cortical Loops, Training and Inference on Edge Without Backpropogation
Impact of lithography-friendly circuit layout
A dual-MOSFET equivalent resistor thermal sensor
IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning
Mammalian Synthetic Gene Networks
Noise-tolerant high fan-in dynamic CMOS circuit design
SIREN: a depth-first search algorithm for the filter design optimization problem
A novel architecture for power maskable arithmetic units
A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II
Evolution of Defenses against Transient-Execution Attacks
CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation
Cost Modeling and Analysis of TSV and Contactless 3D-ICs
Hardening AES Hardware Implementations Against Fault and Error Inject Attacks
MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA
Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs
Algorithm and hardware complexity reduction techniques for k-best sphere decoders
KPU-SQL: Kernel Processing Unit for High-Performance SQL Acceleration
Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks
Multi-corner multi-voltage domain clock mesh design
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms
Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering
Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation
Fixed-outline floorplanning based on common subsequence
Rate-optimal static scheduling for DSP data-flow programs
An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs
Schematic driven layout for the custom VLSI design environment
A dual-rail LUT for reconfigurable logic using null convention logic
Exact Computation of the Entropy of a Logic Circuit
Transistor Chaining in CMOS Leaf Cells of Planar Topology
Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders