yusuke1997/dblp-id-title huggingface dataset:
Analytical Modeling of Pipeline Parallelism
Hardware acceleration in the IBM PowerEN processor: architecture and performance
Optimizing stencil code via locality of computation
The Value Evolution Graph and its Use in Memory Reference Analysis
Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM
SMT-centric power-aware thread placement in chip multiprocessors
Performance extraction and suitability analysis of multi- and many-core architectures for next generation sequencing secondary analysis
Scheduling optimization through iterative refinement
Raising the level of many-core programming with compiler technology: meeting a grand challenge
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs
Orchestrating Multiple Data-Parallel Kernels on Multiple Devices
PEMOGEN: automatic adaptive performance modeling during program runtime
A Loop Correlation Technique to Improve Performance Auditing
Compiler techniques for data prefetching on the PowerPC
Boustrophedonic Frames: Quasi-Optimal L2 Caching for Textures in GPUs
SLAMBooster: An Application-Aware Online Controller for Approximation in Dense SLAM
34th International Conference on Parallel Architectures and Compilation Techniques, PACT 2025, Irvine, CA, USA, November 3-6, 2025
A partitioning-independent paradigm for nested data parallelism
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
Memory System Support for Image Processing
HUNTing the Overlap
Applying Data Speculation in Modulo Scheduled Loops
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
An empirical evaluation of chains of recurrences for array dependence testing
The Dynamic Trace Memorization Reuse Technique
SWEL: hardware cache coherence protocols to map shared data onto shared caches
Realm: an event-based low-level runtime for distributed memory architectures
Tutorials and Workshops
A Heterogeneous Parallel Framework for Domain-Specific Languages
Efficient sequential consistency using conditional fences
Student Research Poster: Software Out-of-Order Execution for In-Order Architectures
2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA
FAME: FAirly MEasuring Multithreaded Architectures
MeToo: Stochastic Modeling of Memory Traffic Timing Behavior
Type-Directed Program Synthesis and Constraint Generation for Library Portability
POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs
POSTER: An Optimized Predication Execution for SIMD Extensions
Big Data Analytics on Flash Storage with Accelerators
Base-delta-immediate compression: practical data compression for on-chip caches
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, PACT'96, Boston, MA, USA, October 20-23, 1996
Architectural support for operating system-driven CMP cache management
Bulk Synchronous Parallel: practical experience with a model for parallel computing
Adaptive insertion policies for managing shared caches
From functional equations to Occam programs: systolizing compilation
IPF for real-time image processing on massively parallel architectures
Region Based Structure Layout Optimization by Selective Data Copying
Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach
Sandboxing transactional memory
Auto-parallelizing stateful distributed streaming applications
Energy-Efficient Acceleration of Hash-Based Post-Quantum Cryptographic Schemes on Embedded Spatial Architectures
Using Hybrid Schedules to Safely Outperform Classical Polyhedral Schedules
Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison
POSTER: CogR: Exploiting Program Structures for Machine-Learning Based Runtime Solutions
Hardware prefetchers for emerging parallel applications
Activation Sequence Caching: High-Throughput and Memory-Efficient Generative Inference with a Single GPU
Eliminating Bottlenecks on Parallel Systems using Adaptive Objects
Introspective Computing
POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection
32nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2023, Vienna, Austria, October 21-25, 2023
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Parallel frame rendering: Trading responsiveness for energy on a mobile GPU
Increasing and Detecting Memory Address Congruence
Dynamic parallelization of modifications to directed acyclic graphs
StatCC: a statistical cache contention model
Practically private: enabling high performance CMPs through compiler-assisted data classification
SpecCheck: A Tool for Systematic Identification of Vulnerable Transient Execution in gem5
Agentic Auto-Scheduling: An Experimental Study of LLM-Guided Loop Optimization
Accelerating Decision-Tree-Based Inference Through Adaptive Parallelization
Superscalar Execution with Direct Data Forwarding
Parallel flow-sensitive pointer analysis by graph-rewriting
COMIC: a coherent shared memory interface for cell be
Adaptive reorder buffers for SMT processors
Multitasking workload scheduling on flexible-core chip multiprocessors
DMATiler: revisiting loop tiling for direct memory access
Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors
A low-cost memory remapping scheme for address bus protection
Compiling to avoid communication
A software memory partition approach for eliminating bank-level interference in multicore systems
Efficient Interconnects for Clustered Microarchitectures
Component-Based Lock Allocation
A Synchronization-Avoiding Distance-1 Grundy Coloring Algorithm for Power-Law Graphs
A Stable Marriage Requires a Shared Residence with Low Contention and Mutual Complementarity
Design Trade-Offs in High-Throughput Coherence Controllers
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems
AutoHOOT: Automatic High-Order Optimization for Tensors
Initial Observations of the Simultaneous Multithreading Pentium 4 Processor
Deep computing in biology: challenges and progress
Drug Design on the Cell BroadBand Engine
Sparso: Context-driven Optimizations of Sparse Linear Algebra
Evaluation of blue Gene/Q hardware support for transactional memories
Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining
Oblivious Routing in On-Chip Bandwidth-Adaptive Networks
ATCache: reducing DRAM cache latency via a small SRAM tag cache
Nomadic Threads: a migrating multithreaded approach to remote memory accesses in multiprocessors
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
Load Balancing in Individual-Based Spatial Applications
Virtues and limitations of commodity hardware transactional memory
Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding
The effects of mispredicted-path execution on branch prediction structures
TSXProf: Profiling Hardware Transactions
GPU Adaptive In-situ Parallel Analytics (GAP)
An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors
Fast Track: Supporting Unsafe Optimizations with Software Speculation
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000
Write Prediction for Persistent Memory Systems
Multithreading with the EM-4 distributed-memory multiprocessor
Early Register Release for Out-of-Order Processors with RegisterWindows
Distributed cooperative caching
The Earth Simulator and Beyond-Technological Considerations Toward the Sustained PetaFlops Machine
Optimize Winograd Convolution for a Novel MIMD Many-core Architecture PEZY-SC3s
POSTER: AR-MMAP: Write Performance Improvement of Memory-Mapped File
G-Sparse: Compiler-Driven Acceleration for Generalized Sparse Computation for Graph Neural Networks on Modern GPUs
A Cost-Effective Clustered Architecture
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999
Feedback-directed pipeline parallelism
The Effect of Program Optimization on Trace Cache Efficiency
Core architecture optimization for heterogeneous chip multiprocessors
Efficient Parallelization Using Combined Loop and Data Transformations
POSTER: IRISX: A Dynamic Trade-off System for Performance Portability on Multi-Accelerator Platforms
The Fault Tolerant Parallel Algorithm: the Parallel Recomputing Based Failure Recovery
Maximizing system utilization via parallelism management for co-located parallel applications
Accelerating DFS-based Subgraph Matching on GPU via Reusing Intersection
Verification-Aware Microprocessor Design
Guess, Measure & Edit: Using Lowering to Lift Tensor Code
The PARSEC benchmark suite: characterization and architectural implications
On-the-fly workload partitioning for integrated CPU/GPU architectures
Scanning Polyhedra without Do-loops
CnC: A Dependence Programming Model
Efficient techniques for predicting cache sharing and throughput
An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors
Data-reuse optimizations for pipelined tiling with parametric tile sizes
Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores
Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processors
FLASH: An Abstract Machine for Modelling Fully Homomorphic Encryption Accelerators
Optimizing Software Data Prefetches with Rotating Registers
Automatic Code Generation for High-Performance Graph Algorithms
Using Algebraic Transformations to Optimize Expression Evaluation in Scientific Codes
Performance Portable Optimizations for Loops Containing Communication Operations
Exploiting Staleness for Approximating Loads on CMPs
Task sampling: Computer architecture simulation in the many-core era
Trace Cache Sampling Filter
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors
Application Transformations for Energy and Performance-Aware Device Management
Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing
Acceleration of bulk memory operations in a heterogeneous multicore architecture
The StarT-Voyager Parallel System
SkipCache: miss-rate aware cache management
3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures
Low-Latency Proactive Continuous Vision
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors
MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory
Automatic Tuning Matrix Multiplication Performance on Graphics Hardware
Scaling Data Analytics with Moore's Law
Overlapping dependent loads with addressless preload
The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation
Branch and data herding: reducing control and memory divergence for error-tolerant GPU applications
Tiered Hashing: Revamping Hash Indexing under a Unified Memory-Storage Hierarchy
X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions
Scalability-based manycore partitioning
Bandwidth Bottleneck in Network-on-Chip for High-Throughput Processors
S-CAVE: Effective SSD caching to improve virtual machine storage performance
EARTH: Efficient Architecture for RISC-V Vector Memory Access
Integrating Loop and Data Transformations for Global Optimization
Integrating nanophotonics in GPU microarchitecture
L1 Cache Filtering Through Random Selection of Memory References
Adaptive Performance Sensitivity Model to Support GPU Power Management
Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations
Branch Prediction in Multi-Threaded Processors
A low-overhead dynamic optimization framework for multicores
Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures
aSOC: A Scalable, Single-Chip Communications Architecture
A Lightweight Model for Software Thread-Level Speculation (TLS)
Accelerating multicore reuse distance analysis with sampling and parallelization
Decomposed software pipelining with reduced register requirement
NLP-Fast: A Fast, Scalable, and Flexible System to Accelerate Large-Scale Heterogeneous NLP Models
Data Dependence Testing in Practice
Maximizing CMP Throughput with Mediocre Cores
ScaleMoE: A Fast and Scalable Distributed Training Framework for Large-Scale Mixture-of-Experts Models
Detecting Change in Program Behavior for Adaptive Optimization
Communication Avoiding Algorithms: Analysis and Code Generation for Parallel Systems
Modeling and Performance Evaluation of TSO-Preserving Binary Optimization
Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systems
Parallelism in Mainstream Enterprise Platforms of the Future
Custom High-Performance Vector Code Generation for Data-Specific Sparse Computations
Towards concurrency race debugging: an integrated approach for constraint solving and dynamic slicing
Building expressive, area-efficient coherence directories
The changing role of supercomputing
General chairs' welcome message
Optimizing Aggregate Computation of Graph Neural Networks with on-GPU Interpreter-Style Programming
The Role of Computational Science in Energy Efficiency and Renewable Energy
On the Complexity of Loop Fusion
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults
Overcoming Limitations of Prefetching in Multiprocessors by Compiler-Initiated Coherence Actions
A scalable register file architecture for dynamically scheduled processors
Challenges and New Approaches to Program Analysis
Dryadic: Flexible and Fast Graph Pattern Matching at Scale
Analysing Dataflow Programs with Causation Traces
Heterogeneous microarchitectures trump voltage scaling for low-power cores
POSTER: A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLS
Tiling and optimizing time-iterated computations on periodic domains
Locality Analysis for Parallel C Programs
Lightweight Provenance Service for High-Performance Computing
Making STMs Cache Friendly with Compiler Transformations
Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core Scaling
Extending Object-Oriented Optimizations for Concurrent Programs
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches
PATS: pattern aware scheduling and power gating for GPGPUs
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
An Efficient Vectorization Approach to Nested Thread-level Parallelism for CUDA GPUs
Proximity coherence for chip multiprocessors
Leveraging on-chip networks for data cache migration in chip multiprocessors
MaSiF: machine learning guided auto-tuning of parallel skeletons
Cache Miss Curve Analysis via Cardinality Domain
Path Prediction for High Issue-Rate Processors
ALEA: Fine-Grain Energy Profiling with Basic Block Sampling
Multi-mode energy management for multi-tier server clusters
POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling
ATTC (@C): Addressable-TLB based Translation Coherence
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors
Compiling and Optimizing Java 8 Programs for GPU Execution
Compressing Extended Program Traces Using Value Predictors
WAYPOINT: scaling coherence to thousand-core architectures
Accelerating Fourier and Number Theoretic Transforms using Tensor Cores and Warp Shuffles
Thread-to-Core Allocation in ARM Processors Building Synergistic Pairs
In-memory Data Flow Processor
TCPT - Thread criticality-driven prefetcher throttling
Exploring the Design Space of Future CMPs
InnerSP: A Memory Efficient Sparse Matrix Multiplication Accelerator with Locality-Aware Inner Product Processing
From petascale to the pocket: Adaptively scaling parallel programs for mobile SoCs
Data remapping for an energy efficient burst chop in DRAM memory systems
POSTER: A Polyhedral+Dataflow Intermediate Language for Performance Exploration
FlatPack: Flexible Compaction of Compressed Memory
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling
Beforehand Migration on D-NUCA Caches
An event-based language for dynamic binary translation frameworks
Approximate Pattern Matching for On-Chip Interconnect Traffic Prediction
Split Last-Address Predictor
The design of a modulo scheduler for a superscalar RISC processor
MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance
SPipe: Hybrid GPU and CPU Pipeline for Training LLMs under Memory Pressure
Speculative dynamic vectorization for HW/SW co-designed processors
NoC-aware cache design for chip multiprocessors
Optimally Synchronizing DOACROSS Loops on Shared Memory Multiprocessors
Combining optimization for cache and instruction-level parallelism
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Compiler Directed Early Register Release
Inter-Procedural Loop Fusion, Array Contraction and Rotation
Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing
Fooling the Sense of Cross-Core Last-Level Cache Eviction Based Attacker by Prefetching Common Sense
Automatic generation of loop scheduling for VLIW
Efficient data protection for distributed shared memory multiprocessors
Control of loop parallelism in multithreaded code
Enhancing Data Locality for Dynamic Simulations through Asynchronous Data Transformations and Adaptive Control
FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks
Performance Characterization of Popular DNN Models on Out-of-Order CPUs
Active learning accelerated automatic heuristic construction for parallel program mapping
Energy-Efficient Hybrid DRAM/NVM Main Memory
PACT '20: International Conference on Parallel Architectures and Compilation Techniques, Virtual Event, GA, USA, October 3-7, 2020
Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks
Deep Jam: Conversion of Coarse-Grain Parallelism to Instruction-Level and Vector Parallelism for Irregular Applications
Multilayer Compute Resource Management with Robust Control Theory
ReACT: Redundancy-Aware Code Generation for Tensor Expressions
To Stack or Not To Stack
A Phase-Adaptive Approach to Increasing Cache Performance
Cost-driven thread coarsening for GPU kernels
DART: distributed adaptive radix tree for efficient affix-based keyword search on HPC systems
rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main Memory
An Adaptive Algorithm Selection Framework
Application-to-core mapping policies to reduce memory interference in multi-core systems
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016
AKULA: a toolset for experimenting and developing thread placement algorithms on multicore systems
MOSAIC: Heterogeneity-, Communication-, and Constraint-Aware Model Slicing and Execution for Accurate and Efficient Inference
SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels
HBMax: Optimizing Memory Efficiency for Parallel Influence Maximization on Multicore Architectures
Efficient Backtracking Instruction Schedulers
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation
Enforcing Crash Consistency of Evolving Network Analytics in Non-Volatile Main Memory Systems
Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy Update
AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors
POSTER: Pagoda: A Runtime System to Maximize GPU Utilization in Data Parallel Tasks with Limited Parallelism
Fast Parallel Equivalence Relations in a Datalog Compiler
A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors
Programming Strategies for GPUs and their Power Consumption
What is the cost of weak determinism?
Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy
Efficient emulation of hardware prefetchers via event-driven helper threading
Locality-aware memory association for multi-target worksharing in OpenMP
A design study of the EARTH multiprocessor
I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems
Transactional event profiling in a best-effort hardware transactional memory system
Moths: mobile threads for on-chip networks
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
BOLT: Optimizing OpenMP Parallel Regions with User-Level Threads
Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018
Y-Branches: When You Come to a Fork in the Road, Take It
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches
Fairness-aware scheduling on single-ISA heterogeneous multi-cores
Predicting Conditional Branches With Fusion-Based Hybrid Predictors
Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications
Adaptive granularity: transparent integration of fine- and coarse-grain communication
The PROMIS Compiler Prototype
Parallelizing Neural Network Models Effectively on GPU by Implementing Reductions Atomically
POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms
Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreading
SimplePIM: A Software Framework for Productive and Efficient Processing-in-Memory
ArrayTool: a lightweight profiler to guide array regrouping
Bitwise data parallelism in regular expression matching
RackMem: A Tailored Caching Layer for Rack Scale Computing
Increasing superscalar performance through multistreaming
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors
Performance of Message-Passing Systems using a Zero-Copy Communication Protocol
Prediction Based DRAM Row-Buffer Management in the Many-Core Era
Runahead Threads: Reducing Resource Contention in SMT Processors
SPATL: Honey, I Shrunk the Coherence Directory
On the Efficiency of Reductions in µ-SIMD Media Extensions
Greater Performance and Better Efficiency: Predicated Execution has shown us the way
POSTER: Quiescent and Versioned Shadow Copies for NVM
Poster:Value-Aware Scheduler for Energy Reduction
Subspace snooping: filtering snoops with operating system support
Exploiting subtrace-level parallelism in clustered processors
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors
An Architecture for Resilient Federated Learning through Parallel Recognition
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures
μC-States: Fine-grained GPU Datapath Power Management
Determining the Idle Time of Tiling: New Results
SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link
ComP-net: command processor networking for efficient intra-kernel communications on GPUs
COLORIS: a dynamic cache partitioning system using page coloring