yusuke1997/dblp-id-title huggingface dataset:
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells
An Accurate and Efficient Method for Eliminating the Requirement of Coherent Sampling in Multi-Tone Test
A DFT Technique for Analog-to-Digital Converters with digital correction
Fault injection scan design for enhanced VLSI design verification
Testing for Transistor Aging
Reducing Embedded SRAM Test Time under Redundancy Constraints
Keynote address: New opportunities in the internet of things
Salvaging test windows in BIST diagnostic
A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset
Automatic Test Pattern Generation for Interconnect Open Defects
Analog circuit simulation and troubleshooting with FLAMES
Integrated CMOS Power Sensors for RF BIST Applications
Hardware-based Real-time Workload Forensics via Frame-level TLB Profiling
Performance Degradation Monitoring for Analog Circuits Using Lightweight Built-in Components
A built-in self-test technique for transmitter-only systems
Gradient Attention Map Based Verification of Deep Convolutional Neural Networks with Application to X-ray Image Datasets
A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?
A practical approach to instruction-based test generation for functional modules of VLSI processors
Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories
Silicon Evaluation of Static Alternative Fault Models
Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding
Design of a fault tolerant 100 Gbits solid-state mass memory for satellite
Detectable perturbations: a paradigm for technology-specific multi-fault test generation
Innovative Practices Track: Next Generation Test Standards
RF Digital Signal Generation Beyond Nyquist
Delay test resource allocation and scheduling for multiple frequency domains
An Introduction to RF Testing: Device, Method and System
A totally self-checking checker for a parallel unordered coding scheme
Finding best voltage and frequency to shorten power-constrained test time
A fault model for switch-level simulation of gate-to-drain shorts
Cost modeling and analysis for interposer-based three-dimensional IC
A holistic approach to accurate tuning of RF systems for large and small multiparameter perturbations
A distributed AXI-based platform for post-silicon validation
Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods
IP Session on Machine Learning Applications in IC Test-Related Tasks
Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes
A Programmable Window Comparator for Analog Online Testing
Hybrid Binary Neural Networks: A Tutorial Review
Expanding a Pool of Functional Test Sequences to Support Test Compaction
On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection
Keynote address: Opening keynote
16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA
Garblet: Multi-party Computation for Protecting Chiplet-based Systems
Fault Testing for Reversible Circuits
Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering
Hardware-Software Co-Design for Test: It's the Last Straw!
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy
Staggered ATPG with capture-per-cycle observation test points
A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits
A Built-In Self-Repair Scheme for Multiport RAMs
Linear microcircuit fault modeling and detection
Gate-to-channel shorts in BiCMOS logic gates
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
Parallel Loopback Test of Mixed-Signal Circuits
Verification of Processor Microarchitectures
Path Delay Fault Simulation on Large Industrial Designs
Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probing
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
Special Session: Does Approximation Make Testing Harder (or Easier)?
Constraints for using IDDQ testing to detect CMOS bridging faults
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin
Highly X-Tolerant Selective Compaction of Test Responses
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric
Testing of a low-VMIN data-aware dynamic-supply 8T SRAM
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
Artificial Bee Colony Optimization to Accelerate High-Speed Serial I/O Tx Equalization
Design of a fast, easily testable ALU
Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs
Aliasing computation using fault simulation with fault dropping
Low-Power Voltage Reference: Review & Progress
Diagnosis of Scan Clock Failures
Special Session: Machine Learning for Semiconductor Test and Reliability
Design for Testability of Low Dropout Regulators
Real-time on-board bus testing
Test generator with preselected toggling for low power built-in self-test
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions
Program Slicing for Hierarchical Test Generation
Harmony Widget for X-free scan testing
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions
Probe point insertion for at-speed test
Innovative practices on memory test practice
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Fault tolerance of approximate compute algorithms
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits
Development and empirical verification of an accuracy model for the power down leakage tests
Diagnosis of Full Open Defects in Interconnecting Lines
Test Compaction Under Bounded Transparent-Scan
Speeding-Up IDDQ Measurements
Consistency in wafer based outlier screening
Diagnosis of scan path failures
Decompression of test data using variable-length seed LFSRs
Wireless Test
Efficient Implication - Based Untestable Bridge Fault Identifier
Testability properties of acyclic structures and applications to partial scan design
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit
Integrating Logic BIST in VLSI Designs with Embedded Memories
Exponent monitoring for low-cost concurrent error detection in FPU control logic
Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise
On Removing Redundant Faults in Synchronous Sequential Circuits
Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses
Using ATPG for clock rules checking in complex scan design
Diagnostic Test Pattern Generation for Sequential Circuits
Coverage closure in SoC verification: Are we chasing a mirage?
Checking experiments to test latches
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing
Improving topological ATPG with symbolic techniques
Design SRAMs for burn-in
Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology
Implementing a Scheme for External Deterministic Self-Test
Machine Learning-based Noise Classification and Decomposition in RF Transceivers
Process independent gain measurement with low overhead via BIST/DUT co-design
Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm
Fault modeling and testing of self-timed circuits
Special session 11B: Hot topic hardware security: Design, test and verification issues
Error Resilient Hyperdimensional Computing Using Hypervector Encoding and Cross-Clustering
Path constraint solving based test generation for observability-enhanced branch coverage
Pseudoduplication of floating-point addition. A method of compiler generated checking of permanent hardware faults
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development
Detection of CMOS Defects under Variable Processing Conditions
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
Testing "untestable" faults in three-state circuits
A Structural Approach for Space Compaction for Concurrent Checking and BIST
Accurate spectral testing with non-coherent sampling for large distortion to noise ratios
Innovative practices session 11C SoC testing
Testing retention flip-flops in power-gated designs
Logic BIST Using Constrained Scan Cells
On Silicon-Based Speed Path Identification
DFT and Test Problems from the Trenches
Innovation Practices Track: Innovation on Telemetry Monitoring
Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme
Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault Simulation
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
Towards spatial fault resilience in array processors
Word Voter: A New Voter Design for Triple Modular Redundant Systems
VTS 1999 Keynote Address Embedded Test OR External Test
A Circuit Level Fault Model for Resistive Opens and Bridges
Scalable parallel fault simulation for shared-memory multiprocessor systems
A testable static RAM structure for efficient coverage of pattern sensitive faults
Functional learning: a new approach to learning in digital circuits
A Built-In Self-Test scheme for DDR memory output timing test and measurement
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
Guardbanding VLSI EEPROM test programs
The buck stops with wafer test: Dream or reality?
On the Automation of the Test Flow of Complex SoCs
Switch-level modeling of feedback faults using global oscillation control
Monitoring power dissipation for fault detection
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code
Special Session: Testing and Characterization for Large-Scale Programmable Analog Systems
Efficient test generation for built-in self-test boundary-scan template
An Overview of Failure Mechanisms in Embedded Flash Memories
Soft Delay Error Effects in CMOS Combinational Circuits
Built-in self-test for manufacturing TSV defects before bonding
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan
An unexpected factor in testing for CMOS opens: the die surface
27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA
Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages
On the Fault Coverage of Interconnect Diagnosis
Eliminating undetectable shorts between horizontal wires during channel routing
An industrial case study of analog fault modeling
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
A Test Interface for Built-In Test of Non-Isolated Scanned Cores
Special Session: Reliability Analysis for AI/ML Hardware
Ping-pong test: Compact test vector generation for reversible circuits
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits
OpenAssert: Towards Secure Assertion Generation using Large Language Models
Integral impact of BTI and voltage temperature variation on SRAM sense amplifier
Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final
IP and Automation to Support IEEE P1500
Defect Tolerance for Gracefully-Degradable Microfluidics-Based Biochips
A Memory Failure Pattern Analyzer for memory diagnosis and repair
Decision Tree Based Mismatch Diagnosis in Analog Circuits
Constructing Augmented Multimode Compactors
Behavior of faulty single BJT BiCMOS logic gates
Built-In Test of RF Components Using Mapped Feature Extraction Sensors
Special Session: ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security Verification
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration
An aging-aware flip-flop design based on accurate, run-time failure prediction
A new strategy for testing analog filters
A model for testing reliable VLSI routing architectures
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs
A diagnosis testbench of analog IP cores against on-chip environmental disturbances
Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study
RF/Analog Test of Circuits and Systems
Special session: How approximate computing impacts verification, test and reliability
Exact probabilistic analysis of error detection for parity checkers
On estimating bounds of the quiescent current for I DDQ testin
Calibration-assisted production testing for digitally-calibrated ADCs
MBIST-based Trim-Search Test Time Reduction for STT-MRAM
Using Verification Technology for Validation Coverage Analysis and Test Generation
Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
A design for testability technique for test pattern generation with LFSRs
Automatic Generation of Diagnostic March Tests
Enabling Embedded Memory Diagnosis via Test Response Compression
Performance enhancement techniques and verification methods for radio frequency circuits and systems
Fast RF Mismatch Calibration Using Built-in Detectors
At-Speed Transition Fault Testing With Low Speed Scan Enable
Scalable dynamic technique for accurately predicting power-supply noise and path delay
Delay testing and failure analysis of ECL logic with embedded memories
GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness
Analysis of Ground Bounce in Deep Sub-Micron Circuits
Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *
Signature oriented model pruning to facilitate multi-threaded processors debugging
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach
Cellular automata for deterministic sequential test pattern generation
Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits
Incremental logic rectification
Distributed self-diagnosis of VLSI mesh array processors
Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects
High-Accuracy, Cost-Effective Built-In Self-Test Approach for High-Resolution Data Converters
Security primitives (PUF and TRNG) with STT-MRAM
Fast Test Generation for Structurally Similar Circuits
Design-For-Testability for Switched-Current Circuits
Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems
Pre and post silicon server platform transient performance using trans-inductor voltage regulator
Best Methods for At-Speed Testing?
Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity
Probabilistic measures of fault equivalence in mixed-signal systems
Innovative practices session 5C: Post-silicon debug
Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment
March iC-: An Improved Version of March C- for ADOFs Detection
Fault diagnosis for flow-based microfluidic biochips
Thwarting timing attacks on NEMS relay based designs
Signal probability calculations using partial functional manipulation
A design for testability scheme to reduce test application time in full scan
Handling Pattern-Dependent Delay Faults in Diagnosis
Efficient Seed Utilization for Reseeding based Compression
Hard faults diagnosis in analog circuits using sensitivity analysis
Timing-Verification Test Generation Targeting Small Delay Defects
Scan testing of micropipelines
24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA
Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests
A method for phase noise extraction from data communication
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States
Security validation in IoT space
A defect-tolerant design for mask ROMs
An Economic Selecting Model for DFT Strategies
Special session: Hot topic design and test of 3D and emerging memories
Aging monitor reuse for small delay fault testing
Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
Behavioral Fault Modeling in a VHDL Synthesis Environment
Discrete test generation by continuous methods
Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs
Diagnostic simulation of stuck-at faults in combinational circuits
A multi-parameter functional side-channel analysis method for hardware trust verification
Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test
Controllability and observability measures for functional-level testability evaluation
Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and Testing
Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics
A methodology for the insertion of a hierarchical and boundary-scan compatible self test
Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability
Training-based forming process for RRAM yield improvement
Innovative practices session 10B innovative practices in Asia-2: From cost perspective
On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair
Architecture of test support ICs for mixed-signal testing
Functional Test Generation for AI Accelerators using Bayesian Optimization ∗
A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended Prob
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation
Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts?
VDDmin test optimization for overscreening minimization through adaptive scan chain masking
Methods for testing path delay and static faults in RSFQ circuits
A Secure and Low-overhead Active IC Metering Scheme
Innovative Practices Track: Session 7 Yield Optimization, Reducing Costs, and Improving Quality
Nonlinear Analog DC Fault Simulation by One-Step Relaxation
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis
Special Session: Calibrating mismatch in an ISFET with a Floating-Gate
Safety computations in integrated circuits
Hot topic session 9C: Test and fault tolerance for emerging memory technologies
ELF-Murphy Data on Defects and Test Sets
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
High-Level Observability for Effective High-Level ATPG
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes
On robustness of required random test length with regard to fault occurrence hypotheses
A Novel Graph Coloring Based Solution for Low-Power Scan Shift
Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -
Inconsistent Fail due to Limited Tester Timing Accuracy
Compact test sets for industrial circuits
Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure Processes
Yield and Cost Analysis of a Reliable NoC
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test
Recent advances in BIST
26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA
A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
On the investigation of built-in tuning of RF receivers using on-chip polyphase filters
Test Technology Technical Council
Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead
Chip-level modeling and analysis of electrical masking of soft errors
BIST Pretest of ICs: Risks and Benefits
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs
Special Session: Novel Attacks on Logic-Locking
A pseudo-dynamic comparator for error detection in fault tolerant architectures
Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs
Synthesis for Broadside Testability of Transition Faults
Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs
15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA
Innovative Practices Track: Session 3 Test and Functional Safety Standards
Built-in self-diagnostic by space-time compression of test responses
On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field Sensor
Innovative practices session 1C: New technologies, new challenges - 1 [3 presentations]
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories
On parallel switch level fault simulation
Use of Multiple IDDQ Test Metrics for Outlier Identification
Flash Memory Built-In Self-Diagnosis with Test Mode Control
Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs
Flash Memory Disturbances: Modeling and Test
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation
Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier
A unified test architecture for on-line and off-line delay fault detections
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs
Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes
Continuous wave radar circuitry testing using OFDM technique
Efficient SAT-based generation of hazard-activated TSOF tests
A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging
Improving Path Delay Fault Testability by Path Removal
An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories
An industrial experience in the built-in self test of embedded RAMs
ATPG for Design Errors-Is It Possible?
35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017
Fault detection and fault localization using I DDQ -testing in parallel testable FAST-SRAMs
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores
An Evaluation of Pseudo Random Testing for Detecting Real Defects
Measuring Stray Capacitance on Tester Hardware