yusuke1997/dblp-id-title huggingface dataset:
SHEAR er : highly-efficient hyperdimensional computing by software-hardware enabled multifold approximation
Adopting TLB index-based tagging to data caches for tag energy reduction
Power-efficient variation-aware photonic on-chip network management
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference
XIOSim: power-performance modeling of mobile x86 cores
Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs
Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training
System level power and performance modeling of GALS point-to-point communication interfaces
Post placement leakage reduction with stress-enhanced filler cells
Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon
A 1.2V, 430MHz, 4dBm power amplifier and a 250muW front-end, using a standard digital CMOS process
Let's get physical: Adding physical dimensions to cyber systems
Wearable computing: a catalyst for business and entertainment
Dynamic voltage frequency scaling for multi-tasking systems using online learning
Bank stealing for conflict mitigation in GPGPU Register File
SRAM Gauge: SRAM Health Monitoring via Cells Race
Branch prediction on demand: an energy-efficient solution
Irredundant address bus encoding for low power
An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding
Micro power "relative precision" 13 bits cyclic RSD A/D converter
Lower bounds on power dissipation for DSP algorithms
Towards wearable piezoelectric energy harvesting: modeling and experimental validation
Energy efficient design of portable wireless systems
Deep-PowerX: a deep learning-based framework for low-power approximate logic synthesis
HANDS: heterogeneous architectures and networks-on-chip design and simulation
Floating body effects in partially-depleted SOI CMOS circuits
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems
A framework for energy consumption based design space exploration for wireless sensor nodes
Leakage minimization using self sensing and thermal management
Scaling of stack effect and its application for leakage reduction
A GHz-class charge recovery logic
Visible Light Synchronization for Time-Slotted Energy-Aware Transiently-Powered Communication
Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
SpartanSSD: a Reliable SSD under Capacitance Constraints
Pulse width modulation for reduced peak power full-swing on-chip interconnect
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
Activity-sensitive clock tree construction for low power
Energy-efficient design of battery-powered embedded systems
An Analog Multiplier Utilizing an Unconventional Bit-Weighting Scheme with Application to Neural Network Quantization
Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation
LOCo: LPDDR Optimization with Compression and IECC scheme for DNN Inference
Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures
PreTrans: Reducing TLB CAM-search via page number prediction and speculative pre-translation
Understanding the energy efficiency of simultaneous multithreading
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2024, Newport Beach, CA, USA, August 5-7, 2024
Clocking strategies and scannable latches for low power appliacations
The need for a full-chip and package thermal model for thermally optimized IC designs
Something old and something new: P-states can borrow microarchitecture techniques too
A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOS
WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories
An Efficient Parallel Scheduling Scheme on Multi-partition PCM Architecture
Energy efficient Modulation and MAC for Asymmetric RF Microsensor Systems
Operating-system directed power reduction
SRAM cell optimization for low AVT transistors
ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors
Towards a software approach to mitigate voltage emergencies
A look inside IBM's green data center research
Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier
Fast and energy-efficient constant-coefficient FIR filters using residue number system
A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applications
A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers
An analytical solution for multi-core energy calculation with consideration of leakage and temperature dependency
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2021, Boston, MA, USA, July 26-28, 2021
Technology exploration for adaptive power and frequency scaling in 90nm CMOS
Power-aware code scheduling for clusters of active disks
Large-scale battery system modeling and analysis for emerging electric-drive vehicles
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
REEL: Reducing effective execution latency of floating point operations
SPADES: A 0.54-GFLOPS/W Sparse Matrix Vector Multiplication Accelerator Featuring On-the-Fly GZIP Decompression for 3.36X Reduction in Off-Chip Data Movement
Design and implementation of nonvolatile power-gating SRAM using SOTB technology
A 2.6 mW Single-Ended Positive Feedback LNA for 5G Applications
Simultaneous buffer and wire sizing for performance and power optimization
Gated low-power clock tree synthesis for 3D-ICs
A low voltage CMOS current source
High performance and low power FIR filter design based on sharing multiplication
An expected-utility based approach to variation aware VLSI optimization under scarce information
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives
A bipolar ±40 MV self-starting boost converter with transformer reuse for thermoelectric energy harvesting
Low power design from technology challenge to great products
Linear programming for sizing, V th and V dd assignment
A high speed and low power SOL inverter using active body-bias
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique
XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage
A 1V, 5mW, 1.8GHz balanced voltage-controlled oscillator with an integrated resonator
Next-generation power-aware design
DR. Swap: energy-efficient paging for smartphones
Retractile clock-powered logic
Can We Guarantee Performance Requirements under Workload and Process Variations?
Practical considerations of clock-powered logic
How to cultivate a green decision tree without loss of accuracy?
Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation
Stream synthesis for efficient power simulation based on spectral transforms
A dynamic body-biased SRAM with asymmetric halo implant MOSFETs
Dynamic thermal management for MPEG-2 decoding
Tag check elision
Wireless sensor networks: application driver for low power distributed systems
Statues: Energy-Efficient Video Object Detection on Edge Security Devices with Computational Skipping
Model-Driven Dataset Generation for Data-Driven Battery SOH Models
Dynamic Bit-width Reconfiguration for Energy-Efficient Deep Learning Hardware
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits
Theoretical bounds for switching activity analysis in finite-state machines
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
A novel continuous-time common-mode feedback for low-voltage switched-OPAMP
Process variation aware data management for STT-RAM cache design
Reducing pipeline energy demands with local DVS and dynamic retiming
A programming environment with runtime energy characterization for energy-aware applications
A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design
Thermal-aware bus-driven floorplanning
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
Energy conservation by adaptive feature loading for mobile content-based image retrieval
Design exploration of racetrack lower-level caches
Simultaneous Optimization of Placement Legalization and Multi-bit Flip-flop Allocation in Physical Design Automation
The opportunity cost of low power design: a case study in circuit tuning
Understanding query complexity and its implications for energy-efficient web search
Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design
Full-system chip multiprocessor power evaluations using FPGA-based emulation
Modulation scaling for Energy Aware Communication Systems
A 5V output voltage boost switching converter with hybrid digital and analog PWM control
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface
Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment
The impact of variability on power
Enhanced 3D Implementation of an Arm ® Cortex ® -A Microprocessor
Towards the capability of providing power-area-delay trade-off at the register transfer level
Transistor reordering for low power CMOS gates using an SP-BDD representation
A low-power digitally-programmable variable gain amplifier in 65 nm CMOS
Scaled Population Division for Approximate Computing
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation
CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks
Estimation of power distribution in VLSI interconnects
Improving sampling efficiency for system level power estimation
GRLC: grid-based run-length compression for energy-efficient CNN accelerator
Practically scalable floorplanning with voltage island generation
FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation
Spin-torque sensors with differential signaling for fast and energy efficient global interconnects
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition
High-throughput and low-power DSP using clocked-CMOS circuitry
A deterministic-dither-based, all-digital system for on-chippower supply noise measurement
A compact macromodel for the charge phase of a battery with typical charging protocol
Energy-recovery CMOS for highly pipelined DSP designs
Adaptive RF chain management for energy-efficient spatial-multiplexing MIMO transmission
Low power branch prediction for embedded application processors
Therminator: a thermal simulator for smartphones producing accurate chip and skin temperature maps
Securing Deep Neural Networks on Edge from Membership Inference Attacks Using Trusted Execution Environments
A case for leveraging 802.11p for direct phone-to-phone communications
Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning
Automatic characterization and modeling of power consumption in static RAMs
Power grid voltage integrity verification
Analysis of the Effect of Hot Carrier Injection in An Integrated Inductive Voltage Regulator
Reducing the frequency of tag compares for low power I-cache design
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs
Self-timed circuits for energy harvesting AC power supplies
Power-efficient embedded processing with resilience and real-time constraints
Reconfigurable thermoelectric generators for vehicle radiators energy harvesting
Low-power H.264/AVC baseline decoder for portable applications
Is nanoelectronics the future of microelectronics?
Power-aware modulo scheduling for high-performance VLIW processors
Controller re-specification to minimize switching activity in controller/data path circuits
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
Power-performance management on an IBM POWER7 server
Enabling efficient ReRAM-based neural network computing via crossbar structure adaptive optimization
A selective filter-bank TLB system
Hyft: A Reconfigurable Softmax Accelerator with Hybrid Numeric Format for both Training and Inference
CASA: correlation-aware speculative adders
On Trade-off Between Static and Dynamic Power Consumption in NoC Power Gating
PiQi: Partially Quantized DNN Inference on HMPSoCs
Analog circuit shielding routing algorithm based on net classification
An energy-efficient adaptive hybrid cache
Non-stationary effects in trace-driven power analysis
Microarchitectural techniques for power gating of execution units
Similarity-Based LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition
Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction
A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node
PS-BC: power-saving considerations in design of buffer caches serving heterogeneous storage devices
A low-power APUF-based environmental abnormality detection framework
Tackling voltage emergencies in NoC through timing error resilience
Low power address encoding using self-organizing lists
A unified approach in the analysis of latches and flip-flops for low-power systems
A Low-power 4096x2160@30fps H.265/HEVC Video Encoder for Smart Video Surveillance
Powering the internet of things
A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications
A framework of concurrent task scheduling and dynamic voltage and frequency scaling in real-time embedded systems with energy harvesting
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments
Design of a low-power CMOS baseband circuit for wideband CDMA testbed (poster session)
A simple yet efficient accuracy configurable adder design
Predict and act: dynamic thermal management for multi-core processors
Power-delay tradeoffs for radix-4 and radix-8 dividers
Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs
A Multicore GNN Training Accelerator
Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU
Dynamic thermal management for single and multicore processors under soft thermal constraints
1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM
A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints
Bus encoding for simultaneous delay and energy optimization
Emerging technologies and their impact on system design
Associative processing with coupled oscillators
Short circuit power consumption of glitches
Synergistic circuit and system design for energy-efficient and robust domain wall caches
Power management for mobile games on asymmetric multi-cores
Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM
Hierarchical power budgeting for Dark Silicon chips
An extended addressing mode for low power
Balanced energy optimization
Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization
A capacitor-based D/A converter with continuous time output for low-power applications
A model for array-based approximate arithmetic computing with application to multiplier and squarer design
A recursive algorithm for low-power memory partitioning
Sleep transistor sizing and control for resonant supply noise damping
Content-based Power-saving Design for Augmented Reality Applications on Mobile Devices
12-b 125 MSPS CMOS D/A designed for spectral performance
A gate resizing technique for high reduction in power consumption
Vibration energy scavenging and management for ultra low power applications
Invited paper: Secure swarm intelligence: A new approach to many-core power management
Memory energy management for an enterprise decision support system
A tutorial on test power
Ultra low power electronics in the next decade
Hybrid dual-threshold design techniques for high-performance processors with low-power features
Accelerating LLM Inference with Flexible N:M Sparsity via A Fully Digital Compute-in-Memory Accelerator
Power reduction techniques for a spread spectrum based correlator
Small-area and low-energy K -best MIMO detector using relaxed tree expansion and early forwarding
Semantics-driven sensor configuration for energy reduction in medical sensor networks
Design and optimization of a reconfigurable power delivery network for large-area, DVS-enabled OLED displays
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
Versatile high-fidelity photovoltaic module emulation system
Dynamic power estimation using the probabilistic contribution measure (PCM)
Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system
ACE-GPU: Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU
Real-energy: a new framework and a case study to evaluate power-aware real-time scheduling algorithms
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits 1, 2
PARE: a power-aware hardware data prefetching engine
A low power switching power supply for self-clocked systems
The CAD challenges of designing low power, high performance VLSI system
Statistical Optimization of Compute In-Memory Performance Under Device Variation
Tutorial: The Energy Cost of Privacy and Security
Power phase variation in a commercial server workload
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture
Reducing data cache energy consumption via cached load/store queue
Effects of correlations on accuracy of power analysis - an experimental study
eDRAM-based tiered-reliability memory with applications to low-power frame buffers
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction
A three-port nRERL register file for ultra-low-energy applications
A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications
Algorithmic transforms for efficient energy scalable computation
Optimizing Heterogeneous Compute-in-Memory with Hybrid Dataflow and In-Network Reduction for Vision Transformer
An Energy-Efficient 3D Point Neural Network Accelerator with Fine-grained LiDAR-SoC Pipeline Structure
Estimation of energy consumption in speed-independent control circuits
Enabling Highly-Efficient DNA Sequence Mapping via ReRAM-based TCAM
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
Energy-efficient dynamic instruction scheduling logic through instruction grouping
The digital bidirectional function as a hardware security primitive: Architecture and applications
TensorCV: Accelerating Inference-Adjacent Computation Using Tensor Processors
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion
A low-power, multichannel gated oscillator-based CDR for short-haul applications
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes
Reducing power density through activity migration
Layerwise Disaggregated Evaluation of Spiking Neural Networks
Everlast: long-life, supercapacitor-operated wireless sensor node
Peak power modeling for data center servers with switched-mode power supplies
Lazy instruction scheduling: keeping performance, reducing power
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing
Write intensity prediction for energy-efficient non-volatile caches
HomeRun: HW/SW Co-Design for Program Atomicity on Self-Powered Intermittent Systems
3D CMOS SOL for high performance computing
Transformation and synthesis of FSMs for low-power gated-clock implementation
Oversampled gain-boosting
Low power and low voltage CMOS digital circuit techniques
Power dissipated by CMOS gates driving lossless transmission lines
Proactive temperature management in MPSoCs
Fine-grained write scheduling for PCM performance improvement under write power budget
Estimating influence of data layout optimizations on SDRAM energy consumption
Making TSUBAME2.0, the world's greenest production supercomputer, even greener: challenges to the architects
Experimental investigation of inductorless, single-stage boost rectification for sub-mW electromagnetic energy harvesters
An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systems
Analysis and implementation of charge recycling for deep sub-micron buses
Fixed-phase retiming for low power design
Low power SRAM techniques for handheld products
Models for energy-efficient approximate computing
Design of dual threshold voltages asynchronous circuits
Circuit methods for the integration of low voltage (1.1-1.8V) analog functions on system-on-a-chip IC's in a single-poly CMOS processes
TSV array utilization in low-power 3D clock network design
Characterizing and modeling minimum energy operation for subthreshold circuits
Autonomous I/O for Intermittent IoT Systems
Efficient scan-based BIST scheme for low power testing of VLSI chips
Power macro-models for DSP blocks with application to high-level synthesis
Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers
Peak temperature control and leakage reduction during binding in high level synthesis
Low-power adaptive RF system design using real-time fuzzy noise-distortion control
Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel)
Contents provider-assisted dynamic voltage scaling for low energy multimedia applications
Energy-secure computing
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V DD ) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V DD between flip-flops and combinational logics
Failing to fail: achieving success in advanced low power design using UPF
A preactivating mechanism for a VT-CMOS cache using address prediction
Expected system energy consumption minimization in leakage-aware DVS systems
Low cost instruction cache designs for tag comparison elimination
ML-Power: Machine Learning based Power Estimation for SoCs
Does low-power design imply energy efficiency for data centers?
A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices
SHRIMP: Efficient Instruction Delivery with Domain Wall Memory