yusuke1997/dblp-id-title huggingface dataset:
Low-power multipliers by minimizing switching activities of partial products
Automatic skill acquisition in Reinforcement Learning using connection graph stability centrality
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity
Reliability Assessment of Many-Core Dynamic Thermal Management
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness
Gain and slew rate enhancement for amplifiers through current starving and feeding
Power Efficient Approximate Booth Multiplier
A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS
A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level
Antenna-array 2D-IIR digital filters for carrier-modulated frequency-agile and cognitive wireless systems
Delay bound based CMOS gate sizing technique
Digital system for detection and classification of electrical events
Time-resolved reflectance using short source-detector separation
A Sub-Nanosecond Level Shifter with Ultra-High dV/dt Immunity Suitable for Wide-Bandgap Applications
Fast Sub-sampling Block Matching Algorithm Employing Adaptively Assigned Sizes and Locations of Search Windows
An optimal packetization scheme for fine granularity scalable bitstream
Real-time moving object tracking using phase-difference compensation and nonuniform pulse transmission
. Grazing bifurcations in periodic hybrid systems
Scene Retrieval from Multiple Resolution Generated Images Based on Text-to-Image GAN
A dual edge-triggered phase-frequency detector architecture
A Neural Network Based Calibration Technique for TI-ADCs with Derivative Information
Hardware implementation of all digital calibration for undersampling TIADCs
A High-Voltage Single-Inductor Multiple-Output DC-DC Buck Converter for the Power Management Unit of a Gate-Shaping Digital Gate Driver
Robust adaptive control of a class of nonlinear systems by internal model design
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
A Low-Noise, Low-Power Neural Signal Amplifier for Deep Brain Stimulation System Chips Tolerating 3V Stimulation
MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS
Bi-criterion optimization of non-uniform filter banks for acoustic echo cancellation
Noise Simulation and Modeling for MEMS Varactor Based RF VCOs
A Mathematical and Lumped-Element Model for Multiple Cascaded Lossy Transmission Lines with Arbitrary Impedances and Discontinuities
A Novel 2-Dimensional Correction Method for mm-Wave Cartesian I/Q Modulators
A generalized MIMO architecture for set-membership-based signal processing
An inverse filter realisation of a single scale Inverse continuous wavelet transform
A novel implementation scheme for high area-efficient DCT based on signed stochastic computation
A fault-aware dynamic routing algorithm for on-chip networks
CMOS Inductor Performance Estimation using Z- and S-parameters
Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder
Memory efficient architecture for belief propagation based disparity estimation
A new edge directed interpolation algorithm using accurate estimation of edge directional covariance
Pattern generation for Mutation Analysis using Genetic Algorithms
A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS
A successive approximation based process-invariant ring oscillator
Extraction and application of wiring symmetry rules to route analog multiport terminals
Implementation of SIMD vision chip with 128×128 array of analogue processing elements
Two Stage Step-Size Scaler Adaptive Filter Design for ECG Denoising
tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI
Live demonstration: An optimization software and a design case of a novel dual band wireless power and data transmission system
Multirate single-stage and multistage structures for high-speed recursive digital filtering
An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers
Empowering Traditional Carasau Bread Production Using Wireless Sensor Network
Design considerations of Ku-band high gain wideband CMOS power amplifier for FMCW radar application
Analysis and design of lumped-element quadrature couplers with lossy passive elements
Synthesis of Fault Tolerant Architectures for Molecular Dynamics
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
Efficient packet scheduling for scalable video delivery to mobile clients
Block Sequential CORDIC Architectures
Very Low Bit Rate Segmented Video Coding for Visual Telephony
A new highly-linear highly-sensitive differential voltage-to-time converter circuit in CMOS 65nm technology
A 0.2 dBm 225 GHz Frequency Quadrupler with 330° Phase Control in 130 nm SiGe BiCMOS
Information-processing-driven interfaces in hybrid large-area electronics systems
Derivation of two- and three-branch lumped element codirectional couplers and their frequency characteristics
Region and time based unequal error protection for video transmission over mobile links
An energy-efficient, dynamic voltage scaling neural stimulator for a proprioceptive prosthesis
A field deployable imaging system for detecting microplastics in the aquatic environment
Scalable Prediction Structure for Multiview Video Coding
The Determination of the Searching Sequence for VQ Encoding
An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode
A programmable gain amplifier buffer design for video applications
Convolutional networks and applications in vision
Efficient Gabor Filter Design Using Rician Output Statistics
Beyond ICA: robust sparse signal representations
Neuromorphic Computing Chips: Challenges and Trends
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor
ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator
Enhancing Security of Double Random Phase Encryption Schemes Based on Discrete Fractional Fourier Transforms
On the Filter Design for a Class of Multimode Transmultiplexers
Modelling the Effects of Early Exposure to Alcohol on the Excitability of Cortical Neurons
A LiDAR-assisted Smart Car-following Framework for Autonomous Vehicles
Live Demo of a Transient-Motion-Powered Human Motion Detector
Asynchronous pulse logic cell for threshold logic and Boolean networks
The Research of Stance-Phase Detection to Improve ZUPT-Aided Pedestrian Navigation System
Stability Analysis of High-order Modulators for Delta-Sigma ADCs
A high-speed, low latency RSA decryption silicon core
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path
A Conceptual Associative Memory with Full Memory Capacity and Ability to Associate Arbitrary Patterns
Performance evaluation of hierarchical NoC topologies for stacked 3D ICs
UV-Visible-NIR Image Sensor for Labeled and Label-free Intra-operative Imaging with Human Clinical Validation
A 230-nA Quiescent Current and Enhanced Transient Performance DC-DC Converter with Suppressed Under/Overshoot for IoT SoCs
Bidirectionally decodable Wyner-Ziv video coding
Domino ADC: A novel analog-to-digital converter architecture
Towards A Fully Integrated TES Controller Operating at 4K Temperature
On the robustness of vector set partitioning image coders to bit errors
A Ring Amplifier Architecture for Continuous-Time Applications
High-speed multiplier block design based on bit-level critical path optimization
Application of Pulsed Digital Oscillators in 'reverse mode' to eliminate undesired vibrations in high-Q MEMS resonators
A semi-Gray encoding algorithm for low-power state assignment
VLSI implementation of a hardware-optimized lattice reduction algorithm for WiMAX/LTE MIMO detection
The Opto-Electronic Transconductor and Its Applications
Remaining Useful Life Prediction of Lithium-Ion Batteries using Semi-Empirical Model and Bat-Based Particle Filter
A High Efficiency DC-DC Converter Architecture with Adjustable Switching Frequency to Suppress Noise Injection in RF Receiver Front-Ends
Computing the elements embedded into a positive feedback loop
U-shaped slow-wave transmission lines in 0.18μm CMOS
A study of exponential stability of multiple equilibria in delayed recurrent neural networks
Investigating the implications of outer hair cell connectivity using a silicon cochlea
An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]
Partial Diffusion Affine Projection Algorithm Over Clustered Multitask Networks
Efficient pipelined tunable heterodyne notch filter implementation in FPGAs
Fuzzy logic and additive wavelet based image fusion
On the effectiveness of noise reduction methods in DCSK systems
Hardware decoders for polar codes: An overview
A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation
Room-Temperature Dual-mode CMOS Gas-FET Sensor for Diabetes Detection
Placement for the reconfigurable datapath architecture
A robust fine granularity scalability using trellis based predictive leak
Integrated capacitor switchbox for security protection
Q-Enhancing Technique for High Speed Active Inductors
A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation
IIR Notch Filtering - Comparisons of Four Adaptive Algorithms for Frequency Estimation
Power efficient SAR ADC adaptive to input activity for ECG monitoring applications
Design of a radiation-tolerant high-speed driver for Mach Zender Modulators in High Energy Physics
Wide Dynamic Range Front-End Programmable Isolation Amplifier using Integrated CMOS Hall Effect Sensor
Peak-to-average power-ratio reduction algorithms for OFDM systems via constellation extension
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access
Digital Integrator Design Using Recursive Romberg Integration Rule and Fractional Sample Delay
Low-noise biasing of voltage-controlled oscillators by means of resonant inductive degeneration
Qualitative dynamics of the boost converter
A Hybrid Instruction and Functional Level Energy Estimation Framework for Embedded Processors
CMOS readout and control architecture for single-cell real-time microsystems
Design and Analysis of Isolated Voltage-Mode Memristor Cellular Nonlinear Network Cells
UMTS/GSM multi mode receiver design
Closed form design of prototype filters for linear phase DFT polyphase filter banks
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs
Current-slope-controlled adaptive-on-time DC-DC converter with fixed frequency and fast transient response
CNN Model with Transfer learning and Data Augmentation for Obstacle Detection in Rail Systems
Short segment automatic language identification using a multifeature-transition matrix approach
Static Noise Margin and Soft-Error Rate Simulations for Thin Film Transistor Cell Stability in a 4 Mbit SRAM Design
Qualitative Analysis of Hopfield Neural Nets with Delays: Global and Local Results
A computationally efficient DAB bit-stream processor
Multi-agent design for power distribution system reconfiguration based on the artificial immune system algorithm
A 0.7-V and 10-nA CMOS-Only Voltage Reference with 1-mA Load Driving Capability Based on Gate-Voltage Compensation Loop
A compact low-power vertical filter for very-high-frequency applications
A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications
Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique
Read-out circuit in RT-fluxgate
Device degradation and resilient computing
An eigenvalue formulation for determining initial conditions of induction machines in dynamic power system simulations
Performance analysis of high-speed MOS transistors with different layout styles
Reduced-rank antenna selection for MIMO DS-CDMA channels
Design and application of allpass filters with equiripple group delay errors
Characterization of Sub-Nyquist TIA with Equalization in Optical Receivers
On the Design of Digital Control for Lab-on-chip Systems
Wireless brain computer interfaces enabling synchronized optogenetics and electrophysiology
Computing on silicon with trigger waves: experiments on CNN-UM chips
Toward nanoelectronic systems integration
Live demonstration: A dynamic vision sensor with direct logarithmic output and full-frame picture-on-demand
Class-E CMOS power amplifiers for RF applications
ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX Monitoring
Triple-Mode Low-Power 20 Gb/s SST Driver for Short Reach Interconnects
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate
Reconfigurable multiple scan-chains for reducing test application time of SOCs
A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse
A genetic approach to the design space exploration of superscalar microprocessor architectures
Dynamics of a bandpass sigma-delta modulator as a piecewise isometry
Stability analysis and design methodology for an Åkerberg-Mossberg filter
Analog filter adaptation using a dithered linear search algorithm
Third-generation and beyond (3.5G) wireless networks and its applications
Event-based Plane-fitting Optical Flow for Dynamic Vision Sensors in FPGA
A Chopped Ultra-Low-Power, Low-Noise Wearable EEG Amplifier with Pseudo-Resistor Calibration
Secret Sharing Enabling Multi-Operations on FPGA Design for Multi-party Computation in Storage Systems
A silicon olfactory bulb oscillator
SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance
CMOS Image Compression Sensor with Algorithmically-multiplying ADCs
Three-Level Output Side Gate Driver for 1 V Thin-Gate-Oxide NMOSFET Switch in a SIDO Converter
Power and delay analysis of 4: 2 compressor cells
A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation
2-D non-separable paraunitary matrices and Grobner bases
A new modified nodal analysis for nano-scale memristor circuit simulation
A Low-Power Neuromorphic CMOS Delta-Sigma Modulator Featuring Tunable Background Attenuation and Potentiostatic Asynchronous Readout for Smart Amperometric Electrochemical Sensors
A backpropagation learning framework for feedforward neural networks
OpenSpike: An OpenRAM SNN Accelerator
A Wireless Headstage Based on a 32-Channel Neuromodulator Integrated Circuit
Device engineering and CMOS integration of nanoscale memristors
A Pipelined Systolic Arrays Architecture for the Hierarchical Block-Matching Algorithm
Design of 2-D Allpass Digital Filters For Delay Equalisation
Hybrid modelling of the general middle-sized genetic regulatory networks
A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology
A 9.2-Gram Fully-Flexible Wireless Dry-Electrode Headband for Non-Contact Artifact-Resilient EEG Monitoring and Programmable Diagnostics
Implementation of Bayesian Fly Tracking Model using Analog Neuromorphic Circuits
Novel adaptive soft input soft output demodulator for serially concatenated CPM signals
A massively parallel algorithm for local binary pattern based face recognition
130nm Low power asynchronous AES core
Blind electromagnetic source separation and localization
Optimal periodic sampling sequences for nearly-alias-free digital signal processing
A new synchronous mirror delay with an auto-skew-generation circuit
A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI
Smart Clothing using Antenna and Memristive ANN
Efficient and Lightweight Quantized Compressive Sensing using μ-Law
A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network
Design of a low-power, implantable electromyogram amplifier
An Electrode-Impedance-Aware Neurostimulator ASIC That Achieves Low-Power Consumption and Fast Charge Balancing
A Flexible Printed Radio Frequency Direction Finder Using Carbon Nanotube Field Effect Transistors
A concurrent multi-band LNA for multi-standard radios
MPEG-4 HVXC encoder realtime implementation on floating point DSP
Error Probability Models to Facilitate Approximate Computing in TFET based Circuits
CapPUF: A Tamper-Resistant PUF Utilizing I/O Capacitances for IoT Nodes
The 2-D Modulated Discrete Fourier Transform for 2-D fast convolution and digital filtering
Wave digital simulation of electrical networks containing nonlinear dynamical elements-a new approach
A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system
Assessing the Reusability of Cloud-Received Feature Streams on Advanced Networks
Leveraged current mirror op amp
Error Analysis of Parallel Analog to Digital Converters
A Single-Point, Auto-Calibration Technique For PTAT/CTAT Resistance Based Current References
An ultra-fast parallel architecture using sequential circuits computing on random bits
Stochastic Interpolation Model Scheme for Statistical Circuit Design
Synthesis of continuous-time linear systems with minimum L 2 -sensitivity
An efficient DFT-based algoritiim for the charger noise problem in capacitive touch applications
Analysis and synthesis of signal set with constrained magnitude spectrum
An adaptive notch filter for eliminating multiple sinusoids with reduced bias
A high-accuracy temperature sensor with second-order curvature correction and digital bus interface
Efficient interconnect timing analysis via piecewise linear technique
Music to Dance: Motion Generation Based on Multi-Feature Fusion Strategy
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits
FPGA implementation of a demux based on a multirate filter bank
Implementation of a motion sickness evaluation system based on EEG spectrum analysis
Compact and High-speed Hardware Architectures for Hash Function Tiger
Closed-Form Analysis of Metastability Voltage in 28 nm UTBB FD-SOI CMOS Technology
The emerging JPEG-2000 security (JPSEC) standard
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part II - FPGA Implementation
Battery-less modular responsive neurostimulator for prediction and abortion of epileptic seizures
Synthesis of Asynchronous Circuits - Testing Unique Circuit Behavior of Signal Transition Graphs
Optimal allocation of FACTS devices to enhance total transfer capability using evolutionary programming
Capacity bounds for the 2-user Gaussian IM-DD optical multiple-access channel
High-Accuracy Stress Detection Using Wrist-Worn PPG Sensors
Design of a class of maximally-flat spatial filters
Incorporating Back Telemetry in a Full-Wave CMOS Rectifier for RFID and Biomedical Applications
A routing method using chaotic neurodynamics for the transportation networks with the next generation vehicles
Magnetic (RL-) multivibrator using transconductance amplifier
Parallel boolean matrix multiplication in linear time using rectifying memristors
Multiplexed Detection of Spike Patterns using Active Graphene Neurosensors
A Correlated Double Sampling Technique for Charge-Sensitive Amplifiers based on TFTs
A spur-reduction frequency synthesizer for WIMAX applications
A CMOS distributed amplifier with current reuse optimization
Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent
Constant-time discontinuity map for forward sensitivity analysis to initial conditions: Spurs detection in fractional-N PLL as a case study
A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL
A general theory of third-order intermodulation distortion in common-emitter radio frequency circuits
A sensor array for phase and amplitude detection of synchronous modulated light sources
A compact CMOS 2 V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9 GHz RF transmitter applications
Random Undersampling Wireless EEG Measurement Device using a Small TEG
Accurate rise time and overshoots estimation in RLC interconnects
Performance-driven design of high speed receivers for wireless indoor networks
Semantic Segmentation on Compressed Video using Block Motion Compensation and Guided Inpainting
Dynamical hysteresis neural networks for graph coloring problem
Analytic approach to or transformations for FET circuit synthesis. Part I. Nullator-norator tree transformations
Security Vulnerabilities of Obfuscated Analog Circuits
A 2.6nW, 0.5V, 52dB-DR, 4 th -order Gm-C BPF: Moving closer to the FoM's fundamental limit
A Real-Time Digital Baseband MIMO Channel Emulation System
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation
A new approximation theory for Z-domain elliptic transfer functions
Learned Hierarchical B-frame Coding with Adaptive Feature Modulation for YUV 4: 2: 0 Content
A Stacked-Inverter Ring Oscillator for 50 mV Fully-Integrated Cold-Start of Energy Harvesters
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O
An IR-UWB transmitter with digital pulse duration control
Efficient computation of the sensitization probability of a critical path considering process variations and path correlation
All-MOS subthreshold log filters
A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider
Self-calibration of gain and output match in LNAs
Low-power CMOS circuit techniques for motion estimators
Efficient and fully scalable encryption for MPEG-4 FGS
Self organizing map based channel prediction for OFDMA
Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform
A 65-nm CMOS 1.4-nW Self-Controlled Dual-Oscillator-Based Supply Voltage Monitor for Biofuel-Cell-Combined Biosensing Systems
Using condition flag prediction to improve the performance of out-of-order processors
Proxy Circuits for Fault-Tolerant Primitive Interfacing in Reconfigurable Devices Targeting Extreme Environments
An RS (255, 239) Decoder with e-PIBM Algorithm, 25.6Gb/s Throughput and 623 TSNT FoM Value Using Fractional Folding Technique in 40nm Technology
Tracking instantaneous frequency using two-sided linear prediction
A 0.7-V, 192 pA Current Reference with 0.51%/V Line Regulation for Ultra-Low Power Applications
On various low-hardware-complexity LMS algorithms for adaptive I/Q correction in quadrature receivers
A Min-Max Optimization Framework for Multi-task Deep Neural Network Compression
Circuit implementation of floating point range reduction for trigonometric functions
Super-resolution technique for thermography with dual-camera system
StawGAN: Structural-Aware Generative Adversarial Networks for Infrared Image Translation
Voltage-Source Parallel Resonant Class E Oscillator
A clock recovery circuit using half-rate 4×-oversampling PD
A preamplifier IC design for photonic links
Modeling and verification of a programmable mixed-signal device using Verilog
Boundary filters with maximum coding gain and ideal DC behavior for size-limited paraunitary filter banks
Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system
A single-phase three-level boost type rectifier
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop
Sub-1 V Output-Capacitor-Less Low-Dropout Regulator with Two Compensation Amplifiers for Enhanced Power Supply Rejection
Linear low-frequency filter using on-chip giga-ohm resistance
A probabilistic reasoning approach to closed-room people monitoring
Combined Reinforcement Learning via Artificial Potential Field: A Case Study in Pommerman
A Low Power 16-bit 125MS/s Pipeline ADC with 100dB SFDR
Portable array biosensors
SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications