yusuke1997/dblp-id-title huggingface dataset:
A 28GHz 20.3%-Transmitter-Efficiency 1.5°-Phase-Error Beamforming Front-End IC with Embedded Switches and Dual-Vector Variable-Gain Phase Shifters
16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz
TD: Trends in Wireless Systems
An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOS
3.2 The A100 Datacenter GPU and Ampere Architecture
A bitline sense amplifier for offset compensation
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization
16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection
12.4 A 7.5W-output-power 96%-efficiency capacitor-free single-inductor 4-channel all-digital integrated DC-DC LED driver in a 0.18μm technology
A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range
F2: Data-converter calibration and dynamic-matching techniques
A 0.5mΩ/√Hz 106dB SNR 0.45cm2 Dry-Electrode Bioimpedance Interface with Current Mismatch Cancellation and Boosted Input Impedance of 100MΩ at 50kHz
Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS
A 37.6mm 2 1024-channel high-compliance-voltage SoC for epiretinal prostheses
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS
12.4 A 19μW 200Mb/s loT Tag Demonstrating High-Definition Video Streaming via a Digital-Switch-Based Reconfigurable 16-QAM Backscatter Communication Technique
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity
A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop
35.3 A 30MHz Wideband 92.7dB SNR 99.6% Accuracy Bioimpedance Spectroscopy IC Using Time-to-Digital Demodulation with Co-Prime Delay Locked Sampling
A 460W Class-D output stage with adaptive gate drive
CMOS Electro-Chemical DNA-Detection Array with On-Chip ADC
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band
8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor
F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors
Session 24 overview: GaN drivers and converters: Power management subcommittee
Session 27 Overview: Discrete-Time ADCs Data Converters Subcommittee
18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme
A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS
A Wireless Adiabatic Stimulator System with Current-Mode Power Reception and Stimulus Current Regulation Achieving Precise Charge Delivery and Electrode Scalability for Miniaturized Electroceuticals
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells
A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming
mm-Wave Tranceivers and Building Blocks
Nyquist ADC Techniques
4.7 A 2.1Mpixel organic-film stacked RGB-IR image sensor with electrically controllable IR sensitivity
9.6 A 3.9kHz-frame-rate capacitive touch system with pressure/tilt angle expressions of active stylus using multiple-frequency driving method for 65″ 104×64 touch screen panel
A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS
29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme
20.2 A 67μW/Channel, 0.13nW/Synapse/b Nose-on-a-Chip for Noninvasive Diagnosis of Diseases with On-Chip Incremental Learning
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels
A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation
20.3 A 4.0×3.7×1.0mm 3 -MEMS CMOS Integrated E-Nose with Embedded 4×Gas Sensors, a Temperature Sensor and a Relative Humidity Sensor
A 52% Peak-Efficiency >1W Isolated Power Transfer System Using Fully Integrated Magnetic-Core Transformer
A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS
7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration
A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS
23.1 A 4GS/s 80dB DR Current-Domain Analog Front-End for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive LiDAR
17.7 A packaged 90-to-300GHz transmitter and 115-to-325GHz coherent receiver in CMOS for full-band continuous-wave mm-wave hyperspectral imaging
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU
An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators
25.7 A 2.4GHz 4mW inductorless RF synthesizer
A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion time
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface
1.1 Unleashing the Future of Innovation
A Digital-Type GaN Driver with Current-Pulse-Balancer Technique Achieving Sub-Nanosecond Current Pulse Width for High-Resolution and Dynamic Effective Range LiDAR System
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC
4.2 A fully integrated CMOS fluorescence biochip for multiplex polymerase chain-reaction (PCR) processes
A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS
34.5 A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers
An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor
A 128×2 CMOS Single-Photon Streak Camera with Timing-Preserving Latchless Pipeline Readout
Power-efficient readout circuit for miniaturized electronic nose
25.1 A fully integrated 0.55THz near-field sensor with a lateral resolution down to 8µm in 0.13µm SiGe BiCMOS
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection
A 38Mb/mm 2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology
An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners
A 400 μW 4.7-to-6.4GHz VCO under an Above-IC Inductor in 45nm CMOS
A millimeter-wave intra-connect solution
21.8 A pulling mitigation technique for direct-conversion transmitters
SE6 Secure Digital Systems
A 0.06mm 2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS
A global-shutter CMOS image sensor with readout speed of 1Tpixel/s burst and 780Mpixel/s continuous
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS
70GHz CMOS Harmonic Injection-Locked Divider
A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5°C (3 σ) from -40 to 105°C
4.5 A 2-phase resonant switched-capacitor converter delivering 4.3W at 0.6W/mm 2 with 85% efficiency
A 200Mb/s inductively coupled wireless transcranial transceiver achieving 5e-11 BER and 1.5pJ/b transmit energy efficiency
A 390Mb/s 3.57mm 2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS
A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS
MEMS for Frequency Synthesis and Wireless RF Communications (or Life without Quartz Crystal)
28.5 A 0.6V/0.9V 26.6-to-119.3µW ΔΣ-Based Bio-Impedance Readout IC with 101.9dB SNR and <0.1Hz 1/f Corner
A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS
3.2 A 0.028mm² 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from -40°C to 125°C and ±1600ppm Inaccuracy After Accelerated Aging
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV
An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL
A 0.2°/hr Micro-Gyroscope with Automatic CMOS Mode Matching
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan
13.7 A +10dBm 2.4GHz transmitter with sub-400pW leakage and 43.7% system efficiency
A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process
23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement
A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation
A single-inductor 0.35µm CMOS energy-investing piezoelectric harvester
A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting G m Boosting
18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor
Session 25 overview: GaN drivers and galvanic isolators
A simple LED lamp driver IC with intelligent power-factor correction
A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency
TD: Emerging Devices Devices and Circuits
3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI
Session 9 Overview: ML Processors From Cloud to Edge Machine Learning Subcommittee
17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking
17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation
Session 27 overview: Data converter techniques: Data converters subcommittee
Minimally Invasive Retinal Prosthesis
10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise
A 2.75mW wideband correlation-based transceiver for body-coupled communication
13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology
Creating neural "co-processors" to explore treatments for neurological disorders
21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system
A compact CMOS MEMS microphone with 66dB SNR
A 60V capacitive gain 27nV/√Hz 137dB CMRR PGA with ±10V inputs
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme
A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver
VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration
A 200MHz 300ps 0.5pJ/ns optical pulse generator array in 0.35µm CMOS
SOLI: A Tiny Device for a New Human Machine Interface
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS
Jaguar: A next-generation low-power x86-64 core
32.4 A 67.8-to-108.2GHz Power Amplifier with a Three-Coupled-Line-Based Complementary-Gain-Boosting Technique Achieving 442GHz GBW and 23.1% peak PAE
SC1: Circuits for the internet of everything
Vision for future television
A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization
EE2: Workshop on circuits for social good
A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers
EE1: Class of 2025 - Where will be the best jobs?
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass
A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power
A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS
10.1 A 77GHz Hybrid TDMA-MIMO Phased-Array Radar with 186m Detection Range and 3cm Range Resolution
A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters
A 56-to-65GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90nm CMOS
6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices
Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems
A 13 th -order CMOS reconfigurable RF BPF with adjustable transmission zeros for SAW-less SDR receivers
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface
Computational imaging
A CMOS-SOI 2.45GHz Remote-Powered Sensor Tag
A 172mm 2 32Gb MLC NAND flash memory in 34nm CMOS
A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS
Future of High-Speed Transceivers (Forum)
15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips
7.5 A 0.3mm-resolution Time-of-Flight CMOS range imager with column-gating clock-skew calibration
A 24-to-30GHz Double-Quadrature Direct-Upconversion Transmitter with Mutual-Coupling-Resilient Series-Doherty Balanced PA for 5G MIMO Arrays
Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure
27.8 A 4600μm 2 1.5°C (3σ) 0.9kS/s thermal-diffusivity temperature sensor with VCO-based readout
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency
2.5 A high-efficiency multiband Class-F power amplifier in 0.153µm bulk CMOS for WCDMA/LTE applications
26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique
A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution
A low-power true random number generator using random telegraph noise of single oxide-traps
15.7 Heterogeneous integrated CMOS-graphene sensor array for dopamine detection
An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays
A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput
1.1 The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming
A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz
20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput
4.2 An E-Band High-Linearity Antenna-LNA Front-End with 4.8dB NF and 2.2dBm IIP3 Exploiting Multi-Feed On-Antenna Noise-Canceling and Gm-Boosting
5.5 A 2µW 40mVpp linear-input-range chopper- stabilized bio-signal amplifier with boosted input impedance of 300MΩ and electrode-offset filtering
A ΔΣ interface for MEMS accelerometers using electrostatic spring-constant modulation for cancellation of bondwire capacitance drift
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation
Biomedical Devices
Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing
An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL
A 62-to-68GHz linear 6Gb/s 64QAM CMOS doherty radiator with 27.5%/20.1% PAE at peak/6dB-back-off output power leveraging high-efficiency multi-feed antenna-based active load modulation
9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time
6.2 210ke- Saturation signal 3µm-pixel variable-sensitivity global-shutter organic photoconductive image sensor for motion capture
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability for FMCW Radar
A piecewise-linear 10b DAC architecture with drain-current modulation for compact AMLCD driver ICs
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec
13.5 A 4-antenna-path beamforming transceiver for 60GHz multi-Gb/s communication in 28nm CMOS
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
TV Tuner / RFID
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization
A 3.5GHz Rotary-Traveling-Wave-Oscillator Clocked Dynamic Logic Family in 0.25µm CMOS
19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot
A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS
A 9Mb HZO-Based Embedded FeRAM with 10 12 -Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier
A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and Testability
5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage
25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
A digitally controlled DC-DC buck converter with lossless load-current sensing and BIST functionality
A 5000S/s Single-Chip Smart Eye-Tracking Sensor
3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection
A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter
31.1 An 82mW ΔΣ - Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency
A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring
An 18b 12.5MHz ADC with 93dB SNR
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF
Brain-Inspired technologies: Towards chips that think?
26.7 A 10mm3 syringe-implantable near-field radio system on glass substrate
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency
Session 21 overview: Extending silicon and its applications: Technology directions subcommittee
A 65nm 63.3µW 15Mbps Transceiver with Switched-Capacitor Adiabatic Signaling and Combinatorial-Pulse-Position Modulation for Body-Worn Video-Sensing AR Nodes
A 2.19µW Self-Powered SoC with Integrated Multimodal Energy Harvesting, Dual-Channel up to -92dBm WRX and Energy-Aware Subsystem
13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor
12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution
15.1 Large-scale acquisition of large-area sensors using an array of frequency-hopping ZnO thin-film-transistor oscillators
A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider
A 0.0375mm 2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control
33.5 Closed-Loop 100-Channel Highly-Scalable Retinal Implant with 1.02μW Analog ED-Based Adaptive-Threshold Spike Detection and Poisson-Coded Temporally Distributed Optogenetic Stimulation
Session 4 overview: Processors: High-performance digital subcommittee
A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS
A scalable 2.9mW 1Mb/s eTextiles body area network transceiver with remotely powered sensors and bi-directional data communication
What is the next RF frontier?
A 4b ADC manufactured in a fully-printed organic complementary technology including resistors
A 110V/230V 0.3W Offline Chip-Scale Power Supply with Integrated Active Zero-Crossing Buffer and Voltage-Interval-Based Dual-Mode Control
A 3-to-40V VIN 10-to-50MHz 12W isolated GaN driver with self-excited tdead minimizer achieving 0.2ns/0.3ns tdead, 7.9% minimum duty ratio and 50V/ns CMTI
A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC
14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector
An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
A 480Gb/s/mm 1.7pJ/b Short-Reach Wireline Transceiver Using Single-Ended NRZ for Die-to-Die Applications
SAW-less analog front-end receivers for TDD and FDD
A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver
8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time
16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm
26.9 A 0.19×0.17mm 2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry
A switched-capacitor power amplifier for EER/polar transmitters
4.4 A 10/30MHz Wide-duty-cycle-range buck converter with DDA-based Type-III compensator and fast reference-tracking responses for DVS applications
24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique
A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure
An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS
A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems
10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS
Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum)