yusuke1997/dblp-id-title huggingface dataset:
A Hierarchical Methodology for Word-Length Optimization of Signal Processing Systems
Static Malware Analysis using ELF features for Linux based IoT devices
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems
The Acceleration of OPUS Codec Using Processor - FPGA Co-processing
Formal Verification of Combinational Circuit
SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip
PIDISC: Pattern Independent Design Independent Seed Compression Technique
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header
Design Issues in Switched Capacitor Ladder Filters
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
Accurate Substrate Noise Analysis Based on Library Module Characterization
Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign
A Test Generator for Segment Delay Faults
Exploring the Limits of Port Reduction in Centralized Register Files
COST Circuit Optimization SysTem in ASIC Library Development Environment
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters
Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
4 GHz 130nm Low Voltage PLL Based on Self Biased Technique
Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications
Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs
Opto-VLSI Systems for Multimedia Computing
A Novel Approach to Domino Circuit Synthesis
Effective Liveness Verification Using a Transformation-Based Framework
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM
30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, January 7-11, 2017
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit
A Mechanism for Fine-Grain Concurrent Sharing of Design Data Among CAD Tools
Sequential Spectral ATPG Using the Wavelet Transform and Compaction
On the Transistor Sizing Problem
A Machine Learning Based Approach to Predict Power Efficiency of S-Boxes
VLSI Architecture for a Flexible Motion Estimation with Parameters
PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry
Quad Asynchronous Communication Element (ACE) with FIFO
A Novel RF Front-End Chipset For ISM Band Wireless Applications
DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency
Efficient Design and Analysis of Robust Power Distribution Meshes
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs
Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder
A Framework for Design Space Exploration of Parameterized VLSI Systems
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs
Small, Smart, Intelligent and Interactive Handheld Devices
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)
Invited Address: A Wireless Portable Video-On-Demand System
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining
Gate Leakage and Its Reduction in Deep Submicron SRAM
Accelerated Design Verification Coverage Closure Using Machine Learning
Synthesis of Symmetric Functions for Path-Delay Fault Testability
Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy?
The k-layer Topological Via Minimization Problem on a Circular Channel
Power Reduction Techniques and Flows at RTL and System Level
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters
An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes
Constrained Via Minimisation In Greedy Channel Routing
Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel
Freedom: Statistical Behavioral Estimation of System Energy and Power
Output-Dependent Diagnostic Test Generation
Living at the Edge
Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications
High Level Design Experiences with IDEAS
Detection and Generation of Self-Timed Pipelines from High Level Specifications
Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor
Register Transfer Level Synthesis: From Theory to Practice
Asynchronous Implementation of Synchronous Esterel Specifications
Energy Aware Software
ESL - The Next Leadership Opportunity for India?
Analysis of temperature dependence of Si-Ge HBT
Dictionary Based Code Compression for Variable Length Instruction Encodings
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA
An Improved Deductive Fault Simulator
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model
VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder
A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods
Characterizing Individual Gate Power Sensitivity in Low Power Design
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects
Designing Systems On Silicon: A Digital Spread Spectrum Pager
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits
A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface
A Novel Translinear Principle Based BiMOS Transconductor
Write Variation Aware Non-volatile Buffers for On-Chip Interconnects
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
Parallel simulated annealing strategies for VLSI cell placement
LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design
A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO Systems
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial
A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method
Is Compiled Simulation Really Faster than Interpreted Simulation?
Structured Construction of VLSI Circuits Using Adjacency Lists
Digital Testing - Basics to Advanced Research Issues
Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations
Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions
Low Power and Area Efficient Approximate 2D-DCT Architecture for Wireless Capsule Endoscopy
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits
Design of a VLSI Hardware PET Decoder
Estimation of Maximum Power-Up Current
Why is Design Automation and Reuse of Analog Designs Increasingly Trailing the Digital World?
A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization
Making Sense Out of the Potential Babble of Low Power Standards
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study
The Technological and Geographical Migration of the Semiconductor Industry
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories
A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI
E2GC: Energy-efficient Group Convolution in Deep Neural Networks
Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFET
Design Optimization and Automation for Secure Cryptographic Circuits
Genetic multiway partitioning
Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols
Transmission Line Modeling by Modified Method of Characteristics
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process
Ultra Fine-Grain Template-Driven Synthesis
Implementation of design functions by available devices: a new algorithm
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
Test-Vector Prediction of M-Testable Iterative Arrays
Performance Analysis of Systems with Multi-Channel Communication Architectures
Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops
Software-Only Bus Encoding Techniques for an Embedded System
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
Dynamic Power Optimization of Interactive Systems
FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing
Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network
System-Level Design of Embedded Media Systems (Tutorial Abstract)
Optimizing Medical Image Analysis: Leveraging Efficient Hardware and AI Algorithms
Throughput Efficient Parallel Implementation of SPIHT Algorithm
A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems
An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage
Low-Power Design Strategies for Mobile Computing
The New Electronics Industry
VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal Technique
A 55-mW 300MS/s 8-bit CMOS Parallel Pipeline ADC
Test generation for cyclic combinational circuits
Tutorial T1: Neuromorphic Computing - Algorithms, Devices and Systems
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study
New and Exact Filling Algorithms for Layout Density Control
Pre-mapping Algorithm for Heterogeneous MPSoCs
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio
Identification of Faulty TSVs in 3D IC During Pre-Bond Testing
Web-based Distributed VLSI Design
Embedded tutorial - Emerging memory technologies: What it means for computer system designers
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD)
Optimizing Quantum Circuits for Modular Exponentiation
A Shared Memory Parallel Algorithm for Logic Synthesis
Concurrent Optimization of Technology and Design for Nano CMOS
Automatic Implementation and Evaluation of Error-Correcting Codes for Quantum Computing: An Open-Source Framework for Quantum Error Correction
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
A Switch-Memory Chip for Packet Switching at Gigabits per Second
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization
Temperature Aware Scheduling for Embedded Processors
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology
Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM Applications
Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness
Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region
16-Bit Segmented Type Current Steering DAC for Video Applications
Analysis and Optimization of Enhanced MTCMOS Scheme
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
FARAD: Automated Formal Verification of Approximate Restoring Array Dividers
Coverage Management with Inline Assertions and Formal Test Points
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design
Design Challenges for High Performance Nano-Technology
A Fast Compact Thermal Model For Smart Phones
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications
Modular Design Methodologies for Image Processing Architectures
OTA Based Neural Network Architectures with On-Chip Tuning of Synapses
Clock-Skew Constrained Cell Placement
ADOPT: An Approach to Activity Based Delay Optimization
On Fault-Simulation Through Embedded Memories On Large Industrial Designs
Sequential Circuit Testing: From DFT to SFT
Efficient Online RTL Debugging Methodology for Logic Emulation Systems
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs
Low Power Extended Range Multi-Modulus Divider Using True-Single-Phase-Clock Logic
A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Receiver Frond End with Split TCAs in 180nm CMOS
A New Divide and Conquer Method for Achieving High Speed Division in Hardware
A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs
Modeling of RF- MEMS BAW Resonator
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs
Interfacing Cores with On-chip Packet-Switched Networks
RF System Design of an RFIC Receiver for IoT
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology
Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults
Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
Enhancing Output Corruption Through GSHE Switch Based Logic Encryption
Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25µm CMOS
An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs
Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
System-Level Point-to-Point Communication Synthesis using Floorplanning Information
FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation
Test-Time Reduction for Power-Aware 3D-SoC
Syndrome signature in output compaction for VLSI BIST
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver
A Low Power 6-Bit A/D Converter Achieving 10-Bit Resolution for MEMS Sensor Interface Using Time-Interleaved Delta Modulation
BEST: Bond Editor and Test Vector Translator
Noninvasive Cuffless Blood Pressure Measurement by Vascular Transit Time
Quantum Analysis of LESCA
Verification of Circuits Described in VHDL through Extraction of Design Intent
Board level fault diagnosis using cellular automata array
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D
Tutorial IND1B: Realtime Operating Systems for Embedded Systems Development
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults
Net Buffering in the Presence of Multiple Timing Views
Optimizing SoC Manufacturability
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
Switching-Time Dependent PUF Using STT-MRAM
Stepsize Control in Piecewise Approximate Circuit Simulation
Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
HapticGuide: Interactive Wearable Braille Guide for Enhancing Visual Education
A Novel Method to Improve the Test Efficiency of VLSI Tests
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage
On Test Scheduling for Core-Based SOCs
Interfacing Synchronous and Asynchronous Domains for Open Core Protocol
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption
CMOS Oscillator Having Stable Frequency with Process, Temperature and Voltage Variation
Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients
Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions
A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs
An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology
A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands
Performance Driven Optimization for MUX based FPGAs
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS
Parallel algorithms for single row routing in narrow streets
Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS
An Asynchronous Morphological Processor for Multi-Media Applications
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models
Exploring Scope of Power Reduction with Constrained Physical Synthesis
A new methodology for the design of low-cost fail safe circuits and networks
An Assertion Based Technique for Transistor Level Dynamic Power Estimation
Design Considerations and Implementation of a High Performance Dynamic Register File
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction
SHAKTI Processors: An Open-Source Hardware Initiative
A PC based Ultrasound back-end signal processor using Intel® Performance Primitives
Analyzing Hardware Security Properties of Processors through Model Checking
3.75ppm/ ° C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications
A Switch-Level Test Generation System
Optimizations for Behavioral/RTL Simulation
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters
Design and Implementation of Threshold Logic Functions Using Memristors
MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign
Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges
A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications
LUT-based FPGA Technology Mapping using Permissible Functions
Surviving the SOC Revolution: The Platform Approach to SOC Design
A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation
Global Routing Using Monotone Staircases with Minimal Bends
Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion
Generating Scalable Polynomial Models: Key to Low Power High Performance Designs
Design Considerations for BEOL MIM Capacitor Modeling in RF CMOS Processes
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead
Hardware Implementation of Blind Decoding of Downlink Control Information for 5G
EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs
VLSI in Mobile Communication
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software
Chip Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using Embedded Passives in a Silicon Package
Tutorial T8: Scheduling Issues in Embedded Real-Time Systems
HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract)
VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width
Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems
Low Power VLSI Signal Processing
Floorplanning in Modern FPGAs
Variance Reduction in Monte Carlo Capacitance Extraction
TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems
Novel Memory Bus Driver/Receiver Architecture for Higher Throughput
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability
Routing using implicit connection graphs [VLSI design
On the Use of Hash Tables for Efficient Analog Circuit Synthesis
Synthesis of Testable Pipelined Datapaths Using Genetic Search
Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined Networking
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
Architecture and Design of a High Performance SRAM for SOC Design
A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis
An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits
Applying River Formation Dynamics to Analyze VLSI Power Grid Networks
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements
On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective
Power and Energy Safe Real-Time Multi-Core Task Scheduling
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing
Embedded Hardware Face Detection
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology
Wear Leveling-Aware Active Battery Cell Balancing
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions