yusuke1997/dblp-id-title huggingface dataset:
Understanding Mobile Banking Usage: An Integrative Perspective
Extending a facility training program to include a minority skills training program
Bringing in the expert: Private consultant penetration into local governments
Quantifying the Digital Innovation Mindset: Development of a Measurement Instrument
Executive Dysfunction, Emotion Dysregulation, and IT Employee Burnout
Communication-aware scheduling of data-parallel tasks: work-in-progress
Control-theoretic dynamic frequency and voltage scaling for multimedia workloads
Towards Quality-Driven Approximate Software Generation for Accurate Hardware: Work-in-Progress
Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems
Optimizing inter-nest data locality
A fast and generic hybrid simulation approach using C virtual machine
PIFT: efficient dynamic information flow tracking using secure page allocation
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator
Compiler optimization of embedded applications for an adaptive SoC architecture
A novel compilation approach for image processing graphs on a many-core platform with explicitly managed memory
Evaluation of an accelerator architecture for speckle reducing anisotropic diffusion
Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010
Leakage-proof program partitioning
Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures
Fault-tolerant platforms for automotive safety-critical applications
Efficient architectures through application clustering and architectural heterogeneity
Automatic custom instruction identification in memory streaming algorithms
Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004
A memory interface for multi-purpose multi-stream accelerators
Balanced cache bypassing for critical warp reduction: work-in-progress
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs
Writing-aware data variable allocation on hybrid SRAM+NVM SPM: work-in-progress
A self-maintained memory module supporting DMM
SECA: security-enhanced communication architecture
A post-compilation register reassignment technique for improving hamming distance code compression
CGRA express: accelerating execution using dynamic operation fusion
A network agent for diagnosis and analysis of real-time Ethernet networks
Translating affine nested-loop programs to process networks
Adapting compilation techniques to enhance the packing of instructions into registers
Mighty-morphing power-SIMD
A low power architecture for embedded perception
A system-level simulation framework for evaluating task migration in MPSoCs
An empirical evaluation of high level transformations for embedded processors
Approximate acceleration: A path through the era of dark silicon and big data
Work-in-Progress: Temporal RegionDrop - Frame Difference Sparsity for Efficient Video Inference
Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet
Exploiting cache conflicts to reduce radiation sensitivity of operating systems on embedded systems
Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation
What do Transformers have to learn from Biological Spiking Neural Networks?
Incremental training of CNNs for user customization: work-in-progress
FastCollect: offloading generational garbage collection to integrated GPUs
Advanced ahead-of-time compilation for Javascript engine: work-in-progress
Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs
Light-weight primitive, feather-weight security: a cryptanalytic knock-out
Energy-aware probabilistic multiplier: design and analysis
Adaptive object code compression
Performance, energy, and reliability tradeoffs in replicating hot cache lines
Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system
Primer on Data in Quantum Machine Learning
Automatic floating-point to fixed-point conversion for DSP code generation
Low-overhead virtualization of mobile platforms
Syntax-driven implementation of software programming language control constructs and expressions on FPGAs
PAC: Program Analysis for Approximation-aware Compilation
Stochastic computing: embracing errors in architectureand design of processors and applications
Advanced conservative and optimistic register coalescing
Increasing the number of effective registers in a low-power processor using a windowed register file
Embedding SDL implemented protocols into DSP
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems
An accurate and efficient simulation-based analysis for worst case interruption delay
Cache leakage control mechanism for hard real-time systems
Recursive function data allocation to scratch-pad memory
Techniques for code and data management in the local stores of the cell processor
Quality-configurable memory hierarchy through approximation: special session
Function inlining and loop unrolling for loop acceleration in reconfigurable processors
Extensible control architectures
Design and implementation of a hierarchical exception handling extension to systemC
Control-layer optimization for flow-based mVLSI microfluidic biochips
Protected heap sharing for memory-constrained java environments
Work-in-Progress: Cooperative MLP-Mixer Networks Inference On Heterogeneous Edge Devices through Partition and Fusion
Supporting precise garbage collection in Java Bytecode-to-C ahead-of-time compiler for embedded systems
A high-level model of embedded flash energy consumption
Design space exploration for field programmable compressor trees
A control-theoretic approach to dynamic voltage scheduling
Optimus: efficient realization of streaming applications on FPGAs
Execution context optimization for disk energy
High-level power analysis for multi-core chips
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2024, Raleigh, NC, USA, September 29 - Oct. 4, 2024
Reaching fast code faster: using modeling for efficient software thread integration on a VLIW DSP
E < MC2: less energy through multi-copy cache
System lifetime extension by battery management: an experimental work
Equivalence checking of arithmetic expressions using fast evaluation
Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices
Energy-efficient instruction cache using page-based placement
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, Shanghai, China, October 7-14, 2022
Experience with a retargetable compiler for a commercial network processor
Balancing memory and performance through selective flushing of software code caches
CASES '21: Proceedings of the 2021 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Virtual Event, October 8 - 15, 2021
Heuristics for greedy transport triggered architecture interconnect exploration
Non-transparent debugging for software-pipelined loops
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis
Low cost multicast authentication via validity voting in time-triggered embedded control networks
CaffePresso: an optimized library for deep learning on embedded accelerator-based platforms
Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs
Power efficient branch prediction through early identification of branch addresses
Improving scratchpad allocation with demand-driven data tiling
Work-in-Progress: Towards a Smaller than Grain Stream Cipher: Optimized FPGA Implementations of Fruit-80
Tight WCRT analysis of synchronous C programs
Siblingrivalry: online autotuning through local competitions
Selective just-in-time compilation for client-side mobile javascript engine
A quantifiable approach to approximate computing: special session
High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
Hardware acceleration for programs in SSA form
Exposing non-standard architectures to embedded software using compile-time virtualisation
Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects
Advances and throwbacks in hardware-assisted security: special session
Micro embedded monitoring for security in application specific instruction-set processors
Instruction selection by graph transformation
Heterogeneous memory management for embedded systems
Automatic generation of application specific processors
Reducing code size with echo instructions
Challenges for embedded multicore architecture
Context-sensitive timing simulation of binary embedded software
Mitigating soft error failures for multimedia applications by selective data protection
Reducing both dynamic and leakage energy consumption for hard real-time systems
Algorithms for energy optimization using processor instructions
Secure protocols for serverless remote product authentication
Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers
Towards the design of fault-tolerant mixed-criticality systems on multicores
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
Implementing dynamic implied addressing mode for multi-output instructions
A first-step towards an architecture tuning methodology for low power
DRAM cache access optimization leveraging line locking in tag cache: work-in-progress
A low-entropy first-degree secure provable masking scheme for resource-constrained devices
Scalable subgraph mapping for acyclic computation accelerators
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress
Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications
Work-in-Progress: MLGOPerf: An ML Guided Inliner to Optimize Performance
A code generation framework for Java component-based designs
Auto-parallelization of data structure operations for GPUs
Establishing a tight bound on task interference in embedded system instruction caches
LOCUS: low-power customizable many-core architecture for wearables
WCET-driven branch prediction aware code positioning
Work-in-Progress:ACPO: An AI-Enabled Compiler Framework
Design, Model, and Explore Approximate Arithmetic Operators with AI/ML: A Tutorial
Energy efficient special instruction support in an embedded processor with compact isa
A preprocessing step for global loop transformations for data transfer optimization
Saving memory movements through vector processing in the DRAM
Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs
Work-in-Progress: High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage
Unroll-and-jam for imperfectly-nested loops in DSP applications
Emerging (un-)reliability based security threats and mitigations for embedded systems: special session
A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC
Programming models and architectures for FPGA platforms
A dual-processor solution for the MAC layer of a software defined radio terminal
A platform for developing adaptable multicore applications
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
EPerf: energy-efficient execution of user-interactive event-driven applications: work in progress
Graphical user interface energy characterization for handheld computers
Validating software pipelining optimizations
A low-power parallel design of discrete wavelet transform using subthreshold voltage technology
Exploiting phase inter-dependencies for faster iterative compiler optimization phase order searches
Smart cache cleaning: energy efficient vulnerability reduction in embedded processors
Instruction generation and regularity extraction for reconfigurable processors
Scrubbing unit repositioning for fast error repair in FPGAs
Hardware-Aware Compilation and Simulation for In-Memory Computing
Performance modeling for data distribution in heterogeneous computing systems: work in progress
An efficient framework for dynamic reconfiguration of instruction-set customization
Region-based caching: an energy-delay efficient memory architecture for embedded processors
Exploring and predicting the architecture/optimising compiler co-design space
Vector-aware register allocation for GPU shader processors
Information theoretic models for signatures in VLSI power delivery systems
Persistence improvement for distributed cache with NVM based storage system: work-in-progress
Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA
Energy aware kernel for hard real-time systems
International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013, Montreal, QC, Canada, September 29 - October 4, 2013
Implementing virtual secure circuit using a custom-instruction approach
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
A joined architecture/compiler design environment for ASIPs
A group-based wear-leveling algorithm for large-capacity flash memory storage systems
Trusted sharing of intellectual property in electronic hardware design
ILP-based modulo scheduling for high-level synthesis
Scratch-pad memory allocation without compiler support for java applications
Real Java for real time - gain and pain
Negotiation of security services: a multi-criteria decision approach
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
A new correlation frequency analysis of the side channel
Verifiable annotations for embedded java environments
Reducing energy consumption of queries in memory-resident database systems
Supporting multithreading in configurable soft processor cores
Parallel saturating multioperand adders
Probabilistic arithmetic and energy efficient embedded signal processing
On Evaluation of On-chip Thermal Covert Channel Attacks
Code coverage and input variability: effects on architecture and compiler research
Optimizing energy to minimize errors in dataflow graphs using approximate adders
How compilers and tools differ for embedded systems
Side channel analysis of AVR XMEGA crypto engine
MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs
Work-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies
Disk drive energy optimization for audio-video applications
Architectural synthesis of flow-based microfluidic large-scale integration biochips
An evaluation of different modeling techniques for iterative compilation
Energy-oriented compiler optimizations for partitioned memory architectures
A new CRT-RSA algorithm resistant to powerful fault attacks
Combined partitioning and data padding for scheduling multiple loop nests
Erbium: a deterministic, concurrent intermediate representation to map data-flow tasks to scalable, persistent streaming processes
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2025, Taipei, Taiwan, September 28 - Oct. 3, 2025
Self-powered wearable sensor platforms for wellness
Proceedings of the Workshop on Embedded Systems Security, WESS 2013, Montreal, Quebec, Canada, September 29 - October 4, 2013
Non-intrusive dynamic application profiler for detailed loop execution characterization
Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee
Optimization of multi-channel BCH error decoding for common cases
A partitioning strategy for exploring error-resilience in circuits: work-in-progress
Efficient design space exploration in PICO
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
III-V/Si integration: potential and outlook for integrated low power micro and nanosystems
ILPc: A novel approach for scalable timing analysis of synchronous programs
A new method for compiling schizophrenic synchronous programs
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002
Porting new Versatile Video Coding transforms to a heterogeneous GPU-based technology
Fault resilient physical neural networks on a single chip
Towards efficient quantized neural network inference on mobile devices: work-in-progress
Team up: Cooperative memory management in embedded systems
Optimizing mobile display brightness by leveraging human visual perception
DaaC: device-reserved memory as an eviction-based file cache
Improved procedure placement for set associative caches
A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems
Power on demand for mobile computing devices
Memory overflow protection for embedded systems using run-time checks, reuse and compression
Incremental elaboration for run-time reconfigurable hardware designs
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2023, Hamburg, Germany, September 17-22, 2023
Work-in-Progress: Prediction-based Fine-Grained LDPC Reading to Enhance High-Density Flash Read Performance
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems
LLBT: an LLVM-based static binary translator
SCCP/x: a compilation profile to support testing and verification of optimized code
Stack bounds analysis for microcontroller assembly code
A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization
Power-performance modeling on asymmetric multi-cores
Design space exploration of the lightweight stream cipher WG-8 for FPGAs and ASICs
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures
Exploring the design space of LUT-based transparent accelerators
Efficient code caching to improve performance and energy consumption for java applications
Improving the quality of ring oscillator PUFs on FPGAs
Efficient pulsed-latch implementation for multiport register files: work-in-progress
Multiple approximate instances in neural processing units for energy-efficient circuit synthesis: work-in-progress
A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor
A high-performance FPGA accelerator for sparse neural networks: work-in-progress
Non-deterministic processors: FPGA-based analysis of area, performance and security
Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses
Enabling Energy-efficient AI Computing: Leveraging Application-specific Approximations : (Education Class)
Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2000, San Jose, California, USA, November 7-18, 2000
The virtual hospital: the emergence of telemedicine
WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System
Automatic performance model construction for the fast software exploration of new hardware designs
Energy-interference-free system and toolchain support for energy-harvesting devices
Dynamic scheduling of concurrent tasks with cost performance trade-off
A low power front-end for embedded processors using a block-aware instruction set
Neural network transformation under hardware constraints
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE
Bitcoin and the age of Bespoke Silicon
Hybrid network-on-chip architectures for accelerating deep learning kernels on heterogeneous manycore platforms
Efficient spill code for SDRAM
Platform-dependent code generation for embedded real-time software
Scheduling instruction effects for a statically pipelined processor
Multicore architectures
Intra-task scenario-aware voltage scheduling
Causality analysis of synchronous programs with delayed actions
Limitations of special-purpose instructions for similarity measurements in media SIMD extensions
Instruction cache locking inside a binary rewriter
Reducing cache leakage energy for hybrid SPM-cache architectures
Hardware compilation of sequential Ada
OPAIMS: open architecture precision agriculture information monitoring system
Clustered calculation of worst-case execution times
A cost-effective tag design for memory data authentication in embedded systems
A real-time digital-microfluidic platform for epigenetics
Software-directed power-aware interconnection networks
Providing time- and space- efficient procedure calls for asynchronous software thread integration
Spatial complexity of reversibly computable DAG
Side channel attacks and the non volatile memory of the future
ShiftQ: a bufferred interconnect for custom loop accelerators
Decoupled root scanning in multi-processor systems
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems
Static program analysis of embedded executable assembly code
A hybrid code compression technique using bitmask and prefix encoding with enhanced dictionary selection
A simplified java bytecode compilation system for resource-constrained embedded processors
Efficient compilation of ESTEREL for real-time embedded systems
Active control and digital rights management of integrated circuit IP cores
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques
Power agnostic technique for efficient temperature estimation of multicore embedded systems
Maximizing I/O throughput and minimizing performance variation via reinforcement learning based I/O merging for SSDs: work-in-progress
An integrated ARM and multi-core DSP simulator
A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs
Scalable custom instructions identification for instruction-set extensible processors
Work-in-Progress: DRAM-MaUT: DRAM Address Mapping Unveiling Tool for ARM Devices
Balancing design options with Sherpa
LNS architectures for embedded model predictive control processors
Code-size-aware mapping for synchronous dataflow graphs on multicore systems: work-in-progress
Methods for power optimization in distributed embedded systems with real-time requirements
Components for embedded software: the PECOS approach
Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB
Low Power Control Techniques For TFT LCD Displays
SAT to SAT-Hard Clause Translator
Runtime management of adaptive MPSoCs for graceful degradation
Fine-grain performance scaling of soft vector processors