yusuke1997/dblp-id-title huggingface dataset:
An on-line testable UART implemented using IFIS
A linear code-preserving signature analyzer COPMISR
Practical Considerations on ESD Testing
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Advanced test methods for SRAMs
System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
Power-up Self Auto Calibration of High Speed SAR Converter in a 22nm FD-SOI CMOS Process
WaferCap: Open Classification of Wafer Map Patterns using Deep Capsule Network
A Test Vector Inhibiting Technique for Low Energy BIST Design
Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios
Improving the accuracy of diagnostics provided by fault dictionaries
Scalability study of PSANDE: Power supply analysis for noise and delay estimation
Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
Innovative Practices on Software and Hardware based Silicon Debug/Fault Isolation
Forming multi-cycle tests for delay faults by concatenating broadside tests
Design Diversity for Concurrent Error Detection in Sequential Logic Circuts
Test generation techniques for sequential circuits
Fault simulation with test switching for static test compaction
Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue
Path selection based on static timing analysis considering input necessary assignments
Fault coverage of a long random test sequence estimated from a short simulation
Innovative practices session 9C DFT and data for diagnostics
Innovation Practices Track: Frontiers in Diagnosis and Debug
Invited paper: Yin and Yang of embedded sensors for post-scaling-era
IP Session on Chiplet: Design, Assembly, and Test
Low-cost diagnosis of defects in MCM substrate interconnections
Automatic Selection of Internal Observation Signals for Design Verification
Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits
A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators
A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications
An on-chip NBTI monitor for estimating analog circuit degradation
Cantilever Type Probe Card for At-Speed Memory Test on Wafer
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
Low Power Embedded Deterministic Test
Fast Self-Recovering Controllers
Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction
Test and Characterization of a Variable-Capacity Multilevel DRAM
Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs
P1450.1: STIL for the Simulation Environmen
Group delay measurement of frequency down-converter devices using chirped RF modulated signal
Test Complexity in the Semiconductor Landscape
A Flexible Path Selection Procedure for Path Delay Fault Testing
IC layout weak point effectiveness evaluation based on statistical methods
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor
From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1
Accurate jitter decomposition in high-speed links
On the design of at-speed testable VLSI circuits
Auxiliary State Machine Controlled Autonomous Design Verification Framework
An Efficient Methodology for Generating Optimal and Uniform March Tests
Exploring Model-based Failure Prediction of Passive Bio-electro-mechanical Implants
Test-cost optimization in a scan-compression architecture using support-vector regression
Estimation of reject ratio in testing of combinatorial circuits
A Low Overhead Checksum Technique for Error Correction in Memristive Crossbar for Deep Learning Applications
Easing the verification bottleneck using high level synthesis
Scan insertion criteria for low design impact
Ultrafast stimulus error removal algorithm for ADC linearity test
Characterization and All-Region Virtual-Source Modeling of 40 nm GaN HEMT Technology for High Frequency IC Design
Innovative practices session 11C: Advanced scan methodologies [3 presentations]
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method
A scheduling problem in test generation
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers
VTS 2004 Best Paper Award
High level synthesis of a Front End filter and DSP engine for analog to digital conversion - a case study
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression
Impact of parameter variations on FinFET faults
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
High efficient low cost EEPROM screening method in combination with an area optimized byte replacement strategy which enables high reliability EEPROMs
Speeding up behavioral test pattern generation using an algorithmic improvement
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs
Online soft-error vulnerability estimation for memory arrays
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
Innovative practices session 1C screening for layout sensitive defects
Multi-Parameter Optimization of mm-Wave Antenna Layout Using Hybrid Modeling and Incremental Model Learning
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management
Design for testability (DFT) for RSFQ circuits
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture
Frequency-based BIST for analog circuit testin
Spectrum-Based BIST in Complex SOCs
BIST-Aided Scan Test - A New Method for Test Cost Reduction
Innovation Practices Track: Security in Test and Test for Security
Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era
Dynamic docking architecture for concurrent testing and peak power reduction
Optimization of the IEEE 1687 access network for hybrid access schedules
Impact of behavioral modifications for testability
Sampling Techniques of Non-Equally Probable Faults in VLSI System
Capacitive Coupling Mitigation for TSV-based 3D ICs
Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise
Innovative practices session 3C hardware security
A multi-layered methodology for defect-tolerance of datapath modules in processors
At-speed interconnect testing and test-path optimization for 2.5D ICs
Fast path selection for testing of small delay defects considering path correlations
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions
The roles of controllability and observability in design for test
Self-heating thermal-aware testing of FPGAs
CNN-based Stochastic Regression for IDDQ Outlier Identification
A generic low power scan chain wrapper for designs using scan compression
On polynomial-time testable classes of combinational circuits
Accelerated online error detection in many-core microprocessor architectures
Special session 9B: New topic test facilities and infrastructure in Canada
A solution for the on-line test of analog ladder filters
Delay Fault Testing of Designs with Embedded IP Cores
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage
Security Verification and Secure Testing Solutions
BIST for Network-on-Chip Interconnect Infrastructures
Multiple Scan Chain Design for Two-Pattern Testing
AlN Sputtering Parameter Estimation Using A Multichannel Parallel DCT Neural Network
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?
Testability preserving Boolean transforms for logic synthesis
Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks
Iterative test-point selection for analog circuits
Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]
A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study
Using fault sampling to compute I DDQ diagnostic test set
CLP-based Multifrequency Test Generation for Analog Circuits
Output Hazard-Free Transition Delay Fault Test Generation
Special session 4A: Elevator talks
Obtaining High Fault Coverage with Circular BIST Via State Skipping
Improvement of analog circuit fault detectability using fault detection observers
Process variation oriented delay testing of SRAMs
Bounding Circuit Delay by Testing a Very Small Subset of Paths
Pattern generator card, emulation, and debug
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Keynote Address
Defect-oriented non-intrusive RF test using on-chip temperature sensors
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
Enhanced Resolution Jitter Testing Using Jitter Expansion
Runtime resource management for lifetime extension in multi-core systems
How Many Test Patterns are Useless?
Gate-oxide early-life failure identification using delay shifts
Modular Compactor of Test Responses
Panel 12C: Apprentice - VTS edition judging session
Combining IEEE Standard 1149.1 with reduced-pin-count component test
Synthesis for Arithmetic Built-In Self-Tes
MOSAIC: Collaborative Compute-in-Memory µArrays for Flexible and Scalable Deep Learning
An adaptive device impedance matching circuit
BIST Technique by Equally Spaced Test Vector Sequences
Test, Debug, and Repair for Chiplet-Based Designs
Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise Integration
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Special Session: Countering IP Security threats in Supply chain
An Efficient External Memory Test Solution: Case Study for HPC Application
Worst-case analysis for pseudorandom testing
Scan testing of latch arrays
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations
An All-Digital High-Precision Built-In Delay Time Measurement Circuit
Detection of Inter-Port Faults in Multi-Port Static RAMs
Artificial Intelligence Based High Power Calibration Method for RF Pulse Amplifiers
Adaptive test delivers wide range of sophisticated test solutions
Fault characterization of standard cell libraries using inductive contamination
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits
Multi-Modal Built-In Self-Test for Symmetric Microsystems
Improved power supply noise control for pseudo functional test
Algorithm to Architecture to RTL to GDSII: Incorporating Security into All Phases of SoC Design and Implementation Flow - Keynote
Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing
Power-down integrated circuit built-in self-test structures
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories
Scan Vector Compression/Decompression Using Statistical Coding
PCB Hardware Trojans: Attack Modes and Detection Strategies
Fault models and tests for Ring Address Type FIFOs
Special session: Recent developments in hardware security
Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design Level
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
Innovative practices session 9C: Yield improvement: Challenges and directions
Circuit Failure Prediction and Its Application to Transistor Aging
Diagnosis of Tunneling Opens
Small Delay Fault Model for Intra-Gate Resistive Open Defects
Data driven neural-based measurement discrimination for IC parametric faults diagnosis
Built-in current self-testing scheme (BICST) for CMOS logic circuits
Testing cross wire opens within complex gates
Integrating on-chip temperature sensors into DfT schemes and BIST architectures
Automated Observability Analysis for Mixed-Signal Circuits
Delay Defect Screening using Process Monitor Structures
Special session 4B: Panel: Testing and calibration for power management circuits
Use of CrossCheck test technology in practical applications
Delta Iddq for Testing Reliability
Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studies
33rd IEEE VLSI Test Symposium, VTS 2015, Napa, CA, USA, April 27-29, 2015
Supply Voltage Noise Aware ATPG for Transition Delay Faults
Validation and Test Problems for Cross Talk Noise
Innovation Practices Track: VLSI Functional Safety
Low-capture-power at-speed testing using partial launch-on-capture test scheme
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements
Machine Learning Based Calibration Techniques for ADCs: An Overview
Power supply noise control in pseudo functional test
Special session 12C: Young professionals in test - Town meeting
Static Compaction Techniques to Control Scan Vector Power Dissipation
Innovative Practices Track: Novel Methods for Validation and Test
Special Session: Closed Chassis Platform Debug of Compute Systems using the Functional Ubiquitous USB Type-C Receptacle
Power noise and its impact on production test and validation of SoC devices
Special session on machine learning: How will machine learning transform test?
HBIST: An approach towards zero external test cost
Diagnosis of Quantum Circuits in the NISQ Era
Internal I/O Testing: Definition and a Solution
An optimized BIST test pattern generator for delay testing
21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures
Semi-Supervised Root-Cause Analysis with Co-Training for Integrated Systems
Logic-AAA: Debug of Logic Failures with an on-ATE Expert System
Exploiting X-correlation in output compression via superset X-canceling
Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN?
Innovative practices on quality levels of A/MS devices
A Time Domain Method to Measure Oscillator Phase Noise
Transition delay fault testing of 3D ICs with IR-drop study
Improving CMOS open defect coverage using hazard activated tests
Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model
Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks
Test Methodology for Detecting Defect-Based Hold-Time Faults
Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs
Selecting the most relevant structural Fmax for system Fmax correlation
Sequential Decoders for Binary Linear Block ECCs
COMPACT: A Hybrid Method for Compressing Test Data
Parameter Estimation for a Model with Both Imperfect Test and Repair
Innovative practices on test in Japan
Validation and Test of Network Processors and ASICs
Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache
New Techniques for Deterministic Test Pattern Generation
Static Gate-Level Information Flow for Hardware Information Security with Bounded Model Checking
Board-level fault diagnosis using Bayesian inference
An iterative diagnosis approach for ECC-based memory repair
Design and performance of CMOS TSPC cells for high speed pseudo random testing
Test pattern generation system for delay faults using a high speed simulation processor 'SP'
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions
Power delivery dynamics and its impact on silicon validation
Generating deterministic unordered test patterns with counters
LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets
Consistently dominant fault model for tristate buffer nets
Automated test pattern generation for analog integrated circuits
Challenges of Mixed-Signal Board Design and Test
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
On-chip voltage-droop prediction using support-vector machines
Interconnect verification of multichip modules using boundary scan
Special Session: Delay Fault Testing - Present and Future
Defect-tolerant cache memory design
A design-for-testability expert system for silicon compilers
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
Will 0.1um Digital Circuits Require Mixed-Signal Testing
Identifying sequentially untestable faults using illegal states
LLMs for Hardware Security: Boon or Bane?
A novel pattern generator for near-perfect fault-coverage
Effective Design of Layout-Friendly EDT Decompressor
Special Session: Physically Flexible Devices for Health and Activity Monitoring: Challenges from Design to Test
Special session 4C: Hot topic 3D-IC design and test
Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures
Fault Simulation Model for i{DDT} Testing: An Investigation
Yield prognosis for fab-to-fab product migration
Revisiting shift register realization for ease of test generation and testing
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
Evaluating the Reliability of Supervised Compression for Split Computing
Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits
Code-modulated embedded test for phased arrays
Design of reduced testing for VLSI circuits based on linear code theory
Analyzing Crosstalk in the Presence of Weak Bridge Defects
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation
Controlling DPPM through Volume Diagnosis
Fault Modeling and Testing of ReRAM-based CAM Array
Sensitivity analysis of a radiation immune CMOS logic family under defect conditions
Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms
On the diagnosis of programmable interconnect systems: Theory and application
Innovative practices session 7C automotive quality assurance
ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips
Aging-resilient SRAM design: an end-to-end framework
Where We Might Stumble with Embedded-System Test
Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs
Innovative Design for Test in State-of-the-Art Analog Systems
Planar High Performance Ring Generators
Innovative practices session 1C: Innovative practices in RF test
Automated Selection of Signals to Observe for Efficient Silicon Debug
Testing and design for testability of BiCMOS logic circuits
Edge Computing Trends, Design and Test Challenges - Keynote
A mixed signal tester solution for: standards traceable AC calibration of analog modules
Multi Domain Test: Novel test strategy to reduce the Cost of Test
Abstraction-based relation mining for functional test generation
Fault modeling and testing of resistive nonvolatile-8T SRAMs
TAM Design and Optimization for Transparency-Based SoC Test
Static test compaction for transition faults under the hazard-based detection conditions
A design-for-test technique for switched-capacitor filters
Kernel Smoothing Technique Based on Multiple-Coordinate System for Screening Potential Failures in NAND Flash Memory
Short burst software transparent on-line MBIST
A Storage Based LBIST Scheme for Logic Diagnosis
Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems
On the Sensitivity of Analog Artificial Neural Network Models to Process Variation
Scalable and accurate estimation of probabilistic behavior in sequential circuits
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm
Estimating Power Supply Noise and its impact on path delay
Testing, Verification, and Diagnosis in the Presence of Unknowns
On A Software-Based Self-Test Methodology and Its Application
A Systematic DFT Procedure for Library Cells
Special session on BIST/calibration of A/MS devices
Memory-based embedded digital ATE
Thermal Modeling and Management Challenges in Heterogenous Integration: 2.5D Chiplet Platforms and Beyond
Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)
Detection of multiple faults in CMOS circuits using a behavioral approach
Experimental fault analysis of 1 Mb SRAM chips
Innovative Practices Track: Session 6 - Using AI to Address the Silicon Growth Curve
Incremental test pattern generation
Development of Energy Consumption Ratio Test
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA
Approximating Infinite Dynamic Behavior for DRAM Cell Defects
Deep Stalling using a Coverage Driven Genetic Algorithm Framework
Novel Approach to Clock Fault Testing for High Performance Microprocessors
Design for Consecutive Transparency of Cores in System-on-a-Chip
SNIFU: Secure Network Interception for Firmware Updates in legacy PLCs
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries
ZeroScreen: A Novel Structure for IC Reliability Screening at Time-Zero
STarS: a target switching algorithm for sequential test generation
Evaluation of test generation algorithms
Enhanced fault modeling for DRAM test and analysis
Critical hazard free test generation for asynchronous circuits
Semi-Formal Test Generation for a Block of Industrial DSP
Physical design for testability for bridges in CMOS circuits
Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages
Standard and ROM-based synthesis of FSMs with control flow checking capabilities
Minimal March Tests for Unlinked Static Faults in Random Access Memories
Reduction of Instantaneous Power by Ripple Scan Clocking
Special Session: Trustworthy Hardware-AI at the Cloud
Neural network diagnosis of IC faults
Special Session: STT-MRAMs: Technology, Design and Test
Testable Sequential Circuit Design: A Partition and Resynthesis Approach
Detecting I DDQ defective CMOS circuits by depowering
High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement
Algorithms for the design verification of bipolar array chips
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment
Fail data reduction for diagnosis of scan chain faults under transparent-scan
Adaptive test flow for mixed-signal ICs
On test generation for combinational circuits consisting of AND and EXOR gates
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
Workload-driven selective hardening of control state elements in modern microprocessors
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters
Testability of one dimensional ILAs under multiple faults
Classification of bridging faults in CMOS circuits: experimental results and implications for test