yusuke1997/dblp-id-title huggingface dataset:
Perception Computing-Aware Controller Synthesis for Autonomous Systems
Side-channel power analysis of XTS-AES
Fast STA prediction-based gate-level timing simulation
Formal Semantics of Synchronous SystemC
Dynamic partitioning of processing and memory resources in embedded MPSoC architectures
Architecture Exploration of NAND Flash-based Multimedia Card
Provably-Robust Runtime Monitoring of Neuron Activation Patterns
Low complexity FIR filters using factorization of perturbed coefficients
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits
Post-layout optimization of power and timing for ECL LSIs
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Analysis of NBTI effects on high frequency digital circuits
An integrated scratch-pad allocator for affine and non-affine code
A power-driven thermal sensor placement algorithm for dynamic thermal management
Advancing hardware security using polymorphic and stochastic spin-hall effect devices
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm
A Self-Tuning Cache Architecture for Embedded Systems
Digitalization in automotive and industrial systems
BOMIG: A Majority Logic Synthesis Framework for AQFP Logic
Heterogeneous Co-Simulation of Networked Embedded Systems
Using constraint logic programming in memory synthesis for general purpose computers
Adapting to adaptive testing
Intelligent Methods for Test and Reliability
Attack-resilient sensor fusion
Crosstalk Reduction in Area Routing
Retiming multi-rate DSP algorithms to meet real-time requirement
Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAs
Modular SoC integration with subsystems: the audio subsystem case
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
Low Power Analogue 90 Degree Phase Shifter
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique
Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS
Multi-disciplinary integrated design automation tool for automotive cyber-physical systems
The FORA European Training Network on Fog Computing for Robotics and Industrial Automation
Optimized scheduling of multi-IMA partitions with exclusive region for synchronized real-time multi-core systems
AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs
A Composable Design Space Exploration Framework to Optimize Behavioral Locking
Resistive configurable associative memory for approximate computing
Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit
Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture
Energy-efficient real-time task scheduling with task rejection
Virtual Gang Scheduling of Parallel Real-Time Tasks
RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization
A special-purpose compiler for look-up table and code generation for function evaluation
Panel Session - Who Is Closing the embedded software design gap?
EDA Tools for RF: Myth or Reality?
Design for Testability of Gated-Clock FSMs
Safety and Security Analysis of AEB for L4 Autonomous Vehicle Using STPA
ECM: Improving IoT Throughput with Energy-Aware Connection Management
DATE Panel: Chips of the Future: Soft, Crunchy or Hard?
Diagnosis of multiple arbitrary faults with mask and reinforcement effect
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs
Software annotations for power optimization on mobile devices
A Network Traffic Generator Model for Fast Network-on-Chip Simulation
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems
Designing Resilient Autonomous Systems with the Reflex Pattern
Agile Requirement Engineering for a Cloud System for Automated and Networked Vehicles
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors
High speed communications links for ASICs
Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification
Quantitative Evaluation in Embedded System Design: Predicting Battery Lifetime in Mobile Devices
Cross-Level Hierarchical High-Level Synthesis
Synthesis of Fault-Tolerant Reconfigurable Scan Networks
Is Approximation Universally Defensive Against Adversarial Attacks in Deep Neural Networks?
Hybrid Token Selector based Accelerator for ViTs
Full-Chip Multilevel Routing for Power and Signal Integrity
Power management trends in portable consumer applications
Channel-Based Behavioral Test Synthesis for Improved Module Reachability
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning
New static compaction techniques of test sequences for sequential circuits
Improving scalability of CMPs with dense ACCs coverage
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms
Hardware-assisted code obfuscation for FPGA soft microprocessors
Wafer-Level Adaptive Vmin Calibration Seed Forecasting
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface
Fast controllers for data dominated applications
Analyzing Real-Time Systems
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems
A BIST approach to delay fault testing with reduced test length
Online Scheduling for Block-Partitioned Reconfigurable Devices
An efficient NBTI-aware wake-up strategy for power-gated designs
Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency
Multi-level phase analysis for sampling simulation
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction
Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems
Formal verification of sequential Galois field arithmetic circuits using algebraic geometry
Deep Positron: A Deep Neural Network Using the Posit Number System
Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems
A spatio-temporal fractal model for a CPS approach to brain-machine-body interfaces
StreamFTL: Stream-level address translation scheme for memory constrained flash storage
Architecture of ring-based redundant TSV for clustered faults
Incorporating graceful degradation into embedded system design
Long-term Continuous Assessment of SRAM PUF and Source of Random Numbers
MicroNAS: Zero-Shot Neural Architecture Search for MCUs
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip
Hardware implementation of a Reed-Solomon soft decoder based on information set decoding
DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators
Predictive models for multimedia applications power consumption based on use-case and OS level analysis
The split register file
Address Bus Encoding Techniques for System-Level Power Optimization
FLAMES: A Fuzzy Logic ATMS and Model-based Expert System for Analog Diagnosis
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories
Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoring
Design and selection of buffers for minimum power-delay product
Ternarized TCN for $\mu \mathrm{J}/\text{Inference}$ Gesture Recognition from DVS Event Frames
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Built-in self-test and characterization of polar transmitter parameters in the loop-back mode
Practical evaluation of code injection in encrypted firmware updates
Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis
ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization
A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces
Learning to infer: RL-based search for DNN primitive selection on Heterogeneous Embedded Systems
A secure scan design methodology
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits
Technology-aware logic synthesis for ReRAM based in-memory computing
Models for deterministic execution of real-time multiprocessor applications
NOCEVE: Network on chip emulation and verification environment
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits
Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Platform Based Design for Automotive Sensor Conditioning
eF 2 lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks
SmartCap: user experience-oriented power adaptation for smartphone's application processor
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms
Differential Power Analysis enhancement with statistical preprocessing
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits
Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing Systems
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
LowGradQ: Adaptive Gradient Quantization for Low-Bit CNN Training via Kernel Density Estimation-Guided Thresholding and Hardware-Efficient Stochastic Rounding Unit
AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Accelerate Hardware Logging for Efficient Crash Consistency in Persistent Memory
EMC-aware design on a microcontroller for automotive applications
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
A Constraint Network Based Approach to Memory Layout Optimization
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores
High-quality sub-function construction in functional decomposition based on information relationship measures
An industrial case study of low cost adaptive voltage scaling using delay test patterns
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
A software update service with self-protection capabilities
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection
BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs
MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing
InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting
Low-Rank Compression for IMC Arrays
Analog circuit topological feature extraction with unsupervised learning of new sub-structures
Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips
Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques
CRONuS: Circuit Rapid Optimization with Neural Simulator
AUTOSAR and the automotive tool chain
CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming
A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing
TypeCNN: CNN Development Framework With Flexible Data Types
Amplitude demodulation-based EM analysis of different RSA implementations
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain
Timing simulation of interconnected AUTOSAR software-components
The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor
Joint DNN Partition and Thread Allocation Optimization for Energy-Harvesting MEC Systems
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs
Exact Synthesis Based on Semi-Tensor Product Circuit Solver
Super-Efficient Super Resolution for Fast Adversarial Defense at the Edge
Learning early-stage platform dimensioning from late-stage timing verification
Verification of a Complex SoC: The PRO3 Case-Study
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
The ARTEMIS cross-domain architecture for embedded systems
Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count
SERICO: Scheduling Real-Time I/O Requests in Computational Storage Drives
A Middleware Journey from Microcontrollers to Microprocessors
Global Wire Bus Configuration with Minimum Delay Uncertainty
Error prediction based on concurrent self-test and reduced slack time
Formal Verification of the Pentium ® 4 Floating-Point Multiplier
Energy efficient video fusion with heterogeneous CPU-FPGA devices
An Approach to Model Checking for Nonlinear Analog Systems
Machine learning-based volume diagnosis
Breaking the energy barrier in fault-tolerant caches for multicore systems
Optimal High-Resolution Spectral Analyzer
Hardware-Assisted Malware Detection using Machine Learning
Energy-efficient scheduling for memory-intensive GPGPU workloads
Meeting Delay Constraints in DSM by Minimal Repeater Insertion
A sub-μ a power management circuit in 0.18μ m CMOS for energy harvesters
A Graph Based Processor Model for Retargetable Code Generation
On the statistical memory architecture exploration and optimization
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA
Low power aging-aware register file design by duty cycle balancing
Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving
ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs
On Analog Signature Analysis
Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems
DWR: Differential Wearing for Read Performance Optimization on High-Density NAND Flash Memory
An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems
Domain specific model driven design for automotive electronic control units
Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints
A Flash-based Current-mode IC to Realize Quantized Neural Networks
FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian Splatting
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Impact of steep-slope transistors on non-von Neumann architectures: CNN case study
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits
Ultra-low-power ECG front-end design based on compressed sensing
Multiplicative Window Generators of Pseudo-random Test Vectors
Embedded systems to high performance computing using STT-MRAM
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations
System-level hardware-based protection of memories against soft-errors
Response Time Analysis for Energy-Harvesting Mixed-Criticality Systems
A spectral clustering approach to application-specific network-on-chip synthesis
An efficent dynamic multicast routing protocol for distributing traffic in NOCs
White box performance analysis considering static non-preemptive software scheduling
Assertion-based verification of RTOS properties
Skewed pipelining for parallel simulink simulations
System Design Based on Single Language and Single-Chip Java ASIP Microcontroller
Analysis of Oscillator Injection Locking by Harmonic Balance Method
On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations
Resource-Aware MapReduce Runtime for Multi/Many-core Architectures
Value-Driven Mixed-Precision Quantization for Patch-Based Inference on Microcontrollers
Adaptive prefetching for shared cache based chip multiprocessors
Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering
Automating the pipeline of arithmetic datapaths
Hot Topic Session: RF Design Technology for Highly Integrated Communication Systems
Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming
Evaluation of heterogeneous AIoT Accelerators within VEDLIoT
A Novel Analog Module Generator Environment
Runtime Monitoring Neuron Activation Patterns
Optimization-based wideband basis functions for efficient interconnect extraction
Cost-effective analysis of post-silicon functional coverage events
Multidimensional periodic scheduling: a solution approach
A Lightweight Approach for Embedded Reconfiguration of FPGAs
Designing System-Level Software Solutions for Open OS's on 3g Wireless Handsets
Characterization of possibly detected faults by accurately computing their detection probability
Counting Priority Inversions: Computing Maximum Additional Core Requests of DAG Tasks
Approximate computing for spiking neural networks
An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
Mapping the physical layer of radio standards to multiprocessor architectures
SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators
Statistical library characterization using belief propagation across multiple technology nodes
Asynchronous SRT Dividers: The Real Cost
Power Variance Analysis breaks a masked ASIC implementation of AES
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors
Guaranteed Compression Rate for Activations in CNNs using a Frequency Pruning Approach
Scalable compile-time scheduler for multi-core architectures
Formal Specification in VHDL for Hardware Verification
UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE
PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash
Adaptive Simulation for Single-Electron Devices
Designing Closer to the Edge
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters
Test quality analysis and improvement for an embedded asynchronous FIFO
Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches
SACPlace: Multi-Agent Deep Reinforcement Learning for Symmetry-Aware Analog Circuit Placement
FMTT: Fused Multi-Head Transformer with Tensor-Compression for 3D Point Clouds Detection on Edge Devices
Temperature and voltage aware timing analysis: application to voltage drops
Nonvolatile processors: Why is it trending?
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
NVCiM-PT: An NVCiM-Assisted Prompt Tuning Framework for Edge LLMs
High data rate fully flexible SDR modem advanced configurable architecture & development methodology
On routing fixed escaped boundary pins for high speed boards
MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors
Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation
Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA
A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study
Task scheduling for reliable cache architectures of multiprocessor systems
Symmetric Multiprocessing on Programmable Chips Made Easy
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems
Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise
Cyber-physical cloud computing: The binding and migration problem
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression
Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis
Automated Optimal Design of Switched-Capacitor Filters
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis
Verification by Simulation Comparison using Interface Synthesis
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
Timing analysis of an avionics case study on complex hardware/software platforms
Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors
System Fault Diagnosis based on a Fuzzy Qualitative Approach
Implementation of a reduced-lattice MIMO detector for OFDM Systems
Analysis and synthesis of quantum circuits by using quantum decision diagrams
Adiabatic Implementation of Manchester Encoding for Passive NFC System
Energy-efficient real-time task scheduling with temperature-dependent leakage
Functional qualification of TLM verification
SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware
Comparison of Test Pattern Decompression Techniques
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
A Practical Approach for Reconciling High and Predictable Performance in Non-Regular Parallel Programs
Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks
E-Design Based on the Reuse Paradigm
Timing error statistics for energy-efficient robust DSP systems
Memory Management Methodology for Application Data Structure Refinement and Placement on Heterogeneous DRAM/NVM Systems
Register synthesis for speculative computation
Architecting a common-source-line array for bipolar non-volatile memory devices
Accurately timed transaction level models for virtual prototyping at high abstraction level
Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment
Vacuity analysis for property qualification by mutation of checkers
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies
Low Power Embedded Software Optimization Using Symbolic Algebra
SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions
IP-Based System-on-a-Chip Design
STSearch: State Tracing-based Search Heuristics for RTL Validation
Automatic generation of streaming datapaths for arbitrary fixed permutations
Minimizing the number of floating bias voltage sources with integer linear programming
GPU-EvR: Run-time event based real-time scheduling framework on GPGPU platform