yusuke1997/dblp-id-title huggingface dataset:
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms
Hardware architecture design and implementation for FMCW radar signal processing algorithm
An inter-task real time DVFS scheme for multiprocessor embedded systems
Energy consumption characterization of a Massively Parallel Processor Array (MPPA) platform running a hyperspectral SVM classifier
High-Level Online Power Monitoring of FPGA IP Based on Machine Learning
Range estimation of floating-point variables in Simulink models
Wireless Sensor Network node global energy consumption modeling
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition
Performance evaluation of total focusing method on GPP and GPU
A resource-aware nearest-neighbor search algorithm for k-dimensional trees
Hardware-Software Implementation of a SFM Module for Navigation an Unmanned Aerial Vehicles-A Demo
A fast method for overflow effect analysis in fixed-point systems
New 3D-integrated burst image sensor architectures with in-situ A/D conversion
Tetrahedral volume reconstruction in X-ray tomography using GPU architecture
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems
Demo: UHD live video streaming with a real-time scalable HEVC encoder
Design of fixed-point rounding operators for the VHDL-2008 standard
PHAT: A technology for prototyping parallel heterogeneous architectures
Comparative Study of Memory Optimization Techniques for Dataflow-Modeled Applications
On the scalability of image and signal processing parallel applications on emerging cc-NUMA many-cores
LiFT: Lightweight, FPGA-Tailored 3D Object Detection Based on LiDAR Data
Consumption analysis and estimation in the design of GStreamer based multimedia applications
Object tracking with the use of a moving camera implemented in heterogeneous zynq SoC - A demo
FPGA-based bio-inspired architecture for multi-scale attentional vision
Hardware implementation of a biometric recognition algorithm based on in-air signature
Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radios
Session 6: Smart and adaptive devices
The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs
Session 5: Image processing on multicore plateforms
Parallel implementation of an iterative PCA algorithm for hyperspectral images on a manycore platform
Constrained non-linear fitting for stochastic modeling of inertial sensors
Investigating performance variations of an optimized GPU-ported granulometry algorithm
Many-core parallelization of fixed-point optimization of VLSI circuits through GPU devices
Particle filters and resampling techniques: Importance in computational complexity analysis
Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures
Demo: Overlay architectures for heterogeneous FPGA cluster management
Session 9 (special session): Software defined radio
The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer
Model-driven reliability evaluation for MPSoC design
DFG implementation on multi GPU cluster with computation-communication overlap
A prototype of an invasive tightly-coupled processor array
Analysis on scalability and energy efficiency of HEVC decoding using task-based programming model
Accelerating local feature extraction using OpenCL on heterogeneous platforms
Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentation
High-speed camera with embedded FPGA processing
Worst-case latency analysis of SDF-based parametrized dataflow MoCs
Energy efficiency and performance management of parallel dataflow applications
Parallelization of an ultrasound reconstruction algorithm for non destructive testing on multicore CPU and GPU
TURNUS: An open-source design space exploration framework for dynamic stream programs
Designing processors using MAsS, a modular and lightweight instruction-level exploration tool
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application
Design and analysis of an FPGA based encoder SoC for locally stationary image source
An overflow free fixed-point eigenvalue decomposition algorithm: Case study of dimensionality reduction in hyperspectral images
Joint Underwater Depth Estimation and Dehazing from a Single Image Using Attention U-Net
Application-specific instruction processor for extracting local binary patterns
Sparsity-based real-time audio restoration
A 3D reconstruction from real-time stereoscopic images using GPU
A hybrid dual-core Reconfigurable Processor for EBCOT tier-1 encoder in JPEG2000 on next generation of digital cameras
Gradient - An adaptive fault-tolerant routing algorithm for 2D mesh Network-on-Chips
A wearable human activity recognition system on a chip
Session 4: Advanced hardware architectures
A nature-inspired adaptive floating-point coprocessing system
Automatic generation of dataflow-based reconfigurable co-processing units
Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster
2013 Conference on Design and Architectures for Signal and Image Processing, Cagliari, Italy, October 8-10, 2013
Special session 2 Computer vision and Image analysis
A hierarchical Ant-Colony heuristic for architecture synthesis for on-chip communication
Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures
On-chip compression for HDR image sensors
Distilling the knowledge in CNN for WCE screening tool
An evaluation on using GPU coprocessing for software radios on a low-cost platform
FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study
A neural model for hardware plasticity in artificial vision systems
Hardware-software implementation of vehicle detection and counting using virtual detection lines
Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures
A Highly Configurable Platform for Advanced PPG Analysis
Efficient FPGA Implementation of ViT Non-linear Functions
Implementing large-kernel 2-D filters using Impulse CoDeveloper
Flexible VLIW processor based on FPGA for real-time image processing
Crosstalk-aware link power model for Networks-on-Chip
A new single-error correction scheme based on self-diagnosis residue number arithmetic
Design and Architecture for Signal and Image Processing - 18th International Workshop, DASIP 2025, Barcelona, Spain, January 20-22, 2025, Proceedings
Video surveillance application based on application specific vector processors
Demo night
Power efficient dataflow design for a heterogeneous smart camera architecture
FPGA-based rectification of stereo images
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation
Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs
Design and Architecture for Signal and Image Processing - 16th International Workshop, DASIP 2023, Toulouse, France, January 16-18, 2023, Proceedings
Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors
Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems
Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach
GRECO: GREen communicating objects
FPGA-based real-time MFCC extraction for automatic audio indexing on FM broadcast data
Efficient Software and Hardware Implementations of a QCSP Communication System
Session 2: Tools for DSP algorithm implementation
Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems
Task placement for dynamic and partial reconfigurable architecture
Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality
Multiplier free filter bank based concept for blocker detection in LTE systems
Energy-efficient heterogeneous reconfigurable sensor node for distributed structural health monitoring
The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case
Reducing the impact of internal upsets inside the correlation process in GPS Receivers
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods
Demo: Localisation in a faulty digital GPS receiver
Closed-loop adaptive and stochastic prefetch mechanism for data array
Design under constraints of availability and energy for sensor node in wireless sensor network
A dynamically reconfigurable asynchronous processor for low power applications
Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard
POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing
Smart sensor architectures for embedded biosignal analysis
Towards Real-Time and Energy Efficient Siamese Tracking - A Hardware-Software Approach
XMSIM: A tool for early memory hierarchy evaluation
Tools for deploying dataflow models on FPGA targets
A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms
Foreground detection in video streams in an FPGA without external memory
Reliable NCO carrier generators for GPS receivers
Task model and online operating system API for hardware tasks in OLLAF platform
Foreground object features extraction with GLCM texture descriptor in FPGA
Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chip
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip
Session 2: Architectures for image processing
A hierarchical implementation of Hadamard transform using RVC-CAL dataflow programming and dynamic partial reconfiguration
Efficient hardware acceleration for approximate inference of bitwise deep neural networks
A comparison of cost construction methods onto a C6678 platform for stereo matching
Real-time correlation for locating systems utilizing heterogeneous computing architectures
A case study of the stochastic modeling approach for range estimation
Using Time-of-Flight Sensors for People Counting Applications
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays
Optimization methodologies for complex FPGA-based signal processing systems with CAL
Architectural decomposition of video decoders for many core architectures
HaLOEWEn: A heterogeneous reconfigurable sensor node for distributed structural health monitoring
KD-AHOSVD: Neural Network Compression via Knowledge Distillation and Tensor Decomposition
Analysis techniques for static dataflow models with access patterns
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms
The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems
FPGA-Based Real Time Embedded Hough Transform Architecture for Circles Detection
Exploring frequency tuning policies for USRP-N210 SDR platform and GNU radio
Systemc modelization for fast validation of imager architectures
An efficient parallel motion estimation algorithm and X264 parallelization in CUDA
GPU implementation of motion estimation for visual saliency
Code generation for a SIMD architecture with custom memory organisation
Design of a processor optimized for syntax parsing in video decoders
Noise probability density function in fixed-point systems based on smooth operators
MARTE to ΠSDF transformation for data-intensive applications analysis
Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC
Low power noise detection circuit utilizing switching activity measurement method
A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA
FPGA implementations of HEVC Inverse DCT using high-level synthesis
HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA
2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, October 12-14, 2016
Hardware implementation of a soft cancellation decoder for polar codes
Partitioning and context switching for a reconfigurable FPGA-based DAB receiver
Architectures and signal reconstruction methods for nanosecond resolution Integrated Streak Camera in standard CMOS technology
A low energy adaptive motion estimation hardware for H.264 Multiview Video Coding
A portable demonstration device for an integrated optical angle measurement system
Optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-Based Vision
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework
2018 Conference on Design and Architectures for Signal and Image Processing, DASIP 2018, Porto, Portugal, October 10-12, 2018
GAMPIX: A new generation of gamma camera
Session 7 (special session): Advanced image processing for space applications
Toward the synthesis of fixed-point code for matrix inversion based on Cholesky decomposition
Foreground detection and image segmentation in a flexible ASVP platform for FPGAs
Self-adaptive harris corner detector on heterogeneous many-core processor
Fuzzy logic modeling for objective image quality assessment
Evaluation of an RTOS on top of a hosted virtual machine system
MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations
A New Real-Time Embedded Video Denoising Algorithm
A runtime adaptive H.264 video-decoding MPSoC platform
Dynamic power evaluation of LTE wireless baseband processing on FPGA
Video++, a modern image and video processing C++ framework
Virtualization of heterogeneous and adaptive multi-core/multi-board systems
Low Latency Architecture Design for Decoding 5G NR Polar Codes
Proposition and evaluation of a real-time generic architecture for a laser stripe detection system on FPGA
GPU Based Quarter Spectral Correlation Density Function
GPU-based acceleration of symbol timing recovery
2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology
Implementation of a Real-Time Image-Based Vibration Detection and Adaptive Filtering on an FPGA
A scalable hardware architecture for retinal blood vessel detection in high resolution fundus images
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding
Middleware approaches for adaptivity of Kahn Process Networks on Networks-on-Chip
A new approach to 3D form recognition within video capsule endoscopic
Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy
A prototype of an adaptive computer vision algorithm on MPSoC architecture
CUVLE: Variable-length encoding on CUDA
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control
A review of world's fastest connected component labeling algorithms: Speed and energy estimation
Reconfigurable vision processing system for player tracking in indoor sports
CSD-Driven Speedup in RISC-V Processor
High-level modelling and automatic generation of dynamicaly reconfigurable systems
Low-cost guaranteed-throughput communication ring for real-time streaming MPSoCs
sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA
2019 Conference on Design and Architectures for Signal and Image Processing, DASIP 2019, Montreal, QC, Canada, October 16-18, 2019
Hardware-based architecture for asymmetric numeral systems entropy decoder
Programmable routers for efficient mapping of applications onto NoC-based MPSoCs
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, October 8-10, 2014
Image tiling for embedded applications with non-linear constraints
Prototype of a novel steady-state load identification technique for digitally controlled DC-DC power supplies
Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array
Exploring Performance Improvement Opportunities in Directive-Based GPU Programming
Prototype of a radio-on-demand broadcast receiver with real time musical genre classification
Real-Time FPGA Implementation of the Semi-global Matching Stereo Vision Algorithm for a 4K/UHD Video Stream
A hierarchical approach to the out-of-order arrival of frames in video streaming applications on clustered MPSoC
QoS Aware Design-Time/Run-Time Manager for FPGA-Based Embedded Systems
A framework for the design of reconfigurable fault tolerant architectures
Evaluation of driver assistance systems with a car simulator using a virtual and a real FPGA platform
Influence of Dataflow Graph Moldable Parameters on Optimization Criteria
FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applications
Real-time moving object detection for video surveillance system in FPGA
Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration
A generic video adaptation FPGA implementation towards content- and context-awareness in future networks
Demo: SLP-aware word length optimization
Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications
Fixed-Point Code Synthesis Based on Constraint Generation
Single-FPGA complete 3D and 2D medical ultrasound imager
Hardware code generation from dataflow programs
A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool
Exploring Fully Convolutional Networks for the Segmentation of Hyperspectral Imaging Applied to Advanced Driver Assistance Systems
A Roadmap for Autonomous Fault-Tolerant Systems
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support
Camera-based system for tracking and position estimation of humans
Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform
Comparison of Different Methods Making Use of Backup Copies for Fault-Tolerant Scheduling on Embedded Multiprocessor Systems
Airport markings recognition for automatic taxiing
Hardware realization of an FPGA processor - Operating system call offload and experiences
Real-time RGB-D data processing on GPU architecture
Session 8: 3D vision systems and applications
Demo: HELICoiD tool demonstrator for real-time brain cancer detection
SiPM based smart pixel for photon counting integrated streak camera
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding
Detecting data-parallel synchronous dataflow graphs
Enabling GPU software developers to optimize their applications - The LPGPU 2 approach
High-throughput LDPC decoding using the RHS algorithm
FPGA memory optimization for real-time imaging
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms
Communication cost reduction for hardware tasks placed on homogeneous reconfigurable resource
Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing
Hardware architecture for lowering the error floor of LTE turbo codes
FPGA implementation of a flexible synchronizer for cognitive radio applications
A flexible implementation of a Global Navigation Satellite System (GNSS) receiver for on-board satellite navigation
3D tomography back-projection parallelization on FPGAs using opencl
Embedded vision-based SLAM: A model-driven approach
Effects of colored noise in Linear Adaptive Filters applied to GNSS multipath detection
Characterization of capture actions in video sequences
A Practical HW-Aware NAS Flow for AI Vision Applications on Embedded Heterogeneous SoCs
A systemc TLM framework for distributed simulation of complex systems with unpredictable communication
Memory management in embedded vision systems: Optimization problems and solution methods
Application of temporal decoupling to the creation of efficient performance models of automotive architectures
A framework for rapid prototyping of embedded vision applications
Session 3: Method and tools for system design
Custom processor design for efficient, yet flexible Lucas-Kanade optical flow
Rakeness-based compressed sensing on ultra-low power multi-core biomedicai processors
Efficient FFT pruning algorithm for non-contiguous OFDM systems
Scratchy: A Class of Adaptable Architectures with Software-Managed Communication for Edge Streaming Applications
POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA
Flexible front-end processing for software defined radio applications using application specific instruction-set processors
Generation of static tables in embedded memory with dense scheduling
Session 4 (special session): Modern localisation techniques
CNN hardware acceleration on a low-power and low-cost APSoC
A high-level language for programming a NoC-based Dynamic Reconfiguration Infrastructure
Scalable FPGA Implementation of Dynamic Programming for Optimal Control of Hybrid Electrical Vehicles
A system-level security approach for heterogeneous MPSoCs
Implementation of a Fast Fourier transform algorithm onto a manycore processor
Real-Time Analysis of Living Biological Cell Activity
Runtime adaptive allocation of dynamically mixed tasks on a heterogeneous MPSoC platform
A rapid control prototyping platform methodology for decentralized automation
Session 1: Vision and image processing architectures
An Initial Framework for Prototyping Radio-Interferometric Imaging Pipelines
Fast and accurate hybrid power estimation methodology for embedded systems
Application workload model generation methodologies for system-level design exploration
Efficient maximal convex custom instruction enumeration for extensible processors
Efficient Solving of Markov Decision Processes on GPUs Using Parallelized Sparse Matrices
System-level PMC-driven energy estimation models in RVC-CAL video codec specifications
Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder
Networked embedded acoustic processing system for smart building applications
Classification and transformation of dynamic dataflow programs
Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters
ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration technique
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs
Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification
2017 Conference on Design and Architectures for Signal and Image Processing, DASIP 2017, Dresden, Germany, September 27-29, 2017
Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study
Convolutional Fully-Connected Capsule Network (CFC-CapsNet)
Adaptive space-time structural coherence for selective imaging
Monte Carlo method based precision analysis of deep convolution nets
Data-Type Assessment for Real-Time Hyperspectral Classification in Medical Imaging
Demo: WIFI-WiMax vertical handover on an ARM-FPGA platform with partial reconfiguration
Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes
Black-box and white-box early power intent simulation and verification: Two novel approaches
High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs
Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation
DExIE - An IoT-Class Hardware Monitor for Real-Time Fine-Grained Control-Flow Integrity