yusuke1997/dblp-id-title huggingface dataset:
A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application
An Open-source Library of Large Integer Polynomial Multipliers
Autocalibration Approach for Improving Robustness of Analog ICs
Fast time-parallel C-based event-driven RTL simulation
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs
Sources of bias in EDA tools and its influence
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems
Dedicated hardware architecture for object tracking preprocessing implemented in FPGA
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
Real-time sleep detection and warning system to ensure driver's safety based on EEG
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor
ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators
Efficiency of oscillation-based BIST in 90nm CMOS active analog filters
Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices
Design and Implementation of an Adaptive Algorithm for Hybrid Automatic Repeat Request
Applicative System Level Test introduction to Increase Confidence on Screening Quality
External capacitorless low dropout linear regulator using cascode structure
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters
Can Clock Faults be Detected Through Functional Test?
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching
Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage
Test-data compression with low number of channels and short test time
Fast Simulation of SystemC Synthesizable Subset
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators
Security properties of oscillator rings in true random number generators
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture
A symbolic RTL synthesis for LUT-based FPGAs
Radiation-tolerant combinational gates - an implementation based comparison
Firmware Update Manager: A remote firmware reprogramming tool for low-power devices
Formal Design Space Exploration for memristor-based crossbar architecture
SOC Diagnostic Design Using RESPIN Architecture
Quadrature-Phase Topology of a High Frequency Ring Oscillator
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
On-chip aging sensor to monitor NBTI effect in nano-scale SRAM
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs
A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles
A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumption
Functional Verification of Arithmetic Circuits: Survey of Formal Methods
Quadruple voltage mixed quenching and active resetting circuit in 150 nm CMOS for an external SPAD
Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor
Efficient Patch Module for Single-bank or Dual-bank Firmware Updates for Embedded Devices
Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown
Synthesis of asynchronous monitors for critical electronic systems
Design technology and the cloud
Body biasing for analog design: Practical experiences in 22 nm FD-SOI
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications
On hardware-based fault-handling in dynamically scheduled processors
A new SAT-based ATPG for generating highly compacted test sets
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters
Intermittent Resistive Faults in Digital CMOS Circuits
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents
High-level symbolic simulation for automatic model extraction
A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks
River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars
QDI Binary Comparator Networks and their Application in Combinational Logic
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle
Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics
A 64-MHz∼640-MHz 64-phase clock generator
Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis
Asynchronous two-level logic of reduced cost
Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems
Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC
A hybrid power modeling approach to enhance high-level power models
A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip
A low phase noise Ka-band voltage controlled oscillator using 0.15 µm GaAs pHEMT technology
Design-for-Test of Asynchronous Networks-on-Chip
A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015
An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology
Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches
A low phase noise 20 GHz voltage control oscillator using 0.18-μm CMOS technology
Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP
Predictive Fault Grouping based on Faulty AC Matrices
Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array
From online fault detection to fault management in Network-on-Chips: A ground-up approach
A unified CMOS inverter model for planar and FinFET nanoscale technologies
Flip-Flops and Scan-Path Elements for Nanoelectronics
Hash-based Pattern Matching for High Speed Networks
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects
Hardware acceleration in computer networks
Burst-pulse Generator based on transmission line toward sub-MMW
A new analog output buffer for data driver of active matrix displays using low-temperature polycrystalline silicon thin-film transistors
Modeling temperature distribution in Networks-on-Chip using RC-circuits
Mealy-to-moore transformation
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
PaGoRi:A Scalable Parallel Golomb-Rice Decoder
Architecture model for approximate palindrome detection
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study
Forward and backward guarding in early output logic
Automatic integration of hardware descriptions into system-level models
Simulation-based sensitivity and worst-case analyses of automotive electronics
A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems
Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience
Bounded model checking of Contiki applications
A SBST strategy to test microprocessors' Branch Target Buffer
Cognitive self-adaptive computing and communication systems: Test, control and adaptation
Reliability-aware cross-layer custom instruction screening
Web-Based Framework for Parallel Distributed Test
Heuristic algorithm of two-level minimization of fuzzy logic functions
Tunable Voltage Reference circuit in a standard 65nm CMOS technology
Design and implementation of high-performance high-valency ling adders
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs
Increasing the efficiency of analog OBIST using on-chip compensation of technology variations
A Design Preconditioning Flow for Low-Noise Circuits
MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers
Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip
A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model
FPGA-based Fault Simulator
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration
Ad-Hoc Translations to Close Verilog Semantics Gap
Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit
Noise and linearity analysis of a frequency to voltage converter
Exploiting error detection latency for parity-based soft error detection
TSV based 3D stacked ICs: Opportunities and challenges
Global parametric faults identification with the use of Differential Evolution
Test Pattern Compression Based on Pattern Overlapping
Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates
ADCs in deep submicron technologies for ASICs of pixel architecture
Low-cost fault tolerance on the ALU in simple pipelined processors
A 65nm embedded low power SRAM compiler
Q-Learning-based Routing Algorithm for 3D Network-on-Chips
Software-Level TMR Approach for On-Board Data Processing in Space Applications
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring
Formal Verification of Software for the Contiki Operating System Considering Interrupts
A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores
An Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning
Partitioning methods for unicast/multicast traffic in 3D NoC architecture
Digital methods of offset compensation in 90nm CMOS operational amplifiers
Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations
Optimal Memory Address Seeds for Pattern Sensitive Faults Detection
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks
Power analysis methodology for secure circuits
8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference
Hardware Implementation of a RSS Localization Algorithm for Wireless Capsule Endoscopy
Design of a Scalable Asynchronous Dataflow Processor
Optimizing DD-based synthesis of reversible circuits using negative control lines
Mixed-Signal DFT for fully testable ASIC
Interface Protection Against Transient Faults
On-chip Integration of Magnetic Force Sensing Current Monitors
SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures
Heuristic for Page-Based Incremental Reprogramming of Wireless Sensor Nodes
Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration
A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology
Boosting SW Development Efficiency with Function Lifetime Diagrams
A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation
Multiple stuck-at-fault detection theorem
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test
Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch
A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel
Optimized differencing algorithm for firmware updates of low-power devices
Comparison of different test strategies on a mixed-signal circuit
Improved design of the uninterruptable power supply unit for powering of network devices
Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology
Efficient diagnostics algorithms for regular computing structures
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
Analog front-end for precise human body temperature measurement
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime
Max-Fill: A method to generate high quality delay tests
Muller C-elements based on minority-3 functions for ultra low voltage supplies
Improving combinational circuit resilience against soft errors via selective resource allocation
UVM-based Verification of Bluetooth Low Energy Controller
Towards Polynomial Formal Verification of Complex Arithmetic Circuits
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
Fully Differential Difference Amplifier for Low-Noise Applications
A don't care identification method for test compaction
Failure probability of SRAM-FPGA systems with Stochastic Activity Networks
Test of automotive embedded processors with high diagnostic resolution
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description
Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults
Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networks
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology
Natural Language Based Power Domain Partitioning
VeSFET as an analog-circuit component
New Strategies for System-Level Design
A Low Ripple Current Mode Voltage Doubler
Efficient mixture preparation on digital microfluidic biochips
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012
CRC based hashing in FPGA using DSP blocks
On NFA-split architecture optimizations
Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations
A Concept Towards Pressure-Controlled Microfluidic Networks
An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip
RF Transformer Model Parameters Measurement
Reduction of FPGA resources for regular expression matching by relation similarity
Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder
High throughput architecture for the Advanced Encryption Standard Algorithm
Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests
A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement
Improve clock gating through power-optimal enable function selection
Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level
FPGA Prototyping and Accelerated Verification of ASIPs
A Contextual Resources use: a Proof of Concept through the APACHES' Platform
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns
Developing a new phase noise estimation technique based on time varying model
Intermittent Resistance Fault Detection at Board Level
Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST
Design and optimisation of NiTi pressure gauge
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines
Design and Test of Microfluidic Biochips
Inference Energy Analysis in Context of Hardware-Aware NAS
Design of Low-Bit Robust Analog-to-Digital Converters for Signals with Gaussian Distribution
4th IEEE/ACM International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC, CANOPIE-HPC@SC 2022, Dallas, TX, USA, November 14, 2022
3rd International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC, CANOPIE-HPC@SC 2021, St. Louis, MO, USA, November 14, 2021
Complete Provenance for Application Experiments with Containers and Hardware Interface Metadata
Libfabric-based Injection Solutions for Portable Containerized MPI Applications
Deploying Containerized QuanEX Quantum Simulation Software on HPC Systems
One Step Closer to Converged Computing: Achieving Scalability with Cloud-Native HPC
A separated model for running rootless, unprivileged PMIx-enabled HPC applications in Kubernetes
Feasibility of Running Singularity Containers with Hybrid MPI on NASA High-End Computing Resources
Multiscale scientific workflows on high-performance hybrid cloud
Scaling Podman on Perlmutter: Embracing a community-supported container ecosystem
RollingGantryCrane: Automation for unpacking containers into HPC environments
It's a Scheduling Affair: GROMACS in the Cloud with the KubeFlux Scheduler
Simple Constraint Embedding for Quantum Annealers
Computing architecture to perform approximated simulated annealing for Ising models
Information-theoretic limits of algorithmic noise tolerance
Reducing the Size of Spiking Convolutional Neural Networks by Trading Time for Space
Linking Sparse Coding Dictionaries for Representation Learning
Future Computing Systems (FCS) to Support "Understanding" Capability
Routing Congestion Aware Cell Library Development for Monolithic 3D ICs
Generating Sparse Representations Using Quantum Annealing: Comparison to Classical Algorithms
Hierarchical Network Partitioning for Reconfigurable Large-Scale Neuromorphic Systems
Optimization of Magnetic Tunneling Junction Devices for Neuromorphic Circuits for Solving MAXCUT
Classical Adiabatic Annealing in Memristor Hopfield Neural Networks for Combinatorial Optimization
An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics
Technology considerations for neuromorphic computing
An FPGA-Based Neuromorphic Processor with All-to-All Connectivity
Parallel data processing with Magnonic Holographic Co-Processor
Why Reliability for Computing Needs Rethinking
SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance
Design Principles of Large-Scale Neuromorphic Systems Centered on High Bandwidth Memory
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip
In-Memory Execution of Compute Kernels Using Flow-Based Memristive Crossbar Computing
The RISP Neuroprocessor - Open Source Support for Embedded Neuromorphic Computing
Adiabatic Circuits for Quantum Computer Control
Nonlinear Dynamics and Chaos for Fleixble, Reconfigurable Computing
IEEE International Conference on Rebooting Computing, ICRC 2024, San Diego, CA, USA, December 16-17, 2024
Electromechanical Adiabatic Computing: Towards Attojoule Operation
The Dilemma of Random Parameter Initialization and Barren Plateaus in Variational Quantum Algorithms
An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems
IEEE International Conference on Rebooting Computing, ICRC 2022, San Francisco, CA, USA, December 8-9, 2022
2021 International Conference on Rebooting Computing (ICRC), Los Alamitos, CA, USA, November 30 - Dec. 2, 2021
Multiplication with Fourier Optics Simulating 16-Bit Modular Multiplication
Parallelized Linear Classification with Volumetric Chemical Perceptrons
Enhanced methods for Evolution in-Materio Processors
Synaptic Sampling of Neural Networks
A Mini-MIPS microprocessor for adiabatic computing
Harnessing adaptive dynamics in neuro-memristive nanowire networks for transfer learning
On the Physical Underpinnings of the Unusual Effectiveness of Probabilistic and Neural Computation
Using non-convex optimization in quantum process tomography: Factored gradient descent is tough to beat
The Largest Cognitive Systems Will be Optoelectronic
Thermodynamic Intelligence, a Heretical Theory
Cross Entropy Hyperparameter Optimization for Constrained Problem Hamiltonians Applied to QAOA
Optimized Telecloning Circuits: Theory and Practice of Nine NISQ Clones
Quancorde: Boosting fidelity with Quantum Canary Ordered Diverse Ensembles
Rebooting Quantum Computing
HiAER-Spike: Hardware-Software Co-Design for Large-Scale Reconfigurable Event-Driven Neuromorphic Computing
Hybrid Topologies for Reconfigurable Matrices Based on Nano-Grain Cells
Neuromorphic mixed-signal circuitry for Asynchronous Pulse Processing
Socrates-D: Multicore Architecture for On-Line Learning
FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices
Reconfigurable and Programmable Ion Trap Quantum Computer
A Bayesian Stochastic Machine for Sound Source Localization
SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks
Rethinking operating systems for rebooted computing
An FPGA-Quantum Annealer Hybrid System for Wide-Band RF Detection
FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator
Opportunities in physical computing driven by analog realization
Hybrid Programming for Near-Term Quantum Computing Systems
All-optical neuromorphic computing in optical networks of semiconductor lasers
Alien vs. Predator: Brain Inspired Sparse Coding Optimization on Neuromorphic and Quantum Devices
A Quantum Method for Subchannel allocation in Device-to-Device Communication
Exploring More-Coherent Quantum Annealing
On-Chip Passive Photonic Reservoir Computing with Integrated Optical Readout
Overcoming the Static Learning Bottleneck - the need for adaptive neural learning
A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
Clustering Vehicle Routing Problems on Specialized Hardware
Accelerating Simulation-based Inference with Emerging AI Hardware
Computing with a Chemical Reservoir
Rebooting the Data Access Hierarchy of Computing Systems
Advanced Packaging and Heterogeneous Integration to Reboot Computing
Arithmetic Primitives for Efficient Neuromorphic Computing
A novel operational paradigm for thermodynamically reversible logic: Adibatic transformation of chaotic nonlinear dynamical circuits
Reoptimization of Quantum Circuits via Hierarchical Synthesis
NNgine: Ultra-Efficient Nearest Neighbor Accelerator Based on In-Memory Computing
Image Classification Using Quantum Inference on the D-Wave 2X
Hierarchical Memcapacitive Reservoir Computing Architecture
Reconfigurable Probabilistic AI Architecture for Personalized Cancer Treatment
Digital neuromorphic design of a Liquid State Machine for real-time processing
Towards On-Chip Optical FFTs for Convolutional Neural Networks
Challenges for optical interconnect for beyond Moore's law computing
High throughput neural network based embedded streaming multicore processors
Processor-in-memory support for artificial neural networks
Mixture of Experts with Mixture of Precisions for Tuning Quality of Service
High-Speed Compilation of Large-Scale Stochastic Circuits
IEEE International Conference on Rebooting Computing, ICRC 2023, San Diego, CA, USA, December 5-6, 2023
Stochastic single flux quantum neuromorphic computing using magnetically tunable Josephson junctions
Designing reconfigurable large-scale deep learning systems using stochastic computing
Heterogeneous Technology Configurable Fabrics for Field-Programmable Co-Design of CMOS and Spin-Based Devices
Equivalence of Coupled Parametric Oscillator Dynamics to Lagrange Multiplier Optimization
Reducing data movement with approximate computing techniques
Assessing a Neuromorphic Platform for use in Scientific Stochastic Sampling
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing
An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS
Advanced unembedding techniques for quantum annealers
From the Quantum Moore's Law toward Silicon Based Universal Quantum Computing
Brain inspired photonic motif networks
Computationally-redundant energy-efficient processing for y'all (CREEPY)
High density multilayer optical circuit board for unprecedented connectivity at board scales
Spatial-Spectral Materials for High Performance Optical Processing