yusuke1997/dblp-id-title huggingface dataset:
On Buffering Schemes for Long Multi-Layer Nets
DRRA-based Reconfigurable Architecture for Mixed-Radix FFT
Media Processors
Status Condition Analysis during Data Path Verification of Sequential Circuits
Thermal-Aware Test Data Compression Using Dictionary Based Coding
A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA Platforms
Application of Test-View Modeling to Hierarchical ATPG
Bridge Over Troubled Wrappers: Automated Interface Synthesis
Improving Reliability and Energy Requirements of Memory in Body Sensor Networks
A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata
Design of Manchester Carry Chain Hybrid Adder for MASH 1-1-1 Delta Sigma Modulator for Fractional-N Frequency Synthesizers
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition
E-DOSA: Efficient Dataflow for Optimising SNN Acceleration
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
A Low Power-Delay Product Page-Based Address Bus Coding Method
Geometry Independent Wirelength Estimation Method in VLSI Routing
Verification of KPN Level Transformations
A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip
Solutions for a small car - Made for India and Made in India
A Power Efficient Approach to Fault-Tolerant Register File Design
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG
FPGA based Smart and Sustainable Agriculture
An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards
K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible Multiplier
Keynote Talk: A History of the VLSI Design Conference
Energy Optimized Non-preemptive Scheduling of Real-Time Tasks with Precedence and Reliability Constraints
Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing
A Reconfigurable Architecture for Secure Multimedia Delivery
Software Coherence Management on Non-coherent Cache Multi-cores
Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's
Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing
JouleQuest: An Accurate Power Model for the StarCore DSP Platform
An Integrated Approach for Combining BDD and SAT Provers
IEEE 1394a_2000 Physical Layer ASIC
An Architecture To Test Random Access Memories
A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic
A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips
A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
Tutorial T3: DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield
Calculation of Minimum Number of Registers in Arbitrary Life Time Chart
Broadband spectrum generation in Silicon nanocrystal-based dual-slot waveguide
A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits
Tutorial T8A: Designing Silicon-Photonic Communication Networks for Manycore Systems
Charge-Sharing-Problem Reduced Split-Path Domino Logic
Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence
Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions
Parasitic Interactions with Intermediate Substrates and Methods to Mitigate their Impact: A Case Study in Voltage Protection ICs
Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization
A Reconfigurable Oscillator Topology for Dual-Band Operation
Instruction Selection in ASIP Synthesis Using Functional Matching
Customizable Head-mounted Device for Detection of Eye Disorders using Virtual Reality
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis
A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits
2D Thermal Contour Modeling of 14 nm SOI FinFET Using Machine Learning for Efficient Thermal Profile Prediction
On-Chip Signature Checking for Embedded Memories
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control
An Approach to Architectural Enhancement for Embedded Speech Applications
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation
Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research
Design and Test of MEMs
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs
20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra
Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation
Impact of Variations on Synchronizer Performance: An Experimental Study
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages
Constrained Floorplanning with Whitespace
Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter
Reinforcement Learning based Droplet Routing Technique in Hexagonal Digital Microfluidic Biochips using Dueling Network
Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme
Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs
Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies
Design of an Efficient ASIC for the Control of Microwave Ovens
14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India
A Quasi-Static Model for the Coupling Impedance between Coplanar Rectangular Contacts on a Bulk Substrate
A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T SRAM in FinFET Technology
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits
Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques
A Neural Net Branch Predictor to Reduce Power
Challenges in Adoption of RF to DC Converter for Micro-Scale RF Energy Harvesting Systems
Low Power Solution for Wireless Applications
A Low Power CMOS Imager Based on Distributed Compressed Sensing
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures
Library Binding for High-Level Synthesis of Analog Systems
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
n OHM - A Multi-Process Device Synthesis Tool for Lateral DMOS Structures
Timing Verification and Delay Test Generation for Hierarchical Designs
Device Reliability and Failure Mechanisms Related to Gate Dielectrics and Interconnects
Ultra Low Power Digital Front-End for Single Lead ECG Acquisition
Test Generation for Hybrid Systems Using Clustering and Learning Techniques
Layout-Driven Timing Optimization by Generalized De Morgan Transform
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects
Improving accuracy in path delay fault coverage estimation
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Minimizing Energy Consumption for High-Performance Processing
Energy-Efficiency of VLSI Caches: A Comparative Study
A Unified Solution to Scan Test Volume, Time, and Power Minimization
A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access
Accurate Power Macro-modeling Techniques for Complex RTL Circuits
Combined Synthesis of Easily Testable Datapath and Control Designs
Efficient 3D Modeling Methodology for High-Speed Channels
Synthesis of Low Power High Performance Dual-VT PTL Circuits
Optical Waveguide Channel Routing with Reduced Bend-Loss for Photonic Integrated Circuits
Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout
A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications
A Semi-Digital Delay Locked Loop for Clock Skew Minimization
Floating Point Multiplication Mapping on ReRAM Based In-memory Computing Architecture
Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors
Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test
Tutorial T8B: Wireless System Design and Systems Engineering Challenges
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults
True Minimum Energy Design Using Dual Below-Threshold Supply Voltages
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation
Improvement of ASIC Design Processes
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode
FPGA Implementation of Low Power Parallel Multiplier
Design of Hardware Efficient Approximate DCT Architecture
Exploring the Number of Register Windows in ASIP Synthesis
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection
Tutorial T7B: Optimally Addressing Verification Constraint Complexity for Effective Functional Convergence
Automatic Model Refinement for Fast Architecture Exploration
Hardware Solution for Real-Time Face Recognition
Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking
Hierarchical Delay Fault Simulation
Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology
Testing Flash Memories
Automatic Device Layout Generation for Analog Layout Retargeting
Single Phase Dynamic CMOS POS PLA
2nd Order Sallen Key Switched Capacitor LPF with N-type Transistors
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors
Design of a Low Power, Variable-Resolution Flash ADC
A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise
Multiobjective Search in VLSI Design
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies
Security and Dependability of Embedded Systems: A Computer Architects' Perspective
A High Performance Gated Voltage Level Translator with Integrated Multiplexer
Integrated TIA-Equalizer for High Speed Optical Link
SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking
Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham's Razor
A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling
Low Power Sensor Node for a Wireless Sensor Network
Temperature-limited microprocessors: Measurements and design implications
Synthesis of Full-Adder Circuit Using Reversible Logic
Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces
An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS
Framework for Synthesis of Virtual Pipelines
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy
Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary
High-Level Synthesis with Variable-Latency Components
An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis
Adaptive Test Methods for High IC Quality and Reliability
Clockless Pipelining for Coarse Grain Datapaths
Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism
Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling
I DDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation
A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification
An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling
A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET
SOI Digital Circuits: Design Issues
Partial scan design for technology mapped circuits
Timing Yield Calculation Using an Impulse-Train Approach
Certifying Learning-Enabled Autonomous Cyber Physical Systems - A Deployment Perspective
Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Delay-Insensitive Carry-Lookahead Adders
11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India
Power Management for Mobile Multimedia: From Audio to Video & Games
Compact Modeling of Suspended Gate FET
Efficient FPGA Implementations of Lifting based DWT using Partial Reconfiguration
On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis
A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals
A Run-time Reconfiguration Algorithm for VLSI Arrays
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
Multiprocessor Architectures for Embedded System-on-chip Applications
A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification
Functional test generation for non-scan sequential circuits
High Speed Integrated A to D Converters
A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation
Input Referred Offset Reduction in Very High Speed Differential Receivers
A Sense Amplifier Based Bulk Built-In Current Sensor for Detecting Laser-Induced Currents
Generation of Asymmetric Triangular Pulse by A Dispersion and Nonlinearity Engineered Silicon Core Optical Fiber
Unguided Machine Learning-Based Computation Offloading for Near-Memory Processing
An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch
Distributed Diagnostic Simulation of Stuck-At Faults in Sequential Circuits
Novel Census Transform Hardware IP
Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic
Energy Aware Dynamic Load Balancer for Embedded Multi-core Systems
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults
New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets
Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors
Power Switch Network Design for MTCMOS
An Algorithm to Test Reconfigured RAMs
Off-Line Testing of Asynchronous Circuits
Property-Specific Testbench Generation for Guided Simulation
Front-End Design Flows for Systems on Chip: An Embedded Tutorial
Export of VLSI Design and CAD: Present and Future
Efficient Implementation of ADPCM Codec
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages
Elimination of Dynamic Hazards from Signal Transition Graphs
Conventional RC oscillators, though offer inexpensiveProgrammable High Frequency RC Oscillator
A Parallel VLSI Circuit Layout Methodology
Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology
VLSI implementation of variable resolution image compression
Optimization and Analysis Techniques for the Deep Submicron Regime
An Ultra-Fast, On-Chip BiST for RF Low Noise Amplifiers
Reliable High-Performance Programmable Voltage Regulator with 0.55A Sink Current for Cryo-Cooler Electronics in 0.18μm HV-CMOS Technology
A New Statistical Approach to Timing Analysis of VLSI Circuits
A Low-Complexity, Reduced-Power Viterbi Algorithm
A Low Power and Low Noise, Self Body Biased Low Noise Amplifier
Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control
A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC
Testing Flash Memories for Tunnel Oxide Defects
A System Approach to Energy Management
User-centric Resource Management for Embedded Multi-core Processors
Towards System level modeling and synthesis
TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products
Design and Testing of an Integrated Circuit for Multi-Electrode Neural Recording
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication
Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications
DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification
Robot Navigation Using Neuro-electronic Hybrid Systems
Low Power Asynchronous Data Acquisition Front End for Wireless Body Sensor Area Network
Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs
On the Generation of Weights for Weighted Pseudo Random Testing
Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network
Advances in VLSI Design and Product Development Challenges
Processor Architecture Design Using 3D Integration Technology
A Linear Systolic Array for LU Decomposition
A Scalable LDPC Decoder on GPU
Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design
Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
New CMOS Structures for the Synthesis of Dominant Functions
PAF-Enc: Position Affine Encoding to Reduce Bit-Flips in Non-Volatile Main Memories
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems
Implementing the Best Processor Cores
Knowledge-Guided Methodology for Third-Party Soft IP Analysis
erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering
Power Integrity Analysis for Interoperability of BoW Chiplet Interfaces
Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC
A Switch-Cap Regulator for SoC Applications
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters
Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects
A high-speed 32-bit parallel correlator for spread spectrum communication
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
New Net Models for Spectral Netlist Partitioning
Interconnection Delay and Clock Cycle Selection in High Level Synthesis
Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis
HIPER: Low Power, High Performance and Area-Efficient Hardware Accelerators for Hidden Periodicity Detection using Ramanujan Filter Banks
Self-Induced Supply Noise Reduction Technique in GBPS Rate Transmitters
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures
Dynamic Variable Ordering during Algebraic Backward Rewriting for Formal Verification of Multipliers
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter
Embedded Tutorial ET3: Packaging Trends, Die Package Co-Design Flow and Challenges
SOC Design for Wireless Communications
SIGMA: A VLSI Chip for Galois Field GF(2 m ) Based Multiplication and Division
Test generation for mixed-signal devices using signal flow graphs
Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell
Architecture of a Min-Max Simulator on MARS
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions
Analytical Expressions For Static Characteristics of Submicron CMOS Inverters
Feedback Biasing Based Adjustable Gain Ultrasound Preamplifier for CMUTs in 45nm CMOS
Energy Aware Computation Driven Approximate DCT Architecture for Image Processing
Understanding 2-Propanol Sensing Mechanism of Pd Modified Graphene Based Gas Sensor Devices using DFT Study
Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks
Efficient Macromodeling for On-Chip Interconnects
Challenges in Low Power Microprocessor Design
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design
A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications
Power Reduction of Functional Units Considering Temperature and Process Variations
Genetic Beam Search for Gate Matrix Layout
Fast Congestion Aware Routing for Pin Assignment
Buffer Design and Eye-Diagram Based Characterization of a 20 GS/s CMOS DAC
MIX: A Test Generation System for Synchronous Sequential Circuits
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors
Core Based ASIC Design
Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization
Memory-Centric Motion Estimator
Hierarchical Test Generation for Systems On a Chip
Embedding Security in Wireless Embedded Systems
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources
Power Scalable Digital Baseband Architecture for IEEE 802.15.4
High Level Design Validation: Current Practices and Future Directions
Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication
Physical Synthesis Optimization Prediction Using Machine Learning
Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
HEART: A Heterogeneous Energy-Aware Real-Time Scheduler
Active Cooling Technique for Efficient Heat Mitigation in 3D-ICs
Built-In Self-Test for Systems on Silicon
Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
A Memory Efficient 3-D DWT Architecture
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
Margin Propagation based Analog Soft-Gates for Probabilistic Computing
Hardware Efficient Architecture for Generating Sine/Cosine Waves
Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits
A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications