yusuke1997/dblp-id-title huggingface dataset:
DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization
Nonlinearity cancellation in digital PLLs (Invited paper)
A DAC-based Transmitter with VCSEL Bias-Current Generation enabling 180 Gbit/s PAM-8 Electrical and 100 Gbit/s PAM-4 VCSEL-based Transmission in 22nm SOI
A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS
A 500nA quiescent current, trim-free, ±1.75% absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETs
A 0.012mm 2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply
Chemical microsystem based on integration of microresonant sensor and CMOS ASIC
A 32nm 0.5V-supply dual-read 6T SRAM
A programmable floating-gate voltage reference in 0.5 μm CMOS
Dividerless Frequency Acquisition & Charge Pump Mismatch Compensation for Low-Power Millimeter-Wave Sub-Sampling PLL
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS
A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor
SiGe BiCMOS technology for communication products
Impact of technology scaling on CMOS RF devices and circuits
Low-voltage power-efficient operational amplifier design techniques - an overview
A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS
A high dynamic range ASK demodulator for passive UHF RFID with automatic over-voltage protection and detection threshold adjustment
A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancement
Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator
An Implantable Fully-Packaged Current-Controlled Wireless Near-Adiabatic Neural Stimulator Achieving 71.7% Peak Efficiency and 13.5% Efficiency Variation Across Supported Stimulation Current Range
A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS
Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration
A dual-band RF front-end for WCDMA and GSM applications
A 40nm 1.26µ/Op Energy-Efficient CRYSTALS-KYBER Post-Quantum Crypto-Processor with Comprehensive Side Channel Security Analysis and Countermeasures
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces
A scalable architecture for MPEG-4 embedded zero tree coding
An Emulated Peak/Valley Curve Assisted Fast-Transient Buck Converter Achieving Precise One-Cycle Charge Balance with One-Parameter Calibration
A 1.2A auto-configurable dual-output switched-capacitor DC-DC regulator with continuous gate-drive modulation achieving <0.01mV/mA cross regulation
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS
Test chips for die stress characterization using arrays of CMOS sensors
A millimeter-wave fully differential transformer-based passive reflective-type phase shifter
Autocorrelation analysis of distortion generated from bandpass nonlinear circuits
A novel CPLD based implementation of a motion detection algorithm for surveillance applications
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs
A 5-MHz 91% peak-power-efficiency buck regulator with auto-selectable peak- and valley-current control
A 9.3mV Load and 5.2mV Line transients Fast Response Buck Converter with Active Ramping Voltage Mode Control
MBus: A 17.5 pJ/bit/chip portable interconnect bus for millimeter-scale sensor systems with 8 nW standby power
Low power and error resilient PN code acquisition filter via statistical error compensation
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers
Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings
A 0.66 W/mm2 Power Density, 92.4% Peak Efficiency Hybrid Converter with nH-Scale Inductors for 12 V System
Mixed-signal stochastic computation demonstrated in an image sensor with integrated 2D edge detection and noise filtering
RF distortion analysis with compact MOSFET models
A novel switched-capacitor-filter based low-area and fast-locking PLL
A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps
A 93.6dB-SNDR 5kHz-BW Fully Dynamic Hybrid CT-DT Noise Shaping SAR ADC
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs
A bipolar >40-V driver in 45-nm SOI CMOS technology
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS
A dynamic timing control technique utilizing time borrowing and clock stretching
A 5mW 250MS/s 12-bit synthesized digital to analog converter
A circuit designer's guide to 5G mm-wave
PLC advanced technology demonstrator TestChipB
Effect of technology scaling on digital CMOS logic styles
An 80MS/s 70.79dB-SNDR 60.7fJ/Conv-Step Radiation-Tolerant Semi-Time-interleaved Pipelined-SAR ADC
A 64-67GHz partially-overlapped phase-amplitude-controlled 4-element beamforming-MIMO receiver
RC-triggered ESD clamp with low turn-on voltage
Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits
A broadband biosensor interface IC for miniaturized dielectric spectroscopy from MHz to GHz
A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting
A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL Technique
A slew rate-controlled output driver having a constant transition time over the variations of process, voltage and temperature
Analysis of deviation from Pelgrom scaling law in Vth variability of pocket-implanted MOSFET
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper
Frequency-scalable SiGe bipolar RFIC front-end design
Session 8 - Biomedical circuits and systems
A multiple-output fixed current stimulation ASIC for peripherally-implantable neurostimulation system
A Charge-Pump-based Digital LDO Employing an AC-Coupled High-Z Feedback Loop Towards a sub-4fs FoM and a 105, 000x Stable Dynamic Current Range
10× improvement of power transmission over free space using integrated antennas on silicon substrates
A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction
Mondriaan: a tool for automated layout synthesis of array-type analog blocks
A Current-Equalized Distributed Receiver Front-End for UWB Direct Conversion Receivers
Dynamic Data Stability in Low-power SRAM Design
A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS
A 9 - 45V Input 2MHz 3-Switch ZVS Step-up / -down Hybrid Converter with 5x Volume Reduction
A single chip AV decoder for the DVD player adopting the MCP architecture
A low conversion loss passive frequency doubler
ULP Receivers in Self-Powered Industrial loT Applications: Challenges and Prospects
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS
Will continued process-node shrinks kill high-performance analog design?
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0
A 0.5-V, 440-µW frequency synthesizer for implantable medical devices
Interference-immune diagnostic quality ECG recording for patient monitoring applications
A 5.5mA 2.4-GHz two-point modulation Zigbee transmitter with modulation gain calibration
A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology
A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC with Miniaturized Reconfigurable Supply Modulator and Channel Drivers for Cochlear Implants
The next generation BSIM for sub-100nm mixed-signal circuit simulation
A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5fj/conv-step
A highly linear low-power 10 bit DAC for GSM
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network
Demonstration of Logic-Block Performance-Power-Area Gain by 1 st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2 nm Node
Digital clock and data recovery circuit design: Challenges and tradeoffs
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006
A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD
An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOS
A 15b power-efficient pipeline A/D converter using non-slewing closed-loop amplifiers
Integrated DC-DC converter design
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias
A -173 dBc/Hz @ 1 MHz offset Colpitts oscillator using AlN contour-mode MEMS resonator
Nanoscale CMOS Implications on Analog/Mixed-Signal Design
A 12V/24V-to-1V Shared Switched-Capacitor Multi-Inductor Multi-Output Converter with 90.9%/89.5%Peak Efficiency and Negligible Cross Regulation
Injection-Locked Clocking: A New GHz Clock Distribution Scheme
A CMOS VLSI delay oriented waveform converter dedicated to the synthesizer of an UMTS transceiver
Integrated MEMS Switches for Leakage Control of Battery Operated Systems
On IIP2 Improvement by Injecting DC Offset at the Mixer in a Wireless Receiver
Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICE
A 2 V pp linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
A broadband 10 GHz track-and-hold in Si/SiGe HBT technology
A 94GHz Scalable 2 × 2 Phased-Array Receiver in SiGe BiCMOS for High Data-Rate Communication
Multi-Electroanalytical Method Capable, Duty-Cycled, 0.36 mm 2 Electrochemical Frontend, Achieving 170dB Current Sensing Range with Extended Compliance Voltage Adopting Feedforward Cancellation
A 6-18-GHz Reflectionless Blocker-Canceling Mixer-First Receiver with Maximum 55.6-dB Out-of-Band Rejection for Satellite Communication Systems
A 300 °C, 110-dB Sigma-Delta Modulator with Programmable Gain in Bulk CMOS
Combined transistor sizing with buffer insertion for timing optimization
A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers
Filters and amplifiers
A PMOS-Based Deep Cryogenic CMOS Temperature Sensor Achieving a Range from 10K to 410K with a Relative Inaccuracy of 0.5% (3σ)
MRAM and microprocessor system-in-package: technology stepping stone to advanced embedded devices
A Fast-Slow Two-Module DC-DC Solution with Transient and Efficiency Improvements for 2.5D/3D Integration
A 15-bit binary-weighted current-steering DAC with ordered element matching
A 1.6 GS/s Spectrum Channelizer with PWM-LO Based Sub-band Equalization
A 1.6-2.2GHz 23dBm low loss integrated CMOS duplexer
The effect of supply and substrate noise on jitter in ring oscillators
A novel FPGA architecture supporting wide shallow memories
A GFLOPS Vector-DSP for Broadband Wireless Applications
Embedded software in the SoC world. How HdS helps to face the HW and SW design challenge [hardware dependent software]
A 92.4% Efficient, 5.5V: 0.4-1.2V, FCML Converter with Modified Ripple Injection Control for Fast Transient Response and Capacitor Balancing
Modeling of passive elements and reliability
Oscillator phase noise: a tutorial
A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC
Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs
Automated design of switched-current cells
Band runlength coding for low-power continuous micro-monitors
Towards a sub-2.5V, 100-Gb/s Serial Transceiver
Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges
MOS transistor modeling for RF integrated circuit design
Session 10 - Panel discussion Sure, Moore's Law can continue, but should it
A 3.1-8.0 GHz MB-OFDM UWB transceiver in 0.18μm CMOS
Foundations for scaling beyond 14nm
Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement
An LPTV Noise Cancellation Technique for a 0.9-V Filtering-by-Aliasing Receiver Front-End with >67-dB Stopband Rejection
Scalable and Interpretable Brain-Inspired Hyper-Dimensional Computing Intelligence with Hardware-Software Co-Design
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT
A common-base linear rf power amplifier for 3G cellular applications
A 30-40 GHz 1: 16 Internally Matched SiGe Active Power Divider for Phased Array Transmitters
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency
A MPEG4 programmable codec DSP with an embedded pre/post-processing engine
A 65 μW, 1.9 GHz RF to digital baseband wakeup receiver for wireless sensor nodes
Multi-mode cellular transceivers for LTE and LTE-Advanced
Advances in the design of wideband receivers
A 12-bit integrated analog front-end for broadband wireline networks
A low-power highly-integrated MPEG1/2 audio layer 3 (MP3) decoder for CD-based systems
A low-power 1.92MHz CT ΔΣ modulator with 5-bit successive approximation quantizer
A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applications
UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies
Computing in 3D
Yield and Cost Modeling for 3D Chip Stack Technologies
A 159.2mW SoC implementation of T-DMB receiver including stacked memories
New Frontiers in Hardware Security in the IoT Regime
An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias
Analysis and demonstration of MEM-relay power gating
A 1.8V triode-type transconductor and its application to a 10MHz 3 rd -order Chebyshev low pass filter
A Integrated Dual Direct-Conversion Tuner Chip for Digital Satellite Application
Energy-efficient transceiver circuits for short-range on-chip interconnects
A Mm-Wave Phase-Time Co-Apertured Transceiver Array with Beam Squinting Mitigation for Wideband Beamforming/Spatial-Nulling
Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating
Session 11 - Wireline building blocks
An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability
Progress and future challenges of silicon carbide devices for integrated circuits
Magnetic-Tuning Millimeter-Wave CMOS Oscillators (Invited Paper)
A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors
Solutions for highly integrated future generation software radio basestation transceivers
Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM
A 400-to-12 V Fully Integrated Switched-Capacitor DC-DC Converter Achieving 119 mW/mm2 at 63.6 % Efficiency
Session 5 - Broadband circuit techniques for emerging wireless communications
SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration
Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications
Circuit techniques for miniaturized biomedical sensors
Session 9 - Broadband circuit techniques for emerging wireless communications
A 10mW 9.7ENOB 80MSPS pipeline ADC in 65nm CMOS process without any special mask requirement and with single 1.3V supply
Injection locking LC dividers for low power quadrature generation
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS
Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
A 166F2/bit 0.0136%-Native-BER Physically Unclonable Function Based on Gate-Overhang-Shortened Transistor
A Driving Scheme for AMOLED Displays Based on Current Feedback
A 70-V Fully Integrated Dual-SSHC Rectifier for Triboelectric Energy Harvesting with Full-Digital Duty-Cycle-Based MPPT Achieving 598% Power Extraction Enhancement
Fully-integrated 57 mV cold start of a thermoelectric energy harvester using a cross-coupled complementary charge pump
Design and implementation of an embedded 512KB level 2 cache subsystem
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, DoubleTree Hotel, San Jose, California, USA, September 21-24, 2008
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays
A low-phase-noise wide-tuning-range quadrature oscillator in 65nm CMOS
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator
A 220 GHz Sliding-IF Quadrature Transmitter With 38-dB Conversion Gain and 8-dBm Psat in 0.13-µm SiGe BiCMOS
SparseTrim: A Neural Network Accelerator Featuring On-Chip Decompression of Fine-Grained Sparse Model with 10.1TOPS/W System Energy Efficiency
A 0.24mm2 Bridge-less Hybrid SSHI Interface Circuit for Piezoelectric Energy Harvesting with a Wide Load Range and Up to 1620% Power-Extraction Improvement
A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm
Design of miniaturized wireless power receivers for mm-sized implants
Low leakage circuit design for FPGAs
A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS
Chip to carrier C4 technology challenges with Pb free solders
A high performance CMOS programmable logic core
A Scalable Model Methodology for Octagonal Differential and Single-Ended Inductors
An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection
A baseband integrated circuit for homodyne cordless phones
Noise analysis of non-linear dynamic integrated circuits
Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits
Randomized Switching SAR (RS-SAR) ADC Protections for Power and Electromagnetic Side Channel Security
Hybrid PLL architectures and implementations
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs
A 415 nW Physically and Mathematically Secure Electro-Quasistatic HBC Node in 65nm CMOS for Authentication and Medical Applications
CMOS scaling and three-dimensional silicon integration
A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology
Electrically-driven retargeting for nanoscale layouts
Power network analysis for ESD robustness in a 90nm ASIC design system
An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiers
85-to-127 GHz CMOS transmitter for rotational spectroscopy
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling
A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology
A wideband tunable CMOS channel-select filter for a low-IF wireless receiver
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors
Behavioral modeling for RF and AMS
A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization
Hierarchical watermarking for protection of DSP filter cores
A bidirectional lens-free digital-bits-in/-out 0.57mm 2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication
A 200MHz-BW 0.13mm 2 62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS
Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding
Energy centric model of SRAM write operation for improved energy and error rates
A new algorithm for computing the "effective capacitance" in deep sub-micron circuits
A fully integrated electroencephalogram (EEG) analog front-end IC with capacitive input impedance boosting loop
An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOS
Progress and outlook of lithography for semiconductor IC
Performance and reliability of asymmetric LDD devices and logic gates
High-efficient DC-DC converter design
Schematic driven module generation for analog circuits with performance optimization and matching considerations
A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology
A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor
A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices
A mixed-domain modeling method for RF systems
Analysis and IC Techniques of Wireless Power Transfer Circuits
The embedded SCR NMOS and low capacitance ESD protection device
A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules
Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS
Reliability modeling of HK MG technologies
Educational session 1-2: Time interleaved ADCs requirements vs. application
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology
Re-inventing the DRAM for embedded use: a compiled, wide-databus DRAM macrocell with high bandwidth and low power
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS
CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications
FireBird: PowerPC e200 based SoC for high temperature operation
Process variation in nano-scale memories: failure analysis and process tolerant architecture
RASP 2.8: A new generation of floating-gate based field programmable analog array
A 58dB SNR 6 th order broadband 10.7 MHz SC ladder filter
An ultralow power single-chip CMOS 900 MHz receiver for wireless paging
LEIA: A 2.05mm 2 140mW lattice encryption instruction accelerator in 40nm CMOS
A 0.622-10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS
A new generation of DSP architectures
A 27μW subcutaneous wireless biosensing platform with optical power and data transfer
A passive UHF tag for RFID-based train axle temperature measurement system
Photoplethysmography (PPG) Sensor Circuit Design Techniques
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging
Mixed-signal quadrature demodulator with a multi-carrier regeneration system
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology
A 980μW 5.2dB-NF current-reused direct-conversion bluetooth-low-energy receiver in 40nm CMOS
Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access
A Calibration-Free 13b 625MS/s Tri-State Pipelined-SAR ADC with PVT-Insensitive Inverter-Based Residue Amplifier
10+ Gb/s 90nm CMOS serial link demo in CBGA package