yusuke1997/dblp-id-title huggingface dataset:
Design of Convolutional Neural Network for Classifying Depth Prediction Images from Overhead
Time-interleaved sample clock generator for ultrasound beamformer application
Leveraging Algorithm-based Fault Tolerance for Propagation Error Detection in NPUs
The Design of Embedded Fuzzy Logic Controller for Autonomous Mobile Robots
Extracting the frequency response of switching DC-DC converters in CCM and DCM from time-domain simulations
Effective readout pixel sensor circuit design for infrared focal plane array and three-dimension image MEMS VLSI system
A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator
RSCE-aware ultra-low-voltage 40-nm CMOS circuits
Neural network based seizure detection system using raw EEG data
Power Reduction Techniques for Energy-Efficient Audio Continuous-Time Delta-Sigma Modulator
Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements
Memory efficient self guided image filtering
A 0.4-VIN, External-Capacitor-Free, Adaptive-Biased LDO with Look-Ahead Droop Reduction for Wake-up Features in Edge Devices
A system-level design of MapReduce-based embedded multiprocessor system-on-chips
Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis
Joint Generative Network for Abnormal Event Detection in Surveillance Videos
Opportunities and Challenges of DRAM-based Computing-in-Memory for AI Accelerator
P-backtracking: A new scan chain diagnosis method with probability
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI
Design and analysis of a power-efficient cascode-compensated amplifier
Power Integrity Specification Definition for an Integrated Clock Circuit Design
Real-time stereo matching for 3D hand gesture recognition
A pipeline ROM-less DDFS using equal-division interpolation
Low Phase Noise Voltage-Controlled Oscillator with Self-Biased Negative-Gm Cell for IoT Applications
Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL
Digitally Programmable Gain and Tunable Band-Width DPOTA based Bio-medical Amplifier
Considerations in Evaluation of Deep Hashing Networks for Information Retrieval System
A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem
Convolutional neural network for industrial egg classification
Mobile phone antenna
An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process
A 288nV/√Hz low-noise capacitively-coupled instrumentation amplifier (CCIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors
Approximate stochastic computing (ASC) for image processing applications
Design of high dimming ratio power-LED driver with preloading inductor current methodology
Improved Nagata Current Source Insensitive to Temperature and Power Supply Voltage
A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory
Feed-Forward Control of PAM4 CTLE for Optical Receivers Based on a Step Response Analysis
Design of low-power receiver front-end IC for low-frequency wireless time signal broadcast system
A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process
A design of ultra low power I2C synchronous slave controller with interface voltage level independency in 180 nm CMOS technology
A Novel Global Maximum Power Point Tracking Technique based on Shading Detection for Photovoltaic Strings
Tensor Compressive Sensing Processor for 64x64 Terahertz Single-Pixel Imaging
A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers
A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications
First-order Continuous Time Delta-sigma Modulator with 3-bit SAR ADC and PNM DAC
International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017
Programmable of a Frequency for Concurrent Driving Signals of Touch Screen Controller
A Linear Array Mutual Coupling Compensation Technique for Angle of Arrival Estimation
Hardware Implementation of Minimum Filter based on 2-D Cumulative Histogram
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT
A FPGA-based neural accelerator for small IoT devices
Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition
Path search engine for fast optimal path search using efficient hardware architecture
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration
Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells
Cell-based delay locked loop compiler
Image acquisition design of the AOTF imaging spectrometer based on SOPC
A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier
10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control
10 Gb/s Energy-efficient Optical Transceiver using 1060 nm HCG MEMS-tunable VCSEL in 28 nm FD-SOI Technology
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface
Estimation of Leakage Distribution Utilizing Gaussian Mixture Model
Improved Accuracy of Stochastic Accumulator Using Low-Cost Bitonic Sorter
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs
Early Termination of STDP Learning with Spike Counts in Spiking Neural Networks
Hardware design exploration of fully-connected deep neural network with binary parameters
A novel analog-to-residue converter for biomedical DSP application
Implementation of Low complexity inter prediction for IoT systems
Analysis of Test Environment Configuration for High-Speed Link Chip Measurement
A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication
PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems
CNN inference simulator for accurate and efficient accelerator design
Diagnosis of Scan Chain Faults Based-on Machine-Learning
A novel charge recovery logic structure with complementary pass-transistor network
Security analysis of intelligent vehicles: Challenges and scope
Fusion for Tile-based Deconvolution Layers
Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors
A novel sequential tree algorithm based on the status of the processing nodes to reduce congestion
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling
Differential Gaze Estimation with Ocular Counter-Rolling Compensation
A Sub-1-mW Fractional-N Phase-Locked Loop For Mixer-Based Wake-up Receiver In Wireless Sensors
A Framework for Detecting the Presence of an Unattended Child in a Vehicle
An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference
Division-less high-radix interleaved modular multiplication using a scaled modulus
A hardware-efficient ergodic sequential logic neuron network for brain prosthetic FPGA
A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC
High-Quality HTTP Live Streaming System for Limited Communication Bandwidth
Hardware Design of Optimized Large Integer Schoolbook Polynomial Multiplications on FPGA
Memory-like Defect Diagnosis for CMOL FPGAs
Design of 100 GHz OOK Transceiver in 28nm CMOS Process for High Speed Communication
An Approximate Multiplier Design Based on Mitchell's Algorithm
Memristor-based Neuromorphic Implementations for Artificial Neural Networks
High Voltage Driver with Multiple Outputs Capable of Independent PWM Control
ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on Pytorch
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs
An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifier
Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach
Design-time energy optimization for asymmetric multiprocessor system-on-chip
60-GHz voltage-controlled oscillator and frequency divider in 0.25-µm SiGe BiCMOS technology
Digital Controller Implementation of Grid-Tied Zeta Inverter Using 16-bits Microcontroller
An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers
Low-cost SDR-based Reader for Chipless Sensor Tag
High efficiency multi-channel LED driver based on SIMO switch-mode converter
A 4-way Matrix Multiply Unit for High Throughput Machine Learning Accelerator
Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing
Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM
A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators
A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems
A 10-Gb/s equalizer with digital adaptation
Low-latency area-efficient decoding architecture for shortened reed-solomon codes
Quantum Biometric Fingerprint Encryption based on Twofish Algorithm
Normally-off power management for sensor nodes of global navigation satellite system
Automatic Shading Detection System for Photovoltaic Strings
Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS
An Energy Efficient Period-modulation-based Current-to-digital Converter for FET-type Sensors
On Exploring Non-negative Matrix Factorization for Deep Neural Network Compression
Design of 32-bit Processor for Embedded Systems
Lego: Dynamic Tensor-Splitting Multi-Tenant DNN Models on Multi-Chip-Module Architecture
Analysis of predictive coding model with hierarchical reservoir computing for modeling Stroop effects
Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function
Power Side-Channel Analysis for Different Adders on FPGA
A Wide Range Digitally Controlled Oscillator with Direct Proportional Loop Control
Electro-Optical Phase Locked Loop design for FMCW LiDAR TX in 28-nm CMOS
Search-Efficient NAS: Neural Architecture Search for Classification
A low-cost, ultra sensitive hand-held system for explosive detection using piezo-resistive micro-cantilevers
Hardware implementation of fast traffic sign recognition for intelligent vehicle system
A Resilient All-Digital PLL Using Ping-Pong Delay Line
Development of an IoT-based Aquaponics Monitoring and Correction System with Temperature-Controlled Greenhouse
A flexible software defined radio-based UHF RFID reader based on the USRP and LabView
Optimized Instruction Set Architecture for Programmable Memory Test Pattern Generation
2 b-sigmoid and 2 b-tanh: Low Hardware Complexity Activation Functions for LSTM
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs
A Two-stage Training Mechanism for the CNN with Trainable Activation Function
A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-nm CMOS
A fast Multi-scale Retinex algorithm using dominant SSR in weights selection
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension
Anomaly information detection and fault tolerance control method for CAN-FD bus network
A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio
Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects
A TDC-based skew compensation technique for high-speed output driver
An efficient dual-supply design for low-power mobile systems
Online Machine Learning-based Temperature Prediction for Thermal-aware NoC System
Bit-Serial multiplier based Neural Processing Element with Approximate adder tree
Variable Length MAC for CAN Security Protocol
50 MHz 3-Level Buck Converter with added Boost Converter
Implementation of Activation Functions using various approximation methods
An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition
Low latency IFFT design for 3GPP LTE
Development of an IoT-based visitor detection system
A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption
2 β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance
3D network-on-chip with wireless links through inductive coupling
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor
A 24-28GHz Reconfigurable CMOS Power Amplifier in 22nm FD-SOI for Intelligent SoC Applications
Traffic sign detection and identification using SURF algorithm and GPGPU
High resolution tactile sensing with silicon MEMS sensors for measurement of fingertip sensation
A Design of Low Inrush Current Low Dropout Regulator Using the Method of Pre-charging the Load
VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick
A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCs
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems
A Spatio-Temporal Switchable Data Prefetcher for Convolutional Neural Networks
Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache
Reducing Refresh Overhead with In-DRAM Error Correction Codes
Cooperation of multi robots for disaster rescue
An efficient GPIO block design methodology using formalized SFR description
DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration
Exploring Hot/Cold Data Separation for Garbage Collection Efficiency Enhancement on OCSSDs
A vector coprocessor architecture for embedded systems
Low Cost Early Exit Decision Unit Design for CNN Accelerator
Maximizing Power Saving Through State-Driven Clock Gating
A quick overview of carbon nanotubes and graphene applications for future electronics
Dense stereo-based real-time ROI generation for on-road obstacle detection
A Morphological Image-based Recognition of Iron Triad using a Convolutional Neural Network
Bionic Sypantic Application of OxRRAM Devices
Investigation for Impact of Environmental Noise on Power Analysis Attacks
Pedestrian detection and tracking using deformable part models and Kalman filtering
Object Detection Network Robust to Local Illumination Variations
Bifurcation analysis of a chaotic interrupted system with a periodic threshold
A design of ultra-low noise LDO using noise reduction network techniques
A fine-grained timing driven synthesis of arithmetic circuits
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver
The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network Applications
Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank Approximation
Improving Performance of Current Sensor Chip Based on Multi-Parameter Compensation : Compensation & Decimation Filter for Digital Chip
An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm 2
A Test Methodology for Neural Computing Unit
Buck DC-DC converter with PFM/PWM dual mode self-tracking zero current detector
A CMOS bandgap voltage reference with current-control circuits for the extended operating temperature range
Design of highly stable bandgap reference circuit for RF power harvester module of a 13.56 MHz smart card tag IC
Implementation of Multi-Channel FM Repeater using Digital Signal Processing Algorithm in FPGA
A new repair scheme for TSV-based 3D memory using base die repair cells
Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis
Emulation of processing in memory architecture for application development
Optimization Technique of Memory Traffic for FPGA-Based Image Processing System
A Programmable DLL-based Delay Chain
Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics
Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period
A high efficiency piezoelectric energy harvesting system
Monocular Depth Estimation with Optical Flow Attention for Autonomous Drones
Layer-wise Pruning of Transformer Attention Heads for Efficient Language Modeling
Design time stamp hardware unit supporting IEEE 1588 standard
On-Device Eye Tracking System with Dual Lightweight AI Processor
Noise-Aware and Lightweight LSTM for Keyword Spotting Applications
The Sparsity and Activation Analysis of Compressed CNN Networks in a HW CNN Accelerator Model
The Analysis of CNN Structure for Image Denoising
A Simple Up-and-Down Weight Update Method for Tiny 8-bit Quantized CNN Training
A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions
Memory ECC architecutre utilizing memory column spares
A digital low-dropout(DLDO) regulator with 14dB power supply rejection enhancement
Frustrated Complex Networks of Nonlinear Circuits With Stochastically Coupling
Efficient Hardware Implementation of Nonlinear Activation Function For Inference Model
Modified Wilkinson Power Divider with Resonating Stubs for Physical Isolation of Output Ports
CPR: Correlation-based Page Remapping
A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator
Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation
Modeling of second order continuous-time sigma delta modulator in LabVIEW
Design of Class-Φ3 Inverter
Current mode four-quadrant multiplier design using CNTFET
A High Input Impedance Low Noise Amplifier Capable Of Handling 1V Electrode Offset for Biopotential Recording
High-performance two-step lagrange interpolation technique for 4K UHD applications
Analyses of nonlinear transient phenomena of ergodic cellular automaton central pattern generator
A Current-link CMOS Analog Neuron with Simplified Synapse Using a Merged Switch Array
Low Power High Speed Body Driven Comparator for Implantable Electronics
Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow
Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology
Target voltage independent capacitance measurement circuit implemented by 0.18 µm CMOS for PWM-MEMS control
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme
Boosted gain programmable Opamp with embedded gain monitor for dependable SoCs
Mitigating Write Amplification of Dual-mode Flash Memory
A design of 10MHz/20MHz bandwidth baseband circuit with high performance of ACRR
Design of a 3D-IC based AI-Vision SoC
Development of a reduction algorithm for CAN frame bits
Triple-Rail Stochastic Number and Its Applications
Lookup Table and Neural Network Based Decoders for Real Time Quantum Error Correction
Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control
A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system
DDS-PLL Architecture for Adaptive Beam Steering
A low-power SerDes for high-speed on-chip networks
A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts
High performance and low power timing controller design for LCoS microdisplay system
Suppression of Chaos Propagation in Ladder Chaotic Circuits by Local Switching of Coupling Strength
A 0.5-V 320 μW CMOS MedRadio receiver RF front-end with a current-reuse gw-boosting common gate low noise amplifier
FPGA Implementation of Hybrid Karatsuba Multiplications for NIST Post-Quantum Cryptographic Hardware Primitives
System-level simulation acceleration for architectural performance analysis using hybrid virtual platform system
Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders
FPGA power estimation simulator for dynamic input data
Optimized Image Quality Determination for Backlight Dimming
Dehazing in color filter array domain
A GaN Driver IC With a TDC-Based Dead-Time Controller For GaN DC-DC Buck Converters
UCP: A Unified Cryptographic Processor for High Performance and Low Power Security Applications
Design of State of Charge and Health Estimation for Li-ion Battery Management System
A new scheme for secret-hiding in DSP circuits
Implementation of a Round Robin Processing Element for Deep Learning Accelerator
Design of multi-core rasterizer for parallel processing
Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network
Stereo vision-based Collision Avoidance for Unmanned Systems
Stochastic Edge Detection for Fine-Grained Progressive Precision
Performance aware partitioning for 3D-SOCs
Low Cost Hand Gesture Control in Complex Environment Using Raspberry Pi
High Quality Power-Aware Verification of Mixed Signal designs using UPF checkers
A Wideband Differential VCO Based on Multiple-path Loop Architecture
Application of Blind-Signal-Processing Algorithm in Image Separation - Blind-Signal-Processing in Image Separation
Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image Processing
An ultra-low-power 2.4 GHz receiver RF front-end employing a RF quadrature Gm-stage for Bluetooth low energy applications
Variation-aware aging analysis with non-Gaussian parameters
Instant and Accurate Instance Segmentation Equipped with Path Aggregation and Attention Gate
Integrating CNN and RCE Networks for Efficient On-Device Image Classification
Parallel in-order execution architecture for low-power processor
A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes
A novel scheme for information hiding at physical layer of wireless communications
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL
Performance Evaluation of a RISC-V CPU at Cryogenic Temperature for Future Quantum Control
Design of a High Performance RF Energy Harvester for Wide Input Power Range
Low power BCH decoder using early termination scheme for WBAN standard
Investigation of the Effect of Adding Random Noise to Noisy Biological Signals on the Classification of Neural Network
Effective Software Scheme of the Space Vector Modulation Using One-Chip Micro-Controller
Parallel architecture for concatenated polar-CRC codes
Artificial neural network implementation in FPGA: A case study
A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology
Possibility verification of drone detection radar based on pseudo random binary sequence
Facial expression recognition system using machine learning
Lightweighted AI-based Inference using Deterministic Randomness Compensation for Microcontroller ADC Resolution Enhancement
Resistive Switching Behavior of Solution-Processed AlOx, based RRAM with Ni and TiN Top Electrode at Low Annealing Temperatures
A loosely-coupled binding model for Wireless Sensor Networks
Adaptive Tag Comparison for Hybrid Cache
Implicit Hardware Trojan: Principles and Enabling Methods
Implementation of CNN based Demosaicking on FPGA
A wideband differential VCO based on double-short-path loop architecture
Highly-efficient parallel convolution acceleration by using multiple GPUs
A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS
System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles
Memory-Centric Architecture of Neural Processing Unit for Edge Device
Early HW/SW Co-Verification Using Virtual Platforms
Application specific processor for multi-standard video decoding
Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory
Parallel decoding for multi-stage BCH decoder
Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems
Design of timing-error-resilient systolic arrays for matrix multiplication
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor
A fully integrated high-efficiency step-up DC-DC converter for energy harvesting applications