yusuke1997/dblp-id-title huggingface dataset:
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014
Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead Analysis
State-of-the-Art in Rapid Prototyping
A security aware routing approach for NoC-based MPSoCs
A 1-MHz, 24-ppm/°C fully-integrated RC relaxation clock reference using 180 nm open-source PDK
Reliability by Design: Avoiding Migration-Induced Failure in IC Interconnects
Future Design Tools for Platform FPGAs
Run-time Cache Configuration for the LEON-3 Embedded Processor
SRAM-based FPGAs: A Structural Test Approach
A Cross-Layer Approximate Kernel for Gaussian Filtering
A ultra low power CMOS pA/V transconductor and its application to wavelet filters
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model
High performance silicon MEMS for niche market applications
Energy-aware scheduling in transactional memory systems
Hardware Implementation of a Sliding Detection Algorithm for Robotic Hands Using Force Sensors
Design and Optimization of High Sensitivity Transimpedance Amplifiers in 130 nm CMOS and BiCMOS Technologies for High Speed Optical Receivers
Jale3D - Platform-independent IC/MEMS Layout Edition Tool
Low-power multi-size HEVC DCT architecture proposal for QFHD video processing
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator
Partitioned Branch Condition Resolution Logic
A low-voltage bandgap reference source based on the current-mode technique
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
Dual-standard BiCMOS LNA for DCS1800/W-CDMA applications
Efficient IC Design of SC Decimation Filters
Architecture and CAD for FPGAs
Body-bias compensation technique for SubThreshold CMOS static logic gates
A Consumer Report on BDD Packages
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
Capacitor Charge Control Technique Applied to Digitally Programmable IIR Switched-Capacitor Filter
A precision autozero amplifier for EEG signals
Push-Pull Based Operational Transconductor Amplifier Topologies for Ultra Low Voltage Supplies
SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS
Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC
CMOS Transconductor Analysis for Low Temperature Sensitivity Based on ZTC MOSFET Condition
A PLL for clock generation with automatic frequency control under TID effects
A 2.7ua sub1-v voltage reference
An Integrated Circuit for the in Situ Characterization of CMOS Best-Process Micromachining
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007
A -40 to 250°C Triple Modular Redundancy Temperature Sensor for Turbofan Engines
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2001, Pirenopolis, Brazil, September 10-15, 2001
Computationally-Efficient Neural Image Compression Using Asymmetric Autoencoders
Low power IEEE 802.11ah receiver system-level design aiming for IoT applications
JADE: An Embedded Systems Specification, Code Generation and Optimization Tool
Hardware and software infrastructure to implement many-core systems in modern FPGAs
Using majority logic to cope with long duration transient faults
Design of high speed digital circuits with E-TSPC cell library
PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform
Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder
Topological Parameters for Library Free Technology Mapping
Functional verification of an MPEG-4 decoder design using a random constrained movie generator
An XML Format Based Integration Infrastructure for IP Based Design
A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference
A Case Study for a WWW based CAD Framework
Circuits for Low Power Consumption in GaAs Technology
Internet-based Training of Reconfigurable Technologies
Time-domain analog signal processing techniques
A Constraint Management System for IC Physical Design
CMOS OTA Sizing Using ACM Model in a Graphical Approach
Bus encoding schemes for minimizing delay in VLSI interconnects
ByZFAD: a low switching activity architecture for shift-and-add multipliers
A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering
Differential Evolution to Reduce Energy Consumption in Three-Level Memory Hierarchy
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing
Testability Properties of BDDs
Testing the Printability of VLSI Layouts
MCML Gate Design for Standard Cell Library
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, SBCCI 1998, Rio de Janiero, Brazil, September 30 - October 2, 1998
Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable
Design of Low-Power 5.8-GHz ULV LNTAs using Normalized Biasing Metric
A new march sequence to fit DDR SDRAM test in burst mode
SiGe HBT mm-Wave DC Coupled Ultra-wide-band Low Noise Monolithic Amplifiers
Design for reality: knowledge discovery in design and test data
A novel hybrid polarization-quadrature pixel cluster for local light angle and intensity detection
Modeling of a MOS ultralow voltage oscillator: experimental results
Cache coherency communication cost in a NoC-based MPSoC platform
Suppression of delta-sigma DAC quantisation noise by bandwidth adaptation
Low-Voltage Class AB Operational Amplifier
On the design of very small transconductance OTAs with reduced input offset
Noise and reliability in advanced CMOS devices for low power applications
RABBIT - A Modular Rapid Prototyping Platform for Distributed Mechatronic Systems
Employing Approximate Storage for Rate-Distortion Optimization in VVC Encoders
Using MDE for the formal verification of embedded systems modeled by UML sequence diagrams
A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems
Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model
Optimization Methodology for a 460-MHz-GBW and 80-dB-SNR Low-Power Current-Mode Amplifier
Combination of radix-2 m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers
Operation in Space of Artificial Neural Networks Implemented by Means of a Dedicated Architecture based on a Transputer
On the energy-efficiency of software transactional memory
A 0.7V Fully Differential First Order GZTC-C filter
Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning
Multi-bit flip-flop usage impact on physical synthesis
10 mV: 1V Step-up Converter for Energy Harvesting Applications
SisECO: Design of an Echo-Canceling IC for Base Band Modems
Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization
On the design of micro power practical GmC filters for biomedical applications
A Two-level Pipelined Implementation of the IDEA Cryptographic Algorithm
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos
A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System Solving
Extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response
Improving Error Correction Efficacy by Applying Nesting Encoding Approach
Repeater and Interconnect Strategies for High-Performance Physical Designs
Power-Aware Design of Electronic System Level using Interoperation of Hybrid and Distributed Simulations
A self-adaptable distributed DFS scheme for NoC-based MPSoCs
LogosPGA: Synthesis System for LUT Devices
Communication Architectures for System-on-Chip
A Modular and Distributed Impedance Control Architecture on a Chip for a Robotic Hand
Zero logic overhead integration of partially reconfigurable modules
A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding
SystemC: From Language to Applications, from Tools to Methodologies
Application driven traffic modeling for NoCs
FPGAs for Network Function Virtualization: Challenges in Placement and Partitioning
CMOS Bandgap with Base-Current Thermal Compensation
Efficient hardware implementation of the Richardson-Lucy Algorithm for restoring motion-blurred image on reconfigurable digital system
A CMOS continuous variable gain low-noise amplifier(LNA) for WLAN applications
Transistor sizing in lithography-aware regular fabrics
Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs
Implementation of dispatching algorithms for elevator systems using reconfigurable architectures
Exploiting cache locality to speedup register clustering
A reconfigurable platform for multi-service edge routers
Bias Dependence of Noise Correlation in MAGFETs
Broker Fault Recovery for a Multiprocessor System-an-Chip Middleware
CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC
Transfer characteristics and high frequency modeling of logic gates using carbon nanotube field effect transistors (CNT-FETs)
Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs
A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns
Inserting permanent fault input dependence on PTM to improve robustness evaluation
An optimized hybrid approach to provide fault detection and correction in SoCs
A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision Trees
An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification
An analog RF fully differential common mode controlled delay line in 28nm FDSOI technology
Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless Applications
Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus Parallel
A very low power area efficient CMOS only bandgap reference
Traffic generation and performance evaluation for mesh-based NoCs
Platform-Independent Hardware Design for Low-Power Neural Video Hyperprior Decoding
Self-Verification as the Key Technology for Next Generation Electronic Systems
A Novel Limiter with Application in Crest Factor Reduction Techniques for Wireless Communications
An Integrated High-Level Test Synthesis for Built-in Self-Testable Designs
Synthesis of threshold logic gates to nanoelectronics
Impact of ESD Protection and Power Supply Decoupling on 10 GHz Low Noise Amplifier
Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs
Analysis and Design of a MOS RF Envelope Detector in All Inversion Regions
A Study of Motion Coding Schemes for Learned Video Compression
Run-time reconfigurabilility and other future trends
Exploiting approximate computing for low-cost fault tolerant architectures
Power Management Exploration for a Block Turbo Decoder
Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis
A mutual rectification-interference avoidance technique with cascade filters for both downward-direction tailed-RDF deconvolution
Dynamic NoC-based architecture for MPSoC security implementation
Pipelined Entropy Coders for JPEG Compression
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009
An efficient ME architecture for high definition videos using the new MPDS algorithm
A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems
Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs
Deriving Reduced Transistor Count Circuits from AIGs
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis
Design-oriented delay model for CMOS inverter
A BIST Procedure for Analog Mixers in Software Radio
On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
System-Level Object-Orientation in the Specification and Validation of Embedded Systems
FPGA Placement: Dynamic Decision Making Via Machine Learning
Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF
Ant colony based routing architecture for minimizing hot spots in NOCs
A comparative study of CMOS gates with minimum transistor stacks
Going beyond TMR for protection against multiple faults
Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends
Reducing Test Application Time through Interleaved Scan
Router architecture for high-performance NoCs
Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs
System concept for an FPGA based real-time capable automotive ECU simulation system
Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applications
Task sheduling for power optimisation of multi frequency synchronous data flow graphs
System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications
Focal plane processors & pixel level processing: mimicking natural vision systems to solve image processing problems
Real-Time UHD 4K Hardware Design for the Gradient-Based Search of the VVC Affine ME
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology
A Co-Synthesis Approach based on Symbolic Reachability Analysis
Metal filling impact on standard cells: definition of the metal fill corner concept
Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router
A Simplified Methodology for the Extraction of the ACM MOST Model Parameters
Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE
A Novel SPICE Model of Memristive Devices with Threshold Current Based Control
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
Uncorrelated Pseudo-Random Generator for FPGA
Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization
High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package
Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore
A class-J power amplifier for 5G applications in 28nm CMOS FD-SOI technology
A decoder with soft decoding capability for high-rate generalized concatenated codes with applications in non-volatile flash memories
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications
A balanced logic routing block for Factorial-DLL based Frequency Generation
Efficient Thread Tuning for Asymmetric Multicores
Design of a Dynamic Obfuscation-Based Strong PUF Resistant to Modeling Attacks
Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case
A methodology for the automatic design of operational amplifiers including yield optimization
A survey of multistep A to D converters and error correction mechanisms
CLEVER: Cross-Layer Error Verification, Evaluation and Reporting
Memory and communication driven spatio-temporal scheduling on MPSoCs
Analytical logical effort formulation for minimum active area under delay constraints
A Study on a Garbage Collector for Embedded Applications
Placement of intermodule connections on partially reconfigurable devices
Topological impact on latency and throughput: 2D versus 3D NoC comparison
A Graph-Oriented CAD Tool for Establishing the Topological Diagnostic Conditions of Analogue Circuits
An efficient memory hierarchy for full search motion estimation on high definition digital videos
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006
Behavioral Modeling of Analogue and Mixed Integrated Systems with VHDL-AMS for RF Applications
A low complexity image compression solution for onboard space applications
Impact on Delay, Power and Area of Machine Learning-based Approximate Logic Synthesis
On the dynamic behavior of a novel digital-only sigma--delta A/D converter
Exploiting Java through binary translation for low power embedded reconfigurable systems
Energy-Efficient Execution of Parallel Regions on Heterogeneous Multi-Cores
Low Power Bulk-Driven OTA Design Optimization Using Cuckoo Search Algorithm
Automatic generation of test sets for SBST of microprocessor IP cores
Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems
Implementation of split-radix FFT pruning for the reduction of computational complexity in OFDM based cognitive radio system
Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity
Modeling an E1/TU12 Mapper for SDH Systems
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes
A high-speed low-power CMOS comparator using auto-zero offset cancellation technique
A Comparison of OO and Reactive Based Specifications on the Design of Embedded Systems
CAM/TCAM - NML: (ternary) content addressable memory implemented with nanomagnetic logic
Micro Power CMOS Analog Cells
A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor Array
Bit-Width Optimized Transposition Buffer Design for the AV1 2D-DCT Transform
A New Architecture for 2's Complement Gray Encoded Array Multiplier
Low-power inter-core communication through cache partitioning in embedded multiprocessors
Design validation of multithreaded architectures using concurrent threads evolution
Unified Theory to Build Cell-Level Transistor Networks from BDDs
A 25-dBm 1-GHz Power Amplifier Integrated in CMOS 180nm for Wireless Power Transferring
The interval page table: virtual memory support in real-time and memory-constrained embedded systems
A simplified executable model to evaluate latency and throughput of networks-on-chip
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008
Mapping and Migration Strategies for Thermal Management in Many-Core Systems
FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector
A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder
On Designing Mixed-Signal Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies
An ultra low power low voltage linear PMU for portable applications
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC
CentroidM: a centroid-based localization algorithm for mobile sensor networks
Highly improved IIP2 direct conversion receiver
Microelectronics Education using WWW and CAD Tools
Methodology for an Early Exploration of Embedded Systems using Portable Test and Stimulus Standard
Advanced technology mapping for standard-cell generators
Top-down design for Low power Multi-bit Sigma-Delta Modulator
A novel AES cryptographic core highly resistant to differential power analysis attacks
An efficient test and characterization approach for nanowire-based architectures
RoSA: a reconfigurable stream-based architecture
High-speed CMOS analog-to-digital converter for front-end receiver applications
NMLSim 2.0: a robust CAD and simulation tool for in-plane nanomagnetic logic based on the LLG equation
A small area 8bits 50MHz CMOS DAC for bluetooth transmitter
Time-interleaved pipeline ADC design: a reconfigurable approach supported by optimization
Approximate Radix-2 m Bit-Leading-Based Adder
Optimizing BDD-Based Verification Analysing Variable Dependencies
Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function
A statistical power estimation methodology embedded in a SystemC code translator
Design of Oscillator and Charge Pump for the Startup of Ultra-Low-Voltage Energy Harvesters
Energy-Efficient Register Access
A Petri Net Based Approach for Hardware/Software Partitioning
Fine-grain temperature monitoring for many-core systems
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, SBCCI 2017, Fortaleza, Ceará, Brazil, August 28 - September 01, 2017
On-chip 4to20mA reconfigurable current loop transmitter for smart sensor applications
A JAVA-Based Mixed-Signal Design Environment
Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations
Energy Aware Demodulation Implementation with Fixed Point Adaptive Precision for OFDM Systems
Evaluation of Compiler Optimization Flags Effects on Soft Error Resiliency
An MPEG-2 transport stream demultiplexer IP corecompliant with SBTVD
Robustness Analysis of Atomic Silicon Quantum Dot Logic Gates
Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor
AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture
An FPGA-Based RFID Baseband Processor Using a RISC-V Platform
A built-in current sensor for high speed soft errors detection robust to process and temperature variations
Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning
A 2-decades Wideband Low-Noise Amplifier with High Gain and ESD Protection
Highly integrated, re-configurable RF front-ends in deep sub-micron CMOS: (with an example of a WCDMA, GSM/GPRS/EDGE receiver without inter-stage SAW filter)
Energy efficient NoC design
Retiming Finite State Machines to Control Hardened Data-Paths
A 9.6 kb/s CMOS FSK modem for data transmission through power lines
A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
MagPDK: An open-source process design kit for circuit design with magnetic tunnel junctions
Formal Verification of VHDL ¾ The Model Checker CV
A methodology to evaluate the aging impact on flip-flops performance
Low power, high-sensitivity clock recovery circuit for LF/HF RFID applications
System-level Design of Single-bit Sigma-Delta Modulators Based on MSA and SNR Data Graphics
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration
A Structural Test Methodology for SRAM-Based FPGAs
eSi-BTC: an energy efficient Bitcoin mining core
A Straightforward Methodology for QCA Circuits Design
CMOS Power Amplifiers for X-Band: A Survey
Protecting SRAM PUF from BTI Aging-based Cloning Attack
Robust low power computing in the nanoscale era
Towards a Framework to Perform DPA Attack on GALS Pipeline Architectures
Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters
Packaging issues for 22nm and beyond
Heavy Ion Microbeam Experimental Study of ASET on a Full-Custom CMOS OpAmp
Improving Critical Path Identification in Functional Timing Analysis
ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks
A Study on Communication Issues for Systems-on-Chip
A temperature-aware analysis of latched comparators for smart vehicle applications
Analysis and System-Level Design of a High Resolution Incremental ΣΔ ADC for Biomedical Applications
A test chip for automatic MOSFET mismatch characterization
A radio-frequency real-time spectrum sensor based on an analog signal processing magnitude calculator
CMOS op-amp power optimization in all regions of inversion using geometric programming
Razor: a low-power pipeline based on circuit-level timing speculation
MOTIM: an industrial application using nocs
FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic
Analog design synthesis method using simulated annealing and particle swarm optimization
A novel system on chip for software-defined, high-speed OFDM signal processing
A parallel Motion Estimation solution for heterogeneous System on Chip
Enhancing Manycore Lifetime Through Reinforcement Learning Task Mapping and Migration
Protecting digital circuits against hold time violation due to process variability
A High-Performance Switching Element for a Multistage Interconnection Network
Deep Neural Network Feasibility Using Analog Spiking Neurons