yusuke1997/dblp-id-title huggingface dataset:
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory
Self-Reconfigurable Pervasive Platform for Cryptographic Application
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
Survey of domain-specific languages for FPGA computing
A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture
A reconfigurable computing architecture using magnetic tunneling junction memories
FPGA acceleration of quasi-Monte Carlo in finance
Improving the memory footprint and runtime scalability of FPGA CAD algorithms
A Flexible Implementation of a Temporal Filter with Motion Compensation
MORPHEUS: Heterogeneous Reconfigurable Computing
Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching
Design and Implementation of FPGA Circuits for High Speed Network Monitors
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
A Co-processor System with a Virtex FPGA for Evolutionary Computation
FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing
Hardware/Software Process Migration and RTL Simulation
An FPGA aligner for short read mapping
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs
An Instance-Specific Hardware Algorithm for Finding a Maximum Clique
SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs
Bent Routing Pattern for FPGA
FPGA Design Migration: Some Remarks
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems
DARP - A Digital Audio Reconfigurable Processor
Supercomputing with Reconfigurable Architectures
Auto-Tuning of Raw Filters for FPGAs
Choice - A Tunable PUF-Design for FPGAs
Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network
A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
FPGA-based all-digital software defined radio system demonstration
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch
Timing-Driven Routing of High Fanout Nets
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs
Arithmetic Operation Oriented Reconfigurable Chip: RHW
A Placement/Routing Approach for FPGA Accelerators
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs
Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs
High Performance FPGA-based Post Quantum Cryptography Implementations
FPGA based hardware-software co-designed dynamic binary translation system
Clock duplicity for high-precision timestamping in Gigabit Ethernet
FPLD HDL synthesis employing high-level evolutionary algorithm optimisation
High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects
Performance metrics for hybrid multi-tasking systems
Reconfigurable Computing for Speech Recognition: Preliminary Findings
Design space exploration for automatically generated cryptographic hardware using functional languages
Automatic Topology Optimization for FPGA Interconnect Synthesis
A Quantitative Prediction Model for Hardware/Software Partitioning
Multi Stream Cipher Architecture for Reconfigurable System-on-Chip
Non-uniform Segmentation for Hardware Function Evaluation
Configuration Merging for Adaptive Computer Applications
Processing Repetitive Sequence Structures with Mismatches at Streaming Rate
19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic
A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis
Efficient Hardware Architectures for Modular Multiplication on FPGAs
Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software
KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA
Minimizing Communication Cost for Reconfigurable Slot Modules
An FPGA acceleration of a level set segmentation method
An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms
A portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs
Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks
Line rate programmable packet processing in 100Gb networks
Growable FPGA Macro Generator
Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device
Migration from Schematic-Based Designs to a VHDL Synthesis Environment
Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
A Virtual File System for Dynamically Reconfigurable FPGAs
Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems
LavA: An Open Platform for Rapid Prototyping of MPSoCs
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC
A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization
Accelerating MPI Message Matching through FPGA Offload
Programmable Asynchronous Pipeline Arrays
Enabling Low Impact, Rapid Debug for Highly Utilized FPGA Designs
An optimization method of DMA transfer for a general purpose reconfigurable machine
Low-latency high-bandwidth HW/SW communication in a virtual memory environment
Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs
Fault Models and Yield Analysis for QCA-based PLAs
PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAs
Pipelined Multipliers and FPGA Architectures
Analyzing the thermal hotspots in FPGA-based embedded systems
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards
On Reconfigurable Architectures for Efficient Matrix Inversion
Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA
Rendering Postscript Fonts on FPGAs
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path
Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
A Hardwar/Software Co-design Environment for Reconfigurable Logic Systems
Parallel hardware objects for dynamically partial reconfiguration
The Monte Carlo PUF
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms
Estimating circuit delays in FPGAs after technology mapping
Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study
A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture Discrimination
Fly - A Modifiable Hardware Compiler
A high performance FPGA-based accelerator for large-scale convolutional neural networks
Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm
A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs
Towards a hardware-assisted information flow tracking ecosystem for ARM processors
Hot-Swapping architecture extension for mitigation of permanent functional unit faults
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining
Chosen-message SPA attacks against FPGA-based RSA hardware implementations
Initial Analysis of the Proteus Architecture
HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics
Automatically exploiting regularity in applications to reduce reconfiguration memory requirements
Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p
Track Placement: Orchestrating Routing Structures to Maximize Routability
A spiking neural network on a portable FPGA tablet
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture
Real-time Generation of Three-Dimensional Motion Fields
A Self-Compilation Flow Demo on FOS - The FPGA Operating System
SONIC - A Plug-In Architecture for Video Processing
artNoC - A Novel Multi-Functional Router Architecture for Organic Computing
Numerically controlled oscillators using linear approximation
Placing, Routing, and Editing Virtual FPGAs
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities
The FOS (FPGA Operating System) Demo
Synthesizing RTL Hardware from Java Byte Codes
Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA
LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs
Dynamic bitwidth assignment for efficient dot products
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS
FEMIP: A high performance FPGA-based features extractor & matcher for space applications
Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System
XDL-Based Module Generators for Rapid FPGA Design Implementation
Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources
FPGA Acceleration of Rotation in Homomorphic Encryption Using Dynamic Data Layout
Field-Programmable Custom Computing Machines - A Taxonomy -
Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview)
Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
Dynamic power estimation based on switching activity propagation
Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation
A dynamically reconfigurable parallel pixel processing system
Automatic Compiler Based FPGA Accelerator for CNN Training
Pre-route Interconnect Capacitance and Power Estimation in FPGAs
DFiant: A dataflow hardware description language
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification
ZAREPTA: A Zero Lead-Time, All Reconfigurable System for Emulation, Prototyping and Testing of ASICs
Implementing Processor Arrays on FPGAs
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations
A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA
Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures
Relocation-aware communication network for circuits on Xilinx FPGAs
Improving FPGA accelerated tracking with multiple online trained classifiers
RISPP: A run-time adaptive reconfigurable embedded processor
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
Time and Energy Efficient Matrix Factorization Using FPGAs
Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS
A secure and unclonable embedded system using instruction-level PUF authentication
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006
GraVF: A vertex-centric distributed graph processing framework on FPGAs
Intellectual Property Protection for RNS Circuits on FPGAs
Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
Exploration of Heterogeneous Reconfigurable Architectures
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC
Reconfigurable Hardware for Power-over-Fiber Applications
An investigation into a circuit based supply chain analyzer for FPGAs
An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies
FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs
System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?
Design of a Power Conscious, Customizable CDMA Receiver
Real-time image super resolution using an FPGA
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs
A Digit-Serial Structure for Reconfigurable Multipliers
Low power techniques for Motion Estimation hardware
Threshold Element-Based Symmetric Function Generators and Their Functional Extension
Program-driven fine-grained power management for the reconfigurable mesh
FPGA-Efficient Hybrid LUT/CORDIC Architecture
New approaches for in-system debug of behaviorally-synthesized FPGA circuits
TILT: A multithreaded VLIW soft processor family
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options
Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization
Speedy bus mastering PCI express
A deep convolutional neural network based on nested residue number system
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture
Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
A transport-layer network for distributed FPGA platforms
Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive
Self-recofigurable embedded systems on Spartan-3
Convey vector personalities - FPGA acceleration with an openmp-like programming effort?
Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures
A Programmable Logic Architecture for Prototyping Clockless Circuits
A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture
FPGA Roofline modeling and its Application to Visual SLAM
Design Visualisation for Dynamically Reconfigurable Systems
Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler
MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA
A Low Power FPAA for Wide Band Applications
Characterizing Power Distribution Attacks in Multi-User FPGA Environments
A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem
Using Reconfigurable HW for High Dimensional CAF Computation
Improving FPGA Performance and Area Using an Adaptive Logic Module
Reconfigurable multi-processor architecture for streaming applications
An FPGA Implementation of Goertzel Algorithm
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
A high-throughput reconfigurable processing array for neural networks
An FPGA Co-processor for Real-Time Visual Tracking
FPGA supercomputing platforms: A survey
Implementation of (Normalised) RLS Lattice on Virtex
OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
A Reconfigurable Approach to Packet Filtering
High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs
Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations
A Self-Reconfigurable Gate Array Architecture
FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008
Programmabel Prototyping System for Image Processing
Compact Hardware Architecture for Hummingbird Cryptographic Algorithm
Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA
Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching
Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration
SoC and FPGA oriented high-quality stereo vision system
Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs
Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm
Two-level MUX Design and Exploration in FPGA Routing Architecture
Design and Implementation of Real-Time Transactional Memory
Detecting Patterns in Various Size and Angle Using FPGA
Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings
Modeling of dynamic reconfigurable systems with Haskell
Pipeline morphing and virtual pipelines
The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures
A Design Environment with Emulation of Prototypes for Hardware/Software Systems Using XILINX FPGA
Multi-FPGA reconfigurable system for accelerating MATLAB simulations
A resiliency-aware scheduling approach for FPGA configuration: Preliminary results
A Tool-Set for Simulating Altera-PLDs Using VHDL
Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures
Using DSP Slices as Content-Addressable Update Queues
fpgaHART: A Toolflow for Throughput-Oriented Acceleration of 3D CNNs for HAR onto FPGAs
Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation
High-level FPGA logic synthesis from .NET programs for software developers
Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring
An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems
Switch Level Fault Emulation
Evaluating Fault Emulation on FPGA
Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators
Memory Access Optimization and RAM Inference for Pipeline Vectorization
Fast RTL Power Estimation for FPGA Designs
A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration
Optimizing an Open-Source Processor for FPGAs: A Case Study
High-speed PCAP configuration scrubbing on Zynq-7000 All Programmable SoCs
Field Programmable Communication Emulation and Optimization for Embedded System Design
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes
High-level synthesis with behavioral level multi-cycle path analysis
Tunable Fine-grained Clock Phase-shifting for FPGAs
Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
Power Dissipation Driven FPGA Place and Route Under Delay Constraints
Hyperreconfigurable architectures
Real-Time Detection of Moving Objects
Extending dynamic circuit switching to meet the challenges of new FPGA architectures
A Novel Field Programmable Gat Array Architecture for High Speed Arithmetic Processing
Tracking elephant flows in internet backbone traffic with an FPGA-based cache
Reconfigurable Breakpoints for Co-debug
High performance binary neural networks on the Xeon+FPGA™ platform
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting
System-Level Modeling of Dynamically Reconfigurable Co-processors
FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory
27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, September 4-8, 2017
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar Applications
Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System
Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation
Synthesized In-BramGarbage Collection for Accelerators with Immutable Memory
Mullet - A Parallel Multiplier Generator
Automatic generation of run-time parameterizable configurations
RIFFA 2.0: A reusable integration framework for FPGA accelerators
TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks
Verification of Dynamically Reconfigurable Logic
Sizing of Processing Arrays for FPGA-Based Computation
Enhancing performance of Tall-Skinny QR factorization using FPGAs
An Efficient Sparse LSTM Accelerator on Embedded FPGAs with Bandwidth-Oriented Pruning
High level programming framework for FPGAs in the data center
A Novel Watermarking Technique for LUT Based FPGA Designs
Thermal-aware partitioning for 3D FPGAs
Efficient Reconfigurable Logic Circuits for Matching Complex Network Intrusion Detection Patterns
Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures
Runtime reconfigurable beamforming architecture for real-time sound-source localization
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures
Developing Interface Libraries for Reconfigurable Data Acquisition Boards
Testing Superscalar Processors in Functional Mode
Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA
A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes
A Data Re-use Based Compiler Optimization for FPGAs
System-Level Design for FPGAs
High-level linear projection circuit design optimization framework for FPGAs under over-clocking
Real-Time Fault Detection and Diagnostics Using FPGA-based Architectures
HPTA: A High Performance Transformer Accelerator Based on FPGA
How Secure Are FPGAs in Cryptographic Applications?
Multiple Constant Multiplication: From Target Constants to Optimized Pipelined Adder Graphs
A hardware compilation flow for instance-specific VLIW cores
Bitstream compression techniques for Virtex 4 FPGAs
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing
Accelerated analysis of Boolean gene regulatory networks
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology
FPGA implementation to estimate the number of endmembers in hyperspectral images
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference
A Universal CLA Adder Generator for SRAM-Based FPGAs
Wireless Base Station Design Using a Reconfigurable Communications Processor
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
Operating system support for online partial dynamic reconfiguration management
A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment
Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA
Data path driven waveform-like reconfiguration
Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML
IP protection in Partially Reconfigurable FPGAs
An Algorithm Designer's Workbench for Platform FPGA's
Integration of a NoC-Based Multimedia Processing Platform
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks
Partially Reconfigurable Cores for Xilinx Virtex
A Testbench Design Method Suitable for FPGA-Based Prototyping of Reactive Systems