yusuke1997/dblp-id-title huggingface dataset:
A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences
High-performance data converters: Trends, process technologies and design challenges
A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder
A High Accuracy and High Sensitivity System Architecture for Electrical Impedance Tomography System
Common mode current characteristics in transmission line with common mode choke represented by two-port chain matrix
Roundoff noise reduction in state-space digital filters using high-order error feedback and realization
A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine Interface
Optimal Evasive Path Planning with Velocity Constraint
Impact of skew and jitter on the performance of VLSI interconnects
Biobjective Optimization Problems in a Simplified Model of Boost Converter with Photovoltaic Input
Depth refinement on sparse-depth images using visual perception cues
A CMOS low-voltage fully differential sample-and-hold circuit
Automatic ECG interpretation via morphological feature extraction and SVM inference nets
A Novel Structure of Conjunction Decision Feedback Equalizer for Nonlinear Channels
Design of single-inductor dual-output switching converters with average current mode control
Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices
Fast design approach for implementing the approximate squaring function
On Edge FPN Reduction in CMOS Image Sensor Using CNN with Attention Mechanism
Transient responses of voltage and current on dual-mode ring resonator bandpass filters
A V-band power amplifier with 11.6dB gain and 7.8% PAE in GaAs 0.15µm pHEMT process technology
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC
Precoded MIMO-SC-FDE and blind channel estimation
Enumeration of Genaralized Parallel Counters for Multi-Input Adder Synthesis for FPGAs
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks
An inverter-based OTA using improved composite transistors and bulk-driven common-mode rejection
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding
A performance and interoperability study of an OpenH323-based multimedia over IP (MOIP) system
Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET
Curved segmentation path generation for unconstrained handwritten Chinese text lines
Standard Cells with Inverted Inputs in 7nm Technology
A high output-swing current mirror with neuron MOSFETs in standard CMOS technology
Post-Processing of K-best MIMO Detection for High-Order Modulations
A RSSI-based environmental-adaptive dynamic radiation power management for Wireless Sensor Networks
A region adaptive encoding algorithm for simple image compression
Efficient FPGA design for Convolutions in CNN based on FFT-pruning
Japanese Vowel-mora Visualization for Dysarthria Rehabilitation with Variational Autoencoder
A 1.3 nW, 0.014 %/V and Dual-output CMOS Voltage Reference with Self-biased Current Source
VLSI layout hotspot detection based on discriminative feature extraction
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm
Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor Paradigm
New Criteria Enhancing Robustness and Efficiency of Solving Systems of Circuit Equations
Analog Neuron as Generalised Similarity Metric
Fast CTU Partition Decision Algorithm for VVC Intra and Inter Coding
Self-Ordering Machine for Canteen (SELFO)
Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/Undershoot
Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process
An ultra low-power Successive Approximation ADC using an offset-biased auto-zero comparator
Threshold triggers and accelerator for deep submicron interconnection
DFM-aware Routing for Yield Enhancement
On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing
Computer aided analysis of channel state and transition in transmitted symbol for the channel h c (z)=0.5+1.0z -1 at noise variance 0.40
A novel space vector modulation method of three-level inverter based on the synthesized middle space vectors
Sensor Node with Position Validation towards Camptocormia Measurement at Home
Equidistant mixer-based frequency generation for 60 GHz FBMC transmitter topologies
Wave digital filters using digit serial 3-port adaptors
Power Management in Circuits Design
A new online test and debug methodology for automotive camera image processing system
IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008
Dark current analysis of P-type and N-type pixels under total ionizing dose radiation effects
A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism
A CGRA based Neural Network Inference Engine for Deep Reinforcement Learning
A low complexity soft demapping method for expanded M-QAM constellations
A procedure for singularity measurement using wavelet
A low-latency GALS interface implementation
A 12-bit Domino ADC with a Background Offset Calibration Scheme
Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder
An Incremental Zoom ADC With Quantization Level Shifting Technique For Over-Ranging Reduction
Frequency Interval Gramians based Model Reduction
A modified predictor-corrector method for tracing solution curves
Multi-frequency narrowband active noise control with online feedback-path modeling using IIR adaptive notch filters
Noise Efficient Three-Channel Amplifier for MEMS Cantilever Readout
VLSI implementation and optimization design of Reed-Solomon decoder in QAM demodulation chip
Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints
On a new edge coloring related to multihop wireless networks
Paged cache: an efficient partition architecture for reducing power, area and access time
Narrowband interference suppression with symbol interleaving for UWB communication systems
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators
Learning Enriched Features for Video Denoising with Convolutional Neural Network
Random testing of C compilers based on test program generation by equivalence transformation
A voltage equalizer using flyback converter with active clamp
An Automatic Cache Generator Based on Content-Addressable Memory
Using Fully Connected and Convolutional Net for GAN-Based Face Swapping
A $118\ \text{dB}\Omega$ 190 MHz CMOS Transimpedance Amplifier Using Phase Compensator for MEMS Beam Oscillator
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding
Compact Power Front-end Management for Wireless Supply of Multi-voltages to Neuromodulators
Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus
A range of allowable number of input bits for tone free delta-sigma operation in digital MASH Delta-Sigma Fractional-N frequency synthesizers
A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter
A reconfigurable ASIP-based approach for high performance image signal processing
A novel predictor coefficient interpolation algorithm for enhancement of spatial resolution of images
Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform
Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models
100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects
Wide area sensor network for disaster prevention and monitoring: Concept and service coverage
Low-voltage digitally controlled current differencing buffered amplifier
A Filled Function Method for Box-constrained System of Nonlinear Equations
A low-offset high-CMRR switched-capacitor instrumentation amplifier for data acquisition applications
An untrimmed CMOS amplifier with high CMRR and low offset for sensor applications
Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions
PIC based photovoltaic maximum power point tracking control system
SSTA considering switching process induced correlations
Design of high linearity low flicker noise 5.2 GHz down-conversion mixer for direct conversion receiver
Peak Power Minimization through Power Management Scheduling
A Wide-Range and High PSRR CMOS Voltage Reference for Implantable Device
Digital PID Based on Pseudo Type-III Compensation for DC-DC Converter
A processor shield for software-based on-line self-test
An unconditionally stable Voltage Regulator
A 600MHz, 6 th order, highly linear Gm-C bandpass filter design
Efficient built-in self-test for video coding cores: A case study on motion estimation computing array
Machine learning (ML)-based lithography optimizations
SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network
Investigation of Voltage Fault Injection Attacks on NN Inference Utilizing NVM Based Weight Storage
Low IR drop and low power parallel CAM design using gated power transistor technique
A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair
Nonlinear STATCOM Controller using Passivity-Based Sliding Mode Control
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs
Estimating required driver strength in the resonant clock generator
Switched Capacitor based High Positive and Negative Voltage Charge-pump using Sample and Hold technique
Experimental Cryptanalysis of No-equilibrium Chaotic System Based Random Number Generator
A Novel DPWM Based on Fully Table Look-Up for High-Frequency Power Conversion
A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle
VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing
Derivations and Relations of Various Cost Functions for Allpass Phase-Equalizing Filter Design
A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology
Design of a linearly increasing inrush current limit circuit for DC-DC boost regulators
Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament
Efficient Buffer Management for Retry Mechanism in InfiniBand
Automotive hybrid voltage regulator design with adaptive LDO dropout using load-sense technique
Limited search sphere decoder and adaptive detector for NOMA with SU-MIMO
A 0.13μm CMOS UWB receiver front-end using passive mixer
Arithmetic reduction of adder leakage in nanoscale CMOS
ADC clock jitter measurement and correction using a stochastic TDC
A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems
Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency
Double Gate JLT Based New TIGFET for Dynamic C 2 MOS Application
Web Based Design for E-Learning Contents on Cloud Network
Additional power reduction offered by fast power control over slow power control in multimedia communications over WLANs
Implementation of variable step-size algorithm for lattice form structure for echo cancellation
Global Routing Optimization Analysis based on Deep Reinforcement Learning
A randomized algorithm for the fixed-length routing problem
INL Prediction Method in Pipeline ADCs
Near-infrared-ray and side-view video based drowsy driver detection system: Whether or not wearing glasses
An improved Montgomery inversion algorithm over GF(2 m ) targeted for low area scalable inverter on FPGA
An Automation Program for March Algorithm Fault Detection Analysis
Design of Extended RISC-V for Q-Learning Hardware Accelerator using HW/SW Co-Design
A 3.125-GHz Limiting Amplifier for Optical Receiver System
2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults
Determination consideration for DOCSIS implementation
SDR structure based CFO estimation and compensation circuit for OFDM systems using reconfigurable CORDIC FPGA modules
Post-scheduling frequency assignment for energy-efficient high-level synthesis
Design of DXT architecture using current switched integrator
A capacitive-coupled transformerless active power filter with coupling current feedback control
High-speed and low-power serial accumulator for serial/parallel multiplier
A Novel Dual Direction SCR With Dummy Gate Structure for High Voltage ESD Protection
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems
Frequency stabilization of FBG external cavity laser diode
Formant frequency estimation with windowless autocorrelation in the presence of noise
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design
Estimation-based run-time power profile flattening for RF-powered smart card systems
Kernel Extraction for Watermarking Combinational Logic Networks
A low-voltage, low-power subthreshold CMOS voltage reference without resistors and high threshold voltage devices
NoC AI Chip Integration for Industrial IoT Fault Diagnosis and Notification System
A Compact 1-5.2 GHz Wideband Low Noise Amplifier
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder
LDPC Decoder Based on Markov Chain Monte Carlo Method
Hardware complexities of low-complexity Chase Reed Solomon decoders and comparisons
A Design of PUF Circuit Using Adiabatic Logic
A Novel Prediction Technique for Intermittent UWB Positioning System Using Hybrid LSTM-Trilateration
A new decentralized discrete-time algorithm for estimating algebraic connectivity of multiagent networks
Delta discrete-time operator-based doubly-terminated two-port: Application to filter design and stability testing
An accurate design approach for two-stage CMOS operational amplifiers
Decimal Multiplication Using Combination of Software and Hardware
A 4 Bit Segmented Current-Steering Harmonic-Cancelling Digital-to-Analog Converter for High Frequency Sine-Wave Synthesis
Study on analysis of movement-related cortical potentials included in saccade-related EEG
A Comparative Study on the Robustness of Chaos-Based Random Number Generators
A 0.9V Current-Mode Bandgap Reference with Wideband PSRR Better than 70dB from -40°C to 75°C
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity
Polyimide-Based Flexible 3-Coil Inductive Link Design and Optimization
Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognition
A Radiation-Hardened Serial Peripheral Interface with an ECC-Protected SRAM in a 65nm CMOS Technology
An ASIC Implementation of Lifting-Based 2-D Discrete Wavelet Transform
A Closed Form Solution to L2-Sensitivity Minimization of Second-Order Digital Filters Subject to L2-Scaling Constraints
Exploiting Nonlinear Dynamics to Search for the Existence of Matches in a Database
A wide band and low PN PLL design for digital tuner
Reform and Practice of Analog Circuits
New Methods for QDDFS with Millions' Compression Ratio
Low Noise Low Power Readout Circuit For Capacitance Based MEMS Accelerometers
Minimization of delay insertion in clock period improvement in general-synchronous framework
RaceCheck: A race logic audit program for ESL-based soc designs
A conductivity and temperature sensor array for detecting saltwater intrusion in shore-based communities
A Data-Efficient Training Model for Signal Integrity Analysis based on Transfer Learning
A high-level synthesis method for simultaneous placement and scheduling considering data communication delay
New Reconfiguration Algorithm for Degradable VLSI Arrays
On the Implementation of a Rotated Chaotic Lorenz System on FPGA
OCR is All you need: Importing Multi-Modality into Image-based Defect Classification System
Analysis of a reconfigurable TEG array for high efficiency thermoelectric energy harvesting
Methods of Reducing the Intrinsic Loss for Continuously-Scalable-Conversion-Ratio SC Converters
Automatic detection of epileptic spikes based on wavelet neural network
An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator
Design and implementation of GPIO subsystem using external foundry I/O buffer
A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter
Innovations in Hardware Security: Leveraging FeFET Technology for Future Opportunities
Exploitation of temporal redundancy for lossless video coding
A High Linearity 6 th -order active R-MOSFET-C band-pass filter for power-line communication
Low-power high-speed dual-modulus prescaler for Gb/s applications
Control system using fuzzified input neural network
Enabling a deleted-key-value-aware garbage collection strategy for LSM-tree on OCSSD
Stabilizing unstable periodic orbits in higher dimensional systems based on stability transformation method
Perceptual multiband spectral subtraction for noise reduction in hearing aids
A concurrent dual-band mixer with on-wafer balun for multi-standard applications
Low power integrated circuits for wireless neural recording applications
Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm
A 1V 2.4GHz Down Conversion Folded Mixer
Digital GFSK Carrier Synchronization
A novel current-mode readout circuit for ISFET sensor
Design of a 3rd-Order 12-bit Incremental ADC for Power Monitoring Applications
A Low Cost/Low Power Chaos-based Transceiver Exploiting Ergodicity
An Area-Efficient Differential Serial DAC with Mismatch Compensation Scheme
Study of Real-Time Detecting System for Driver's Safety
Op-Amp sizing with large number of design variables using TuRBO
A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing
A Fast Macroblock Mode Decision Algorithm for H.264
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1)
SAR ADC algorithm with redundancy
Multi-type SRAM Test Structure with an Improved March LR Algorithm
Implementation of 12nm Graphene Flakes in TiO2/G Composite for High Power Conversion in DSSCs: *Note: Sub-titles are not captured in Xplore and should not be used
Multifunction RNS modulo (2 n ±1) multipliers based on modified booth encoding
A Novel Compiler for Regular Expression Matching Engine Construction
Discrete fractional Hénon map based on digital fractional order integrator
SDPQ classification based on maximum similarity principle of S-transform MTFM
Low-Complexity RDFT-Based Impedance Calculation for Enhanced EIS Analysis
An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity
A BIRA using fault-free memory region for area reduction
TRNG Based on Multiple Entropy Sources Using CTDSM
A Digital Random Number Generator Based on Regular Sampling of Double Scroll Chaos
Techniques of Power-gating to Kill Sub-Threshold Leakage
Live Demonstration: A 772μJ/frame ImageNet Feature Extractor Accelerator on HD Images at 30FPS
A novel leakage-estimation method for input-vector control
Wide-band injection-locked frequency doubler
SAR ADC that is configurable to optimize yield
A low supply-dependence fully-MOSFET voltage reference for low-voltage and low-power
A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems
Performance Analysis of Successive Interference Cancellation in Multiuser CDMA over Flat Channels
Statistical analysis of inner products from normal-vectors to 3D point cloud clustering
A ZVS Active Rectifier with Adaptive On/Off Delay Compensation for WPT Systems
Implementing Content-Defined Chunking for Deduplication in Host-Managed SSDs
Operation Scheduling for False Loop Free Circuits
Low power multiplexer tree design using dynamic propagation path control
Switched Capacitor based Area Efficient Positive and Negative Voltage Multiplier
RaceCheck: A Race Logic Audit Program For SoC Designs
Implementing a reconfigurable MAP decoder on a soft core processor system
3D Multiresolution Analysis for reduced features segmentation of medical volumes using PCA
An impedance measurement analog front end for wirelessly bioimplantable applications
Performance enhancement of logical link control using channel quality in GPRS
Oscillation death and amplitude change in coupled van der pol oscillators with strong frustrations
FPGA implementation of hamming code for increasing the frame rate of CAN communication
A novel quantization algorithm suitable for high-speed analog-to-digital converters
A cascadable current-mode universal biquadratic filter using MO-CCCCTAs
A low complexity modulo 2 n +1 squarer design
A 0.672 μW, 2 μVrms CMOS Current-Feeback ECG Pre-amplifier With 77 dB CMRR
An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance
Live demonstration: A low-power high-level synthesis system
An extended framework for worst-case throughput analysis with router constraint
Smart wearable device for real time gait event detection during running
The Integration of File Server Function and Task Management Function to Replace Web Application on Cloud Platform for Cost Reduction
Low-frequency noise reduction technique for accelerometer readout circuit
Road network detection from SPOT satellite image using Hough transform and optimal search
An all-digital battery capacity monitor using calibrated current estimation approach
Synchronization phenomena in star-coupled van der pol oscillators by adding different frequency oscillators
Dynamic binary neural networks and storage of control signals for switching circuits
Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems
Design of a low-complexity O-QPSK transceiver with spatial modulation for internet-of-things applications
Calculating the probability of timing violation of F/F-controlled paths with timing variations
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
Cache utilization-aware scheduling for multicore processors
Adjacent common centroid placement for analog IC layout design
An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding
A 348-nW, 10.5-bit Analog Front End with Amplifier Resistor Series Loop for Acoustic Application
Distributed video transcoding on a heterogeneous computing platform
Efficient radius and list updating units design for list sphere decoders
A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking
A wireless front-end for implantable cardiac micro-stimulator
Cognitive Frailty Classification Models for Older Adults in a Point-of-Care System
2PCDAL: Two-phase clocking dual-rail adiabatic logic
Timing-constrained yield-driven redundant via insertion
Optical Interconnect Technology; Photons Based Signal Communication
Effective model construction for enhanced prediction in example-based super-resolution
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion
Clock control strategy of four-phase Dickson charge pump for power efficiency improvement
Numerical implementation of a Functional Observability algorithm: A Singular Value Decomposition Approach
Modeling of DLL-based frequency multiplier in time and frequency domain with Matlab Simulink
An Overview of Digital Low Drop-out Regulator Design
An Ultra-Low-Supply Output-Capacitorless LDO with Signal- and Transient-Enhancement
A new noise-constrained normalized least mean squares adaptive filtering algorithm
Computation Complexity Reduction Based on Quick Leaky-Integrate-And-Fire Mechanism for SNNs
Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic
Design of low power and improved tlatch comparator for SAR ADC
A 10-bit 1.25GSample/s partially-segmented D/A Converter for Ultra Wide-Band communication system
FPGA Implementation of Matrix Decomposition Based FIR Filter
Adaptive blind equalization of SIMO FIR second order Volterra channels
Circuit Area-latency Optimization Technique for High-precision Elementary Functions
Unsupervised Image Dataset Annotation Framework for Snow Covered Road Networks
Design of a process-insensitive digital controller for high-frequency DC-DC SMPS
Data partition analyses for video decoders on PAC Duo platform