yusuke1997/dblp-id-title huggingface dataset:
Information hiding for trusted system design
Algorithms for Library-Specific Sizing of Combinational Logic
Multi Chip Modules
Reasoning about digital systems using temporal logic
Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024
A Transmission Line Simulator for GaAs Integrated Circuits
Electronics beyond nano-scale CMOS
A database management approach to CAD/CAM systems integration
A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators
Electro-magnetic analysis of GPU-based AES implementation
Late Breaking Results: Fast Fair Medical Applications? Hybrid Vision Models Achieve the Fairness on the Edge
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications
An embedded infrastructure of debug and trace interface for the DSP platform
Design Reuse: Fact or Fiction? (Panel)
Energy-aware error control coding for Flash memories
A man-machine approach toward solving the traveling salesman problem
Mixed-Precision Quantization for Deep Vision Models with Integer Quadratic Programming
On software design for stochastic processors
Synthesis and implementation of active mode power gating circuits
The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication
Carbon nanotube circuits in the presence of carbon nanotube density variations
Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions
A Constraint Based Approach to Automatic Design of Analog Cells
Accurate simulation of flip-flop timing characteristics
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture
Systems for human-powered mobile computing
A survey of techniques for energy efficient on-chip communication
The Role of Long and Short Paths in Circuit Performance Optimization
Proceedings of the 16th Design Automation Conference, DAC '79, San Diego, California, USA, June 25-27, 1979
Distributed Design-Space Exploration for High-Level Synthesis Systems
Efficient simulation of AHPL
An architecture design and assessment system for software/hardware codesign
Random test generation using concurrent logic simulation
An efficient test vector generation for checking analog/mixed-signal functional models
BLoG: post-silicon bug localization in processors using bug localization graphs
Security analysis of automotive architectures using probabilistic model checking
A Fully-Automated Desynchronization Flow for Synchronous Circuits
GDR-HGNN: A Heterogeneous Graph Neural Networks Accelerator Frontend with Graph Decoupling and Recoupling
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage
Performance-Driven Integration of Retiming and Resynthesis
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
An algebra for logic strength simulation
An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells
Walking a thin line: performance and quality grading vs. yield overcut
Response-time analysis of DAG tasks supporting heterogeneous computing
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration
Directed Self-Assembly (DSA) Template Pattern Verification
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
Incremental layer assignment for critical path timing
GLite: a fast and efficient automatic graph-level optimizer for large-scale DNNs
The chip layout problem: An automatic wiring procedure
Path directed abstraction and refinement in SAT-based design debugging
CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc
An Overview of the Penn State Design System
Application-aware NoC design for efficient SDRAM access
Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDs
Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal Circuits
Efficient system design space exploration using machine learning techniques
Efficient escape routing for hexagonal array of high density I/Os
Embedded systems education (panel abstract)
Parametric pattern router
The computer in the space planning process
A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between
Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition
An Interactive Simulation System for structured logic design - ISS
An Electrical Optimizer that Considers Physical Layout
Towards the automatic exploration of arithmetic-circuit architectures
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
Computing Optimal Clock Schedules
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers
Cache side-channel attacks and time-predictability in high-performance critical real-time systems
An HDL-Based System Design Methodology for Multistandard RF SoC's
Scan chain clustering for test power reduction
Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence Transformations
Policy Optimization for Dynamic Power Management
A Transistor Reordering Technique for Gate Matrix Layout
Physics-based full-chip TDDB assessment for BEOL interconnects
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking
Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process
Structured Design Methodology for High-Level Design
Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog Circuits
A notation and system for 3-D constructions
The synthesis of robust polynomial arithmetic with stochastic logic
Geometric modeling technology
Automatic component placement in the nomad system
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping
On Trading Wear-leveling with Heal-leveling
Heuristic adaptability to input dynamics for SpMM on CPUs
The Constrained Via Minimization Problem for PCB and VLSI Design
On testing timing-speculative circuits
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
Signature based Boolean matching in the presence of don't cares
Rectilinear Steiner Trees with Minimum Elmore Delay
Lightning Talk: The New Era of Computational Cognitive Intelligence
On the Temporal Equivalence of Sequential Circuits
System Simulation of Printed Circuit Boards Including Packages and Connectors
Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes
DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022
High level formal verification of next-generation microprocessors
Object Type Oriented Data Modeling for VLSI Data Management
KV-SSD: What Is It Good For?
An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs
Physically aware high level synthesis design flow
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model
Machine aids to the design of ceramic substrates containing integrated circuit chips
Automatic test equipment "production test in the design automation system"
A multiple media delay simulator for MOS LSI circuits
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory
Browsing in Chip Design Database
Timing-driven Steiner trees are (practically) free
Printed circuit artwork checker
Practical public PUF enabled by solving max-flow problem on chip
PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units
Towards accurate and high-speed spiking neuromorphic systems with data quantization-aware deep networks
SIMMOS: a multiple-delay switch-level simulator
Digital network design aids - an integrated approach
Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies
Improved fault diagnosis in scan-based BIST via superposition
GCiM: A Near-Data Processing Accelerator for Graph Construction
Design for Manufacturability and Yield
Computer-aided process design and simulation for forging of turbine blades
Algorithms for Coupled Domain MEMS Simulation
Model composition for scheduling analysis in platform design
Online SystemC emulation acceleration
Logical correctness by construction
Invited: Automated Code generation for Information Technology Tasks in YAML through Large Language Models
Tighter Dimensioning of Heterogeneous Multi-Resource Autonomous CPS with Control Performance Guarantees
Efficient fingerprint-based user authentication for embedded systems
Electronic CAD/CAM-is it revolution or evolution (tutorial session)
BlasPart: A Deterministic Parallel Partitioner for Balanced Large-Scale Hypergraph Partitioning
CAD Tool Needs for System Designers
System level leakage reduction considering the interdependence of temperature and leakage
Effect of Distributed Directories in Mesh Interconnects
Humans for EDA and EDA for humans
58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021
Sequential Circuit Test Generation on a Distributed System
Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract)
Automated conversion of design data for building the IBM 3081
SpecASR: Accelerating LLM-based Automatic Speech Recognition via Speculative Decoding
Leakage-aware redundancy for reliable sub-threshold memories
A fast and robust failure analysis of memory circuits using adaptive importance sampling method
A novel analytical method for worst case response time estimation of distributed embedded systems
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes
Steady-state dynamic temperature analysis and reliability optimization for embedded multiprocessor systems
Interface-Based Design
Performance-Driven Constructive Placement
Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis
Contest: A Concurrent Test Generator for Sequential Circuits
Techniques for Verifying Superscalar Microprocessors
Analyzing CMOS Power Supply Networks Using Ariel
Circuit Partitioning for Huge Logic Emulation Systems
Hierarchical architecture of flash-based storage systems for high performance and durability
The impact of technological advances on programmable controller s(tutorial session)
StreamCSD: SSD-Autonomous Stream Management via In-Storage Content Learning
Dynamic FPGA routing for just-in-time FPGA compilation
The MIMOLA design system a computer aided digital processor design method
Cool shapers: shaping real-time tasks for improved thermal guarantees
PRIMAL: Power Inference using Machine Learning
Computationally Efficient Power Integrity Simulation for System-on-Package Applications
Variability and energy awareness: a microarchitecture-level perspective
ASCache: An Approximate SSD Cache for Error-Tolerant Applications
SPFuzz: Stateful Path based Parallel Fuzzing for Protocols in Autonomous Vehicles
Schedule Validation for Embedded Reactive Real-Time Systems
Facing the challenge of new design features: an effective verification approach
The cat and mouse in split manufacturing
Dynamic binary translation to a reconfigurable target for on-the-fly acceleration
Automated placement of multi-terminal components
A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMs
ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs
Extension of the Critical Path Tracing Algorithm
Dynamic behavior of cell signaling networks: model design and analysis automation
Automatic input and interactive editing systems of logic circuit diagrams
Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
PHIPLA-a new algorithm for logic minimization
Fuzzy Logic Approach to Placement Problem
Double patterning lithography-aware analog placement
System-Level Hardware/Software Trade-offs
ReVeil: Unconstrained Concealed Backdoor Attack on Deep Neural Networks using Machine Unlearning
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Specification and synthesis of hardware checkpointing and rollback mechanisms
Buffer Insertion with Accurate Gate and Interconnect Delay Computation
CrowdMine: towards crowdsourced human-assisted verification
Microarchitecture-aware floorplanning using a statistical design of experiments approach
A new time-stepping method for circuit simulation
Hitachi-PA/50, SH Series Microcontroller
A Database Management System for a VLSI Design System
Principles of the SYCO compiler
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading
Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs
A lattice-based framework for the classification and design of asynchronous pipelines
A view of a user-oriented production test data generation system
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems
Incremental power grid verification
Women in the Microelectronics Industry (Panel Abstract)
Application-driven floorplan-aware voltage island design
A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis
Towards structured ASICs using polarity-tunable Si nanowire transistors
The calculation of the dimensions for an electromagnet with a T armature
A MOS/LSI oriented logic simulator
SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs
Delay budgeting in sequential circuit with application on FPGA placement
Impact of process variations on emerging memristor
A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors
Closing the power gap between ASIC and custom: an ASIC perspective
Placement algorithms for custom VLSI
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits
Task generation and compile-time scheduling for mixed data-control embedded software
ESP: A New Standard Cell Placement Package Using Simulated Evolution
Differentiate and deliver: leveraging your partners
Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM Inference
TRIP: An Automated Technology Mapping System
Bounds on the saved area ratio due to PLA folding
Quadratic placement using an improved timing model
Central DA and its role: An executive view
Daedalus: toward composable multimedia MP-SoC design
CADMON: Improving the CAD system human interface
Efficient Approximation Algorithms for Floorplan Area Minimization
A Scalable Formal Verification Methodology for Pipelined Microprocessors
Fast Approximation of the Transient Response of Lossy Transmision Line Trees
The effects of CAD on the engineering organization (Position paper)
Hybrid energy storage systems and battery management for electric vehicles
Hardware realization of BSB recall function using memristor crossbar arrays
A formal method for computer design verification
A Methodology for HW-SW Codesign in ATM
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design
Zhuyi: perception processing rate estimation for safety in autonomous vehicles
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
Relational data handling techniques in integrated circuit mask layout procedures
LTX - a system for the directed automatic design of LSI circuits
Extracting behavior and dynamically generated hierarchy from SystemC models
Parameter variations and impact on circuits and microarchitecture
Phase correct routing for alternating phase shift masks
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation
MACH : a high-hitting pattern checker for VLSI mask data
BDD Variable Ordering for Interacting Finite State Machines
Property-Based Timing Analysis and Optimization for Complex Cyber-Physical Real-Time Systems
Silicon validation of LUT-based logic-locked IP cores
Easz: An Agile Transformer-based Image Compression Framework for Resource-constrained IoTs
More Practical Bounded-Skew Clock Routing
Thermal Resistance Network Derivative (TREND) Model for Efficient Thermal Simulation and Design of ICs and Packages
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Learning Concise Models from Long Execution Traces
ΣVP: host-GPU multiplexing for efficient simulation of multiple embedded GPUs on virtual platforms
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems
Beyond local optimality of buffer and splitter insertion for AQFP circuits
First-order incremental block-based statistical timing analysis
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits
Introduction of local memory elements in instruction set extensions
Divide-and-concatenate: an architecture level optimization technique for universal hash functions
Wave-steering one-hot encoded FSMs
Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics
A general examination of engineering design
Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms
Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing
An Interactive Maze Router with Hints
Models, abstractions, and architectures: the missing links in cyber-physical systems
StressTest: an automatic approach to test generation via activity monitors
Fast post-placement rewiring using easily detectable functional symmetries
Sharry: An Efficient and Sharing Far Memory System
Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors
A Practical Approach to Static Signal Electromigration Analysis
Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver
Capacitance of TSVs in 3-D stacked chips a problem?: not for neuromorphic systems!
Memory and Computation Coordinated Mapping of DNNs onto Complex Heterogeneous SoC
Parallelizing SRAM arrays with customized bit-cell for binary neural networks
An Automated and Process-Portable Generator for Phase-Locked Loop
Large-scale capacitance calculation
A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain Decomposition
Connectivity Biased Channel Construction and Ordering for Building-Block Layout
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition
Analyzing k -step induction to compute invariants for SAT-based property checking
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout
Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation
PALMINI - Fast Boolean Minimizer for Personal Computers
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications
Formal design verification of digital systems
Optimization of Inductor Circuits via Geometric Programming
Evolution of the engineering design system data base
Functional Verification Methodology for the PowerPC 604 Microprocessor
Tutorial: basic concepts in quantum circuits
PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration
WISEDRAM: A Reliable Bitwise In-DRAM Accelerator
Heuristics for the Circuit Realization Problem
Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits
Creator: General and Efficient Multilevel Concurrent Fault Simulation
A Functional-Level Test Generation Methodology Using Two-level Representations
A high density, carbon nanotube capacitor for decoupling applications
A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge
System-level Innovation for the Next Decade AI Performance, Power, Area with Co-optimization
StocHD: Stochastic Hyperdimensional System for Efficient and Robust Learning from Raw Data
Hcompare: A Hierarchical Netlist Comparison Program
Neural Pruning Search for Real-Time Object Detection of Autonomous Vehicles
Generating Incremental VLSI Compaction Spacing Constraints
A methodology for energy-quality tradeoff using imprecise hardware
C 2 PI: An Efficient Crypto-Clear Two-Party Neural Network Private Inference
HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs
An empirical analysis of the performance of a multiprocessor-based circuit simulator
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor
Design Methodologies for consumer-use video signal processing LSIs
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
Utilizing Logic Information in Multi-Level Timing Simulation
Simultaneous Placement and Module Optimization of Analog IC's
Simulation environment configuration for parallel simulation of multicore embedded systems
Crossroads: Time-Sensitive Autonomous Intersection Management Technique
Custom VLSI electrical rule checking in an intelligent terminal
Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry
Assembly drawings and bills of material creating system (ADMS)
Compiler Optimization for Quantum Computing Using Reinforcement Learning
Timing closure for low-FO4 microprocessor design
SIDS (A Symbolic Interactive Design System)
On-Chip Inductance Issues in Multiconductor Systems
Learning-based Data Separation for Write Amplification Reduction in Solid State Drives
Distributed time, conservative parallel logic simulation on GPUs
Parallel FPGA Routing based on the Operator Formulation
Deep-DFR: A Memristive Deep Delayed Feedback Reservoir Computing System with Hybrid Neural Network Topology
PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators
Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time
Re-use-centric architecture for a fully accelerated testbench environment
An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems
Power-Aware NoCs through Routing and Topology Reconfiguration
SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets
Search space characterization for approximate logic synthesis
ASRR-PINN: Adaptive Sub-Regional Random Resampling-Based PINN for Thermal Analysis of 3D-ICs
An Application of Exploratory Data Analysis Techniques to Floorplan Design
A Fast Secure Deletion Strategy for High-Density Flash Memory through WOM-v Codes
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
HybDTM: a coordinated hardware-software approach for dynamic thermal management
Exploiting PDN noise to thwart correlation power analysis attacks in 3D ICs
Systematic functional coverage metric synthesis from hierarchical temporal event relation graph
Manufacturing engineering and information
System-level exploration tools for MPSoC designs
An effective power mode transition technique in MTCMOS circuits
Timing Analysis in a Logic Synthesis Environment
Cooperative Approach to a Practical Analog LSI Layout System
An Integrated Design Environment for Performance and Dependability Analysis