yusuke1997/dblp-id-title huggingface dataset:
A compensation technique for transistor mismatch in current mirrors
Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data
A power-area analysis of NoCs in FPGAs
A low power sub-1 V CMOS voltage reference
Dynamic Precision Multiplier For Deep Neural Network Accelerators
AC-Logic Family for Smart Dust and IoT Applications
Process Variation Aware Parallelization Strategies for MPSoCs
Reduced computation and memory access for VBSME using pixel truncation
Power and area evaluation of a fault-tolerant network-on-chip
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models
Energy-Aware MPEG-4 Single Profile in HW-SW Multi-Platform Implementation
Optimization of best polarity searching for mixed polarity reed-muller logic circuit
A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits
Design and ASIC acceleration of cortical algorithm for text recognition
Optimum design and trade-offs for a triple-band LNA for GSM, WCDMA and GPS applications
Pseudo parallel architecture for AES with error correction
Expandable MDC-based FFT architecture and its generator for high-performance applications
Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo
An Enhanced 1440 Coupled CMOS Oscillator Network to Solve Combinatorial Optimization Problems
CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control
T1B: Special session: Data analytics driven design for yield, manufacturability and reliability: Where machine learning meets design automation
1.81 kHz Relaxation Oscillator With Forward Bias Comparator and Leakage Current Compensation Based Techniques
An IMU-aided Fitness System
ZodiacMSM: A Heterogeneous, Multi-node and Scalable Multi-Scalar Multiplication System for Zero Knowledge Proof Acceleration
End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms Detection
Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms
Training Deep Neural Networks Using Posit Number System
The evolutionary spintronic technologies and their usage in high performance computing
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction
T1A: Time sensitive networks for industry 4.0
Machine learning interatomic potential prediction of thermal and mechanical characteristics of Si nanosheet transistors for low power applications
Low voltage Flash memory design based on floating gate SOFFET
A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic
Low-power multiplier design with row and column bypassing
ADPLL variables determinations based on phase noise, spur and locking time
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks
Next-Gen Physical Design with AI
A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications
A scalable electrical characterization method for inter-strata interconnects in 3-D ICs
Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation
SOSoC, a Linux framework for System Optimization using System on Chip
A Pulse-Based Full-Band UWB Transceiver SoC in 0.18μm SiGe BiCMOS
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing
Statistical rare event analysis using smart sampling and parameter guidance
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications
A Low Power Analog Front-end for Ultrasound Receiver
Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks
Compiler Support for Voltage Islands
Energy scalable approximate DCT architecture trading quality via boundary error-resiliency
Pin Accessibility Improvement with Hit-Point Distribution Metrics for Sub-4nm Standard Cell
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips
Digital clock frequency doubler
A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises
A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC
Efficient fault emulation using automatic pre-injection memory access analysis
Design of complex circuits using the Via-Configurable transistor array regular layout fabric
A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection
Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC
High-Efficiency Step-Down Multi-Mode Switching DC-DC Converter for IoT Devices
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization
Plenary speaker: "The pig in the poke? - Strategies to avoid unpleasant surprises with IP on your SoC"
Interconnect system compression analysis for multi-core architectures
A CMOS third order ΔΣ modulator with inverter-based integrators
Power estimation framework for single processor based SoC platform
Effect of a polywell leometry on a CMOS photodiode array
High performance IP lookup circuit using DDR SDRAM
Assertion based design error diagnosis for core-based SoCs
Application of machine learning methods in post-silicon yield improvement
A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor
Reconfigurable flash A/D converters
The role of interconnects in the performance scalability of multicore architectures
Comparative Analysis of Human-Designed vs AI-Generated USB4 Logical Layer: RTL Design and Verification
Performance Optimization of p-Channel SnO Cylindrical Thin Film Transistors (CTFT) Using 3D Modelling
Reconfigurable architecture for video applications
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems
8Gbps high-speed I/O transmitter with scalable speed, swing and equalization levels
HiFi-LLP: High-Fidelity, Low-Cost Latency Predictors with Confidence for Robust HW-NAS
Multi-processor SoC integration: a case study on BlueGene/L
A Compact and High Performance Switch for Circuit-Switched Network-On-Chip
Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications
Adaptive admission control on the SpiNNaker MPSoC
Failure analysis for ultra low power nano-CMOS SRAM under process variations
Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms
BayNNgine: Hardware-Enabled Bayesian Neural Network Support for Dependable AI Inference
Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1™ standard [architecurtes read architectures]
GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systems
Design space exploration for robust power delivery in TSV based 3-D systems-on-chip
A new multi-channel on-chip-bus architecture for system-on-chips
Power-efficient implementation of turbo decoder in SDR system
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications
Well tapping methodologies in power-gating design
A DNN Compression Framework for SOT-MRAM-based Processing-In-Memory Engine
IBM Q - Introduction into quantum computing with live demo
Automatic gain control circuit for power line communication application
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter
On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression
Stereolithography-Based Rectenna for Wireless Energy Harvesting
LLM Assisted Code Coverage Closure
Low power RS codec using cell-based reconfigurable processor
A SiPM Based Sensor For Nuclear Detection Applications
CNN inference: VLSI architecture for convolution layer for 1.2 TOPS
OAL: An obstacle-aware legalization in standard cell placement with displacement minimization
DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage Area
High-Performance random data lookup for network processing
Design of interlock-free combined allocators for Networks-on-Chip
Low-voltage 9T FinFETSRAM cell for low-power applications
Way-load balancing scheme for mobile cache LRU replacement
HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture
LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network
Scalable system map library for address map and data integrity verification
Multiple clock domain synchronization for network on chip architectures
Tutorial 1A: Design challenges for the Internet of Things
A BDD-based approach to design power-aware on-line detectors for digital circuits
Low noise output stage for oversampling audio DAC
A compact pipelined architecture with high-throughput for context-based binary arithmetic coding
Plenary speaker: Low power solutions for a smarter future
Efficient virtual channel allocator for NoC router micro-architecture
A reconfigurable co-processor for GMM-based classifier
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks
Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture
Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory
Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme
Vertical Power Delivery for Emerging Packaging and Integration Platforms - Power Conversion and Distribution
A General Method to VLSI Polyphase Filter Analysis and Design for Integrated RF Applications
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development
Design and verification of complex SoC with configurable, extensible processors
A novel power reduction technique using wire multiplexing
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration
A NAND Flash Endurance Prediction Scheme with FPGA-based Memory Controller System
UCIe Meets mmWave: Scalable, Latency-Aware and Energy-Efficient Hybrid Chiplet Integration
A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector
A body-bias based current sense amplifier for high-speed low-power embedded SRAMs
Efficient high-speed current-mode links for network-on-chip performance optimization
Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip
Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array
Design of a scalable RF microarchitecture for heterogeneous MPSoCs
Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs
Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors
I/Q-Channel Mismatch Transfer and Amplification Effects and Applications to the Measurement and Calibration of Integrated VLIF RF Receivers
High Precision Winner-Take-All Circuit for Neural Networks
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
A Novel Mini-LVDS Receiver in 0.35-um CMOS
Pressure-Activated RF Sensing: A Smart Cushion Approach for Energy-Efficient IoT Health Monitoring
Yield-award placement optimization for Switched-Capacitor analog integrated circuits
A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit
When does Network-on-Chip bypassing make sense?
A novel CMOS exponential approximation circuit
Modeling and simulation of quantum-well infrared photodetectors
Deadline-Aware Interference Mitigation Accelerator Design for Automotive Radar SoC
Propelling breakthrough embedded microprocessors by means of integrated photonics
Robust 3GHz CMOS low noise amplifier adapted for RFID receivers
Plenary presentation A
A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy model
Extensible software emulator for reconfigurable instruction cell based processors
User-Authenticated Device-Independent Quantum Secure Direct Communication Protocol
Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications
Memristive Neural Network with Efficient In-Situ Supervised Training
1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology
Finding ground traces using the laplacian of the meshes of the associated graph
0.5V 1OMS/S 9-Bits Asynchronous SAR ADC for BLE Receivers in L80NM CMOS Technology
Novel adaptive keeper LBL technique for low power and high performance register files
Integration of code optimization and hardware exploration for a VLIW architecture by using fuzzy control system
LDO-based Odometer to Combat IC Recycling
A decomposition-based system level synthesis method for heterogeneous multiprocessor architectures
Optimizing CNN Accelerator With Improved Roofline Model
A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems
A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance
A One-to-Many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platforms
Optimizing Compute Express Link Link Layer Using Adaptive Packing-Mode-Selection Algorithm
Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper
A 64 dB Dynamic Range Programmable Gain Amplifier for Dual Band WLAN 802.11abg IF Receiver in 0.18 μm CMOS Technology
A Low-voltage-Driven Single-ended Column based SRAM for Low-Power Micro-display
Adaptive CDMA based multicast method for photonic networks on chip
Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment
Compiler-assisted technique for rapid performance estimation of FPGA-based processors
PVT variations aware optimal sleep vector determination of dual VT domino OR circuits
Thermal Side-channel Leakage Protection in Monolithic Three Dimensional Integrated Circuits
On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits
Exploring Training of Approximate CNNs using Straight-Through and Linear Regression-Based Gradient Estimation
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit
A Multi-Objective Architecture Optimization Method for Application-Specific Noc Design
Stochastic Glitch Estimation and Path Balancing for Statistical Optimization
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability
Accelerating CRYSTALS-Kyber and Dilithium via a Single Montgomery Reduction ISE on RISC-V
DCVS Level Shifter for Clock Path
Design space exploration for application specific FPGAS in system-on-a-chip designs
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique
A programmable FFT/IFFT/Windowing processor for multi standard DSL applications
Energy-efficient gas recognition system with event-driven power control
F1B: Algorithms, models and simulation for systems
SparHiXcel: A Cost-Effective Sparsity-Aware Convolutional Accelerator
Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes
T2B: Machine learning and parallel architectures
2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013
Efficient Task Graph Generation for DNN Inference on FPGA-based SoC Platforms
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing
Fan-in sensitive low power dynamic circuits performance statistical characterization
Region based cache coherence for tiled MPSoCs
Low-power floating bitline 8-T SRAM design with write assistant circuits
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding
A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step
Crosstalk-aware TSV-buffer Insertion in 3D IC
Reconfigurable framework for high-bandwidth stream-oriented data processing
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture
Design of Ultra-Low Power Combinational Standard Library Cells Using A Novel Leakage Reduction Methodology
Ower and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing
Design of an NoC with on-chip photonic interconnects using adaptive CDMA links
Differential Pass Transistor Pulsed Latch
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor
VFSMC - a core for cycle accurate multithreaded processing in hard real-time Systems-on-Chip
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor
A novel methodology for Multi-Project System-on-a-Chip
Wiring resource minimization for physically-complex Network-on-Chip architectures
eXtreme Energy Conservation for Mobile Communications
Timing-driven placement for carbon nanotube circuits
Synthesis of Linear and Non-linear Analog Circuits
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System
Experimental analysis of substrate isolation techniques for RF-SOC integration
Evaluating mobile SOCs as an energy efficient DSP platform
Evaluating Area-Time-Power Trade-offs in NTT Accelerators for Post-Quantum Cryptography
Routability-driven RDL routing with pin reassignment
A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder
Implementation and Evaluation of a Neural Network-Based LiDAR Histogram Processing Method on FPGA
A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E/D7 Standard and its Efficient Implementation on a DSP Processor
On designing circuit primitives for cortical processors with memristive hardware
On Metric-Driven Development of Embedded Neuromorphic AI
A Jitter Cancellation Circuit for High Speed I/O Interfaces
BlooXY: On a non-invasive blood monitor for the IoT context
Double-differential recording and AGC using amplifier ASIC
Integration of Configurable Processors in a Multiprocessor Platform
Reducing crosstalk noise in high speed FPGAs
Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing
Design and Analysis of 66GHz Voltage Controlled Oscillators for FMCW Radar Applications with Phase Noise Impact Consideration
Neuromorphic computing: A SoC scaling path for the next decades
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash
A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC
Exploration of GFP frame delineation architectures for network processing
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT
Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design
3-D Heterogeneous SoC for detecting and filtering infected biological cells
A Power-Efficient Programmable DCNN Processor for Intelligent Sensing
Ultra-NoC: Unified Low-Transmission Routing Assisted NoC for High-flexible DNN Accelerator
Providing throughput guarantees in mixed-criticality networks-on-chip
Quadrature RF-Only Logic Family for Single-Chip Self-Powered Transceivers
Stochastic glitch elimination considering path correlation
A Learning-Guided Hierarchical Approach for Biomedical Image Segmentation
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems
Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks
Design of a programmable cryptoprocessor for multiple cryptosystems
T3A: Design and managements of multiprocessor systems-on-chips
Unleash the parallelism of 3DIC partitioning on GPGPU
A Runtime Security Monitoring Architecture for Embedded Hypervisors
A 32kHz Crystal Oscillator Leveraging Voltage Scaling in an Ultra-Low Power 40NA Real-Time Clock
Performance evaluation of a FFT using adpative clocking
Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance
A Reconfigurable Viterbi Traceback for Implemenation on Turbo Decoding Array
Non-deterministic Quantization for mmWave Beam Prediction
Evaluation of layout design styles using a quality design metric
Hardware implementation of Hierarchical Temporal Memory algorithm
An embedded read only memory architecture with a complementary and two interchangeable power/performance design points
Real-time efficient FPGA implementation of aes algorithm
On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study
Low energy transmission coding for on-chip serial communications
38th IEEE International System-on-Chip Conference, SOCC 2025, Dubai, United Arab Emirates, September 29 - Oct. 1, 2025
A 120nm CMOS Fully Differential Rail-to-Rail I/O Opamp with Highly Constant Signal Behavior
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects
Composability in the time-triggered system-on-chip architecture
A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors
Constant-Time Modulo: A Secure Hardware Design Against Timing Attacks
A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output
Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware
Flow control solution for efficient communication and congestion avoidance in NoC
X-Route: An X-architecture full-chip multilevel router
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation
Very fast co-simulation model and accurate on-the-fly performance estimation methodology for heterogeneous MPSoC
A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing
Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT
CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs
Tutorial 3B: The design challenges for self-powered wireless wearable ECG sensor SoC
KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs
Feature study on a programmable network traffic classifier
Design automation for Labs-on-Chip: A new "playground" for SoC designers
In-field system-health monitoring based on IEEE 1687
An accelerated successive approximation technique for analog to digital converter design
On circuit design of on-chip non-blocking interconnection networks
Quotient prediction for low power division
0.8% BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique
A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction
Embedded Controllers for Solving Complex Industry Applications
A Low-Cost Fault Injection Attack Resilient FSM Design
Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)
Hybrid MOSFET/CNFET based power gating structure
VLFF - A Very Low-power Flip-flop with only Two Clock Transistors
A run-time distributed cooperative approach to optimize power consumption in MPSoCs
Recent research and emerging challenges in design and optimization for digital microfluidic biochips
Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors
Recent research and emerging challenges in the System-Level Design of digital microfluidic biochips
A High-Performance Router Design for VDSM NoCs