yusuke1997/dblp-id-title huggingface dataset:
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips
Inter-view motion prediction in 3D-HEVC
A Lightweight RISC-V Multi-Core Interaction Framework For Embedded Real-Time Applications
Inductive and ultrasonic wireless power transmission to biomedical implants
Concurrent Self Test of Switched Current Circuits Based on the S 2 I-Technique
STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme
A Sliding and Variable Window Based Multitone Excision for Digital Audio Broadcasting
Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication
High-Order Multilayer Input-Absorptive RF Filter With Wideband Quasi-Flat Group Delay and Multiple Stopband Transmission Zeros
An efficient method for control of continuous-time systems subject to input saturation and external disturbance
Concurrent skew and control step assignments in RT-level datapath synthesis
Pseudorandom carrier based subharmonic PWM for cascaded multilevel inverters
Temperature compensation of floating-gate transistors in field-programmable analog arrays
Sinusoid Signal Generator for On-chip Impedance Spectroscopy
Fast Convergence with Low Precision Weights in ART1 Networks
Colony Fingerprinting - A Novel Method for Discrimination of Food-Contaminating Microorganisms Based on Bioimage Informatics
A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters
A new unified modular adder/subtractor for arbitrary moduli
Wide-range optical CMOS-based diagnostics
A Real-time Point Cloud Segmentation System with Optimized Ground Estimation Algorithm and Selective Neural Network
A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits
A low ripple on-chip charge pump for bootstrapping of the noise-sensitive nodes
Effective two-dimensional pattern generation for self-aligned double patterning
A Design Technique for Polyphase Decimators with Binary Constrained Coefficients for High Resolution A/D Converters
Stability Prediction of Δ∑ Modulators using Artificial Neural Networks
Current-mode image sensor with 1.5 transistors per pixel and improved dynamic range
Development of a high performance TSPC library for implementation of large digital building blocks
A Class-AB Slew Rate-Enhanced OTA for Triboelectric Sensing Interfaces in Smart Textiles
Satellite Navigation: New Signals, New Challenges
Minimization of total area in integrated active RC filters
Mixed-Mode Continuous-Time Video Acquisition Filters
Coverage Optimization of the Tunable Ladder Matching Networks
A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters
A novel application specific network protocol for wireless sensor networks
A high-performance 1D-DCT architecture
Advanced biochip: principle and applications in medical diagnostics and pathogen detection
Computer aided simulation and verification of forward error-correcting biosensors
Design of continuous-time ΣΔ modulators with sine-shaped feedback DACs
An adaptive maximum power point tracker for maximising solar cell efficiency in wireless sensor nodes
Realization and optimization of DSP based H.264 encoder
Live Demonstration: An Intelligent Stethoscope with ECG and Heart Sound Synchronous Display
FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine
A High Bandwidth Modified Regulated Cascode TIA for High Capacitance Photodiodes in VLC
Parameter estimation for target tracking with uncertain sensor positions
A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET
Wearable Multiple Body Signal Monitoring System with Single Biocompatible AlN Piezoelectric Sensor
Wideband DOA Estimation Based on Tensor Completion and Decomposition
Graph problems in multi-hop networks
Quasi-Static Energy Recovery Logic with Single Power-Clock Supply
Bandwidth utilization and signal strength-based handover initiation in mobile multimedia cellular networks
Synaptic sampling in hardware spiking neural networks
Stereo video coding system with hybrid coding based on joint prediction scheme
A ΔΣ ADC for low power sensor applications
Automatic synchronization of speech transcript and slides in presentation
Grouping of Brain MR Images via Affinity Propagation
Synthesis of log-domain integrators for silicon synapses with global parametric control
Comparison of three FPGA architectures for embedded multidimensional categorization through Kohonen's self-organizing maps
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier
Integrated blind electronic equalizer for fiber dispersion compensation
An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction
Non-causal error diffusion for image halftoning
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques
A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem
Bit-width Adaptive Accelerator Design for Convolution Neural Network
Floating-gate FPAA calibration for analog system design and built-in self test
Improving PA efficiency by chaos-based spreading in multicarrier DS-CDMA systems
Area-efficient systolic architectures for inversions over GF(2 m )
New adaptive Kalman filters using filter bank
A Structured ASIC Design Approach Using Pass Transistor Logic
Attentive motion sensor for mobile robotic applications
PointNet on FPGA for Real-Time LiDAR Point Cloud Processing
A simple radix-4 Booth encoded modulo 2 n +1 multiplier
Two-dimensional direction finding for wideband signals using simplified array configuration
Live Demonstration: A VLSI Implementation of Time-Domain Analog Weighted-Sum Calculation Model for Intelligent Processing on Robots
On Securing SSN Architecture using Test Vector Encryption
A novel approach for combinatorial optimization problems using chaotic neurodynamics
Multiple pitch estimation of poly-phonic audio signals in a frequency-lag domain using the bispectrum
LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access
Adaptive Transform Size and Frame-field Selection for Efficient VC-1 to H.264 High Profile Transcoding
A Lightweight and Efficient Schoolbook Polynomial Multiplier for Saber
Feasibility of hybrid ultrasound-electrical nerve stimulation for electroceuticals
Chaotic communications using nonlinear transform-pairs
Design of a 1.5-V high-order curvature-compensated CMOS bandgap reference
All-CMOS subbandgap reference circuit operating at low supply voltage
An efficient algorithm for the conjugate symmetric sequency-ordered complex Hadamard transform
A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA
Performance-driven crosstalk elimination at post-compiler level
An Analogue-Domain, Switch-Capacitor-Based Arithmetic-Logic Unit
A Unified Oscillator-Based TRNG and PUF with a Gate-Tunneling Entropy Source
A Dual Frequency Range Integrated Circuit Accelerometer Using Capacitive and Piezoelectric Sensing Techniques
SENSATION: A New Environment for Automatic Circuit Optimization and Statistical Analysis
A 3-D Integrator-Differentiator Double-Loop (IDD) Filter for Raster-Scan Video Processing
Hybrid silicon/silicone (polydimethylsiloxane) microsystem for cell culture
Response of coupled chaotic circuits to sinusoidal input signal
Constant transconductance bias circuit with an on-chip resistor
Development of an audio player as system-on-a-chip using an open source platform
Design and implementation of multiplier-less tunable 2-D FIR filters using McClellan transformation
Target region-aware tone reproduction
Parasitic capacitance reduction for a Bi-directional floating-base-PNP ESD device for CAN Bus
Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering
Where to cut: Efficient ADC quantization for analog in-memory computing with discrete values
Congestion-driven W-shape multilevel full-chip routing framework
Live Demonstration: A Wearable EIT System for Hand Prosthesis Motion Controls
High Performance CMOS Level up Conversion for Systems with Low-Voltage Power Supply
SLNR Based Hybrid Precoding for HAP Massive MIMO Systems with Limited RF Chains
A pipelined multiply-accumulate unit design for energy recovery DSP systems
Modeling and Validation of Offset Cancellation for Hybrid Photonic-Electronic Transimpedance Amplifier Using All-Electronic Circuits
Classification of BPSK and QPSK signals with unknown signal level using the Bayes technique
A self-calibrated 10-bit 1 MSps SAR ADC with reduced-voltage charge-sharing DAC
Compensation of track and hold frequency response mismatches in interleaved analog to digital converters for high-speed communications
FPGA-Based Hardware Architecture for Sequence Alignment by Genetic Algorithm
A compact low-power VLSI architecture for real-time sleep stage classification
LC filters with enhanced memristive damping
Emerging adaptive antenna techniques for wireless ad-hoc networks
Exact transient and steady state analyses of linear systems with periodic inputs
Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrix
Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping
Simultaneous delay and power optimization in global placement
N-scroll chaotic attractors from a general jerk circuit
Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems
Cell and network level design of a mixed-mode CNN
Rate Control for Spatial/CGS Scalable Extension of H.264/AVC
2D scroll grid attractors from pulse-excited nonautonomous circuits
Hausdorff distance for target detection
A half-pel motion estimation architecture for MPEG-4 applications
Multiple description coding with randomly offset quantizers
Design of CMOS telemetry circuits for in-vivo wireless sonomicrometry
Video special effects editing in MPEG-2 compressed video
HOS based minimal transmit redundancy space-time FIR precoder-blind equalizer
Power spectral density of Transmit Reference Doublet trains and Reference Sharing Doublet trains in ultra wideband systems
Asynchronous balanced gates tolerant to interconnect variability
Knowledge- and optimization-based design of RF power amplifiers
A maximally-digital VCO-ADC with inherent mixing input capability
Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders
Kalman filter for robust noise suppression in white and colored noises
High performance compressive sensing reconstruction hardware with QRD process
Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding
A highly accurate BiCMOS cascode current mirror for wide output voltage range
Implementation of a Cache-Based IPv6 Lookup System with Hashing
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters
Study and behavioural simulation of phase noise and jitter in oscillators
A 93.7% peak efficiency DC-DC buck converter with all-pass network based passive level shifter in 55 nm CMOS
A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces
NeuralPV: A Neural Network Algorithm for PV Power Forecasting
A dynamic frame-skipping video combiner for multipoint video conferencing
Stereo Correspondence based on Rotation Invariant Correlation
A low power adaptive transmitter architecture for low band UWB applications
Unified eigentilter approach: With applications to spectral/spatial filtering
An adaptive multi-layer low-latency transmission scheme for H.264 based screen sharing system
Track Assignment Using Gradient Indication and Simulated Annealing
A study of the partitioned dynamic programming algorithm for genome comparison in FPGA
Targeting Multistable Dynamics in a Second-Order Memristor Circuit
High resolution 2-D DOA estimation using second-order partial-differential of MUSIC spectrum
Integrated radioactive thin films for sensing systems
Analog Filter Banks with Low Intermodulation Distortion
3-D Subband Video Coding Technique Using Adaptive Wavelet Packet Bases
Iterative Multiple-Path One-Shot NAS for the Optimized Performance
A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS
Live Demonstration: Modulating Luminescence Emissions of Solar Cells for Sensing and Identification
A Single-Ended Digital Transmitter Based on I/Q-Sharing Switched-Capacitor Power Amplifier and Third-Order Harmonic-Rejection
Fast pixel-based video scene change detection
Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
Monolithic Graphene Nanoribbon Electronics for Interconnect Performance Improvement
An Algorithm for the Construction of Synthetic Self Synchronizing Biological Circuits
Digital signal processing for reducing the effects of RF imperfections in radio devices - An overview
Statistics in Bilateral Domain: Novel Statistics of Natural Images
A scalable compact architecture for the computation of integer binary logarithms through linear approximation
Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles
Wafer-level adaptive trim seed forecasting based on E-tests
Rate control for replicated video streams
Gain Cell-based Analog Content Addressable Memory for Dynamic Associative Tasks in AI
Operation of class DE amplifier outside optimum condition
Sensitivity-Driven Placement of Analog Modules
Automatic design of high-order SC filter circuits
Design of an OFDM receiver for high-speed wireless LAN
Stochastic dendrites enable online learning in mixed-signal neuromorphic processing systems
Recurrent Deformable Fusion for Compressed Video Artifact Reduction
Exploiting stable features for iris recognition of defocused images
SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors
A unified optimization framework for simultaneous gate sizing and placement under density constraints
Polynomial search algorithms for motion estimation
Utilizing synthesis to verify Boolean function models
BIST for clock jitter measurements
Arrangements of the secondary source on the performance of active noise control systems
A Neuromorphic Head Direction Cell System
A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process
A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm
An Adaptable Mixer-Enabled VCO-Based Edge Sensing Platform for Agile Pulse Monitoring
Ultra Wideband Low Noise N-path Direct Conversion Receiver for 5G-advanced and 6G Wireless System
Algorithm adaptive video deinterlacing using self-validation framework
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
A CMOS current-to-LCD interface for portable amperometric sensing systems
Using granulometries in processing images of malarial blood
New class of the FPGA efficient cryptographic primitives
VLSI implementation of a WiMAX/LTE compliant low-complexity high-throughput soft-output K-Best MIMO detector
An enhanced pulse width modulator with adaptive duty cycle and frequency control
A new approach for diagnosing bridging faults in logic designs
Heterogeneous integration of biomimetic acoustic microsystems
Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting
Implementation and Test Results of a Chip for the Separation of Mixed Signals
An FPGA co-processor for adaptive lane departure warning system
Enhancing Real-Time Video Streaming with Joint Frame Size and Rate Adaptation
Long-Term Memory Performance with Learning Behavior of Artificial Synaptic Memristor Based on Stacked Solution-Processed Switching Layers
1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994
High Speed Analog Filtering Using Feedforward Neural Network Architectures
Ring VCO Phase Noise Optimization by Pseudo-Differential Architecture in 28nm FD-SOI CMOS
Attenuation Compensation for High-Frequency Acoustic-Resolution Photoacoustic Imaging
High Resolution Multi-frequency Digital Phase Locked Loop
Optimal layout of hexagonal minimum spanning trees in linear time [VLSI]
An artificial synapse for interfacing to biological neurons
An adaptive method for consistent parameter estimation of a non-Gaussian MA process
Mismatch calibration strategy for query-driven AER read-out in a memristor-CMOS neuromorphic chip
Coincidence Detection with an Analog Spiking Neuron Exploiting Ferroelectric Polarization
Exploring the Importance of Sensors' Calibration in Inertial Navigation Systems
50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process
A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network
Implant electronics for intraocular epiretinal neuro-stimulators
A CMOS down-conversion micromixer for IEEE 802.11b WLAN transceivers
A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference
Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array
Characterization of a metastability measurement system
A One-Off-Chip-Capacitor Wireless High-Voltage Power Management Unit Generating Regulated Supplies with 80.6-dB-PSRR in Low-Voltage CMOS
A 10Gb/s PI-Based Quarter Rate all Digital CDR with Improved Linearity
Improved method for parameter estimation of complex sinusoids in noise
Analog envelop constrained filter with input uncertainty
A novel flash analog-to-digital converter
A single stage buck-boost three-phase rectifier with high power factor operating in continuous conduction mode (CCM)
Adaptive blind demodulation of DS/CDMA signals with transform domain Griffiths' algorithm
An analytical study of a magnetically tuned matching network
Adaptive Caching Policies for Chiplet Systems Based on Reinforcement Learning
Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic
A secure design-for-test infrastructure for lifetime security of SoCs
A partial scan design by unifying structural analysis and testabilities
Fast rate distortion optimized quantization method for HEVC
Placement-aware Clustering for Integrated Clock and Power Gating
Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area
A low power 2.4/5.2GHz concurrent receiver using current-reused architecture
Fractional-N frequency synthesizer for wireless communications
Automatic Design of Transparent Standard Cells with TRANSCAD II
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code
A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations
Boost converter with high voltage gain using a switched capacitor circuit
The Novel SCR-based ESD Protection Device with High Holding Voltage
Efficient filter bank multicarrier realizations for 5G
DLL based test solution for interposers in 2.5-D ICs
Image Coding Using Vector Filter Bank and Vector Quantization
DNL and INL yield models for a current-steering D/A converter
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model
Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression
Nonlinear techniques and neural activity: emergent trends in MEG data
Noise-Aware Floorplanning for Fast Power Supply Network Design
Complex behaviours in two bi-directionally coupled Lorenz systems
A multistage filterbank-based channelizer and its multiplier-less realization
Register relocation to optimize clock network for multi-domain clock skew scheduling
New design method of sliding mode controller for a class of nonlinear second-order systems
A Multi-Lidar-based Point Cloud Acquisition Platform and Data Fusion for Autonomous Vehicle in Complex Urban Environment
Quantum circuit design of discrete Hartley transform using recursive decomposition formula
Semi-Siamese Network for Content-Based Video Relevance Prediction
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis
Fully integrated 500uW speech detection wake-up circuit
CMOS distributed amplifiers for UWB radar
VaLI: Variability-aware Fine-tuning with Low-rank Adapter and Iterative Training for ReRAM Computation-in-Memory
Simultaneous realization of Z 21 /Z 11 and Y 21 of an RC two-port
A novel list-scheduling algorithm for the low-energy program execution
Synchronization in dynamical oscillatory networks with non-uniform coupling distributions
Reducing Power Consumption in LNA by Utilizing EEG Signals as Basis Matrix in Compressed Sensing
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits
Harmonic signal recovery and order estimation based on cascaded sparse processing
A New Signal and Power Composite Modulation Strategy for SRG Based DC Microgrids
Class-N high-frequency power amplifier
Capacitive-data links, energy-efficient and high-voltage compliant visual intracortical microstimulation system
StereoGest-SNN: Robust Gesture Detection With Stereo Acoustic Setup Using Spiking Neural Networks
Synthesis of a pulse-forming reactance network to shape a delayed quasi-rectangular pulse
Image processing with quantum dot nanostructures
IIR digital filter design via orthogonal projection of singular perturbational model reduction
Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation
Cross coupled transconductance cell with improved linearity range
An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording
A CMOS Low-noise Low-power Quadrature LC Oscillator
Nondestructive durian maturity determination by using microwave free space measurement
Analysis of Random Clock Jitter Effect in Time-Interleaved DACs
A Circuit-Based Noise Parameter Extraction Technique for MOSFETs
An aggregator-less distributed smart sensor network with selective data exchange
3.7μW 0.8V VCO-integrator-based high-efficiency capacitor-free low-dropout voltage regulator
Online calibration of quadrature low-IF receivers
Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces
Design of a non-isolated single-switch three-port DC-DC converter for standalone PV-battery power system
Novel linearization technique for low-distortion high-swing CMOS switches with improved reliability
A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing
Micropower Design of an Energy Autonomous RF Tag for UWB Localization Applications
A low-power RF front-end with merged LNA, differential power splitter, and quadrature mixer for IEEE 802.15.4 (ZigBee) applications
Improved Camera Calibration Method Using Complementary Patterns
20 Years of research on intellectual property protection
Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation
A 12.6V 130MHz Rail-to-Rail Output Bipolar Amplifier with Overdrive Supply Current Limit
Probabilistic Gradient Descent Bit-Flipping Decoders for Flash Memory Channels
A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity
Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron
A CMOS multi-standard receiver architecture for ISM and UNII band applications
Object Tracking Based on RFID Coverage Visual Compensation in Wireless Sensor Network
Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition
An ultra-low quiescent current power management ASIC with MPPT for vibrational energy harvesting
A 7-transistor-per-cell, high-density analog storage array with 500µV update accuracy and greater than 60dB linearity
A Cryogenic Phase-Selection Superconducting Qubit Controller with Envelope-Tracking in 28nm Bulk CMOS
A 14-Gb/s PAM4 Reference-Less Half-Baud-Rate CDR
A Switched-Capacitor Power Side-Channel Attack Detection Circuit in 65-nm CMOS
Complex Motion Planning for Quadruped Robots Using Large Language Models
A High-Performance ORB Accelerator with Algorithm and Hardware Co-design for Visual Localization