yusuke1997/dblp-id-title huggingface dataset:
Efficient timing propagation with simultaneous structural and pipeline parallelisms: late breaking results
NTT-PIM: Row-Centric Architecture and Mapping for Efficient Number-Theoretic Transform on PIM
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm
An experimental comparison of force directed placement techniques
LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop Prediction
Physical synthesis methodology for high performance microprocessors
On lower bounds for scheduling problems in high-level synthesis
A Cost Efficient Online Algorithm for Automotive Idling Reduction
Macro-modeling concepts for the chip electrical interface
Panel: (When) Will FPGAs Kill ASICs?
Enabling Failure-resilient Intermittently-powered Systems Without Runtime Checkpointing
Stochastic-HMDs: Adversarial-Resilient Hardware Malware Detectors via Undervolting
DOSS: a storage system for design data
Theoretical and practical limits of dynamic voltage scaling
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator
An overview of the design and verification subsystem of the Engineering Design System
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems
Hierarchical analysis of IC artwork with user defined abstraction rules
The ADAM advanced design automation system: overview, planner and natural language interface
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates
Mixed signals on mixed-signal: the right next technology
Efficient memory partitioning for parallel data access in multidimensional arrays
Functionality matters in netlist representation learning
Functional Verification of SiCortex Multiprocessor System-on-a-Chip
Physics-based field-theoretic design automation tools for social networks and web search
Wire length prediction based clustering and its application in placement
Synthesis by delayed binding of decisions
Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN
RTG: automatic register level test generator
A method for correcting the functionality of a wire-pipelined circuit
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
An optimized ATPG
On Global Wire Ordering for Macro-Cell Routing
Accurate timing analysis by modeling caches, speculation and their interaction
Fast statistical timing analysis handling arbitrary delay correlations
A computing origami: folding streams in FPGAs
Self-testing with correlated faults
Dynamic thread and data mapping for NoC based CMPs
Improved Approximate Reachability Using Auxiliary State Variables
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation
HoBBy: Hardening Unbalanced Branches against Control Flow Attacks on Intel SGX and AMD SEV
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
Security as a new dimension in embedded system design
Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data
3D Scheduling: High-Level Synthesis with Floorplanning
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
Reducing BDD Size by Exploiting Functional Dependencies
ACORN: a local customization approach to DCVS physical design
Transistor Size Optimization in the Tailor Layout System
Multi-Objective Local-Search Optimization using Reliability Importance Measuring
An Efficient Two-level DC Operating Points Finder for Transistor Circuits
"Microprogramming - uses and tradeoffs"
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Next generation wireless-multimedia devices: who is up for the challenge?
High-level power management of embedded systems with application-specific energy cost functions
FedLight: Federated Reinforcement Learning for Autonomous Multi-Intersection Traffic Signal Control
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling
System architecture and software design for electric vehicles
Invited: Software Defined Accelerators From Learning Tools Environment
Quality level and fault coverage for multichip modules
An accurate time delay model for large digital network simulation
A "lookahead" router for multilayer printed wiring boards
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search
Code Compression for Embedded Systems
An Improved Algorithm for Minimum-Area Retiming
RTL c-based methodology for designing and verifying a multi-threaded processor
D-C and transient analysis of networks using a digital computer
Wire Segmenting for Improved Buffer Insertion
Invited: Hardware/Software Co-Synthesis and Co-Optimization for Autonomous Systems
FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs
Optimized Code Generation of Multiplication-free Linear Transforms
Exploiting program-level masking and error propagation for constrained reliability optimization
VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable Faults
High-Level Synthesis for Testability: A Survey and Perspective
A timing verification system based on extracted MOS/VLSI circuit parameters
Coverage Estimation for Symbolic Model Checking
An integrated CAD system for architecture
Making non-volatile nanomagnet logic non-volatile
DACPara: A Divide-and-Conquer Parallel Approach for High-Quality Logic Rewriting in Large-Scale Circuits
Net Resource Allocation: A Desirable Initial Routing Step
Invited paper: Enhancing Design Automation with Quantum Algorithms for Chip Design
Signature-based workload estimation for mobile 3D graphics
An error tolerance scheme for 3D CMOS imagers
HAFIX: hardware-assisted flow integrity extension
An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm
Forensic engineering techniques for VLSI CAD tools
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks
Dadu: Accelerating Inverse Kinematics for High-DOF Robots
A computer aided interconnection system
INVITED: AI Utopia or Dystopia - On Securing AI Platforms
Placement of digital microfluidic biochips using the t-tree formulation
SABLE: A tool for generating structured, multi-level simulations
Can CAD meet the VLSI design problems of the 80's?
Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators
Tracking appliance usage information in residential settings using off-the-shelf low-frequency meters
Adaptive data partitioning for ambient multimedia
Aquarius: Logic simulation on an Engineering Workstation
Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998
A discipline for generating practical optimal structural designs
SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering
MCNC's vertically integrated symbolic design system
Technology Mapping Using Fuzzy Logic
Energy efficient computation with asynchronous races
Experiments using interactive color raster graphics for CAD
An optimized page translation for mobile virtualization
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation
Power network analysis using an adaptive algebraic multigrid approach
Robust Techniques for Watermarking Sequential Circuit Designs
Optimal Scheduling and Allocation of Embedded VLSI Chips
Autonomous Automobiles: Developing Cars That Drive Themselves
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays
On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction
Area-time efficient addition in charge based technology
Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm
The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment
Dual quadtree representation for VLSI designs
Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping
Faster Architectural Simulation Through Parallelism
Automatic scenario detection for improved WCET estimation
DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions
Lightweight Structural Choices Operator for Technology Mapping
Compressive sensing based asymmetric semantic image compression for resource-constrained IoT system
Exploring the programmability for deep learning processors: from architecture to tensorization
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
Visual Cortex Inspired Pixel-Level Re-configurable Processors for Smart Image Sensors
Efficient Software Performance Estimation Methods for Hardware/Software Codesign
Effective safety property checking using simulation-based sequential ATPG
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing
Implementing an FPGA system for real-time intent recognition for prosthetic legs
Aspect-oriented Modeling of Attacks in Automotive Cyber-Physical Systems
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach
LEMOE: LLM-Enhanced Multi-Objective Bayesian Optimization for Microarchitecture Exploration
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition
A family of cells to reduce the soft-error-rate in ternary-CAM
HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs
Resource budgeting for reliability in reconfigurable architectures
Computer-aided computer-aided design: Improving CAD programmer productivity
Test application time and volume compression through seed overlapping
PRIMEAIDS: An integrated electrical design environment
A method for IC layout verification
A language for selective distortion of spatial structures
A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction
BEOL variability and impact on RC extraction
Flute - a floorplanning agent for full custom VLSI design
Piece-wise approximations of RLCK circuit responses using moment matching
RASSP Virtual Prototyping of DSP Systems
High Performance and Low Power Electronics on Flexible Substrate
A New Nonlinear Driver Model for Interconnect Analysis
Efficient Monte Carlo based incremental statistical timing analysis
The design and use of simplepower: a cycle-accurate energy estimation tool
ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training
SGL: Spectral Graph Learning from Measurements
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs
Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems
A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations
Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas
Task Mapping on SMART NoC: Contention Matters, Not the Distance
SEGMA - A simulation package for conception aid and fault tolerance evaluation of computing systems
Non-intrusive dynamic application profiling for multitasked applications
Multi-defect real time diagnosis using a single pin probe
Hierarchical memory-constrained operator scheduling of neural architecture search networks
Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers
A design study on graphics support in a Fortran environment
A Framework for Industrial Layout Generators
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores
A holistic approach for statistical SRAM analysis
A new enhanced constructive decomposition and mapping algorithm
Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks
"Timing closure by design, " a high frequency microprocessor design methodology
Routability-driven and fence-aware legalization for mixed-cell-height circuits
Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators
Process Multi-Circuit Optimization
Predicate learning and selective theory deduction for a difference logic solver
A 10 Mbit/s Upstream Cable Modem with Automatic equalization
Knowledge Based Approach for the Verification of CAD Database Generated by an Automated Schematic Capture System
Reducing serial I/O power in error-tolerant applications by efficient lossy encoding
EENet: Energy Efficient Neural Networks with Run-time Power Management
Switch Directed Dynamic Causal Networks - a Paradigm for Electronic System Diagnosis
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
Synthesizing SVA Local Variables for Formal Verification
RUPlace: Optimizing Routability via Unified Placement and Routing Formulation
The Transfer of University Software for Industry Use
A preprocessor for the via minimization problem
Partitioning of logic graphs: A theoretical analysis of pin reduction
GreenTPU: Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit
An interactive design automation system
Managing a large volume of design/manufacturing/test data in a chip and module factory
The Aurora RAM Compiler
A human engineered PCB design system
DeFer: deferred decision making enabled fixed-outline floorplanner
A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts
Classification of PCB types for cost effective solutions
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors
DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix Multiplication
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance
BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs
Signal delay in RC tree networks
Parametric Representations of Boolean Constraints
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis
Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuits
System-level exploration with SpecSyn
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
An IDF-based trace transformation method for communication refinement
An effective delay analysis system for a large scale computer design
Verification problems in reusing internal design components
InfoPad - An Experiment in System Level Design and Integration
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells
A general decomposition strategy for verifying register renaming
iTaskSense: Task-Oriented Object Detection in Resource-Constrained Environments
Switch-level simulation of VLSI using a special-purpose data-driven computer
Forest vs. trees: where's the slack?
LAMBDA: A quick, low cost layout design system for master-slice LSI s
Powertrain Co-Simulation using AUTOSAR and the Functional Mockup Interface standard
Uncertainty-aware circuit optimization
Application of Term Rewriting Techniques to Hardware Design Verification
CamSkyGate: camouflaged skyrmion gates for protecting ICs
A layout system for the random logic portion of MOS LSI
Worst-case Delay Estimation of Transistor Groups
Invited: Autonomous Driving Digital Twin Empowered Design Automation: An Industry Perspective
Computer aided LSI circuit design: A relationship between topology and performance
DySpMM: From Fix to Dynamic for Sparse Matrix-Matrix Multiplication Accelerators
Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter
Energy optimization by exploiting execution slacks in streaming applications on multiprocessor systems
A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow
The N. mPc system description facility
Timing analysis with nonseparable statistical and deterministic variations
DREDGE: Dynamic Repartitioning during Dynamic Graph Execution
Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software
Improving PUF security with regression-based distiller
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
Invited: Accelerating Fully Homomorphic Encryption with Processing in Memory
Static Timing Analysis of Embedded Software
POGO: Programmer-oriented graphics operation
EDiFy: An Execution time Distribution Finder
Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation
The zen of nonvolatile memories
Accelerator design with decoupled hardware customizations: benefits and challenges: invited
UPVSS: Jointly Managing Vector Similarity Search with Near-Memory Processing Systems
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs
Synthesis of Embedded Software Using Free-Choice Petri Nets
A novel verification technique to uncover out-of-order DUV behaviors
RegPlace: a high quality open-source placement framework for structured ASICs
APPEND: Rethinking ASIP Synthesis in the Era of AI
Making cyclic circuits acyclic
Regularization of hierarchical VHDL-AMS models using bipartite graphs
LORES - Logic Reorganization System
Way Stealing: cache-assisted automatic instruction set extensions
Invited - Wireless sensor nodes for environmental monitoring in internet of things
TAAS: a timing-aware analytical strategy for AQFP-capable placement automation
HAL: a multi-paradigm approach to automatic data path synthesis
INCREDYBLE-TG : INCREmental DYnamic test generation based on LEarning
PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration
Fast maze router
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules
Formal methods for semi-autonomous driving
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications
A Modular Partitioning Approach for Asynchronous Circuit Synthesis
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDs
Support vector machines for analog circuit performance representation
Carbon nanotube field-effect transistors and logic circuits
A near-storage framework for boosted data preprocessing of mass spectrum clustering
Symbolic system synthesis in the presence of stringent real-time constraints
Interactive specification of structured designs
Low Energy Memory and Register Allocation Using Network Flow
Lightning Talk: Can memory technologies meet demands of data abundant applications?
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs
On harmonic fixed-priority scheduling of periodic real-time tasks with constrained deadlines
The use of color and 3-D temporal and spatial data management techniques in computer-aided design
Correction and wiring check-system for master-slice LSI
Multifunctional photonic integration for the agile optical internet
An up-stream design auto-fix flow for manufacturability enhancement
Uncertainty-Aware Energy Management for Wearable IoT Devices with Conformal Prediction
InstantNet: Automated Generation and Deployment of Instantaneously Switchable-Precision Networks
Nuts and Bolts of Core and SoC Verification
Parameterized timing analysis with general delay models and arbitrary variation sources
Technology design rules - a user's perspective
Automatic Test Knowledge Extraction from VHDL (ATKET)
Muffin: A Framework Toward Multi-Dimension AI Fairness by Uniting Off-the-Shelf Models
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy
SARA: self-aware resource allocation for heterogeneous MPSoCs
Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies
ABCD-L: approximating continuous linear systems using boolean models
Loop Optimization in Register-Transfer Scheduling for DSP-Systems
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique
Optimization of negative gate networks realized in weinberger-LIKF layout in a boolean level silicon compiler
SecDCP: secure dynamic cache partitioning for efficient timing channel protection
Fine-grained application source code profiling for ASIP design
B*-Trees: a new representation for non-slicing floorplans
Scalable Generic Logic Synthesis: One Approach to Rule Them All
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration
Device aging-based physically unclonable functions
DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping
Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning
Dynamic Chip Clustering and Task Allocation for Real-time Flash
Sequence Compaction for Probabilistic Analysis of Finite-State Machines
A New Model for Improving symbolic Product Machine Traversal
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions
Aesop: A Tool for Automated Transistor Sizing
Role of power grid in side channel attack and power-grid-aware secure design
Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Mask Verification on the Connection Machine
Side-Channel Attack Pitfalls
Verification for fault tolerance of the IBM system z microprocessor
Design automation and queueing networks: An interactive system for the evaluation of computer queueing models
NOFIS: Normalizing Flow for Rare Circuit Failure Analysis
The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer
Why is ATPG Easy?
On Timing Closure: Buffer Insertion for Hold-Violation Removal
Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
Automating mask layout and specification panel session
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach
Functional Verification - Real Users, Real Problems, Real Opportunities (Panel)
Fault-tolerant 3D clock network
Constraint-driven communication synthesis
Graph-optimization techniques for IC layout and compaction