yusuke1997/dblp-id-title huggingface dataset:
Eagle-eye: a near-optimal statistical framework for noise sensor placement
Timing verification of sequential domino circuits
DEC's engineering to manufacturing BRIDGE system based on the D-BUS architecture
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Minimizing the number of test configurations for FPGAs
Power optimization using divide-and-conquer techniques for minimization of the number of operations
Symmetry detection and dynamic variable ordering of decision diagrams
DSP address optimization using a minimum cost circulation technique
Optimal allocation of carry-save-adders in arithmetic optimization
Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) Designs
Improved interconnect sharing by identity operation insertion
An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing
CacheGuardian: A Timing Side-Channel Resilient LLC Design
Parameterized transient thermal behavioral modeling for chip multiprocessors
A Unified Framework for the Formal Verification of Sequential Circuits
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
ICCAD-2017 CAD contest in resource-aware patch generation
Kauffman networks: analysis and applications
A methodology for the early exploration of design rules for multiple-patterning technologies
A circuit-software co-design approach for improving EDP in reconfigurable frameworks
Exploiting level sensitive latches in wire pipelining
Module placement on BSG-structure and IC layout applications
Network and Compiler Optimizations for Efficient Linear Algebra Kernels in Private Transformer Inference (Invited Paper)
Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations
Induction-Based Gate-Level Verification of Multipliers
How to Obtain and Run Light and Efficient Deep Learning Networks
GPU Acceleration for Versatile Buffer Insertion
Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators
DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network
QCIR: Pattern Matching Based Universal Quantum Circuit Rewriting Framework
HLS-based optimization and design space exploration for applications with variable loop bounds
DIVE: Dynamic Information-Guided Variable Expansion for Deeper Analog Circuit Optimization
Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion
CTDM: Resource-Efficient FPGA-Accelerated Simulation of Large-Scale NPU Designs
2019 CAD Contest: System-level FPGA Routing with Timing Division Multiplexing Technique
RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture
Modeling and analysis of (nonstationary) low frequency noise in nano devices: a synergistic approach based on stochastic chemical kinetics
Knowledge-Based Debugging of ASICs: Real Case Study and Performance Analysis
Carioca-A 'smart' and flexible switch-box router
Platform-based resource binding using a distributed register-file microarchitecture
Folding of logic functions and its application to look up table compaction
Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis
Hierarchical Power Co-Optimization and Management for LLM Chiplet Designs
Getting to the bottom of deep submicron
Temperature tracking: an innovative run-time approach for hardware Trojan detection
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Optimal checkpointing for secure intermittently-powered IoT devices
FabGPT: An Efficient Large Multimodal Model for Complex Wafer Defect Knowledge Queries
Steady-state analysis of voltage and current controlled oscillators
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects
The reproducing placement problem with applications
Towards Accurate Characterization of In-Memory Computing Non-Idealities: A Physics & Data Co-Driven Generative Framework
Combining optimistic and pessimistic DVS scheduling: An adaptive scheme and analysis
Test scheduling for core-based systems
FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric
Post-route alleviation of dense meander segments in high-performance printed circuit boards
An approximate timing analysis method for datapath circuits
Hybrid CEGAR: combining variable hiding and predicate abstraction
Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies
Configuration bitstream compression for dynamically reconfigurable FPGAs
Three-phase chip planning - an improved top-down chip planning strategy
MGR: Multi-level global router
Mitigating the Power Density and Temperature Problems in the Nano-Era
Accurate layout area and delay modeling for system level design
RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Positive/Negative Approximate Multipliers for DNN Accelerators
High-speed compiled-code simulation of transition faults
Towards formal evaluation and verification of probabilistic design
Ultra high density logic designs using transistor-level monolithic 3D integration
Noise based logic: Why noise?
Noise in deep submicron digital design
Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
A Flexible Architecture for Systematic Implementation of SoC Security Policies
Synthesis of reusable DSP cores based on multiple behaviors
The role of adaptation and resiliency in computation and power management
A new approach to simultaneous buffer insertion and wire sizing
Global refinement for building block layout
A Flexible Scheme for State Assignment Based on Characteristics of the FSM
Latency-Guided On-Chip Bus Network Design
An algorithm for power estimation in switched-capacitor circuits
Simultaneous escape routing and layer assignment for dense PCBs
Thermal analysis in SPICE
Sequential optimisation without state space exploration
General framework for removal of clock network pessimism
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow
Optimization of FinFET-based circuits using a dual gate pitch technique
A Parallel Analytical Legalization Algorithm via Alternating Direction Method of Multipliers
pGRASS-Solver: A Parallel Iterative Solver for Scalable Power Grid Analysis Based on Graph Spectral Sparsification
Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms
H 2 EAL: Hybrid-Bonding Architecture with Hybrid Sparse Attention for Efficient Long-Context LLM Inference
Building an Open CGRA Ecosystem for Agile Innovation
Robust latch mapping for combinational equivalence checking
Towards High Performance and Accurate BNN Inference on FPGA with Structured Fine-Grained Pruning
Precise identification of the worst-case voltage drop conditions in power grid verification
ORCHARD: Visual object recognition accelerator based on approximate in-memory processing
Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration
Interconnect parasitic extraction in the digital IC design methodology
Apollo: Automated Routing-Informed Placement for Large-Scale Photonic Integrated Circuits
SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization
Feedback-Driven Datapath Optimization in Fasolt
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control
A Point Transformer Accelerator with Fine-Grained Pipelines and Distribution-Aware Dynamic FPS
Leakage power modeling and reduction with data retention
The fast optimal voltage partitioning algorithm for peak power density minimization
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy
TILA: Timing-Driven Incremental Layer Assignment
Formal verification of phase-locked loops using reachability analysis and continuization
ALISE: Accelerating Large Language Model Serving with Speculative Scheduling
Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits
METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session Paper
Optimization of hierarchical designs using partitioning and resynthesis
Progress and challenges in VLSI placement research
Robust object estimation using generative-discriminative inference for secure robotics applications
Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices
A new global router for row-based layout
Hardware implementation of BLTL property checkers for acceleration of statistical model checking
Dynamic test signal design for analog ICs
Thermal-sensitive design and power optimization for a 3D torus-based optical NoC
Sizing and verification of communication buffers for communicating processes
Interval-valued reduced order statistical interconnect modeling
An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus
Optimal layout decomposition for double patterning technology
Detecting Fraudulent Services on Quantum Cloud Platforms via Dynamic Fingerprinting
Reliability, thermal, and power modeling and optimization
A statistical optimization-based approach for automated sizing of analog cells
MuSTNet: SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement Awareness
Area minimization for general floorplans
Invited Paper: End-to-end RFIC Topology Synthesis and Design combining Reinforcement learning and Inverse Design
Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
Software-Style Hardware Debugging: A Hardware Generation, Simulation and Debugging Framework
Canonicalization of threshold logic representation and its applications
Unit delay simulation with the inversion algorithm
Accurate Hybrid Delay Models for Dynamic Timing Analysis
Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization
Graph matching-based algorithms for FPGA segmentation design
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
Large-Scale Circuit Placement: Gap and Promise
Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI Systems
DIMA: a depthwise CNN in-memory accelerator
Consistency and observability invariance in multi-level logic synthesis
Evaluating the Security of eFPGA-Based Redaction Algorithms
QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults
Model and integrate medical resource availability into verifiably correct executable medical guidelines
Overview of vectorless/early power grid verification
Risk Propagation Based Vector Profiling for High Coverage Dynamic IR-Drop Analysis
PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern Pruning
Phantom redundancy: a high-level synthesis approach for manufacturability
System-level routing of mixed-signal ASICs in WREN
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
Delay Budgeting for a Timing-Closure-Driven Design Method
GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging
fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU
Adjustable Width Linear Combinational Scan Vector Decompression
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Delay Computation in Combinational Logic Circuits: Theory and Algorithms
Digitalization of mixed-signal functionality in nanometer technologies
Power consumption characterization, modeling and estimation of electric vehicles
Multi-level logic optimization by implication analysis
Vulnerability assessment and defense technology for smart home cybersecurity considering pricing cyberattacks
RandOhm: Mitigating Impedance Side-channel Attacks using Randomized Circuit Configurations
The case for retiming with explicit reset circuitry
PGT_SOLVER: An efficient solver for power grid transient analysis
Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate
Optimal routing algorithms for pin clusters in high-density multichip modules
Performance optimization of sequential circuits by eliminating retiming bottlenecks
A symbolic method to reduce power consumption of circuits containing false paths
Validation coverage analysis for complex digital designs
Low-power clock trees for CPUs
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy
Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis
Behavior-to-Placed RTL Synthesis with Performance-Driven Placement
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk)
Efficient Ultra-Dense 3D IC Power Delivery and Cooling Using 3D Thermal Scaffolding
CycSAT: SAT-based attack on cyclic logic encryptions
On the optimization power of retiming and resynthesis transformations
Keynote address: Design of secure systems - Where are the EDA tools?
A New Template Based Approach to Module Generation
Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators
Test Vector Minimization During Logic Synthesis
A corner stitching compliant B ∗ -tree representation and its applications to analog placement
TransSizer: A Novel Transformer-Based Fast Gate Sizer
State transformation in event driven explicit simulation
Simulating sigma-delta modulators in AWEswit
System level verification of digital signal processing applications based on the polynomial abstraction technique
Bisim: a simulator for custom ECL circuits
Statistical technology mapping for parametric yield
Reducing structural bias in technology mapping
Pseudo Adjoint Optimization: Harnessing the Solution Curve for SPICE Acceleration
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
Statistical design and optimization of SRAM cell for yield enhancement
Bridging pre- and post-silicon debugging with BiPeD
Built-in self-test for large embedded CMOS folded PLAs
Global Interconnect Optimization
CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature
GPU-Accelerated Static Timing Analysis
3D-MoE: Accelerating Multi-Expert Activated LLMs on 3D In/Near-Memory Computing Architecture via Hybrid Parallelism
VLSI Placement Parameter Optimization using Deep Reinforcement Learning
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Quantum Machine Learning for Finance ICCAD Special Session Paper
Logic synthesis of binarized neural networks for efficient circuit implementation
BIST TPG for faults in system backplanes
Technology Mapping Using Multi-Output Library Cells
An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators
Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature Selection
FPGA-CC: Confidential Containers for Virtualized FPGAs
Techniques for energy minimization of communication pipelines
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints
Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices
Invited Paper: 2025 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop
2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009
Hardware security: threat models and metrics
An efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuits
Converting Combinational Circuits into Pipelined Data Paths
Random pattern testable logic synthesis
Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage Cards
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning
Victim alignment in crosstalk aware timing analysis
An empirical model for accurate estimation of routing delay in FPGAs
RFUZZ: coverage-directed fuzz testing of RTL on FPGAs
Simulation Framework and Optimization of Superconducting Transmon-Tunable Coupler-Transmon System for Qudit Gates
Overview of the 2017 CAD contest at ICCAD: Invited paper
Soft error reduction in combinational logic using gate resizing and flipflop selection
An ASIP instruction set optimization algorithm with functional module sharing constraint
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays
What is the cost of delay insensitivity?
Implementation and use of SPFDs in optimizing Boolean networks
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
MatFactory: A Framework for High-Performance Matrix Factorization on FPGAs
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability
Achieving fast sanitization with zero live data copy for MLC flash memory
OA-LAMA: An Outlier-Adaptive LLM Inference Accelerator with Memory-Aligned Mixed-Precision Group Quantization
Statistical Learning in Chip (SLIC)
An optimization-theoretic approach for attacking physical unclonable functions
Word Level Property Directed Reachability
State re-encoding for peak current minimization
Floorplan design using distributed genetic algorithms
Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization
A symbolic analysis tool for analog circuit design automation
SOI technology and tools (abstract)
KirchhoffNet: A Scalable Ultra Fast Analog Neural Network
OpenSource Heterogeneous Chiplet-based Computing Architectures
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit
A band relaxation algorithm for reliable and parallelizable circuit simulation
ECSTASY: a new environment for IC design optimization
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Compaction of ATPG-generated test sequences for sequential circuits
Statistically certified approximate logic synthesis
GRASP based metaheuristics for layout pattern classification
Multi-way VLSI circuit partitioning based on dual net representation
On the preconditioner of conjugate gradient method - A power grid simulation perspective
Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning
DALS: delay-driven approximate logic synthesis
A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs
ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing
Designing Energy-Efficient Decision Tree Memristor Crossbar Circuits Using Binary Classification Graphs
Delay computation in switch-level models of non-treelike MOS circuits
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing
Efficient state space exploration: Interleaving stateless and state-based model checking
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions
Prospects for emerging nanoelectronics in mainstream information processing systems
Simultaneous functional-unit binding and floorplanning
A parallel preconditioning strategy for efficient transistor-level circuit simulation
STAR: Improving Lifetime and Performance of High-Capacity Modern SSDs Using State-Aware Randomizer
Considering fabrication in sustainable computing
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Logical effort based technology mapping
PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design
Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
Verifying clock schedules
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems
Exact evaluation of memory size for multi-dimensional signal processing systems
A New Global Router Based on a Flow Model and Linear Assignment
DeepGate3: Towards Scalable Circuit Representation Learning
Lightweight secure PUFs
Trunk decomposition based global routing optimization
BDD-based synthesis of reconfigurable single-electron transistor arrays
Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays
Boolean constrained encoding: a new formulation and a case study
Fast power estimation for deterministic input streams
A new layout optimization methodology for CMOS complex gates
Uranus: Ultra-efficient Acceleration Architecture for the Privacy Inference of Graph Neural Networks
Improving shared cache behavior of multithreaded object-oriented applications in multicores
Multi-layer interconnect performance corners for variation-aware timing analysis
Accelerating Exact Combinatorial Optimization via RL-based Initialization - A Case Study in Scheduling
Hardening extended memory access control schemes with self-verified address spaces
Data-parallel simulation for fast and accurate timing validation of CMOS circuits
CCCS: Customized SPICE-level Crossbar-array Circuit Simulator for In-Memory Computing
µLAM: A LLM-Powered Assistant for Real-Time Micro-architectural Attack Detection and Mitigation
Interpolating functions from large Boolean relations
On multilevel circuit partitioning
An exact minimizer for Boolean relations
A simple algorithm for fanout optimization using high-performance buffer libraries
RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis
Power vs. delay in gate sizing: conflicting objectives?
Track Assignment in the Pathway Datapath Layout Assembler
Linear decomposition algorithm for VLSI design applications
Computation of minimal counterexamples by using black box techniques and symbolic methods
Fast-yet-accurate PVT simulation by combined direct and iterative methods
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes
Switch-level VHDL descriptions
Multi-Stage Optimization for Energy-Efficient Active Cell Balancing in Battery Packs
Two-level logic minimization for low power
Stochastic error rate estimation for adaptive speed control with field delay testing
Probabilistic model checking for comparative analysis of automated air traffic control systems
Cell Library Characterization using Machine Learning for Design Technology Co-Optimization
Overview of the 2016 CAD contest at ICCAD
Towards interdependencies of aging mechanisms
A novel unified dummy fill insertion framework with SQP-based optimization method
ALISA: An Adaptive Learned Index Structure for Spatial Data on Solid-State Drives
POLAR 3.0: An Ultrafast Global Placement Engine
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis
Bandwidth-aware reconfigurable cache design with hybrid memory technologies
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals