yusuke1997/dblp-id-title huggingface dataset:
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency
Deflection-routed butterfly fat trees on FPGAs
Design Flow for Efficient FPGA Reconfiguration
FPL Demo: Logic Shrinkage: A Neural Architecture Search-Based Approach to FPGA Netlist Generation
How fast is an FPGA in image processing?
Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems
FPGA Resource Reduction Through Truncated Multiplication
Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA
Timing-Aware Routing in the RapidWright Framework
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs
High-speed programmable FPGA Configuration through JTAG
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration
Power Modelling in Field Programmable Gate Arrays (FPGA)
K-means clustering on CGRA
f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs
Automated Speculation and Parallelism in High Performance Network Applications
On the design parameters of runtime reconfigurable systems
A Framework for Teaching (Re)Configurable Architectures in Student Projects
Logarithmic Number System and Floating-Point Arithmetics on FPGA
Bambu: A modular framework for the high level synthesis of memory-intensive applications
The study of three-dimensional multiphase-flow simulator
Efficient AES S-boxes implementation for non-volatile FPGAs
Generation of partial FPGA configurations at run-time
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016
An efficient and flexible host-FPGA PCIe communication library
Multi-fidelity Optimization for High-Level Synthesis Directives
Exploiting Stateful Inspection of Network Security in Reconfigurable Hardware
Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System
A Pipeline Implementation of a Watershed Algorithm on FPGA
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations
Telecommunication-Oriented FPGA and Dedicated CAD System
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems
Multiplexer Based Reconfiguration for Virtex Multipliers
The Chess Monster Hydra
Implementing Stream-Processing Applications on FPGAs: A DSL-Based Approach
Evaluation of the XC6200-series Architecture for Cryptographic Applications
Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications
A Unified Streaming Architecture for Real Time Face Detection and Gender Classification
RAMP Blue: A Message-Passing Manycore System in FPGAs
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
FPGA acceleration of SAT/Max-SAT solving using variable-way cache
Postscript TM rendering with virtual hardware
Dynamic Polymorphic Reconfiguration for anti-tamper circuits
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro
Replace: An incremental placement algorithm for field programmable gate arrays
A high-performance system-on-chip architecture for direct tracking for SLAM
The Architecture of a General-Purpose Processor Cell
Memory System for a Dynamically Adaptable Pixel Stream Architecture
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs
sFPGA - A scalable switch based FPGA architecture and design methodology
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
A high performance deblocking filter hardware for High Efficiency Video Coding
A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller
Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol
Implementing Asynchronous Circuits on LUT Based FPGAs
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA
Formal Verification of Timing Rules in Design Specifications
Reduced complexity single and multiple constant multiplication in floating point precision
Auto-configurable array for GCD computation
Real Environments Image Labelling Based on Reconfigurable Architectures
Multi-kernel floorplanning for enhanced CGRAS
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
Accelerating low bit-width convolutional neural networks with embedded FPGA
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory
GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains
Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs
Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays
Regular Expression Software Deceleration for Intrusion Detection Systems
Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces
H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP Architecture
A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems
General Purpose Computing with Reconfigurable Acceleration
Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering
28th International Conference on Field Programmable Logic and Applications, FPL 2018, Dublin, Ireland, August 27-31, 2018
Exploiting Redundancy to Speedup Reconfiguration of an FPGA
CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters
Mapping basic prefix computations to fast carry-chain structures
TputCache: High-frequency, multi-way cache for high-throughput FPGA applications
Fast and accurate resource estimation of RTL-based designs targeting FPGAS
Run-time resource management in fault-tolerant network on reconfigurable chips
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems
A variable length hash method for faster short read mapping on FPGA
A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs
Fast and area efficient adder for wide data in recent Xilinx FPGAs
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
A Radix Tree Router for Scalable FPGA Networks
Academia to IPO - A Modern Odyssey
FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding
An FPGA-based Node Controller for a High Capacity WDM Optical Packet Network
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic
H2PIPE: High Throughput CNN Inference on FPGAs with High-Bandwidth Memory
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
Operation scheduling for FPGA-based reconfigurable computers
Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer
Evaluating high-level design strategies on FPGAs for high-performance computing
ATCA-based computation platform for data acquisition and triggering in particle physics experiments
Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts
CRUSH: Cognitive Radio Universal Software Hardware
FPGA's Middleware for Software Defined Radio Applications
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
Toward a pixel-parallel architecture for graph cuts inference on FPGA
Efficient FPGA Resynthesis Using Precomputed LUT Structures
Adaptive Thermoregulation for Applications on Reconfigurable Devices
An On-Line Arithmetic Based FPGA for Low-Power Custom Computing
The power of communication: Energy-efficient NOCS for FPGAS
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Unleashing Parallelism in Elastic Circuits with Faster Token Delivery
In-network online data analytics with FPGAs
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
Efficient Self-Reconfigurable Implementations Using On-chip Memory
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks
Automation of IP Core Interface Generation for Reconfigurable Computing
Integrated Layout Synthesis for FPGAs
Power/performance optimization in FPGA-based asymmetric multi-core systems
Pipelined Floating Point Arithmetic Optimized for FPGA Architectures
Body bias grain size exploration for a coarse grained reconfigurable accelerator
Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules
A comparison of embedded reconfigurable video-processing architectures
Towards in the Field Fast Pathogens Detection Using FPGAs
Code Re-ordering for a Class of Reconfigurable Microprocessors
A region merging approach for image segmentation on FPGA
An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers
Implementing GCD Systolic Arrays on FPGA
A Radiation Hard Lut Block with Auto-Scrubbing
Dual-core motion estimation processor
FPGA family composition and effects of specialized blocks
Using Reconfigurable Hardware Through Web Services in Distributed Applications
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs
Programming and Implementation of Reconfigurable Routers
Aggressive Loop Pipelining for Reconfigurable Architectures
Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications
Data Stream Statistics Over Sliding Windows: How to Summarize 150 Million Updates Per Second on a Single Node
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed
A Hardware Implementation of a Content Based Image Retrieval Algorithm
A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs
A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems
A low-complexity implementation of QC-LDPC encoder in reconfigurable logic
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures
A resource-efficient probabilistic fault simulator
FPGA-based K-means clustering using tree-based data structures
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy
HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model
Compact implementation of CCM and GCM modes of AES using DSP blocks
Execution Objects for Dynamically Reconfigurable FPGA Systems
Experiences of Using XBLOX for Implementing a Digital Filter Algorithm
A prototyping environment for fuzzy controllers
An implementation method of poisson image editing on FPGA
Dynamic reconfigurable mixed-signal architecture for safety critical applications
A fully pipelined FPGA architecture for stochastic simulation of chemical systems
A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
HardWire: A Risk-Free FPGA-to-ASIC Migration Path
A High-Performance Out-of-Order Soft Processor Without Register Renaming
Multiple constant multiplication with ternary adders
Minimising Reconfiguration Overheads in Embedded Applications (Abstract)
Remote Identification of Neural Network FPGA Accelerators by Power Fingerprints
Macrocell Architectures for Product Term Embedded Memory Arrays
Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance
Decimal multiplier on FPGA using embedded binary multipliers
VineTalk: Simplifying software access and sharing of FPGAs in datacenters
Flow Monitoring in High-Speed Networks with 2D Hash Tables
FPGA Architecture Design Methodology
Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA
Resource Elastic Database Acceleration
Thermal Gradient Aware Clock Skew Scheduling for FPGAs
A 6200 Model and Editor Based on Object Technology
Design of a hardware accelerator for fingerprint alignment
A 64-bit MIPS processor running freebsd on a portable FPGA tablet
An efficient reconfigurable architecture by characterizing most frequent logic functions
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks
Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs
Real-time processing of local contrast enhancement on FPGA
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms
Skin Color Detection for Real Time Mobile Applications
Bitstream compression through frame removal and partial reconfiguration
Complete activation scheme for FPGA-oriented IP cores design protection
Random decision tree body part recognition using FPGAs
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
Low Power Reconfigurable Devices
High throughput AES encryption/decryption with efficient reordering and merging techniques
Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools
A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment
RaPiD - Reconfigurable Pipelined Datapath
Caffe Barista: Brewing Caffe with FPGAs in the Training Loop
Improving Annealing Via Directed Moves
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic
FPGA based control for real time systems
Implementation of HW$im - A Real-Time Configurable Cache Simulator
Lightweight Side-Channel Protection using Dynamic Clock Randomization
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models
Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion
Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking
Multitasking Support for Dynamically Reconfig Urable Systems
Instruction Set Extension Using Microblaze Processor
Fast Prototyping with Co-operation of Simulation and Emulation
An efficient FPGA overlay for portable custom instruction set extensions
Impact of hard macro size on FPGA clock rate and place/route time
Compensating for variability in FPGAs by re-mapping and re-placement
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement
A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA
A non-volatile run-time FPGA using thermally assisted switching MRAMS
International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece
Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC
A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders
An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning
IMAGine: An In-Memory Accelerated GEMV Engine Overlay
An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems
An approach to system-wide fault tolerance for FPGAs
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2
Efficient Multiple Constant Multiplication Using DSP Blocks in FPGA
Thermal monitoring on FPGAs using ring-oscillators
An FPGA Based Memory Efficient Shared Buffer Implementation
Timing Aware Interconnect Prediction Models for FPGAs
Using an OpenCL framework to evaluate interconnect implementations on FPGAs
An EPLD Based Transient Recorder for Simulation of Video Signal Processing Devices in an VHDL Environment Close to System Level Conditions
Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication
MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge
The Intel Geneseo Project
A High Speed License Plate Recognition System on an FPGA
Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA
Power-Aware Computing Systems on FPGAs: A Survey
An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005
A Slow Motion Engine for the Analysis of FPGA-Based Prototypes
Fast Adaptive Image Processing in FPGAs Using Stack Filters
Modelling delay degradation due to NBTI in FPGA Look-up tables
AITIA: Embedded AI Techniques for Industrial Applications
Resource Management for the Heterogeneous Arrays of Hardware Accelerators
VPH - A Tool for Exploring Hybrid FPGAs
VPR: A new packing, placement and routing tool for FPGA research
CRISP: A Template for Reconfigurable Instruction Set Processors
The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer
Improving DSP Performance with a Small Amount of Field Programmable Logic
Charge recycling for power reduction in FPGA interconnect
Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic
Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs
Prototyping Framework for Reconfigurable Processors
Design of Safety Systems Using Field Programmable Gate Arrays
Creation of Hardware Objects in a Reconfigurable Computer
Runtime-Programmable Pipelines for Model Checkers on FPGAs
Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow
SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems
Energy efficient parameterized FFT architecture
Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device
A New Floorplanning Method for FPGA Architectural Research
A Structured Methodology for System-on-an-FPGA Design
Dynamic Inter-Block Scheduling for HLS
Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES
Can Graphics Processing Units be Used to Improve Video Processing Systems?
An Asynchronous Transfer Mode (ATM) Stream Demultiplexer and Switch
FPGA acceleration of Monte-Carlo based credit derivative pricing
A Compact Transactional Memory Multiprocessor System on FPGA
FPGA Implementation of 3-D Thermal Model Simulator
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation
JVX - A Rapid Prototyping System Based on Java and FPGAs
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation
A FPL Prototyping Package with a C++ Interface for the PC Bus
Fast Modular Division for Application in ECC on Reconfigurable Logic
Classification and Performance of Reconfigurable Architectures
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug
Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies
From opencl to high-performance hardware on FPGAS
Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters
FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding
Stream Computations Organized for Reconfigurable Execution (SCORE)
Annotation-based finite-state transducers on reconfigurable devices
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network
Exploration of Short Reads Genome Mapping in Hardware
FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction
Reduced-voltage OmpSs@FPGA: A Demonstration
Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
A Data Acquisition Reconfigurable Coprocessor for Virtual Instrumentation Applications
ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS
Routing algorithms for FPGAS with sparse intra-cluster routing crossbars
FGYM: Toolkit for Benchmarking FPGA based Reinforcement Learning Algorithms
Wotan: A tool for rapid evaluation of FPGA architecture routability without benchmarks
Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification
An Internet Based Development Framework for Reconfigurable Computing
Accelerated Inference of Positive Selection on Whole Genomes
Fast Adjustable NPN Classification using Generalized Symmetries
A Dynamically Reconfigurable Asynchronous FPGA Architecture
A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs
SPADES: A Productive Design Flow for Versal Programmable Logic
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
Integration of a multi-FPGA system in a common cluster environment
FPGA-accelerated Information Retrieval: High-efficiency document filtering
Shared reconfigurable architectures for CMPS
High-throughput implementation of a million-point sparse Fourier Transform
Efficient assembly for high order unstructured FEM meshes
The XPP Architecture and Its Co-simulation Within the Simulink Environment
Dynamic Heap Management in High-Level Synthesis for Many-Accelerator Architectures
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding
High-performance fpga-based floating-point adder with three inputs
Key Issues for User Acceptance of FPGA Design Tools
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm
Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA
Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism
Exploring reconfigurable architectures for explicit finite difference option pricing models
BunchBloomer: Cost-Effective Bloom Filter Accelerator for Genomics Applications
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs
A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits
Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs
FPGA based nonlinear Support Vector Machine training using an ensemble learning
BOUNCE, a new approach to measure sub-nanosecond time intervals
Computing Weight Distributions of Binary Linear Block Codes on a CCM
Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications
XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications
Fast Floorplanning for FPGAs
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs