yusuke1997/dblp-id-title huggingface dataset:
DWC: dynamic write consolidation for phase change memory systems
Supporting automatic recovery in offloaded distributed programming models through MPI-3 techniques
Auto-vectorization through code generation for stream processing applications
An Experimental Performance Evaluation of Touchstone Delta Concurrent File System
A comparison of two approaches for independent scaling up of processing and communication capacities in multicomputer networks
Roccom : an object-oriented, data-centric software integration framework for multiphysics simulations
Subdomain communication to increase scalability in large-scale scientific applications
SPARK: a benchmark package for sparse computations
Scientific applications vs. SPEC-FP: a comparison of program behavior
An efficient caching support for critical sections in large-scale shared-memory multiprocessors
Fast, accurate, and scalable memory modeling of GPGPUs using reuse profiles
A method for parallel program generation with an application to the Booster language
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law World
Experimental evaluation of application-level checkpointing for OpenMP programs
Incremental dependence analysis for interactive parallelization
MIC-RO: enabling efficient remote offload on heterogeneous many integrated core (MIC) clusters with InfiniBand
Automatic performance prediction to support parallelization of Fortran programs for massively parallel systems
Monotonic evolution: an alternative to induction variable substitution for dependence analysis
Value influence analysis for message passing applications
Finite Element Methods on Parallel and Vector Computers: Application in Fluid Dynamics
I/O threads to reduce checkpoint blocking for an electromagnetics solver on Blue Gene/P and Cray XK6
FTL design exploration in reconfigurable high-performance SSD for server applications
Another Combining Scheme to Reduce Hot Spot Contention in Large Scale Shared Memory Parallel Computers
A Performance Study of Cosmological Simulations on Message-Passing and Shared-Memory Multiprocessors
International Conference on Supercomputing, ICS'12, Venice, Italy, June 25-29, 2012
BonVoision: leveraging spatial data smoothness for recovery from memory soft errors
Tools for application-oriented performance tuning
Imogen: a parallel 3D fluid and MHD code for GPUs
Exascale science: the next frontier in high performance computing
Proceedings of the 5th international conference on Supercomputing, ICS 1991, Cologne, Germany, June 17-21, 1991
HPAT: high performance analytics with scripting ease-of-use
The architecture of the HP Superdome shared-memory multiprocessor
The shared-thread multiprocessor
Implementing Codes on a SIMD / SPMD Architecture: Application to a Subset of EISPACK
Enabling and Exploiting Flexible Task Assignment on GPU through SM-Centric Program Transformations
Warp-Consolidation: A Novel Execution Model for GPUs
CFDNet: a deep learning-based accelerator for fluid simulations
GreenGear: Leveraging and Managing Server Heterogeneity for Improving Energy Efficiency in Green Data Centers
Generalized Cannon's Algorithm for Parallel Matrix Multiplication
Realization of a Knowledge-Based Parallelization Tool in a Programming Environment
Optimized MPI collective algorithms for dragonfly topology
Author retrospective for anatomy of a message in the alewife multiprocessor
Facilitating the search for compositions of program transformations
Resource usage models for instruction scheduling: two new models and a classification
Using virtual lines to enhance locality exploitation
Load and store reuse using register file contents
Accurate memory data flow modeling in statistical simulation
Performance prediction of loop constructs on multiprocessor hierarchical-memory systems
Compiling object-oriented data intensive applications
Least squares solvers for distributed-memory machines with GPU accelerators
Author retrospective for search and replication in unstructured peer-to-peer networks
Automatic compiler techniques for thread coarsening for multithreaded architectures
Fault resilience of the algebraic multi-grid solver
Handling heavy-tailed input of transformer inference on GPUs
Isometry: A Path-Based Distributed Data Transfer System
The NOV-II super parallel computer for signal processing
Parallel Processing Architecture for the Hitachi S-3800 Shared-Memory Vector Multiprocessor
Fast memory snapshot for concurrent programmingwithout synchronization
Bloom filtering cache misses for accurate data speculation and prefetching
DStore: A Lightweight Scalable Learning Model Repository with Fine-Grain Tensor-Level Access
SHA-256 Collision Attack with Programmatic SAT
A Natural-Language Proof Assistant for Higher-Order Logic (Work in Progress)
Joint Proceedings of the 9th Workshop on Practical Aspects of Automated Reasoning (PAAR) and the 9th Satisfiability Checking and Symbolic Computation Workshop (SC-Square), 2024 co-located with the 12th International Joint Conference on Automated Reasoning (IJCAR 2024), Nancy, France, July 2, 2024
Empirical Properties of Term Orderings for Superposition
SC-TPTP: An Extension of the TPTP Derivation Format for Sequent-Based Calculus
Proceedings of the Workshop on Practical Aspects of Automated Reasoning Co-located with the 11th International Joint Conference on Automated Reasoning (FLoC/IJCAR 2022), Haifa, Israel, August, 11 - 12, 2022
Under-Approximation of a Single Algebraic Cell (Extended Abstract)
On SGGS and Horn Clauses
A Two-Watched Literal Scheme for First-Order Logic
Reuse of Introduced Symbols in Automatic Theorem Provers (short paper)
The Isabelle Community Benchmark
An Extensible Logic Embedding Tool for Lightweight Non-Classical Reasoning (short paper)
Cautious Specialization of Strategy Schedules (Extended Abstract)
QuAPI: Adding Assumptions to Non-Assuming SAT & QBF Solvers
Prefixed Tableaux and Decision Procedures for Many-Valued Modal Logics
Automated Reasoning in Non-classical Logics in the TPTP World
Exploring Partial Models with SCL
Optimal Strategy Schedules for Everyone
Lazy Paramodulation in Practice
Symbolic Computation for All the Fun
Exploring Representation of Horn clauses using GNNs
TPTP World Infrastructure for Non-classical Logics
The Vampire Approach to Induction (short paper)
Generating Compressed Combinatory Proof Structures: An Approach to Automated First-Order Theorem Proving
Towards Producing Shorter Congruence Closure Proofs in a State-of-the-art SMT Solver (Extended Abstract)
A Technological Approach to Teaching Inequalities, Propositional and Predicate Logic
International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010
From 3D circuit technologies and data structures to interconnect prediction
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning
The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings
Pre-layout estimation of individual wire lengths
Reconfigurable interconnect for next generation systems
Worst-case noise prediction using power network impedance profile
System level interconnect design for network-on-chip using interconnect IPs
Process-induced skew variation for scaled 2-D and 3-D ICs
Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing
Clock clustering and IO optimization for 3D integration
Application of 3-D ICs to FPGAs
Optimizing heterogeneous NoC design
Predictions of CMOS compatible on-chip optical interconnect
Impact of interconnect resistance increase on system performance of low power and high performance designs
Floorplan-based FPGA interconnect power estimation in DSP circuits
Extending quantum systems with optical interconnects (invited)
The X architecture: not your father's diagonal wiring
LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, SLIP 2024, Newark, NJ, USA, 31 October 2024
Prediction of high-performance on-chip global interconnection
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2021, Munich, Germany, November 4, 2021
Is overlay error more important than interconnect variations in double patterning?
Sidewinder: a scalable ILP-based router
Sequential delay budgeting with interconnect prediction
Accurate pseudo-constructive wirelength and congestion estimation
Synthetic traffic generation as a tool for dynamic interconnect evaluation
Revisiting inherent noise floors for interconnect prediction
Measurement techniques and interconnect estimation
Yield modeling and BEOL fundamentals
Optimized pin assignment for lower routing congestion after floorplanning phase
Compact modeling and system implications of microring modulators in nanophotonic interconnects
Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects
Predicting the worst-case voltage violation in a 3D power network
Generation of design guarantees for interconnect matching
Heterogeneity and interconnect
Analytical modeling of NoCs for fast simulation and design exploration (invited)
Graphene based nanomaterials for VLSI interconnect and energy-storage applications
Analysis of post-placement length estimation
Early and accurate analysis of SoCs: oxymoron or real?
Revisiting fidelity: a case of elmore-based Y-routing trees
Evolution as the blind engineer: wiring minimization in the brain
3D NoC emulation model on a single FPGA
A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA's
Towards the power networks of the future: needs, challenges and tools
Scaling trends of on-chip Power distribution noise
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects
Package level interconnect options
Network-on-Chips for Future 3D Stacked Dies (Invited)
Tutorial on congestion prediction
Interconnect solutions for TeraScale computing
Silicon Photonics Technology for Terabit-scale Optical I/O (Invited)
Prediction of interconnect fan-out distribution using Rent's rule
Switching activity analysis and pre-layout activity prediction for FPGAs
Wire layer geometry optimization using stochastic wire sampling
Using circuit structural analysis techniques for networks in systems biology
A comprehensive look at system level model
Clock tree synthesis for heterogeneous 3-D integrated circuits
Multi-product floorplan and uncore design framework for chip multiprocessors
The nuts and bolts of physical synthesis
Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures
Slew-down: analysis of slew relaxation for low-impact clock buffers
IBM CMOS compatible photonics and traveling wave electro-optic modulator design
Stochastic interconnect layout sensitivity model
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems
Integrated interlayer via planning and pin assignment for 3D ICs
Communication Considerations for Silicon Interconnect Fabric
Communication architecture enabling 100x accelerated simulation of biological neural networks
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, USA, June 2, 2013
Fence-aware detailed-routability driven placement
Interconnect prediction for programmable logic devices
Statistical analysis and optimization in the presence of gate and interconnect delay variations
Revisiting 3DIC Benefit with Multiple Tiers
Estimation needs for future networking systems interconnect
On partitioning vs. placement rent properties
Wiring requirement and three-dimensional integration of field-programmable gate arrays
A-priori wirelength and interconnect estimation based on circuit characteristics
SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm
Wireless on Networks-on-Chip
Timing optimization in logic with interconnect
Multilevel full-chip routing with testability and yield enhancement
Improving Performance of Network-on-Memory Architectures via (De-)/Compression-in-DRAM
The next resource war: computation vs. communication
Application of generalized scattering matrix for prediction of power supply noise
Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation
Interconnect implications of growth-based structural models for VLSI circuits
Constant impedance scaling paradigm for interconnect synthesis
SLIP: 10 years ago and 10 years from now
The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration
Networks on chips: keeping up with Rent's rule and Moore's law
A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce
A priori system-level interconnect prediction: Rent's rule and wire length distribution models
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs
Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, SLIP 2023, San Francisco, CA, USA, 2 November 2023
On rent's rule for rectangular regions
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited)
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings
Fast estimation of the partitioning rent characteristic using a recursive partitioning model
Why interconnect prediction doesn't work
Optimal bounded-skew steiner trees to minimize maximum k -active dynamic power
Noise-Aware Circuit Clustering based on Analytical Placement Evolution
Technology trends in power-grid-induced noise
Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
Improving broadcast efficiency in wireless sensor network time synchronization protocols
Simultaneous signal and power routing under K model
Design and optimization of communication fabrics: an industrial perspective
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)
Congestion prediction in early stages
Maximum multiplicity distributions (MMD)
A heuristic method for obstacle avoiding group Steiner tree construction
Pre-layout prediction of interconnect manufacturability
Self-consistent power/performance/reliability analysis for copper interconnects
Toward quantifying the IC design value of interconnect technology improvements
UI-route: An ultra-fast incremental maze routing algorithm
Getting more out of Donath's hierarchical model for interconnect prediction
Interconnect complexity-aware FPGA placement using Rent's rule
Statistical crosstalk aggressor alignment aware interconnect delay calculation
The scaling of interconnect buffer needs
Reducing energy and increasing performance with traffic optimization in many-core systems
Cost based tradeoff analysis of standard cell designs
The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)
Chip-scale physical interconnect models (Tutorial)
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
Optimizations in GPU: Smart compilers and core-level reconfiguration
Power supply design parameters prediction for high performance IC design flows
Energy-guided exploration of on-chip network design for exa-scale computing
SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020
Advances in PCB routing
A statistical model for estimating the effect of process variations on crosstalk noise
Proceedings of the 18th System Level Interconnect Prediction Workshop, SLIP 2016, Austin, TX, USA, June 4, 2016
Principle hessian direction based parameter reduction for interconnect networks with process variation
Interconnect scaling into the sub-10nm regime
Performance analysis and technology of 3-D ICs
High-dimensional metamodeling for prediction of clock tree synthesis outcomes
Circuit and physical design of the MDGRAPE-4 on-chip network links
An effective low power design methodology based on interconnect prediction
Methodology for electromigration signoff in the presence of adaptive voltage scaling
Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?
An overview of on-chip interconnect variation
2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011
Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack
An accurate and efficient probabilistic congestion estimation model in x architecture
Distributed power network co-design with on-chip power supplies and decoupling capacitors
The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings
Buffered Interconnects in 3D IC Layout Design
Machine-Learning Based Delay Prediction for FPGA Technology Mapping
Exploiting on-chip data behavior for delay minimization
Range-based dynamic routing of hierarchical on chip network traffic
Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects
A low power approach to system level pipelined interconnect design
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling
Simulation based study of wireless RF interconnects for practical CMOs implementation
Role of on-chip networks in building domain-specific architectures (DSAs) for sparse computations (invited)
Enabling Chiplet Integration Beyond 7nm (Invited)
Wirelength and congestion estimation for routability-driven placement
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods
21st ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2019, Las Vegas, NV, USA, June 1-2, 2019
Security Network On-Chip for Mitigating Side-Channel Attacks
High-performance ULSI: the real limiter to interconnect scaling
Theoretical limits for signal reflections due to inductance for on-chip interconnections
ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2014, San Francisco, CA, USA, June 1, 2014
A Novel PUF Architecture Against Non-Invasive Attacks
Rent's rule based switching requirements
Connectivity Effects on Energy and Area for Neuromorphic System with High Speed Asynchronous Pulse Mode Links
Analysis of high-performance clock networks with RLC and transmission line effects
Impact of interconnect length changes on effective materials properties (dielectric constant)
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network
FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping
Validation of wire length distribution models on commercial designs
Hybrid network on chip (HNoC): local buses with a global mesh architecture
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling
Wire length prediction in constraint driven placement
The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings
Topology optimization for application-specific networks-on-chip
The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings
Neural Network Model for Detour Net Prediction
Performance modeling for interconnects for conventional and emerging switches
Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper
Compact models and model standard for 2.5D and 3D integration
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era
Interconnect exploration for future wire dominated technologies
Rent's rule and parallel programs: characterizing network traffic behavior
A tale of two nets: studies of wirelength progression in physical design
SI for free: machine learning of interconnect coupling delay and transition effects
Power line communication for hybrid power/signal pin SOC design
The routability of multiprocessor network topologies in FPGAs
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Multi-terminal nets do change conventional wire length distribution models
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems
Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited)
Estimation and removal or routing congestion (discussion session)
Fast, accurate a priori routing delay estimation
Building a quantum computer (invited)
A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs
Future of interconnect fabric: a contrarian view
Interconnection lengths and delays estimation for communication links in FPGAs
Stability and scalability in global routing
Interconnect width selection for deep submicron designs using the table lookup method
Global interconnects in VLSI complexity single flux quantum systems
Power network-on-chip for scalable power delivery
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings
An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper
Pacman: driving nonuniform clock grid loads for low-skew robust clock network
Timing driven routing tree construction
Multi-core architectures and streaming applications
Wafer scale interconnect and pathfinding for machine learning hardware (invited)
A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for Wireless Network-on-Chip
Prediction of interconnect adjacency distribution: derivation, validation, and applications
Handling global traffic in future CMP NoCs
Performance and power analysis of through silicon via based 3D IC integration
Error-correction and crosstalk avoidance in DSM busses
The Open Domain-Specific Architecture: An Introduction (Invited)
Early electrical wire projections and implications
The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings
Worst-case performance prediction under supply voltage and temperature variation
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures
Impact of lithography retargeting process on low level interconnect in 20nm technology
Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited)
Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects
Fast dual-vdd buffering based on interconnect prediction and sampling
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs
A pre-placement net length estimation technique for mixed-size circuits