yusuke1997/dblp-id-title huggingface dataset:
A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches
Erasure-Coded Multi-Block Updates Based on Hybrid Writes and Common XORs First
Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUs
Comparative analysis of copper and CNT interconnects for H-tree clock distribution
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes
Specifying and Verifying Systems with Multiple Clocks
Multiple Input Bridging Fault Detection in CMOS Sequential Circuits
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks
GPE: A New Representation for VLSI Floorplan Problem
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC TM Microprocessor
Systolic L-U decomposition array with a new reciprocal cell
Adaptive Masking: a Dynamic Trade-off between Energy Consumption and Hardware Security
VLSI programming
Identifying optimal generic processors for biomedical implants
STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes
Forty Five Years of Computer Architecture-All That's Old is New Again
A yield model for the evaluation of topologically constrained chip architectures
Novel approximate synthesis flow for energy-efficient FIR filter
Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators
Logic extraction based on normalized netlengths
Data rate maximization by adaptive thresholding RF power management under renewable energy
Learn to Floorplan through Acquisition of Effective Local Search Heuristics
A Power Perspective of Value Speculation for Superscalar Microprocessors
Exploiting application-dependent ambient temperature for accurate architectural simulation
Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages
Breakthrough to Adaptive and Cost-Aware Hardware-Assisted Zero-Day Malware Detection: A Reinforcement Learning-Based Approach
Malicious key emission via hardware Trojan against encryption system
Implicit state minimization of non-deterministic FSMs
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators
Thermal-aware 3D design for side-channel information leakage
Mitigating Application Diversity for Allocating a Unified ACC-Rich Platform
BDD Variable Ordering by Scatter Search
A Low Power Approach to Floating Point Adder Design
Early stage FPGA interconnect leakage power estimation
Algorithm clustering for multi-algorithm processor design
Source-Level Transformations for Improved Formal Verification
Intelligent Prediction of Flash Lifetime via Online Domain Adaptation
Sub-threshold charge recovery circuits
FPGA Virtualization in Cloud-Based Infrastructures Over Virtio
Comparative Study of Strategies for Formal Verification of High-Level Processors
Dynamic prefetcher reconfiguration for diverse memory architectures
Use of Local Memory for Efficient Java Execution
Memory module-level testing and error behaviors for phase change memory
HiSEP-Q: A Highly Scalable and Efficient Quantum Control Processor for Superconducting Qubits
Design Alternatives for Parallel Saturating Multioperand Adders
Efficient code compression for coarse grained reconfigurable architectures
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip
BEOL stack-aware routability prediction from placement using data mining techniques
Low Power Spatial Localization of Mobile Sensors with Recurrent Neural Network
The performance of hypermesh NoCs in FPGAs
Domain Based Testing: Increasing Test Case Reuse
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure
Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs
Increasing reconfigurability with memristive interconnects
Design Methodologies and Architecture Solutions for High-Performance Interconnects
Composite Instruction Prefetching
A Scalable and Overflow-Tolerant Mechanism for Minimum Virtual Time Tracking
How to Design a Parallel Computer
Towards a Methodology for the Formal Hierarchical Verification
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors
Fast register consolidation and migration for heterogeneous multi-core processors
BiCMOS design overview and implementation methodology
Towards Real-Time Temporal Graph Learning
CMOS Gate Delay Models for General RLC Loading
Hardware Support for Bulk Data Movement in Server Platforms
Cryptographic vote-stealing attacks against a partially homomorphic e-voting architecture
Design and Performance of Compressed Interconnects for High Performance Servers
Concurrent Test Scheduling in Built-In Self-Test Environment
Efficient double asymmetric error correcting codes
Analysis and Mitigation of Data Sanitization Overhead in DAX File Systems
REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation
A thermal adaptive scheme for reliable write operation on RRAM based architectures
POMI: Polling-Based Memory Interface for Hybrid Memory System
Whitespace redistribution for thermal via insertion in 3D stacked ICs
DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures
Dynamic minimization of OKFDDs
PSQ: An Automatic Search Framework for Data-Free Quantization on PIM-based Architecture
Countering code injection attacks with TLB and I/O monitoring
Exploiting request characteristics and internal parallelism to improve SSD performance
Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths
The In-Car Computing Network: An Embedded Systems Challenge
System level modeling of real-time embedded software
Rethinking High-Level Synthesis Design Space Exploration from a Contrastive Perspective
Engineering Privacy at the Edge: A Practical Guide to Differential Privacy in System Architectures
Conciliating Speed and Efficiency on Cache Compressors
A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management
Retiming of Circuits with Single Phase Transparent Latches
Architectural and Cost Implications of the 5G Edge NFV Systems
Neighbour State Transition Method for VLSI Optimization Problems
Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
A Better ATPG Algorithm and Its Design Principles
IBM AS/400 Processor Technology
Offline and Online Algorithms for Cache Allocation with Monte Carlo Tree Search and a Learned Model
Safe clocking register assignment in datapath synthesis
Microarchitecture and Performance Analysis of Godson-2 SMT Processor
Why we need statistical static timing analysis
Fault-Aware Prediction-Guided Page Offlining for Uncorrectable Memory Error Prevention
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing
Reversi: Post-silicon validation system for modern microprocessors
Automotive Virtual Integration Platforms: Why's, What's, and How's
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware
Accelerator-rich CMPs: From concept to real hardware
An Area Minimizer for Floorplans with L-Shaped Regions
Computer systems employing reconfigurable board-to-board free-space optical interconnections: COSINE-1 and -2
Assertion-Based Microarchitecture Design for Improved Reliability
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages
Modified Booth Algorithm for High Radix Multiplication
Environment Synthesis for Compositional Model Checking
Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC
A Design For Test Perspective on I/O Management
Computer aided design system for VLSI interconnections
SPMario: Scale up MapReduce with I/O-Oriented Scheduling for the GPU
Design of Resonant Global Clock Distributions
An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V
Synthesis of Arrays and Records
Router and cell library co-development for improving redundant via insertion at pins
Security Trade-Offs in Microfluidic Routing Fabrics
Designing an Asynchronous Microcontroller Using Pipefitter
Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree
MASkIt: Soft error rate estimation for combinational circuits
Automatic Verification of Refinement
LM-Fix: Lightweight Bit-Flip Detection and Rapid Recovery Framework for Language Models
3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time
Comparative analysis of latches and flip-flops for high-performance systems
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators
A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented Networks-on-Chip
APES: an integrated system for behavioral design, simulation and evaluation of array processors
Dynamic converter reconfiguration for near-threshold non-volatile processors using in-door energy harvesting
Energy-aware co-processor selection for embedded processors on FPGAs
A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level
An Ultra-efficient Look-up Table based Programmable Processing in Memory Architecture for Data Encryption
Reducing dynamic power dissipation in pipelined forwarding engines
Design and Implementation of Low-Power Digit-Serial Multipliers
Energy-delay tradeoffs in 32-bit static shifter designs
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture
Power Droop Testing
Efficient Forward-Only Training for Brain-Inspired Hyperdimensional Computing
Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution
Output Prediction Logic: A High-Performance CMOS Design Technique
Low-power radix-8 divider
An Efficient Pattern Match Architecture for Production Systems Using Content-Addressable Memory
Random Testability of Redundant Circuits
Accurate and Efficient Static Timing Analysis with Crosstalk
Dynamically Disabling Way-prediction to Reduce Instruction Replay
An analog parallel distributed solution to the shortest path problem
A Technique for Generating Efficient Simulators
AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects
A new coding scheme for fault tolerant 4-phase delay-insensitive codes
Fine grain 3D integration for microarchitecture design through cube packing exploration
Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping
SelSMaP: A Selective Stride Masking Prefetching Scheme
TensTFM: Efficient Total Focusing Method for Ultrasonic Array Imaging on Dataflow Accelerators
Flexible NTT Accelerators for RLWE Lattice-Based Cryptography
Design Optimization for High-speed Per-address Two-level Branch Predictors
Evaluation of an Object-Caching Coprocessor Design for Object-Oriented Systems
Logic synthesis for a single large look-up table
Computation with simultaneously concurrent error detection using bi-directional operands
Filtering Superfluous Prefetches Using Density Vectors
Derivation of signal flow direction in MOS VLSI: an alternative
DOC: Fast and accurate congestion analysis for global routing
Improving the Heavy Re-encryption Overhead of Split Counter Mode Encryption for NVM
Design of application-specific 3D Networks-on-Chip architectures
Use of redundant binary representation for fault-tolerant arithmetic array processors
Protecting pipelined asynchronous communication channels against single event upsets
A 3D stacked high performance scalable architecture for 3D Fourier Transform
Hardware Self-Tuning and Circuit Performance Monitoring
Simulation points for SPEC CPU 2006
Variation tolerance and error resilience in a low power wireless receiver
Properties of the Input Pattern Fault Model
TriMedia CPU64 Architecture
VLSI Designs for High-Speed Huffman Decoder
Design aids and test results for laser-programmable logic arrays
Equivalence checking of partial designs using dependency quantified Boolean formulae
Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications
Design of a 64-processor by 128-memory crossbar switching network
Limits on voltage scaling for caches utilizing fault tolerant techniques
Routability-driven flip-flop merging process for clock power reduction
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI
Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example
A resource efficient content inspection system for next generation Smart NICs
Accuracy sensitive word-length selection for algorithm optimization
UniCoMo: A Unified Learning-Based Cost Model for Tensorized Program Tuning
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
Enhanced Chip/Package Design for the IBM ES/9000 TM
Fourier Transform based DS/FH Spread Spectrum Receiver
Macrocell-level compaction with automatic jog introduction
Reducing Multimedia Decode Power using Feedback Control
Mobile ecosystem driven application-specific low-power control microarchitecture
3D Integration: New opportunities in defense against cache-timing side-channel attacks
Enhancing GPU Performance via Neighboring Directory Table Based Inter-TLB Sharing
Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems
Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer
Exact Dichotomy-based Constrained Encodi
Optimal single probe traversal algorithm for testing of MCM substrat
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors
A testing platform for on-drone computation
Implicit hints: Embedding hint bits in programs without ISA changes
3D vs. 2D analysis of FinFET logic gates under process variations
Fine-Line Printed Circuit Board for High-Performance Computer Design
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers
DesignFab: A Methodology for ULSI Microprocessor Design
Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame drops
Simultaneous EUV flare- and CMP-aware placement
A superscalar RISC processor with pseudo vector processing feature
Dynamically compressible context architecture for low power coarse-grained reconfigurable array
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests
Forensics of Error Rates of Quantum Hardware
Design space exploration of multiple loops on FPGAs using high level synthesis
DR DRAM: Accelerating Memory-Read-Intensive Applications
Complex Gate Performance Improvement by Jog Insertion into Transistor Gates
A Novel Clock Distribution System for CMOS VLSI
Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM
Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology
Hot-FV: A Semi-Formal Test Generation Framework for RTL Functional Coverage Using Warm Starting States
A Field Programmable Accelerator for Compiled-Code Applications
The power play: Security-energy trade-offs in the IoT regime
Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations
Mapping properties of multi-level logic synthesis operations
Branch-Directed and Stride-Based Data Cache Prefetching
A PRET microarchitecture implementation with repeatable timing and competitive performance
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment
A Practical Algorithm for Retiming Level-Clocked Circuits
The DIMM tree architecture: A high bandwidth and scalable memory system
Parallel Event-Driven Waveform Relaxation
GCNTrain: A Unified and Efficient Accelerator for Graph Convolutional Neural Network Training
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis
ROA-brick topology for rotary resonant clocks
DOART: A low-power and low-latency Network-on-Chip
Just in Time Scheduling
RSFQ: What We Know and What We Don't
Execution-time profiling for multiple-process behavioral synthesis
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing
The Future of Programmable Logic and Its Impact on Digital System Design
Enhancing FSM Traversal by Temporary Re-Encoding
Modeling fo Interconnections Lines for Stimulation of VLSI Circuits
Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation
NapFS: A High-Performance NUMA-Aware PM File System
Design- Time Optimization of Reconfigurable PV Architectures for Irregular Surfaces
Early Termination with Activation Sign Prediction for Energy-Efficient CNN Inference Using Sum-of-Power-of-Two Quantization
Non-enumerative generation of statistical path delays for ATPG
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Constraint-Programmed Initial Sizing of Analog Operational Amplifiers
Economics in Design and Test
CREATE-LIFE: a design system for high performances VLSI circuits
Analysis of Blocking Dynamic Circuits
The POTATO chip architecture: a study in tradeoffs for signal processing chip design
Z2-ZNCC: ZigZag Scanning based Zero-means Normalized Cross Correlation for Fast and Accurate Stereo Matching on Embedded GPU
A Signature Analyzer for Analog and Mixed-signal Circuits
Power Management of Wireless Sensor Nodes with Coordinated Distributed Reinforcement Learning
Hybrid modeling attacks on current-based PUFs
Fault-tolerant architecture for high performance embedded system applications
Computational bit-width allocation for operations in vector calculus
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
ModelShield: A Generic and Portable Framework Extension for Defending Bit-Flip based Adversarial Weight Attacks
An Efficient Functional Coverage Test for HDL Descriptions at RTL
Transient fault behavior in a microprocessor - A case study
Formal Verification of Synthesized Analog Designs
Speed-area optimized FPGA implementation for Full Search Block Matching
A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs
Legion: Tailoring Grouped Neural Execution Considering Heterogeneity on Multiple Edge Devices
Hardware-based attacks to compromise the cryptographic security of an election system
Pre-routing Estimation of Shielding for RLC Signal Integrity
Toward Lifelong-Sustainable Electronic-Photonic AI Systems via Extreme Efficiency, Reconfigurability, and Robustness
New Classes of Unidirectional Error-Detecting Codes
On-Chip Oscilloscopes for Noninvasive Time-domain Measurement of Waveforms
Exact lower bound for the number of switches in series to implement a combinational logic cell
Performance Enhancements to the Active Memory System
OLSATM: Online Learning Based State-Aware Task Migration on S-NUCA Many-Cores
System-level design verification in the AT&T computer division: overview and strategy
Impact of BiCMOS technology on SRAM circuit design
System LSI Implementation Fabrics for the Future (special panel discussion)
A single-inductor-cascaded-stage topology for high conversion ratio boost regulator
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography
State Assignment Algorithms for Parallel Controller Synthesis
FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications
Consistent RDMA-Friendly Hashing on Remote Persistent Memory
Blink: Breaking Parallel Implementation of Crystals-Kyber with Side-Channel Attack
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis
Speeding up Variable Reordering of OBDDs
RISC architecture of the M88000
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths
Equivalence Checking for Flow-Based Computing
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array
SIMD Extension to VLIW Multicluster Processors for Embedded Applications
An Enhancement for a Scheduling Logic Pipelined over two Cycles
A Comprehensive Exploration of the Parallel Prefix Adder Tree Space
LCD Display Energy Reduction by User Monitoring
Trace-Level Speculative Multithreaded Architecture
Towards Low-Latency and Adaptive Ransomware Detection Using Contrastive Learning
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists
Arithmetic Error Analysis of a new Reciprocal Cell
Submicron BiCMOS technologies for supercomputer and high speed system implementation
Synthesis design strategies for energy-efficient microprocessors
Static Timing Analysis with False Paths
A New Statistical Optimization Algorithm for Gate Sizing
CNN Acceleration with Joint Optimization of Practical PIM and GPU on Embedded Devices
T-BUS: Taming Bipartite Unstructured Sparsity for Energy-Efficient DNN Acceleration
An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits
Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine
An Analytical Model for Trace Cache Instruction Fetch Performance
A serial-input serial-output bit-sliced convolver
Techniques for Fast CMOS-based Conditional Sum Adders
The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI
Positive Davio-based synthesis algorithm for reversible logic
Large memory embedded ASICs
Approximate Disjoint Bi-Decomposition and Its Application to Approximate Logic Synthesis
Multi-voltage domain clock mesh design
Efficient Design Error Correction of Digital Circuits
Constraint satisfaction in incremental placement with application to performance optimization under power constraints
Interference-Aware DNN Serving on Heterogeneous Processors in Edge Systems
Optimizing Data Placement for Hybrid SPM with SRAM and Racetrack Memory
Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis
Mamba: A scalable communication centric multi-threaded processor architecture
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics
VarVE: Bringing SIMD Performance to Variable-Width Values
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
$\mu\text{STT}$: Microarchitecture Design for Speculative Taint Tracking
Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications
Some Results on the Complexity of Boolean Functions for Table Look Up Architectures
ADAM: Adaptive Block Placement with Metadata Embedding for Hybrid Caches
Evaluating Techniques for Exploiting Instruction Slack
FPC: a floating-point processor controller chip for systolic signal processing
Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network
Implementation-Independent Model of an Instruction Set Architecture Using VHDL
PolyPE: An Efficient Multi-Precision Multi-Mode Floating-Point Processing Element for HPC and AI
Incas: a cycle accurate model of UltraSPARC
A Distributed Scheme for Accelerating Semantic Video Segmentation on An Embedded Cluster
SageSC: Accelerating GraphSAGE Minibatch Inference on Memory-Intensive Graphs