yusuke1997/dblp-id-title huggingface dataset:
ToF Estimation Based on Compressed Real-Time Histogram Builder for SPAD Image Sensors
Design of concurrent multi-band matching networks
Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization
Switched-capacitor circuits using a single-phase scheme
Computing Criticality of Lines in Power Systems
The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator
Integration of Double Barrier Memristor Die with Neuron ASIC for Neuromorphic Hardware Learning
Study of wind profile prediction with a combination of signal processing and computational fluid dynamics
A Single-Stage Four-Phase Dual-Output Regulating Rectifier With Ultrafast Transient Response Using Double-Frequency Current-Wave Modulation
A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application
Regularity in difference in transmission characteristics for Gaussian superlattices and periodic superlattices
Losses analysis and low standby losses quasi-resonant flyback converter design
High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications
A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication
A delay compensation technique for n-phase clock generation with 2(N-1) delay units
Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length
Generalized Cellular Neural Networks Represented in he NL q Framework
Bandpass spread spectrum clocking for reduced clock spurs in autozeroed amplifiers
Implications of noise insertion mechanisms of different countermeasures against side-channel attacks
On complexity of bifurcations for some classes of systems with simple dynamics
A novel CAVLC architecture for H.264 Video encoding at high bit-rate
Effects of switching power converter nonidealities in envelope elimination and restoration technique
Study of a least-squares type method for noisy FIR filtering
A comparison of fractal dimension algorithms using synthetic and experimental data
An adaptive CMOS imager with time-based compressive active-pixel response
A ray queueing and sorting design for real time ray casting
An area-efficient analog VLSI architecture for state-parallel Viterbi decoding
An adaptive Butler-Cantoni based time delay estimation (ABCTDE) method IIR whitening filtering approach
RARN: A Real-Time Skeleton-based Action Recognition Network for Auxiliary Rehabilitation Therapy
Active noise cancellation headset
A new approach to analyze interconnect delays in RC wire models
Multi-step analog-to-digital converters with trapping window
Selective Diversity Reception in Underwater Optical Camera Communication
Outliers in bound-based state estimation and identification
A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits
Interpolation and Extrapolation by Prolate Spheroidal Wave Functions Using Nonuniform Division and Generalized Chirp Modulation
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology
Algorithmic Delta-Sigma-modulated FIR filter
Selective redundancy-based design techniques for the minimization of local delay variations
Design of a high linearity mixer for direct-conversion base-station receiver
Fast sub-pixel motion estimation with simplified modeling in HEVC
Charge Pump for optimal dynamic range filters
A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue
An orientation selective 2D AER transceiver
Analysis of a high-voltage-gain hybrid switched-capacitor buck converter
Efficient dictionary based video coding with reduced side information
Sizing of MOS transistors for amplifier design
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation
Strong practical stability for a class of 2D linear systems
A 22-mW 435 MHz silicon on insulator CMOS high-gain LNA for subsampling receivers
Two-step ADC with Self-Successive Doubling Algorithm for High-Speed CIS
A mismatch-robust period-based VCO frequency comparison technique for ULP receivers
Historical Patterns of Emerging Residue Number System Technologies During the Evolution of Computer Engineering and Digital Signal Processing
1.4 V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency
A time-interleaved ADC architecture exploiting correlations between samples
A CMOS charge pump for sub-2.0 V operation
Adaptive illumination in wireless capsule endoscopy system
LLM Training Workload IO Characteristics
Event-driven random backpropagation: Enabling neuromorphic deep learning machines
Back-illuminated ultraviolet image sensor in silicon-on-sapphire
On the testability of SC filters based on allpass sections
RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications
Compressed-domain fall incident detection for intelligent home surveillance
Design a Co-processor for Output Probability Calculation in Speech Recognition
Development of an integrated CMOS-microfluidic instrumentation array for high throughput membrane protein studies
A low dark current wide dynamic range CMOS pixel
A rational function based predistorter for high power amplifier
A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC
Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference
A new circuit structure for near field wireless power transmission
A digital filter code generator with automatic scaling of internal variables
High performance absolute value calculator based on stochastic computing
General-pupose technology for a general-purpose nervous system
A +12dBm Output Power and -97.5dBm Sensitivity 2.4G/5.8GHz BLE/BT Compliant Transceiver with RX/TX Co-Matching using Bondwires
An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS
A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL
Minimizing Bit-Error-Rate by Optimizing Power Amplifier's Output Power in Wireless Links
Adaptive channel scheduling for Scalable Video broadcasting over MIMO wireless networks
A symmetric quadrature-less image rejection architecture for RF receivers
Design paradigm for standard agnostic channelization in flexible mobile radios
Self tuned fully integrated high image rejection low IF receivers: architecture and performance
A 6 V CMOS switching mode amplifier for continuous-wave signals from DC to 3 GHz
An ultra-low-power 902-928MHz RF receiver front-end in CMOS 90nm process
A Trajectory Measurement System and Algorithms for Unicondylar Knee Replacement Surgery
A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump
A High-Resolution Delta-Sigma D/A Converter Architecture with High Tolerance to DAC Mismatch
Enhanced visualization of power system stability limits imposed by singularity induced bifurcations
Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate
A New Approach to Design A-Stabel Linear Multistep Integration Algorithms
26TSPC: A Low Hold Time, Low Power Flip-Flop With Clock Path Optimization
VLSI architecture of extended in-place path metric update for Viterbi decoders
Bit-Error Rate Measurements for A High Frequency Interpolated Frequency-Hopping Spread-Spectrum System
Pulse mode neuron with leakage integrator and additive random noise
Explicit Circuit Models of Multi-Dimensional Piecewise-Linear Networks
Learning vector quantization: cluster size and cluster number
Template design for binary-programmable cellular nonlinear networks
System Level Modeling and Optimization of Hybrid Vibration Energy Harvesters
Adder Circuits with Transistors using Independently Controlled Gates
A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs
Sliding-mode control analog integrated circuit for switching DC-DC power converters
Op-amp swing reduction in sigma-delta modulators
Broadband capacitive sensor CMOS interface circuit for dielectric spectroscopy
Demonstration of Ripple-based Index for Predicting Fast-scale Instability in Switching Power Converters
A 10-b statistical ADC employing pipelining and sub-ranging in 32nm CMOS
Graphene Devices, Interconnect and Circuits - Challenges and Opportunities
Design equations for sub-optimum operation of class-E amplifier with nonlinear shunt capacitance
Hybrid Additive Random Sampling and its Realization
A 2.793µW Near-Threshold Neuronal Population Dynamics Simulator for Reliable Simultaneous Localization and Mapping
Continuation techniques for reachability analysis of uncertain power systems
PSRR improvement technique for amplifiers with Miller capacitor
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system
Adaptive optimization of notch bandwidth of an IIR filter used to suppress narrow-band interference
Pipelined Adaptive IIR Filter Architecture
Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures
Live Demonstration: Unobtrusive and Continuous Monitoring of Respiration Employing a Dual CW Radar Assembly
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation
Properties of deletion methods in competitive learning
High capacity reversible data hiding using the histogram modification of block image
Analog circuit synthesis: a search for the Holy Grail?
A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC
Low-Power Fixed-Point Compressed Sensing Decoder with Support Oracle
Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes
Electroporation Improvement of Leukemic Cells Using Dielectrophoresis Technique
A High-Throughput Lossless Image Compression Engine Optimized for Compression Ratio
Optimal PN Sequences Design for Quasi-Synchronous CDMA Communication Systems
An efficient split-radix FHT algorithm
Power consumption of a Hamming distance search CAM using neuron MOS transistors
Communication in Brain Circuits and Systems: a Primer
Compressive sampling of EMG bio-signals
X ray and blue print: tools for MOSFET analog circuit design addressing short-channel effects
A novel method to represent the speech signals by using language and speaker independent predefined functions sets
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM
NoC Router Lifetime Improvement using Per-Port Router Utilization
A novel 1.5V DC offset cancellation CMOS down conversion mixer
Design and Implementation of Cosine-Modulated Dimensional Perfect Reconstruction FIR Filter Banks
A 0.9 V rail-to-rail constant g m amplifier for implantable biomedical applications
Three Coils, High-Resolution Receiver Positioning System for Wireless Power Transfer
A new method for robust beamforming using iterative second-order cone programming
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing
A BICMOS Limiting Amplifier for SONET OC-3
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing
ASAUN-CS: Adaptive Stage Activated Unfolding Network for Compressive Sensing
A Macromodel Compaction Scheme for the Fast Stimulation of Large Linear Mesh Circuits
Accuracy analysis for correlation-based image registration algorithms
AVAC: A Machine Learning Based Adaptive RRAM Variability-Aware Controller for Edge Devices
A 0.02 nJ self-calibrated 65nm CMOS delay line temperature sensor
Nanoelectromechanical analog-to-digital converter for low power and harsh environments
Spike-Predictable Neuron Circuits with Adaptive Threshold for Low-Power SNN Systems
Attention-Based Auto-Encoder Framework for Abnormal Driving Detection
Introducing negative feedback with an integrator as the central element
Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing
Floorplanning with clock tree estimation
A fluorescence based endoscopic microcancer detection capsule
FPGA implementation of the CAR Model of the cochlea
A Bio-Inspired Recurrent Neural Network with Self-Adaptive Neurons and PCM Synapses for Solving Reinforcement Learning Tasks
A dual band FMCW radar receiver with integrated active balun and baseband AGC loop
Adaptive Weighting Feature Aggregation using Particle Swarm Optimization for Image Retrieval
EEGCAPS: Brain Activity Recognition Using Modified Common Spatial Patterns and Capsule Network
Background adaptive linearization of high-speed digital-to-analog Converters
Sub-volt supply analog circuits based on quasi-floating gate transistors
A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS
A Self-Organized Network with a Supervised Training
Complex-coefficient variable filter design using successive vector-array-decomposition
Self-organisation in arrays of nonlinear systems induced by chaotic perturbation: An experimental approach
ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator
Conflict-free parallel memory access scheme for FFT processors
Morphological learning in multicompartment neuron model with binary synapses
Use of source degeneration for non-intrusive BIST of RF front-end circuits
FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels
A Low Power Sinc3 Filter for Sigma-Delta Modulators
New relaxation-based circuit simulator based on fast automatic differentiation
A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking
A merged first and second stage for low power pipelined ADC
Modulo deflation in (2 n +1, 2 n , 2 n -1) converters
Adversarial Defense using Memristors and Input Preprocessing *
Design of a frequency signal conditioning unit applied to rotating systems in high temperature aero engine control
Classification of Alzheimer's Disease from MRI Data Using a Lightweight Deep Convolutional Model
An Integrated Piezoelectric Energy Harvesting Interface Circuit with Adaptive S3BF Control
Tuning a Resonant DC/DC Converter on the Second Harmonic for Improving Performance: A Case Study
Design and optimization of a low noise 2.4 GHz CMOS VCO with integrated LC tank and MOSCAP tuning
A High-Temperature Resistant Railway Vibration Monitoring System Based on Piezoelectric Ceramics and Silicon Carbide Devices
Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based Hardware Accelerator
Hardware Implementation of Habituation
Fast single frame super-resolution using perceptual visibility optimization
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices
An edge-preserving fuzzy filter based on differences between pixels
Electromechanical cardiac monitoring SoC for atrial fibrillation detection
Low power readout control circuit for high resolution CMOS image sensor
Software-Defined Cognitive Radar Implementation for Spectrum Management using MATLAB
A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS
Reducing computation complexity for disparity matching
Homoclinic Bifurcation of a Voltage Source Converter with Second-Order Grid-Forming Control
Impulsive consensus for second-order multi-agent systems with a reference velocity and input delays
Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors
Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
cFPGA: CNT emerging memory-based FPGA
PDR-KAN: Pipeline-Driven Reconfigurable Accelerator for Kolmogorov-Arnold Networks with Cross-Mode Sparsity Support
Development of an evaluation model for the design of fault-tolerant solid state mass memory
Design of an Extremely Low Cutoff Frequency Highpass Frontend for CMOS ISFET via Direct Tunnelling Principle
A Mismatch-Free CMOS Dynamic Voltage Comparator
A Sub-pico Joules Per Bit Robust Physical Unclonable Function Based on Subthreshold Voltage References
A modified TESPAR algorithm for wildlife sound classification
High-speed DACs with random multiple data-weighted averaging algorithm
A 110 × 64 150 mW 28 frames/s integrated visible/near-infrared CMOS image sensor with dual exposure times for image guided surgery
DCT-based edge detector for snapshot images
Hardware and software infrastructure for a family of floating-gate based FPAAs
A Monolithic CMOS Realization of the Double-Quadrature Image-Reject Weaver Receiver
Modelling of multidimensional (MD) heat diffusion via the Kirchhoff paradigm
Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT ΣΔ Modulator
Parameter estimation of Hodgkin-Huxley neuronal model using dual extended Kalman filter
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition
6-bit low power low area frequency modulation based flash ADC
Design and Characterization of a Silver-enhanced Gold Nanoparticle-based Biochip
Prediction of brain electrical activity in epilepsy using a higher-dimensional prediction algorithm for discrete time cellular neural networks (DTCNN)
Saturated-pixel enhancement for color images
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar
Fast intra prediction algorithm and design for high efficiency video coding
Neural Network-based Error Concealment for B-Frames in VVC
Low-complexity adaptive algorithms for pre-distortion of power amplifiers
A vector based fast block motion estimation algorithm for implementation on SIMD architectures
Log-domain Circuit Models of Chemical Reactions
A novel resynchronization marker positioning approach for robust video transmission
On-chip calibration technique for delay line based BIST jitter measurement
Tri-Directional Decoder for Edge Discontinuity Classification
A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver
An unsupervised dictionary learning algorithm for neural recordings
A new regularized recursive dynamic factor analysis with variable forgetting factor for wireless sensor networks with missing data
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS
High-speed hardware architectures for authenticated encryption mode GCM
A Raspberry Pi Based Video Pipeline for 2-D Wave Digital Filters on Low-Cost FPGA Hardware
A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology
A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS
Efficient list decoder architecture for polar codes
Bifurcation in parallel-connected boost DC/DC converters
A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches
Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input
A study on resistive-type truncated CVNS Distributed Neural Networks
Simulating Spiking Neural Networks with 8-Bit Floating-Point Numbers
Disparity map acquisition with occlusion handling using warping constraint
Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit
Analysis and design of high performance frequency-interleaved ADC
Order reduction for Roesser state-space model based on elementary operations
A Survey of Ensemble Methods for Mitigating Memristive Neural Network Non-idealities
High-speed serial communication with error correction using 0.25 um CMOS technology
Physical Computing for Hopfield Networks on a Reconfigurable Analog IC
A 8-Gb/s 0.256-pJ/b transceiver for 5-mm on-chip interconnects in 130-nm CMOS
Speech processing using higher order statistics
Jointly minimum SER transmitter and receiver FIR MIMO filters for QAM signalling
Noncoherent Correlation-Based Communication Systems Choosing Different Chaotic Maps
Low complexity image correction using color and focus matching for stereo video coding
A fully integrated switched-capacitor based PMU with adaptive energy harvesting technique for ultra-low power sensing applications
An overview of decimator structures for efficient sigma-delta converters: Trends, design issues and practical solutions
A SIFT-based Image Fingerprinting Approach Robust to Geometric Transformations
A measurement system for electric car charging stations utilising a FPGA board for flexibility in configuration
Hysteric controller for CMOS on-chip switching power converters
A novel electronic architecture used to support biomedical photo-acoustic imaging
A CMOS linear voltage/current dual-mode imager
A new learning algorithm for pattern classification using cellular neural networks
Analysis of border-collision bifurcation in a simple circuit
Live demonstration: A real-time moving object localization and extraction system
Energy Harvesting and Limits of Low Power Mixed-signal Circuit Design
An all CMOS 743 MHz variable gain amplifier for UWB systems
Ultra-compact SRAM design using TFETs for low power low voltage applications
A design and implementation of programmable multiplierless FIR filters with powers-of-two coefficients
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications
Ultra-Lightweight CNN Based Fast Intra Prediction for VVC Screen Content Coding
An Always Dual-Path Hybrid DC-DC Converter with Multiphase Interleaving Switched-Capacitor Cell Obtaining 45% Output Ripple Reduction
Efficient adaptive Volterra filters for active nonlinear noise control with a linear secondary-path
An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages
Hardware efficient architectures for coupled-form IIR filters
Microstrip stepped impedance lowpass filters based on the maxwell-wagner polarization mechanism
Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs
Transistor sizing strategy for simultaneous energy-delay optimization in CMOS buffers
Compressive modulation in digital communication
Throughput evaluation of DSP applications based on hierarchical dataflow models
A Novel Ladder Control Assisted Startup for Primary Side Regulated Flyback Converter
Energy Efficient Content-based Image Retrieval for Mobile Systems
SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing
Steganalysis of data hiding in binary text images
A comparison of output envelope waveforms of the delta-sigma modulated class D series resonant inverter
Adjusting the neurons models in neuromimetic ICs using the voltage-clamp technique
An efficient RF power transfer and bidirectional data transmission to implantable electronic devices
An ultra low-power CMOS action potential detector
A Battery-Less 0.37 V 126 nW 0.29 mm 2 65-nm CMOS Biofuel-Cell-Modulated Biosensing System Featuring an FSK-PIM-Combined 2.4 GHz Transmitter for Continuous Glucose Monitoring Contact Lenses
High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller
A Mott Insulator-Based Oscillator Circuit for Reservoir Computing
PVT-aware digital techniques for a power line energy-harvesting sensor node
A 30 GHz Power Detector based Reflectometer in 130nm SiGe BiCMOS for Dielectric Spectroscopy
Interactive lecturing techniques
Low power binary addition using carry increment adders
Small Amplitude, Phase Locked Response in Oscillatory Networks with Delays
Multiuser wavelet based MC-CDMA receiver with linearly constrained constant modulus IQRD-RLS algorithm
MMIC active floating gyrator design and accurate modelling
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars
Feedforward linearisation applied to a direct carrier modulation transmitter
Analysis of disturbance rejection by PI λ controller using solid state fractional capacitor
Vol-Net and V3C-Net: Towards End to End Traffic Volume Estimation
Two-Dimensional Spectral Representation with Applications
Efficient CNN-Based Side-Channel Attacks on Dilithium without Device Access
A Continuous Time Analog-to-Digital Converter With 90µW and 1.8µV/LSB Based on Differential Ring Oscillator Structures
Memory efficient EMS decoding for non-binary LDPC codes