yusuke1997/dblp-id-title huggingface dataset:
A low overhead hardware technique for software integrity and confidentiality
Pseudo-Random Pattern Testing of Bridging Faults
SAP: design of a systolic array processor for computation in vision
Preference-Driven Hierarchical Hardware/Software Partitioning
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping
BIST Generators for Sequential Faults
VLSI Design Automation for the Application System/400
DACCT - Dynamic ACCess Testing of IBM Large Systems
Synthesizing Converters Between Finite State Protocols
SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance
Current sensing for built-in testing of CMOS circuits
IP characterization methodology for fast and accurate power consumption estimation at transactional level model
Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms
38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020
Fixed-function hardware sorting accelerators for near data MapReduce execution
Detecting and Predicting Performance Degradation Caused by Impaired Cache Isolation
Concurrent testing of VLSI circuits using conservative logic
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability
Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology
Track assignment considering crosstalk-induced performance degradation
Guiding Architectural SRAM Models
A novel cryptographic key exchange scheme using resistors
Variation-aware thermal characterization and management of multi-core architectures
AS/400 TM 64-bit PowerPC TM -Compatible Processor Implementaiton
An asynchronous Network-on-Chip router with low standby power
Block-LSM: An Ether-aware Block-ordered LSM-tree based Key-Value Storage Engine
A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface
Hybrid scratchpad and cache memory management for energy-efficient parallel HEVC encoding
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc
FLASH-RL: Federated Learning Addressing System and Static Heterogeneity using Reinforcement Learning
Continuous Retiming: Algorithms and Applications
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors
Generating efficient and high-quality pseudo-random behavior on Automata Processors
A PLL design based on a standing wave resonant oscillator
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores
Targeted Fault Injection Attack on Semantic Segmentation Models
System level power estimation methodology with H.264 decoder prediction IP case study
RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive Memory
34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016
Multiple-Page Translation for TLB
The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks
A formal verification technique for embedded software
A design of a memory management unit for object-based systems
HIT: a standard constructional system for testability and maintainability
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning
Design techniques of eNVM-enabled neuromorphic computing systems
QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog
Tutorial: Evolutionary Design Methods in Electronic Design Automation
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy
A one-pass test-selection method for maximizing test coverage
SoftBeam: Precise tracking of transient faults and vulnerability analysis at processor design time
TriState-SET: Proactive SET for improved performance of MLC phase change memories
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers
Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC
On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering
The resource conflict methodology for early-stage design space exploration of superscalar RISC processors
Design and Synthesis of Monotonic Circuits
A novel simulation based approach for trace signal selection in silicon debug
Inter-socket victim cacheing for platform power reduction
SuperMap: High-Performance and Flexible Memory-Mapped IO for Fast Storage Device
Imperfection-immune Carbon Nanotube digital VLSI
Potential applications of high-T c superconducting transmission lines in integrated systems
Stealthy Rootkits in Smart Grid Controllers
RAID45: Hybrid Parity-Based RAID for Reducing Parity Write Wear on High-Density SSDs
Dual-Axis ECC: Vertical and Horizontal Error Correction for Storage and Transfer Errors
Low-Power Driven Technology Mapping under Timing Constraints
A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip
Modeling timing assumptions with trace theory
Tunable Memory Protection for Secure Neural Processing Units
High Level Functional Verification Closure
Fault-tolerant VLSI processor array for the SVD
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis
Asynchronous Transpose-Matrix Architectures
A Systolic Array for Approximate String Matching
Motion estimation VLSI architecture for image coding
BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile Applications
System-on-a-Chip Bus Architecture for Embedded Applications
CloudSocket: Smart grid platform for datacenters
LMS-based low-complexity game workload prediction for DVFS
Energy optimal on-line Self-Test of microprocessors in WSN nodes
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU
In-System FPGA Prototyping of an Itanium Microarchitecture
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits
High Level Design: A Design Vision for the 90's
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
Architecture and design of a 40 gigabit per second ATM switch
System Level ASIC Design for Hewleet-Packard's Low Cost PA-RISC Workstations
A high performance bus and cache controller for PowerPC multiprocessing systems
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor
The Selective Extra-Stage Butterfly
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
Library-Adaptively Integrated Data Path Synthesis for DSP Systems
Circular buffered switch design with wormhole routing and virtual channels
Multiple Paths Sensitization of Digital Oscillation Built-In Self Test
AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs
DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture
COBRA: An 1.2 Million Transistor Expandable Column FFT Chip
A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication
Evolution in the application of ASICs in the second-generation Titan
The Effects of Compiler Options on Application Performance
A Signal Integrity Test Bed for PCB Buses
Eca-Router : On Achieving Endpoint Congestion Aware Switch Allocation in the On-Chip Network
Fault-Tolerant Model of Neural Computing
36th IEEE International Conference on Computer Design, ICCD 2018, Orlando, FL, USA, October 7-10, 2018
Compiling and Optimizing Real-world Programs for STRAIGHT ISA
Logic synthesis for programmable logic devices
A floating point radix 2 shared division/square root chip
A Note About the Correction Cycle of High Radix Booth's Multiplication
Insertion policy selection using Decision Tree Analysis
A Joint Optimization of Buffer and Splitter Insertion for Phase-Skipping Adiabatic Quantum - Flux - Parametron Circuits
A novel, highly SEU tolerant digital circuit design approach
Adaptive routing in Clos networks
Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core
Voting system design pitfalls: Vulnerability analysis and exploitation of a model platform
Rule-based testability rule check program
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders
A simple pipelined logarithmic multiplier
Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions
Adaptive SRAM memory for low power and high yield
Functional Fault Models and Gate Level Coverage for Sequential Architectures
An automated design flow for approximate circuits based on reduced precision redundancy
Embedded way prediction for last-level caches
Simulating Uniform Lossy Lines by the Time-Domain Modal Analysis
On the Detectability of Parametric Faults in Analog Circuits
A self-reconfiguration scheme for fault-tolerant VLSI processor arrays
High Performance Parallel Fault Simulation
Future Challenges of Deep Sub-Micron Processer Design
Sorting on an array of processors
Elastic EDA: Auto-Scaling Cloud Resources for EDA Tasks via Learning-based Approaches
Multiway Partitioner for High Performance FPGA Based Board Architecture
A new class of symmetric error correcting / unidirectional error detecting codes
BiCMOS fault models: is stuck-at adequate?
Design and evaluation of a delay-based FPGA Physically Unclonable Function
CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs
DASICS: Efficient In-Process Protection with Hardware-Assisted Dynamic Compartmentalization
Stochastic functions using sequential logic
LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactions
Reliability issues of MOS and bipolar ICs
Computer-aided design for microfluidic chips based on multilayer soft lithography
A VLSI Priority Packet Queue with Overwrite and Inheritance
Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs
Set-associative dynamic random access memory
Network-on-Chip: The Intelligence is in The Wire
Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems
Power-agility metrics: Measuring dynamic characteristics of energy proportionality
Embedded Systems Design with Frontend Compilers
Beyond Compression Ratio: A Throughput Analysis of Memory Compression Techniques for GPUs
Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs
Physically Realizable Gate Models
Applications of Deep Neural Networks for Ultra Low Power IoT
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length
Predictive Strategies for Low-Power RTOS Scheduling
Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation
Toward reliable SRAM-based device identification
An Improved method for Fast Noise Estimation based on Net Segmentation
Reliability Support for On-Chip Memories Using Networks-on-Chip
Heuristic minimization of Boolean relations using testing techniques
High-Speed Link Design, Then and Now
Highly reliable A/D converter using analog voting
Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion
Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy
WAS-Deletion: Workload-Aware Secure Deletion Scheme for Solid-State Drives
Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation
Increasing Processor Performance Through Early Register Release
Isle-Tree: A B+-Tree with Intra-Cache Line Sorted Leaves for Non-volatile Memory
An integrated free space optical bus
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction
"Stubborn" strategy to mitigate remaining cache misses
Security implications of cyberphysical digital microfluidic biochips
Virtual Page Tag Reduction for Low-power TLBs
Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs
DCP: an algorithm for datapath/control partitioning of synthesizable RTL models
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study
The Birth of the Baby
FPGA and Rapid Prototyping Technology Use in a Special Purpose Computer for Molecular Genetics
Intra-task scheduling for storage-less and converter-less solar-powered nonvolatile sensor nodes
Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache
Resonant Compute-In-Memory (rCIM) 10T SRAM Macro for Boolean Logic
An enhanced high performance combinational fault simulator using two-way parallelism
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures
A functional approach to formal hardware verification: the MTI experience
Subword Sorting with Versatile Permutation Instructions
Minimum Energy Near-threshold Network of PLA based Design
Speculative Code Value Specialization Using the Trace Cache Fill Unit
CHARM: Collaborative Host and Accelerator Resource Management for GPU Datacenters
DR-SNUCA: An energy-scalable dynamically partitioned cache
ECO-Map: Technology remapping for post-mask ECO using simulated annealing
RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V
MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization
EaD: a Collision-free and High Performance Deduplication Scheme for Flash Storage Systems
Approximate time-domain models of three-dimensional interconnects
A TCAM generator for packet classification
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
EFM: Elastic Flash Management to Enhance Performance of Hybrid Flash Memory
Timing Verification and Optimization for the PowerPC TM Processor Family
Implicit Test Sequences Compaction for Decreasing Test Application Cos
Evaluating the performance of active cache management schemes
A Study on self-timed asynchronous subthreshold logic
An Efficient Unique State Coding Algorithm for Signal Transition Graphs
High-Level Power Modeling of CPLDs and FPGAs
An Efficient Symbolic Design Verification System
IBM ES/9000 TM System Architecture and Hardware
Optimizing CMOS Implementations of the C-element
FlexZNS: Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones
Timing verification of the 21264: A 600 MHz full-custom microprocessor
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis
Process Variation Mitigation on Convolutional Neural Network Accelerator Architecture
A novel approach to parameterized verification of cache coherence protocols
Adaptative backtrace and dynamic partitioning enhance ATPG
PIMFY: Eliminating Remote Page Walks in MCM GPUs
Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency
Global Bus Design of a Bus-Based COMA Multiprocessor DICE
Field-Programmable Integrted Circuits - Overview and Future Trends
QuPAA: Exploiting Parallel and Adaptive Architecture to Scale up Quantum Computing
Verifiable and executable theories of design for synthesizing correct hardware
Throughput-Oriented LLM Inference via KV-Activation Hybrid Caching with A Single GPU
Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architectures
DNNCloak: Secure DNN Models Against Memory Side-channel Based Reverse Engineering Attacks
Reliable cache design with detection of gate oxide breakdown using BIST
F-RISC/I: Fast Reduced Instruction Set Computer with GaAs (H)MESFET Implementation
A memristor-based memory cell using ambipolar operation
BIST-Based Fault Diagnosis in the Presence of Embedded Memories
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology
Optimal Inductance for On-chip RLC Interconnections
Improving the Efficiency of Power Management via Dynamic Interrupt Management
Pragmatic design of gated-diode FinFET DRAMs
MamCIMFlow: An Integrated Co-Design of RRAM-Based CIM and Selective State-Space Streaming for Efficient Mamba Model Acceleration
S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators
Antirandom vs. pseudorandom testing
Built-in test methodology for a full custom processor chip
Free ECC: An efficient error protection for compressed last-level caches
CPACT - The conditional parameter adjustment cache tuner for dual-core architectures
Secure Access Policy (SAP): Invisibly Executing Speculative Unsafe Accesses in an Isolated Environment
Customization of a CISC Processor Core for Low-Power Applications
Scaled Population Subtraction for Approximate Computing
Maximizing crosstalk-induced slowdown during path delay test
RMMIO: Enabling Reliable Memory-Mapped I/O for Persistent Memory Systems
Laser and Radiation Testing of Compiler-Based Protection for Multi-Bit Upsets
Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design
Fault-tolerant synthesis using non-uniform redundancy
Simplifying SoC design with the Customizable Control Processor Platform
Mera: Memory Reduction and Acceleration for Quantum Circuit Simulation via Redundancy Exploration
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation
In-Line Interrupt Handling for Software-Managed TLBs
2.5 Gbits/sec telecommunications gate array
A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications
HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer
DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention
Accelerating Persistent Hash Indexes via Reducing Negative Searches
RT-PMalloc: Optimizing Persistent Memory Allocation for Soft Real-Time Systems
Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
Accurate Performance Bounds Calculation for Dynamic Voltage-Freq Islands in Best Effort NoCs
IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011
Optimal Scheduling of Finite-State Machines
Performance assessment of embedded Hw/Sw systems
Value Speculation through Equality Prediction
Automatic synthesis of computation interference constraints for relative timing verification
A generalized approach to the constrained cubical embedding problem
The BACK algorithm for sequential test generation
TeraNOC: A Multi-Channel 32-Bit Fine-Grained, Hybrid Mesh-Crossbar Noc for Efficient Scale-Up of 1000+ Core Shared-L1-Memory Clusters
Optimizing Virtual Resource Management for Consolidated NUMA Systems
High performance circuits for the i486TM processor
Integrated Diagnostics for Embedded Memory Built-in Self Test on Power PC TM Devices
Subcomponent Timing-Based Detection of Malware in Embedded Systems
SpecLock: Speculative Lock Forwarding
Fingerprinting Field Programmable Gate Arrays
A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA
Application behavior aware re-reference interval prediction for shared LLC
Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles
Flame: A Multiplier-Free LLM Accelerator with Dynamic Block Floating Point
Modeling economics of LSI design and manufacturing for test design selection
The Tempest approach to distributed shared memory
Private Tensor Freezing for an Efficient Federated Learning with Homomorphic Encryption
HYPER: an interactive synthesis environment for high performance real time applications
Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans
Special Session: Quantum Error Correction in Near Term Systems
MIXER: Mixed-Signal Fault Simulator
A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units
Test generation in a parallel processing environment
RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments
Performance optimization for on-chip sensors to detect recycled ICs
Alloyed Path-pattern Scheme for Branch Prediction
Automatic layout generation for mixed analog-digital VLSI neural chips
QuRE: The Quantum Resource Estimator toolbox
Channel Density Minimization by Pin Permutation
A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips
Design and Test: The Lost World
Random testability analysis: comparing and evaluating existing approaches
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
The T9000 Transputer
Updates of the ITRS design cost and power models
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization
pacSCA: A Profiling-Assisted Correlation-based Side-Channel Attack on GPUs
SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order
Design Methodology and CAD Tools for the NVAX Microprocessor
An Architecture for Fast Processing of Large Unstructured Data Sets
Automatic Error Correction of Tri-State Circuits
An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration
Scan chain design for three-dimensional integrated circuits (3D ICs)
A Methodology for Rapid Prototyping of Analog Systems
Clock-Delayed Domino for Adder and Combinational Logic Desig
GPT-LS: Generative Pre-Trained Transformer with Offline Reinforcement Learning for Logic Synthesis
A global router on GPU architecture
Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor
Error-tolerance memory Microarchitecture via Dynamic Multithreading
Ant Colony Optimization directed program abstraction for software bounded model checking
Towards efficient dynamic data placement in NoC-based multicores
Power Grab in Aggressively Provisioned Data Centers: What is the Risk and What Can Be Done About It
Retiming for the Global Optimization of Synchronous Sequential Circuits
Spec Based Flip-Flop And Buffer Insertion
Design issues in mixed static-domino circuit implementations
CESAR - A programmable high performance systolic array processor
Predicting the throughput of multiprocessor applications under dynamic workload
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths
PROTEUS: Programmable Hardware for Telecommunication Systems
A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics
A global feedback detection algorithm for VLSI circuits
An FPGA Implementation of Stochastic Computing-Based LSTM
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor
Efficient Tagged Memory
Performance-controllable shared cache architecture for multi-core soft real-time systems
Intelligent backtracking in test generation for combinational circuits
Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II
Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces
Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems
Learning as applied to stochastic optimization for standard cell placement
Lumos+: Rapid, pre-RTL design space exploration on accelerator-rich heterogeneous architectures with reconfigurable logic
Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors
CAD Techniques for Embedded Systems-on-Silicon
Analyzing and controlling accuracy in stochastic circuits
A GaAs Receiver Module for Optoelectronic Computing and Interconnection