yusuke1997/dblp-id-title huggingface dataset:
A Pipelined Salsal20 Encryption Hardware Accelerator
Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip
Delay-Insensitive Cell Matrix
An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation
Limits of Dynamic Voltage and Frequency Scaling Algorithms
Low Power Methodologies and Challenges for PWM DC-DC Converters
Saving Cache Memory Using a Locking Cache in Real-time Systems
Hierarchical Multi-Scale Architectures with Spin Waves
Methods of Error Detection in Arithmetic Operations
A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist
The Design and Implementation of Partial Virtual Machine for Device Driver Fault Isolation
A New Methodology for Hardware Design Based on UML for SystemC
A Configuration Concept for a Massively Parallel FPGA Architecture
A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor
EM-Modeling of Excitation Source in Transverse Wave Approach (TWA) for RF Integrated Circuits Applications
CMOL FPGA circuits
Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs
Verilog Coding Style for Efficient Synthesis In FPGA
Single-Electron Tunneling Circuits for Image Processing Applications
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency
Optimal and Heuristic Testing Procedures for k-out-of-n Systems with Precedence Constraints
Crosstalk at the Dynamic Node of Domino CMOS Circuits
Improved Implementation Choices for Iterative Improvement Partitioning Algorithms on Circuits
A Dynamic ECC Scheme for Lengthening the Lifetime of Flash Memory
Monte Carlo Simulation For Optimized Sensitivity of Online Proactive Fault Monitoring Schemes
An Effective Replacement Policy Focusing on Lifetime of a Cache Line
Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs
New DSP Benchmark based on Selectable Mode Vocoder (SMV)
Scalable Directory Organization for Tiled CMP Architectures
Design of Low-area Rijndael Hardware Core
A Survey of Input Sensing and Processing Techniques for Multi-Touch Systems
A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications
Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation
A Low-Power, Pulsed Domino CMOS 64-bit Adder
A Hardware System for Tracking Eyes of Computer User
Null Conventional Logic (NCL) Implementation of a Bit-Wise Pipeline Dual-Rail (NCL) 2 (to the power of) S Complement Multiplier
Built-In Self-Test Circuit Optimization for Embedded Cores
Low Energy I-Cache for Embedded Processors
Evolving More Testable Digital Combinational Circuits
Simulation of a Turing Machine using EndoII Splicing Rules
ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design
Minimal Steiner Trees in X Architecture with Obstacles
Design for A Fast And Low Power 2's Complement Multiplier
Bio-Inspired Celluar Systems With Cyclic Metamorphic Memory
On the Management of Object Interrelationships
Completely Redundant Modular Exponentiation by Operand Changing
Reducing Memory References for FFT Calculation
Indirect-Mapped Caches: Approximating Set-Associativity with Direct-Mapped Caches
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme
Space and Time Efficient Lottery Scheduling
Use of Kernel (Regression) Based Methods for Sensor Validation
Communicating Distributed H systems with Simple Splicing Rules
Transcoding Load Distribution Policy for Wireless Mobile Clients
Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability
Possibility and Limitation of a Hardware-Assisted Data Prefetching Framework Using Off-Line Training of Markovian Predictors
On Increasing the Observability of Modern Microprocessors
Benchmarking GPU Devices with N-Body Simulations
A Block Based Validation Methodology for Derivative SoC Products
An O(L) Parallel Shortest Path Algorithm
Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase
A Cost-Effective TCP/IP Offload Accelerator Design for Network Interface Controller
A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization
A VHDL Design for PCA
A Multi-Block Interleaving Structure for NAND Flash Memory Storage
High Performance Cache
High-Speed Energy Estimation for Delay-Insensitive Circuits
Zero Detect-Based Low Power Registers File Access
Efficient Synthesis of Symmetric Function
Modeling Non-Iterated System Behavior with Chu Spaces
Performance Analysis of an Intel Pentium-4 Based Personal Computer for Multiplke Sequence Alignment
Compilation for Future Nanocomputer Architectures
Scan-Based Detection of Crosstalk Noise in FPGAs
Real Time Redundancy Study of a Exponential Time Dependent Model
On-Chip Split Shared Data Bus Architecture for SoC
Low-Power Branch Prediction
An FPGA Based Digital Speech Processor for Auditory Prosthesis
An Operand Status Based Instruction Steering Scheme for Clustered Architectures
Image Reconstruction Using Reconfigurable Hardware
Thermal-aware Duplicated Filter Cache for Improving Processor Reliability
Capturing Dynamic Memory Structures
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Pipeline Scheduling with Dual Voltages for Low Power Design
MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer Architectures
A Computer Algebra Algorithm for the Symbolic Solution of a Problem involving the diffusion of adatoms on a Circular Wafer when sculpting a Nanopore with an Ion Beam
Low Power Register File Design by Power Aware Register Assignment
Recurring Pattern Identification and its Application to Instruction Set Extension
Parallel and Fault-Tolerant Routing in Nanoscale Spin-Wave Architectures
Security of QImage File
Energy-Aware 32bit Parallel Processing Unit with Multi Operation Modes and 2 Step Data Gating Technique for Multimedia Processor
Is the Complicated ECC Array Necessary for Data Caches?
Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005
Teraflop Computing for Nanoscience
Hardware Acceleration of the Generalized Finite Automata Algorithm
Nanowire Crossbar PLA with Adaptive Variable Redundancy
Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling
An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation
The Zaaf Tablet PC Concept
Bandwidth-Friendly Cache Hierarchy
Estimation of Architectural Vulnerability Factors for Discrimination of Single Event Upsets in Cache Memory
A Modern Hardware Kit For Computer Science
A Generic Framework for Rapid Prototyping of System-on-Chip Designs
Performance Evaluation Model of Branch Input Vectors using Neural Network
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers
Planning and Designing Model of the Synthesized Design Method
Analytic Models for Peak Current Computation in General Interconnect Circuits
Improving the System Performance by a Dynamic File Prediction Model
Proceedings of the 2007 International Conference on Computer Design, CDES 2007, Las Vegas, Nevada, USA, June 25-28, 2007
An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits
Nanocompilation for the Cell Matrix Architecture
Development of FPGA Chip for Laser- based Distance Measurer for Defense Applications
The Impact of Cache Organization in Optimizing Microprocessor Power Consumption
Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes
Memory Design for Multimedia Applications
The Computing Technology And John Von Neumann's Computer Architecture Giving Way To Optical Computing
Analysis & Modeling of Substrate Noise in Domino CMOS Circuits
The Effect of Number of Virtual Channels on NoC EDP
A Built-in Current Monitor Design for Transient Current Testing
Performance Evaluation of Multimedia Extensions on Variable Many-Core Processors
CSPA: An Adder Faster Than Carry-Lookahead
A User-Space Device Driver Framework
DIM: a Post-Silicon Engineering Impact Analysis Method for Derivative SoC Products
A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters
Spectral Decomposition and Reconstruction of Telemetry Signals from Enterprise Computing Systems
Yield and Reliability Enhancement for VLSI Design
Proceedings of the 2009 International Conference on Computer Design, CDES 2009, July 13-16, 2009, Las Vegas Nevada, USA
Survey and Evaluation of Low-Power Flip-Flops
Moving From Binary Towards Multi-valued logic
Towards a Nanoscale Artificial Cortex
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS
How to Mark an Image from a Quantum Point of View
Semi-Contiguous Memory Allocation for Efficient Sequential-Access
How to Really Save Computer Energy?
Proactive Fault Monitoring in Enterprise Servers
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer
A New Processor Architecture with a New Program Driving Method
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006
Novel Complex Vauled Neural Networks
Protein Secondary Structure Prediction Accuracy versus Reduction Methods
Super-Program Architectures - A New Driving Method for Executing Instructions
Some Power-Law Scaling LImits to Computer Memory Architectures
Proceedings of the 2008 International Conference on Computer Design, CDES 2008, Las Vegas, Nevada, USA, July 14-17, 2008
Finite Element Technique to Mimic the Vibrational Behavior of Single-walled Carbon Nanotubes
Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
A Novel Functional Testing and Verification Technique for Logic Circuits
A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs
Efficient Global Fault Collapsing for Combinational Library Modules
Design and Verification of I/O Controller for Future Communication System
High-Level Automatic Test Generation for VHDL Descriptions
Delay-Insensitive Ternary Logic
A Fault Injection Attitude based on Background Debug Mode in Embedded Systems
Using Task Recomputation During Application Mapping in Parallel Embedded Architectures
A Survey on Power-Aware Computer System Design
Design of Network Security Platform with two XFI Interfaces using Network Processor
Compact Design of a Combined MixColumn/InvMixColumn Transformation Module for AES
Subbus Control Line Impact on Effectiveness of Bus Encoding Schemes
A Quantum Algorithm for Finding Minimum Exclusive-Or Expressions for Multi-Output Incompletely Specified Boolean Functions
Performance Measurement of Single, Dual and Quad Core Machines Using SPEC CPU2006
Low-Power Data Address Bus Encoding Method
Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations
EPIC: An Energy Exploitative Architecture
CLIW - Clue - Compressed Long Instruction Words
Thread Control Mechanism for Multithreading Processor
Modeling and Verification of a Distributed Transmission Protocol
Test Pattern Generation Method for VHDL Descriptions with BFS-DEVS Simulator
Classification Schemes of Software agents, with a Review of Development Technology and Framework
Finding Minimal ESCT Expressions for Boolean Functions with Weight of up to 7
A Survey of Nanotechnology Principles in Modern Computing Architectures
Implementation of Network Systems Using Network Processor Technology: Performance Evaluation
Effects of Register File Organization on Leakage Power Consumption
On Operating System Basic Building Blocks
NetSin: An Object-Oriented Architectural Simulator Suite
Low-Complexity Bypass Network Using Small RAM
A System-on-Chip Approach to Intelligent Traffic Signal Control
Design for Test Methodology for the IBM PowerPC 440 Embedded Core
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation
Parasitic Operating System with the Corresponding Computer System Architecture Thereof
Isleen Aid - An Alternative Input Method for Visually Impaired People
Particle Swarm Optimization: A Hardware Implementation
System - Level Partitioning for Embedded Systems Design Using Population - Based Incremental Learning
Architectural Sensitivity Analysis on Network Workloads
Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC
DAMQ Self-Compacting Buffer Schemes for Systems with Network-On-Chip
Nanofabric PLA Architecture with Double Variable Redundancy
Round-Robin Arbiter Design
Partial Reversible Gates(PRG) for Reversible BCD Arithmetic
DELSIC: A Delay Simulator for Interconnect Circuits
Implementation of Design For Test for Asynchronous NCL Designs
RHT: A Context-Based Return Address Predictor
Study on Evaluation and Optimization Measures of Shunfeng Express Green Logistics
Research on digital twin technology architecture for distribution network business collaboration
Research on the Spatial Layout Method of High Speed Rail Hub Based on Improved Faster R-CNN
Studying Intelligent Testing Algorithms for English Writing Using Neural Networks and English Semantics
Homomorphic Encryption-Based Privacy and Security Protection Method for Multi-Objective Electric Heat Network Collaborative Data
"Research on the Optimization of Agricultural Product Uplink(APU) Traceability System with\"Internet+Blockchain\" Technology"
Research on Carrying Capacity and Resource Management of Tourism Destinations Combined with Machine Learning
Research on Gear Image Classification Algorithm
Design of Employee Turnover Rate Prediction and Intervention Algorithm Based on Artificial Neural Network Model
Proceedings of the 2023 International Conference on AI and Metaverse in Supply Chain Management, AIMSCM 2023, Bhubaneswar, India, November 18-19, 2023
Research on Green Finance Investment Decision Based on Environmental Risk Assessment Algorithm from the Perspective of Innovation and Entrepreneurship
Adaptive Impedance Control for Force Tracking of the Chewing Robot
Research on Site Planning and Design of Mobile Communication Network Based on Multi-Objective Planning
Research on Supply Chain Risk Assessment Based on Grey Neural Network
Optimal planning of intelligent unmanned logistics vehicles based on different business models
A Data-Driven Examination of the Risk of Spot Market Electricity Prices
Research on Economic Data Collection and Analysis Platform Based on Cloud Computing and Internet of Things Technology
Design and Debugging of Transmission Handling Manipulator Control System in Automobile Production Line
Research on Natural Language Recognition Processing System in Computer Intelligent Graphics
Research on Cold Chain Food Logistics Traceability Method Based on Big Data Technology
Design and Implementation of Battery Performance Monitoring Device Based on STM Single Chip Microcomputer
Research on the Scheme Design and Strategy of Supply Chain Financial Security Based on Blockchain
Design of Risk Management Decision-making Framework for Tourism Enterprises Based on Artificial Intelligence
Examining the Efficacy of a Fuzzy Multi-Objective Integrated Logistics Model for Resolving Challenges in Green Supply Chain Management
Research on an operational control method of power grid digital twin model
Design and Simulation Analysis of Intelligent Acousto-Optic Control Circuit Between Corridors
A multi-dimensional information sensing and monitoring system based on wearable devices
Research on Emergency Logistics Management System of Drug Reserve Based on MySQL Database
Analysis of Agricultural Market Trend Under Digital Economy by Using Grey Neural Network
Efficiency improvements in the injection moulding unit based on the "machine for man"
Research on the Application of Witness in Logistics Management of Container Terminals
Financing Mode of Small and Medium-Sized Enterprises from the Perspective of Green Supply Chain Finance
Design of Road Traffic Light Circuit Based on Intelligent Control
Pronunciation Correction for Learners of Oral English in College English under Artificial Intelligence Algorithms: Based on Pronunciation Correction Model of Graph Neural Network
Research on Operation flow Optimization of Marine Container whole Business based on ECRS Analysis
Traffic Sign Recognition Using Improved YOLOv7 Model
Innovation of Enterprise Management Incentive Mechanism Based on IOT Technology
Time Series Analysis and Algorithm Application of Agricultural Product Price Forecast
Design and Implementation of a Web GIS-based Quality Management Information System for Reservoir Projects
Passenger Flow Prediction in Urban Rail Transit: An Ensemble Learning Method to Distinguish Between Weekdays and Holidays
DODA: A Decentralized Online Dating Application
Preliminary Study of Named Entity Recognition Techniques in Japanese Light Novels
A Machine Learning Based Method for Rating Adversarial Board Games
Effective Candidate Invariant Generation Using GPGPUs and Optimisations
Hippo: Accelerating Transaction Processing for Approximate Query Processing Engine with Sampling Semantics
PESA: Power-Efficient SPHINCS+ Accelerator for Multi-Domain Security Applications on FPGA SoC
Poisoning Attacks against Network Intrusion Detection Systems Using Shapley Values to Identify Trends in Poisoning Data
An eBPF-based packet capture system with embedded application metadata for network forensics
Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
Data Augmentation with Pseudo-Infrared Night-Vision Image Conversion for Improved Nighttime Object Detection
Asynchronous Separation of Unconscious Colored Robots
Eleventh International Symposium on Computing and Networking, CANDAR 2023 - Workshops, Matsue, Japan, November 27-30, 2023
Polynomial-Time Cloudlet Placement Scheme with an Improved Approximation Ratio
Security Risk Visualization for Open-Source Software based on Vulnerabilities, Repositories, and Dependencies
On Dynamics of Basic Network Creation Games with Non-Uniform Communication Interest
A Design of Multithreaded RISC-V Processor for Real-Time System
Bicycle-based collision prevention system using pedestrian trajectory prediction with an iPhone
Making Simplified SMR Protocol Tolerant to Partial Network Partitions
Updatable Decision Tree in Malware Detection Hardware Using Processor Information
A study for environmental adaptation of IoT devices
Twelfth International Symposium on Computing and Networking, CANDAR 2024, Naha, Japan, November 26-29, 2024
Privacy-preserving efficient M+1st-price sealed bid auction in cross-chain communication
A Dynamic Method for Forming Vehicle Platoons and Its Evaluations in Urban Areas
A Cryptanalysis against the Cheating Detectable Secret Sharing from NISS 2019
Priority-MPTCP: A Novel Multipath Data Transfer Method for V2V Communication
Motivation Survey and Influence Factor Analysis of Old People to Improve Digital Literacy
A GPU-Based Parallel Implementation of the GWO Algorithm: Application to the Solution of Large-Scale Nonlinear Equation Systems
Pseudo-Random Number Generation by Staggered Sampling of LFSR
Estimating tomato plant leaf area in greenhouse environment using multiple RGB-D cameras
Browser-based Java Development Environment for Programming Education
Multi-objective Quantum Optimization based on Bayesian Approach for Computing Resource Assignment Problems
Measuring Driver's Emotion
Performance Improvement of Federated Learning Server using Smart NIC
A Multitenant Single-Page Application for Programming Education
Resilient Pub/Sub Multicast in Dynamic MANETs with High Node Mobility
Depth-First Search Algorithms for Algebraic Connectivity Maximizing Regular Graphs
Analysis of API calls with 'A' and 'W' suffixes used in parent and child processes for ransomware detection
Evaluating Differential Privacy in Federated Continual Learning: A Catastrophic Forgetting-Performance Tradeoff Analysis
Petri net-based QUBO Model Formulation for Multi-Resource Flow-Shop Scheduling Problems
Performance Evaluation and Improvement of HTTP/3 Considering TLS
Emergency Button: Evacuation of Crypto Asset When Key Loss
A Smart Contract Based Blockchain Approach Integrated with Elliptic Curve Cryptography for Secure Email Application
Asynchronous Complete Visibility Algorithm for Luminous Robots on Grid
Bounded unpopularity matching in a (3, 3)-hypergraph with one-sided preferences
A Graph-based Molecular Structure Identification Method via Feature Extraction for Three-dimensional Electron Diffraction Data
A Hierarchical Heuristic for Clustered Steiner Trees in the Plane with Obstacles
Poisoning Attacks on Federated-learning based NIDS
AI-Based Multi-Objective Optimization Algorithm for Intelligent School Lunch Menu Planning System
Enhanced Source Location Privacy for Energy Efficiency in Underwater Wireless Sensor Networks
Fast Hybrid Transactional Index with Scalable Phantom Avoidance
Adaptive Thread Type Selection on the Java Virtual Machine
On Implementation of Brownian Circuits by Swarm Agents
An Implementation of an Instruction Controlled Cache Replacement Policy on a RISC-V Processor
Extraction of Subjective Information from Generative AI Models
Group Signatures with Designated Traceability over Openers' Attributes from Lattices
Analyzing Post-injection Attacker Activities in IoT Devices: A Comprehensive Log Analysis Approach
Hammering Tests of Tiles Fixed with Organic Adhesives with the aid of Machine Learning
Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
A Flow Distribution Algorithm with Segment Routing for Software-Defined Networking
CaT: A Category-oriented Transformer for Text and Sentiment Analysis in Japanese Hotel Overall Ratings Prediction
Verifiable Homomorphic Secret Sharing for SIMD Operations
A Performance Study on Rust and C Programs
BERT Pre-training for Cooking Time Prediction from Cooking Recipes
NUSS:Non-Interactive Updatable of Secret Sharing Schemes Using Homomorphic Encryption
Benchmarking Classical and Quantum Optimizers for Quantum Simulator
Serval: A Wait-free Multi-version Deterministic Concurrency Control Scheme
A Proposal of Solving NTRU Equation Using Matrix Representation Instead of Recursive Operation
Proxy-based Transaction Acceleration for NewSQL
Breaking SHA-1 through QUBO models
RNN-based Congestion Control in the Linux Kernel
A Learning-based Control Scheme for Prioritized SMT Processor
Deep Graph Attention Networks
Proposal and Evaluation of a Gaze Authentication Method that Combines Image Selection and Eye Movement Trajectory Features
A QA-Assisted Job Scheduler for Minimizing the Impact of Urgent Computing on HPC System Operation
Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28 - Dec. 1, 2023
Prevention Method for Stack Buffer Overflow Attack in TA Command Calls in OP-TEE
FPGA Implementation of a Pipelined XMSS Leaf Accelerator
An asynchronous P system for solving the minimum Steiner tree with branch and bound
An Improved Method for Detecting EDoS Attacks in the Cloud With Hyperparameter Optimization and Metaheuristic Algorithms
An implementation of ELiPS-based Ciphertext-Policy Attribute-Based Encryption
SEM: A Simple Yet Efficient Model-agnostic Local Training Mechanism to Tackle Data Sparsity and Scarcity in Federated Learning
Retrieving similar partial trajectories in soccer games considering surrounding player movements
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation
Small-Scale Implementation of a Hardware Detector for Malicious Communications and Malware Targeting the IoT
Online Assignment of Reservations to Parking Lots for Smart Cities under the i.i.d. Model
A Translation Method from 64-bit ARM Machine Code to LLVM IR for Binary-Level Optimization
Entity Linking for Wikidata using Large Language Models and Wikipedia Links
A Transparent Zero-Knowledge Dual Membership Set Commitment based on Perfect Hash Function