yusuke1997/dblp-id-title huggingface dataset:
A fast incremental clock skew scheduling algorithm for slack optimization
Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS
Maximizing the harvested energy for micro-power applications through efficient MPPT and PMU design
A constructive method for data path area estimation during high-level VLSI synthesis
Energy-efficient RISC design with on-demand circuit-level timing speculation
The multiple variable order problem for binary decision diagrams: theory and practical application
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology
Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply
Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs
Coarse grain reconfigurable architecture (embedded tutorial)
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator
The development of high performance FFT IP cores through hybrid low power algorithmic methodology
Stacking signal TSV for thermal dissipation in global routing for 3D IC
Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique
A Task Parallelism Runtime Solution for Deep Learning Applications using MPSoC on Edge Devices
On combining iteration space tiling with data space tiling for scratch-pad memory systems
LSTP: A Logic Synthesis Timing Predictor
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
Concurrency in DD-based Quantum Circuit Simulation
Optimizing routability in large-scale mixed-size placement
Lazy BTB: reduce BTB energy consumption using dynamic profiling
System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production
FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits
Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic Measurement
Communication protocol analysis of transaction-level models using Satisfiability Modulo Theories
A new CMAC neural network architecture and its ASIC realization
Guiding template-aware routing considering redundant via insertion for directed self-assembly
An optimization of AND-OR-EXOR three-level networks
A dual-MST approach for clock network synthesis
High performance lithographic hotspot detection using hierarchically refined machine learning
Transaction-based waveform analysis for IP selection
Efficient model reduction of interconnects via double gramians approximation
Quantization through Search: A Novel Scheme to Quantize Convolutional Neural Networks in Finite Weight Space
An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm
Delay abstraction in combinational logic circuits
A control theory approach for thermal balancing of MPSoC
Technology mapping with crosstalk noise avoidance
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
Heuristic power/ground network and floorplan co-design method
A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor
Multi-level placement for large-scale mixed-size IC designs
Learning to Prune and Low-Rank Adaptation for Compact Language Model Deployment
SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimization
Intelligent corner synthesis via cycle-consistent generative adversarial networks for efficient validation of autonomous driving systems
SISCO: Selective Invariant Sharing, Clustering and Ordering for Effective Multi-Property Formal Verification
Routability-driven bump assignment for chip-package co-design
Feasibility analysis of messages for on-chip networks using wormhole routing
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis
Air-Pressure-Model-Based Fast Algorithms for General Floorplan
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits
Enabling on-chip diversity through architectural communication design
Region definition and ordering assignment with the minimization of the number of switchboxes
Logic optimization for asynchronous speed independent controllers using transduction method
Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCs
Learning Assisted Side Channel Delay Test for Detection of Recycled ICs
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
The Liquid Metal IP bridge
LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference
Symmetry-aware placement with transitive closure graphs for analog layout design
Time-domain performance bound analysis of analog circuits considering process variations
PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM
A new linear-time harmonic balance algorithm for cyclostationary noise analysis in RF circuits
Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via
Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions
Power minimization by clock root gating
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems
LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip
Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPC
Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout
Motion Estimator LSI for MPEG2 High Level Standard
Modeling of coplanar waveguide for buffered clock tree
OpticalHDC: Ultra-fast Photonic Hyperdimensional Computing Accelerator
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification
Fast false path identification based on functional unsensitizability using RTL information
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Automated Power-saving User-interfaces for Application Designers
A novel network node architecture for high performance and function flexibility
Design of a high performance FFT processor based on FPGA
Room-temperature fuel cells and their integration into portable and embedded systems
How sub-micron delay and timing issues will be solved?
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs
Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation
BeSAT: behavioral SAT-based attack on cyclic logic encryption
CAR-Net: Solving Electrical Crosstalk Problem in Capacitive Sensing Array
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension
System-level architectural exploration using allocation-on-demand technique
Hardware architecture design of an H.264/AVC video codec
The future of semiconductor industry - A foundry's perspective
Process-induced skew reduction in nominal zero-skew clock trees
Realizable parasitic reduction for distributed interconnects using matrix pencil technique
ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation
BSC: Block-based Stochastic Computing to Enable Accurate and Efficient TinyML
Clock tree synthesis with data-path sensitivity matching
Approximation of Quantum States Using Decision Diagrams
VCO Jitter Simulation and Its Comparison With Measurement
A fast and accurate delay estimation method for buffered interconnects
Stochastic thermal simulation considering spatial correlated within-die process variations
Loop aware IR-level annotation framework for performance estimation in native simulation
Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparator
Fast vectorless power grid verification using maximum voltage drop location estimation
Logic Locking over TFHE for Securing User Data and Algorithms
Data partitioning for maximal scratchpad usage
Hybrid Compact Modeling Strategy: A Fully-Automated and Accurate Compact Model with Physical Consistency
Optimal simultaneous pin assignment and escape routing for dense PCBs
A Novel Performance-Driven Topology Design Algorithm
Abstraction and optimization of consistent floorplanning with pillar block constraints
MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Workload prediction and dynamic voltage scaling for MPEG decoding
A sharing-aware L1.5D cache for data reuse in GPGPUs
An ultra-low-noise differential relaxation oscillator based on a swing-boosting scheme
Rethinking error injection for effective resilience
An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis
Implementation of the super-systolic array for convolution
Delay-optimal wiring plan for the microprocessor of high performance computing machines
Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency
A Clock-Gating Method for Low-Power LSI Design
A formalism for functionality preserving system level transformations
ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction
On coloring rectangular and diagonal grid graphs for multiple patterning lithography
Compact yet high performance (CyHP) library for short time-to-market with new technologies
Synthesis of resilient circuits from guarded atomic actions
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains
Speed and voltage selection for GALS systems based on voltage/frequency islands
Compiler based exploration of DSP energy savings by SIMD operations
Logic synthesis for energy-efficient photonic integrated circuits
Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing
A Computation and Energy Efficient Hardware Architecture for SSL Acceleration
Maximizing data reuse for minimizing memory space requirements and execution cycles
Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded software
Quantum Data Compression for Efficient Generation of Control Pulses
Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel Pruning
Efficient parallel verification of Galois field multipliers
Automatic instrumentation of embedded software for high level hardware/software co-simulation
A current mode cyclic A/D converter with a 0.8 μm CMOS process
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs
RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations
Typing abstractions and management in a component framework
Analytical expressions for phase noise eigenfunctions of LC oscillators
Online hardware/software partitioning in networked embedded systems
Application of UML for hardware design based on design process model
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
A new and accurate interconnection delay time evaluation in a general tree-type network
Energy-Performance Co-Management of Mixed-Sensitivity Workloads on Heterogeneous Multi-core Systems
Analog circuit behavioral modeling via wavelet collocation method with auto-companding
Delay Uncertainty Reduction by Interconnect and Gate Splitting
BUQS: Battery- and user-aware QoS scaling for interactive mobile devices
A low-power management technique for high-performance domino circuits
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
PAALM: Power Density Aware Approximate Logarithmic Multiplier Design
Securing the hardware of cyber-physical systems
Three-dimensional place and route for FPGAs
Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphs
Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systems
LightSim: A leakage aware ultrafast temperature simulator
Thread partitioning method for hardware compiler bach
A volume diagnosis method for identifying systematic faults in lower-yield wafer occurring during mass production
A compressed frame buffer to reduce display power consumption in mobile systems
Obstacle-aware longest path using rectangular pattern detouring in routing grids
System level design technology for realizing an ambient intelligent environment
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures
Accelerating design space exploration using pareto-front arithmetics
FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors
Breaking Analog Biasing Locking Techniques via Re-Synthesis
Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems
A hardware/software codesign method for pipelined instruction set processor using adaptive database
On error tolerance and Engineering Change with Partially Programmable Circuits
Design-patterning co-optimization of SRAM robustness for double patterning lithography
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
A negative-resistance sense amplifier for low-voltage operating STT-MRAM
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform
A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology
Newton : a library-based analytical synthesis tool for RF-MEMS resonators
Computer-aided recoding for multi-core systems
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs
Routing on regular segmented 2-D FPGAs
Optimization of Linear Placements for Wirelength Minimization with Free Sites
A real-time 64-monosyllable recognition LSI with learning mechanism
Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing
Learned Image Codec on FPGA: Algorithm, Architecture and System Design
A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors
Approximate Computing for ML: State-of-the-art, Challenges and Visions
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction
On improving FPGA routability applying multi-level switch boxes
2-SAT based linear time optimum two-domain clock skew scheduling
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
Stochastic Multivariate Universal-Radix Finite-State Machine: a Theoretically and Practically Elegant Nonlinear Function Approximator
Interconnect capacitance estimation for FPGAs
Spiking brain models: Computation, memory and communication constraints for custom hardware implementation
Proceedings of the 29th Asia and South Pacific Design Automation Conference, ASPDAC 2024, Incheon, Korea, January 22-25, 2024
Line sharing cache: Exploring cache capacity with frequent line value locality
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits
Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification
Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Logic Design of Neural Networks for High-Throughput and Low-Power Applications
Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling
Automatic abstraction refinement of TR for PDR
Gate-level simulation of quantum circuits
When Machine Learning Meets Quantum Computers: A Case Study
Conformance and mirroring for timed asychronous circuits
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning
Enabling quality-of-service in nanophotonic network-on-chip
Electronics Development of Silicon Microdisplay for Virtual Reality Applications
The prospects of next generation television - Japan's initiative to 2020
Fault diagnosis aware ATE assisted test response compaction
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time
Automatic extraction of function bodies from software binaries
A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT Applications
DVFSspy: Using Dynamic Voltage and Frequency Scaling as a Covert Channel for Multiple Procedures
ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications
Manipulation of *BMDs
A fast and accurate network-on-chip timing simulator with a flit propagation model
A3MAP: architecture-aware analytic mapping for networks-on-chip
Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis
Frequency-dependent reluctance extraction
Energy optimization of stochastic applications with statistical guarantees of deadline and reliability
Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model
An efficient design of non-linear CA based PRPG for VLSI circuit testing
Flow Time Minimization under Energy Constraints
Pre-layout Delay Calculation Specification for CMOS ASIC Libraries
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems
Wire sizing with scattering effect for nanoscale interconnection
Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations
BDD-based two variable sharing extraction
Phone-nomenon: a system-level thermal simulator for handheld devices
A fast thermal aware placement with accurate thermal analysis based on Green function
Stoht: an SDL-to-hardware translator
27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022
Configurable Multi-Processor Platforms for Next Generation Embedded Systems
System-level development of embedded software
Technnology Mapping for Low Power
An efficient control-oriented coverage metric
Placement for Wafer-Scale Deep Learning Accelerator
ROBIN: A Novel Framework for Accelerating Robust Multi-Variant Training
Boosting Pin Accessibility Through Cell Layout Topology Diversification
CAPTOR: a class adaptive filter pruning framework for convolutional neural networks in mobile applications
Compiling SpecC for simulation
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
An HMAC processor with integrated SHA-1 and MD5 algorithms
Data sensing and analysis: Challenges for wearables
On resilient task allocation and scheduling with uncertain quality checkers
Security analysis and enhancement of model compressed deep learning systems under adversarial attacks
A processor core synthesis system in IP-based SoC design
A complete approach to unreachable state diagnosability via property directed reachability
RPack: routability-driven packing for cluster-based FPGAs
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications
ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture
An Adaptive Electromigration Assessment Algorithm for Full-chip Power/Ground Networks
Parametric reduced order modeling for interconnect analysis
Pin Tumbler Lock: A shift based encryption mechanism for racetrack memory
Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures
Vertical via design techniques for multi-layered P/G networks
Accurate remaining range estimation for Electric vehicles
Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC
Thermally optimal stop-go scheduling of task graphs with real-time constraints
Energy savings through embedded processing on disk system
Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology
A fast algorithm for finding common multiple-vertex dominators in circuit graphs
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS
Efficient circuit failure probability calculation along product lifetime considering device aging
Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation
Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing
Low power design of the next-generation High Efficiency Video Coding
Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs
The evolution of SoC platform according to the new mobile paradigm
ASP-DAC 2017 keynote speech III: All-programmable FPGAs: More powerful devices require more powerful tools
Variability-aware memory management for nanoscale computing
A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation
ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
Cellular automata as a built in self test structure
Low-power silicon architecture for wireless communications: embedded tutorial
Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability
Complexity-effective auditory compensation with a controllable filter for digital hearing aids
A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip
Concurrent cell generation and mapping for CMOS logic circuits
Object-oriented modeling and synthesis of SystemC specifications
CMOS-on-quartz pulse generator for low power applications
Battery-aware instruction generation for embedded processors
Optimality and scalability study of existing placement algorithms
Delay defect screening for a 2.16GHz SPARC64 microprocessor
Temperature-aware global placement
An Analytical Delay Model for SRAM-Based FPGA Interconnections
Track routing optimizing timing and yield