yusuke1997/dblp-id-title huggingface dataset:
Proceedings of the 8th annual workshop on Microprogramming, MICRO 1975, Chicago, Illinois, USA, September 21-23, 1975
Characterizing the resource-sharing levels in the UltraSPARC T2 processor
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity
Processor Acceleration Through Automated Instruction Set Customization
ASR: Adaptive Selective Replication for CMP Caches
Compacting MIMOLA microcode
Task Superscalar: An Out-of-Order Task Pipeline
Fitting processors to the needs of a General Purpose Array (EGPA)
Value-Based Deep Learning Hardware Acceleration
DSPatch: Dual Spatial Pattern Prefetcher
Control flow obfuscation with information flow tracking
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
More with Less - Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization
Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash
Finding concurrency bugs with context-aware communication graphs
Vector Extensions for Decision Support DBMS Acceleration
Load Value Approximation
Penelope: The NBTI-Aware Processor
A chip set microarchitecture for a high-performance VAX implementation
A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus
Shapeshifter: Dynamically changing pipeline width and speed to address process variations
I/O device Emulation in The Stanford Emulation Laboratory
The proposal of a computing model for prototypes of microprogrammed machines solving complex problems
Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories
Target-independent high-level microprogramming
Realizing Emotional Interactions to Learn User Experience and Guide Energy Optimization for Mobile Architectures
Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning
(Almost) Fence-less Persist Ordering
Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations
GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
AutoScale: Energy Efficiency Optimization for Stochastic Edge Inference Using Reinforcement Learning
Speculative lock elision: enabling highly concurrent multithreaded execution
Proceedings of the 13th annual workshop on Microprogramming, MICRO 1980, Colorado Springs, Colorado, USA
Exploiting data-width locality to increase superscalar execution bandwidth
Increasing the size of atomic instruction blocks using control flow assertions
Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992
NoCVision: A Network-on-Chip Dynamic Visualization Solution
Minimum register requirements for a modulo schedule
Linearizing irregular memory accesses for improved correlated prefetching
Scalable Hardware Memory Disambiguation for High ILP Processors
Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
MAD MAcce: Supporting Multiply-Add Operations for Democratizing Matrix-Multiplication Accelerators
A data-flow driven resource allocation in a retargetable microcode compiler
Controlling and sequencing a heavily pipelined floating-point operator
Superblock formation using static program analysis
A functional model of clocked microarchitectures
Microarchitecture and Design Challenges for Gigascale Integration
AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers
On approximation algorithms for microcode bit minimization
Improving Scalability in Thermally Resilient Hybrid Photonic-Electronic NoCs
PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors
Architectural support for secure virtualization under a vulnerable hypervisor
Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory
Initial Results on the Performance and Cost of Vector Microprocessors
NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
Proactive instruction fetch
Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latency
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Enhanced modulo scheduling for loops with conditional branches
High level language programs run ten times faster in microstore
ENMC: Extreme Near-Memory Classification via Approximate Screening
Executing compressed programs on an embedded RISC architecture
Morph: Flexible Acceleration for 3D CNN-Based Video Understanding
A study of slipstream processors
Floodgate: application-driven flow control in network-on-chip for many-core architectures
Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling
Alternative implementations of hybrid branch predictors
Dynamic acceleration of multithreaded program critical paths in near-threshold systems
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance
A model of clocked micro-architectures for firmware engineering and design automation applications
Eager writeback - a technique for improving bandwidth utilization
Operating system enhancement through firmware
An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers
Efficiently enforcing strong memory ordering in GPUs
A code decompression architecture for VLIW processors
Global Predicate Analysis and Its Application to Register Allocation
Y-Pipe: a conditional branching scheme without pipeline delays
Microprogrammed implementation of a single chip microprocessor
LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering
Dictionary sharing: An efficient cache compression scheme for compressed caches
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory
A firmware monitor to support vertical migration decisions in the UNIX operating system
Bungee jumps: accelerating indirect branches through HW/SW co-design
A new universal microprogram converter
IDEAL: image denoising accelerator
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs
Accelerating microprocessor silicon validation by exposing ISA diversity
Two implementations of the 'FLEX' machine
Warped gates: gating aware scheduling and power gating for GPGPUs
Using an oracle to measure potential parallelism in single instruction stream programs
CSE: Parallel Finite State Machines with Convergence Set Enumeration
Hardware microcontrol schemes using PLAs
3D-FPIM: An Extreme Energy-Efficient DNN Acceleration System Using 3D NAND Flash-Based In-Situ PIM Unit
The era of many-modules SoC: revisiting the NoC mapping problem
Boosting Store Buffer Efficiency with Store-Prefetch Bursts
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
Proceedings of the 8th International Workshop on Network on Chip Architectures, NoCArc '15, Waikiki, HI, USA, December 5, 2015
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach
Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins
Dynamic addressing memory arrays with physical locality
Self-Managing DRAM: A Low-Cost Framework for Enabling Autonomous and Efficient DRAM Maintenance Operations
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
DaDianNao: A Machine-Learning Supercomputer
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
Point Cloud Acceleration by Exploiting Geometric Similarity
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
A communication-centric approach for designing flexible DNN accelerators
A microprogrammed storage management system for a paged stack machine
Architectural Support for Efficient Large-Scale Automata Processing
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip
Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications
Compresso: Pragmatic Main Memory Compression
Motivation and framework for using genetic algorithms for microcode compaction
Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis
CoScale: Coordinating CPU and Memory System DVFS in Server Systems
Defending Against EMI Attacks on Just-In-Time Checkpoint for Resilient Intermittent Systems
PASC-HLL: An experience in design techniques for firmware and the supporting hardware
Limitation of superscalar microprocessor performance
Systems Architecture for Quantum Random Access Memory
A New Technique for Induction Variable Removal
Harnessing Soft Computations for Low-Budget Fault Tolerance
Register renaming and dynamic speculation: an alternative approach
On balancing hardware-firmware for designing a fault-tolerant computers' series
In-Register Parameter Caching for Dynamic Neural Nets with Virtual Persistent Processor Specialization
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads
Beehive: A Flexible Network Stack for Direct-Attached Accelerators
InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing
The 16-fold way: a microparallel taxonomy
LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs
Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors
Prefetched Address Translation
Predicting Future-System Reliability with a Component-Level DRAM Fault Model
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
Efficient conditional operations for data-parallel architectures
SwiftDir: Secure Cache Coherence without Overprotection
IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems
Qubit Mapping and Routing via MaxSAT
Development of courses in microprogramming
Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems
A Dynamically Adaptable Hardware Transactional Memory
An investigation of the performance of various instruction-issue buffer topologies
CleanupSpec: An "Undo" Approach to Safe Speculation
A case for dynamic frequency tuning in on-chip networks
Verification of chip multiprocessor memory systems using a relaxed scoreboard
A representation for the analysis of microprogram operation
Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
DELI: a new run-time control point
Emulating an MIMD architecture
Extensibility - a new approach for designing machine independent microprogramming languages
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks
Continuous Path and Edge Profiling
Delaying Physical Register Allocation through Virtual-Physical Registers
DESC: energy-efficient data exchange using synchronized counters
The Fuzzy Correlation between Code and Performance Predictability
SAM: Accelerating Strided Memory Accesses
Free launch: optimizing GPU dynamic kernel launches through thread reuse
Multiple instruction issue and single-chip processors
IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming
A comparision of superscalar and decoupled access/execute architectures
Compiling Prolog into microcode: a case study using the NCR/32-000
SUV: Static Analysis Guided Unified Virtual Memory
QuComm: Optimizing Collective Communication for Distributed Quantum Computing
Characterizing and predicting value degree of use
MICROSIM: A microinstruction simulator for teaching microprogramming and emulation
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
GraphQ: Scalable PIM-Based Graph Processing
Equinox: Training (for Free) on a Custom Inference Accelerator
Design and implementation of a flexible and interactive microprogram simulator
Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays
Approximate storage in solid-state memories
A data abstraction language based on microprogramming
User microprogrammability in the HP-21MX minicomputer
Enabling dynamic and programmable QoS in SoCs
Accurate and efficient predicate analysis with binary decision diagrams
Effective compiler support for predicated execution using the hyperblock
A compilation technique for software pipelining of loops with conditional jumps
Avoiding information leakage in the memory controller with fixed service policies
Hardware Prefetchers Leak: A Revisit of SVF for Cache-Timing Attacks
UDP: a programmable accelerator for extract-transform-load workloads and more
Resilient microring resonator based photonic networks
Dataflow Predication
S4NOC: a minimalistic network-on-chip for real-time multicores
Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip
Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010
Three-dimensional memory vectorization for high bandwidth media memory systems
The instruction parsing microarchitecture of the CVAX microprocessor
Optimization for a Superscalar Out-of-Order Machine
CounterMiner: Mining Big Performance Data from Hardware Counters
Improving DRAM latency with dynamic asymmetric subarray
A new rapid prototyping firmware (RPF) tool
ERASER: Towards Adaptive Leakage Suppression for Fault-Tolerant Quantum Computing
Design and realization of MLM: a multilingual machine
Instruction scheduling for the Motorola 88110
Binary Star: Coordinated Reliability in Heterogeneous Memory Systems for High Performance and Scalability
Efficient static single assignment form for predication
ZR: a 3D API transparent technology for chunk rendering
Reconfigurable Links for Self-Timed On-Chip Communication
Controlled graphs and instructions
Accelerating RTL Simulation with Hardware-Software Co-Design
Practical Byte-Granular Memory Blacklisting using Califorms
Horus: Persistent Security for Extended Persistence-Domain Memory Systems
Execution time prediction for energy-efficient hardware accelerators
Procedure for testing microprograms
Predictor-directed stream buffers
Hardware Support for Relaxed Concurrency Control in Transactional Memory
AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads
Design of a testable RISC-to-CISC control architecture
Thermal Management of On-Chip Caches Through Power Density Minimization
Fast-BCNN: Massive Neuron Skipping in Bayesian Convolutional Neural Networks
Instruction Fetch Mechanisms for Multipath Execution Processors
SwapCodes: Error Codes for Hardware-Software Cooperative GPU Pipeline Error Detection
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
STEP development tools: METASTEP language system
Dataflow execution of sequential imperative programs on multicore architectures
Phantom: Exploiting Decoder-detectable Mispredictions
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
Ghost Arbitration: Mitigating Interconnect Side-Channel Timing Attacks in GPU
Short-Circuiting Memory Traffic in Handheld Platforms
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks
Deterministic Atomic Buffering
FloatAP: Supporting High-Performance Floating-Point Arithmetic in Associative Processors
DaxVM: Stressing the Limits of Memory as a File Interface
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints
Harnessing voltage margins for energy efficiency in multicore CPUs
Low-cost soft error resilience with unified data verification and fine-grained recovery for acoustic sensor based detection
Minimizing branch misprediction penalties for superpipelined processors
Random Fill Cache Architecture
Sparse Tensor Core: Algorithm and Hardware Co-Design for Vector-wise Sparse Neural Networks on Modern GPUs
ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization
A low-cost host processor for emulation research
Control flow prediction with tree-like subgraphs for superscalar processors
Crossing the machine interface
CoreRacer: a practical memory race recorder for multicore x86 TSO processors
The effect of speculatively updating branch history on branch prediction accuracy, revisited
Efficient macro-code emulation in hardwired pipelined processors
CRONUS: Fault-isolated, Secure and High-performance Heterogeneous Computing for Trusted Execution Environment
Space Microdatacenters
VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors
Modulo scheduling with multiple initiation intervals
Azul: An Accelerator for Sparse Iterative Solvers Leveraging Distributed On-Chip Memory
Stream Programming on General-Purpose Processors
A dynamic very high-level debugger for low-level microprograms
A system level perspective on branch architecture performance
Speculative execution exception recovery using write-back suppression
Yield enhancement by robust application-specific mapping on Network-on-Chips
Tradeoffs in processor/memory interfaces for superscalar processors
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
ReplayCache: Enabling Volatile Cachesfor Energy Harvesting Systems
RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation
Some correctness principles for machine language programs and microprograms
Exploiting short-lived variables in superscalar processors
FPGA Bitstream Modification with Interconnect in Mind
Software Pipelining for Transport-Triggered Architectures
Reducing memory traffic with CRegs
Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors
NoxyGen: A Network-On-Chip RTL Generator and Validation Tool
GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping
The implementation of Prolog via VAX 8600 microcode
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020
Pack & Cap: adaptive DVFS and thread packing under power caps
GRAPE: Minimizing energy for GPU applications with performance requirements
A practical approach to the evaluation of microcode systems
Challenges and opportunities of wireless network-on-chip for manycore architectures
Multi-GPU System Design with Memory Networks
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication
Theoretical modeling of superscalar processor performance
Virtually Pipelined Network Memory
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Partitioned register file for TTAs
On the instruction-level characteristics of scalar code in highly-vectorized scientific applications
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?
Static branch frequency and program profile analysis
HARMONY: Heterogeneity-Aware Hierarchical Management for Federated Learning System
Reducing peak power with a table-driven adaptive processor core
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication
2n-way jump microinstruction hardware and an effective instruction binding method
An integrated approach to the design of fault tolerant computing systems
ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
Graph-partitioning based instruction scheduling for clustered processors
49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016
Iterative modulo scheduling: an algorithm for software pipelining loops
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Stripes: Bit-serial deep neural network computing
Second International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York, NY, USA
Some studies on microprogram optimization
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics
BurstLink: Techniques for Energy-Efficient Video Display for Conventional and Virtual Reality Systems
Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches
Automatic Synthesis of High-Speed Processor Simulators
RACER: Bit-Pipelined Processing Using Resistive Memory
Q3DE: A fault-tolerant quantum computer architecture for multi-bit burst errors by cosmic rays
An experimental microarchitecture for a superconducting quantum processor
Efficient Router Bypass via Hybrid Flow Control
A fine-grained MIMD architecture based upon register channels
Characterizing and Mitigating Soft Errors in GPU DRAM
Asymmetric routing in 3D NoC using interleaved edge routers
Conference record of the 7th annual workshop on Microprogramming, MICRO 1974, Palo Alto, California, USA, September 30 - October 2, 1974
A VLIW architecture for optimal execution of branch-intensive loops
Microcode development for microprogrammed processors
TDL: A hardware/microcode test language interpreter
Software Pipelining: An Evaluation of Enhanced Pipelining
Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks
Impact of Cache Coherence Protocols on the Processing of Network Traffic
Adaptation and personalization of VLSI-based computer architecture
Light64: lightweight hardware support for data race detection during systematic testing of parallel programs
On-chip wireless interconnect paradigm
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
ADA-GP: Accelerating DNN Training By Adaptive Gradient Prediction
From SODA to scotch: The evolution of a wireless baseband processor
A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs
Cerebros: Evading the RPC Tax in Datacenters
Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization
Stream-Based Data Placement for Near-Data Processing with Extended Memory
Towards a microprogramming language schema
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design
Formally based static analysis of microcode
Instruction decomposition and microprogramming by exception in a generalized processor
On heterogeneous network-on-chip design based on constraint programming
GPUMech: GPU Performance Modeling Technique Based on Interval Analysis
Execution time (and memory) optimization in microprograms
Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures
Characterizing and mitigating the impact of process variations on phase change based memory systems
ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning
Ideograph/Ideogram: framework/hardware for eager evaluation
51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018