yusuke1997/dblp-id-title huggingface dataset:
Iterative Wirability and Performance Improvement for FPGAs
Distributed scheduling for many-cores using cooperative game theory
On-Device Unsupervised Image Segmentation
Critical Paths Prediction under Multiple Corners Based on BiLSTM Network
A Memory-Efficient Edge Inference Accelerator with XOR-based Model Compression
Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers
SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory
EnAAM: energy-efficient anti-aging for on-chip video memories
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
Automated board layout
Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis
Safe Controller Synthesis for Nonlinear Systems via Reinforcement Learning and PAC Approximation
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs
A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects
IAfinder : identifying potential implicit assumptions to facilitate validation in medical cyber-physical system
Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing
Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout
The MICON System for Computer Design
Extending the lifetime of fuel cell based hybrid systems
A security vulnerability analysis of SoCFPGA architectures
An Efficient Routing Algorithm for SOG Cell Generation on a Dense Gate-Isolated Layout Style
A "greedy" channel router
Near-optimal n -layer channel routing
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis
MEMTONIC: A Neuromorphic Accelerator for Energy Efficient Deep Learning
Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits
Wireless platforms: GOPS for cents and MilliWatts
HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
An Efficient Non-Quasi-Static Diode Model for Circuit Simulation
A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986
Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking
Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations
A Dynamic Design Estimation and Exploration Environment
Engineering synthetic killer circuits in bacteria
A real-time program trace compressor utilizing double move-to-front method
Adaptive sensitivity analysis with nonlinear power load modeling
Computer hardware description languages and their applications
Automated Pipeline Design
GDRouter: interleaved global routing and detailed routing for ultimate routability
Use of the subscripted DALG in submodule testing with applications in cellular arrays
MCU-Wide Timing Side Channels and Their Detection
A Flat Timing-Driven Placement Flow for Modern FPGAs
On logic comparison
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis
On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration
Design space exploration and prototyping for on-chip multimedia applications
On the exploitation of the inherent error resilience of wireless systems under unreliable silicon
Throughput maximization for periodic real-time systems under the maximal temperature constraint
ACE: A Circuit Extractor
Design of a high-throughput low-power IS95 Viterbi decoder
Interactive shape generation and spatial conflict testing
DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis
Man-machine interaction in the design of rotating electrical machines
3 Channel Dependency-Based Power Model for Mobile AMOLED Displays
Grasp: Group-based Prediction of Activation Sparsity for Fast LLM Inference
A Methodology for the Verification of a "System on Chip"
HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition
A Memory-Efficient LLM Accelerator with Q-K Correlation Prediction using Cluster-Based Associative Array for Selective KV Accessing
Latch Clustering for Timing-Power Co-Optimization
An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits
Design automation effects on the organization
False timing path identification using ATPG techniques and delay-based information
High-level Software Energy Macro-modeling
Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning
Efficient winograd-based convolution kernel implementation on edge devices
Adaptive neural recovery for highly robust brain-like representation
Quantum-dot cellular automata: computing by field polarization
FPGA Security: From Features to Capabilities to Trusted Systems
On-line circuit analysis and optimization with commercially available time-shared computer systems
Dynamic design rule checking in an interactive printed circuit editor
Reconfigurable computing using content addressable memory for improved performance and resource usage
Efficient and Scalable Architectures for Multi-level Superconducting Qubit Readout
Statistical Estimation of Average Power Dissipation in Sequential Circuits
Multi-level approach for integrated spiral inductor optimization
False Coupling Interactions in Static Timing Analysis
Methods for hierarchical automatic layout of custom LSI circuit masks
Yield analysis modeling
ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor
LLMs Meet Post-Silicon Test Engineering: A New Era (Invited)
An Improved Synthesis Algorithm for Multiplexor-Based PGA's
Synthesis from Production-Based Specifications
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation
Optimal bipartite folding of PLA
MES-Attacks: Software-Controlled Covert Channels based on Mutual Exclusion and Synchronization
A power and temperature aware DRAM architecture
A Module Area Estimator for VLSI Layout
Instruction set processor specifications for simulation, evaluation, and synthesis
On Minimizing the Number of L-Shaped Channels
Inductive Verification of Iterative Systems
A New Model for the High Level Description and Simulation of VLSI Networks
LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic locking
An automated simultaneous probing system for testing complex logic assemblies 'the bed of nails system'
Logic simulation for LSI
Low power network processor design using clock gating
A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines
Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices
Comparing Structurally Different Views of a VLSI Design
Clustering and linear placement
Worst-case aggressor-victim alignment with current-source driver models
Virtualizing embedded systems: why bother?
Invited - Airtouch: a novel single layer 3D touch sensing system for human/mobile devices interactions
A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits
Sparse LU factorization for parallel circuit simulation on GPU
NASFLOW, a Simulation Tool for Silicon Technology Development
McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMs
The challenge of interoperability: model-based integration for automotive control software
Error-resilient low-power DSP via path-delay shaping
A quantum annealing approach for boolean satisfiability problem
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility
PUFiM: A Robust and Efficient FeFET-Based Security Solution Merging Physical Unclonable Function with Compute-in-Memory for Edge AI
Clock buffer and wire sizing using sequential programming
Advanced Techniques for Designing Stealthy Hardware Trojans
Energy-Efficient Large-Scale Vector Similarity Search in NAND-Flash via Hybrid Matching
Developing synthesis flows without human knowledge
GPU obfuscation: attack and defense strategies
TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC
On Thermal Effects in Deep Sub-Micron VLSI Interconnects
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade
Demystifying Energy Usage in Smartphones
PracMHBench: Re-evaluating Model-Heterogeneous Federated Learning Based on Practical Edge Device Constraints
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture
Exact Minimum Cycle Times for Finite State Machines
VLSI design methodology the problem of the 80's for microprocessor design
An efficient shift invariant rasterization algorithm for all-angle mask patterns in ILT
Automatic architecture refinement techniques for customizing processing elements
An automated probing procedure for board testing
ALIGN: Open-Source Analog Layout Automation from the Ground Up
A Design Rule Independent Cell Compiler
Combinational logic synthesis from an HDL description
Oil fields, hedge funds, and drugs
Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
A database management system for design engineers
Application and realization of gateways between conventional automotive and IP/ethernet-based networks
Developments in verification of design correctness (A Tutorial)
Hardware speech recognition for user interfaces in low cost, low power devices
Embedded memory binding in FPGAs
Re-synthesis for delay variation tolerance
Pad Placement and Ring Routing for Custom Chip Layout
Computer/interactive cleanup of non-gridded PWB's after automatic routing
MIST - A Design Aid for Programmable Pipelined Processors
ACCLAIM - a computer aided design system
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987
Electronic Chip-in-Place Test
"A minicomputer-based logic-fault simulator"
Equivalence among stochastic logic circuits and its application
Fast Online/Offline Netlist Compilation of Hierarchical Schematics
VIPER: An Efficient Vigorously Sensitizable Path Extractor
Horizontal Partitioning of PLA-based Finite State Machines
XBioSiP: A Methodology for Approximate Bio-Signal Processing at the Edge
Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm
A standard cell initial placement strategy
An Efficient Deep Learning Accelerator for Compressed Video Analysis
Partitioning Very Large Circuits Using Analytical Placement Techniques
Formal Techniques for SystemC Verification; Position Paper
Joint precision optimization and high level synthesis for approximate computing
Re-target-able software power management framework using SoC data auto-generation
Process variation-aware routing in NoC based multicores
Workload-Aware Harmonic Partitioned Scheduling of Periodic Real-Time Tasks with Constrained Deadlines
Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications
Layout design-lessons from the Jedi designer (tutorial session)
FLNA: An Energy-Efficient Point Cloud Feature Learning Accelerator with Dataflow Decoupling
The Electronic Design Interchange Format EDIF: Present and Future
Implementation of an interactive printed circuit design system
Power management of hybrid DRAM/PRAM-based main memory
The automatic recognition of silicon gate transistor geometries: An LSI design aid program
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing
IP delivery for FPGAs using Applets and JHDL
JPDHeap: A JVM Heap Design for PM-DRAM Memories
PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory System
Vex - A CAD Toolbox
Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect
Solid model in geometric modelling system: HICAD
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Technical documentation by "MAGIC" (Machine Aided Graphics for Illustration and Composition
Smart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors
Embedding Functions Into Reversible Circuits: A Probabilistic Approach to the Number of Lines
Interactive wiring system
DiffPattern: Layout Pattern Generation via Discrete Diffusion
Functionally linear decomposition and synthesis of logic circuits for FPGAs
Efficient Boolean Division and Substitution
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
Efficient Transformer Inference with Statically Structured Sparse Attention
Test-case generation for embedded simulink via formal concept analysis
Scalable min-register retiming under timing and initializability constraints
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs
Partitioning logic circuits to maximize fault resolution
Reducing clock skew variability via cross links
Automatic System Level Test Generation and Fault Location for Large Digital Systems
Virtual Chip: Making Functional Models Work on Real Target Systems
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision
Design Principles for True Random Number Generators for Security Applications
Computer aided design of long-haul optical transmission systems
Optimal integer delay budgeting on directed acyclic graphs
ADAM: run-time agent-based distributed application mapping for on-chip communication
INCOD: A system for Interactive Conceptual Data Base Design
Incremental retiming for FPGA physical synthesis
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation
PairGraph: An Efficient Search-space-aware Accelerator for High-performance Concurrent Pairwise Queries
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract)
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction
Structured/platform ASIC apprentices: which platform will survive your board room?
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs
Design automation - lessons of the past, challenges for the future
AASD: Accelerate Inference by Aligning Speculative Decoding in Multimodal Large Language Models
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters
Protecting bus-based hardware IP by secret sharing
Invited: Pre-silicon Side Channel and Fault Analysis
Security Opportunities and Challenges for Disaggregated Architectures (Invited)
A high performance delay calculation software system for MOSFET digital logic chips
Taming the complexity of coordinated place and route
Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service
Power-based side-channel instruction-level disassembler
Government interest and involvement in design automation development (Panel Discussion)
Modular description/simulation/synthesis using DDL
Digital test generation and design for testability
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL
Hardware-software co-design of embedded reconfigurable architectures
Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories
A Scheme for Integrated Controller-Datapath Fault Testing
A Clock Tree Optimization Framework with Predictable Timing Quality
StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic Circuits
Module positioning algorithms for rectilinear macrocell assemblies
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree Architecture
Optimization of Area in Digital FIR Filters using Gate-Level Metrics
ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement Learning
Core vs. uncore: the heart of darkness
Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
Exact One-pass Synthesis of Digital Microfluidic Biochips
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs
Protection and Versioning for OCT
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly support-circuit preconditioners
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits
A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction
Efficient implementation of experimental design systems
New Techniques for Efficient Verification with Implicitly Conjoined BDDs
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization
Interaction, interfaces and design
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview
A Performance and Routability Driven Router for FPGAs Considering Path Delays
Harnessing Conventional Video Processing Insights for Emerging 3D Video Generation Models: A Comprehensive Attention-aware Way
Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors
FACOM 230-series computer design automation system
Incremental Event-Driven Simulation of Digital FET Circuits
Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems
A reconfigurable analog substrate for highly efficient maximum flow computation
Hybrid simulation for embedded software energy estimation
Comprehensive Integration of Hyperdimensional Computing with Deep Learning towards Neuro-Symbolic AI
Power gating scheduling for power/ground noise reduction
Auto-ISP: An Efficient Real-Time Automatic Hyperparameter Optimization Framework for ISP Hardware System
Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design
Efficient methods for embedded system design space exploration
A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions
New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour
Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography
Flushing-Enabled Loop Pipelining for High-Level Synthesis
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs
Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning
New sub-20nm transistors: why and how
Automated design of operational transconductance amplifiers using reversed geometric programming
Power emulation: a new paradigm for power estimation
BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks
A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Ultralow power acoustic feature-scoring using gaussian I-V transistors
The state-of-the-art in semiconductor reverse engineering
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
Data Parallel Simulation Using Time-Warp on the Connection Machine
Fast Virtual Gate Extraction For Silicon Quantum Dot Devices
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
Litmus tests for comparing memory consistency models: how long do they need to be?
SimLL: Similarity-Based Logic Locking Against Machine Learning Attacks
Fast Hypergraph Partition
High-performance operating system controlled memory compression
Interface Timing Verification with Application to Synthesis
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning
Retiming of Two-Phase Latch-Based Resilient Circuits
High-Level Power Modeling, Estimation, and Optimization
Hardware Support for Durable Atomic Instructions for Persistent Parallel Programming
Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias
Business models in IP, software licensing, and services
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs
Multi-threaded collision-aware global routing with bounded-length maze routing
Multiprocessor-based placement by simulated annealing
ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via Rowhammer
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Automating Constraint-Aware Datapath Optimization using E-Graphs
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis
New Test Data Decompressor for Low Power Applications
Optimal Wire-Sizing Formular Under the Elmore Delay Model
Late Breaking Results: Parallelizing Net Routing with cGANs
Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box? (Panel Abstract)
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems
Design of high performance pattern matching engine through compact deterministic finite automata
An Advanced Timing Characterization Method Using Mode Dependency
GaBAN: a generic and flexibly programmable vector neuro-processor on FPGA
SALSA: systematic logic synthesis of approximate circuits
Automatic placement a review of current techniques (tutorial session)
Routing Considerations in Symbolic Layout Synthesis
MIDAS an on-line real time material system
KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA
Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization
Replay4NCL: An Efficient Memory Replay-based Methodology for Neuromorphic Continual Learning in Embedded AI Systems
MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design
EP-ORAM: Efficient NVM-Friendly Path Eviction for Ring ORAM in Hybrid Memory
Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
Enabling On-Device Large Language Model Personalization with Self-Supervised Data Selection and Synthesis
Glitch Analysis and Reduction in Register Transfer Level
Delay and power optimization in VLSI circuits
The structure and operation of a relational database system in a cell-oriented integrated circuit design system
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip
Circuit-aware architectural simulation
Global Floorplanning via Semidefinite Programming