yusuke1997/dblp-id-title huggingface dataset:
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
Embedded software debug and test: Needs and requirements for innovations in debugging
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines
A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography
A low-power VLIW processor for 3GPP-LTE complex numbers processing
Panel: The world is going... analog & mixed-signal! What about EDA?
Self-Supervised Quantization of Pre-Trained Neural Networks for Multiplierless Acceleration
Activation Density based Mixed-Precision Quantization for Energy Efficient Neural Networks
Are Analytical Techniques Worthwhile for Analog IC Placement?
Simulation-guided property checking based on a multi-valued AR-automata
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density
Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware
Assessing the Cost Effectiveness of Integrated Passives
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming
A low-cost BLE-based distance estimation, occupancy detection and counting system
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Scaling Deeper to Submicron: On-Line Testing to the Rescue
Lightweight code-based cryptography: QC-MDPC McEliece encryption on reconfigurable devices
Area-efficient error protection for caches
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking
A Power and Performance Model for Network-on-Chip Architectures
SOH-aware active cell balancing strategy for high power battery packs
Test front loading in early stages of automotive software development based on AUTOSAR
Correct-by-construction generation of device drivers based on RTL testbenches
Design Space Exploration for Dynamically Reconfigurable Architectures
Integrated circuit white space redistribution for temperature optimization
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
Interactive presentation: Radix 4 SRT division with quotient prediction and operand scaling
Specification and Design Considerations for Reliable Embedded Systems
APUF Faults: Impact, Testing, and Diagnosis
RVEBS: Event-Based Sampling on RISC-V
Adaptive multi-voltage scaling in wireless NoC for high performance low power applications
Dynamic thermal management in 3D multicore architectures
Late Breaking Results: A Data Compaction Strategy for Extensive Test Flows of Memories Embedded in Automotive SoCs
Efficient parameter variation sampling for architecture simulations
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories
Intelligent Hybrid Memory Scheduling Based on Page Pattern Recognition
Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash
Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection
Handling complex dependencies in system design
On Removing Multiple Redundancies in Combinational Circuits
GRAAL - A Development Framework for Embedded Graphics Accelerators
Towards new applications of multi-function logic: Image multi-filtering
Efficient Solution of Language Equations Using Partitioned Representations
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution
Interactive presentation: Reliability-aware system synthesis
A smaller and faster variant of RSM
Digital Ground Bounce Reduction by Phase Modulation of the Clock
A register-transfer-level fault simulator for permanent and transient faults in embedded processors
AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit
Fast Computation of Substrate Resistances in Large Circuits
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design
Reducing trace size in multimedia applications endurance tests
ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization
High-level simulation of substrate noise generation from large digital circuits with multiple supplies
Application performance improvement by exploiting process variability on FPGA devices
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
Digital test of ZigBee transmitters: Validation in industrial test environment
3D floorplanning with thermal vias
IoT 2 - the Internet of Tiny Things: Realizing mm-Scale Sensors through 3D Die Stacking
VerC3: A library for explicit state synthesis of concurrent systems
An ASIC design for real-time image processing in industrial applications
HW/SW Codesign of an Engine Management System
A synthesis-agnostic behavioral fault model for high gate-level fault coverage
An on Chip ADC Test Structure
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses
NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator
Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures
Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map
Guaranteed service virtual channel allocation in NoCs for run-time task scheduling
RAFS: A RAID-Aware File System to Reduce the Parity Update Overhead for SSD RAID
Reconfigurable threshold logic gates using optoelectronic capacitors
Adding Dual Variables to Algebraic Reasoning for Gate-Level Multiplier Verification
DVS for On-Chip Bus Designs Based on Timing Error Correction
Modeling and Refining Heterogeneous Systems With SystemC-AMS: Application to WSN
Scratchpad memory optimizations for digital signal processing applications
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors
Advancing CMOS with carbon electronics
Timing simulation of digital circuits with binary decision diagrams
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE
Butterfly Effect Attack: Tiny and Seemingly Unrelated Perturbations for Object Detection
System Level Analysis of the Bluetooth Standard
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience
WAVSTAN: waveform based variational static timing analysis
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
Online latency monitoring of time-sensitive event chains in safety-critical applications
Next Generation System Level Design Tools
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence
Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvesting
Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation
Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory
A scalable and high-density FPGA architecture with multi-level phase change memory
Library Compatible Ceff for Gate-Level Timing
Yield optimization for radio frequency receiver at system level
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data
Orchestration-Aware Optimization of ROS2 Communication Protocols
Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function
Autonomous Realization of Safety- and Time-Critical Embedded Artificial Intelligence
Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing
Genetic Algorithm-Driven IMC Mapping for CNNs Using Mixed Quantization and MLC FeFETs
A coupling area reduction technique applying ODC shifting
Two-Stream Neural Network for Post-Layout Waveform Prediction
Mission profile aware IC design - A case study
Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col
A Hardware/Software Codesign Case Study: Design of a Robot Arm Controller
Faster exploration of high level design alternatives using UML for better partitions
Assessing Soft Error Reliability in Vectorized Kernels: Vulnerability and Performance Trade-Offs on Arm and RISC-V ISAs
Scheduling of Soft Real-Time Systems for Context-Aware Applications
An Assembler Driven Verification Methodology (ADVM)
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures
Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy
Design methodology for PicoRadio networks
An FPGA Overlay for Efficient Real-Time Localization in 1/10th Scale Autonomous Vehicles
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Design For Testability Method for CML Digital Circuits
System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs
Design-Manufacturing Interface: Part I - Vision
Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Switch folding: network-on-chip routers with time-multiplexed output ports
Wireless LAN: Past, Present, and Future
Stay Away from Minimum Design-Rule Values
Run-time integrity monitoring of untrustworthy analog front-ends
E-pipeline: elastic hardware/software pipelines on a many-core fabric
Suspect set prediction in RTL bug hunting
Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing
Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs
Towards coverage closure: Using GoldMine assertions for generating design validation stimulus
Towards provably-secure performance locking
TxISC: Transactional File Processing in Computational SSDs
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing
An Automated Verification Framework for HalideIR-Based Compiler Transformations
AIME: Watermarking AI Models by Leveraging Errors
Quantization-Aware In-situ Training for Reliable and Accurate Edge AI
Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy
Extending JTAG for Testing Signal Integrity in SoCs
Cooptimization of interface hardware and software for I/O controllers
A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications
Robust non-preemptive hard real-time scheduling for clustered multicore platforms
Mach-Zehnder interferometer based design of all optical reversible binary adder
Automated synthesis of streaming C applications to process networks in hardware
Timing-Driven Global Placement With Hybrid Heuristics and Nadam-Based Net Weighting
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design
Role of design in multiple patterning: technology development, design enablement and process control
Better Late Than Never : Verification of Embedded Systems After Deployment
Architectural exploration and optimization for counter based hardware address generation
Dynamic skewed tree for fast memory integrity verification
Late Breaking Results: Physical Co-Design for Field-Coupled Nanocomputing
A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation
A flexible layered architecture for accurate digital baseband algorithm development and verification
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks
CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning
Quantitative analysis of transaction level models for the AMBA bus
EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction
Harmonizing Safety, Security and Performance Requirements in Embedded Systems
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes
galsC: A Language for Event-Driven Embedded Systems
Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems
Scheduling independent liveness analysis for register binding in high level synthesis
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors
Rack-scale disaggregated cloud data centers: The dReDBox project vision
A new parallel SystemC kernel leveraging manycore architectures
SafeTEE: Combining Safety and Security on ARM-based Microcontrollers
LFSR seed computation and reduction using SMT-based fault-chaining
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies
M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search
A methodology for automated design of embedded bit-flips detectors in post-silicon validation
A general design of stochastic circuit and its synthesis
Trade-offs in execution signature compression for reliable processor systems
On test generation by input cube avoidance
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning
Efficient compression and handling of current source model library waveforms
Arithmetic logic units with high error detection rates to counteract fault attacks
Biasing symbolic search by means of dynamic activity profiles
REH: Redesigning Extendible Hashing for Commercial Non-Volatile Memory
Automatic Assertion Generation from Natural Language Specifications Using Subtree Analysis
A Fine-Grained Soft Error Resilient Architecture under Power Considerations
The mobile society - chances and challenges for micro- and power electronics
Hardware security through chain assurance
HReRAM: a hybrid reconfigurable resistive random-access memory
SERD: A simulation framework for estimation of system level reliability degradation
Algorithms for Maximum Satisfiability using Unsatisfiable Cores
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
Towards fault tolerant parallel prefix adders in nanoelectronic systems
Realizing Quantum Algorithms on Real Quantum Computing Devices
Compact Macromodel for Lossy Coupled Transmission Lines
A Memory Architecture with 4-Address Configurations for Video Signal Processing
UPaRC - Ultra-fast power-aware reconfiguration controller
Area Fill Generation With Inherent Data Volume Reduction
Self-aware computing systems: From psychology to engineering
Multi resolution touch panel with built-in fingerprint sensing support
A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis
Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis
Quantifying error: Extending static timing analysis with probabilistic transitions
An energy efficient DRAM subsystem for 3D integrated SoCs
2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
Blender: A Traffic-Aware Container Placement for Containerized Data Centers
A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects
DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems
Fast cone-of-influence computation and estimation in problems with multiple properties
Physical vulnerabilities of Physically Unclonable Functions
A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing
Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow
Potentials of Chip-Package Co-Design for High-Speed Digital Applications
Effective verification of low-level software with nested interrupts
Synthesis of Fault-Tolerant Embedded Systems
Enhancing symbolic system synthesis through ASPmT with partial assignment evaluation
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
Synthesis of activation-parallel convolution structures for neuromorphic architectures
SODA: software defined FPGA based accelerators for big data
Modeling and simulation alternatives for the design of networked embedded systems
Approximate logic synthesis for error tolerant applications
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities
Algorithm-Hardware Co-Design for Efficient Brain-Inspired Hyperdimensional Learning on Edge
Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers
Probabilistic response time bound for CAN messages with arbitrary deadlines
Guidelines for model based systems engineering
Efficient Approximate Nearest Neighbor Search via Data-Adaptive Parameter Adjustment in Hierarchical Navigable Small Graphs
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation
Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution
The SELENE Deep Learning Acceleration Framework for Safety-related Applications
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Cross-layer floorplan optimization for silicon photonic NoCs in many-core systems
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation
GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM
A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscillators
Multi-core for mobile phones
Advancing source-level timing simulation using loop acceleration
Pipeline schedule synthesis for real-time streaming tasks with inter/intra-instance precedence constraints
Clock domain crossing fault model and coverage metric for validation of SoC design
vDARM: Dynamic Adaptive Resource Management for Virtualized Multiprocessor Systems
c2c-gem5: Full System Simulation of Cache-Coherent Chip-to-Chip Interconnects
Challenges in the design of automotive software
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction
WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP
A novel zero weight/activation-aware hardware architecture of convolutional neural network
Three Sidekicks to Support Spectre Countermeasures
Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process
Development of on board, highly flexible, Galileo signal generator ASIC
Formal probabilistic analysis of distributed resource management schemes in on-chip systems
A systematic IP and bus subsystem modeling for platform-based system design
An Encoding Technique for Low Power CMOS Implementations of Controllers
OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network Acceleration
Data management: limiter or accelerator for electronic design creativity
Efficient Hotspot Detection via Graph Neural Network
CARAT: Context-aware runtime adaptive task migration for multi core architectures
SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture
Transparent acceleration of program execution using reconfigurable hardware
LFSR-based test-data compression with self-stoppable seeds
How OEMs and suppliers can face the network integration challenges
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
An accurate Single Event Effect digital design flow for reliable system level design
PiPoMonitor: Mitigating Cross-core Cache Attacks Using the Auto-Cuckoo Filter
Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components
Communication-Computation co-Design of Decentralized Task Chain in CPS Applications
Verifying timing synchronization constraints in distributed embedded architectures
A New Effective Congestion Model in Floorplan Design
Virtual Compression through Test Vector Stitching for Scan Based Designs
GraphVine: Exploiting Multicast for Scalable Graph Analytics
Investigating the impact of NBTI on different power saving cache strategies
Reinforcement-Learning-Based Job-Shop Scheduling for Intelligent Intersection Management
ConZone: A Zoned Flash Storage Emulator for Consumer Devices
Fast isomorphism testing for a graph-based analog circuit synthesis framework
Efficient software-based fault tolerance approach on multicore platforms
Enabling area efficient RF ICs through monolithic 3D integration
Interactive presentation: An FPGA implementation of decision tree classification
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities
Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges
KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking
Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL
Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory
NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support
SMARTag: Error Correction in Cache Tag Array by Exploiting Address Locality
Tackling the bottleneck of delay tables in 3D ultrasound imaging
Automatic Topology Optimization for Analog Module Generators
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
Signal Prediction for Digital Circuits by Sigmoidal Approximations Using Neural Networks
A histogram method for analog-digital converters testing in time and spectral domain
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder
Connecting different worlds - Technology abstraction for reliability-aware design and Test
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
Implementing digital logic with sinusoidal supplies
Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning
Verifying Imprecisely Working Arithmetic Circuits
Fast Method to Include Parasitic Coupling in Circuit Simulations
Analytical heat transfer model for thermal through-silicon vias
Recovery-aware proactive TSV repair for electromigration in 3D ICs
Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters
Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis
Late Breaking Results: Iterative Design Automation for Train Control with Hybrid Train Detection
A unified model for co-simulation and co-synthesis of mixed hardware/software systems
Automatic technology migration of analog IC designs using generic cell libraries
A design-for-test structure for optimising analogue and mixed signal IC test
Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm