yusuke1997/dblp-id-title huggingface dataset:
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000
COAST: Correlated material assisted STT MRAMs for optimized read operation
Optimal technology selection for minimizing energy and variability in low voltage applications
Temperature-Aware Memory Mapping and Active Cooling of Neural Processing Units
Nanoscale CMOS circuit leakage power reduction by double-gate device
An approach to energy-error tradeoffs in approximate ripple carry adders
Thread-associative memory for multicore and multithreaded computing
Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model)
LPBP: low-power basis profile of the Java 2 Micro Edition
Analysis of discharge techniques for multiple battery systems
OS-level power minimization under tight performance constraints in general purpose systems
An Energy-Efficient High-Swing PAM-4 Voltage-Mode Transmitter
An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices
An estimation technique to guide low power resynthesis algorithms
Application-level prediction of battery dissipation
Innovations to extend CMOS nano-transistors to the limit
GC-eDRAM design using hybrid FinFET/NC-FinFET
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999
Partial bus-invert coding for power optimization of system level bus
An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing
EDeN: Enabling Low-Power CNN Inference on Edge Devices Using Prefetcher-assisted NVM Systems
Lower and upper bounds on the switching activity in scheduled data flow graphs
Energy-efficient computing using adaptive table lookup based on nonvolatile memories
Industry focus session on low-power design
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS
A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs
Causes and Fixes of Unexpected Drone Shutoffs
Multicasting based topology generation and core mapping for a power efficient networks-on-chip
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
Thermal analysis of 8-T SRAM for nano-scaled technologies
A game theoretic resource allocation for overall energy minimization in mobile cloud computing system
Analysis of crosstalk in NISQ devices and security implications in multi-programming regime
Multivoltage scheduling with voltage-partitioned variable storage
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells
Low-power sub-threshold design of secure physical unclonable functions
Analogue LSI RF switch and beamforming matrixes for communications satellites
A way-halting cache for low-energy high-performance systems
Always-On Sensing in Energy-Harvested Systems via Stochastic Intermittent Computing
Challenges and opportunities for low power FPGAs in nanometer technologies
A low-power crossroad switch architecture and its core placement for network-on-chip
An ARM perspective on addressing low-power energy-efficient SoC designs
Replacing global wires with an on-chip network: a power analysis
Jack Unit: An Area- and Energy-Efficient Multiply-Accumulate (MAC) Unit Supporting Diverse Data Formats
Low voltage tunnel transistor architecture and its viability for energy efficient logic applications
A 1.5V class AB output buffer
SOI CMOS as a mainstream low power technology: a critical assessment
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies
Quasi-static energy recovery logic and supply-clock generation circuits
Experience with a low power wireless mobile computing platform
±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme
A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system
Experimental measurement of a novel power gating structure with intermediate power saving mode
2.3 ppm/°c 40 nW MOSFET-only voltage reference
Low power signal processing architectures for network microsensors
Power prediction for intel XScale processors using performance monitoring unit events
Energy-efficient hybrid wakeup logic
A compact low-power eDRAM-based NoC buffer
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion
An Ultra-Efficient Memristor-Based DNN Framework with Structured Weight Pruning and Quantization Using ADMM
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory
ASCIB: adaptive selection of cache indexing bits for removing conflict misses
Content-driven adaptive computation offloading for energy-aware hybrid distributed video coding
How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions
Energy-efficient GPU design with reconfigurable in-package graphics memory
A systems approach to molecular electronics
Clock distribution using multiple voltages
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes
PEEC based parasitic modeling for power analysis on custom rotary rings
A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function
Power distribution in high-performance design
How Much Energy Can We Harvest Daily for Wearable Applications?
Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session)
Application adaptive energy efficient clustered architectures
ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers
A novel methodology for transistor-level power estimation
On-chip Integrated Voltage Regulators: Frontside, Backside, or Off-Chipƒ
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology
Design of a Correlation-Insensitive HFQ Stochastic Adder by Local Two-Phase Clocking
A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses
Post-layout leakage power minimization based on distributed sleep transistor insertion
Software energy estimation based on statistical characterization of intermediate compilation code
Fixing sensor-related energy bugs through automated sensing policy instrumentation
Online work maximization under a peak temperature constraint
Technology variability and uncertainty implications for power- efficient VLSI systems
Early evaluation techniques for low power binding
Low-power and high-performance technologies for mobile SoC in LTE era
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination
Accelerator-rich architectures: from single-chip to datacenters
A methodology for analysis and verification of power gated circuits with correlated results
A spatially-adaptive bus interface for low-switching communication (poster session)
Locality-driven architectural cache sub-banking for leakage energy reduction
Unifying carry-sum and signed-digital number representations for low power
A physical level study and optimization of CAM-based checkpointed register alias table
FPIA: Field-Programmable Ising Arrays with In-Memory Computing
Statistically optimized asynchronous barrel shifters for variable length codecs
Vibration-to-electric energy conversion
TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform
Synonymous address compaction for energy reduction in data TLB
A symbolic algorithm for low-power sequential synthesis
Energy Efficient Cache Design with Piezoelectric FETs
Holistic low power solutions for the new world
Power minimization of functional units partially guarded computation
Full chip leakage estimation considering power supply and temperature variations
A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs
Determining accuracy bounds for simulation-based switching activity estimation
WMixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces
Utilizing reverse short channel effect for optimal subthreshold circuit design
Low-voltage low-overhead asynchronous logic
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs
Compact models for estimating microprocessor frequency and power
Improved clock-gating through transparent pipelining
High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement
Implementation of a micro power 15-bit "floating-point" A/D converter
Design techniques for low power high bandwidth upconversion in CMOS
Switching activity estimation using limited depth reconvergent path analysis
FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation
Meta-Heuristic Optimization of Karatsuba Multiplier Designed ECC Processor
Hierarchical value cache encoding for off-chip data bus
Circuit-level techniques to control gate leakage for sub-100nm CMOS
A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology
A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting
A Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface for Speech Recognition
MultiScale: memory system DVFS with multiple memory controllers
A statistical model of cell-to-cell variation in Li-ion batteries for system-level design
Automatic source code specialization for energy reduction
Tutorial: Autonomy with Neuromorphic System
A low-leakage dynamic register file with unclocked wordline and sub-segmentation for improved bitline scalability
A Programmable Analog-to-Information Converter for Agile Biosensing
Comparison of class A amplifiers for low-power and low-voltage switched capacitor applications
A power optimization method considering glitch reduction by gate sizing
Information theoretic measures of energy consumption at register transfer level
JointNF: Enhancing DNN Performance through Adaptive N: M Pruning across both Weight and Activation
Advances in process technology & IBM collaborative ecosystem for leadership power performance SOC designs
A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs
A novel envelope edge detector for ultra-low power sensor wake-up circuit
A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOS
Comparison of high speed voltage-scaled conventional and adiabatic circuits
ASAP-FE: Energy-Efficient Feature Extraction Enabling Multi-Channel Keyword Spotting on Edge Processors
Energy efficient E-textile based portable keyboard
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis
TAP: token-based adaptive power gating
Resilient microprocessor design for high performance & energy efficiency
Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session)
Early detection of current hot spots in power gated designs
Adaptive front-end throttling for superscalar processors
System energy minimization via joint optimization of the DC-DC converter and the core
FTRANS: energy-efficient acceleration of transformers using FPGA
Reducing access energy of on-chip data memory considering active data bitwidth
Low power robust signal processing
Cache design trade-offs for power and performance optimization: a case study
Low Overhead Logic Locking for System-Level Security: A Design Space Modeling Approach
Joint Optimization of Cache Management and Graph Reordering for GCN Acceleration
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era
LowPASS: A Low power PIM-based accelerator with Speculative Scheme for SNNs
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
Better-Than-Worst-Case Design Methodology for a Compact Integrated Switched-Capacitor DC-DC Converter
TEA-DNN: the Quest for Time-Energy-Accuracy Co-optimized Deep Neural Networks
Simulation based architectural power estimation for PLA-based controllers
Power mapping and modeling of multi-core processors
Battery lifetime prediction for energy-aware computing
Voltage- and ABB-island optimization in high level synthesis
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW
Transaction-based adaptive dynamic voltage scaling for interactive applications
Reducing translation lookaside buffer active power
vGreen: a system for energy efficient computing in virtualized environments
An asynchronous matrix-vector multiplier for discrete cosine transform
Symbolic computation of logic implications for technology-dependent low-power synthesis
TapeCache: a high density, energy efficient cache based on domain wall memory
Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
A sub-1V dual-threshold domino circuit using product-of-sum logic
Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption
Frequency-domain supply current macro-model
Battery life challenges on future mobile notebook platforms
An optimization strategy for low energy and high performance for the on-chip interconnect signalling
All You Need is Unary: End-to-End Unary Bit-stream Processing in Hyperdimensional Computing
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP
Online tuning of Dynamic Power Management for efficient execution of interactive workloads
Ultra low voltage CMOS
A system-level energy minimization approach using datapath width optimization
Techniques for low energy software
Variation-driven device sizing for minimum energy sub-threshold circuits
Computing with stochastic processors: revisiting the correctness contract between software and hardware
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme
Energy-efficient dynamic circuit design in the presence of crosstalk noise
Power-efficient LDPC code decoder architecture
Pho$: A Case for Shared Optical Cache Hierarchies
Energy-efficient dot product computation using a switched analog circuit architecture
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS
Variable threshold CMOS (VTCMOS) in series connected circuits
A low-voltage CMOS multiplier for RF applications (poster session)
A 33μW 42 GOPS/W 64x64 pixel vision sensor with dynamic background subtraction for scene interpretation
Green at the micro-scale: towards self-powered embedded systems
Energy Harvesting-Supported Efficient Low-Power ML Processing with Adaptive Checkpointing and Intermittent Computing
Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM
Reducing power through compiler-directed barrier synchronization elimination
Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design
Cycle-accurate macro-models for RT-level power analysis
Enabling efficient fine-grained DRAM activations with interleaved I/O
Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances
Variable voltage scheduling
ER: elastic RESET for low power and long endurance MLC based phase change memory
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
Evaluating design tradeoffs in on-chip power management for CMPs
Energy priority scheduling for variable voltage processors
On-chip digital power supply control for system-on-chip applications
Dynamic voltage scheduling technique for low-power multimedia applications using buffers
A three-step power-gating turn-on technique for controlling ground bounce noise
A novel approach for variation aware power minimization during gate sizing
STT-MRAM-based Near-Memory Computing Architecture with Read Scheme and Dataflow Co-Design for High-Throughput and Energy-Efficiency
True single-phase energy-recovering logic for low-power, high-speed VLSI
Full chip power benefits with negative capacitance FETs
Software power optimization: analysis and optimization for energy-efficient software
A technique for low energy mapping and routing in network-on-chip architectures
ACAM: Approximate Computing Based on Adaptive Associative Memory with Online Learning
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
Reducing energy and delay using efficient victim caches
TEE-SFL: Time and Energy-efficient solution for addressing communication heterogeneity in Split Federated Learning Schemes
The petrol approach to high-level power estimation
Energy efficient sampling for event detection in wireless sensor networks
Enhancing the Energy Efficiency of Journaling File System via Exploiting Multi-Write Modes on MLC NVRAM
New clock-gating techniques for low-power flip-flops
Efficacy of Pruning in Ultra-Low Precision DNNs
Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session)
A study of the effectiveness of CPU consolidation in a virtualized multi-core server system
A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session)
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study
FSM--based power modeling of wireless protocols: the case of bluetooth
Power benefit study of monolithic 3D IC at the 7nm technology node
Eliminating energy of same-content-cell-columns of on-chip SRAM arrays
A micropower energy harvesting circuit with piezoelectric transformer-based ultra-low voltage start-up
Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems
Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time
A fine-grained many V T design methodology for ultra low voltage operations
SmartSaver: turning flash drive into a disk energy saver for mobile computers
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation
Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories
Strained-si devices and circuits for low-power applications
Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators
Reducing cache energy consumption by tag encoding in embedded processors
ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, Massachusetts, August 10-12, 2020
Opportunities in system power management for high performance mixed signal platforms
Intelligent frame refresh for energy-aware display subsystems in mobile devices
Energy delay analysis of partial product reduction methods for parallel multiplier implementation
A comparative study of MOS VCOs for low voltage high performance operation
Dynamic reconfiguration of photovoltaic energy harvesting system in hybrid electric vehicles
High performance DSPs - what's hot and what's not?
Understanding nanoscale conductors
A hybrid display frame buffer architecture for energy efficient display subsystems
Power analysis techniques for SoC with improved wiring models
Energy-Harvesting-Aware Adaptive Inference of Deep Neural Networks in Embedded Systems
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element
Two dimensional codes for low power
Dynamic thermal management using thin-film thermoelectric cooling
Power Map Characterization and Modeling for Commercial CPU/GPUs Considering Temperature Dependence
A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Efficient Precision-Scalable Hardware for Microscaling (MX) Processing in Robotics Learning
Exploration of Low-Power Flexible Stress Monitoring Classifiers for Conformal Wearables
Clock network design for ultra-low power applications
Signoff power methodology for contactless smartcards
A critical analysis of application-adaptive multiple clock processors
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs
Mixed-swing quadrail for low power dual-rail domino logic
Substituting associative load queue with simple hash tables in out-of-order microprocessors
DIAN: Differentiable Accelerator-Network Co-Search Towards Maximal DNN Efficiency
Statistical information processing: Computing for the nanoscale era
Architecting large-scale SRAM arrays with monolithic 3D integration
High-efficiency crossbar switches using capacitively coupled signaling
Analysis and Design of Energy Efficient Time Domain Signal Processing
RMAC: Runtime Configurable Floating Point Multiplier for Approximate Computing
Across the Stack Opportunities for Deep Learning Acceleration
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs
Multi-Complexity-Loss DNAS for Energy-Efficient and Memory-Constrained Deep Neural Networks
Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS
Noise-aware power optimization for on-chip interconnect
An architectural solution for the inductive noise problem due to clock-gating
Energy-aware memory allocation in heterogeneous non-volatile memory systems
Energy optimality and variability in subthreshold design
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing
Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise
GPUVolt: modeling and characterizing voltage noise in GPU architectures
Thermal response to DVFS: analysis with an Intel Pentium M
Optimal power and noise allocation for analog and digital sections of a low power radio receiver
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS
An environmental energy harvesting framework for sensor networks
Estimation of maximum power supply noise for deep sub-micron designs
Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2018, Seattle, WA, USA, July 23-25, 2018
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
Fabrication and performance of mesa interconnect
Space-efficient Graph Data Placement to Save Energy of ReRAM Crossbar
Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI
Enhancing phase change memory lifetime through fine-grained current regulation and voltage upscaling
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction
3D IC Architecture Evaluation and Optimization with Digital Compute-in-Memory Designs
The simulation and evaluation of dynamic voltage scaling algorithms
Ultra-low power digital subthreshold logic circuits
Low power mixed analog-digital signal processing
Quantifying the impact of variability on the energy efficiency for a next-generation ultra-green supercomputer
BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories
Towards energy-aware software-based fault tolerance in real-time systems
Heterogeneous integration of nano enabling devices for 3D ICs
Simultaneous Vt selection and assignment for leakage optimization
Re-encoding for low power state assignment of FSMs
Workload-adaptive process tuning strategy for power-efficient multi-core processors