yusuke1997/dblp-id-title huggingface dataset:
An 88% Efficiency 2.4μW to 15.6μW Triboelectric Nanogenerator Energy Harvesting System Based on a Single-Comparator Control Algorithm
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer
Subthreshold voltage reference with nwell/psub diode leakage compensation for low-power high-temperature systems
Wind speed forecasting using hybrid ANN-Kalman Filter techniques
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS
A 16-bit SAR ADC with Capacitor Dielectric Relaxation Effect Canceler in a 22-nm Microcontroller for Multi-Input Channel Applications
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
A Cross-Coupled Hybrid SC Converter with Extended VCR Range and Intrinsic Loss Balance Achieving 90% Average Efficiency with 1.5% Variation Over Full Li-ion Battery Input Range and 0.95A/mm 2 Peak Current Density
Piezoresistive 6-MNA coated microcantilevers with signal conditioning circuits for electronic nose
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment
T/R-Switch Composed of 3 High-Voltage MOSFETs with 12.1 µW Consumption that can Perform Per-channel TX to RX Self-Loopback AC Tests for 3D Ultrasound Imaging with 3072-channel Transceiver
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process
A 12-V charge pump-based square wave driver in 65-nm CMOS technology
A Unified Microrobotic Visual-Perception Processor with 62.2-FPS/mm 2 and 103-uJ/frame Navigation in 28nm
An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Nodes
ANVMP: A 28nm 52.6 μW 1.25pJ/SOP Asynchronous Non- Volatile-Memory-based Computing-In-Memory Neuromorphic Processor for Edge-Al Applications
CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS
An EEG-NIRS ear-module SoC for wearable drowsiness monitoring system
Photovoltaic-Assisted Self-Vth-Cancellation CMOS RF Rectifier for Wide Power Range Operation
A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS
A 74.0 dB-SNDR 175.4 dB-FoM Pipelined-SAR ADC Using a Cyclically Charged Floating Inverter Amplifier
A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA
A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications
An 83.6dB-SNDR 101.6dB-SFDR 4 th -Order Noise-Shaping SAR with 2 nd -Order Nonlinearity Error Shaping
A 0.91-pJ/b 20.8-32-Gb/s Reference-Less Sub-Baud-Rate CDR Circuit
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues
A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique
A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery
A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems
Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics
A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update
A 100-pA Adaptive-FOCV MPPT Circuit with >99.6% Tracking Efficiency for Indoor Light Energy Harvesting
A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic
Clustering the behaviour of electricity consumption
A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications
A Compact High Efficiency and High Power Front-end Module for GSM/EDGE/TD-SCDMA/TD-LTE Applications in 0.13um CMOS
A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS
Injection-locked clock receiver for monolithic optical link in 45nm SOI
An 890 μW Multichannel Injection-Locked OOK Transmitter with 23% Global Efficiency and 22 pJ/bit Energy Efficiency
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU
An ultra-low-cost Bluetooth SOC in 0.11-μm CMOS
A 10b Ternary SAR ADC with decision time quantization based redundancy
An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision
A low power W-band PLL with 17-mW in 65-nm CMOS technology
A 18.9-nA standby current comparator with adaptive bias current generator
An Instant-Setup On-Delay Compensation Scheme Based on Phase Detection for Series-Resonant Wireless Power Receiver with Up-to-4.41% Efficiency Enhancement
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines
A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems
Current-limited voltage control strategies for multiple-input buck converters applied in renewable energy hybrid systems
A micropower biomedical signal processor for mobile healthcare applications
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference
Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate
CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering
A 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology
A 950-pW, 39-pJ/Conversion Leakage-Based Temperature-to-Digital Converter With 43mk Resolution
A 67 GHz dual injection quadrature VCO with -182.9 dBc/Hz FOM in 90-nm CMOS
A Single/Dual-Output Switched-Capacitor DC-DC Converter with Geometrically Arranged Soft VCR Transitions
A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL
A 20-GHz Ultra-Low-Power LNA Using gm-Boosted and Current-Reuse Techniques in 65-nm CMOS for Satellite Communication Terminals
A 0.033-mm 2 21.5-aF Resolution Continuous-Time Delta-Sigma Capacitance-to-Digital Converter with Parasitic Capacitance Immunity up to 480pF
25 fJ/bit, 5Mb/s, 0.3 V true random number generator with capacitively-coupled chaos system and dual-edge sampling scheme
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process
A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS
A time-domain architecture and design method of high speed A-to-D converters with standard cells
AµProcessor Layer for mm-Scale Die-Stacked Sensing Platforms Featuring Ultra-Low Power Sleep Mode at 125°C
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition
A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique
Design of SRM DSP-based control system
A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication
AI Drives Domain Specific Processors
A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS
A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots
A 0.6V Fully-Integrated BLE Transmitter in 65nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F2 PA Achieving 25% System Efficiency at 0dBm
Optimized power trading of a PEV charging station with energy storage system
On overcoming the limitations of single-ended signaling for graphics memory interfaces
A fully-integrated 860-GHz CMOS terahertz sensor
A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation
A Conversion-Ratio-Insensitive High Efficiency Soft-Charging-Based SC DC-DC Boost Converter for Energy Harvesting in Miniature Sensor Systems
1.68μJ/signature-generation 256-bit ECDSA over GF(p) signature generator for IoT devices
A 12b 3 GS/s Passive T/H Assisted Time-Interleaved Pipelined SAR ADC with Metastability Reduction Technique and Dynamic-Bias RA
IEEE Asian Solid-State Circuits Conference, A-SSCC 2020, Virtual Event, Japan, November 9-11, 2020
Voice Activity Detection with >83% Accuracy under SNR down to -3dB at $1.19\mu \mathrm{W}$ and 0.07mm 2 in 40nm
A 92.7%-Efficiency 6.78-MHz Dual-Output Energy-Resuscitating Resonant Regulating Rectifier for Wirelessly Powered Systems
Fault-tolerant topology of a grid-connected PV inverter coupled by a Scott transformer
A TFT-Based Flexible PPG Acquisition Circuit in a 3-μm LTPS Process for Packaging-Free Smart Ring Applications
A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuit
A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques
A programmable RFSoC in 16nm FinFET technology for wideband communications
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications
A Computationally Efficient, Hardware Re-configurable Architecture for QRS Detection and ECG authentication
Configurable data exchange tool design based on tagged data structure
IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016
A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture
An area-efficient amplifier-less digitally-controlled li-ion battery charger in 0.35μm CMOS
A 0.06-mm 2 double-sampling single-OTA 2nd-order ΔΣ modulator in 0.18-μm CMOS technology
A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines
A 13.56 MHz, 162 mW magnetically coupled digital rectifier with 94% VCR, 96% PCE over 50-to-5k Ω load range, and embedded 80 kbps DBPSK demodulator for biomedical applications
Electric vehicle charging profile prediction for efficient energy management in buildings
Flicker noise upconversion mechanisms in K-band CMOS VCOs
A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS
An integrated 8A pulsed VCSEL array driver under 12V supply with built-in pulse monitor and automatic peak current control for direct time-of-flight applications
A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
Development and evaluation of DC-DC converter for isolated PV power supply system with EV
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW
A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices
An 83% peak efficiency and 1.07W/mm 2 power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zero th -Order Control
IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm
A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS
Site selection procedures for tidal in-stream energy in the Philippines: A Preliminary Study
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages
Bee colony optimization of battery capacity and placement for mitigation of voltage rise by P V in radial distribution network
A 0.000261 mm 2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS
A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key
An 80-dB Dynamic Range Hybrid Pulse-Phase Analog Front-End Circuit Cooperating With a Low-Resolution TDC for LiDAR
An efficient and stable power management circuit with high output energy for wireless powering capsule endoscopy
A 37.5-45. lGHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOS
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
A 196.2 dBc/Hz FOMT 16.8-to-21.6 GHz Class-F23 VCO with Transformer-Based Optimal Q-factor Tank in 65-nm CMOS
Internet of Things: Evolution towards a hyper-connected society
A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm 2 in 32 nm SOI CMOS
An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators
A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry
A Wide Current Range and Fast Transient Flipped Voltage Follower Based Low Dropout Regulator
RMMIC: A 40 μW Reconfigurable Multi-modal Multi-channel Interface Circuit System for Bio-signals Monitoring
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications
Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS
A 5× OSR 1MHz-BW 81dB-SNDR 5 th -Order Noise-Shaping SAR ADC with Zero-Optimized 3 rd -Order Integrator
Transient stability assessment of power system with large amount of wind power penetration: The Danish case study
A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique
8.6fJ/step VCO-Based CT 2 nd -Order $\Delta\Sigma$ ADC
A 28-GHz Compact SPDT Switch Using LC-Based Spiral Transmission Lines in 65-nm CMOS
A -60 to 145 °C, 216 fJ·K2 Energy-Efficient MOS-Based Temperature Sensor Achieving 71.8 mK Resolution
An Area-Efficient PVT-Dependent Adaptive Assist Termination Technique with SNM Detector for High Density SRAM
A Single-Inductor Triple-Output Converter with an Automatic Detection of DC or AC Energy Harvesting Source for Supplying 93% Efficiency and 0.05mV/mA Cross Regulation to Wearable Electronics
A 684Mbps 57mW joint QR decomposition and MIMO processor for 4×4 MIMO-OFDM systems
A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout
54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique
The potential for electricity generation from rice-husk in Vietnam
A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications
A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems
Evaluation of energy storage system to support Danish island of Bornholm power grid
A Bimodal (NRZ/PAM-4) ISI Tolerant Timing Recovery with Adaptive DDJ Equalization
A 83% peak efficiency 1.65 V to 11.4V dynamic voltage scaling supply for electrical stimulation applications in standard 0.18μm CMOS process
A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC
A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration
A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS
An asynchronous mixed-mode neuro-fuzzy controller for energy efficient machine intelligence SoC
A 23mW/lane 1.2-6.8Gb/s multi-standard transceiver in 28nm CMOS
IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011
An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW
Memory Centric Computing, The Foundation of the Next Smart Society
An All-digital, 3.68 mV/LSB Voltage Sensor based Droop Prediction and Fast Mitigation System in 28nm CMOS
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data
A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS
A low energy crystal-less double-FSK transceiver for wireless body-area-network
A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers
A Fully Integrated 4: 1 DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators Achieving 74.5% Peak Efficiency and 0.78W/mm² Peak Power Density
A 0.6V to 1.6V, 46μW voltage and temperature independent 48 MHz pulsed LC oscillator for RFID tags
NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator
A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetry
A 16-43 GHz low-noise amplifer with 2.5-4.0 dB noise figure
A 33.6 FPS Embedding based Real-time Neural Rendering Accelerator with Switchable Computation Skipping Architecture on Edge Device
A probabilistic operation method of power systems with WFs considering voltage and power flow constraints
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices
35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors
A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization
On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system
A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technology
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation
Load frequency control using a NAS battery system controlled by a Kaiman filter
An Asynchronous Energy-Efficient CNN Accelerator with Reconfigurable Architecture
Quad Full-HD transform engine for dual-standard low-power video coding
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications
An 8.7 μJ/class. FFT accelerator and DNN-based configurable SoC for Multi-Class Chronic Neurological Disorder Detection
An 82.1%-Power-Efficiency Single-Inductor Triple-Source Quad-Mode Energy Harvesting Interface with Automatic Source Selection and Reversely Polarized Energy Recycling
A 0.7mW 13b temperature-stable MASH ΔΣ TDC with delay-line assisted calibration
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems
A 64-channel SPAD-based LiDAR sensor with Compact Coincidence Detection Circuit and Inter-frame Correlation-based Nonlinear Partial Histogram Builder
A 0.036mm 2 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET
A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration
A 8-channel Rectifier-Free SECE Circuit with 15nA/ch Quescient Current and 580% Efficiency Improvement for Ambient Vibration Energy Harvesting with Broadband MEMS PET Array
Recognition and simulation of electromagnetic transients in power systems of Southern Vietnam
A Single-Channel 3.1GS/s 45dB SNDR Pipelined ADC using Amplify-and-Select Structure in 28nm CMOS
A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain
A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 μW ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer
Multi agent system based wide area protection against cascading events
A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection
A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process
A 28mn FD-SOI 4KB Radiation-hardened 12T SRAM Macro with 0.6 ~ 1V Wide Dynamic Voltage Scaling for Space Applications
A Passive IoT Bidirectional Tag Demonstrating 95m Downlink through Antenna-Array-Based Power-Data-Fusion Technique
A low-power calibration-free fractional-N digital PLL with high linear phase interpolator
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS
A 56Gbps ADC/DAC-Based Jitter-Robust Multicarrier Transceiver with RX MIMO-DSP for > 40dB Loss Channel
IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019
An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection
IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014
A high stability DC-DC Boost Converter with Ripple Current Control and capacitor-free LDOs for AMOLED display
56-Level programmable voltage detector in steps of 50mV for battery management
A 0.28V 80.9μW Transformer-Based DCO with 80kHz 1/f 3 corner and 192.6dBc/Hz FoM
A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS Technology
Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF
A 22T Static Contention-free Conjoined Master-Slave Flip-flop for Low-Voltage, Low-Power, and Low-Area Applications
A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing
A MOS current-mode boost DC-DC converter with the duty-ratio-independent frequency characteristics
A CMOS broadband precise programmable gain amplifier with bandwidth extension technique
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS
A 320MHz BW NS TD-ADC Assisted C/DT Hybrid Pipelined ADC with SAB-based Residue Amplifying Filter
Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS
CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution
Highly linear TIA for SAW-less FDD receivers
A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS
A matrix converter based Inductive Power Transfer system
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator