yusuke1997/dblp-id-title huggingface dataset:
Primitive Concept Identification In A Given Set Of Wafer Maps
A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging
Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS Technology
A low-noise high-efficient buck converter with noise-shaping technique
A monolithic 1.85GHz 2-stage sige power amplifier with envelope tracking for improved linear power and efficiency
Multi-processor debug in SoC and processor designs
Reconfigurable Database Processor for Query Acceleration on FPGA
Design of a pipelined clos network with late release scheme
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property
Adaptive granularity and coordinated management for timely prefetching in multi-core systems
A high-performance current-mode DC-DC buck converter with adaptive clock control technique
A power-efficient circuit design of feed-forward FxLMS active noise cancellation for in-ear headphones
A pliable and batteryless real-time ECG monitoring system-in-a-patch
Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs
Design and implementation of an optical OFDM baseband receiver in FPGA
ASIC synthesis using Architecture Description Language
Hardware Trojan Detection at Run-time using Machine-Learning Techniques
An Imu-Based Wearable Ring For On-Surface Handwriting Recognition
Efficient test and repair architectures for 3D TSV-based random access memories
Building best in class System solutions: Enabled by collaboration
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3
User- Friendly Compact Model of Magnetic Tunnel Junctions for Circuit Simulation Based on Switching Probability
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout
Lifetime-aware LRU promotion policy for last-level cache
ONNC-Based Software Development Platform for Configurable NVDLA Designs
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver
An Ising model mapping to solve rectangle packing problem
Test strategies for the clock and power distribution networks in a multi-die IC
Energy-harvesting microsystems
Emerging technologies and concepts for 5G applications - A. making additive manufactured ceramic microwave filters ready for 5G
A novel design methodology for hybrid process 3D-IC
Industry 4.0: Open as well as closed
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform
Advances in computing
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism
A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing
Self-Heating Effects from Transistors to Gates
Disruptive technologies for the future generation smart systems
Electroceuticals - Replacing drugs by devices enabled through advanced VLSI technologies
On designing two-dimensional scan architecture for test chips
Ultraflexible Amplification Circuits for Imperceptible Brain Monitoring System
High-level low-power system design optimization
Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation method
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study
Shutdown mode implementation for Boost and Inverting Buck-Boost converter
Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography
Design-technology innovations enabling differentiation in emerging applications
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages
MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router
Embedded Memory: The Future of Emerging Memories
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators
Event-driven read-out circuits for energy-efficient sensor-SoC's
Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs
Highly efficient 5G linear power amplifiers (PA) design challenges
A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode
Thermal challenges to building reliable embedded systems
New Memory Technology, Design and Architecture Co-Optimization to Enable Future System Needs
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V
Improving IJTAG Test Efficiency and Security
Bridging the Physical and Digital Worlds in Data-Driven Systems
A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications
Circuit Routing Using Monte Carlo Tree Search and Deep Reinforcement Learning
A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism
A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator
Identify problematic layout patterns through volume diagnosis
Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems
Programming Systems for Parallelizing VLSI CAD and Beyond
MORAS: An energy-scalable system using adaptive voltage scaling
Computer architecture for die stacking
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications
Silicon Process Impact on 5G NR mmWave Front End Design and Performance
Power integrity optimization on USB power distribution network for EMI reduction
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications
A configurable bus-tracer for error reproduction in post-silicon validation
A novel DFT architecture for 3DIC test, diagnosis and repair
High speed DDR2/3 PHY and dual CPU core design for 28nm SoC
A Current-Mode Differential Sensing CMOS Imager for Optical Linear Encoder
Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems
Security Done Right: Start at the Heart of the SoC
Routing-efficient implementation of an internal-response-based BIST architecture
BlueBox: A Complete Recorder for Code-Blue Events in Hospitals
A background calibration technique for fully dynamic flash ADCs
A current feedback instrumentation amplifier with chopping and dynamic element matching techniques and employing the current-reuse technique in input/feedback stages
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects
A 1-V 60 GHz CMOS low noise amplifier with low loss microstrip lines
Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model
Current-mirror miller compensation: An improved frequency compensation technique for two-stage amplifiers
Excursion Prevention Strategyto Increase Chip Performance by Photomask Tuning
A 45µW, 9.5MHz current-reused RC oscillator using a swing-boosting technique
Extended abstract: Industrial performance to serve economical rebound
Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems
Technology and design challenges for smartphone SOCs
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017
Advanced CMOS reliability challenges
Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs
Full-custom all-digital phase locked loop for clock generation
Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS
Roadway to innovation
Creating options for 3D-SIC testing
Analog front-end amplifier for ECG applications with feed-forward EOS cancellation
Jitter error cancellation technique in digital domain for ADC
An FPGA implementation of high-throughput key-value store using Bloom filter
Reducing aging on scratchpad memory using temporal- and FSM-based power management
Composite Fault Diagnosis of Rotating Machinery With Collaborative Learning
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies
A Compact Thermal Sensor with Duty-Cycle Modulation on 1200 µm 2 in 7nm FinFET
Heterogeneous SoCs
A configurable wavelet processor for biomedical applications
Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systems
Large set construction of user uplink ranging codes for M2M applications
3-D centric technology and realization with TSV
VLSI CAD for emerging nanolithography
Journey to 5G
A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS
Intelligent Document Recognition on Financial Process Automation
Customization of a Deep Learning Accelerator
A 363-µW/fps power-aware green multimedia processor for mobile applications
ITRI mmWave radio access technology development
R&D Activities for 5G Radio Access Technologies Using SHF Bands and Co-Creation of New Services Using 5G
Design for reliability for low power digital circuits
A Cycle Count Accurate TLM bus modeling approach
Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator
Wireless power link design using silicon-embedded inductors for brain-machine interface
Chip Performance Prediction Using Machine Learning Techniques
A hardware in the loop design methodology for FPGA system and its application to complex functions
Design validation on multiple-core CPU supported low power states using platform based infrared emission microscopy (PIREM) technique
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips
Cross-layer dynamic prefetching allocation strategies for high-performance multicores
High-Throughput 64K-point FFT Processor for THz Imaging Radar System
A solar powered single-inductor dual-output (SIDO) DC-DC boost for power management unit system with high light-load efficiency
Virtual Reality: The new era of the future world
Deep fusion of heterogeneous sensor modalities for the advancements of ADAS to autonomous vehicles
High-throughput Von Neumann post-processing for random number generator
VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015
Video Dehazing Hardware Accelerator Design based on Dark Channel Prior with Sky Preservation
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System
A Digital Phase-Locked Loop With Background Supply Noise Cancellation
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process
Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm
ATPG and Test Compression for Probabilistic Circuits
VLSI implementations of stereo matching using Dynamic Programming
Timing-aware clock gating of pulsed-latch circuits for low power design
Process Design Kit and Design Automation for Flexible Hybrid Electronics
Digital intelligence and chip design
Universal architecture prototype for patient-centric medical environment
A time delay integration CMOS image sensor with online deblurring algorithm
The applications of power integrated circuits with energy saving
Technology Challenges to IC Industry for Next Decade
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction
A CMOS 0.85-V 15.8-nW Current and Voltage Reference without Resistors
Unified technology optimization platform using integrated analysis (UTOPIA) for holistic pathfinding DTCO of advanced transistors
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array
Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design
A nonlinear optimization methodology for resistor matching in analog integrated circuits
A novel processor design flow using processor description language applied to a vector coprocessor
Techology trend of edge AI
LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems
Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units
A fast ECG diagnosis by using spectral artificial neural network (SANN) approach
Computing-In-Memory a Processing-In-Sensor Techniques for Low-Power Edge Devices
A survey of technical trend of ADAS and autonomous driving
BRAM efficient multi-ported memory on FPGA
Constraints and design approaches in analog ICs forlmplantable medical devices
Semiconductor Evolution for Chip and System Design- From 2D Scaling to 3D Heterogeneous Integration
Case study of yield learning through in-house flow of volume diagnosis
A cuffless wearable system for real-time cutaneous pressure monitoring with cloud computing assistance
Highly automated and efficient simulation environment with UVM
Smart feature detection device for cloud based video recognition system
Mobile/embedded DNN and AI SoCs
3D IC test scheduling using simulated annealing
Co-designed systems for deep learning hardware accelerators
Automatic Floorplanning for AI SoCs
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model
An FPGA-based test platform for analyzing data retention time distribution of DRAMs
Design of a High-Throughput and Area-Efficient Ultra-Long FFT Processor
Design of divider circuit for electrochemical impedance spectroscopy measurement system
A hybrid built-in self-test scheme for DRAMs
A distributed thread scheduler for dynamic multithreading on throughput processors
End-to-end hardware accelerator for deep convolutional neural network
Efficient techniques for canceling transceiver noise
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications
A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC
Design of a real-time software-based GPS baseband receiver using GPU acceleration
A 0.9-V 2.36-GHz MedRadio-band 10-Mbps low-power OOK modulator for neural implants
Triangle-based process hotspot classification with dummification in EUVL
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine
Circuit design in nano-scale CMOS technologies
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems
A low power synthesis flow for multi-rate systems
Embedded non-volatile memory system as an enabler of smarter world
A TinyMLaaS Ecosystem for Machine Learning in IoT: Overview and Research Challenges
On the futility of thermal through-silicon-vias
Machine learning further improving place and route QoR
Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier
GaN-based digital transmitter architectures for 5G
Beyond structural test, the rising need for system-level test
Failure Root Cause Analysis Automation on Functional Simulation Regressions
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array
Will reliability limit Moore's law?
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering
Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks
A novel on-chip current-sensing structure for current-mode DC-DC converter
The sum of the parts: Overcoming leading edge design challenges by working in partnership
Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs
A digital peak current delay compensation for primary-side regulation flyback adapter
Powerful smartphone solutions unleashing new technology innovations
Bias adapted operation of CMOS PA for handset application
A fast and accurate instruction-oriented processor simulation approach
String Pattern Matching in Polynomial Time
A Fully Abstract Trace Model for Dataflow Networks
On the Complexity of the Circularity Test for Attribute Grammars
Precise Interprocedural Dataflow Analysis via Graph Reachability
Efficient deductive methods for program analysis
Incremental Evaluation for Attribute Grammars with Application to Syntax-Directed Editors
Conference Record of POPL'95: 22nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, San Francisco, California, USA, January 23-25, 1995
JFlow: Practical Mostly-Static Information Flow Control
Fabular: regression formulas as probabilistic programming
A relational model of types-and-effects in higher-order concurrent separation logic
Subjective auxiliary state for coarse-grained concurrency
Manticore: a heterogeneous parallel language
Coding by Everyone, Every Day
Proceedings of the POPL 2011 Workshop on Declarative Aspects of Multicore Programming, DAMP 2011, Austin, TX, USA, January 23, 2011
Proceedings of the 37th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2010, Madrid, Spain, January 17-23, 2010
Fully Abstract Translations between Functional Languages
Automating Proofs of the Absence of Common Runtime Errors
Recovering C++ Objects From Binaries Using Inter-Procedural Data-Flow Analysis
Unboundedness and downward closures of higher-order pushdown automata
Formal verification of compilers and static analyzers
The geometry of types
Modular session types for distributed object-oriented programming
A Semantics for ML Concurrency Primitives
A Metalanguage for Interactive Proof in LCF
A program logic for concurrent objects under fair scheduling
A logic for information flow in object-oriented programs
Static and dynamic semantics of NoSQL languages
Cost semantics for space usage in a parallel language
A Type Declaration and Inference System for Smalltalk
Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding
A typed store-passing translation for general references
Dependence Graphs and Compiler Optimizations
The power of parameterization in coinductive proof
Symbolic optimization with SMT solvers
Mutatis mutandis: safe and predictable dynamic software updating
Proceedings of the 31st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2004, Venice, Italy, January 14-16, 2004
Views: compositional reasoning for concurrent programs
A proposal for parallel self-adjusting computation
Trust and Partial Typing in Open Systems of Mobile Agents
Type-base flow analysis: from polymorphic subtyping to CFL-reachability
Path-Sensitive Value-Flow Analysis
Incompleteness-aware programming with RDF data
From SOS Rules to Proof Principles: An Operational Metatheory for Functional Languages
A Type System for Smalltalk
Stop Losing Sleep Over Incomplete Data Type Specifications
Formal prototyping in early stages of protocol design
Program Schemas with Concurrency: Execution Time and Hangups
Polymorphic Unification and ML Typing
Recursively Defined Data Types
Playing in the grey area of proofs
Aggregate Structure Identification and Its Application to Program Analysis
PolyCheck: dynamic verification of iteration space transformations on affine programs
Programming Aspects of VLSI
From Polyvariant Flow Information to Intersection and Union Types
Common Compiler Optimisations are Invalid in the C11 Memory Model and what we can do about it
Engineering with logic: HOL specification and symbolic-evaluation testing for TCP implementations
Imperative self-adjusting computation
Imperative Functional Programming
Recursive proofs for inductive tree data-structures
Type Elaboration and Subtype Completion for Java Bytecode
A Unified Approach to Global Program Optimization
Environmental bisimulations for probabilistic higher-order languages
Retargetable High-Level Alias Analysis
Declarative coordination in a multicore environment: the tyranny of streams
Lower Bounds on Type Inference with Subtypes
Principles of Proving Programs Correct in Gypsy
A Description of Path Expressions by Petri Nets
Hypercollecting semantics and its application to static analysis of information flow
From sequential programs to multi-tier applications by program transformation
A Generic Account of Continuation-Passing Styles
Elimination of Single Productions from LR Parsers in Conjunction with the Use of Default Reductions
Completion of a Set of Rules Modulo a Set of Equations
Complexity verification using guided theorem enumeration
Dependent types and program equivalence
Node Listings Applied to Data Flow Analysis
A Mark-and-Sweep Collector for C++
Uncovering Principles of Novice Programming
Proving correctness of compiler optimizations by temporal logic
Meta-theory à la carte
Relational cost analysis
Formalizing the LLVM intermediate representation for verified program transformations
Programming Language Constructs for Which it is Impossible to Obtain "Good" Hoare-Like Axiom Systems
Hybrid type checking
Deciding equivalence with sums and the empty type
Combinators for bi-directional tree transformations: a linguistic approach to the view update problem
Relevant Context Inference
Temporal Abstract Interpretation
Bisimulation Can't Be Traced
Pure versus Impure LISP
Call Forwarding: A Simple Interprocedural Optimization Technique for Dynamically Typed Languages
Analyzing program dependencies for malware detection
A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code
Accelerating Haskell array codes with multicore GPUs
On the Expressive Power of Query Languages for Relational Databases
Randomized accuracy-aware program transformations for efficient approximate computations
A parallel ASP instantiator based on DLV
Synchronous Schemes and Their Decision Problems
Printing floating-point numbers: a faster, always correct method
An abstract Monte-Carlo method for the analysis of probabilistic programs
Conference Record of the Thirteenth Annual ACM Symposium on Principles of Programming Languages, St. Petersburg Beach, Florida, USA, January 1986
Edit lenses
On the Synthesis of a Reactive Module
Reasoning about Recursively Defined Data Structures
Modular verification of a non-blocking stack
The complexity of interaction
Combinations of Abstract Domains for Logic Programming
Editing by Example
Modules, abstract types, and distributed versioning
Canonicity for 2-dimensional type theory
Partitioning Dataflow Analyses Using Types
Unification Factoring for Efficient Execution of Logic Programs
Automating string processing in spreadsheets using input-output examples
Conditional must not aliasing for static race detection
Bounding space usage of conservative garbage collectors
Programming with binders and indexed data-types
SAC: off-the-shelf support for data-parallelism on multicores
Context logic and tree update
Expressive modular fine-grained concurrency specification
Pattern Driven Lazy Reduction: A Unifying Evaluation Mechanism for Functional and Logic Programs
Deciding choreography realizability
The Modula-3 Type System
Conference Record of the Fourteenth Annual ACM Symposium on Principles of Programming Languages, Munich, Germany, January 21-23, 1987
Generic Polymorphism
Enforcing Trace Properties by Program Transformation
Principal Signatures for Higher-Order Program Modules
A Type System for Dynamic Web Documents
Subtyping Recursive Types
Abstract conflict driven learning
Variance analyses from invariance analyses
Abstraction-guided synthesis of synchronization
Complete instantiation-based interpolation
A sound and complete abstraction for reasoning about parallel prefix sums
Specifying C++ concepts