yusuke1997/dblp-id-title huggingface dataset:
In-depth! The Silicon Valley Sentinel-Observer's public affairs NetTV program presents: toxic knowledge
Taking the byte out of cookies: privacy, consent, and the Web
The campaign for an ethical Internet
Using an alternative ethical paradigm for analysis: an example regarding e-mail privacy issues
CORPORATE IEEE-CS-ACM Joint Task Force on Software Engineering Ethics: Software engineering code of ethics and professional practice (version 4)
Developing guidelines within the Canadian "knowledge-based economy/society"
Navigating the knowledge infrastructure: strategies for increasing workplace democracy and knowledge management (abstract)
Liberty and community online
Beyond the code of ethics: the responsibility of professional societies
Survey results from the incredible shrinking pipeline (abstract)
What makes professionals so difficult: an investigation into professional ethics teaching
Raising the bar: a software engineering code of ethics and professional practice
Cryptography, data retention, and the panopticon society (abstract)
ACM Policy 1998, The ethics and social impact component on Shaping policy in the information age, Washington, DC, USA, May 10-12, 1998, Proceedings
An ethics for the new surveillance (abstract)
Anonymity, pseudonymity, or inescapable identity on the net (abstract)
Including the social and ethical implications of computing in the computer science curriculum
CPSR's approach to advising policymakers
The FCC's universal service rules (abstract): for schools and libraries
Who shapes the future? problem framings and the development of handheld computers
Who profits? online copyright concerns for writers
Layered Patterns in Modelling and Transformation of Service-Based Software Architectures
Software Architecture, First European Workshop, EWSA 2004, St Andrews, UK, May 21-22, 2004, Proceedings
From Acme to CORBA: Bridging the Gap
Software Architecture: The Next Step
Aspect Modelling at Architecture Design
Generation and Enactment of Controllers for Business Architectures Using MDA
Constraints of Behavioural Inheritance
Synthesis of Concurrent and Distributed Adaptors for Component-Based Systems
Towards an MDA-Based Development Methodology
Software Architectures for Designing Virtual Reality Applications
Managing Dynamic Reconfiguration in Component-Based Systems
A Distributed Intrusion Detection Approach for Secure Software Architecture
Engineering MDA into Compositional Reasoning for Analyzing Middleware-Based Applications
Component Deployment Evolution Driven by Architecture Patterns and Resource Requirements
Model Checking for Software Architectures
An Architecture Description Language for Mobile Distributed Systems
Introspective Model-Driven Development
Architecting Global Automation Systems over a Distributed Multi-agent Infrastructure
Formalization of an HCI Style for Accelerator Restart Monitoring
Pattern-Based Architectural Design Driven by Quality Properties: A Platform to Model Scientific Calculation
Handling Dynamic Behaviour in Software Architectures
On the Systematic Conformance Check of Software Artefacts
Automated Selection of Software Components Based on Cost/Reliability Tradeoff
Integrating Software Architecture into a MDA Framework
The Decision View of Software Architecture
Modeling and Analyzing Mobile Software Architectures
The ArchWare Tower: The Implementation of an Active Software Engineering Environment Using a pi-Calculus Based Architecture Description Language
The FABRIC Project
UML 1.4 versus UML 2.0 as Languages to Describe Software Architectures
Modes for Software Architectures
On the Role of Architectural Style in Model Driven Development
Towards Context-Sensitive Intelligence
Experiences Using Viewpoints for Information Systems Architecture: An Industrial Experience Report
Eliminating Execution Overhead of Disabled Optional Features in Connectors
Expressing Domain Variability for Configuration
Formal Analysis of Architectural Patterns
Concern-Based Development of Pattern Systems
Software Architecture, 2nd European Workshop, EWSA 2005, Pisa, Italy, June 13-14, 2005, Proceedings
Deriving Architecture Specifications from KAOS Specifications: A Research Case Study
Architectural Modelling in Product Family Context
Context-Awareness in Software Architectures
Primacy of Place: The Reorientation of Software Engineering Demanded by Software Architecture
ArchWare: Architecting Evolvable Software
Reflection-Based, Aspect-Oriented Software Architecture
Architectural Aspects of Architectural Aspects
Modelling to Safety
Identifying "Interesting" Component Assemblies for NFRs Using Imperfect Information
Configurations by UML
Architecture Transformation and Refinement for Model-Driven Adaptability Management: Application to QoS Provisioning in Group Communication
Correct Development of Embedded Systems
Sotograph - A Pragmatic Approach to Source Code Architecture Conformance Checking
Software Architecture, Third European Workshop, EWSA 2006, Nantes, France, September 4-5, 2006, Revised Selected Papers
Using Architectural Models at Runtime: Research Challenges
Automating the Building of Software Component Architectures
Software Architecture Evolution through Dynamic AOP
Architecture Description for Mobile Distributed Systems
Fault Tolerant Web Service Orchestration by Means of Diagnosis
Distilling Scenarios from Patterns for Software Architecture Evaluation - A Position Paper
On the Modular Representation of Architectural Aspects
Maintainability through Architecture Development
Towards MDD Transformations from AO Requirements into AO Architecture
Towards More Flexible Architecture Description Languages for Industrial Applications
Dynamic Evolution in Aspect-Oriented Architectural Models
Preserving Software Quality Characteristics from Requirements Analysis to Architectural Design
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs
Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs
Activity Estimation for Field-Programmable Gate Arrays
On the feasibility of early routing capacitance estimation for FPGAs
Direct Device-to-Device Physical Page Migrations in Multi-FPGA Shared Virtual Memory Systems
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores
Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor
Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers
Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm
IP-XACT extensions for IP interoperability guarantees and software model generation
Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings
An FPGA Solver for SAT-Encoded Formal Verification Problems
A Reconfigurable Architecture for High Speed Computation by Pipeline Processing
Adaptive Processor: A Dynamically Reconfiguration Technology for Stream Processing
On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs
Prototyping Environment for Dynamically Reconfigurable Logic
FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs
Exploiting reconfigurability through domain-specific systems
A Data-Center FPGA Acceleration Platform for Convolutional Neural Networks
Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs
(GECO) 2 : A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture
Optimization of Run-Time Reconfigurable Embedded Systems
Transparent Integration of a Dynamic FPGA Database Acceleration System
Genetic Programming Using Self-Reconfigurable FPGAs
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education
Towards a unique FPGA-based identification circuit using process variations
Tear Down The Wall: Unified and Efficient Intra-and Inter-Cluster Routing for FPGAs
Power efficient DSP datapath configuration methodology for FPGA
The Java environment for reconfigurable computing
A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy
Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form
FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs
Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS
Power Reduction in Network Equipment through Adaptive Partial Reconfiguration
An FPGA-based embedded wideband audio codec system
Implementation of 3-D Adaptive LUM Smoother in Reconfigurable Hardware
HW/SW Co-design by Automatic Embedding of Complex IP Cores
Meaningful Benchmarks for Logic Optimization of Table-Lookup FPGAs
An efficient hardware architecture of the optimised SIFT descriptor generation
Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application
A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs
Method for dynamic power monitoring on FPGAs
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model
Automatic Software Hardware Co-Design for Reconfigurable Computing Systems
Reconfigurable hardware: The holy grail of matching performance with programming productivity
Specifying Control Logic for DSP Applications in FPGA
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
System Level Architecture Exploration for Reconfigurable Systems On Chip
Safe PLD-based Programmable Controllers
Rapid FPGA design prototyping through preservation of system logic: A case study
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation
Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs
Accurate power analysis for near-Vt RRAM-based FPGA
Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings
Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
In field, energy-performance tunable FPGA architectures
Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit
Mining CryptoNight-Haven on the Varium C1100 Blockchain Accelerator Card
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs
Field-Programmable Logic: Catalyst for New Computing Paradigms
Acceleration of a production rigid molecule docking code
Compression system for the phonocardiographic signal
Towards a guided design flow for heterogeneous reconfigurable architectures
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Programmable System Level Integration Brings System-on-Chip Design to the Desktop
Data-triggered breakpoint for in-circuit debug without re-implementation
The hardware application platform of the hartes project
Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA
Dataflow graph partitioning for high level synthesis
Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips
Arbitrating Instructions in an pmu-Coded CCM
Verification of streaming designs by combining symbolic simulation and equivalence checking
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform
Tightly Integrated Placement and Routing for FPGAs
Combining data and computation transformations for fine-grain reconfigurable architectures
Enabling SRAM-PUFs on Xilinx FPGAs
A hardware accelerated approach for imaging flow cytometry
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains
An enhanced and embedded GNU radio flow
A virus scanning engine using a parallel finite-input memory machine and MPUs
HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation
Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations
FPGA Implementation of High-Performance PHM / DPHM Schedulers
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications
Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks
Coping With Uncertainty in FPGA Architecture Design
Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays
Scalable high-performance architecture for convolutional ternary neural networks on FPGA
SOC and RTOS: Managing IPs and Tasks Communications
AHA-GRAPE: Adaptive Hydrodynamic Architecture-GRAvity PipE
A flexible and reliable embedded system for detector control in a high energy physics experiment
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications
A case study of algorithm implementation in reconfigurable hardware and software
Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems
Direct sigma-delta modulated signal processing in FPGA
An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
Intelligent Parking System Design Using FPGA
Improved Functional Simulation of Dynamically Reconfigurable Logic
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator
Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem
Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor
RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks
Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns
Improving the Reliability of FPGA CRO PUFs
A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding
An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis
Design and implementation of fault-tolerant soft processors on FPGAs
FPGA Accelerated Deep Learning Radio Modulation Classification Using MATLAB System Objects & PYNQ
Mapping Recursive Functions to Reconfigurable Hardware
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
Dynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filters
SimXMD: Simulation-based HW/SW co-debugging
A runtime reconfigurable FPGA-based microphone array for sound source localization
A Generic Library for Adaptive Computing Environments
FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms
Configware Design Space Exploration Using Rewriting Logic
A new methodology for debugging and validation of soft cores
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
Identifying sequences of optimizations for HW/SW compilation
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux
A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects
A Codesign Tool for High Level Systhesis of Vision Models on FPL
An FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics
On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs
Variable-Length Hashing for Exact Pattern Matching
An FPGA architecture for the Pagerank eigenvector problem
Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA
Implementing CSAT Local Search on FPGAs
VHDL-Based Rapid Hardware Prototyping Using FPGA Technology
Virtual Instruments Based on Reconfigurable Logic
A Many-core Implementation based on the Reconfigurable Mesh Model
An Open-Source And Extensible Framework for Fast Prototyping and Benchmarking of Spiking Neural Network Hardware
Mapping and scheduling with task clustering for heterogeneous computing systems
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers
Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells
Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer
The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates
A Knowledge-Based System for Prototyping on FPFAs
Adventures with a Reconfigurable Research Platform
Low-cost multiplier-based FPU for embedded processing on FPGA
A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems
A biophysically accurate floating point somatic neuroprocessor
Modular Partitioning for Incremental Compilation
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices
Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor
Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform
An FPGA implementation of a matched filter detector for spread spectrum communications systems
FPGA partial reconfiguration via configuration scrubbing
High Speed Low Level Image Processing on FPGAs Using Distributed Arithmetic
Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic
A framework for Open Tiled Manycore System-On-Chip
A portable abstraction layer for hardware threads
K-means implementation on FPGA for high-dimensional data using triangle inequality
CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS
Scalable parallel architecture for singular value decomposition of large matrices
An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization
Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures
Optimizing streaming stencil time-step designs via FPGA floorplanning
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs
Encoded-Low Swing Technique for Ultra Low Power Interconnect
Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks
An Analytical Approach to Generation and Exploration of Reconfigurable Architectures
Modeling recursion data structures for FPGA-based implementation
Customised Hardware Based on the REDOC III Algorithm for High-Performance Date Ciphering
A Scalable and Cross-Technology Quantum Control Processor
Relational query processing on OpenCL-based FPGAs
A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks
PPMC: Hardware scheduling and memory management support for multi accelerators
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector
A Novel Strategy for Flexible Placement and Routing of AVS Sensors on FPGAs
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Hierarchical Force-Based Block Spreading for Analytical FPGA Placement
Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs
Scalable and high throughput biosensing platform
Memory efficient and high performance key-value store on FPGA using Cuckoo hashing
Reconfigurable Systems Emerge
FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystems
Hardware acceleration of a software-based VPN
Transparent memory encryption and authentication
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators
Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures
Body bias optimization for variable pipelined CGRA
A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation
A High-Density Optically Reconfigurable Gate Array Using Dynamic Method
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Find the real speed limit: FPGA CAD for chip-specific application delay measurement
Design and Evaluation of an FPGA Architecture for Software Protection
Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework
A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays
Measure twice and cut once: Robust dynamic voltage scaling for FPGAs
A framework for integrated monitoring of real-time embedded SoC
Generative Development System for FPGA Processors with Active Components
A Configurable TLB Hierarchy for the RISC-V Architecture
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs
TTA-SIMD Soft Core Processors
A Method for Fast Hardware Specialization at run-time
Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
Low area memory-free FPGA implementation of the AES algorithm
New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic
Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm
A generic high throughput architecture for stream processing
A comparison of FPGA and FPAA technologies for a signal processing application
Phase calibrated ring oscillator PUF design and implementation on FPGAs
Exploiting fast carry-chains of FPGAs for designing compressor trees
Automatic Creation of Reconfigurable PALs/PLAs for SoC
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization
Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures
Optimal random sampling based path planning on FPGAs
A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture
Automatic high-level synthesis of multi-threaded hardware accelerators
Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme
Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration
A study of data partitioning on OpenCL-based FPGAs
Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communications
Real-time stereopsis using FPGAs
Coherent Demodulation with FPGAs
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement
Demonstration of a Multimode SoC FPGA-Based Acoustic Camera
Dynamic Reconfiguration in Mobile Systems
An Effective Architecture for Trace-Driven Emulation of Networks-on-Chip on FPGAs
Design and Implementation of RNS-Based Adaptive Filters
Carnac: Algorithm Variability for Fast Swarm Verification on FPGA
E 3 HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices
Single-FPGA 3D ultrasound beamformer
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA
An analytical model describing the relationships between logic architecture and FPGA density
An Efficient Exact Fused Dot Product Processor in FPGA