yusuke1997/dblp-id-title huggingface dataset:
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process
An integrated 33.5dBm linear 2.4GHz power amplifier in 65nm CMOS for WLAN applications
oder: http: //potol.eecs.berkeley.edu/~jr Analytical equations for predicting injection locking in LC and ring oscillators
Session 9 - Advanced simulation techniques
Coral-automating the design of systems-on-chip using cores
A 33μW/node Duty Cycle Controlled HBC Transceiver system for medical BAN with 64 sensor nodes
A 21-27GHz self-shielded 4-way power-combining PA balun
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply
Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs
Session 6 - RF and millimeter-wave power amplifiers and transmitters
Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation space
An electrically robust method for placing power gating switches in voltage islands
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM
Circuit design, transistor sizing and wire layout of FPGA interconnect
Secure contactless smartcard ASIC with DPA protection
A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver
A 3-Phase Resonant Current-Mode Wireless Power Receiver with Residual-Free Energy Delivery and Digital-Assisted ZVS Achieving 94.5% Efficiency
A low noise buck converter with a fully integrated continuous time ΣΔ modulated feedback controller
A 760 nW, 180 nm CMOS Analog Voice Activity Detection System
ViPro: Focal-Plane Spatially-Oversampling CMOS Image Compression Sensor
Highly-integrated guidewire vascular ultrasound imaging system-on-a-chip
A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop
A CMOS TDC-based digital magnetic Hall sensor using the self temperature compensation
Robust platform design in advanced VLSI technologies
High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications
A quadrature direct digital downconverter
Mismatch analysis and statistical design at 65 nm and below
Modeling leakage in ASIC libraries
A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST
Current sensor IC provides 9 bit+sign result without external sense resister
The Intel® PXA800F wireless Internet-on-a-chip architecture and design
A multicarrier QAM-modulator for WCDMA basestation with on-chip D/A converter
A 28nm 3.14 TFLOP/W BF16 LLM Fine-Tuning Processor with Asymmetric Quantization Computing for AI PC
Characterization of matching variability and low-frequency noise for mixed-signal technologies
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
Trends and challenges of large scale embedded memories
A low power high reliability dual-path noise-cancelling LNA for WSN applications
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
A Fully-Integrated Direct-Conversion Resonant Switched Capacitor Converter with Modular Multi-Winding Current Ballasting
A noise-tolerant dynamic circuit design technique
Session 22 - High frequency analog techniques
Complete noise analysis for CMOS switching mixers via stochastic differential equations
A 10/2.5-Gb/s Hyper-Supplied CMOS Low-Noise Burst-Mode TIA with Loud Burst Protection and Gearbox Automatic Offset Cancellation for XGS-PON
Education session 4 - Low Power IoT wireless powering for ultra low power batteryless IoT sensing and communication
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS
A 350-mV, under-200-ppm allan deviation floor gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS
Session 11 - Advanced techniques for power amplifier transceiver front-ends
Reconfigurable mobile stream processor for ray tracing
A tail current-shaping technique to reduce phase noise in LC VCOs
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS
A single chip CMOS APS camera with direct frame difference output
A Fully-Integrated Biofuel-Cell-Based Energy Harvester with 86% Peak Efficiency and 0.25V Minimum Input Voltage Using Source-Adaptive MPPT
A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm
Design challenges for system-in-package vs system-on-chip
Three Dimensional integration - Considerations for memory applications
Burst mode: a new acceleration mode for 128-bit block ciphers
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C
Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology
Silicon Integrated Circuits Incorporating Antennas
ADMS-automatic device model synthesizer
A 23-37GHz Autonomous Two-Dimensional MIMO Receiver Array with Rapid Full-FoV Spatial Filtering for Unknown Interference Suppression
High-voltage tolerant stimulation monitoring circuit in conventional CMOS process
A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control
A start-up boosting circuit with 133× speed gain for 2-transistor voltage reference
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS
A Low Phase Noise 100MHz Silicon BAW Reference Oscillator
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture
A 10 GHz CMOS distributed voltage controlled oscillator
A 38GHz Power-Combined Doherty PA Based on an Extended Rat-Race Coupler Achieving 27.5dBm Saturated Power and 15.0% Efficiency at 6dB Back-Off
A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager
Initialization of a wireless clock distribution system using an external antenna
A 0.791mm 2 fully on-chip controller with self-error-correction for boost DC-DC converter based on Zero-Order Control
An Ultra-Compact 84.9-107GHz LNA with 4.9dB NF by Utilizing Coupled-line-based Gm-Boosting and Noise-Canceling Techniques in 65-nm CMOS Technology
A 28-nm Real-Time Reinforcement Learning Processor for Mapless Autonomous Navigation with Unified Actor-Critic Network and Inference-on-Request Scheduling
Impact of random telegraph noise on CMOS logic circuit reliability
How to make theoretically passive reduced-order models passive in practice
A hardware/software solution for embeddable FPGA
A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology
A/D converter circuit and architecture design for high-speed data communication
Multiband UWB transceivers
Session 14 - Advanced SoCs - techniques and applications
A $36\times 40$ Wireless Fluorescence Image Sensor for Real-Time Microscopy in Cancer Therapy
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems
A 695 pW standby power optical wake-up receiver for wireless sensor nodes
A 41.5 pJ/b, 2.4GHz Digital-Friendly Orthogonally Tunable Transceiver SoC with 3-decades of Energy-Performance Scalability
Session 19 - Low power and non-traditional RF tranceivers
Integration architecture for system-on-a-chip design
A 14nV/√Hz 14μW Chopper Instrumentation Amplifier with Dynamic Offset Zeroing (DOZ) Technique for Ripple Reduction
A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants
An efficient inductance modeling for on-chip interconnects
Frequency tunable silicon carbide resonators for MEMS above IC
A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies
Design for data-center, low-power and SoCs
A 30Gb/s 2x Half-Baud-Rate CDR
Data converter techniques
Notice of Violation of IEEE Publication PrinciplesA Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA
A 0.0013mm 2 10b 10MS/s SAR ADC with a 0.0048mm 2 42dB-rejection passive FIR filter
A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet
Electronics-photonics co-design for robust control of optical devices in dense integrated photonic circuits
A 500 MHz OTA-C 4 th order lowpass filter with class AB CMFB in 0.35 μm CMOS technology
A 368 × 184 Optical Under-Display Fingerprint Sensor With Global Shutter and High-Dynamic-Range Operation
A 105 dB SNR multibit ΣΔ ADC for digital audio applications
EMI resisting smart-power integrated LIN driver with reduced slope pumping
Gigabit transceivers and building blocks
A 1V 420μW 32-channel Cortical Signal Interface
A single-inductor dual-output switching converter with low ripples and improved cross regulation
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration
Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit]
Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS
A 16b 10MS/s digitally self-calibrated ADC with time constant control
A 5-115V efficiency-enhanced synchronous LED driver with adaptive resonant timing control
A 46 μW motion artifact reduction bio-signal sensor with ICA based adaptive DC level control for sleep monitoring system
Low-Voltage Multi-Mode Gm-C Channel Selection Filter for Mobile Applications
The first copper ASICs: A 12M-gate technology
Circuit simulation and design methodology
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs
A distributed "hybrid" wave oscillator array for millimeter-wave phased-arrays
Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits
Integrated CMOS transceivers design towards flexible full duplex (FD) and frequency division duplex (FDD) systems
A 40 μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants
A 7.9 ps Resolution, Multi-Event TDC Using an Ultra-Low Static Phase Error DLL and High Linearity Time Amplifier for dToF Sensors
A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS
A13b-ENOB Third-Order Noise-Shaping SAR ADC using a Hybrid Error-Control Structure
Ultra low voltage switched opamp ΣΔ modulator for portable applications
An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications
Linearity and efficiency enhancement strategies for 4G wireless power amplifier designs
Millimeter-wave CMOS integrated circuits for gigabit WPAN applications
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM
A 12-/14-bit, 4/2MSPS, 0.085mm 2 SAR ADC in 65nm using novel residue boosting
A wideband RF receiver with >80 dB harmonic rejection ratio
Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS
A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction
A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting
Impedance, filtering and noise in n-phase passive CMOS mixers
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators
A 50-300-MHz low power and high linear active RF tracking filter for digital TV tuner ICs
A 14 nA quiescent current inductorless dual-input-triple-output thermoelectric energy harvesting system based on a reconfigurable TEG array
A 150 MHz 13b 12.5 mW IF digitizer
CMOS terahertz receivers
A CMOS instrumentation amplifier with 600 nV offset, 8.5 nV/⎷(Hz) noise and 150 dB CMRR
SLiMO: A 61.8% Efficiency Single-Link Multiple-Output Isolated DC-DC Converter Using Low-Cost FPC Micro- Transformer with Local Voltage and Global Power Regulation
An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gate
A new dynamic, self-consistent electro-thermal model of power HBTs and a novel interpretation of thermal collapse loci in multi-finger devices
A Monolithic 3D Magnetic Sensor in 65nm CMOS with rms Noise and 14.8μW Power
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS
Measurement of high-speed ADCs
Mismatch Characterization of Ring Oscillators
Statistical aging under dynamic voltage scaling: A logarithmic model approach
A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression
A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output
Design techniques for a 1-V operation Bluetooth RF transceiver
Design-For-Safety For Automotive IC Design: Challenges And Opportunities
A programmable CMOS transceiver for structural health monitoring
A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process
A Fractional-N Cascaded PLL Employing the Calibration-Free Noise-and-Spur Cancellation Technique
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects
Timing in-situ monitors: Implementation strategy and applications results
A 328 μW 5 GHz voltage-controlled oscillator in 90 nm CMOS with high-quality thin-film post-processed inductor
Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems
A low power 1.3GHz dual-path current mode Gm-C filter
Issues for fabless design companies moving towards deep submicron system on a chip design
A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload
Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS
RF/analog and mixed-signal design techniques in FD-SOI technology
An equation-based method for phase noise analysis [oscillator examples]
A 7b 1.4GS/s ADC with offset drift suppression techniques for one-time calibration
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter
Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond
A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehicles
Auto Correction Feedback for ripple suppression in a chopper amplifier
Efficient full-wave simulation in layered, lossy media
A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference
Session 24 - Advanced subsystems for connectivity and cellular radio
A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery
A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array
Advanced simulation techniques
EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision
Design metrics for blind ADC-based wireline receivers
A 2 MHz GFSK IQ receiver for Bluetooth with DC-tolerant bit slicer
Bottom-up digital system-level reliability modeling
A low power, high performance, 960 macrocell, SRAM based complex PLD
A 10-b, 1-GSample/s track-and-hold amplifier using SiGe BiCMOS technology
A CMOS switched-capacitor fractional bandgap reference
A 7.4μW and 860μm 2 per Channel Cryo-CMOS IC for 70-Channel Frequency-Multiplexed μs-Readout of Semiconductor Qubits
MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation
An architecture for a programmable mixed-signal device
A 0.06-mm 2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion
A mixed-mode FPAA SoC for analog-enhanced signal processing
A 5V-Input, 12.5-to-45V-Output Reconfigurable Hybrid Boost Converter with an SC-Based Parallel Auxiliary Cell Achieving 96.8% Peak Efficiency
A nonlinear phase detector for digital phase locked loops
IC and Array Technologies for 100-300GHz Wireless
A High-Performance Passive Base System for Distributed AI/Media Acceleration
Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation
Amplifiers and filters
The Rise of SoC FPAA Devices
Adjoint sensitivity analysis of nonlinear distortion in RF circuits
An ASIC-embedded content addressable memory with power-saving and design for test features
Broadband, 0.25 μm CMOS LNAs with sub-2dB NF for GSM applications
Session 13 - Biomedical, sensors and MEMS
Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory
A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC
An Authentication IC with Visible Light Based Interrogation in 65nm CMOS
Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]
A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz
Adiabatically driven touch controller analog front-end for ultra-thin displays
IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking
Analysis of Oscillators Locked by Large Injection Signals: Generalized Adler's Equation and Geometrical Interpretation
A new scalable VLSI architecture for Reed-Solomon decoders
Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper)
A power-efficient multi-channel PPG ASIC with 112dB receiver DR for pulse oximetry and NIRS
Spurious free time-to-digital conversion in an ADPLL using short dithering sequences
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS
Testing analog circuits by supply voltage variation and supply current monitoring
Hardware/software Co-design for Neuromorphic Systems
A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS
FeRAM device and circuit technologies fully compatible with advanced CMOS
Single reference continuous rate clock and data recovery from 30 Mbit/s to 3.2 Gbit/s
Embedded DRAM: an element and circuit evaluation
Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs
A 19-GHz Broadband Amplifier Using a g m -Boosted Cascode in 0.18-μm CMOS
CMOS pipelined ADC employing dither to improve linearity
Analysis and measurements of EM and substrate coupling effects in common RF integrated circuits
Scalable bus interface for HSDPA co-processor extension
A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction
Diagnosing resistive bridges using adaptive techniques
Piece-wise parabolic interpolation for direct digital frequency synthesis
A capacitive-coupling technique with phase noise and phase error reduction for multi-phase clock generation
A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS
Custom circuits
Phase-locking in wireline systems: Present and future
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation
Proactive design for manufacturing (DFM) for nanometer SoC designs
Emerging data converter architectures and techniques
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO
Reliability challenges for the continued scaling of IC technologies
A GSM receiver front-end in 65 nm digital CMOS process
Intellectual property re-use and system emulation the keys to succeed the SoC challenge: a digital TV application
A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology
Statistical analysis of integrated passive delay lines
mm-Wave Silicon ICs: Challenges and Opportunities
A self-calibration technique for mismatches in image-reject receivers
A high performance, high voltage output buffer in a low voltage CMOS process
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology
An integrated CMOS receiver chip for NMR-applications
Design techniques for very low power ADCs
Towards a 1.1 mm 2 free-floating wireless implantable neural recording SoC
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits
Faster statistical cell characterization using adjoint sensitivity analysis
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C
Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies
A 1.54mm 2 Wake-Up Receiver Based on THz Carrier Wave and Integrated Cryptographic Authentication
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS
A Scalable 256-Channel 12-mA 0.06%-Current-Mismatch 22-V Neurostimulator with Real-Time Current Calibration and Compliance Monitoring
A 44μW 140dB-DR Hybrid Light-to-Digital Converter with Current-Tracking Dynamic Zoom and Power-Scaling OTA
A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS
Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI
CMOS handset power amplifiers: Directions for the future
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System
A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application
A Current-mode ADC with Current Exchanging and Averaging Capabilities by Switching the Currents and Calculating Data in the Digital Domain
A multistage amplifier topology with embedded tracking compensation
A 2GHz, 7W (max) 64b Power TM Microprocessor Core
A 1-V 60-µW 16-channel interface chip for implantable neural recording
A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS
An Embedded 8-bit RISC Controller for Yield Enhancement of the 90-nm PRAM
Reducing the Impact of Non-Idealities on Incremental Δ∑ ADCs by Reconfiguration: A Review
Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 μm CMOS
MEMS for integrated timing and spectral processing
A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs
A low-cost audio computer for information dissemination among illiterate people groups
A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS