yusuke1997/dblp-id-title huggingface dataset:
Network Effects in Double Auction Markets with Automated Traders
Handling Resource Use Oscillation in Multi-agent Markets
Multi-attribute Regret-Based Dynamic Pricing
Automated Negotiation and Bundling of Information Goods
Co-evolutionary Auction Mechanism Design: A Preliminary Report
A Successful Broker Agent for Power TAC
A Budget-Balanced, Incentive-Compatible Scheme for Social Choice
Agent Strategies on DPB Auction Tournaments
Improving Prediction in TAC SCM by Integrating Multivariate and Temporal Aspects via PLS Regression
JACK: A Java Auction Configuration Kit
Goodwill Hunting: An Economically Efficient Online Feedback Mechanism for Environments with Variable Product Quality
Auctions and Bidding with Information
Sequential Auctions with Partially Substitutable Goods
iAuctionMaker: A Decision Support Tool for Mixed Bundling
A Mechanism for Multiple Goods and Interdependent Valuations
A Comparison among Bidding Algorithms for Multiple Auctions
Agent-Mediated Electronic Commerce IV, Designing Mechanisms and Systems, AAMAS 2002 Workshop on Agent Mediated Electronic Commerce, Bologna, Italy, July 16, 2002, Revised Papers
Coordinating Decisions in a Supply-Chain Trading Agent
Generalized Knapsack Solvers for Multi-unit Combinatorial Auctions: Analysis and Application to Computational Resource Allocation
Leading a Best-Response Teammate in an Ad Hoc Team
Three Automated Stock-Trading Agents: A Comparative Study
Approximating the Qualitative Vickrey Auction by a Negotiation Protocol
The Influence of Information on Negotiation Equilibrium
An Intelligent Learning Mechanism for Trading Strategies for Local Energy Distribution
Automated Analysis of Auction Traces
An Ontology Based Approach to Automated Negotiation
Designing Auctions for Deliberative Agents
Agent-Mediated Electronic Commerce III, Current Issues in Agent-Based Electronic Commerce Systems (includes revised papers from AMEC 2000 Workshop)
A Platform for Electronic Commerce with Adaptive Agents
Agent Mediated Electronic Commerce II, Towards Next-Generation Agent-Based Electronic Commerce Systems, IJCAI 1999 Workshop
How Specialised Are Specialists? Generalisation Properties of Entries from the 2008 and 2009 TAC Market Design Competitions
Human Traders across Multiple Markets: Attracting Intra-marginal Traders under Economic Experiments
Multi-attribute Utility Theoretic Negotiation for Electronic Commerce
Agents' Strategies for the Dual Parallel Search in Partnership Formation Applications
Applications of Classifying Bidding Strategies for the CAT Tournament
Sequences of Take-It-or-Leave-It Offers: Near-Optimal Auctions Without Full Valuation Revelation
Self-Enforcing Strategic Demand Reduction
Designing Tariffs in a Competitive Energy Market Using Particle Swarm Optimization Techniques
Designing an Ad Auctions Game for the Trading Agent Competition
Bilateral Negotiation for Agent-Mediated Electronic Commerce
An Effective Broker for the Power TAC 2014
An Options-Based Method to Solve the Composability Problem in Sequential Auctions
Mechanism Design for the Online Allocation of Items without Monetary Payments
Guaranteeing Properties for E-commerce Systems
Electricity Trading Agent for EV-enabled Parking Lots
Trading without Explicit Ontologies
Acquiring Tradeoff Preferences for Automated Negotiations: A Case Study
Ad Exchange - Proposal for a New Trading Agent Competition Game
A Software Infrastructure for Negotiation within Inter-organisational Alliances
Auction Based Mechanisms for Dynamic Task Assignments in Expert Crowdsourcing
Challenges in Large-Scale Open Agent Mediated Economies
Agent-Mediated Electronic Commerce. Designing Trading Strategies and Mechanisms for Electronic Markets - AMEC/TADA 2015, Istanbul, Turkey, May 4, 2015, and AMEC/TADA 2016, New York, NY, USA, July 10, 2016, Revised Selected Papers
A Demand-Driven Approach for a Multi-Agent System in Supply Chain Management
Analysis of Fairness and Incentives of Profit Sharing Schemes in Group Buying
Robust Planning and Control Using Intelligent Products
Autonomous Power Trading Approaches of a Winner Broker
Automated Negotiation in Many-to-Many Markets for Imperfectly Substitutable Goods
Agent-Mediated Electronic Commerce. Designing Trading Strategies and Mechanisms for Electronic Markets - AMEC 2011, Taipei, Taiwan, May 2, 2011, and TADA 2011, Barcelona, Spain, July 17, 2011, Revised Selected Papers
Incentives in Multi-dimensional Auctions under Information Asymmetry for Costs and Qualities
Price-Based Information Certificates for Minimal-Revelation Combinatorial Auctions
Improving Learning Performance by Applying Economic Knowledge
A Multiagent Recommender System with Task-Based Agent Specialization
Agent-Mediated Electronic Commerce. Designing Trading Strategies and Mechanisms for Electronic Markets - AMEC 2013, Saint Paul, MN, USA, May 6, 2013, TADA 2013, Bellevue, WA, USA, July 15, 2013, and AMEC and TADA 2014, Paris, France, May 5, 2014, Revised Selected Papers
Issues in the Design of Negotiation Protocols for Logic-Based Agent Communication Languages
Customer Coalitions in Electronic Markets
Agent Adaptation across Non-ideal Markets and Societies
A Decision Framework for Broker Selection in Smart Grids
Nash Social Welfare in Multiagent Resource Allocation
Time Constraints in Mixed Multi-unit Combinatorial Auctions
Designing Robust Strategies for Continuous Trading in Contemporary Power Markets
A Model-Free Approach for a TAC-AA Trading Agent
Differential -Revelation VCG Mechanisms for Combinatorial Auctions
Analysis of Stable Prices in Non-Decreasing Sponsored Search Auction
Strategic Free Information Disclosure for a Vickrey Auction
On Revenue-Maximizing Walrasian Equilibria for Size-Interchangeable Bidders
Distributed Prediction Markets Modeled by Weighted Bayesian Graphical Games
An Analysis of Power Trading Agent Competition 2014
Evaluation of Market Design Agents: The Mertacor Perspective
Eliciting Expert Advice in Service-Oriented Computing
On the Economic Effects of Competition between Double Auction Markets
Bidding for Customer Orders in TAC SCM
Agent-Mediated Electronic Commerce. Designing Trading Strategies and Mechanisms for Electronic Markets - AAMAS Workshop, AMEC 2009, Budapest, Hungary, May 12, 2009, and IJCAI Workshop, TADA 2009, Pasadena, CA, USA, July 13, 2009, Selected and Revised Papers
Continuous Double Auctions with Execution Uncertainty
Specifying and Monitoring Market Mechanisms Using Rights and Obligations
A Genetic Algorithmic Approach to Automated Auction Mechanism Design
Towards Modeling Securities Markets as a Society of Heterogeneous Trading Agents
Competing Intermediaries in Online Display Advertising
The 2007 TAC SCM Prediction Challenge
Integrating Interaction Protocols and Internet Protocols for Agent-Mediated E-Commerce
A Decommitment Strategy in a Competitive Multi-agent Transportation Setting
Agent-Mediated Electronic Commerce and Trading Agent Design and Analysis - AAMAS Workshop, AMEC 2008, Estoril, Portugal, May 12-16, 2008, and AAAI Workshop, TADA 2008, Chicago, IL, USA, July 14, 2008, Revised Selected Papers
A Grey-Box Approach to Automated Mechanism Design
An Empirical Analysis of QuiBids' Penny Auctions
A Market-Based Coordinated Negotiation for QoS-Aware Service Selection
A Study of Central Auction Based Wholesale Electricity Markets
Rank and Impression Estimation in a Stylized Model of Ad Auctions
From General Game Descriptions to a Market Specification Language for General Trading Agents
Multi-attribute Bilateral Bargaining in a One-to-Many Setting
Policy Search through Adaptive Function Approximation for Bidding in TAC SCM
Classification Driven Detection of Opportunistic Bids in TAC SCM
Mechanism Design for Eliciting Probabilistic Estimates from Multiple Suppliers with Unknown Costs and Limited Precision
A Formal Description of a Practical Agent for E-Commerce
Testing Adaptive Expectations Models of a Continuous Double Auction Market against Empirical Facts
Agent-Mediated Electronic Commerce V, Designing Mechanisms and Systems, AAMAS 2003 Workshop, AMEC 2003, Melbourne, Australia, July 15, 2003, Revised Selected Papers
Online Double Auction for Perishable Goods
The Choice of Eliminating the Uncertainty Cloud in Auctions
Bidding Heuristics for Simultaneous Auctions: Lessons from TAC Travel
An Adaptive Proportional Value-per-Click Agent for Bidding in Ad Auctions
Bidtree Ordering in IDA* Combinatorial Auction Winner-Determination with Side Constraints
On the Use of Off-the-Shelf Machine Learning Techniques to Predict Energy Demands of Power TAC Consumers
An English Auction Protocol for Multi-attribute Items
Search Costs as a Means for Improving Market Performance
Algorithm Design for Agents which Participate in Multiple Simultaneous Auctions
To Bid or Not To Bid Agent Strategies in Electronic Auction Games
Acceptance Strategies for Maximizing Agent Profits in Online Scheduling
Flexibly Priced Options: A New Mechanism for Sequential Auctions with Complementary Goods
Auctions for Divisible Resources: Price Functions, Nash Equilibrium, and Decentralized Update Schemes
Agent-Mediated Electronic Commerce. Designing Trading Strategies and Mechanisms for Electronic Markets - AMEC and TADA 2012, Valencia, Spain, June 4th, 2012, Revised Selected Papers
Effectiveness of Preference Elicitation in Combinatorial Auctions
Social Networking and Information Diffusion in Automated Markets
NSF funding for research on universal access
Web access for elderly citizens
Ubiquitous computing and AI towards an inclusive society
Broadband access technologies
Use of the multimedia taxonomy for a research direction into design and evaluation of materials for the elderly
One content, three devices, the same need: access to information by people with special needs
Challenges for multimodal interfaces towards anyone anywhere accessibility: a position paper
Interface design for older adults
Designing robust multimodal systems for universal access
Open syntax: improving access for all users
A neuroscience-based design of intelligent tools for the elderly and disabled
Development of a new robotic interface for telerehabilitation
The national initiative for people with special needs in the information society: the elderly, people with disabilities and long-term bed-ridden
EC/NSF Workshop on Universal Accessibility of Ubiquitous Computing: Providing for the Elderly, 22-25 May 2001, Alcácer do Sal, Portugal
Involving all in design for all
Universal access to mobile telephony as a way to enhance the autonomy of elderly people
Delivering instructions for inherently-3D construction tasks: lessons and questions for universal accessibility
Adaptive tools for the elderly: new devices to cope with age-induced cognitive disabilities
EMBASSI: multimodal assistance for universal access to infotainment and service infrastructures
EC/NSF workshop on universal accessibility of ubiquitous computing: providing for the elderly event report
Some reflections on IT
Designing for dynamic diversity: making accessible interfaces for older people
Law and regulation to include elderly in innovations stream
Electromyography based human-computer-interface to induce movement in elderly persons with movement impairments
Assessment of metaphor efficacy in user interfaces for the elderly: a tentative model for enhancing accessibility
Designing user interfaces for severely handicapped persons
Diffy: a Déjà vu-Free Differential Deep Neural Network Accelerator
Keynotes: Internet of Things: History and hype, technology and policy
BLAISE - 1726
Realistic scheduling: compaction for pipelined architectures
A retargetable microcode generation system for a high-level microprogramming language
Handling long-latency loads in a simultaneous multithreading processor
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications
SPARSE: Spatially Aware LFI Resilient State Machine Encoding
Dual use of superscalar datapath for transient-fault detection and recovery
Designing HMO, an integrated hardware microcode optimizer
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995
Microprogram structures for high level language elements
Efficient scheduling of fine grain parallelism in loops
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Access Region Locality for High-Bandwidth Processor Memory System Design
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
ROG: A High Performance and Robust Distributed Training System for Robotic IoT
A novel cache architecture with enhanced performance and security
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Proceedings of the 10th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2017, Cambridge, MA, USA, October 14-18, 2017
Translation-optimized Memory Compression for Capacity
An implementation of microdiagnostics on the ECLIPSE® MV/8000
A microprogramming support tool for pipelined architectures
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
Mirage cores: the illusion of many out-of-order cores using in-order hardware
A unified memory network architecture for in-memory computing in commodity servers
Optimization of Machine Descriptions for Efficient Use
IPStash: a Power-Efficient Memory Architecture for IP-lookup
43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA
StaCS: a Static Control Superscalar architecture
MDS: An improved total system for firmware development
NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18 - 22, 2021
Shift-BNN: Highly-Efficient Probabilistic Bayesian Neural Network Training via Memory-Friendly Pattern Retrieving
Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference
Taming the Killer Microsecond
OpenPiton Optimizations Towards High Performance Manycores
JAM - just another microsequencer
A retargetable compiler for a high-level microprogramming language
Heuristics for the global optimization of microprograms
Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers
Proceedings of the 2014 International Workshop on Network on Chip Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14, 2014
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
Kiln: closing the performance gap between systems with and without persistence support
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory
Junction based routing: a scalable technique to support source routing in large NoC platforms
Emulating Optimal Replacement with a Shepherd Cache
VGA: Hardware Accelerator for Scalable Long Sequence Model Inference
System description of the JHU emulation laboratory
Over-Synchronization in GPU Programs
The microarchitecture of a capability-based computer
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming
PACMan: prefetch-aware cache management for high performance caching
Adaptive data compression for high-performance low-power on-chip networks
Optimizing delayed branches
37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA
Path confidence based lookahead prefetching
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator
Design and performance measurements of a parallel machine for the unification algorithm
The effects of predicated execution on branch prediction
Modifying VM hardware to reduce address pin requirements
Towards efficient server architecture for virtualized network function deployment: Implications and implementations
HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
Microprogramming in large scale architecture
Generating physical addresses directly for saving instruction TLB energy
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
SAFER: Stuck-At-Fault Error Recovery for Memories
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes
Compiler-directed instruction cache leakage optimization
Petri net versus modulo scheduling for software pipelining
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
Virtual I/O, an experiment
The "cultures" of microprogramming
NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers
Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications
SuperBP: Design Space Exploration of Perceptron-Based Branch Predictors for Superconducting CPUs
Experiences in asynchrony
Architecture of a VLSI multiple ISA emulator
Network-on-Chip Microarchitecture-based Covert Channel in GPUs
Through the video display terminal and what Alice found there
Firmware versus software verification
AUDIT: Stress Testing the Automatic Way
MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption
A structural analysis of evolved complex networks-on-chip
Am2900 Bipolar Microprocessor family
AutoComm: A Framework for Enabling Efficient Communication in Distributed Quantum Programs
Networked SSD: Flash Memory Interconnection Network for High-Bandwidth SSD
A prototype engineering tester for microcode and hardware debugging
Two-ported cache alternatives for superscalar processors
Analysis and Hardware Optimization of Lattice Post-Quantum Cryptography Workloads
The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor
Power reduction of CMP communication networks via RF-interconnects
Architectural Support for Optimizing Huge Page Selection Within the OS
SSDcheck: Timely and Accurate Prediction of Irregular Behaviors in Black-Box SSDs
Fifty years of microarchitecture
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
D-SOAP: Dynamic Spatial Orientation Affinity Prediction for Caching in Multi-Orientation Memory Systems
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Power protocol: reducing power dissipation on off-chip data buses
S*(QM-1): An instantiation of the high level microprogramming language scheme S* for the nanodata QM-11
Wrong-path Instruction Prefetching
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors
Versapipe: a versatile programming framework for pipelined computing on GPU
Architectural Support for Probabilistic Branches
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
Implementing Signatures for Transactional Memory
Instruction sets and their implementations
Accelerating Zero-Knowledge Proofs Through Hardware-Algorithm Co-Design
A microcode-based environment for noninvasive performance analysis
Energy efficient frequent value data cache design
Multi-grain coherence directories
UNICO: Unified Hardware Software Co-Optimization for Robust Neural Network Acceleration
Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs
NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors
Distilling the Essence of Raw Video to Reduce Memory Usage and Energy at Edge Devices
REDUCE/1700: A micro-coded Algebra system
PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices
Accurate Fine-Grained Processor Power Proxies
SHiP: signature-based hit predictor for high performance caching
Convergent scheduling
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias
P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks
Idempotent processor architecture
Dynamic path-based branch correlation
Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation
LSI microprocessors and microprograms for user-oriented machines
Improving Data Reuse in NPU On-chip Memory with Interleaved Gradient Order for DNN Training
NDS: N-Dimensional Storage
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors
Selecting the optimal system: automated design of application-specific systems-on-chip
Partial resolution in branch target buffers
Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing
Microcode verification using SDVS-the method and a case study
OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric
Low power flitwise routing in an unidirectional torus with minimal buffering
Sunder: Enabling Low-Overhead and Scalable Near-Data Pattern Matching Acceleration
Revisiting Residue Codes for Modern Memories
Planaria: Dynamic Architecture Fission for Spatial Multi-Tenant Acceleration of Deep Neural Networks
Improving the Accuracy and Performance of Memory Communication Through Renaming
TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks
Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
Distributed Data Persistency
Self-Reinforcing Memoization for Cryptography Calculations in Secure Memory Systems
Dynamically scheduled VLIW processors
Proceedings of the 19th annual workshop on Microprogramming, New York, NY, USA, October 15-17, 1986
Microassembly and area reduction techniques for PLA microcode
Applying Deep Learning to the Cache Replacement Problem
An investigation of the performance of various dynamic scheduling techniques
Structured microprogramming
A Criticality Analysis of Clustering in Superscalar Processors
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
Microarchitecture on the MOSFET Diet
Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks
Algorithmic state machine implementation with hybrid microprocessing/microprogramming scheme
Microbe: A self commenting microassembler
Path Forward Beyond Simulators: Fast and Accurate GPU Execution Time Prediction for DNN Workloads
SMDSS - a structured microcode development and simulation system
Router microarchitecture and scalability of ring topology in on-chip networks
Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory
Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution
An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing