yusuke1997/dblp-id-title huggingface dataset:
Contact testing of copper micro-pillars with very low damage for 3D IC assembly
3D stacking using ultra thin dies
Noise coupling modeling and analysis of through glass via(TGV)
A 3D Process Design Kit generator based on customizable 3D layout design environment
Mechanical and electrical reliability of copper interconnections for 3DIC
In-pixel ADC for a vision architecture on CMOS-3D technology
Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs
The influence of device morphology on wafer-level bonding with polymer-coated layer
Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environment
No pumping at 450°C with electrodeposited copper TSV
High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless Plating
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack
3D research activities in ITRI
Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices - Technology directions
All-wet fabrication technology for high aspect ratio TSV using electroless barrier and seed layers
Development of high-quality low-temperature (≤ 120°C) PECVD-SiN films by organosilane
Photoelectroscopic Study of Mn Barrier Layer on SiO2 for Si Wafer Bonding Process
Electrochemical Deposition of Indium for Scalable 3D Quantum Chiplets
A Design Scheme for 3-D Stacked CNN Accelerators
High reliability insert-bump bonding process for 3D integration
Design and Evaluation of a Novel and Ultra-Compact Fully-TGV-based Self-Shielding Bandpass Filter for 5G Applications
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration
Towards 3D AI Hardware: Fine-Grain Hardware Characterization of 3D Stacks for Heterogeneous System Integration & AI Systems
Wet-process deposition of TSV liner and metal films
Processing active devices on Si interposer and impact on cost
TSV-based, modular and collision detectable face-to-back shared bus design
Plasma etch and dielectric deposition processes for TSV Reveal
Fast filling of through-silicon via (TSV) with conductive polymer/metal composites
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner
Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding
Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack
All-wet TSV filling with highly adhesive displacement plated Cu seed layer
Improved access pattern for ROB soft error rate mitigation based on 3D integration technology
Heat spreading packaging solutions for hybrid bonded 3D-ICs
Modeling of substrate contacts in TSV-based 3D ICs
Early estimation of TSV area for power delivery in 3-D integrated circuits
3D interconnects for dense die stack packages
Void reduction in wafer bonding by simultaneously formed ventilation channels
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs
Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC
High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs
Electrical-thermal co-analysis for power delivery networks in 3D system integration
Impact of parameter accuracy on 3D design
IC-package co-design and analysis for 3D-IC designs
Design of 3D-IC for butterfly NOC based 64 PE-multicore: Analysis and design space exploration
A compact 3D silicon interposer package with integrated antenna for 60GHz wireless applications
International 3D Systems Integration Conference, 3DIC 2024, Sendai, Japan, September 25-27, 2024
Power tile optimization and packaging for efficient temperature management of ASIC's in networking applications
Optical TSV Using Si-Photonics Integrated Curved Micro-Mirror
TiN Guard Ring Around TSV for Cross-Talk Suppression of Parallel Networking of Data Center
High performance 3D interconnects based on electrochemical etch and liquid metal fill
Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC
3D Integrated Pixel Sensor with Silicon-on-Insulator Technology for the International Linear Collider Experiment
3D-IC technologies and 3D FPGA
Best engineering practice for thermal characterization of stacked dice FPGA devices
Copper deep via superfilling by selective accelerator deactivation
Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers
Advanced TSV filling method with Sn alloy and its reliability
IEEE International 3D Systems Integration Conference, 3DIC 2021, Raleigh, NC, USA, October 26-29, 2021
Die-to-Wafer Hybrid Bonding Impact at MM-Wave Frequencies
Advanced 2.5D/3D hetero-integration technologies at GINTI, Tohoku University
Analysis of glass interposer PDN and proposal of PDN resonance suppression methods
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor
New concept of TSV formation methodology using Directed Self-Assembly (DSA)
Surface passivation of Cu cone bump by self-assembled-monolayer for room temperature Cu-Cu bonding
High density interconnect bonding of heterogeneous materials using non-collapsible microbumps at 10 μm pitch
Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer
Bumpless interconnects formed with nanowire ACF for 3D applications
TSV optimization for BEOL interconnection in logic process
The benefits of 3D networks-on-chip as shown with LDPC decoding
Advanced Development of Squeeze Effect Non-Contact Handling Tool for Semiconductor Chips
Noise performance improvement through optimized stacked layer of liner structure around the TSV in 3D IC
Thermal analysis of multi-layer functional 3D logic stacks
Bond Strength Optimization of Plasma Activated Low Temperature Oxide-Oxide Fusion Bonding Through Thermocycling
A very low area ADC for 3-D stacked CMOS image processing system
Fast, Accurate Assembly-Level Physical Verification of 3DIC Packages
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC
Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects
Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)
Current and future 3D activities at Fraunhofer
Stress management strategy to limit die curvature during silicon interposer integration
Si interposer build-up options and impact on 3D system cost
Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation
A Novel Multi-Chip Cooling System Using Direct-on-Chip Jet Impingemnt for High-Performance Interposer Package
A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration
Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack
Which interconnects for which 3D applications? Status and perspectives
Development of ultra-thinning technology for logic and memory heterogeneous stack applications
Fabrication and packaging of microbump interconnections for 3D TSV
On-chip checkpointing with 3D-stacked memories
Towards high density 3D interconnections
Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology
3D DfT architecture for pre-bond and post-bond testing
Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement
Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique
Thermal analysis and modeling of 3D integrated circuits for test scheduling
Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration
3D SRAM Design & Optimization with Open Source Memory Compiler
Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking
A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors
An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems
Impact of TSV integration on 14nm FinFET device performance
Effects of Argon and Nitrogen ion Bombardments on Sputtered and Electroplated Cu Surfaces for Cu Bonding Application
Power delivery network design and optimization for 3D stacked die designs
High density Cu-TSVs and reliability issues
3D integration and challenges for advanced RF and microwave systems: EDA perspective
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance
3D floorplanning considering vertically aligned rectilinear modules using T ∗ -tree
3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)
The development and evaluation of RF TSV for 3D IPD applications
Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias
Guard-ring monitoring system for inspecting defects in TSV-based data buses
A 3D-Integration method to compensate output voltage degradation of boost converter for compact Solid-State-Drives
Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs
Analysis of graphene and CNT based finned TTSV and spreaders for thermal management in 3D IC
A successful implementation of dual damascene architecture to copper TSV for 3D high density applications
Front-side mid-level Tungsten TSV integration for high-density 3D applications
High density and reliable packaging technology with Non Conductive Film for 3D/TSV
Architectural evaluation of 3D stacked RRAM caches
An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration
Analysis of thermal stress distribution for TSV with novel structure
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking
Multichip CMOS Image Sensor Structure for Flash Image Acquisition
3D TSV processes and its assembly/packaging technology
Development of feed-forward design system for rapid SiP design
Direct Sputtered Copper Seed Layer Formation on Low Dielectric Resin to Reduce Transmission Loss
Development of via-last 3D integration technologies using a new temporary adhesive system
Real-time thermal management of 3D multi-core system with fine-grained cooling control
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding
Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure
Impact of Cu Pad Density on Cu-CMP and Bonding Yield for Chip-to-Wafer Hybrid Bonding
SiGe BiCMOS Technology with Embedded Microchannels based on Cu Pillar PCB Integration Enabling sub-THz Microfluidic Sensor Applications
Using 3D-COSTAR for 2.5D test cost optimization
Evaluation of wafer level Cu bonding for 3D integration
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tilting
Cost effectiveness of 3D integration options
Vias-last process technology for thick 2.5D Si interposers
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates
Quality in 3D assembly - Is "Known Good Die" good enough?
High density backside tungsten TSV for 3D stacked ICs
Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies
Hierarchical Design Methodology and Optimization for Proximity Communication based Contactless 3D ThruChip Interface
3D interconnection using copper direct hybrid bonding for GaN on silicon wafer
An Introduction to Marching Memory (MM)
Design platform and tools for 3D IC integration
3D integration demonstration of a wireless product with design partitioning
3D ICs: An opportunity for fully-integrated, dense and efficient power supplies
Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI
2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013
Junction-level thermal extraction and simulation of 3DICs
Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures
3D R&D technology for the future voyage in Japan
Thermal correlation between measurements and FEM simulations in 3D ICs
Multi-ANN embedded system based on a custom 3D-DRAM
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC
Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs
Effect of planarity on the 3D integration in 3-D integrated CMOS image sensor
A routerless system level interconnection network for 3D integrated systems
Logic-on-logic 3D integration and placement
3D X-ray microscopy: A near-SEM non-destructive imaging technology used in the development of 3D IC packaging
Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration
Low temperature Au-Au bonding with VUV/O3 treatment
Investigation of effects of metalization on heat spreading in bump-bonded 3D systems
Investigation of the Influence of Material Properties on Warpage and Solder Joint Reliability of 2.5D & FO Package
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing
Using TSVs for thermal mitigation in 3D circuits: Wish and truth
Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration System
Modeling and compare of through-silicon-via (TSV) in high frequency
3D Stacked Spin Qubit by TCAD Simulations
Advances toward reliable high density Cu-Cu interconnects by Cu-SiO 2 direct hybrid bonding
Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer
A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections
Influential factors in low-temperature direct bonding of silicon dioxide
Novel methodology for 3D MEMS-IC design and co-simulation on MEMS microphone smart system example
High temperature bonding solutions enabling thin wafer process and handling on 3D-IC manufacturing
3D on-chip memory for the vector architecture
Activation of Copper Surfaces by VUV - Redox Method Using a Xenon Excimer Lamp
Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in Package
Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes
Low-temperature bonding of LSI chips to PEN film using Au cone bump for heterogeneous integration
Technology impact analysis for 3D TCAM
HIBS - Novel inter-layer bus structure for stacked architectures
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing
Front to backside alignment for TSV based 3D integration
New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM)
Proposed Standardization of Heterogenous Integrated Chiplet Models
3D integration of standard integrated circuits
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack
Detectability of Resistive Open Defects with Analog Relaxation Oscillators Under Unit-to-Unit Variations of Dies
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers
Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs
IEEE International 3D Systems Integration Conference, 3DIC 2023, Cork, Ireland, May 10-12, 2023
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
A front-illuminated stacked global-shutter CMOS image sensor with multiple chip-on-chip integration
Wafer-level hybrid bonding technology with copper/polymer co-planarization
IME's capabilities and programs in 2.5D/3DIC
First integration of Cu TSV using die-to-wafer direct bonding and planarization
Long term efficacy of ultra-thin Ti passivation layer for achieving low temperature, low pressure Cu-Cu Wafer-on-Wafer bonding
Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications
Exploring AMBA AXI on-Chip interconnection for TSV-based 3D SoCs
Thermal Stress Tracking in Multi-Die 3D Stacking Structure by Finite Element Analysis
A Novel Direct Transfer Bonding Process with Particle Less Tapes for Die to Wafer Integration
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration
Thin wafer handling - Study of temporary wafer bonding materials and processes
Evaluation of fine grain 3-D integrated arithmetic units
A built-in supply current test circuit for electrical interconnect tests of 3D ICs
Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects
A Virtual Platform for Object Detection Systems
Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon
Novel inter layer dielectric and thermal TSV material for enhanced heat mitigation in 3-D IC
Stacked SOI pixel detector using versatile fine pitch μ-bump technology
Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack
Face-to-face bus design with built-in self-test in 3D ICs
Temperature-aware online testing of power-delivery TSVs
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar
Low temperature bonding for 3D interconnects
Intermediate BEOL process influence on power and performance for 3DVLSI
Numerical investigations for 3D power supply on chip by coupling of thermal-fluid, circuit, and electromagnetic field simulations
Keynote speakers day 1: 3D integration with TSV interconnects: Technology trends & market analysis
Characterization of Ozone-Ethylene Radical Pretreatment for Hybrid Bonding without Water Rinsing Processes
Air-gap/SiO2 liner TSVs with improved electrical performance
Die to wafer 3D stacking for below 10um pitch microbumps
Design Considerations and Fabrication Challenges of Surface Electrode Ion Trap with TSV Integration
Fully integrated transformer less floating gate driver for 3D power supply on chip
W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress
High performance 3D stacked DRAM processor architectures with micro-fluidic cooling
CMIT - A novel cluster-based topology for 3D stacked architectures
Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure
Design and analysis of on-interposer active power distribution network for an efficient simultaneous switching noise suppression in 2.5D IC
Coordinating 3D designs: Interface IP, standards or free form?
Low temperature (<180 °C) bonding for 3D integration
Glass interposer with high-density three-dimensional structured TGV for 3D system integration
A Low-Cost and Low-Temperature Method to Realize Carbon Nanotube Conductor in Through-Silicon-Via
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system
A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack
Low temperature CMOS compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC integration
SiN used as a Stressor in Germanium-On-Insulator Substrate
Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias
Material improvement for ultrathin-wafer handling in TSV creation and PECVD process
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV
Electrical performance of high bandwidth memory (HBM) interposer channel in terabyte/s bandwidth graphics module
Pixel detectors in 3D technologies for high energy physics
TSV etching and VDP process integration for high reliability
Equipment challenges and solutions for diverse temporary bonding and de-bonding processes in 3D integration
Wireless power transfer using resonant inductive coupling for 3D integrated ICs
A miniaturized heterogeneous wireless sensor node in 3DIC
Performance evaluation of 3D stacked multi-core processors with temperature consideration
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI
Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs Wafers
Timing analysis and optimization for 3D stacked multi-core microprocessors
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology
Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping
3DIP: An iterative partitioning tool for monolithic 3D IC
Heat Transfer in Nanostructured Si and Heat Flux Control Technique
Design of a 3-D stacked floating-point adder
A capacitive coupling interface with high sensitivity for wireless wafer testing
Aluminum-Germanium eutectic bonding for 3D integration
Effect of frequency in the 3D integration of a PZT-actuated MEMS switch using a single crystal silicon asymmetric beam
High density 3D integration by pre-applied Inter Chip Fill
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs
Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination
Substrate monitoring system for inspecting defects in TSV-based data buses
Crystallinity Dependence of Long-Term Reliability of Electroplated Gold Thin-Film Interconnections
Development of pixel detectors for particle physics using SLID-ICV interconnection technology
Analysis of 3D interconnect performance: Effect of the Si substrate resistivity
Invited talk: Some challenges in scaling 3D ICs to a broader application set
Considerations of TSV effects on next-generation super-high-speed transmission and power integrity design for 300A-class 2.5D and 3D package integration
200°C direct bonding copper interconnects : Electrical results and reliability
Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module
Active Si interposer for 3D IC integrations
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations
Integration of intra chip stack fluidic cooling using thin-layer solder bonding
A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation
TSV process solution for 3D-IC
Selection of underfill material in Cu hybrid bonding and its effect on the transistor keep-out-zone
Antioxidative Cu Electrodeposition for 3D Interconnects with Hybrid Bonding
ITAC: A complete 3D integration test platform
Extreme wafer thinning optimization for via-last applications
Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration
Copper-filled anodized aluminum oxide a potential material for chip to chip bonding
Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test
TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication
Graphite-based heat spreaders for hotspot mitigation in 3D ICs
3D interconnected technology by high speed copper electrodeposition using diallylamine levelers