yusuke1997/dblp-id-title huggingface dataset:
Making sense of thermoelectrics for processor thermal management and energy harvesting
EExNAS: Early-Exit Neural Architecture Search Solutions for Low-Power Wearable Devices
Energy optimization of multi-level processor cache architectures
Minimizing power dissipation of cellular phones
System implications of integrated photonics
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs
Phase-aware adaptive hardware selection for power-efficient scientific computations
Understanding the impact of laptop power saving options on user satisfaction using physiological sensors
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization
NoC frequency scaling with flexible-pipeline routers
PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory Architectures
Invited paper: Ultra-low energy security circuit primitives for IoT platforms
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
Matched public PUF: ultra low energy security platform
Power invariant vector compaction based on bit clustering and temporal partitioning
Composite sequence compaction for finite-state machines using block entropy and high-order Markov models
A probabilistic technique for full-chip leakage estimation
Resource area dilation to reduce power density in throughput servers
Cooperative shared resource access control for low-power chip multiprocessors
Power-saving color transformation of mobile graphical user interfaces on OLED-based displays
Lucid infrared thermography of thermally-constrained processors
AridWalk: Efficient Graph Random Walks on a Resource-Limited Computational Storage Device
Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations
Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache
Remote progressive firmware update for flash-based networked embedded systems
Energy reduction in queues and stacks by adaptive bitwidth compression
Creating a power-aware structured ASIC
Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling
Clustered voltage scaling technique for low-power design
Power conversion efficiency characterization and optimization for smartphones
Cascaded carry-select adder (C 2 SA): a new structure for low-power CSA design
A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding
Logic design for low-voltage/low-power CMOS circuits
A 1-V piecewise curvature-corrected CMOS bandgap reference
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
An energy-efficient checkpointing mechanism for out of order commit processor
CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices
OS-based Resource Accounting for Asynchronous Resource Use in Mobile Systems
Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs
Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump
Low-power radix-4 divider
Variability of flip-flop timing at sub-threshold voltages
Energy-per-cycle estimation at RTL
Power-aware operand delivery
Retiming-based logic synthesis for low-power
Issues and directions in low power design tools: an industrial perspective
Timing-driven row-based power gating
Sound event detection with binary neural networks on tightly power-constrained IoT devices
STINT: selective transmission for low-energy physiological monitoring
A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability
A new 4-2 adder and booth selector for low power MAC unit
Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems
Leakage current cancellation technique for low power switched-capacitor circuits
Innovation for Future Connected Compute
Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures
Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors
Ultra-low-voltage operation: device perspective
Energy-aware demand paging on NAND flash-based embedded storages
Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency
3D-Aware Low Power High-level Resource Binding and Co-Design
Low power synthesis of dual threshold voltage CMOS VLSI circuits
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers
A micro-power mixed signal IC for battery-operated burglar alarm systems
CLOVER: Carbon Optimization of Federated Learning over Heterogeneous Clients
Switched-capacitor boost converter design and modeling for indoor optical energy harvesting with integrated photodiodes
upGEMV: A Bandwidth-Efficient and Scalable GEMV Accelerator for PIM Systems
BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs
Analysis of power consumption in memory hierarchies
Energy-efficient instruction set synthesis for application-specific processors
Charge recovery on a databus
Data driven signal processing: an approach for energy efficient computing
On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers
Inter-program optimizations for conserving disk energy
Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
Improving disk reuse for reducing power consumption
RVO: Unleashing SSD's Parallelism by Harnessing the Unused Power
An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
Efficient Machine Learning on Encrypted Data Using Hyperdimensional Computing
Voltage scheduling under unpredictabilities: a risk management paradigm
A microarchitectural-level step-power analysis tool
A dual-V DD boosted pulsed bus technique for low power and low leakage operation
Standby power management for a 0.18µm microprocessor
Modeling and automating selection of guarding techniques for datapath elements
On the optimum design of regulated cascode operational transconductance amplifiers
A robust edge encoding technique for energy-efficient multi-cycle interconnect
A secure and low-energy logic style using charge recovery approach
Unlocking the true potential of 3D CPUs with micro-fluidic cooling
Circuit design in nano-scale CMOS era: opportunities & challenges
Interlaced accumulation programming for low power DSP
Diet SODA: a power-efficient processor for digital cameras
A programmable implementation of neural signal processing on a smartdust for brain-computer interfaces
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009
Pipeline stage unification: a low-energy consumption technique for future mobile processors
Reducing Power Consumption of GPGPUs Through Instruction Reordering
An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms
Reducing variability in chip-multiprocessors with adaptive body biasing
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM
Triangle Counting in the Temporal Domain
Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit
A low-power CSCD asynchronous viterbi decoder for wireless applications
SOC designs in the energy conscious era
Dynamic algorithm transformation (DAT) for low-power adaptive signal processing
Optimizing total power of many-core processors considering voltage scaling limit and process variations
Integrated solar energy harvesting and storage
LogStore: toward energy-proportional storage servers
Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networks
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's
High-speed low-power frequency divider with intrinsic phase rotator
Wearable Devices and Low-Power Design for Smart Health Applications: Challenges and Opportunities
High-level synthesis techniques for reducing the activity of functional units
A low power high performance switched-current multiplier
A multi-model power estimation engine for accuracy optimization
Directed Acyclic Graph-based Neural Networks for Tunable Low-Power Computer Vision
Decorrelating (DECOR) transformations for low-power adaptive filters
Insights from Biology: Low Power Circuits in the Fruit Fly
Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation
HR 3 AM: A Heat Resilient Design for RRAM-based Neuromorphic Computing
Energy-efficient code generation for DSP56000 family (poster session)
Design of fine-grained sequential approximate circuits using probability-aware fault emulation
Low power RF integrated circuits: principles and practice
Power and performance tradeoffs using various caching strategies
Accurate battery lifetime estimation using high-frequency power profile emulation
Hybrid energy storage system integration for vehicles
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems
Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies
Fine-grain CAM-tag cache resizing using miss tags
Low power high level synthesis by increasing data correlation
Unicorn-CIM: Unconvering the Vulnerability and Improving the Resilience of High-Precision Compute-in-Memory
A Technology-Agnostic Method for Digital LDO Synthesis and Layout Automation
Minimizing Redundant Checkpoint Triggers for Efficient Intermittent Systems
Exploiting the locality of memory references to reduce the address bus energy
Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications
Entropic bounds on FSM switching
Low power architecture for high speed infrared wireless communication system
Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach
Understanding the critical path in power state transition latencies
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Multi-Objective Optimization for Floating Point Mix-Precision Tuning
An ilp based approach to reducing energy consumption in nocbased CMPS
Achieving utility arbitrarily close to the optimal with limited energy
A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode
Survey of low power techniques for ROMs
Approximate memory compression for energy-efficiency
A 20.98TOPS/W Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator
Next-generation wireless technologies trends for ultra low energy
SENIN: An energy-efficient sparse neuromorphic system with on-chip learning
Power exploration for dynamic data types through virtual memory management refinement
Learning to manage combined energy supply systems
Flexibility and low power: a contradiction in terms?
CAM-CIM: A Hybrid Compute-in-Memory Using Content-Addressable Memory with Subword Split Mapping for Reduced ADC Resolution
QMLP: An Error-Tolerant Nonlinear Quantum MLP Architecture using Parameterized Two-Qubit Gates
ThermTap: An online power analyzer and thermal simulator for Android devices
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers
An Energy-Efficient, Yet Highly-Accurate, Approximate Non-Iterative Divider
Future directions in clocking multi-ghz systems
Energy-Efficient Frequency Selection Method for Bio-Signal Acquisition in AI/ML Wearables
Minimum supply voltage for bulk Si CMOS GSI
Sub-threshold design: the challenges of minimizing circuit energy
Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits
Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems
Energy efficient turbo decoding for 3G mobile
Ferroelectric Transistor based Non-Volatile Flip-Flop
A low-leakage dynamic multi-ported register file in 0.13mm CMOS
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Serial sub-threshold circuits for ultra-low-power systems
Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory
STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
STM versus lock-based systems: an energy consumption perspective
CMOS front-end LNA-mixer of micropower RF wireless systems
J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor
A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy
A low-power design methodology for high-resolution pipelined analog-to-digital converters
Low-power color TFT LCD display for hand-held embedded systems
Electroid-oriented adiabatic switching circuits
Penalty for power reduction -: performance or schedule or yield?
Dynamic power management for streaming data
Dissecting Xeon + FPGA: Why the integration of CPUs and FPGAs makes a power difference for the datacenter: Invited Paper
An adaptive serial-parallel CAM architecture for low-power cache blocks
Low power light-weight embedded systems
PVS: passive voltage scaling for wireless sensor networks
Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems
Active Cell Balancing for Life Cycle Extension of Lithium-Ion Batteries under Thermal Gradient
Microprocessor power delivery challenges in the Nano-Era
Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems
Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay
Experimental characterization of in-package microfluidic cooling on a System-on-Chip
Page policy control with memory partitioning for DRAM performance and power efficiency
Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support
Analysis and design of low-phase-noise ring oscillators
All watts considered
Variation aware performance analysis of gain cell embedded DRAMs
Pulsed-latch-based clock tree migration for dynamic power reduction
Ultra-low power challenges for the next generation ASIC
Coordinating Communication, Technology and Design in the IOT Era
A low-power SRAM using bit-line charge-recycling technique
Power exploration for data dominated video applications
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V T sense amplifiers
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures
The new (system) balance of power and opportunities for optimizations
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
Design Techniques for Ultra-low Power Cryogenic CMOS for Quantum Computing Applications
Analysis of super cut-off transistors for ultralow power digital logic circuits
Soft error and energy consumption interactions: a data cache perspective
A novel slope detection technique for robust STTRAM sensing
Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware
Leakage power modeling and optimization in interconnection networks
App-Oriented Thermal Management of Mobile Devices
A 92.4dB SNDR 24kHz ΔΕ modulator consuming 352μW
ePredictNet: Low Cost Error Prediction Neural Network
Low power FPGA design using hybrid CMOS-NEMS approach
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
Joint exploration of architectural and physical design spaces with thermal consideration
Reducing the leakage and timing variability of 2D ICcs using 3D ICs
A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008
On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing
Tracking the power in an enterprise decision support system
Energy-Efficient Machine Learning Acceleration: From Technologies to Circuits and Systems
Single stage static level shifter design for subthreshold to I/O voltage conversion
A carbon nanotube transistor based RISC-V processor using pass transistor logic
Design and Logic Synthesis of a Scalable, Efficient Quantum Number Theoretic Transform
A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications
A reconfigurable dual output low power digital PWM power converter
CARMA: Context-Aware Runtime Reconfiguration for Energy-Efficient Sensor Fusion
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator
HeTraX: Energy Efficient 3D Heterogeneous Manycore Architecture for Transformer Acceleration
Analysis and mitigation of variability in subthreshold design
What is the state of the art in commercial EDA tools for low power?
VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997, Monterey, California, USA, August 18-20, 1997
A pareto-algebraic framework for signal power optimization in global routing
Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension
Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology
DRAM power-aware rank scheduling
Driver pre-emphasis techniques for on-chip global buses
Hard real-time scheduling for low-energy using stochastic data and DVS processors
Power management from cores to datacenters: where are we going to get the next ten-fold improvements?
Static and dynamic co-optimizations for blocks mapping in hybrid caches
Chameleon: Adapting throughput server to time-varying green power budget using online learning
Detailed placement for leakage reduction using systematic through-pitch variation
SACS: A Self-Adaptive Checkpointing Strategy for Microkernel-Based Intermittent Systems
Efficient adaptive voltage scaling system through on-chip critical path emulation
Low power self-timed Radix-2 division (poster session)
On load latency in low-power caches
Voltage scheduling problem for dynamically variable voltage processors
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors
Design and analysis of 3D IC-based low power stereo matching processors
A low power normalized-LMS decision feedback equalizer for a wireless packet modem
Low-power detection of sternocleidomastoid muscle contraction for asthma assessment and control
Low-power considerations in the design of bluetooth (invited talk)
Distributed DVFS using rationally-related frequencies and discrete voltage levels
2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017
Temperature-aware Adaptive VM Allocation in Heterogeneous Data Centers
Hardware Trojans in fdSOI
Device and technology optimizations for low power design in deep sub-micron regime
Platform-dependent, leakage-aware control of the driving current of embedded thermoelectric coolers
Energy optimization techniques in cluster interconnects
TLB index-based tagging for cache energy reduction
A low power architecture for wireless multimedia systems: lessons learned from building a power hog
Non volatile memories to enable system power scaling
Ambient intelligence: industrial research on a visionary concept
ReDEEM: A heterogeneous distributed microarchitecture for energy-efficient reliability
Word-interleaved cache: an energy efficient data cache architecture
Thermal-aware layout planning for heterogeneous datacenters
High-performance, low-power design techniques for dynamic to static logic interface
Semiconductor spintronics: Switching spins at low voltage
A 0.75-mW analog processor IC for wireless biosignal monitor
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor
Energy-Efficient Missing Data Recovery in Wearable Devices: A Novel Search-Based Approach
MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks
Selective instruction compression for memory energy reduction in embedded systems
A Compact, Low Power Transprecision ALU for Smart Edge Devices
Hotspot monitoring and Temperature Estimation with miniature on-chip temperature sensors
SimICT: A fast and flexible framework for performance and power evaluation of large-scale architecture
WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs
Increasing minimum operating voltage (V DDmin ) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators
Robust Low Power Clock Synchronization for Multi-Die Systems
X-IMM: Mixed-Signal Iterative Montgomery Modular Multiplication
SIMES: A simulator for hybrid electrical energy storage systems
4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS
A low energy architecture for fast PN acquisition
Algorithm and architecture of a 1V low power hearing instrument DSP
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces
A clock delayed sleep mode domino logic for wide dynamic OR gate
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist
Single-phase source-coupled adiabatic logic
ML-INSIGHT: Machine Learning for Inrush Current Prediction and Power Switch Network Improvement
CMOS front end components for micropower RF wireless systems
Dynamic current modeling at the instruction level
Design of multi-mode 4-switch buck-boost controller
A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm
Complexity reduction in an nRERL microprocessor
An energy efficient GPGPU memory hierarchy with tiny incoherent caches
Post-silicon power characterization using thermal infrared emissions
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Technology and design challenges for low power and high performance
Gate-level current waveform simulation of CMOS integrated circuits
Energy reduction in multiprocessor systems using transactional memory
Design and analysis of metastable-hardened flip-flops in sub-threshold region
Resiliency analysis and improvement of variational quantum factoring in superconducting qubit
In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches
A non-uniform cache architecture for low power system design
An Energy-Efficient Computational Model for Uncertainty Management in Dynamically Changing Networked Wearables