yusuke1997/dblp-id-title huggingface dataset:
A systematic approach to the time-domain computation of the impulse response and post-initial conditions of causal LTI systems at the origin
Digitizing of UWB signals based on frequency channelization
A low complexity motion compensated frame interpolation method
A 22-mW 435-MHz differential CMOS high-gain LNA for subsampling receivers
An Evolutionary Search Algorithm for Adaptive IIR Equalizer
On mismatch properties of MOS and resistors calibrated ladder structures
Increasing the Speed and Saving Mulitpliers in Block Parallel Digital Filters by a Linear Transformation
The simplest memristor in the world
Active IC Metering of Digital Signal Processing Subsystem with Two-Tier Activation for Secure Split Test
Structure generation and design of tracking ADCs
Convergence of Hopfield Neural Network for Orthogonal Transformation
A K-Band Quadrature Oscillator with Ultra Low Amplitude/Phase Mismatches
High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule
Efficient Detection and Mitigation Schemes for Speculative Side Channels
A Programmable Image Processing System using FPGA
Analysis of traveling wave and transversal analog adaptive equalizers
Using Modified Bessel Functions For Calculations of Drain Current Harmonics In a MOS Transistor Operating in Moderate Inversion
Waves and patterns in delayed oscillatory networks
Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter
Enabling high-speed turbo-decoding through concurrent interleaving
Active self supplied AC-DC converter for piezoelectric energy scavenging systems with supply independent bias
A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs
High-speed and low-power programmable frequency divider
On the influence of static power consumption in multicore embedded systems
Low power high linearity transmitter front-end for 900 MHz Zigbee applications
Redundancy Pruning for Binary Hyperdimensional Computing Architectures
Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery
Rapid block-matching motion estimation using modified diamond search algorithm
High Speed RLS Using Scaled Tangent Rotations (STAR)
A new algorithm for optimum bit loading with a general cost
Design and Implementation of a Low-power Baseband-system for RFID Tag
Effect of relative delay on the dissipated energy in coupled interconnects
A novel decoder for Sigma-Delta modulator providing both high resolution and low latency
Design of soft-output Viterbi decoders with hybrid trace-back processing
Sparsity estimation in image compressive sensing
Influence Of camera imaging pipeline on stereo-matching quality: An experimental study
Interference analysis on Resonant Inductive Coupled Wireless Power Transfer links
Novel rate-distortion modeling for H.264/AVC and its application in two-pass VBR coding
A retargetable tool-suite for the design of application specific instruction set processors using a machine description language
An on-off temporal filter circuit for visual motion analysis
High-PF and ultra-low-THD power factor correction controller by sinusoidal-wave synthesis and optimized THD control
Programmable synaptic weights for an aVLSI network of spiking neurons
An End-to-end Computer Vision System Architecture
High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices only
An oscillator-based true random number generator with jitter amplifier
Mixed Signal Frequency Mixers with Intermodulation Product Cancellation
SQNR Improvement of Incremental Zoom ADCs with Raised-Order CoI Filter and Dither Injection
A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution
An N × N Multiplier-Based Multi-Bit Strong PUF using Path Delay Extraction
Gated threshold compensated noncoherent PPM receiver for UWB impulse radio
Calculation of MOSFET distortion using the transconductance-to-current ratio (gm/ID)
Energy-Efficient Intelligent Pulmonary Auscultation for Post COVID-19 Era Wearable Monitoring Enabled by Two-Stage Hybrid Neural Network
A constraint-based placement refinement method for CMOS analog cell layout
Signal Selection Methods for Efficient Multi-Target Correction
A universal CMOS voltage interface circuit
Image processing using diffusion processes
A New Viterbi Decoder Design for Code Rate K/N
Visual attention data for image quality assessment databases
Thermal conduction path analysis in 3-D ICs
Hardware Implementation of Low Complexity High-speed Perceptron Block
A 2-6GHz broadband CMOS low-noise amplifier with current reuse topology utilizing a noise-shaping technique
Optimal stochastic resonance under low signal-to-noise ratio circumstances
A Frequency-Domain Transfer Model for Predicting FM Error of FMCW Radar Chirp Generators
A CMOS fully-integrated wireless power receiver for autonomous implanted devices
An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies
Low power SOVA architecture using bi-directional scheme
Responsive Visualisation - A Tool for Analog Designers
An active leakage-injection scheme applied to low-voltage SRAMs
Systematic Generation of Flicker and Thermal Noise Canceling Circuits
A 2-Dimensional active cochlear model for analog VLSI implementation
A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC
Adaptive quantization parameter cascading for hierarchical video coding
A transformer-less duplexer with out-of-band filtering for same-channel full-duplex radios
The successive occurrence of torus doubling
Efficient traffic balancing for NoC routing latency minimization
A low-power mixing DAC IR-UWB-receiver
High temperature SOI CMOS technology and circuit realization for applications up to 300°C
New high performance sub-1 V circuit technique with reduced standby current and robust data holding
Experimental Demonstration of Optical OFDM With Polarity-Separated Transmission in Rolling Shutter Based Visible Light Communication
A study on effect of blocking and bypass diodes on partial shaded PV string with compensating circuit using voltage equalizer
Wide-range integrated gas sensor interface based on a resistance-to-number converter technique with the oscillator decoupled from the input device
Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs
Hardware Platform and Implementation of a Real-time Multi-user MIMO-OFDM Testbed
Design of a CMOS image sensor with pixel-level ADC in 0.35µm process
A low power interface circuit for resistive sensors with digital offset compensation
A neuron-MOS parallel associator for high-speed CDMA matched filter
Effect of the Transistor Mismatches on the Performance of Fully-Differential OTAS
A 80V output voltage boost converter with low voltage ripple for Avalanche Photodiode(APD)
ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision
3D reconstruction from planar points: A candidate method for authentication of fingerprint images captured by mobile devices
Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature
Wave repetitive process approach to a class of ladder circuits
An Accurate Sense-FET-based Inductor Current Sensor with Wide Sensing Range for Buck Converters
Solvable 2-dimensional rational chaotic map defined by Jacobian elliptic functions
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers
Filterbank-based fast parallel algorithms for real-valued discrete gabor expansion and transform
A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM
A fully-differential CMOS Clapp VCO for IEEE 802.11a applications
A sequential algorithm for robust parameter estimation and enhancement of noisy speech
An efficient design for FIR filters with variable precision
Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domain
Power flow based allocation procedures for voltage security and transmission losses in deregulated power markets
An event-driven massively parallel fine-grained processor array
Rate distortion optimization in the scalable video coding
FIR DACs in CT Incremental Delta-Sigma Modulators
General Modular Multiplication by Block Multiplication and Table Lookup
Can Overclocking Detect Hardware Trojans?
Human Height Estimation Using Visual Geometry and Feature Learning
Towards High Frequency Switched-Current Filters in CMOS and GaAs Technology
Bootstrapped Complementary Switches for High-Precision Sampling
Through-The-Barrier Communications in Isolated Class-E Converters Embedding a Low-K Transformer
A Scale-Reductive Pooling with Majority-Take-All for Salient Object Detection
VLSI Design of Sequential Minimal Optimization Algorithm for SVM Learning
A truncated polynomial interpolation theorem and its application to the WLS design of IIR filters
Global behaviour analysis of a DC-DC boost power converter operating with constant power load
A VLSI design of sensor node for wireless image sensor network
A 4.5 μW 2.4 GHz wake-up receiver based on complementary current-reuse RF detector
A 1.02 ppm/°C Precision Bandgap Reference with High-order Curvature Compensation for Fluorescence Detection
Regular small-world cellular neural networks: key properties and experiments
Reduced Complexity MIMO Equal Gain Precoding
A high-resolution and fast-conversion time-to-digital converter
A Secure Data-Toggling SRAM for Confidential Data Protection
A Precision CMOS Voltage Reference with Enhanced Stability for the Application to Advance VLSIs
Quantum Accelerated Computer Architectures
A 1-V CMOS receiver front-end for high-speed SI-POF links
Efficient design of modified Booth multipliers for predetermined coefficients
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation
Cosine and sine modulated FIR filter banks utilizing the frequency-response masking approach
Multimode oscillations in a four fully-interconnected Van Der Pol oscillators
Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate Systems
A 65-nm low power ECG feature extraction system
A wave-pipelined CMOS associate router for communication switches
Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication
Joint code-encoder-decoder design for LDPC coding system VLSI implementation
A 1.5 V high folding rate current-mode folding amplifier for folding and interpolating ADC
A Low-Power Analog Hardware Sigmoid-based Neural Network for Biomedical Applications
Cell library for automatic synthesis of analog error control decoders
Contourlet domain image modeling by using the alpha-stable family of distributions
Implementation of a novel read-out strategy based on a Wilkinson ADC for a 16×16 pixel X-ray detector array
A Semi-Analytical Procedure to Describe Lossless Two-Ports with Mixed Lumped and Distributed Elements
Convergence behaviours of an adaptive step-size constant modulus algorithm for DS-CDMA receivers
Canards in a slow-fast continuous piecewise linear vector field
Performance comparison of DWT scheduling alternatives on programmable platforms
Dielectric absorption of low-k materials: extraction, modelling and influence on SAR ADCs
A learning-based video compression on low-quality data by unscented kalman filters with Gaussian process regression
Block-matching evaluation in digital architectures for motion estimation
Demonstration of CAD Deployability for GPR Based Small-Signal Modelling of GaN HEMT
Feedback Cancellation in Hearing Aids: Results from using Frequency-Domain Adaptive Filters
A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator
An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices
Live demonstration: CASCADES.1: A flow-graph-based symbolic analyzer
High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory
Modelling and analysis of vibration energy harvesters with charge pump conditioning circuits
Joint Design of a DS-UWB Modulator and Chaos-Based Spreading Sequences for Sensor Networks
A 1.5 V CMOS VGA based on pseudo-differential structures
The RunBot Architecture for Adaptive, Fast, Dynamic Walking
Classification of Non-Tumorous Facial Pigmentation Disorders using Deep Learning and SMOTE
A 1.8V 2.4GHz CMOS on-chip impedance matching low noise amplifier for WLAN applications
A real frequency technique optimizing broadband equalizer elements
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC
A Programmable Systolic-Array AI Accelerator System with High-Performance Model Quantization and Heart Disease Classification Algorithm Design
Interpolation of discrete periodic nonuniform decimation using alias unraveling
ASIC Implementation of Efficient 512-Neuron 256K-Synapses Digital Neuromorphic Processor with On-Chip Encoding in 22nmFDX
On the Three-dimensional Orthogonal Drawing of Outerplanar Graphs
Benchmarking photon-limited performance of optic flow processing algorithms
Artificial Neural Network Based Post-CTS QoR Report Prediction
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing
A wavelet balance approach for steady-state analysis of nonlinear circuits
Design and analysis of fuzzy logic based robust PID controller for PWM-based switching converter
High-Level Simulation for Spiking Neuromorphic Computing Systems
Cell segmentation and NC ratio analysis of third harmonic generation virtual biopsy images based on marker-controlled gradient watershed algorithm
Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance
A 0.7-1.5GHz Tunable Papoulis All-Pole Low-Pass Filter in 22nm CMOS FDSOI
A 2.5 Gbit/s CMOS optical receiver frontend
Feedforward compensation technique for all digital phase locked loop based synthesizers
Reconstruction of bandlimited signals from noisy data by adaptive thresholding
Reducing Logic Locking Key Leakage through the Scan Chain
Towards spiking analog hardware implementation of a trajectory interpolation mechanism for smooth closed-loop control of a spiking robot arm
Subband blind equalization using wavelet filter banks
A novel current controlled tri-state boost converter with superior dynamic performance
Jitter limitations on multi-carrier modulation
A Digital Jitter Correction Technique For High-Speed ADC-Based Communication Links
Cybersecurity and the electric grid: Innovation and intellectual property
Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos
More or less controllers to synchronize a Kuramoto-oscillator network via a pacemaker?
Craniofacial landmarks extraction by Partial Least Squares Regression
Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization
Effect of Parasitic Components on Dynamic Performance of Power Stages of DC-DC PWM Buck and Boost Converters in CCM
New physics-based compact electro-thermal model of power diode dedicated to circuit simulation
Fast intra block copy (IntraBC) search for HEVC screen content coding
High-speed CRC design for 10 Gbps applications
A low-leakage twin-precision multiplier using reconfigurable power gating
A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement
A 100Gb/s quad-rate transformer-coupled injection-locking CDR circuit in 65nm CMOS
Recently developed approaches for solving blind deconvolution of MIMO-IIR Systems: Super-exponential and eigenvector methods
Extending Winograd's Small Convolution Algorithm to Longer Lengths
A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter
A New Non Competitive Unsupervised Neural Network for Clustering
A Reconfigurable 5-Mode Inductively Assisted Switched-Capacitor DC-DC Converter with 0.5-to-2.5V Output Voltage Range
All Pass Function Based Stability Test for Delta-Operator Formulated Discrete-Time Systems
High performance spatial-temporal de-interlacing technique using interfield information
An improved stochastic model for the least mean fourth (LMF) adaptive algorithm
State space modeling for sub-threshold SRAM stability analysis
A micropower band-pass filter for use in bionic ears
A SHA-Less Front-end Stage Structure Suitable for Time-Interleaved Pipeline ADC
Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops
A new dual-field elliptic curve cryptography processor
Ballistic Deflection Transistors and the Emerging Nanoscale Era
A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems
An Interface ASIC for an Atmospheric-Pressure MEMS Gyroscope with PLL-Based Phase Adjustment and SC Amplitude Regulation
Low depth carry lookahead addition using charge recycling threshold logic
Zero-derivative method of analog controller design applied to step-down DC-DC converters
Pattern detection in noisy signals
An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS Transistors
Kernel-based mixture of experts models for linear regression
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
Fetal heart rate monitoring system with mobile internet
Combining CNN and MLP for Plant Pathology Recognition in Natural Scenes
AxLEAP: Enabling Low-Power Approximations Through Unified Power Format
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes
An efficient max-log MAP algorithm for VLSI implementation of turbo decoders
A frequency digitizer based on the continuous time phase domain noise shaping
An efficient architecture for 1-D discrete biorthogonal wavelet transform
Parallel sparse matrix solver for direct circuit simulations on FPGAs
An Efficient method to collapse the spatial networks
A systolic-array architecture for first-order 4-D IIR frequency-planar digital filters
Reconfigurable implementation of recursive DCT kernels for reduced quantization noise
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs
ASIC design of fast IP-lookup for next generation IP router
Vaccinating SIS epidemics in networks with zero-determinant strategy
Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs
CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples
A practical algorithm for turbo-decoding enhancement
A Mixed Analog-Digital Class-D Amplifier with Third-Order Loop Filter for Audio Applications
A 0.18µm CMOS low-noise elliptic low-pass continuous-time filter
Very low-voltage class AB CMOS precision voltage and current rectifiers
System analysis and energy model for radio-triggered battery-less monolithic wireless sensor receiver
Alternative subband signal structures for complex modulated filter banks with perfect reconstruction
A CMOS current feedback operational amplifier with active current mode compensation
Illumination-invariance and nonlocal means based super resolution
A polynomial-based division algorithm
A low power survivor memory unit for sequential Viterbi-Decoders
A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver
A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture
Fast transient response CFA-based LDO regulator
Bifurcation stabilization for nonlinear systems with double-zero eigenvalues
Redundant multiscale structure coding for error resilient video completion
A Technique for Measuring Picosecond Delays Using Phase Modulation
CASL hypervisor and its virtualization platform
Balanced spatial and frequency localised 2-D nonseparable wavelet filters
Signal waveform monitoring for power systems
High efficiency architecture of escot with pass concurrent context modeling scheme for scalable video coding
A variation-aware simulation framework for hybrid CMOS/spintronic circuits
A 2 1 / 2 -Dimensional Systolic Array Architecture
Advanced chaos-based frequency modulations for clock signals EMC tuning
Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems
Simulation Study of Time-Average-Frequency based Clock Signal Driving Systems with Embedded Digital-to-Analog Converters
SRAM portless bitcell and current-mode reading
Requirements and constraints in MPEG-4 binary shape decoder at main profile
On-chip current sensing technique for CMOS monolithic switch-mode power converters
Retinal ganglion cell software and FPGA model implementation for object detection and tracking
Live Demonstration: ECG-PPG Wearable Cardiovascular Monitoring System Design Using Human Body Communication
Hybrid cache architecture replacing SRAM cache with future memory technology
Live demonstration: Real time objects tracking using a bio-inspired processing cascade architecture
BITLITE: Light Bit-wise Operative Vector Matrix Multiplication for Low-Resolution Platforms
A unified procedure for locating the stabilizable regions of two-dimensional switched systems
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs
Performance characteristics of an ultra-low power VCO
A wide tuning range VCO using capacitive source degeneration
Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators
Comparative analysis of contrast enhancement algorithms in surveillance imaging
Behavioral modeling and simulation of weakly nonlinear sampled-data systems
Nonlinearity and dynamics in RF Oscillators: Analysis and design implications
Live Demonstration: Optical Communications using Solar Cells
The effect of clock jitter on the DR of Sigma Delta modulators
A performance bound for a cascade LMS predictor
A highly efficient reconfigurable architecture for an UTRA-TDD mobile station receiver
Performance Study by Changing the Internal Structure of Hysteresis Reservoir Computing
Design of an SVD engine for 8×8 MIMO precoding systems
New Spatially Adaptive Wavelet-based Method for the Despeckling of Medical Ultrasound Images
A compact, low-power, fully analog implantable microstimulator
A new k-groups neural network
A design space exploration for integrated switching power converters
Silk Piezoelectric Tactile Sensors: The Way Forward to Developing Intelligent Implantable Sensors
Clock jitter compensation for current steering DACs
Synthesis of low coefficient sensitivity digital filters using genetic programming
Tunable analog loudspeaker crossover network
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications
Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM
Application-oriented SHA-256 hardware design for low-cost RFID
Determination of main system parameters of FM-DCSK telecommunications system
A high voltage gain quasi Z-source isolated DC/DC converter
A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping
Rapid bit-error-rate measurements of infrared communication systems
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection
Discrete optimization for error feedback network using lower bound estimation
On a new type of extended Petri nets and its applications
Smart AD and DA converters
Bearing estimatino without using complex transform
Cloud-Edge Architecture for 4K 360-Degree Video Encoding in FoV-based Live DASH
Complementary code keying for RAKE-based indoor wireless communication
A 55nm 1GHz one-cycle-locking de-skewing circuit
Secure dynamic authentication of passive assets and passive IoTs using self-powered timers
Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up mode
A 24GHz low-power CMOS receiver design
An entropy coding method for floating-point texture coordinates of 3D mesh
Detecting community structure of networks using evolutionary coordination games
A DC to 12.5 MHz Fully Integrated and Galvanically Isolated Shunt-Resistor Current Sensor
Optimum probability model selection using Akaike's information criterion for low power applications
Estimation of the Stability Margin of 2-D State-Space Discrete Systems
A multiband CMOS RF front-end for 4G WiMAX and WLAN applications
Low Swing - Low Frequency Rotary Traveling Wave Oscillators