yusuke1997/dblp-id-title huggingface dataset:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
F-C3D: FPGA-based 3-dimensional convolutional neural network
AdapNoC: A fast and flexible FPGA-based NoC simulator
FPGAs BIST Evaluation
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
Portable module relocation and bitstream compression for Xilinx FPGAs
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs
A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs
Behavioural Language Compilation with Virtual Hardware Management
A floating-point Extended Kalman Filter implementation for autonomous mobile robots
An FPGA Implementation of Real-Time Object Detection with a Thermal Camera
Off-line placement of hardware tasks on FPGA
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing
NetFPGA - rapid prototyping of high bandwidth devices in open source
Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management
Specializing FGPU for Persistent Deep Learning
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
The Design of a Coprocessor Board Using Xilinx's XC6200 FPGA - An Experience Report
Automating Customisation of Floating-Point Designs
An OCM based shared Memory controller for Virtex 4
Characterisation of feasibility regions in FPGAs under adaptive DVFS
Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software Development
Building Low-Latency Order Books with Hybrid Binary-Linear Search Data Structures on FPGAs
Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis
Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack
Parallel Hardware Implementation of Connected Component Tree Computation
A scalable FPGA-based design for field programmable large-scale ion channel simulations
Experimental multi-FPGA GNSS receiver platform
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern
Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
Highly Automated FPGA Synthesis of Application-Specific Protocol Processors
Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator
Capture and Visualisation of Radio Signals with an Open Source, Single Chip Spectrum Analyser
In search of agile hardware
A Reconfigurable Instruction Memory Hierarchy for Embedded Systems
Efficient multi-standard cognitive radios on FPGAs
Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit
A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support
COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA
High level structural description of streaming applications
An fpga based open source network-on-chip architecture
A technology mapper for depth-constrained FPGA logic cells
Rapid modular assembly of Xilinx FPGA designs
CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design
FPGA-Based Emulation: Industrial and Custom Prototyping Solutions
Hight-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM)
A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures
A Stream Processor Architecture Based on the Configurable CEPRA-S
A Reconfigurable Viterbi Decoder for a Communication Platform
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs
An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements
An FPGA-based high-throughput stream join architecture
A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor
Quantifying and mitigating the costs of FPGA virtualization
Compact CLEFIA Implementation on FPGAS
A reconfigurable sensor-data processing system for personal robots
A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters
A Framework for Intrinsic Evolvable Systems
Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract
Compiling text analytics queries to FPGAs
Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD
General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems
Fast parallel implementation of DFT using configurable devices
Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach
Satisfiability on reconfigurable hardware
CVC: The C to RTL compiler for callback-based verification model
A Specific Scheduling Flow for Dynamically Reconfigurable Hardware
Digital hilbert transformers for FPGA-based phase-locked loops
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling
A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures
A rapid prototyping framework for nano-photonic accelerators
An FPGA-Based Architecture to Simulate Cellular Automata with Large Neighborhoods in Real Time
Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
Aging monitoring with local sensors in FPGA-based designs
Adaptive Real-Time Systems and the FPAA
Customizing Low-Precision Deep Neural Networks for FPGAs
High-precision self-characterization for the LUT burn-in information leakage threat
Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS
A dynamic partial reconfigurable overlay concept for PYNQ
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs
Thermal aware FPGA architectures and CAD
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs
Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures
PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs
Modular Architecture for Real-Time Astronomical Image Processing with FPGAs
Accelerating the ATDCA Algorithm for Endmember Extraction from Hyperspectral Imagery with Intel oneAPI for FPGAs
Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA
Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration
Demonstration of a partial reconfiguration based microphone array network emulator
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
A VHDL Library to Analyse Fault Tolerant Techniques
IPsec-Protected Transport of HDTV over IP
A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings
Examination of the concept of a row-column separated median filter
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler
An efficient run-time router for connecting modules in FPGAS
Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97)
An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory
CNP: An FPGA-based processor for Convolutional Networks
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
An Optoelectronic 3-D Field Programmable Gate Array
Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
L4: An FPGA-Based Accelerator for Detailed Maze Routing
Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System
Placing partially reconfigurable stream processing applications on FPGAs
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings
Mapping Applications onto Reconfigurable Kress Arrays
Performance assessment of FPGAs as HPC accelerators using the FPGA Empirical Roofline
An implementation method of the box filter on FPGA
Tabu Search: Ultra-Fast Placement for FPGAs
A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs
A new deadlock-free fault-tolerant routing algorithm for NoC interconnections
Storage Allocation for Diverse FPGA Memory Specifications
Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices
A Leak Resistant Architecture Against Side Channel Attacks
Mapping of P4 match action tables to FPGA
A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules
Shared memory heterogeneous computation on PCIe-supported platforms
An Efficient Technique for Mapping RTL Structures onto FPGAs
A reconfigurable coprocessor for a PCI-based real time computer vision system
Low-latency TCP/IP stack for data center applications
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access
A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA
Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem
Hardware conversion of neural networks simulation models for neural processing accelerator implemented as FPGA-based SoC
Reconfiguration-based time-to-digital converter for Virtex FPGAs
Parallel feature extraction and heterogeneous object-detection for multi-camera driver assistance systems
On Channel Architecture and Routability for FPGAs Under Faulty Conditions
The MD5 Message-Digest Algorithm in the XILINX FPGA
P4: A platform for FPGA implementation of protocol boosters
Optimizing hardware design for Human Action Recognition
An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems
BIST Based Interconnect Fault Location for FPGAs
Parameterized Logic Power Consumption Models for FPGA based Systems
A Generic Architecture for Integrated Smart Transducers
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
A novel motion estimation power reduction technique
Improving External Memory Access for Avalon Systems on Programmable Chips.
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation
Revisiting the Newton-Raphson Iterative Method for Decimal Division
High speed fixed point dividers for FPGAs
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities
FPGA-based design of a self-checking TMR voter
A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAs
A Statistical Analysis Tool for FPLD Architectures
Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs
33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023
ERMES: Efficient Racetrack Memory Emulation System based on FPGA
Efficient Priority-Queue Data Structure for Hardware Implementation
Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation
CFSA: An Efficient CPU-FPGA Synergies Accelerator for Neural Radiation Field Rendering
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures
A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers
FPGA Finite-Difference Time-Domain solver for thermal simulation
An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion
Sampling from the exponential distribution using independent Bernoulli variates
FPGAs and the Era of Field Programmability
Data Dependent Circuit Design: A Case Study
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)
Data Dependent Circuit for Subgraph Isomorphism Problem
Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs
Exploring the Versal AI Engines for Signal Processing in Radio Astronomy
Teaching FPGA system design via a remote laboratory facility
Towards Coarse-Grained Reconfigurable Approximate Computing with CGRAgen
Accelerating Continual Learning on Edge FPGA
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
NoC-AXI interface for FPGA-based MPSoC platforms
UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging
Fast Switching Activity Estimation for HLS-Produced Dataflow Circuits
Detection Module in a Complementary Set of Sequences-Based Pulse Compression System
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals
Run-Time Management of Dynamically Recongigurable Designs
Application specific multi-port memory customization in FPGAs
Scalable Defect Tolerance Beyond the SIA Roadmap
Self-Timed FPGA Systems
Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs
Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware
Fast and accurate Single Bit Error injection into SRAM Based FPGAs
Rapid codesign of a soft vector processor and its compiler
Rapid implementation of a partially reconfigurable video system with PYNQ
A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor
Influence of Locig Block Layout Architecture on FPGA Performance
An FPGA Based Hybrid Processor Emulation Platform
On-Chip Communication Topology Synthesis for a Shared Memory Architecture
Cost Effective 2×2 Inner Product Processors
Learning-based interconnect-aware dataflow accelerator optimization
Biomedical image processing and reconstruction with dataflow computing on FPGAs
High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication
Automating the design of mLUT MPSoPC FPGAs in the cloud
Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory
High Performance Communication on Reconfigurable Clusters
FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines
FORC: A High-Throughput Streaming FPGA Accelerator for Optimized Row Columnar File Decoders in Big Data Engines
A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation
Parallel FPGA routing: Survey and challenges
Efficient data-stream management for shared-memory many-core systems
Using FPGAs as Control Support in MIMD Executions
A programming model and runtime system for approximation-aware heterogeneous computing
A reconfigurable data-localised array for morphological algorithms
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support
Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support
Automatic generation of application-specific accelerators for FPGAs from python loop nests
Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping
Mining Association Rules with systolic trees
Efficient techniques and methodologies for embedded system design usign free hardware and open standards
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems
Enhancing stochastic computations via process variation
ARMHEx: A framework for efficient DIFT in real-world SoCs
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology
From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains
FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems
High Speed Document Clustering in Reconfigurable Hardware
Quark Routing
Runtime-quality tradeoff in partitioning based multithreaded packing
The MOLEN rho-mu-Coded Processor
Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
FPGA Based Imaging Particle Detector Trigger System
An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics
A low overhead fault tolerant FPGA with new connection box
Exploring architecture parameters for dual-output LUT based FPGAs
Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
FPGA-Accelerated Object Detection Using Edge Information
High-Performance Integer Factoring with Reconfigurable Devices
Accurate and flexible flow-based monitoring for high-speed networks
Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach
Keynote: High performance computing based on FPGAS
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA
Extending DSP-Boards with FPGA-Based Structures of Interconnection
Fitop-Trans: Maximizing Transformer Pipeline Efficiency through Fixed-Length Token Pruning on FPGA
Accelerated Wire-Speed Packet Capture at 200 Gbps
It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures
Design and Implementation of a CFAR Processor for Target Detection
Erlang Inspired Hardware
Communication Synthesis for Reconfigurable Embedded Systems
Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data
OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs
Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge
Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration
A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware
NoC Implementation in FPGA Using Torus Topology
Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings
Automated Masking of FPGA-Mapped Designs
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology
Activation Function Architectures for FPGAs
Educating hardware design - From primary school children to postgraduate engineers
Interconnect for commodity FPGA clusters: Standardized or customized?
Automatic generation of FPGA hardware accelerators using a domain specific language
Designing for Xilinx XC6200 FPGAs
Formal Verification of a Reconfigurable Microprocessor
HAIL: A Hardware-Accelerated Algorithm for Language Identification
Floating point HOG implementation for real-time multiple object detection
Criticality-aware scrubbing mechanism for SRAM-based FPGAs
Constraint-based Hierarchical Placement of Parallel Programs
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
On Optimal Irregular Switch Box Designs
Adaptive Sequential Monte Carlo approach for real-time applications
Modeling and synthesis of a Dynamic and Partial Reconfiguration controller
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler
NetFlow Probe Intended for High-Speed Networks
A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits TM
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms
A toolset for the analysis and optimization of motion estimation algorithms and processors
FPGA-based all-digital transmitters
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
Resource Optimal Squarers for FPGAs
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings
Modular Exponent Realization on FPGAs
Hardware implementation of motion blur removal
XILINX4000 Architecture-Driven Synthesis for Speed
Fast and robust hashing for database operators
On Optimum Designs of Universal Switch Blocks
System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs
EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU
ARMHEx: A hardware extension for DIFT on ARM-based SoCs
Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing
Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing
Reconfigurable Logic for Fault-Tolerance
A novel net-partition-based multithread FPGA routing method
Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays
Tile size selection for optimized memory reuse in high-level synthesis
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems
Run-Time Adaptive Flexible Instruction Processors
Exploring compact design on high throughput coarse grained reconfigurable architectures
A software configurable coprocessor-based state-space controller
A Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Work and Weight Load Balancing
CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping
Implementing a Fieldbus Interface Using an FPGA
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths
An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment
Image Processing on a Custom Computing Platform
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems
Using Design Hierarchy to Improve Quality of Results in FPGAs
Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage