yusuke1997/dblp-id-title huggingface dataset:
Single-filter multi-color CMOS fluorescent contact sensing microsystem
Very fast programmable CNN based on FG-inverter
Constructive homotopy methods for finding all or multiple DC operating points of nonlinear circuits and systems
Subset averaged median estimators
On the stability of the convex combinations of the stable irrational polynomials
Hardware Implementation of PCM-Based Neurons with Self-Regulating Threshold for Homeostatic Scaling in Unsupervised Learning
Adaptive gain control for speech quality improvement and echo suppression
Functional Text Pattern Generation for Asynchronous Circuits
Machine Learning-Based Design of Load-Independent WPT Systems
Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits
Optimal data distribution in FeFET-based computing-in-memory macros
Automatic circuit adjustment technique for process sensitivity reduction and yield improvement
New Architectures for Low-Cost Public Key Cryptography on RFID Tags
A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic
A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning
A study on the performance, complexity tradeoffs of block turbo decoder design
An acoustic-phonetic feature-based system for automatic phoneme recognition in continuous speech
Silicon spin qubits: A scalable solution for quantum computing
Controlling limit cycles in planar dynamical systems: a nonsmooth bifurcation approach
Nonlinear behavior of electrostatic discharge protection structures under high-power microwave excitation: Modeling and simulation
Charge-pump reducing current mismatch in DLLs and PLLs
Optimization of active circuits for substrate noise suppression
A 110pJ/Bit Star- 16QAM 915MHz Band Ultra-Low Power Receiver Based on Polar Architecture
Live demonstration: Electronic doubler of electricity
A low bit-rate hybrid DWT-SVD image-coding system (HDWTSVD) for monochromatic images
Learning-based Congestion Control for Internet Video Communication over Wireless Networks
BER-optimal analog-to-digital converters for communication links
A self-learning framework to detect the intruded integrated circuits
A resistor-free temperature-compensated CMOS current reference
Ripple correlation control, with some applications
Third-Order Reconnection-Less Electronically Reconfigurable Multifunctional Filter
Simulation and Modelling of Nonlinear Magnetics
Normalized confidence factors for robust direction of arrival estimation
Bitwise ELD Compensation in Δ∑ Modulators
CMOS Circuits for On-Chip Capacitance Ratio Testing or Sensor Readout
Fixed-point configurable hardware components for adaptive filters
K-band phase locked hair-pin oscillator
Tunnel diode integrated circuits
Bayesian procedure for the Detection of Damped Signals
A 0.9-V input PWM DCM boost converter with low output ripples and fast load transient response based on a novel square-root voltage mode (SRVM) control approach
Adaptive motion estimation order for frame rate up-conversion
ECG Signal Processing and Analysis for Data Arising from Rehab Patients Doing Exercises
Pipelined implementations of polar encoder and feed-back part for SC polar decoder
Efficient spectral method for disjoint bi-decompositions of Boolean functions
Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers
Ultrasound image despeckling in the contourlet domain using the Cauchy prior
Analog Layout Placement for FinFET Technology Using Reinforcement Learning
A 28V-to-3.3V, 2 A, Fully Monolithic 3-Level Hybrid Converter in 130 nm HV-CMOS
An evaluation of transmission line models incorporating longitudinal temperature variations
Audio source separation by source localization with Hilbert spectrum
Performance evaluation of error-correcting scheme without redundancy code for noncoherent chaos communications
A new Spice-oriented frequency-domain optimization technique
A hybrid self-testing methodology of processor cores
A 0.7-V 100-µW audio delta-sigma modulator with 92-dB DR in 0.13-µm CMOS
Calculation of non-mixed second derivatives in multirate systems through signal flow graph techniques
Digital filters with sparse coefficients
An improved critical-band transform processor for speech applications
Single supply CMOS Up level shifter for dual voltage system
On the Existence of the Double Scroll Attractor for the Chua's Circuit with a Smooth Nonlinearity
High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding
Finding all solutions of piecewise-linear resistive circuits using the simplex method
Speech emotion recognition based on entropy of enhanced wavelet coefficients
Coupling Convolution, Transformer and Graph Embedding for Motor Imagery Brain-Computer Interfaces
Concurrent estimation of amplifier nonidealities and excess loop delay in continuous-time sigma-delta modulators
CAD tools for designing 3D integrated systems
20 dBm CMOS class AB power amplifier design for low cost 2 GHz-2.45 GHz consumer applications in a 0.13µm technology
Monitoring Radios: Dynamics And Emerging Trends
Lumped passive circuits for 5GHz embedded test of RF SoCs
SoC processor for real-time object labeling in life camera streams with low line level latency
Synchronization of fractional interval counter in non-integer ratio sample rate converters
Source localization using TDOA with erroneous receiver positions
Recover image coding loss with LMS filtering
In-Memory Transformer Self-Attention Mechanism Using Passive Memristor Crossbar
Data Throughput Optimization in the IEEE 802.15.4 Medical Sensor Networks
A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS
A 2.4GHz low power wireless transceiver analog front-end for endoscopy capsule system
Dominant harmonic modification with data adaptive filter based algorithm for robust pitch estimation
Simple criteria to evaluate converter dynamics suitability for operation in active power factor correction systems
Identification and monitoring of biological neural network
Paired comparison for subjective multimedia quality assessment: Theory and practice
Massively parallel KD-tree construction and nearest neighbor search algorithms
A Sub-1V Low-Power High-Speed Static Frequency Divider
Experiment of 3-Phase N-Path Filter for Hum Noise Suppression
Robust stability of a class of nonlinear time-varying discrete systems
ViTA: A Vision Transformer Inference Accelerator for Edge Applications
High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering
Acoustic feedback neutralization in digital hearing aids - A two adaptive filters-based solution
FlexPE: Flexible Processing Elements for Workload Optimization and Acceleration on FPGAs
A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems
An Ion-to-Frequency ISFET Architecture for Ultra-Low Power Applications
A Discrete Approach to Dynamic Vision with Single-Photon Detectors
Design of a fully integrated array of high-voltage digital-to-analog converters
Development of autonomous, mobile micro-electro-mechanical devices
A phase-noise model for nonlinear piezoelectrically-actuated MEMS oscillators
Photon-Detection Timing-Jitter Model in Verilog-A
A novel multiplying D/A converter stage with low sensitivity to amplifier gain
Extended bandwidth open-loop VCO based ADC using Interleaving with a single VCO channel
Programmable-gain amplifiers based on AC couplings for continuous reception
On the design of RF-DACs for random acquisition based reconfigurable receivers
TTCN: A new approach for low-power split-row LDPC decoders
Limit Cycles and Bifurcations in Nonlinear Oscillatory Networks
An overview of the encoding tools in the MPEG-4 reference software
Stratified-Medium Plane-Wave Ultrasound Image Reconstruction via Frequency-Domain Migration
A 9.6 TOPS/W Vision Transformer Processor with Hierarchical Token Merging for Similarity-Driven Difference Computing
Robust stabilization of control systems using piecewise linear Lyapunov functions and evolutionary algorithm
Approaches to the implementation of noise-coupling in continuous-time Delta-Sigma modulators
New Dual-Input Voltage Controlled Integrator/Differentiator and their Digital Control
A New Neuromorphic Computing Approach for Epileptic Seizure Prediction
Lumped/distributed single-pulse matched filter for radar applications based on wave digital filters
Pitch estimation of noisy speech signals using EMD-fourier based hybrid algorithm
Gradient-based PU size selection for HEVC intra prediction
Graph cut video object segmentation using histogram of oriented gradients
An embedded low power reconfigurable fabric for finite state machine operations
RTL Synthesis for Systolic Arrays
Intrinsic signatures for scanned documents forensics : Effect of font shape and size
Fast Simulation of Circuits With Recursive Elements: Application to a BESS
Synchronization phenomena in coupled system of RC transistor oscillators
A Dual-Slope BlueFMCW Radar for Simultaneous Mitigation Against Close-in DRFM and Frequency Domain Spoofing Attacks
A LDO with 5-nA Quiescent Current and Improved Transient Response within a 50-mA Load Current Range
On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulators
AC-DC converters with bi-directional power flow and some possible applications
Analysis of Signal Transmission through Time-Varying Inductively Coupled Links
I-V Curve Tracer Based Intermittent Maximum Power Point Tracking for Photovoltaic System
A hardware security solution against scan-based attacks
Hardware-Software Co-Design for Face Recognition on FPGA SoCs
Fast RLS Fourier analyzers in the presence of frequency mismatch
Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis
New dual-loop topology for ring VCOs based on latched delay cells
An area-efficient TFT-LCD column driver with DAC sharing technique
Recurrent neural networks in systems identification
A Rail-to-Rail Input Class-AB Linear Amplifier with Improved Bandwidth and Slew-Rate for Envelope Tracking Supply Modulators
Auto-LUT: Auto Approximation of Non-Linear Operations for Neural Networks on FPGA
Scalable memory-less architecture for string matching with FPGAs
Spatio-temporal Super-resolution Network: Enhance Visual Representations for Video Captioning
Analog Crosstalk Cancellation for High Data Rate Communication Links
A high-level dynamic-error model of a pipelined analog-to-digital converter
An Automatic Gain Control Topology for CMOS Digital Radio Receiver
Highly parallel bitmap-based regular expression matching for text analytics
FPGA implementation of a frequency adaptive learning SOFM for digital color still imaging
On the axiomatic foundations of circuit theory
High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays
Properties of analog systems with varying parameters [averaging/low-pass filters]
Jitter-Power minimization of digital frequency synthesis architectures
A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters
Multiple operating points in a CMOS log-domain filter
Low Latency Architectures for Wave Digital Filters
An accurate RTL power estimation considering power library unevenness
Scaling Co-Packaged Optical Interconnects Using Hybrid 2.5D/3D Integration
A 0.18µm-CMOS near-end crosstalk (NEXT) noise canceller utilizing tunable active filters for 4-PAM/20Gbps throughput backplane channels
Designing high-throughput hardware accelerator for stream cipher HC-128
Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics
A 2.4 GHz 82 dB-Omega fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topology
Low-voltage amplifier with improved linearity using triode region MOSFET
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight
A Modified Interleaving Resonant Switched Capacitor Converter with Reduced Output Resistance and In-Situ Startup
Compact designs of mixcolumns and subbytes using a novel common subexpression elimination algorithm
Performance analysis of the Bayesian beam former on the CDMA reverse channel
Data hiding in error diffused color halftone images
Power conversion schemes in nanometer CMOS mixed-signal SoCs
Analysis of Reconfigurable Tap Changing Transformer Model through Analog Emulation
WCDMA channel selection filter with high IIP2
A continuous tracking algorithm for long-term memory motion estimation
Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications
Gap Channel Routing with Fixed Wires
Design methodology of multistage time-domain logic speculation circuits
Parametric Analysis of Weighted Order Statistic Filters
RISC-V Barrel Processor for Deep Neural Network Acceleration
A 2-V 11-bit incremental A/D converter using floating gate technique
Improved and fast algorithms for intra 4×4 mode decision in H.264/AVC
A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHz
High Dynamic Range CMOS Imager for Colorimetric Gas Sensors
An alternative natural gradient approach for multichannel blind deconvolution
An energy/bandwidth/area efficient frequency-domain OOK transmitter with phase rotated modulation
3D integrated sensors in silicon-on-sapphire CMOS
Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC
EMI common-mode (CM) noise suppression from self-calibration of high-speed SST driver using on-chip process monitoring circuit
A Switched-Current Double Sampling Bilinear Z-Transform Filter Technique
Current-Mode ISFET Array with Row-Parallel ADCs for Ultra-High Speed Ion Imaging
Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator
A novel approach to real time multimedia forwarding over heterogeneous networks
Frustrated synchronization in two coupled polygonal oscillatory networks
A power efficient neural spike recording channel with data bandwidth reduction
Post-layout redundant wire insertion for fixing min-delay violations
Live Demonstration: Multi-Laptop HEVC Encoding
A 1-V CMOS output stage with high linearity
Dynamic building model for demand response
A low-offset class-AB CMOS operational amplifier
Fabrication of a dual-layer aluminum nanowires polarization filter array
Towards a nearly optimal synthesis of power bridge commands in the driving of AC motors
EDGE transmitter alternative using nonlinear polar modulation
A 1-change-in-4 delay-insensitive interchip link
Robust video multicast with joint network coding and AL-FEC
A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes
A Method for Swift Selection of Appropriate Approximate Multipliers for CNN Hardware Accelerators
Power, clock, and data recovery in a wireless neural recording device
Neural network reconstruction and prediction of chaotic dynamics
Syntax and discontinuity based error concealment
Optimal polynomial predictors with application specific prefilters
A Strong 4 × 4 S-Box Using an Enhanced Tent Map
On the VLSI Implementation of the International Data Encryption Algorithm IDEA
Live demonstration: State-dependent sensory processing in networks of VLSI spiking neurons
Efficient frame-level pipelined array architecture for full-search block-matching motion estimation
On Synchronization of Memristive Neural Networks with Cooperative and Competitive Interactions
DPA resistance of charge-sharing symmetric adiabatic logic
A novel charge-metering method for voltage mode neural stimulation
Region of interest determined by perceptual-quality and rate-distortion optimization in JPEG 2000
Phototransistor image sensor in silicon on sapphire
Layer-wise supervised neural network for face alignment with multi-task regularization
A real-time realization of MPEG-4 video decoder
Watermarking curves using 2D mesh spectral transform
16-Channel modular platform for automatic control and reconfiguration of complex photonic circuits
Measurement and mismatch-modelling of semiconductor devices in BiCMOS technology
An Analog Radial Basis Function Circuit Using a Compact Euclidean Distance Calculator
An Improved Point-to-Multipoint GB(N) ARQ Scheme for High Speed Satellite Communications
C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations
0.08mm 2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications
Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge
A Blockchain-Based Crypto-Anchor Platform for Interoperable Product Authentication
Memristive Non-Idealities: Is there any Practical Implications for Designing Neural Network Chips?
Homogeneity Enhancement of Current-to-Frequency-Converters Operated in Sensor Array Applications
Design Techniques for Self-powered Microsystems
Opportunities and challenges for the virtual prototyping of synthetic biological functions
Co-simulation of RFIC with bondwire antenna via retarded PEEC method
Speaker direction tracking using microphones located at the vertices of equilateral-triangle
3D stacking for multi-core architectures: From WIDEIO to distributed caches
A 2-D silicon cochlea with an improved automatic quality factor control-loop
International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA
A 5.1-GHz CMOS PLL based integer-N frequency synthesizer with ripple-free control voltage and improved acquisition time
Low-complexity bit-serial constant-coefficient multipliers
A digitally skew correctable multi-phase clock generator using a master-slave DLL
A Trimming-Less External-RC Relaxation Oscillator With Self-Calibrating Current Reference for a SiC Active Gate Driver Application
CSL-YOLO: A Cross-Stage Lightweight Object Detector with Low FLOPs
A Fully Integrated NB-IoT Wake-Up Receiver Utilizing An Optimized OFDM 12-Point FFT Wake-Up Engine
Exponentially-modulated filter bank-based transmultiplexer
A second-generation single-chip stereo imager
A 13-Bit ENOB Fully Asynchronous Noise-Shaping SAR ADC With Coarse-Fine Comparison, Mismatch Error Shaping and Digital Prediction
Dynamic nonlinear threshold decomposition algorithm for implementing stack filters
Image restoration of JPEG coded images using mean removed classified vector quantization
The Architecture of the Intended Safety System for Intelligent Driving
A spectrum sensing method based on stratified sampling
Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels
A robust and correct computation for the curvilinear routing problem
A Novel Convolution Computing Paradigm Based on NOR Flash Array with High Computing Speed and Energy Efficient
Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
Squeeze-Excite Fusion Based Multimodal Neural Network for Sleep Stage Classification with Flexible EEG/ECG Signal Acquisition Circuit
Statistical analysis and design of chaotic switched dynamical systems
Robust chaos - the theoretical formulation and experimental evidence
Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems
On-chip inductor structures: a comparative study
An all-digital 50% duty-cycle corrector
Analysis of switched capacitor DC-DC step down converter
Blind separation of a class of nonlinear ICA models
Integrated RF sensors for electronic warfare applications
A Q-enhanced Active-RLC Bandpass Filter
CMOS gate modeling based on equivalent inverter
An 8-channel power-efficient time-constant-enhanced analog front-end amplifier for neural signal acquisition
A novel FPGA architectural implementation of pipelined thinning algorithm
On-chip template training for pattern matching by cellular neural network universal machines (CNN-UM)
A 120-160 GHz 28 mW LNA in 70-nm GaAs mHEMT Technology
Improving Comb Alias Rejection Using Modified Cosine Filters
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems
Modeling Kita-Hon HVDC Link for load frequency control of Eastern Japan 50-Hz power system based on application of the CampusWAMS
Feasibility study of on-chip class E DC-DC converter
An Experimental Reliability Study of Pseudo-Resistors in Biomedical Applications
A Novel Wireless Positioning Approach Based on Distributed Stochastic-Resonance-Enhanced Power Spectrum Fusion Technique
A Mixed-Precision RNS DNN Accelerator
Some structural conditions under which an RLC network is controllable over F(z)
Mixed RL-Huffman encoding for power reduction and data compression in scan test
Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature
Superpipelined reconfigurable hardware for DSP
Design of an improved interpolation filter using a trigonometric polynomial
Experimental evaluation of wide range injection locking in a CMOS RC oscillator
Missing image interpolation using sigma-delta modulation type of DT-CNN
A High Conversion Gain Wideband Mixer Design for UWB Applications
A wide linear range low-voltage transconductor
Optimal Transmitter Design for Short Distance Communication
A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM
An analog VLSI decoding technique for digital codes
System design considerations for sensor network applications
Enhanced direction of arrival estimation via reassigned space-time-frequency methods
Leakage Reduction in FPGA Routing Multiplexers
Stability of Mutually Inverse Rational 2-D Digital Transfer Functions
An FPGA-Based Architecture of True Random Number Generator for Network Security Applications
A Multi-standard Video Decoder for High Definition Video Applications
Shadow PUFs: Generating Temporal PUFs with Properties Isomorphic to Delay-Based APUFs
High performance IP core for HEVC quantization
Fast blind equalization with two-stage single/multilevel modulus and DD algorithm for high order QAM cable systems
A Fast CMOS Voltage-Controlled Ring Oscillator
A high-efficiency reconfigurable digital signal processor for multimedia computing
Graph theoretic or computational geometric research of cellular mobile communications
Speeding up the runtime performance for lossless image coding on GPUs with CUDA
Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001
A low-power cell-based-design multi-port register file in 65nm CMOS technology
Robust adaptive infinite impulse response notch filters: a novel state-space approach
Self-organising behavior of arrays of nonidentical Josephson junctions
The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity
Cache energy reduction by dual voltage supply
Division-free rasterizer for perspective-correct texture filtering
A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs
A High-Speed High-Precision Comparator with Offset Calibration for SHA_less Pipeline ADCs
A novel DPS integrator for fast CMOS imagers
A new SPIHT algorithm based on variable sorting thresholds
Power Reduction in Incremental ΔΣ ADCs Using a Capacitor Scaling Technique
Implantable biomedical device supplying by a 28nm CMOS self-calibration DC-DC buck converter with 97% output voltage accuracy
Single-phase capacitor clamped inverter with simple structure
A low-power active switched-capacitor loop filter for phase locked loops
Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI
A Sensor Network for Real-time Acoustic Scene Analysis
A signed spatial contrast event spike retina chip
A Multilevel N-Path Filter Topology for Low-Power Sinusoidal Clocking with Non-Overlapping Phases
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture
Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology
DNA-like Learning Algorithm of CNN Template Implementing Boolean Functions