yusuke1997/dblp-id-title huggingface dataset:
Person Detection by Low-rank Sparse Aggregate Channel Features
Design and Implementation of Spacecraft Network System Based on Dual-Information
The mutation seagull algorithm optimizes the speech emotion recognition of BP neural network
NSEHA: A Neighbor-based Secure and Efficient Handover Authentication Mechanism for 5G Networks
New Encryption Mechanism for Fax Communications
Multi-Target Distributed Maximum Correntropy Kalman Filter
Experimental Research on subcarrier index power modulation OFDM for visible light communication system
Observation on the Effect of CT Images Based on the Internet of Things Technology in the New Mode of High-quality Nursing Care
Research on high performance network application of short-range multi-mode optical interconnection
A Distributed Trajectory Compression Algorithm for Mobile Sensor Networks
Time series intrusion warning with GAN for missing data in CPS
Research on Architecture of Multi-space Telemetry Network System Based on Genetic Algorithm
Research on Neighbor Discovery Algorithms Based on Reinforcement Learning with Directional Antennas for Ad Hoc Networks
Differential privacy protection method for decision tree ensemble model
A Near-Field-Focused Reflectarray for Highly Efficient Wireless Power Transfer Application: An NFF Reflectarray for Highly Efficient WPT
Global Convergence in Large Sensor Networks under Hybrid Faults
WGLora: Efficient fine-tuning method integrating weights and gradient low-rank adaptation
Gaze Estimation by Integrating Eye and Head Representation
Lightweight Super-resolution Learning Model for Extremely Exposed Images
Distributed Rendering on Volunteered Mobile Resources
Effect of Specified Radiation Pattern on Wi-Fi Networks
Crytojacking Classification based on Machine Learning Algorithm
Near-Field Multi-Beam Design for Extremely Large-Scale RIS Assisted by Multi-Start Adam Algorithm
Cross-Domain Wi-Fi Sign Language Recognition with GANs
Design of Blockchain Smart Contract Based on Ring Signature
Joint Power and Bandwidth Allocation Method Based on Immune Genetic Algorithm for Inter-satellite Links in Beidou Navigation Satellite System
Reconfigurable Hardware Accelerator for Convolution Operations in Convolutional Neural Networks
Proceedings of the 5th International Conference on Communications and Broadband Networking, Bali, Indonesia, February 20 - 22, 2017
MAFIS Overlay Network: Towards a Secure Network for Mobile Automated Fingerprint Identification System over Virtual Private Network (VPN)
Research On Priority Differentiated Polling Mechanism with Limited Service in Wireless Sensor Networks: Extended Abstract
Hybrid Optical and Wireless System Using RoF-PON Based on OCS Modulation
Effectiveness of Formative E-assessment Procedure: Learning Calculus In Blended Learning Environment
A Novel Amplitude Spectrum Formation Algorithm for FRFT-TDCS
A new method of Cloud-based Computation Model for Mobile Devices: Energy Consumption Optimization in Mobile-to-Mobile Computation Offloading
Intrusion Detection based on Multi-measure Feature Selection and DSCA-BiLSTM in Fog Environment
Dynamic Computation Offloading Strategy with DNN Partitioning in D2D Multi-Hop Networks
A High Capacitive Ratio and Low Actuation Voltage RF MEMS Switch for Multi Band: Design and Performance Analysis
Investigation into User-Centric QoE and Network-Centric Parameters for YouTube Service on Mobile Networks
Distributed Algorithm for Computation Offloading in Mobile Edge Computing
Design and Performance Analysis of Wi-Fi Indoor Trilateral Location and Multilateral Location
Research on data access scheme based on attribute-based encryption in blockchain environment
Enhancing Biometric and Mutual Verification in Multi-server Three-factor User Remote Authentication Scheme with Elliptic Curve Cryptography
Influence of Time Delay Accuracy on MVDR Beamforming
A Novel Dynamic Practical Byzantine Fault Tolerance Protocol Based on Node Grouping
A Rapid De-mapping Method for 64-APSK
Phase retrieval with outliers based on smoothing function
An Efficient Privacy-Preserving Medical Record Query Scheme Over Oblivious Transfer in Wireless Body Area Network
Design of TCP Congestion Control in Data Center Networks Based on Stable Round Trip Time
A Mobile Camera Based Navigation System for Visually Impaired People
A Novel Blind Estimation Method of SFO based on QPSK
A PPO-based Channel Hopping Sequence Framework for Time Slot Channel Hopping
Abnormality Detection Approach using Deep Learning Models in Smart Home Environments
Research on Improving the Radiation Performance of Leaky Coaxial Cable
Study on scenario construction of natural disaster chain: A case study of extreme rainstorm on July 20 in Zhengzhou
Broadband Miniaturized Dual-linear Polarization Antenna Based on Short Circuit Loading
Distributed Capability Based Dynamic Path Authorization Scheme for SDSIN
Research on the Radiation Performance of Rectangular Leaky Waveguide with External Reflective Surface
Evaluation & Decision Models for Forest Management
A Compact Dual-Band Circularly Polarized RFID Reader/WLAN Antenna
Water Surface Target Detection Based on Improved YOLOv3 in UAV Images
Clustering-Based Data Collection Using Concurrent Transmission in Wireless Sensor Network
Cryptographic Randomness Test of the Modified Hashing Function of SHA256 to Address Length Extension Attack
A Lightweight and Effective Semantic Segmentation Network for Ethnic Clothing Images Based on DeepLab
A Caching Mechanism for SVRF-based Multicast Packet Forwarding Engines
The Survey of Software Display Technology for General Radar Terminal
Modified Roll-off Filter with Optimized Impulse Response for Reducing PAPR of Transmitted Signal
Coexistence of Multiple Partition Plan Based Physical Database Design
Study on Dynamic Optimization and Control Algorithm of Overlapping Phase of the Traffic Flow
Linear Registration and Robot Motion Planning
Developing a Leader-Follower Kinematic-Based Control System for a Cable-Driven Hyper-redundant Serial Manipulator
On the Snappability and Singularity-Distance of Frameworks with Bars and Triangular Plates
Using Monodromy to Statistically Estimate the Number of Solutions
Adapting Multi-agent Swarm Robotics to Achieve Synchronised Behaviour from Production Line Automata
On the Geometry of Some Localisation Problems in Robotics
Optimization of Cartesian Tasks with Configuration Selection
Active Matter as a Path Planning Interpreter
Calculating the Segmented Helix Formed by Repetitions of Identical Subunits
Synthesis of Planar Stiffness
2nd IMA Conference on Mathematics of Robotics, Manchester, UK, 9-11 September 2020
A Remarkable 8R-Mechanism
Zero-Sum Cycles in Flexible Non-triangular Polyhedra
Flexible Placements of Graphs with Rotational Symmetry
C-Space Analysis Using Tropical Geometry
Combinatorics of a Discrete Trajectory Space for Robot Motion Planning
On Orientation, Position, and Attitude Singularities of General 3R Chains
A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs
Embedded Operating System Optimization through Floating to Fixed Point Compiler Transformation
An Energy-Efficient Adaptive Multiple-Issue Architecture
Dynamic Hardware Management of the H264/AVC Encoder Control Structure Using a Framework for System Scenarios
COSSIM: An Open-Source Integrated Solution to Address the Simulator Gap for Systems of Systems
Auto-repair without test cases: How LLMs fix compilation errors in large industrial embedded code
Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs
Optimization of the Versatile Tensor Accelerator (VTA) Load Module in a Time-Triggered Memory Access
A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
AxBy: Approximate Computation Bypass for Data-Intensive Applications
Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis
Introducing Utilization Caps into Mixed-Criticality Scheduling
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique
FetchFlare: An Open-Source Strided Data Prefetcher for High-Performance Cache Hierarchies
Applying Formal Verification with Protocol Compiler
Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition Candidates
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization
Emission Analysis of Hardware Implementations
LeQC-At: Learning Quantization Configurations During Adversarial Training for Robust Deep Neural Networks
13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France
Compatibility Study of Compile-Time Optimizations for Power and Reliability
A Hardware-In-the-Design Methodology for Wireless Sensor Networks Based on Event-Driven Impulse Radio Ultra-Wide Band
Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool
High-Performance FPGA Architecture for Multi-line Beamforming in Ultrasound Applications
Fault Diagnosis in Integrated Circuits with BIST
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs
Pipelined Large Multiplier Designs on FPGAs
System Modeling in the COSMA Environment
A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time Applications
Be My Guess: Guessing Entropy vs. Success Rate for Evaluating Side-Channel Attacks of Secure Chips
CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-Chip
Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel Attacks
Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC
Network-on-Chip Architecture Exploration Framework
A Safety Certification Strategy for IEC-61508 Compliant Industrial Mixed-Criticality Systems Based on Multicore Partitioning
Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information
Development Flow for FPGA-Based Scalable Reconfigurable Systems
A Review of Near-Memory Computing Architectures: Opportunities and Challenges
Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing
A methodology for the design of AHB bus master wrappers
Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization
On LUT Cascade Realizations of FIR Filters
A Versatile PCM-Based Circuits Emulator and Its Use on Implementing Linear Algebra Functions
Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability
Formal Verification Methodology in an Industrial Setup
2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France
CELR: Cloud Enhanced Local Reconstruction from low-dose sparse Scanning Electron Microscopy images
Implementation of an Assignment Algorithm for Object Tracking on a FPGA MPSoC
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions
A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA
Energy-Optimized Elastic Application Distribution for Automotive Systems in Hybrid Cloud Architectures
Towards Component-Based Design of Safety-Critical Cyber-Physical Applications
Mobile Systems Secure State Management
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m)
Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication
Code is Ethics - Formal Techniques for a Better World
High Reliable Remote Terminal Unit for Space Applications
A Distributed BIST Scheme for NoC-Based Memory Cores
An Improved Input-Output Encoding Approach for Functional Decomposition
Higher-Order Side-Channel Protected Implementations of KECCAK
Cloud to Cable: A Drone Framework for Autonomous Power line Inspection
Performance and Timing Yield Enhancement using Highway-on-Chip Planning
Efficient Multiplication on Low-Resource Devices
Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis
Pipelined Genetic Architecture with Fitness on the Fly
A Hardware/Software Codesign for the Chemical Reactivity of BRAMS
Double Phase Fault Collapsing with Linear Complexity in Digital Circuits
A Parallel and Modular Architecture for 802.16e LDPC Codes
An FPGA based Tiled Systolic Array Generator to Accelerate CNNs
The Parallel Sieve Method for a Virus Scanning Engine
PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis
High-Level Synthesis in Latency Insensitive System Methodology
Feasibility of FPGA Accelerated IPsec on Cloud
Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems
Side-Channel Attack on the A5/1 Stream Cipher
Enhanced Configurable Parallel Memory Architecture
Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems
ASSEC: An Asynchronous Self-Checking RISC-based Processor
Predictable embedding of large data structures in multiprocessor networks-on-chip
OWQS: One-Way Quantum Computation Simulator
Finite State Machine Synthesis Based on Relay-Based Algorithm
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Design of an Event-Driven Residential Demand Response Infrastructure
An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra
A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints
Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture
Reconfigurable Fault-Tolerant System Sychronization
MultiPARTES: Multicore Virtualization for Mixed-Criticality Systems
Guards in Action: First-Order SCA Secure Implementations of Ketje Without Additional Randomness
Dynamic Power Estimation for Motion Estimation Hardware
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions
Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications
Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures
parMERASA - Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability
Automatic Construction of On-line Checking Circuits Based on Finite Automata
Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming
Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer
Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices
TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault Maps
Coverage-Driven Stimuli Generation
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Design-Space Exploration of Serialized Floating-Point Division for DLP Architectures
An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL)
A Modular Safety Case for an IEC-61508 Compliant Generic Hypervisor
APEnetX: A Custom NIC for Cluster Interconnects
Towards Exploring Vast MPSoC Mapping Design Spaces Using a Bias-Elitist Evolutionary Approach
Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor
Classification-Based Unified Cache Replacement via Partitioned Victim Address History
A Library to Model and Configure Large Regular Structures in SystemC
A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics
Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI
Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits
Towards Skin Cancer Self-Monitoring through an Optimized MobileNet with Coordinate Attention
Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis
COMP4DRONES Contributions for Enabling Safe and Autonomous Drones
Highly Parallel Sample Rate Converter for Space Telemetry Transmitters
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection
OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms
A Reconfigurable Architecture for Posit Arithmetic
Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy
A Formal Verification Methodology for IP-based Designs
Efficient Simulation of Droplet Merging in Channel-Based Microfluidic Devices
A New Array Fabric for Coarse-Grained Reconfigurable Architecture
Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems
CPLD-oriented Synthesis of Finite State Machines
Improved Power Modeling of DDR SDRAMs
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded Processing
Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations
A Hardware Design for Camera-Based Power Management of Computer Monitor
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures
Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study
A Microprogrammed Approach for Implementing Statecharts
Evaluating OpenMP Support Costs on MPSoCs
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation
Design and Implementation of a Privacy Framework for the Internet of Things (IoT)
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies
Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms
Architecture Design of a Scalable Single-Chip Multi-Processor
SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals
Power Conscious RTL Test Scheduling
Ad-hoc WSN in Biological Research
Quantitative and Qualitative Evaluation Methods of Automotive Time of Flight Based Sensors
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA
The VALU3S ECSEL Project: Verification and Validation of Automated Systems Safety and Security
MPSoC memory optimization for digital camera applications
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems
Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization
Gain and Pain of a Reliable Delay Model
Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems
Wireless Medical Information System Network for Patient ECG Monitoring
Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems
New ASIC/FPGA Cost Estimates for SHA-1 Collisions
Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization
SIMD Enhancements for a Hough Transform Implementation
Decomposition of Multi-Output Functions for CPLDs
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions
A Multiple Context Reconfigurable Functional Unit
Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification
Programmable Numerical Function Generators for Two-Variable Functions
Quaternary High Performance Arithmetic Logic Unit Design
Estimation of deoxygenated and oxygenated hemoglobin by multispectral blind linear unmixing
Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO Patterns
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs
Embedded Object Architecture
Low-Cost Sub-5W Processors for Edge HPC
A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder
A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks
IMMizer: An Innovative Cost-Effective Method for Minimizing Assertion Sets
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
Stability Verification of Self-Timed Control Systems Using Model-Checking
A New Class of Cellular Automata
MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based Systems
Source Code Transformation to Improve Conditional Hardware Reuse
Performance Improvement for H.264 Video Encoding using ILP Embedded Processor
An Enhanced Path Delay Fault Simulator for Combinational Circuits
A Suite of Processors to Explore CHERI-RISC-V Micro Architecture
Run-time Mapping Algorithm for Dynamic Workloads on Heterogeneous MPSoCs Platforms
Verifying Linear Temporal Logic Properties in UML/OCL Class Diagrams Using Filmstripping
Hardware-aware Decision Tree Ensembles for Radar Data Processing on the Edge with Online Learning
Fault Tolerant FPGAs: Where to Spend the Effort?
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework
State Assignment for Detecting Erroneous Transitions in Finite State Machines
Protecting IoT Devices through a Hardware-driven Memory Verification
An Embedded Hardware Architecture for Real-Time Super-Resolution in Infrared Cameras
Optimizing Picnic for Limited Memory Resources
The CASPER Project Approach Towards User-Centric Mobile Networks
Low-Power Online ECG Analysis Using Neural Networks
Investigating the Impact of Non-Volatile Memories on Energy-Efficiency of Coarse-Grained Reconfigurable Architectures
Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links
Optimization of Circuits for IBM's Five-Qubit Quantum Computers
The Effect of the Transient Faults in Dependability Prediction
On the Design of Modulo 2^n+1 Multipliers
Graph Matching Constraints for Synthesis with Complex Components
Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures
Composable Platform-Aware Embedded Control Systems on a Multi-core Architecture
3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures
Techniques for SAT-Based Constrained Test Pattern Generation
Hybrid BIST Optimization Using Reseeding and Test Set Compaction
A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
Architecture-Driven Synthesis of Reconfigurable Cells
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML
Energy and Performance Model of a SPARC Leon3 Processor
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
Cost-effective VLSI Design of Non Linear Image Processing Filters
A Multicore SDR Architecture for Reconfigurable WiMAX Downlink
Pre-silicon Characterization of NIST SHA-3 Final Round Candidates
Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor
Calibration Error Bound Estimation in Performance Modeling
Fast System Level Benchmarks for Multicore Architectures
Reducing Instruction Issue Overheads in Application-Specific Vector Processors
Methodologies for the WCET Analysis of Parallel Applications on Many-Core Architectures
Test Generation Approach for Post-Silicon Validation of High End Microprocessor
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems
Hardware-Based Implementation of the Common Approximate Substring Algorithm
E2LP: A Unified Embedded Engineering Learning Platform