yusuke1997/dblp-id-title huggingface dataset:
MAPLE chip: a processing element for a static scheduling centric multiprocessor
Hardware Synthesizable Exceptions using Continuations
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes
Bidirectional tuning of microring-based silicon photonic transceivers for optimal energy efficiency
SMYLE OpenCL: A programming framework for embedded many-core SoCs
A novel wavelet method for noise analysis of nonlinear circuits
Array scalarization in high level synthesis
Power optimization for application-specific 3D network-on-chip with multiple supply voltages
Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis
Equivalence Checking of Parameterized Quantum Circuits: Verifying the Compilation of Variational Quantum Algorithms
A delay model for interconnect trees based on ABCD matrix
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion
Fully-automated synthesis of power management controllers from UPF
IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure
Quantifying workload dependent reliability in embedded processors
Power management strategies in data transmission
A novel differential VCO circuit design for USB Hub
Fast synthesis of exact minimal reversible circuits using group theory
Adaptive load distribution in mixed-critical Networks-on-Chip
A 3D prototyping chip based on a wafer-level stacking technology
A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs
Testing Interconnects of Dynamic Reconfigurable FPGAs
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006
Test vector chains for increased targeted and untargeted fault coverage
Dynamic planning of local congestion from varying-size vias for global routing layer assignment
ScanSAT: unlocking obfuscated scan chains
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification
A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC
A new techology mapping for CPLD under the time constraint
Advanced system LSIs for home 3D system
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture
A CMOS image sensor with 2.0-e - random noise and 110-ke - full well capacity using column source follower readout circuits
An Equivalence Checking Framework for Agile Hardware Design
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors
DPA: A data pattern aware error prevention technique for NAND flash lifetime extension
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
Parameterized block-based non-gaussian statistical gate timing analysis
Design issues in heterogeneous 3D/2.5D integration
Placement stability metrics
Integrated flow for reverse engineering of nanoscale technologies
Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening
A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder
Processor shield for L1 data cache software-based on-line self-testing
Standard Cell Layout Generation: Review, Challenges, and Future Works
A 60GHz direct-conversion transmitter in 65nm CMOS technology
Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Towards Multiphase Clocking in Single-Flux Quantum Systems
AIR: A Fast but Lazy Timing-Driven FPGA Router
BDD minimization for approximate computing
Power minization in LUT-based FPGA technology mapping
Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence Transformations
Symbolic computation of SNR for variational analysis of sigma-delta modulator
Efficient computation of canonical form for Boolean matching in large libraries
Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization
Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling
Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis
RExCache: Rapid exploration of unified last-level cache
MD: Minimal path-based fault-tolerant routing in on-Chip Networks
Theoretical Patchability Quantification for IP-Level Hardware Patching Designs
Reclocking for high-level synthesis
A case for wireless 3D NoCs for CMPs
Reconfigurable RTD-based circuit elements of complete logic functionality
Low-power image recognition challenge
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video
Runtime reconfigurable memory hierarchy in embedded scalable platforms
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection
Fault-tolerant TSV by using scan-chain test TSV
Tolerating process variations in high-level synthesis using transparent latches
Implementation of fast CRC calculation
Time-Triggered Scheduling for Time-Sensitive Networking with Preemption
Efficient Computer Vision on Edge Devices with Pipeline-Parallel Hierarchical Neural Networks
Reducing leakage power in instruction cache using WDC for embedded processors
Dynamic test compaction for a random test generation procedure with input cube avoidance
Methodology for high level estimation of FPGA power consumption
Application specified soft error failure rate analysis using sequential equivalence checking techniques
SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation
Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA
A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains
Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline
Tessellating memory space for parallel access
DRL-cloud: Deep reinforcement learning-based resource provisioning and task scheduling for cloud service providers
Silicon virtual prototyping: the new cockpit for nanometer chip design
A 65-nm CMOS fully-integrated circulating tumor cell and exosome analyzer using an on-chip vector network analyzer and a transmission-line-based detection window
Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability
Compact and stable modeling of partial inductance and reluctance matrices
A quantitative analysis for optimizing memory allocation
Comparing high-level modeling approaches for embedded system design
Bit-serial pipeline synthesis and layout for large-scale configurable systems
Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuation
An Effective Netlist Planning Approach for Double-sided Signal Routing
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques
Physical design implementation of segmented buses to reduce communication energy
A new low energy BIST using a statistical code
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation
EDA vendor adoption
Lattice-based Boolean diagrams
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming
Area optimization for leakage reduction and thermal stability in nanometer scale technologies
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
A fixed-die floorplanning algorithm using an analytical approach
A Huffman-based coding with efficient test application
Static analysis and automatic code synthesis of flexible FSM model
ILP-based inter-die routing for 3D ICs
8K LCD: Technologies and challenges toward the realization of SUPER Hi-VISION TV
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture
Cube-embedding based state encoding for low power design
Numerical Function Generators Using Edge-Valued Binary Decision Diagrams
Design technology productivity in the DSM era (invited talk)
On-chip interconnections: impact of adjacent lines on timing
Platform characterization for Domain-Specific Computing
A dynamic reconfigurable RF circuit architecture
Multi-project chip activities in Korea-IDEC perspective
Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process
Pin assignment and routing on a single-layer Pin Grid Array
Statistical corner conditions of interconnect delay (corner LPE specifications)
System-on-chip security architecture and CAD framework for hardware patch
Block-level fault isolation using partition theory and logic minimization techniques
Design of clocked circuits using UML
An inductor-less MPPT design for light energy harvesting systems
One language or more?: how can we design an SoC at a system level?
Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors
Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions
Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement
Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications
Improving the Robustness of Microfluidic Networks
ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA
Design of complex image processing systems in ESL
A new description of CMOS circuits at switch-level
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
High level equivalence symmetric input identification
2.5D design methodology
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits
EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997
Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach
Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators
Formal Semantics of Predictable Pipelines: a Comparative Study
Error correction circuit using difference-set cyclic code
Adjustable contiguity of run-time task allocation in networked many-core systems
Implementing microprocessors from simplified descriptions
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Simulation of gate switching characteristics of a miniaturized MOSFET based on a non-isothermal non-equilibrium transport model
Character design and stamp algorithms for Character Projection Electron-Beam Lithography
Analysis of scratch-pad and data-cache performance using statistical methods
New Methods to Find Optimal Non-Disjoint Bi-Decompositions
Generic fuzzy logic CAD development tool
Experience in critical path selection for deep sub-micron delay test and timing validation
ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation
A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology
Embedded software generation from system level specification for multi-tasking embedded systems
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach
A high-performance platform-based SoC for information security
Statistical delay computation considering spatial correlations
Aging-Aware Request Scheduling for Non-Volatile Main Memory
A novel data format for approximate arithmetic computing
SAT-based area recovery in structural technology mapping
On confidence in characterization and application of variation models
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits
Power-Pro: Programmable Power Management Architecture
Formal verification of tunnel diode oscillator with temperature variations
Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
System-level design space exploration for security processor prototyping in analytical approaches
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications
A 6.9mW 120fps 28×50 capacitive touch sensor for 1mm-φ stylus using current-driven ΔΣ ADCs
Optimizing multi-level combinational circuits for generating random bits
A memory grouping method for sharing memory BIST logic
Hierarchical extraction and verification of symmetry constraints for analog layout automation
Power optimization and management in embedded systems
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares
CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniques
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power
Efficient transient simulation for transistor-level analysis
A Hierarchical Assessment Strategy on Soft Error Propagation in Deep Learning Controller
Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations
MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training
Polymorphic gate based IC watermarking techniques
Cut redistribution with directed self-assembly templates for advanced 1-D gridded layouts
Data mining in functional test content optimization
High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping
Insights and Optimizations on IR-drop Induced Sneak-Path for RRAM Crossbar-based Convolutions
Runtime leakage power estimation technique for combinational circuits
HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads
22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
Platform modeling for exploration and synthesis
HybridGP: Global Placement for Hybrid-Row-Height Designs
A transformational codesign methodology
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs
Recognition of Fanout-free Functions
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation
BatchSizer: Power-Performance Trade-off for DNN Inference
Automatic interface synthesis based on the classification of interface protocols of IPs
MajorSat: A SAT solver to majority logic
Processing-Near-Memory with Chip Level 3D-IC
A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration
A new efficient method for substrate-aware device-level placement (short paper)
A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources
D-A converter based variation analysis for analog layout design
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST
Bitwidth-aware scheduling and binding in high-level synthesis
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin
Compiler-managed register file protection for energy-efficient soft error reduction
Simultaneous redundant via insertion and line end extension for yield optimization
A 13.56 MHz on/off delay-compensated fully-integrated active rectifier for biomedical wireless power transfer systems
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair
Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper)
An automated design approach for CMOS LDO regulators
A Reconfigurable Approximate Multiplier for Quantized CNN Applications
Application-level embedded communication tracer for many-core systems
Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs
A monolithic CMOS L band DAB receiver
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations
Clustering techniques for coarse-grained, antifuse FPGAs
Functional and partially-functional skewed-load tests
Novel dual- V th independent-gate FinFET circuits
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification
ASP-DAC 2017 keynote speech II: Emerging medical technologies for interfacing the brain: From deep brain stimulation to brain computer interfaces
Lithographic defect aware placement using compact standard Cells without inter-cell margin
Memory access pattern analysis and stream cache design for multimedia applications
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
LEneS: task scheduling for low-energy systems using variable supply voltage processors
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
Design and implementation of JPEG encoder IP core
Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration
Partial order method for timed simulation of system-level MPSoC designs
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs
Automated data analysis techniques for a modern silicon debug environment
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture
A hybrid random walk algorithm for 3-D thermal analysis of integrated circuits
RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
Making fast buffer insertion even faster via approximation techniques
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods
A robust min-cut improvement algorithm based on dynamic look-ahead weighting
Placement for configurable dataflow architecture
A 1Tb/s 3W Inductive-Coupling Transceiver Chip
Security Coverage Metrics for Information Flow at the System Level
Register aware scheduling for distributed cache clustered architecture
A practical method for multi-domain clock skew optimization
An anytime symmetry detection algorithm for ROBDDs
ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning
Register and thread structure optimization for GPUs
On-line leakage-aware energy minimization scheduling for hard real-time systems
PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning Transformers
A 60mW baseband SoC for CMMB receiver
Abstracting functionality for modular performance analysis of hard real-time systems
A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems
Detailed-Routing-Driven analytical standard-cell placement
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform
Hardware/software co-design using hierarchical platform-based design method
A comprehensive and accurate latency model for Network-on-Chip performance analysis
Trend in power devices for electric and hybrid electric vehicles
Multi-core parallel simulation of System-level Description Languages
Symmetry Detection for Automatic Analog-Layout Recycling
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system
Peak-to-average pumping efficiency improvement for charge pump in Phase Change Memories
A transduction-based framework to synthesize RSFQ circuits
A Low Cost Weight Obfuscation Scheme for Security Enhancement of ReRAM Based Neural Network Accelerators
Design driven partitioning
A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applications
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow
A probabilistic Boolean logic for energy efficient circuit and system design
Experiences of low power design implementation and verification
Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters
Hardware-software co-design: Tools for architecting systems-on-a-chip
Utilizing quad-trees for efficient design space exploration with partial assignment evaluation
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor
A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter
FAST-SP: a fast algorithm for block placement based on sequence pair
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
PMU-Trojan: On exploiting power management side channel for information leakage
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers
A routability constrained scan chain ordering technique for test power reduction
Can we identify smartphone app by power trace? [Extended abstract for special session]
An efficient homotopy-based Poincaré-Lindstedt method for the periodic steady-state analysis of nonlinear autonomous oscillators
BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization
Leakage power: trends, analysis and avoidance
BIST with negligible aliasing through random cover circuits
An FPGA implementation of low-density parity-check code decoder with multi-rate capability
ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow
Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points
The Survey of 2.5D Integrated Architecture: An EDA perspective
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design
Hippocrates: First-Do-No-Harm Detailed Placement
Proximity-Aware cache Replication