yusuke1997/dblp-id-title huggingface dataset:
CDM-ESD induced damage in components using stacked-die packaging
Concurrent design of ESD protection and ICs for optimization and prediction
A 17V-to-45V Input 25 μW-to-10mW Output Power, 90.2%-Peak-Efficiency SC DC-DC Converter with Recursive Output Connection for High-Voltage Energy Harvesting
Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay
A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield
Voltage references for ultra-low supply voltages
A CMOS readout circuit for pico-ampere thin film pyroelectric array detectors
A 10-b 600-MS/s 2-way time-interleaved SAR ADC with mean absolute deviation based background timing-skew calibration
A High-Throughput Maximum a posteriori Probability Detector
A 1.3-6 GHz triple-mode CMOS VCO using coupled inductors
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme
An 8/4-bit reconfigurable digital pixel array with on-chip non-uniform quantizer
Smart-wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor node
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme
A multi-GHz area-efficient comparator with dynamic offset cancellation
A 32-mW 40-Gb/s CMOS NRZ transmitter
A 4-port-inductor-based VCO coupling method for phase noise reduction
A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling
An ultra-low-power wake-up receiver with voltage-multiplying self-mixer and interferer-enhanced sensitivity
Materials challenges for III-V/Si co-integrated CMOS
A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection
Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects
A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS
An analog record, playback and processing system on a chip for mobile communications devices
A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics
A 17.4fJ/conv.-step, 202µm 2 , 1.5GS/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS
Technology variability from a design perspective
A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS
Fully depleted devices for designers: FDSOI and FinFETs
Analog techniques
Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design
Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines
An Energy-Efficient Healthcare Chest Patch Interface with Multi-Domain On-Sensor Computing and Inter-Sensor Windowing
Voltage-controlled oscillator in the coil
A CMOS programmable gain amplifier with a novel DC-offset cancellation technique
A 0.6V Supply Ultra-Compact Voltage Reference Exploiting MOS Threshold Correlations
Time-interleaved analog-to-digital converters
Piezoelectric-Based Power Conversion: Recent Progress, Opportunities, and Challenges
A flexible decoder IC for WiMAX QC-LDPC codes
A 100A 48-60V to 1V Hybrid LLC Resonant Converter with 51mV Droop for a 70A/20ns Load Transient
Switching well noise analysis and minimization strategy for low V th CMOS integrated circuits
Measurements and analyses of substrate noise waveform in mixed signal IC environment
A 2.7 V 11.8 mW baseband ADC with 72 dB dynamic range for GSM applications
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW
A 4.6-373K Functional 800MS/s 12b Buffer-then-Amplify Charge-Pump-Based Pipelined TI-SAR ADC with Integrated-Active-Hold Technique
A biomedical implantable FES battery-powered micro-stimulator
Power-efficient I/O design considerations for high-bandwidth applications
A 1.5-V CMOS Receiver Front-End for 9-Band MB-OFDM UWB System
A self-timed, fully-parallel content addressable queue for switching applications
Problem of timing mismatch in interleaved ADCs
An analog optimum torque control IC for a 200W wind energy conversion system with over 99% MPPT accuracy, 1.7% THDi and 0.99 power factor
Layout-dependent proximity effects in deep nanoscale CMOS
Recent developments in RF receivers
Test challenges for 3D integration (an invited paper for CICC 2011)
Biomedical electronics forum
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS
Dedicated system-level simulation of ΔΣ modulators
A 1.4 V 60 MHz access, 0.25 μm embedded flash EEPROM
BAG2: A process-portable framework for generator-based AMS circuit design
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS
Mutual Injection Pulling Between Oscillators
Electrical and photonic I/O test and debug
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
DECADES: A 67mm 2 , 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET
A 26.55TOPS/W Explainable AI Processor with Dynamic Workload Allocation and Heat Map Compression/Pruning
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations
An FPGA based move generator for the game of chess
A 6b 3GS/s flash ADC with background calibration
Advances and Challenges in Flip-Chip Packaging
Design optimizations for reduced power and higher operating frequency in a custom x86-64 processor core
Design of tunable digital delay cells
Energy scaling in multi-tiered sensing systems through compressive sensing
Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction
Frequency-hopping vernier clock generators for multiple clock domain SoCs
A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator
Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS
Substrate-induced high-frequency noise in deep sub-micron MOSFETs for RF applications
The UltraSPARC T1 Processor: CMT Reliability
A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS
Capacity limits and matching properties of lateral flux integrated capacitors
A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS
An automatic offset compensation technique applicable to existing operational amplifier core cell
A scalable architecture for fully integrated multi-TV tuners
A monolithic CMOS low-IF Bluetooth receiver
A Resistive Dynamic Bias Comparator with Flying Capacitors Achieving 129µVrms Input-Referred Noise at 1GS/s in 28nm FD-SOI
A 0.64mm 2 Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique
Simulation methodology and flow integration for 3D IC stress management
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing
A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity
System-on-chip security assurance for IoT devices: Cooperations and conflicts
A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited)
High-power digital envelope modulator for a polar transmitter in 65nm CMOS
Process/Product Interactions in a Concurrent Design Environment
A Power-Efficient Jitter-Insensitive 3.2GHz 1-bit CT ΔΣ ADC with Direct Charge Dump Feedback
Progress toward a low-cost millimeter-wave silicon radio
An 83.16-TOPS/W Voltage-Scalable Time-Domain CNN Accelerator with Full-Swing Delay Cell and Gray-Code TDC in 28-nm CMOS
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology
A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR
A fully-integrated optical duobinary transceiver in a 130nm SOI CMOS technology
Single-inductor-multiple-output DC-DC converter design
MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks
An IF FSK demodulator for Bluetooth in 0.35 μm CMOS
Relative inductance extraction method
A Comprehensive Phase-Transfer Model for Delay-Locked Loops
Future wireless systems: UWB, 60GHz, and cognitive radios
ESD implementation strategies
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique
A Distributed RF Front-End for UWB Receivers
A Microwave-Optical Biosensor with 5.4ppm Label/Reference-free Long-term Stability and Single Photon Sensitivity in 28nm Bulk CMOS
Integration of CMOS and MEMS Technologies in the Development of a Neural Imaging and Interface Device: Showcase of an Emerging Bioimaging Technique
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies
Simulation and modeling of intermodulation distortion in communication circuits
A frequency-shift based CMOS magnetic biosensor with spatially uniform sensor transducer gain
Cochlear Implant Signal Processing ICs
Dynamic NBTI management using a 45nm multi-degradation sensor
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
A versatile low-power power line FSK transceiver
A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage
Robust Inductor Design for RF Circuits
Active autonomous AC-DC converter for Piezoelectric Energy Scavenging Systems
MEMS for telecommunications: devices and reliability
Efficient sampling of reference noise in a switched capacitor ΣΔ ADC
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter
A Single-Stage Bias-Flip Regulating Rectifier with Fully-Digital Fast-MPPT for Piezoelectric Energy Harvesting Achieving 9.3X Power Enhancement and 92.5% End-to-End Efficiency
A Negative R-Assisted Amplifier on the Virtual Ground and Its Applications
A 2.4-to-240W, 95.04% Peak Efficiency LLC Isolate Converter Controller with Symmetric Pulse-Width Balancing and Fixed-Period Hysteresis Burst Control
Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections
Session 4 - Frequency and phase generation techniques
A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN
20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS
Millimeter-wave power amplifiers & transmitters
Recent advances in Ga N MMIC technology
H-SIMO: A Hybrid Single-Inductor Multi-Output 5-Level Thin-Oxide Power Management Unit Achieving 91.4% Efficiency from Li-ion Battery Voltages in 28nm FD-SOI
Characterization of Inverse Temperature Dependence in logic circuits
Energy-efficient recognition and mining processor using scalable effort design
Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os
Session 27 - Technology directions
A Resonant Synchronized Switch Harvesting Rectifier with Bias-Flip Charge Recycling for Piezoelectric Energy Harvesting Achieving 13.9x Power Enhancement
A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration
ES4-4: Circuit design techniques for fully integrated voltage regulator using switched capacitors
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS
A 3 - 14V rail-to-rail constant gm opamp in conventional 0.18µm CMOS process
An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache
Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators
Design of an analogue ASIC using subthreshold CMOS transistors to model biological neurons
A 106.1dB DR, 450μA Idle Current Class-H Piezoelectric MEMS MicroSpeaker Driver with Envelope Tracking, Digital and Analog Inputs and Less Than 2.1μs Latency
A wideband low-phase-noise CMOS VCO
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS
Active-feedback frequency compensation for low-power multi-stage amplifiers
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications
An integrated RF transceiver for DECT application
A 5V-to-0.5V Inductor-First Inductor-on-Ground Switched Capacitor Multi-Path Hybrid DC-DC Converter
A Dual-Mode 24-32 GHz 4-Element Phased-Array Transceiver Front-End with SSA Beamformer for Autonomous Agile Unknown Signal Tracking and Blocker Rejection within <0.1 us and 21.3%/15% Transmitter Peak/OP1dB PAE
Non-linear transmission lines for pulse shaping in silicon
Integration and system design trends of ADSL analog front ends and hybrid line interfaces
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout
A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing
MAA evolution: Common access/backhaul reference platform
Efficient capacitance extraction method for interconnects with dummy fills
A 28-MHz wide-band switched-capacitor bandpass filter with high attenuation
A fully integrated CMOS nanoscale biosensor microarray
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013
A fabrication method for high performance embedded DRAM of 0.18 μm generation and beyond
A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter
Pathfinding for 22nm CMOS designs using Predictive Technology Models
DSP for wireless
Characterization and design for variability and reliability
A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications
A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system
Reviews and future prospects of low-voltage embedded RAMs
A 92%-Efficiency 0.828μs Settling Time FC5L Voltage Regulator Featuring Time-Domain Charge Balancing & Flying Capacitor Self-Switching for Wide Dynamic Range & Fast Transient Chiplet Applications
A second-order anti-aliasing prefilter for an SDR receiver
Active CMOS Array for Electrochemical Sensing of Biomolecules
Frequency scalable non-linear waveform generator for mixed-signal power-factor-correction IC controller
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES
A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC
Hard disk drive read channels: technology and trends
A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS
Pathways to mm-scale DC-DC converters: Trends, opportunities, and limitations
Single GSM mixed signal superchip with 96k bytes FLASH and low power micro-controller
A 30.1μm 2 , > ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring
Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection
A 0.031mm 2 , 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS
On-chip RF spiral inductors and bandpass filters using active magnetic energy recovery
A 400MHz NPU with 7.8TOPS 2 /W High-PerformanceGuaranteed Efficiency in 55nm for Multi-Mode Pruning and Diverse Quantization Using Pattern-Kernel Encoding and Reconfigurable MAC Units
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
A 500MHz DLL with second order duty cycle corrector for low jitter
A 0.25 μm CMOS transceiver front-end for GSM
Programmable techniques for cell stability test and debug in embedded SRAMs
A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire
Ultra low-power transceiver SoC designs for IoT, NB-IoT applications
On-chip analog signal generator for mixed-signal built-in self-test
An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifier
An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards
A 1 V 5 th -order Bessel filter dedicated to digital standard processes
A fully integrated zero-IF mobile TV tuner RFIC for S-band CMMB application
A CMOS 3D camera with millimetric depth resolution
Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers
Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)
A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor
Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique
A monolithic buck converter using differentially enhanced duty ripple control
A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET
Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL
A 38.6nV/Hz 0.5 -59.6dB THD dual-band micro-electrode array signal acquisition IC
A multifunction transceiver RFIC for 802.11a/b/g WLAN and DVB-H applications
Multi-project management in real time
A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme
A 2 V 1.6 GHz BJT phase-locked loop
Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper)
A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance
A 9.15mW 0.22mm 2 10b 204MS/s pipelined SAR ADC in 65nm CMOS
Managing linearity in radio front-ends
Nonlinear Phase Macromodel Based Simulation/Design of PLLs with Superharmonically Locked Dividers
Low-Power CMOS Energy Detection Transceiver for UWB Impulse Radio System
OTA linearity enhancement technique for high frequency applications with IM3 below -65dB
A low-power IC design for the wireless monitoring system of the orthopedic implants
Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system
Open-Source AXI4 Adapters for Chiplet Architectures
A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor
A 0.025-mm 2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure
A Neuron-Inspired 0.0032mm 2 -1.38μW/Ch Wireless Implantable Neural Interface with Direct Multiplexing Front-End and Event-Driven Spike Detection and Transmission
A 1-V 2.4-GHz FSK receiver with a complex BPF and a frequency doubler in CMOS/SOI
A 14.6 th -order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process
MAPP: The Berkeley Model and Algorithm Prototyping Platform
Circuits techniques and microsystems assembly for intracortical multichannel ENG recording
Session 8 - Characterization and test methods for device variability in nanoscale technologies
A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS
Advanced digital phase-locked loops
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur
Double-balanced 130-180 GHz passive and balanced 145-165 GHz active mixers in 45 nm CMOS
AMS verification in advanced technologies
A 12-bit 12.5 MS/s multi-bit ΔΣ CMOS ADC
A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain Implants
A Floating-gate Based Low-Power Capacitive Sensing Interface Circuit
A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process
A reconfigurable FIR filter embedded in a 9b successive approximation ADC
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation
High-speed CMOS ring oscillators with low supply sensitivity
Phase noise in inverter-based & differential CMOS ring oscillators
KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting
Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range
A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers
Characterization, simulation, and modeling of FET source/drain diffusion resistance
A 65 nm CMOS tunable 0.1-to-1.6 GHz distributed transmission line N-path filter with +10 dBm blocker tolerance
Power delivery: Droop, jitter, test and debug story (Tutorial)
High-speed wave-shaping techniques
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input
A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 Hz
The fabrication of scalable multi-sensor arrays using standard CMOS technology [chemical sensors]
Energy-efficient bio-sensing systems
A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS
Design of PVT tolerant inverter based circuits for low supply voltages
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process
A New Spread Spectrum Clock Generator for SATA Using Double Modulation Schemes
Ultra wideband circuits and transceivers
A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm
Integrated circuit for high-frequency ultrasound annular array
Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance
A comparison of CMOS and SiGe LNA's and mixers for wireless LAN application
A 7.9-ENOB 1. 5GS/s Common-Mode and Temperature Insensitive Pipelined-SAR ADC with an On-Chip Temperature-Sensor-Based Stage-Gain Compensation
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth
Variable gain differential current feedback amplifier
Arria™ 10 device architecture