yusuke1997/dblp-id-title huggingface dataset:
TSRI Silicon Photonics Design Platform: Standardization and Collaboration
The Supercomputer "Fugaku"
An effective arterial blood pressure signal processing system based on EEMD method
ARM next generation 64bit processors for power efficient compute
Multimode multiband power amplifier optimization for mobile applications
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays
Homo technologicus
A 0.5-V, 1.79-μW, 250-kbps Wake-up Receiver for IoT application in 90-nm CMOS
Distributed Sorting Architecture on Multiple FPGA
Collaboration and innovation for your success
On IC traceability via blockchain
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs
Semiconductor specialty technologies in IOT era
A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits
Efficient architecture for Reed-Solomon decoder
System-level test coverage prediction by structural stress test data mining
Safe and secure SOC architecture for autonomous driving
An Injection-Locked Clock Multiplier With Injection Strength Calibration
Oscillation-based diagnosis by using harmonics analysis on analog filters
An SIMO Step-Down Converter with Coupled Inductor
Challenges and Opportunities in Building Secure IoT Platforms
A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage
Efficient Write Scheme for Algorithm-Based Multi-Ported Memory
A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS
Introduction of Noise-Shaping SAR ADCs
Energy efficient VLSI circuits for machine learning on-chip
Challenges and solutions in modern analog placement
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013
Acceleration of neural network model execution on embedded systems
A Cost-Effective Embedded Nonvolatile Memory with Scalable LEE Flash ® -G2 SONOS for Secure IoT and Computing-in-Memory (CiM) Applications
High-level Fault Diagnosis on network-on-chip using path tracking
To 4G mobile communication and beyond
An addressable UHF EPCGlobal Class1 Gen2 Sensor IC for wireless IOP monitoring on contact lens
Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor
Side-channel-aware LSI design
Deep Learning Creativity in EDA
Wide-I/O 3D-staked DRAM controller for near-data processing system
Optimization of threshold logic networks with ODC-based node merging
A layout-aware automatic sizing approach for retargeting analog integrated circuits
Self-driving cars: Technologies, business opportunities and challenges
A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control
A 360-degree panoramic video system design
Low bandwidth HD1080@60FPS JPEG-XR transform design
Miniaturized CMOS imaging device for implantable applications
Highly integrated 4G front end modules for handset applications - A designer's perspective
Port assignment for interconnect reduction in high-level synthesis
Resistor-Based Temperature Sensing Chip with Digital Output
Robust CNFET Circuit Sizing Optimization
An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming
A dual-edge sampling CES delay-locked loop based clock and data recovery circuits
A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process
Analysis and reduction of SRAM PUF Bit Error Rate
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime
Power and area reduction in multi-stage addition using operand segmentation
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems
Design of low-cost elliptic curve cryptographic engines for ubiquitous security
Utilization of relieved corners from multi-corner libraries in deterministic static timing analysis
A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance
Ambient electronics and ultra-low power LSI design
Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors
Energy-efficient architecture for word-based Montgomery modular multiplication algorithm
Autonomous Driving Technologies and Computing Platform
The evolution of fabless IC industry in China: Past, present, and future
A High Performance, Low Energy, Compact Masked 128-Bit AES in 22nm CMOS Technology
Emerging touch techniques in smart handheld device
Energy Efficient CNN Inference Accelerator Using Fast Fourier Transform
A Test Method for Large-size TSV Considering Resistive Open Fault and Leakage Fault Coexistence
TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches
Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events
Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation
A low cost DPA-resistant 8-bit AES core based on ring oscillators
RF and signal processing technologies for 4G mobile networks
A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications
A versatile data cache for trace buffer support
Statistical SDFC: A metric for evaluating test quality of small delay faults
Bringing Powerful Machine-Learning Systems to Daily-Life Devices via Algorithm-Hardware Co-Design
A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique
C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architectures
The road to a trillion: Making the IoT work
Terahertz systems-on-chip enabled by nano-IC technologies
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling
Future of Computing and Sensing Systems for Embedded Applications
A highly integrated class-D amplifier using driver delay hysteresis control
Silicon-package-board co-design for the eye diagram prediction of a 3Gbps HDMI transmitter
Low power pipelined SAR ADC with loading-free architecture
Experiments and optimizations for TVM on RISC-V Architectures with P Extension
Embedded Memories for Silicon-In-Package: Optimization of Memory Subsystem from IoT to Machine Learning
A sub-GHz mostly digital impulse radio UWB transceiver for wireless body sensor networks
The resilience wall: Cross-layer solution strategies
An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor
Precision material engineering - An equipment point of view
Gait Parameters Analysis Based on Leg-and-shoe-mounted IMU and Deep Learning
A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer
World megatrend of intelligent robotics and AI: Impact on VLSI-DAT
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips
Hardware-efficient true motion estimator based on Markov Random Field motion vector correction
Two-staged parallel layer-aware partitioning for 3D designs
An impact of process variation on supply voltage dependence of logic path delay variation
Design and implementation of 18-band Quasi-ANSI S1.11 1/3-octave filter bank for digital hearing aids
CMOS reliability: From discrete device degradation to circuit aging
The Applications of SiC Power Devices in Renewable Energy and EV
EcoSim: A Smartphone-Based Sensor-Node Emulator with Native Sensors and Protocol Stack
Diagnosing timing related cell internal defects for FinFET technology
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter
Edge-AI Based Cattle Behavior Estimation System for Grazing
Low-Power 3D-PCB Stacking System Design and Validation by Automatic Voltage-Current Scalable Technique
Automotive semiconductor test
Moore's law - predict the unpredictable
Improve speed path identification with suspect path expressions
Improve transition fault diagnosability via observation point insertion
Power semiconductor-driving technology for high power green electronic systems
Machine Learning Applications and Opportunities in IC Design Flow
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs
An all-digital phase-locked loop compiler with liberty timing files
A Novel Test Generation Method for Small-Delay Defects with User-Defined Fault Model
3D-IC BISR for stacked memories using cross-die spares
Soft electronics for the human body
The Rise of RISC-V from Edge to Cloud
Google's C/C++ toolchain for smart handheld devices
The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices
A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications
UltraCMOS ® technology for high-performance switch paths and tunable components
Efficient method for AI computing
Efficient Segment-wise Pruning for DCNN Inference Accelerators
Bio-Chips for Fast Medial Tests Networks
DC-to-5-GHz variable gain amplifier for high speed DSO
Low-noise analog synthesis platform for bio-signal acquisition system
Drivers and aspects of 2.5/3D integration as a potential game-changer
Integrating aging aware timing analysis into a commercial STA tool
A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique
Welcome from the general chairs
Layout placement optimization with isolation rings for high-voltage VLSI circuits
Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis
Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits
Prospect of embedded non-volatile memory in the smart society
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements
SoC test integration platform
Machine learning for IC design and technology co-optimization in extreme scaling
M2M: Challenges and opportunities
Hardware design of disparity computation for stereo vision using guided image filtering
Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs
A view scalable multi-view video decoder system
Wearables to Electronics: The Key Enabler for Personalized Healthcare
Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices
A Hadoop-based Principle Component Analysis on embedded heterogeneous platform
Overview of the OpenROAD Digital Design Flow from RTL to GDS
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers
A Hybrid Supply Modulator for 10-MHz LTE Power Amplifier with 17.3% PAE Improvement
SAT-based complete logic implication with application to logic optimization
A 1 Mb/s-40 Mb/s human body channel communication transceiver
Electromigration- and obstacle-avoiding routing tree construction
RFIC and RF Module for 5G Applications
The quest for a new dimension of system integration
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification
SOI technology: An opportunity for RF designers?
A Light Energy Harvesting Single-Inductor Dual-Input Dual-Output Converter for WSN
Supervised-Learning Congestion Predictor For Routability-Driven Global Routing
Real-time salient object detection engine for high definition videos
Reversible Scan Based Diagnostic Patterns
Emerging memory technology perspective
Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs
Design trends and test challenges in automotive electronics
Silicon photonics : From research to industrial reality
In and out of the cloud
An analytical placer for heterogeneous FPGAs via rough-placed packing
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints
An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filter
A master-slave SoC structure for HMM based speech recognition
How FPGA can contribute to HPC ?
An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 ns
High-performance NTT architecture for large integer multiplication
Highly integrated RF frontend module for high SHF wide-band massive MIMO in 5G, and switching-mode amplifiers beyond 4G
Utilizing NVDIMM to alleviate the I/O performance gap for big data workloads
Machine Learning System-Enabled GPU Acceleration for EDA
A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems
Test Knowledge Data Base
A real-time parallel scalable video encoder for multimedia streaming systems
A high learning capability probabilistic spiking neural network chip
Evaluation methods of computer memory system
Characterization and compensation of performance variability using on-chip monitors
SiGe BiCMOS technology and circuits for active safety systems
Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devices
MVSE: A Multi-core Video decoder System level analytics Engine
Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines
Skillfully diminishing antenna effect in layer assignment stage
Transforming memory systems: Optimizing for client value on emerging workloads
Variational Channel Distribution Pruning and Mixed-Precision Quantization for Neural Network Model Compression
Scaling trends and challenges of advanced memory technology
CAD for Security: A Full Reverse Engineering Toolchain from Layout to RTL
2.5D & 3DIC Advanced Packaging: An EDA Perspective
DVB-T2 LDPC decoder with perfect conflict resolution
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array
Reducing computation redundancy for high-efficiency view synthesis
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator
A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT
Opportunities for 2.5/3D Heterogeneous SoC Integration
Sensorless dead-time exploration for digitally controlled switching converters
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories
2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020, Hsinchu, Taiwan, August 10-13, 2020
Scalable AI Computing Lifecycle
Fuzz testing & software composition analysis in software engineering
Dynamic Mapping Mechanism to Compute DNN Models on a Resource-limited NoC Platform
An OCP-AHB bus wrapper with built-in ICE support for SOC integration
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils
On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystem
Circuits and Architectures for Next-generation Attentive & Intelligent Systems
Silicon Technologies for Next Generation 5G Architectures and Applications
A dual-mode CMOS image sensor for optical wireless communication
Area and reliability efficient ECC scheme for 3D RAMs
Heterogeneous Computing for Edge AI
Power and sensor semiconductors driving automotive applications
A perspective on NVRAM technology for future computing system
A low-area digitalized channel selection filter for DSRC system
RRAM technology and its embedded potential on IoT applications
A fault-tolerant PE array based matrix multiplier design
Detailed routing violation prediction during placement using machine learning
2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018
Systematic co-optimization from chip design, process technology to systems for GPU AI chip
An effective photoplethysmography signal processing system based on EEMD method
Performance validation of dynamic-remapping-based task scheduling on 3D multi-core processors
Accurate and fast obstacle detection method for automotive applications based on stereo vision
An Embedded CNN Design for Edge Devices Based on Logarithmic Computing
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop
Thermal coupling aware task migration using neighboring core search for many-core systems
Case study of process and design performance debugging with Digital Speed Sensor
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS
New embedded memories, from lab to fab
A vision radar system for car safety driving applications
A reference-less all-digital transceiver for human body channel communication
Navigating through the fragmented application maze
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms
A four-band TD-LTE transmitter with wide dynamic range and LPF bandwidth calibration
Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes
Full system simulation framework for integrated CPU/GPU architecture
A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity
5G mmWAVE Technology Design Challenges and Development Trends
Low-complexity architecture for Chase soft-decision Reed-Solomon decoding
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint
A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver
An all-digital delay-locked loop for high-speed memory interface applications
A 22.4 fJ/conversion 0.7V 1.6μW 10-bit successive approximation ADC
A 39 GHz Reflection-Type Phase Shifter for Reflectarray Antenna Application
A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines
A successive approximation ADC with resistor-capacitor hybrid structure
3D Heterogeneous Integration Technology for AI System
A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS TM /3D ICs
A 4.0/7.5-GHz dual-band LC VCO in 0.18-μm SiGe BiCMOS technology
An integrated boost converter with maximum power point tracking for solar photovoltaic energy harvesting
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets
Enabling inter-die co-optimization in 3-D IC with TSVs
A 1-V, 44.6 ppm/°C bandgap reference with CDS technique
A 3D hand tracking design for gesture control in complex environments
Analysis of thermal effects in integrated radio transmitters
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits
An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip
A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS
Silicon Photonics for Scaling the Cloud and Enabling AI
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process
A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional Codes
Using approximate circuits to counter process imperfections in CNFET based circuits
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier
The 2012 ARM powered compute subsystem - delivering the smart handheld platform
Using range-equivalent circuits for facilitating bounded sequential equivalence checking
Compute-in-Memory for AI: From Inference to Training
Wide Band Gap Devices for Power System
Flexible Circuits and Systems for Smart Biomedical Applications
A digitally controlled buck converter with current sensor-less adaptive voltage positioning (AVP) mechanism
A glance of the CASLab HSAIL SIMT GPU for OpenCL and TensorFlow applications
Machine learning opportunities and applications in SoC design
Beyond Digital Neuromorphic Hardware: Time-Based and Flash-Based Designs
Novel test analysis to improve structural coverage - A commercial experiment
International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019
An efficient memory controller for 3D heterogeneous integration platform
Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, April 28-30, 2014
Tunable and reconfigurable solutions using RFSOI-on-HR-Si technologies
Internet of Things: Connecting the physical and digital worlds
Hold violation analysis for functional test of ultra-low temperature circuits at room temperature
A capacitive cross-coupled GaN HEMT injection-locked frequency divider
Intelligence Everywhere: The Challenges and Opportunities for Semiconductor Designs
Slow-Down in Power Scaling and the End of Moore's Law?
A 84.7-DR wide BW incremental ADC using CT structure
Dark Silicon - A thermal perspective
Antenna-in-package design and module integration for millimeter-wave communication and 5G
10-Bit SAR ADC With Novel Pseudo-Random Capacitor Switching Scheme
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks
V2V & V2I for connected vehicle
Output selection for test response compaction based on multiple counters
Silicon Carbide devices open a new era of power electronics
Time-domain analog-to-digital converters with domino delay lines
An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator
R&D Activities for Capacity Enhancement Using 5G Ultra High-Density Distributed Antenna Systems
Terahertz electronics: Opportunities, challenges and technologies
A 10-bit 200-MS/s reconfigurable pipelined A/D converter
Design of 2D Systolic Array Accelerator for Quantized Convolutional Neural Networks
Massive MIMO detection VLSI design
Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems
A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors
A hardware-friendly method for rate-distortion optimization of HEVC intra coding
Embedded Bearing Fault Detection Platform Design for the Drivetrain System in the Future Industry 4.0 Era
Microscopic degradation models for advanced technology
A practical NoC design for parallel DES computation
Clocking for HPC Design: Challenges and Experience Sharing
An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
On efficient error-tolerability evaluation and maximization for image processing applications
Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced
Keep-Out-Zone analysis for three-dimensional ICs
A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion
SlewFTA: Functional Timing Analysis Considering Slew Propagation
MIMO fingerprinting-based particle filter for mobile positioning systems
What happens when circuits grow old: Aging issues in CMOS design
A digital IQ imbalance self-calibration in FDD transceiver
Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems
Spatial-correlation-aware soft error rate analysis using quasi-importance sampling
A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect
A slew rate self-adjusting 2×VDD output buffer With PVT compensation
Improving and optimizing reliability in future technologies with high-κ dielectrics
Adaptive test method on production system-level testing (SLT) to optimize test cost, resources and defect parts per million (DPPM)
Trends and directions in networking - Impact of virtualization and cloud
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs
AI Acceleration with RISC-V for Edge Computing