yusuke1997/dblp-id-title huggingface dataset:
Interval Based X-Masking for Scan Compression Architectures
Probabilistic Delay Budgeting for Soft Realtime Applications
Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation
Quality of Design from an IC Manufacturing Perspective
Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories
Useful clock skew optimization under a multi-corner multi-mode design framework
SEU tolerant SRAM cell
Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs
On evaluating speed path detection of structural tests
Effects of Package Stackups on Microprocessor Performance
LBIST pattern reduction by learning ATPG test cube properties
Avoiding unnecessary write operations in STT-MRAM for low power implementation
IPQ: IP Qualification for Efficient System Design
MAAS: Hiding Trojans in Approximate Circuits
Improved pipeline data flow for DySER-based platform
Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems
CMOS inverter delay model based on DC transfer curve for slow input
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications
Fast reliability exploration for embedded processors via high-level fault injection
Exploring shared memory and cache to improve GPU performance and energy efficiency
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains
Automatic post-layout flow validation tool for Deep Sub-micron process design kits
Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs?
A System for Automatic Recording and Prediction of Design Quality Metrics
An online framework for diagnosis of multiple defects in scan chains
The Challenges and Impact of Parasitic Extraction at 65 nm
Bring it On: Kinetic Energy Harvesting to Spark Machine Learning Computations in IoTs
6-T SRAM performance assessment with stacked silicon nanowire MOSFETs
Minimizing clock domain crossing in Network on Chip interconnect
Process variation aware DRAM design using block based adaptive body biasing algorithm
On-Chip Interconnect Inductance - Friend or Foe (Invited)
Aperiodic Tasks Scheduling of Energy Harvesting Embedded Systems
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield
Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
Device/system performance modeling of stacked lateral NWFET logic
Improving DNN Fault Tolerance using Weight Pruning and Differential Crossbar Mapping for ReRAM-based Edge AI
Self-Checking Performance Verification Methodology for Complex SoCs
Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design
Uncriticality-directed scheduling for tackling variation and power challenges
On improving the range of inductive proximity sensors for avionic applications
Bringing Manufacturing into Design via Process-Dependent SPICE Models
Very low supply voltage room temperature test to screen low temperature soft blown fuse fails which result in a resistive bridge
Impacts of Machine Learning on Counterfeit IC Detection and Avoidance Techniques
Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths
A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations
Variation Analysis of CAM Cells
Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
Statistical static timing analysis flow for transistor level macros in a microprocessor
Soft error rate determination for nanoscale sequential logic
Statistical methodology for modeling non-IID memory fails events
Quantized neural networks with new stochastic multipliers
A virtualization approach for MIPS-based MPSoCs
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives
An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks
0.13 micron: Will the Speed Bumps Slow the Race to Market?
Statistical Models and Frequency-Dependent Corner Models for Passive Devices
Swarm - A VLSI Timing, Fanout-aware Clustering Algorithm
Energy-aware scratch-pad memory partitioning for embedded systems
Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter
Data Replication in Banked DRAMs for Reducing Energy Consumption
Power Savings in USB Hubs Through A Proactive Scheduling Strategy
Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid
Color Counting and its Application to Path Delay Fault Coverage
A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip
Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate
Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy
Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees
A Low-cost keyword spotting architecture based on wavelet packets feature extraction for edge device
A 8b 10Ms/s Low Power Pipelined A/D Converter
An Automated Design Flow for Synthesis of Optimal Switching Power Supply
21st International Symposium on Quality Electronic Design, ISQED 2020, Santa Clara, CA, USA, March 25-26, 2020
Analysis of Process Variation's Effect on SRAM's Read Stability
Simulation and satisfiability guided counter-example triage for RTL design debugging
VLSI architectures of perceptual based video watermarking for real-time copyright protection
Invited: Towards a scalable neuromorphic hardware for classification and prediction with stochastic No-Prop algorithms
In-storage Processing of I/O Intensive Applications on Computational Storage Drives
On-line harmonic-aware partitioned scheduling for real-time multi-core systems under RMS
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Stealthy Conditional Trojans in Quantum Circuits
A Built-in self-calibration scheme for pipelined ADCs
SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design
Power and performance aware memory-controller voting mechanism
Design Space Extrapolation for Power Delivery Networks using a Transposed Convolutional Net
A DLL Based Multiphase Hysteretic DC-DC Converter
FPGA Accelerated Parameterized Cache Simulator
Real-Time Thermal Map Characterization and Analysis for Commercial GPUs with AI Workloads
Automated correction of design errors by edge redirection on High-Level Decision Diagrams
Fail-safe I/O to control RESET# pin of DDR3 SDRAM and achieve ultra-low system power
Hierarchical dynamic power management using model-free reinforcement learning
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process
17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, CA, USA, March 15-16, 2016
A Statistic-Based Approach to Testability Analysis
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM
Detection of malicious hardware components in mobile platforms
An EMI-Noise Analysis on LSI Design with Impedance Estimation
Is built-in logic redundancy ready for prime time?
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs
Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection Systems
Power-Gating Aware Floorplanning
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
Conditional Classification: A Solution for Computational Energy Reduction
A CMOS hysteretic DC-DC buck converter with a low output ripple voltage
Built-In Test of RF Mixers Using RF Amplitude Detectors
An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer Learning
Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation
RTKWS: Real-Time Keyword Spotting Based on Integer Arithmetic for Edge Deployment
Cache Design for Low Power and High Yield
Low-leakage SRAM Design with Dual V_t Transistors
Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis
Calligrapher: A New Layout Migration Engine Based on Geometric Closeness
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture
On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors
System-Level SRAM Yield Enhancement
Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
Non-Gaussian uncertainty propagation in statistical circuit simulation
Statistically Aware SRAM Memory Array Design
A Watermarking System for IP Protection by Buffer Insertion Technique
Design methodology of high performance on-chip global interconnect using terminated transmission-line
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique
Trusted Electronic Systems with Untrusted COTS
An Artificial Intelligence Approach to EDA Software Testing: Application to Net Delay Algorithms in FPGAs
Noise Model for Multiple Segmented Coupled RC Interconnects
Extending the Viability of IDDQ Testing in the Deep Submicron Era
Application-driven power efficient ALU design methodology for modern microprocessors
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
Clock Distribution Architectures: A Comparative Study
Predicting and Designing for the Impact of Process Variations and Mismatch on the Trim Range and Yield of Bandgap References
A study of decoupling capacitor effectiveness in power and ground grid networks
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences
Enhancing Self-sustaining IoT Systems with Autonomous and Smart UAV Data Ferry
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion
19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018
Data center power management for regulation service using neural network-based power prediction
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
Statistical full-chip dynamic power estimation considering spatial correlations
Performance evaluation of wireless networks on chip architectures
On discovery of "missing" physical design rules via diagnosis of soft-faults
Die Area Reduction by Decongesting Top Channels Using Novel Feedthrough Insertion Methodology in Hierarchical SoC Designs
Assessing chip-level impact of double patterning lithography
Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality
The Impact of Logic Locking on Confidentiality: An Automated Evaluation
Study of IC aging on ring oscillator physical unclonable functions
Power estimation methodology for a high-level synthesis framework
Variation Aware Timing Based Placement Using Fuzzy Programming
Design and Challenges of Edge Computing ASICs on Front-End Electronics
A highly reliable SEU hardened latch and high performance SEU hardened flip-flop
Thermal-Aware Floorplanning Using Genetic Algorithms
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
Realistic Worst-Case Modeling by Performance Level Principal Component Analysis
Equivalence checking between SLM and RTL using machine learning techniques
A Lightweight Neighbor-Averaging Technique for Reducing Systematic Variations in Physically Unclonable Functions
Platform-Based Design: A Path to Efficient Design Re-Use
Obfuscation-Resistant Hardware Malware Detection: A Stacked Denoising Autoencoder Approach
RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation
Low power scan bypass technique with test data reduction
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD
Framework for analog test coverage
A Deep Learning Approach for Ventricular Arrhythmias Classification using Microcontroller
Fast and energy-aware resource provisioning and task scheduling for cloud systems
Layout Printability Optimization Using a Silicon Simulation Methodology
A scalable curve-fit model of the substrate coupling resistances for IC design
Structural fault collapsing by superposition of BDDs for test generation in digital circuits
Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
Linear time calculation of state-dependent power distribution network capacitance
An Automated Shielding Algorithm and Tool For Dynamic Circuits
OPC-Friendly Bus Driven Floorplanning
Design of Hardware Accelerators to Compute Parametric Capacitance Tables
Towards Collaborative Intelligence Friendly Architectures for Deep Learning
Variation aware guard -banding for SOC static timing analysis
Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators
Device Boot-Up Security Restoration with Post-Quantum Split-Key KEM
A logic difference generator with spare cells consideration for ECO synthesis
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard
Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks
Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology
Deep Image Segmentation for Defect Detection in Photo-lithography Fabrication
Time-Domain Simulation of Variational Interconnect Models
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors
A Unified Optimal Voltage Selection Methodology for Low-Power Systems
LUTAccel: Look-up-Table Based Vector Systolic Accelerator on FPGAs
Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
Native Mode Functional Self-Test Generation for Systems-on-Chip
Low Power VLSI Architecture of Viterbi Scorer for HMM-Based Isolated Word Recognition
A novel flow for reducing clock skew considering NBTI effect and process variations
TED Thermo Electrical Designer: A New Physical Design Verification Tool
HFGCN: High-speed and Fully-optimized GCN Accelerator
One Approach to Analog System Design Problem Formulation
An Overview of Substrate Noise Reduction Techniques
Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)
Hardware Support for Trustworthy Machine Learning: A Survey
Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation
The Hidden Costs of Design Qualit
Shifting Methods: Adopting a Design for Manufacture Flow
A simplified methodology for complex analog module layout generation
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations
A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing
Matter: Multi-Stage Adaptive Thermal Trojan for Efficiency & Resilience Degradation
Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM
A 12.4μm 2 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation
Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs
Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics
Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation
Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches
Systematic Design of a Flash ADC for UWB Applications
An efficient approach to sip design integration
Soft error reduction through gate input dependent weighted sizing in combinational circuits
A Holistic Approach to SoC Verification
A wireless multifunctional monitoring system of tower body running state based on MEMS acceleration sensor
Lithography-aware layout modification considering performance impact
A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm
Clock mesh framework
Impacts of NBTI and PBTI effects on ternary CAM
Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew
Post-silicon tunable clock buffer allocation based on fast chip yield computation
A CMOS high dimming ratio power-LED driver with a preloading inductor current method
Exploiting the Presence of Abundant Zero Data to Improve NVM Lifespan
Dual-sided doped memristor and it's SPICE modelling for improved electrical properties
Hardware Trojan Detection Method for Inspecting Integrated Circuits Based on Machine Learning
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions
Simplify: Enable Quality, Enable Innovation
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations
An FPGA-based Emulation Process for Dynamic Quantum Circuits
Extracting Power Signature from Low Dropout Voltage Regulator for IoT Security
Pre-route Noise Estimation in Deep Submicron Integrated Circuits
FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection using Graph Convolutional Networks
On-Chip Inductance Extraction and Modeling
Orchestrated application quality and energy storage management in solar-powered embedded systems
Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification
Correct-by-Design CAD Enhancement for EMI Signal Integrity
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques
Adaptive mode assignment in performance-critical cyber-physical systems
ChipAdvisor: A Machine Learning Approach for Mapping Applications to Heterogeneous Systems
Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording system
Low-power Analog and Mixed-signal IC Design of Multiplexing Neural Encoder in Neuromorphic Computing
A novel physical failure analysis of MEMS motion sensor for interface inspection
Analytical Noise-Rejection Model Based on Short Channel MOSFET
Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning
Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs
Compressed CNN for Inferring Rapid RF Fingerprints Using Memristor Crossbar Array
Fast Electromigration Simulation for Chip Power Grids
Diagnosis and Design for Diagnosability for Internet Routers
Verification methodology to guarantee low routing resistance to well taps
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model
Techniques for Early Package Closure in System-in-Packages
Rethinking FPGA Security in the New Era of Artificial Intelligence
Instruction Prediction for Step Power Reduction
Linearly separable pattern classification using memristive crossbar circuits
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design
A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator
Impact of Interconnect Process Variations on Memory Performance and Design
Rollguard: Defending RPC Manipulation Attacks in Optimistic Rollups with Graph ML
Modular service-oriented platform architecture - a key enabler to SoC design quality
Compact Reduced Order Modeling for Multiple-Port Interconnects
Using the Open Library Architecture (OLA) Open Source API in Heterogeneous Design Flows (invited)
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform
Scan chain based IP fingerprint and identification
6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA
On-Chip Inductance in X Architecture Enabled Design
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip
Power-Delay Metrics Revisited for 90nm CMOS Technology
Learning-Enabled NoC Design for Heterogeneous Manycore Systems
Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains
The design of a low-power low-noise phase lock loop
Design and application of multimodal power gating structures
Keep All in Memory with Maxwell: A Near-SRAM Computing Architecture for Edge AI Applications
A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach
Impact of NBTI on SRAM Read Stability and Design for Reliability
RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration
Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization
A Technique for Designing Totally Self-Checking Domino Logic Circuits
Low power latch design in near sub-threshold region to improve reliability for soft error
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models
Dynamic Partial Reconfiguration of FPGAs for Energy-Efficient Machine Learning Inference in IoT Systems
Thermal via structural design in three-dimensional integrated circuits
Transistor design for 5nm and beyond: Slowing down electrons to speed up transistors
Quality Aspects of SOI Circuit Design (Tutorial Abstract)
The design of a low-power high-speed current comparator in 0.35-m CMOS technology
Redundancy Requirements for Embedded Memories
DFM: Impact analysis in a high performance design
Analysis and mitigation of NBTI aging in register file: An end-to-end approach
Compiler-assisted leakage energy optimization of media applications on stream architectures
Slap it Together and Ship it!
Buffer/flip-flop block planning for power-integrity-driven floorplanning
Machine Learning for Evaluating the Impact of Manufacturing Process Variations in High-Speed Interconnects
OBT implementation on an OTA-C band-pass filter
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
Charge-Based Core and the Model Architecture of BSIM5
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC
Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy
POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors
Design, Manufacture and Test - Quality Test Estimation
Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models