yusuke1997/dblp-id-title huggingface dataset:
Heterogeneous photonic Network-on-Chip with dynamic bandwidth allocation
Message from program chairs
Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
Optimizing the heterogeneous network on-chip design in manycore architectures
A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement
Calibration of propagation delay of flip-flops
A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receivers
T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect
Global interconnect optimization with simultaneous macrocell placement and repeater insertion
A Versatile & Adjustable 400 Node CMOS Oscillator Based Ising Machine to Investigate and Optimize the Internal Computing Principle
MOS current mode logic: design, optimization, and variability
A fully integrated charge sharing active decap scheme for power supply noise suppression
T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges
CMOS SoC for irrigation control
Can systems extend to polymer? SoP architecture design and challenges
Implementing high definition video codec on TI DM6467 SOC
RSNN: A Hybrid Framework Leveraging Gradient Boosting for Thermal Trojan Detection in Multi-Processor Systems-on-Chips
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology
Low-power driven standard-cell placement based on a multilevel force-directed algorithm
A low-power design of quantization for H.264 video coding standard
A 200 MS/s 8-bit Time-based Analog-to-Digital Converter with inherit sample and hold
Generative AI Augmented Induction-based Formal Verification
High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties
DyEKF: Dynamic Protection of Approximate NoC Communications Against Hardware Trojan Attacks
36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023
Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology
Time stretcher for a time-to-digital converter with a precisely matched current mirror
A SystemCAMS extension for the simulation of non-linear circuits
A CMOS 6 bit 250MS/s A/D converter with input voltage range detectors
Universal CMOS Diamond-Graph Circuit for Embedded Computing
P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs
A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment
Fluidity concept for NoC: A congestion avoidance and relief routing scheme
Rotator-based multiplexer network synthesis for field-data extractors
Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region
Cycle-Accurate ML-Based Power Modeling for RISC-V Cores Using RTL Simulations
Clock tree layout design for reduced delay uncertainty
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications
SoC framework for FPGA: A case study of LTE PUSCH receiver
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation
T2A: Clock implementation: A question of timing
Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation
Platform-Based Behavior-Level and System-Level Synthesis
A novel flexible foldable systolic architecture FIR filters generator
Plenary speaker: Era of SoCs: What is next?
Power optimization for FinFET-based circuits using genetic algorithms
On wiring delays reduction of tree-based FPGA using 3-D fabric
"Five Forces Shaping the Silicon World: Advanced sensing and intelligence in IoT and vision"
Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec
Clustering-Based-Approach for Hardware Implementation of Activation Functions
Modelling visual attention towards embodiment cognition on a reconfigurable and programmable system
Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing
Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array
On Reduction of Computations for Threshold Function Identification
A clock generator based on multiplying delay-locked loop
Protecting the Integrity of Processor Cores with Logic Encryption
Group Delay Compensation By Combining 3-tap FFE With CTLE for 80Gbps-PAM4 Optical Transmitter
Operating system support for dynamically reconfigurable SoC architectures
Computation and communication aware run-time mapping for NoC-based MPSoC platforms
Feasibility study for communication over Power Distribution Networks of microprocessors
Plenary speaker: "Processor-to-memory interface design methodologies for energy and performance efficiencies"
A 2.4-GHz dual-mode resizing power amplifier with a constant conductance output matching
A 144-configuration context MEMS optically reconfigurable gate array
Power minimization methodology for VCTL topologies
Resource allocation methodology for the segmented bus platform
Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs
An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications
Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications
A versatile fading simulator for on-chip verification of MIMO communication systems
A systematic approach to synthesis of verification test-suites for modular SoC designs
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control
Hierarchical power delivery network analysis using Markov chains
T2A: Analog and RF circuits
High-throughput MQ encoder for pass-parallel EBCOT in JPEG2000
Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling
An accelerator for classification using radial basis function neural network
Estimation of maximum application-level power supply noise
A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications
SOLARCAP: Super capacitor buffering of solar energy for self-sustainable field systems
VLSI design of area-efficient memory access architectures for quasi-cyclic LDPC codes
Secure Your SoC: Building System-an-Chip Designs for Security
F2B: On-chip fabrics
Spiking Neural Networks Design-Space Exploration Platform Supporting Online and Offline Learning
Accelerate On-Chip Artificial Neural Network Training: a Customised fNIRS Signals Processing System-on-Chip
Programmable Impulse and Random Noise Generation Circuit for Power Integrity Tests
A configurable packet classification architecture for Software-Defined Networking
Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research
Simultaneous voltage island generation and floorplanning
Tutorial 2A: 3D integration - challenges and advantages
Solar-supercapacitor harvesting system design for energy-aware applications
ReCPE: A PE for Reconfigurable Lightweight Cryptography
A BCH decoding architecture with mixed parallelization degrees for flash controller applications
PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures
On-chip self-calibrated process-temperature sensor for TSV 3D integration
Digital signal processors for communications, video infrastructure, and audio
Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder
Tutorial: The uncertain end to silicon
A multi-level collaboration low-power design based on embedded system
A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL
A multi-standard micro-programmable deblocking filter architecture and its application to VC-1 video decoder
Asymmetrical Write-assist for single-ended SRAM operation
Multi-standard sub-pixel interpolation architecture for video Motion Estimation
A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security
A high-performance parallel mode EBCOT encoder architecture design for JPEG2000
The IANET Hardware Accelerator for Audio and Visual Data Classification
A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders
Variation-aware Flip-Flop energy optimization for ultra low voltage operation
Novel secret-key IPR protection in FPGA environment
Layout regularity metric as a fast indicator of high variability circuits
Behavioral modeling of drain current of an avalanche ISFET near breakdown
Schematic-driven physical verification: Fully automated solution for analog IC design
Formal equivalence checking between SLM and RTL descriptions
Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators
A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum Transition
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology
MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoC
Fast techniques for standby leakage reduction in MTCMOS circuits
A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks
DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS
Designing for signal integrity in wave-pipelined SOC global interconnects
Novel ECC structure and evaluation method for NAND flash memory
Design and Prototyping of Custom SHA-3 Instruction for CVA6 RISC-V Core
Analytical noise model for avalanche ISFET sensor suitable for Next Generation Sequencing
Artificial Intelligence in Antenna Design and Optimization
Efficient multicasting scheme for irregular mesh-based NoCs
Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications
Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory
An Inverter-based On-chip Voltage Reference Generator for Low Power Application
An Analog Isolation Amplifier Using a Digital Optocoupler for Signal Transmission
A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system
Sealed mask ROM wafer with 5 mm magnetic resonant coupling for long-term digital data preservation
POMR: a power-optimal maze routing methodology
A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS
Power noise suppression technique using active decoupling capacitor for TSV 3D integration
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits
Partitioned reuse cache for energy-efficient soft-error protection of functional units
Diagnosing scan chains using SAT-based diagnostic pattern generation
Bus Buffer Evaluation of Different Arbitration Algorithms
Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric Programming
An efficient VLSI architecture for extended variable block sizes motion estimation
Design of a downlink baseband receiver for IEEE 802.16E OFDMA mode in high mobility
Power evaluation of the arbitration policy for different on-chip bus based SoC platform
A Two-Stage Path Planning Engine for Robot Navigation System
NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators
Realization of buck converter with adaptive variable-frequency control
Analog Circuits Fault Diagnosis Based on Machine Learning
ML-based Reinforcement Learning Approach for Power Management in SoCs
A New Perspective of Inscribing Temporal Encryption on Spatial MPV Imprints for PUF Design
"High Five": Arm's first 5nm Silicon in flip-chip!
Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols and Matching Information
Optimal realization of switched-capacitor circuits by symbolic analysis
Automated Deep Learning Platform for Accelerated Analog Circuit Design
Self-dual diamond-graph CMOS H-bridge logic family
A Flow Graph Technique for DFT Controller Modification
A CMOS RF tuning wide-band bandpass filter for wireless applications
A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware
Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs
A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systems
EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation
Microcells for ICA-SOC for remote sensing of high energy radiation
Thermal via planning for temperature reduction in 3D ICs
A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-based Cryptosystems
Emerging memristor technology enabled next generation cortical processor
A sensor-less NBTI mitigation methodology for NoC architectures
A stable chip-ID generating physical uncloneable function using random address errors in SRAM
A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interface
A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications
Research on crosstalk issue of through silicon via for 3D integration
3-D Topologies for Networks-on-Chip
Mapping of partial reconfigurable data flows to Xilinx FPGAs
Fully Integrated Switched-Capacitor DC-DC Converter With Self-Recovery Hysteresis Control
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams
Analog-to-digital conversion for SONET OC-192
A flow regulator for On-Chip Communication
Low power 120 KSPS 12bit SAR ADC with a novel switch control method for internal CDAC
Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs
A novel multiplier for high-speed applications
The triangle of power density, circuit degradation and reliability
A resistance deviation-to-time interval converter for resistive sensors
Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective
Deep Learning Acceleration using Digital-Based Processing In-Memory
A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC
Functional verifications for SoC software/hardware co-design: From virtual platform to physical platform
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design
Hardware Design Space Exploration in High-Level Synthesis Backend Featuring Online Arithmetic
Cache-locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUs
TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs
A wide tuning range QCCO based on CMOS active inductors
CMOS passive RFID transponder with read-only memory for low cost fabrication
Using Digital Twin Simulation with Pre-Silicon Verification in SW-Defined Vehicles
Substrate and Ground Noise Interactions in Mixed-Signal Circuits
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers
Statistical electro-thermal analysis with high compatibility of leakage power models
VCAS: Viewing context aware power-efficient mobile video embedded memory
Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage Range
Tutorial 2B: CMOS integrated system on a chip for neural interface applications
High defect tolerant low cost memory chips
A Systematic Study of Parallelization Strategies for Optimizing Scientific Computing Performance Bounds
Optimal Multiple-Bit Huffman Decoding
eNVM based In-memory Computing for Intelligent and Secure Computing Systems
A New Breed of Power-Aware Hybrid Shifters
Evolution of Embedded Platform Security Technologies: Past, Present & Future Challenges
DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security
MSMPX: Microarchitectural Extensions for Meltdown Safe Memory Protection
Selectable grained reconfigurable architecture (SGRA) and its design automation
A 3.8Ghz channel-select filter using 0.18μm CMOS
Compact Modeling and Design of Magneto-Electric Transistor Devices and Circuits
Digital LDO modeling for early design space exploration
Synchronous latency-insensitive design for multiple clock domain
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks
A DNN-Oriented Rapid Simulation Framework for Digital Processing-In-Memory Architectures
A 1.3 V 30-mW 8-BIT 166-MS/s A/D Converter in 0.18 μm CMOS with Reference Generator
A high speed and low power content-addressable memory(CAM) using pipelined scheme
Effective IP reuse for high quality SOC design
Usage Driven Relevance Analysis for IP Cores
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory
pbCAM: Probabilistically-banked Content Addressable Memory
Design in the nano-scale Era: Low-power, reliability, and error resiliency
Divided by Designs, United by Flow-Uniquified, modular and automated approach to improve design efficiency
The importance of benchmarking for charge-based and beyond CMOS devices
X-clock routing based on pattern matching
Resistorless on-die high voltage power supply noise measurement
Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip
Thursday Plenary: Anchoring Security in the Connected World
Novel start-up circuit with enhanced power-up characteristic for bandgap references
A novel approach to design a reversible shifter circuit using DNA
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs
A digitally self-calibrated low-noise 7-bit folding A/D converter
Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency
Optimizing Quantum Circuits for Arbitrary State Synthesis and Initialization
A Dynamic Expansion Order Algorithm for the SAT-based Minimization
SoC design of remote terminals for wireless telemetry system
An optimal design of a fault tolerant reversible multiplier
Embedded ICG-based Stroke Volume Measurement System: Comparison of Discrete-Time and Continuous-Time Architectures
Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications
Heloc-NoC: High-Efficiency and Low-Hop On-Chip Communication in 3D Network-on-Chips
W1A: Memories
Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design
A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations
Low-power signal integrity trainings for multi-clock source-synchronous memory systems
Statistical analysis and parametric yield estimation of standard 6T SRAM cell for different capacities
Efficient Low-bit-width Activation Function Implementations for Ultra Low Power SoCs
A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power
Leakage aware SER reduction technique for UDSM logic circuits
A digital background calibration technique for split DAC based SAR ADC by using redundant cycle
Multi-Clock DFT architecture for interface characterization and power
Analysis of retention time under multi-configuration on a DORGA
Capacitance change estimation for an immunosensor chip
Keynote speaker: Driving innovation in the "post-silicon" world
A current bleeding mixer based on Gilbert-cell featuring LO amplification
Architecture for Energy Efficient Sphere Decoding
FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level
Banquet speaker: "The MP3 story and more: Perceptual audio coding from its beginnings to the present"
XANDAR: Verification & Validation Approach for Safety-critical Systems
VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera
Banquet speaker
Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror
FPGA implementation of the "pyramids" block cipher
Networks on chip design for real-time systems
Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation
Automated, inter-macro channel space adjustment and optimization for faster design closure
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices
Smart-flooding: A novel scheme for fault-tolerant NoCs
High-performance energy-efficient memory circuit technologies for sub-45nm technologies
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
Establishing Cyber Resilience in Embedded Systems for Securing Next-Generation Critical Infrastructure
A generic reconfigurable neural network architecture as a network on chip
A novel design of a Dual Functionality Read-Write driver for SRAM
Methodology to determine dominant noise source in a system-on-chip based implantable device
Mutation-analysis driven functional verification of a soft microprocessor
Cryogenic Characterization and Compact Modeling of Forward Body-Bias Effects in 180nm Bulk CMOS Transistors
Deep Reinforcement Learning for Self-Configurable NoC
Hardware Design of Sphere Decoding for MIMO Systems
Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices
A Clock Isolation Method For Complex SoC Designs
A CAD methodology for automatic topology selection & sizing
Fast dynamic power estimation considering glitch filtering
NFA decomposition and multiprocessing architecture for parallel regular expression processing
Programmable CRC circuit architecture
Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade?
Instruction set customization for area-constrained FPGA designs
33rd IEEE International System-on-Chip Conference, SoCC 2020, Las Vegas, NV, USA, September 8-11, 2020
FPGA Based Co-design of Storage-side Query Filter for Big Data Systems
A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications
Low power circuit optimization for IoT
Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier
Taskrunner: A Flexible Framework Optimized for Low Latency Quantum Computing Experiments
Building an Acceleration Overlay for Novice Students
An improved distributed video coding with low-complexity motion estimation at encoder
Interactive Transaction Tracker to Validate Data Integrity of the Compression and Decompression Engines in Neural Camera Applications
Hardware-aware Gradient-based Column-wise Mixed-Precision Quantization for Compute-in-Memory Accelerators
MAZENOC: Novel approach for fault-tolerant NOC routing
Mitigation of Hardware Trojan in NoC using Delta-Based Compression
Leveraging Multi-Layer Crypto-Logic Cross-Coupled with Encoded Code Converter and Conditional Control Flow for Robust Key-Based HLS IP Watermarking
T1A: Opportunities and challenges for secure hardware and verifying trust in integrated circuits
Tutorial: Macro-modeling for solving SOC physical design automation problems
Bit Transition Reduction by Data Transmission Ordering in NoC-based DNN Accelerator
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC
29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016
De-Cache: A novel caching scheme for large-scale NoC based multiprocessor systems-on-chips
Leakage Power Analysis (LPA) Attack in Breakdown Mode and Countermeasure
Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators
A high resolution capacitance deviation-to-digital converter utilizing time stretching
Power characteristics of Asynchronous Networks-on-Chip