yusuke1997/dblp-id-title huggingface dataset:
On the Brink of a New Era in VLSI Design
Process-Variation Aware Multi-temperature Test Scheduling
Self timed division and square-root extraction
A 600MHz Half-Bit Level Pipelined Multiplier Macrocell
Design Migration Across Technology - Making It Work
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis
Low Power Hardware Architecture for VBSME Using Pixel Truncation
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
Performance Aspects of Gate Matrix Layout
A Novel Specification Based Test Pattern Generation Using Genetic Algorithm and Wavelets
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks
Design For Testability: Today And In The Future
A Single Supply Level Shifter for Multi-Voltage Systems
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems
Stitch-avoiding Global Routing for Multiple E-Beam Lithography
Resource-Constrained Compaction of Sequential Circuit Test Sets
Automatic Validation Test Generation Using Extracted Control Models
Optimized QAOA ansatz circuit design for two-body Hamiltonian problems
A New Test Compression Scheme
Hardware Efficient Piecewise Linear Branch Predictor
Exploiting Radio Hierarchies for Power-Efficient Wireless Device Discovery and Connection Setup
Synthesis of System-on-a-chip for Testability
JAGUAR: a high speed VLSI chip for JPEG image compression standard
Diagnostic Tests for Pre-bond TSV Defects
A Methodology and Tooling Enabling Application Specific Processor Design
Some Recent Advances in Software and Hardware Logic Simulation
Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation
Lifetime Reliability Aware Architectural Adaptation
Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process
OaSis: An Application Specific Operating System for an Embedded Environment
Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits
7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer
Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit
Effects of Multi-cycle Sensitization on Delay Tests
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking
A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework
Synthesis of Configurable Architectures for DSP Algorithms
Reinforcement Temporal Difference Learning Scheme for Dynamic Energy Management in Embedded Systems
Certifiable and Efficient Autonomous Cyber-Physical Systems Design
Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array
Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
New Directions in Hardware Security
An On-Chip Coupling Capacitance Measurement Technique
On-Chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier
Hardware Trojan Detection Using ATPG and Model Checking
An Alternative Real-Time Filter Scheme to Block Buffering
Ultra-Low Power Non-Uniform SAR ADC based ECG detector for Early Detection of Cardiovascular Diseases
Way Sharing Set Associative Cache Architecture
An Expert System Approach to Analog Circuit Synthesis
Distributed logic simulation: time-first evaluation vs. event driven algorithms
A New Logic Encryption Strategy Ensuring Key Interdependency
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire
Design of OTA Based Field Programmable Analog Array
High Performance Over-the-Cell Routing
Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry
Design of an On-Line Euclidean Processor
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation
False Path Detection at Transistor Level
Fast Error Diagnosis for Combinational Verification
Implementation of Read- k-times BDDs on Top of Standard BDD Packages
Modeling of High Frequency Noise in SOI MOSFETs
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture
Delay Skew Reduction in IO Glitch Filter
VLSI Design Challenges for Gigascale Integration
A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps
PrOFraC: Property Ordering and Frame Clause Reuse for Multi-Property Verification
Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric Authentication
Dual Code Compression for Embedded Systems
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation
Two Graph Based Circuit Simulator for PDE-Electrical Analogy
Operand Isolation with Reduced Overhead for Low Power Datapath Design
Complexity Of Minimum-Delay Gate Resizing
AATMA: an algorithm for technology mapping for antifuse-based FPGAs
Task Graph Extraction for Embedded System Synthesis
Path Based Timing Validation for Timed Asynchronous Design
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression
EDA-The Next Generation
Inductance Characterization of Small Interconnects Using Test-Signal Method
An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications
Energy Efficient Hardware Synthesis of Polynomial Expressions
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification
Localized Heating for Building Energy Efficiency
Software Power Optimizations In An Embedded System
BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware Circuits
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch
CMOS Digital Imager Design from a System-on-a-chip Perspective
IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT Applications
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile
A Technology Mapper for Xilinx FPGAs
CARM: Congestion Adaptive Routing Method for On Chip Networks
Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation
Architectures for Arithmetic over GF(2 m )
Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition System
An Efficient Design of a Reversible Barrel Shifter
On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme
High Speed Serial Link Transmitter for 10Gig Ethernet Applications
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores
Towards a Symbolic Logic Minimization Algorithm
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems
Parasitic-Aware Automatic Analog CMOS Circuit Design Environment
Definition, Design & Development of the IXE2424 Network Switch/Router ASIC
A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction
PLA based synthesis and testing of hazard free logic
CMOS Scaling for sub-90 nm to sub-10 nm
Evolution of Architectural Concepts and Design Methods of Microprocessors
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
Tuning Schemes for Transmission Zeros of Continuous-Time Filters
Modeling of Linear Variable Differential Transformer
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application
A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal
Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model
A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement
Design and Implementation of Low-Power High-throughput PRNGs for Security Applications
Design of Deep Sub-Micron CMOS Circuits
Artificial neural network-based solution for PSP MOSFET model card extraction
A Low Noise Bandgap Reference with 0.89 V Vref, 0.88 μVrms noise and 80 dB of PSRR
nvited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality?
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories
A High Throughput ASCON Architecture for Secure Edge IoT Devices
Enhanced Performance Parameters of Magnetic Tunnel Junction with Composite Dielectric Barrier
Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL)
An Analytical Delay Model Based on Boolean Process
Signal Agnostic Scalable Scan Wrapper Design
Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA
A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package
Accelerating Hash Computations Through Efficient Instruction-Set Customisation
Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis
On Methods to Improve Location Based Logic Diagnosis
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis
MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing
A RISC Hardware Platform for Low Power Java
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
Asynchronous Design - An Interesting Alternative
Low Energy Switch Block For FPGAs
Physics and Technology: Towards Low-Power DSM Design
How to Half Wire Lengths in the Layout of Cyclic Shifter
Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs
Timing Minimization by Statistical Timing hMetis-based Partitioning
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO
A Low Power Video Frequency Continuous Time Filter
Synchronous Test Generation Model for Asynchronous Circuits
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller
A Tight Area Upper Bound for Slicing Floorplans
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip
A Parallel and Accelerated Circuit Simulator with Precise Accuracy
Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores
An Empirical Study on the Effects of Physical Design in High-Level Synthesis
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors
Startup Circuit for Relaxation Oscillators with Low Functional Current and Minimal Area
Data Path Testability Evaluation via Functional Testability Measures
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS
Silicon-Level Physical Verification of Sub Wavelength(tm) Designs
DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders
Parallel test generation with low communication overhead
Gain, NF and IIP3 Budgeting of LTE Receiver Front End
A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance
Tutorial: CMOS Analog Circuits for Wireless Communications
SmartExtract: Accurate Capacitance Extraction for SOC Designs
FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors
Recent Advances in BDD Based Representations for Boolean Functions: A Survey
Structural Testing: Vmin Silicon Issues and Solutions
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs
Towards Near Data Processing of Convolutional Neural Networks
Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing
Functional Verification of Programmable DSP Cores
Robust testing for stuck-at faults
Design of MoS2 based Inverter Circuits considering Interface Trap effect
Design of an Application Specific VLSI Chip for Image Rotation
PPU: Privacy-Aware Purchasing Unit for Residential Customers in Smart Electric Grids
Flipping Modules to Improve Circuit Performance and Routability
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis
A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS Technology
Fast DC Analysis and Its Application to Combinatorial Optimization Problems
Genetic Algorithms for Scan Path Design
Cryptosystem Designed for Embedded System Security
Embedded Test for Low Cost Manufacturing
Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis
Allocation of FIFO Structures in RTL Data Paths
Euclidean Shortest Path Problem with Rectilinear Obstacles
Implementing LDPC Decoding on Network-on-Chip
ESD Reliability Challenges for RF/Mixed Signal Design & Processing
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits
An mmWave Frequency Range Multi-Modulus Programmable Divider for FMCW Radar Applications
37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024
Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering
CODAC-a characterization system for digital and analog circuits
A Tug-of-War Between Static and Dynamic Memory in Intel SGX
India-Building the Tall, Thin VLSI Engineer
Science, Technology, and the Indian Society
Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect
Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor
Keynote Talk: Challenges in Automotive Cyber-physical Systems Design
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks
Online Detection and Reactive Countermeasure for Leakage from BPU Using TVLA
Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing
Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms
A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock
Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults
Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture
Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers
Energy Driven Application SelfAdaptation
FPUGen: A FrameWork to Generate Custom Floating Point FMA Accelerators on FPGAs
NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems
A Novel Hierarchical Test Generation Method for Processors
A 180 o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors
Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples
An Accurate Energy and Thermal Model for Global Signal Buses
Micropipeline Architecture for Multiplier-less FIR Filters
A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture
Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems
EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings
Design and Implementation of High Speed RNS Input-Output Converters
A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications
A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs
A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source
Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling
A Quadrature-Phase Voltage Controlled Oscillator for Offset Phase and Frequency Compensation
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment
35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022
High Speed Robust Current Sense Amplifier for Nanoscale Memories: - A Winner Take All Approach
The High Walls have Crumpled
A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity Mode
Investigating Impact of Bit-flip Errors in Control Electronics on Quantum Computation
Energy Efficient Power Distribution on Many-Core SoC
Register Transfer Operation Analysis during Data Path Verification
Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding
An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators
A Very High Gain Bandwidth Product Fully Differential Amplifier
On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time
A Framework for Distributed and Hierarchical Design-for-Test
Average Power in Digital CMOS Circuits using Least Square Estimation
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor
FLOR: A Hierarchical Floorplanner Under Vinyas VCX System - System Overview
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators
34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021
A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGA
Processor Evaluation in an Embedded Systems Design Environment
Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver
CAE in Requirements Definition and Specification for Complex Microelectronic Systems
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors
A Methodology for Placement of Regular and Structured Circuits
ABMF: Adaptive Bonsai Merkle Forests for Efficient Integrity Verification in Secure Persistent Memories
K Band High Power Broadband AlGaN/GaN HEMT Balanced Power Amplifier for Satellite Transponder
A Modeling of a Dynamically Reconfigurable Processor Using SystemC
Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model
Tutorial T1: Design of Mixed-Signal Systems using SystemC AMS Extensions
Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
Processing-in-Memory Architecture with Precision-Scaling for Malware Detection
Multi-Valued Logic Synthesis
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings
Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
DPFair Scheduling with Slowdown and Suspension
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic
Synthesis for Logical Initializability of Synchronous Finite State Machines
A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator
High Level Modeling and Validation Methodologies for Embedded Systems: Bridging the Productivity Gap
A Novel Approach for Improving the Quality of Open Fault Diagnosis
Random Access Analog Memory (RA2M) for Video Signal Application
Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs
Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis
Cosynthesis of multiprocessor architectures with high availability
IBM's Blue Logic Design Methodology-Circuits and Physical Design
MLTDRC: Machine Learning Driven Faster Timing Design Rule Check Convergence
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples
A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier
A Methodology for Switching Activity Based IO Powerpad Optimisation
A New Approach To Topology Selection For Cell-Level Analog Circuits
An Effective VHDL-AMS Simulation Algorithm with Event Partitioning
Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits
On the ESD Reliability Issues in Carbon Electronics: Graphene and Carbon Nano Tubes
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs
A multiplier generator for Xilinx FPGAs
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation
MSimDRAM: Formal Model Driven Development of a DRAM Simulator
T1: Multimedia
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
An Object Oriented Environment for Modeling and Synthesis of Hardware Circuits
Testability-oriented channel routing
UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures
Verification of Systems-on-Chip Designs
Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs
Estimation of Power from Module-level Netlists
Embedded Security
Security Assessment of Microfluidic Fully-Programmable-Valve-Array Biochips