yusuke1997/dblp-id-title huggingface dataset:
Wave pipelining for application-specific networks-on-chips
An optimistic and conservative register assignment heuristic for chordal graphs
Automatic detection of fault attack and countermeasures
Aging-aware hardware-software task partitioning for reliable reconfigurable multiprocessor systems
Work-in-Progress: Towards Evaluating CNNs Against Integrity Attacks on Multi-tenant Computation
Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)
Embedded reconfigurable architectures
Performance-driven syntax-directed synthesis of asynchronous processors
Code generator optimizations for the ST120 DSP-MCU core
Vectorizing for a SIMdD DSP architecture
Hardware evaluation of the Luffa hash family
Hardware approximate computing: how, why, when and where? (special session)
Education Abstract: Design Space Exploration for Deep Learning at the Edge
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
An adaptive chip-multiprocessor architecture for future mobile terminals
Enabling large decoded instruction loop caching for energy-aware embedded processors
A post-compiler approach to scratchpad mapping of code
Fast enumeration of maximal valid subgraphs for custom-instruction identification
Computation offloading to save energy on handheld devices: a partition scheme
HW / SW partitioning approach for reconfigurable system design
Matrix multiplication beyond auto-tuning: rewrite-based GPU code generation
Simple offset assignment in presence of subword data
Probabilistic reasoning for analysis of approximate computations
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications
A dynamic binary instrumentation engine for the ARM architecture
Mosaic of organic development through technology intervention in the rural indian context
COMET: communication-optimised multi-threaded error-detection technique
Reducing shift penalty in Domain Wall Memory through register locality
Lazy cache invalidation for self-modifying codes
A low-cost memory interface for high-throughput accelerators
GeMS: a generator for modulo scheduling problems: work in progress
The era of embedded computing
Efficient Neural Networks: from SW optimization to specialized HW accelerators
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2020, Singapore, September 20-25, 2020
The performance and energy consumption of three embedded real-time operating systems
Expandable process networks to efficiently specify and explore task, data, and pipeline parallelism
Cost-effective safety and fault localization using distributed temporal redundancy
2016 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016
Construction of GCCFG for inter-procedural optimizations in Software Managed Manycore (SMM) architectures
Redesigning a tagless access buffer to require minimal ISA changes
Proceedings of the 9th Workshop on Embedded Systems Security, WESS '14, New Delhi, India, October 17, 2014
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems
Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors
Cluster assignment of global values for clustered VLIW processors
Design space exploration of the turbo decoding algorithm on GPUs
Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs
Integrating software caches with scratch pad memory
Self-powered wearable sensor node: Challenges and opportunities
Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2018, Torino, Italy, September 30 - October 05, 2018
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures
A novel approach to code analysis of digital signal processing systems
The emerging power crisis in embedded processors: what can a poor compiler do?
On-the-fly load data value tracing in multicores
System-level modeling and synthesis of flow-based microfluidic biochips
Predictable programming on a precision timed architecture
Control flow optimization in loops using interval analysis
Fault detection and recovery efficiency co-optimization through compile-time analysis and runtime adaptation
PROMPT: a mapping environment for telecom applications on "system-on-a-chip"
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
Hardware/software architecture for flash memory storage systems
Towards industry strength mapping of AUTOSAR automotive functionality on multicore architectures: work-in-progress
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
A software development tool chain for a reconfigurable processor
Cognitive cameras: Assistive vision systems
Hardware support for code integrity in embedded processors
Work-in-Progress: Reliability Evaluation of Power SCADA System with Three-Layer IDS
Scenario-based design flow for mapping streaming applications onto on-chip many-core systems
A signature based architecture for Trojan detection
Digital fingerprints for low-cost platforms using MEMS sensors
Proceedings of the 14th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011
MTSS: multi task stack sharing for embedded systems
Dynamic on-chip memory management for chip multiprocessors
Adapting software pipelining for reconfigurable computing
Work-in-Progress: NoRF: A Case Against Register File Operands in Tightly-Coupled Accelerators
Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005
Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors
Eliminating false phase interactions to reduce optimization phase order search space
Automated compile-time and run-time techniques to increase usable memory in MMU-less embedded systems
Compiling custom instructions onto expression-grained reconfigurable architectures
Mitigating Write Disturbance in Phase Change Memory Architectures
Energy aware task scheduling with task synchronization for embedded real time systems
Extending STI for demanding hard-real-time systems
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Computation Offloading of Acoustic Model for Client-Edge-Based Speech-Recognition
A vision for embedded software
Patchable instruction ROM architecture
Hardware-assisted security enhanced Linux in embedded systems: a proposal
FlashCache: a NAND flash memory file cache for low power web servers
Minimizing bank selection instructions for partitioned memory architecture
Compiler generation from structural architecture descriptions
Scenario-based software characterization as a contingency to traditional program profiling
Cost-efficient soft error protection for embedded microprocessors
A hybrid just-in-time compiler for android: comparing JIT types and the result of cooperation
The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators
2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems, CASES 2019, Work in Progress Papers, New York, NY, USA, October 13-18, 2019
REDEFINE ® ™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)
Iterative procedural abstraction for code size reduction
Optimal loop parallelization for maximizing iteration-level parallelism
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014
EnVM: Virtual memory design for new memory architectures
An architecture for embedded software integration using reusable components
Splitting functions into single-entry regions
Application driven embedded system design: a face recognition case study
An efficient system-on-a-chip design methodology for networking applications
A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software
Work-in-Progress: Object Detection Acceleration Method by Improving Execution Efficiency of AI Device
Work-in-Progress: CAMiSE: Content Addressable Memory-integrated Searchable Encryption
Automatic generation of hardware/software interfaces
Exploiting bank locality in multi-bank memories
Hardware trust implications of 3-D integration
Architectural optimizations for low-power, real-time speech recognition
Ensuring code safety without runtime checks for real-time control systems
A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Effective Profiling for Data-Intensive GPU Programs: Work-in-Progress
Loop-based leakage control for branch predictors
Cycle-time aware architecture synthesis of custom hardware accelerators
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systems
Countermeasures against fault attacks on software implemented AES: effectiveness and cost
Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007
Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001
Highly energy and performance efficient embedded computing through approximately correct arithmetic: a mathematical foundation and preliminary experimental validation
Multi-grained performance estimation for MPSoC compilers: work-in-progress
Hardware implementation of the Ravenscar Ada tasking profile
A prototype network embedded in textile fabric
Dynamic battery state aware approaches for improving battery utilization
Energy-efficient VFI-partitioned multicore design using wireless NoC architectures
D-PUF: an intrinsically reconfigurable DRAM PUF for device authentication in embedded systems
Resource recycling: putting idle resources to work on a composable accelerator
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size
Stack size reduction of recursive programs
Frequent loop detection using efficient non-intrusive on-chip hardware
Hardware assisted control flow obfuscation for embedded processors
Vertical object layout and compression for fixed heaps
A method-based ahead-of-time compiler for android applications
Automating custom-precision function evaluation for embedded processors
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions
Analysis of the split mask countermeasure for embedded systems
An efficient heuristic for instruction scheduling on clustered vliw processors
Work-in-Progress: Ultra-fast yet Accurate Performance Prediction for Deep Neural Network Accelerators
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Eliminating external fragmentation in a non-moving garbage collector for Java
CAPED: Context-aware personalized display brightness for mobile devices
Anomalous path detection with hardware support
Design and Optimization for AI/ML Acceleration on Resource-constrained and Edge Systems
Automatized high-level evaluation of security properties for RTL hardware designs
EVA: An efficient vision architecture for mobile systems
Instruction set extensions for software defined radio on a multithreaded processor
Quality-aware data allocation in approximate DRAM?
A novel thread scheduler design for polymorphic embedded systems
Energy management for commodity short-bit-width microcontrollers
Improving the performance and power efficiency of shared helpers in CMPs
Efficient longest executable path search for programs with complex flows and pipeline effects
From sequential programming to flexible parallel execution
A low-power accelerator for the SPHINX 3 speech recognition system
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
A case study of on-chip sensor network in multiprocessor system-on-chip
Real-time unobtrusive program execution trace compression using branch predictor events
Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study
Approximation-aware Multi-Level Cells STT-RAM cache architecture
Dynamic hardware specialization-using moore's bounty without burning the chip down
Process cruise control: event-driven clock scaling for dynamic power management
Special Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond
Enabling OpenVX support in mW-scale parallel accelerators
An accelerator-based wireless sensor network processor in 130nm CMOS
Reconfigurable accelerator on FPGA for scientific computing : From a space-borne instrument to a high-performance computing data center
Studying optimal spilling in the light of SSA
Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009
Improving NVMe SSD I/O determinism with PCIe virtual channel: work-in-progress
AES and the cryptonite crypto processor
Textiles and computing: background and opportunities for convergence
Enhancing network-on-chip components to support security of processing elements
Lattice-based memory allocation
PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors
Embedded cache architecture with programmable write buffer support for power and performance flexibility
Work-in-Progress: A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM
Programming challenges in network processor deployment
Storage allocation for embedded processors
Balancing register pressure and context-switching delays in ASTI systems
Work in Progress: Emulation of biological tissues on an FPGA
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip
Global property violation detection and diagnosis for wireless sensor networks
An confidentiality and integrity scheme for the distributed shared memory of embedded multi-core system: work in progress
A scalable wide-issue clustered VLIW with a reconfigurable interconnect
On achieving balanced power consumption in software pipelined loops
Predictable programs in barcodes
Power efficient encoding techniques for off-chip data buses
Automatic Generation of Application-Specific FPGA Overlays
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006
From software to accelerators with LegUp high-level synthesis
Hybrid multithreading for VLIW processors
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints
Code transformation strategies for extensible embedded processors
Vector class on limited local memory (LLM) multi-core processors
Flexible instruction processors
The microarchitecture of FPGA-based soft processors
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration
Page Reuse in Cyclic Thrashing of GPU Under Oversubscription: Work-in-Progress
Tutorial: Designing an Edge Inferencing Accelerator with High- Level Synthesis
Proceedings of the 5th Workshop on Embedded Systems Security, WESS 2010, Scottsdale, AZ, USA, October 24, 2010
Work-in-Progress: QRCNN: Scalable CNNs
Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008
Facilitating compiler optimizations through the dynamic mapping of alternate register structures
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
CFLRU: a replacement algorithm for flash memory
Application specific architectures: a recipe for fast, flexible and power efficient designs
Cyber physical systems: Systems engineering of industrial embedded systems - Barriers, enablers and opportunities
Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress
High-performance packet classification algorithm for many-core and multithreaded network processor
Efficient architecture/compiler co-exploration for ASIPs
Minimizing code size via page selection optimization on partitioned memory architectures
Entropy-based low power data TLB design
Embedded system and application aware design of deregulated energy delivery systems
Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic of Korea, October 15-20, 2017
Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization
Risk management in embedded devices using metering applications as example
General loop fusion technique for nested loops considering timing and code size
EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems
Power management of MEMS-based storage devices for mobile systems
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
A Lifelong Health Monitoring Framework in Processors: Work-in-Progress
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
Reducing pressure in bounded DBT code caches
An integrated approach to reducing power dissipation in memory hierarchies
Design space characterization for architecture/compiler co-exploration
Memory optimization by counting points in integer transformations of parametric polytopes
Towards automatic synthesis of a class of application-specific sensor networks
Routing-based synthesis of digital microfluidic biochips
ECC Management with Rate Compatible LDPC Code for NAND Flash Storage
RISC-TAE: Instruction Set Extension for Transformer Model Acceleration
RRAM based learning acceleration
A dynamic code placement technique for scratchpad memory using postpass optimization
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads
Static task partitioning for locked caches in multi-core real-time systems
Multi-granularity sampling for simulating concurrent heterogeneous applications
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
Work-in-Progress: Efficient Low-latency Near-Memory Addition
An efficient technique for exploring register file size in ASIP synthesis
Timing characterization of OpenMP4 tasking model
Exploiting residue number system for power-efficient digital signal processing in embedded processors
Automatic data partitioning for the agere payload plus network processor
Fast and fair: data-stream quality of service
Fast generation of optimized execution plans for parameterizable CNN accelerators: work-in-progress
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations
Enabling parametric feasibility analysis in real-time calculus driven performance evaluation
Revisiting level-0 caches in embedded processors
The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems
A new look at exploiting data parallelism in embedded systems
Optimizing stream programs using linear state space analysis
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks
Mapping stream programs onto heterogeneous multiprocessor systems
Static next sub-bank prediction for drowsy instruction cache
Work-in-Process: Smart Migration for Reliability Enhancement of 3D TLC NAND Flash Storage Systems
Hardware trojan design and detection: a practical evaluation
Strong PUFs and their (physical) unpredictability: a case study with power PUFs
Detection, traceback and filtering of denial of service attacks in networked embedded systems
Compiled multithreaded data paths on FPGAs for dynamic workloads
Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions
AdaPNet: Adapting process networks in response to resource variations
Transparent data-memory organizations for digital signal processors
SSS: self-aware system-on-chip using static-dynamic hybrid method (work-in-progress)
A dynamic memory management unit for embedded real-time system-on-a-chip
Automatic Extraction of pipeline parallelism for embedded heterogeneous multi-core platforms
Proceedings of the 4th Workshop on Embedded Systems Security, WESS 2009, Grenoble, France, October 15, 2009
Pattern matching in reconfigurable logic for packet classification
A programmable unified cache architecture for embedded applications
When less is more (LIMO): controlled parallelism forimproved efficiency
Adaptive and flexible dictionary code compression for embedded applications
State space reconfigurability: an implementation architecture for self modifying finite automata
Increasing power efficiency of multi-core network processors through data filtering
Reducing energy of virtual cache synonym lookup using bloom filters
Hierarchical coarse-grained stream compilation for software defined radio
Some RSSB constructions with improved resistance towards differential power analysis
Work-in-Progress: Smart data reduction in SLAM methods for embedded systems
Graph-coloring and treescan register allocation using repairing
A low-overhead interconnect architecture for virtual reconfigurable fabrics
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique
The Shift PUF: Technique for Squaring the Machine Learning Complexity of Arbiter-based PUFs: Work-in-Progress
Comprehensive isomorphic subtree enumeration
2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015, Amsterdam, The Netherlands, October 4-9, 2015
Evaluating and exploiting impacts of dynamic power management schemes on system reliability
Cost effective memory disambiguation for multimedia codes
Accuracy-aware optimization of approximate programs
Prediction based convolution neural network acceleration: work-in-progress
Compositional analysis of real-time embedded systems
Architectural support for real-time task scheduling in SMT processors
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003
Enabling NVM-based deep learning acceleration using nonuniform data quantization: work-in-progress
Analytical approaches for performance evaluation of networks-on-chip
Architecting processors to allow voltage/reliability tradeoffs
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions
Hardware-based data value and address trace filtering techniques
A system-on-a-chip lock cache with task preemption support
Energy efficient hybrid display and predictive models for embedded and mobile systems
NUVA: Architectural support for runtime verification of parametric specifications over multicores
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
An Esterel processor with full preemption support and its worst case reaction time analysis
Device Noises Resilient Training and Inference Framework for Smart Sensing on Analog Computing In Memory
Secure RPC in embedded systems: evaluation of some GlobalPlatform implementation alternatives
Work in Progress: ACAC: An Adaptive Congestion-aware Approximate Communication Mechanism for Network-on-Chip Systems