yusuke1997/dblp-id-title huggingface dataset:
In-place delay constrained power optimization using functional symmetries
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation
Data mining MPSoC simulation traces to identify concurrent memory access patterns
QSLC: Quantization-Based, Low-Error Selective Approximation for GPUs
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler
Efficient spectral techniques for sequential ATPG
Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph
AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation
Assembly-Related Chip/Package Co-Design of Heterogeneous Systems Manufactured by Micro-Transfer Printing
TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Resource-Efficient Heterogenous Federated Continual Learning on Edge
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs
Scalable Hardware Acceleration of Non-Maximum Suppression
Embedded tutorial - Understanding multicore technologies
A bridging fault model for line coverage in the presence of undetected transition faults
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
Analyzing CAN's Timing under Periodically Authenticated Encryption
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memory Architecture
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications
Generation of communication schedules for multi-mode distributed real-time applications
Random benchmark circuits with controlled attributes
A unified hardware/software MPSoC system construction and run-time framework
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems
Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications
SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction Codes
pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate
High performance AXI-4.0 based interconnect for extensible smart memory cubes
Feedback based droop mitigation
STG Optimisation in the Direct Mapping of Asynchronous Circuits
Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators
High-level synthesis for easy testability
FIFO cache analysis for WCET estimation: a quantitative approach
Bridging discrete and continuous time models with atoms
Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine Learning
Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language Processing
Remote testing and diagnosis of System-on-Chips using network management frameworks
NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators
Morphable Convolutional Neural Network for Biomedical Image Segmentation
Memory Organization with Multi-Pattern Parallel Accesses
Error Detection in Fault Secure Controllers using State Encoding
An Integrated Design Environment for Early Stage Conceptual Design
Design of an application-specific instruction set processor for high-throughput and scalable FFT
Machine-Learning-Driven Matrix Ordering for Power Grid Analysis
Efficient software implementation of ring-LWE encryption
Adaptive ODE Solvers for Timed Data Flow Models in SystemC-AMS
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio
A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network
Privacy-preserving functional IP verification utilizing fully homomorphic encryption
Exploiting System Dynamics for Resource-Efficient Automotive CPS Design
From Synchronous to Asynchronous: An Automatic Approach
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair
Accurate timing analysis using SAT and pattern-dependent delay models
A fault detection mechanism in a Data-flow scheduled Multithreaded processor
Extraction of defect density and size distributions from wafer sort test results
Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel
HyperSpike: HyperDimensional Computing for More Efficient and Robust Spiking Neural Networks
A fast and Effective DFT for test and diagnosis of power switches in SoCs
Fast Performance Evaluation Methodology for High-speed Memory Interfaces
Test Synthesis for Mixed-Signal SOC Paths
MixLock: Securing Mixed-Signal Circuits via Logic Locking
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers
A SAT Solver Using Software and Reconfigurable Hardware
Efficient Implementation of Native Software Simulation for MPSoC
Modeling electromagnetic emission of integrated circuits for system analysis
Fast and accurate resource conflict simulation for performance analysis of multi-core systems
Requirements-centric closed-loop validation of implantable cardiac devices
From DRUP to PAC and Back
Interface timing verification with delay correlation using constraint logic programming
Salvaging chips with caches beyond repair
SystemC-link: Parallel SystemC simulation using time-decoupled segments
Can IP Quality be Objectively Measured?
RNA: a reconfigurable architecture for hardware neural acceleration
On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure
EATBit: Effective automated test for binary translation with high code coverage
Exploiting Arbitrary Paths for the Simulation of Quantum Circuits with Decision Diagrams
Occupancy detection via iBeacon on Android devices for smart building management
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications
Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays
HEBS: Histogram Equalization for Backlight Scaling
Analog Layout Generation using Optimized Primitives
A Generative AI for Heterogeneous Network-on-Chip Design Space Pruning
Congestion Estimation with Buffer Planning in Floorplan Design
Capturing post-silicon variation by layout-aware path-delay testing
RTHeter: Simulating Real-Time Scheduling of Multiple Tasks on Heterogeneous Architectures
An Efficient Filter-Based Approach for Combinational Verification
Electric and electronic vehicle architecture assessment
Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems
GPGPUs: How to combine high computational power with high reliability
Test compaction for transition faults under transparent-scan
Using mission logic for embedded testing
Sweeping for Leakage in Masked Circuit Layouts
Always energy-optimal microscopic wireless systems
TaiChi: Efficient Execution for Multi-DNNs Using Graph-Based Scheduling
A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit
A dynamic self-adaptive correction method for error resilient application
PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNs
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture
DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network
Cost-efficient design for modeling attacks resistant PUFs
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering
Hardware Synthesis from C/C++
Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
Reconfigurable Signal Processing in Wireless Terminals
FairXbar: Improving the Fairness of Deep Neural Networks with Non-Ideal in-Memory Computing Hardware
Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic
Generalized Early Evaluation in Self-Timed Circuits
System design tools for broadband telecom network applications
Organic electronics - From lab to markets
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints
Microsystem design using simulator coupling
Improved worst-case response-time calculations by upper-bound conditions
A fault diagnosis methodology for the UltraSPARC TM -I microprocessor
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform
Verification of partial designs using incremental QBF solving
Technology mapping with all spin logic
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools
Partition-based exploration for reconfigurable JPEG designs
Control network generator for latency insensitive designs
A universal macro block mapping scheme for arithmetic circuits
Optimizing CoW-based File Systems on Open-Channel SSDs with Persistent Memory
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access
SPA: Simple pool architecture for application resource allocation in many-core systems
Exploring trade-off's between centralized versus decentralized automotive architectures using a virtual integration environment
A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge
Towards Coherent Semantics: A Quantitatively Typed EDSL for Synchronous System Design
Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology
An adaptive code rate EDAC scheme for random access memory
Model based hierarchical optimization strategies for analog design automation
Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies
GMDS: Hardware implementation of novel real output queuing architecture
Timing variation-aware custom instruction extension technique
An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems
Power Supply Noise Monitor for Signal Integrity Faults
Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting
A faithful binary circuit model with adversarial noise
EVASION: Efficient KV CAche CompreSsion vIa PrOduct QuaNtization
Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications
Health-care electronics The market, the challenges, the progress
Future memory and interconnect technologies
Parametric Built-In Self-Test of VLSI Systems
Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs
An Exact Schedulability Test for Non-Preemptive Self-Suspending Real-Time Tasks
SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators
Sequential logic minimization based on functional testability
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry
Multi-Level Analysis of GPU Utilization in ML Training Workloads
SDK4ED: One-click platform for Energy-aware, Maintainable and Dependable Applications
Sim2PIM: A Fast Method for Simulating Host Independent & PIM Agnostic Designs
Design challenges and emerging EDA solutions in mixed-signal IC design
Dynamic fault injection into digital twins of safety-critical systems
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
Robustness Evaluation of Localization Techniques for Autonomous Racing
An ultra-low power dual-mode ECG monitor for healthcare and wellness
Towards Low-Cost High-Accuracy Stochastic Computing Architecture for Univariate Functions: Design and Design Space Exploration
HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection
Modeling and simulation of mobile gateways interacting with wireless sensor networks
Interactions of large scale EV mobility and virtual power plants
Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs
Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded Systems
Bringing Theory to Practice: Predictability and Performance in Embedded Systems, DATE Workshop PPES 2011, Grenoble, France, March 18, 2011
Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices
Shared memory aware MPSoC software deployment
Leveraging access port positions to accelerate page table walk in DWM-based main memory
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation
Wire Retiming for System-on-Chip by Fixpoint Computation
Power Saving Techniques for Wireless LANs
Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing
Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips
Designing signal processing systems for FPGAs
DFARPA: Differential fault attack resistant physical design automation
Generation of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities
Automatic Tuning of Two-Level Caches to Embedded Applications
Mutation Sampling Technique for the Generation of Structural Test Data
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing
Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges
Mixed-level cosimulation for fine gradual refinement of communication in SoC design
Garbage collection for multi-version index on flash memory
Rapid prototype of a hardware emulator for a SIMD processor array
A method for testability analysis and BIST insertion at the RTL
An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP)
Efficient helper data reduction in SRAM PUFs via lossy compression
SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level
2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012
Attack Data Generation Framework for Autonomous Vehicle Sensors
A Case Study in Networks-on-Chip Design for Embedded Video
NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table
Compact model of memristors and its application in computing systems
Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications
Comparative analysis of SRAM memories used as PUF primitives
Microarchitecture floorplanning for sub-threshold leakage reduction
Component selection and matching for IP-based design
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction
A Hardware Platform for VLIW Based Emulation of Digital Designs
GATLB: A Granularity-Aware TLB to Support Multi-Granularity Pages in Hybrid Memory System
Hardware Trojans in incompletely specified on-chip bus systems
A Preliminary View on Automotive Cyber Security Management Systems
Defect aware X-filling for low-power scan testing
SystemC-AMS Requirements, Design Objectives and Rationale
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric
Flexible Group-Level Pruning of Deep Neural Networks for On-Device Machine Learning
FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs
Register placement for high-performance circuits
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check
Fault diagnosis of analog circuits based on machine learning
Amphi: Practical and Intelligent Data Prefetching for the First-Level Cache
ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design
A new paradigm for trading off yield, area and performance to enhance performance per wafer
On Exploiting Patterns For Robust FPGA-based Multi-accelerator Edge Computing Systems
Scalable probabilistic power budgeting for many-cores
Lookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language Models
Practical challenges in delivering the promises of real processing-in-memory machines
Statistical static timing analysis using a skew-normal canonical delay model
HW/SW implementation from abstract architecture models
Automated Activation of Multiple Targets in RTL Models using Concolic Testing
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs
PCC: a modeling technique for mixed control/data flow systems
AIL: description of a global electronic architecture at the vehicle scale
Determining relevant model elements for the verification of UML/OCL specifications
Fault Detection for Linear Analog Circuits Using Current Injection
ML-Based AIG Timing Prediction to Enhance Logic Optimization
Minimal Test for Coupling Faults in Word-Oriented Memories
Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine
Late Breaking Results: Improving Deep SNNs with Gradient Clipping and Noise Exploitation in Neuromorphic Devices
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Accurate Probabilistic Miss Ratio Curve Approximation for Adaptive Cache Allocation in Block Storage Systems
Design of 3D nanomagnetic logic circuits: A full-adder case study
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA
Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware
Towards a wireless medical smart card
Thermal-Aware Design and Management of Embedded Real-Time Systems
Optimal DC/AC data bus inversion coding
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing
Towards systematic design of 3D pNML layouts
ADOLT - An ADaptable On - Line Testing Scheme for VLSI Circuits
Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit Behaviors
Efficient validation input generation in RTL by hybridized source code analysis
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles
A UML frontend for IP-XACT-based IP management
Out-of-Distribution Detection Using Power-Side Channels for Improving Functional Safety of Neural Network FPGA Accelerators
A low overhead error confinement method based on application statistical characteristics
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems
Saliency aware display power management
Decision tree generation for decoding irregular instructions
An optimal approach for low-power migraine prediction models in the state-of-the-art wireless monitoring devices
OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing
Error resilience analysis for systematically employing approximate computing in convolutional neural networks
Accuracy Analysis for Stochastic Circuits with D Flip-Flop Insertion
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations
Implicit manipulation of polynomials using zero-suppressed BDDs
Wireless communication and energy harvesting in automobiles
Scalable Variational Quantum Circuits for Autoencoder-based Drug Discovery
Efficient decentralized active balancing strategy for smart battery cells
An Event-Based System for Low-Power ECG QRS Complex Detection
A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers
A CNN Compression Methodology for Layer-Wise Rank Selection Considering Inter-Layer Interactions
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
Statistical Timing Based Optimization using Gate Sizing
VAET-STT: A variation aware estimator tool for STT-MRAM based memories
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models
An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems
Throughput modeling to evaluate process merging transformations in polyhedral process networks
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
Virtual prototyping of embedded platforms for wireless and multimedia
VANDAL: A tool for the design specification of nanophotonic networks
In-growth test for monolithic 3D integrated SRAM
SPMS: Strand based persistent memory system
A methodology for interfacing open source systemC with a third party software
A compact digital amplitude modulator in 90nm CMOS
Using MTBDDs for discrete timed symbolic model checking
Examining the consequences of high-level synthesis optimizations on power side-channel
Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation
An ILP formulation for system-level application mapping on network processor architectures
ALLARM: Optimizing sparse directories for thread-local data
Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems
Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems
FRIDGE: A Fixed-Point Design and Simulation Environment
A Linux-governor based Dynamic Reliability Manager for android mobile devices
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck
Fault Clustering in deep-submicron CMOS Processes
Java, VHDL-AMS, ADA or C for System Level Specifications?
Voltage propagation method for 3-D power grid analysis
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
Multi-core architecture design for ultra-low-power wearable health monitoring systems
Computing approximately, and efficiently
Sequential circuit test generation using dynamic state traversal
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application
Energy-secure swarm power management
Beyond CMOS - benchmarking for future technologies
GPU4S: Major Project Outcomes, Lessons Learnt and Way Forward
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Multi-variant-based design space exploration for automotive embedded systems
Modeling and analysis of fault-tolerant distributed memories for networks-on-chip
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing
PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms
SAT-based fault coverage evaluation in the presence of unknown values
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter
Workload-aware power optimization strategy for asymmetric multiprocessors
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect