yusuke1997/dblp-id-title huggingface dataset:
The Notion of Cross Coverage in AMS Design Verification
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture
Fast floorplanning by look-ahead enabled recursive bipartitioning
LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable Accuracy
Three-dimensional integration technology and integrated systems
Advanced Packaging Technology and Design Methodology for Next Generation Chiplets
Buffered clock tree synthesis for 3D ICs under thermal variations
On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis
Algebraic and Boolean Methods for SFQ Superconducting Circuits
Toward Fair and Efficient Hyperdimensional Computing
A 52mW 1200MIPS compact DSP for multi-core media SoC
Logic and memory design using spin-based circuits
P2LSG: Powers-of-2 Low-Discrepancy Sequence Generator for Stochastic Computing
Practical methodology of post-layout gate sizing for 15% more power saving
Cryo-Compact Modeling Based on Sparse Gaussian Process
Conflict driven scan chain configuration for high transition fault coverage and low test power
Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system
Toward efficient programming of reconfigurable radio frequency (RF) receivers
Optimal SWAP gate insertion for nearest neighbor quantum circuits
Auriga2: a 4.7 million-transistor CISC microprocessor
Synthesis of Power Efficient Systems-on-Silicon
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
Behavioral modeling of EM devices by selective orthogonal matrix least-squares method
Configurable AMBA On-Chip Real-Time Signal Tracer
Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage Comparisons
Low power optimization technique for BDD mapped circuits
Aging-aware chip health prediction adopting an innovative monitoring strategy
Local approximation improvement of trajectory piecewise linear macromodels through Chebyshev interpolating polynomials
Reconfiguration-aware real-time scheduling under QoS constraint
A Time-to-Digital Converter with small circuitry
Scaled Population Arithmetic for Efficient Stochastic Computing
Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew
Embedded tutorial: essential issues for IP reuse
Hardware implementation of super minimum all digital FM demodulator
A 16-bit, low-power microsystem with monolithic MEMS- LC clocking
Reusable component IP design using refinement-based design environment
Finding an optimal functional decomposition for LUT-based FPGA synthesis
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
DPlace2.0: A stable and efficient analytical placement based on diffusion
Implicit prime compatible generation for minimizing incompletely specified finite state machines
Development of a waveform sampling front-end ASIC for PET
Temperature-aware MPSoC scheduling for reducing hot spots and gradients
Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization
MOSFET modeling for RF-CMOS design
Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling
Balanced truncation with spectral shaping for RLC interconnects
Interactive ray tracing on reconfigurable SIMD MorphoSys
Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers
Fault models and test generation for IDDQ testing: embedded tutorial
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU
Correlating system test Fmax with structural test Fmax and process monitoring measurements
Automated Trigger Activation by Repeated Maximal Clique Sampling
Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices
On enabling diagnosis for 1-Pin Test fails in an industrial flow
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Challenges to EDA system from the view point of processor design and technology drivers
Optimal module and voltage assignment for low-power
SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators
A smart position sensor for 3-D measurement
Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application
Variation-aware logic mapping for crossbar nano-architectures
ASP-DAC 2015 keynote speech II programmable network
On the impact of gate oxide degradation on SRAM dynamic and static write-ability
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs
Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning
Manifold construction and parameterization for nonlinear manifold-based model reduction
SAGA: synthesis technique for guaranteed throughput NoC architectures
Tackling signal electromigration with learning-based detection and multistage mitigation
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem
Physics-Informed Learning for EPG-Based TDDB Assessment
Statistical analysis of BTI in the presence of process-induced voltage and temperature variations
On-chip hybrid power supply system for wireless sensor nodes
An Integrated Battery-Hardware Model for Portable Electronics
Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI
Parameterized MAC unit implementation
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits
Zipper: Latency-Tolerant Optimizations for High-Performance Buses
Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs
High-performance global routing with fast overflow reduction
Partitioned model checking from software specifications
Importance of CAD tools and methodology in high speed CPU design: invited talk
Towards acceleration of deep convolutional neural networks using stochastic computing
Hardware debugging method based on signal transitions and transactions
Gen-Adler: the Generalized Adler's equation for injection locking analysis in oscillators
Control synthesis for the flow-based microfluidic large-scale integration biochips
Configurability of performance and overheads in flash management
Using fault model relaxation to diagnose real scan chain defects
Automated synthesis and verification of embedded systems: wishful thinking or reality?
VLSI on-chip power/ground network optimization considering decap leakage currents
Switching-activity driven gate sizing and Vth assignment for low power design
Multi-operand adder synthesis on FPGAs using generalized parallel counters
A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator
Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics
Combinatorial routing analysis and design of universal switch blocks
QoS-aware dynamic resource allocation for spatial-multitasking GPUs
Fanout-tree restructuring algorithm for post-placement timing optimization
FSM model abstraction for analog/mixed-signal circuits by learning from I/O trajectories
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories
Bridging fault testability of BDD circuits
Low-power techniques for network security processors
Real-Time Mobile Acceleration of DNNs: From Computer Vision to Medical Applications
Paired-Spacing-Constrained Package Routing with Net Ordering Optimization
A cycle-based synthesis algorithm for reversible logic
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance
Scalable stochastic-computing accelerator for convolutional neural networks
Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation Oscillator
Action coverage formulation for power optimization in body sensor networks
Optimization of VDD and VTH for low-power and high speed applications
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Layer assignment for crosstalk risk minimization
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
Satisfiability Don't Care condition based circuit fingerprinting techniques
Boosting chipkill capability under retention-error induced reliability emergency
Efficient Critical Paths Search Algorithm using Mergeable Heap
A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps
A novel data processing circuit in high-speed serial communication
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation
Design of a digital CDMA receiver
A Garbage Collection Aware Stripping method for Solid-State Drives
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model
25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020, Beijing, China, January 13-16, 2020
HK386: an x86-compatible 32-bit CISC microprocessor
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms
SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design
A two-dimensional transistor placement for cell synthesis
A scalable time-domain biosensor array using logarithmic cyclic time-attenuation-based TDC for high-resolution and large-scale bio-imaging
An integrated performance and power model for superscalar processor designs
Keynote I: "Designing heterogeneous systems in the AI era: Challenges and opportunities"
Application of linearly transformed BDDs in sequential verification
Using a dataflow abstracted virtual prototype for HdS-design
Adaptive admittance-based conductor meshing for interconnect analysis
Service adaptions for mixed-criticality systems
Lightweight and Secure Branch Predictors against Spectre Attacks
Constraint-driven bus matrix synthesis for MPSoC
Rapid layout pattern classification
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures
Distribution arithmetic for stochastical analysis
A 0.5 mm 2 Ambient Light-Driven Solar Cell-Powered Biofuel Cell-Input Biosensing System with LED Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact Lens
General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure
MINT: Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks
Module placement with boundary constraints using the sequence-pair representation
Needs and trends in embedded software development for consumer electronics
A Multi-Drop Transmission-Line Interconnect in Si LSI
Using loop invariants to fight soft errors in data caches
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits
A CMOS Smart Image Sensor LSI for Focal-Plane Compression
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction
BoostIID: Fault-agnostic Online Detection of WCET Changes in Autonomous Driving
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
Design methodology for SoC arthitectures based on reusable virtual cores
Full exploitation of process variation space for continuous delivery of optimal delay test quality
A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise
Cool and save: cooling aware dynamic workload scheduling in multi-socket CPU systems
ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning
Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification
SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device
Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator
Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessor
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement
21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016
A low power multimedia processor implementing dynamic voltage and frequency scaling technique
Dynamic admission control for real-time networks-on-chips
A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications
An RTL-to-GDS2 design methodology for advanced system LSI
High-Correlation 3D Routability Estimation for Congestion-guided Global Routing
NCFET to Rescue Technology Scaling: Opportunities and Challenges
Comprehensive analysis and optimization of CMOS LNA noise performance
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits
Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers
Synthesis of networks on chips for 3D systems on chips
Battery-aware mapping optimization of loop nests for CGRAs
Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be Made
Sensors for Remote Power Attacks: New Developments and Challenges
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
A Flexible ASIC-Oriented Design for a Full NTRU Accelerator
Crowdedness-balanced multilevel partitioning for uniform resource utilization
Circular-contour-based obstacle-aware macro placement
HyperRec: Efficient Recommender Systems with Hyperdimensional Computing
Towards scalable and secure execution platform for embedded systems
On test and repair of 3D random access memory
Code decomposition and recomposition for enhancing embedded software performance
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof
Monte-Carlo algorithms for layout density control
Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems
Representative frequency for interconnect R(f)L(f)C extraction
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits
Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation
Using link-level latency analysis for path selection for real-time communication on NoCs
DEPOGIT: dense power-ground interconnect architecture for physical design integrity
An introduction to OpenAccess: an open source data model and API for IC design
EPIC: Efficient prediction of IC manufacturing hotspots with a unified meta-classification formulation
DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost
Efficient synthesis of quantum circuits implementing clifford group operations
Fuzzy-based circuit partitioning in built-in current testing
Multi-clock SVA synthesis without re-writing
Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems
Hybrid Temporal Computing for Lower Power Hardware Accelerators
Resilient design in scaled CMOS for energy efficiency
ApproxMap: On task allocation and scheduling for resilient applications
Constraint extraction for pseudo-functional scan-based delay testing
On structure and suboptimality in placement
Efficient Key Switching Accelerator for Fully Homomorphic Encryption
Pairing of microring-based silicon photonic transceivers for tuning power optimization
Neural Network Pruning and Fast Training for DRL-based UAV Trajectory Planning
Finding optimal L1 cache configuration for embedded systems
Automatic process migration of datapath hard IP libraries
Constraint driven I/O planning and placement for chip-package co-design
CAD reference flow for 3D via-last integrated circuits
Nested Dissection Based Parallel Transient Power Grid Analysis on Public Cloud Virtual Machines
Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram
Workload capacity considering NBTI degradation in multi-core systems
Efficient embedded learning for IoT devices
Ultra-low power microcontrollers for portable, wearable, and implantable medical electronics
Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory
A hierarchical analysis methodology for chip-level power delivery with realizable model reduction
Micro-scale energy harvesting: a system design perspective
Comprehensive frequency dependent interconnect extraction and evaluation methodology
NBTI-aware power gating design
Nomadik®: A Mobile Multimedia Application Processor Platform
Hungarian algorithm based virtualization to maintain application timing similarity for defect-tolerant NoC
SPIN-PAC: test compaction for speed-independent circuits
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
A dual-output SC converter with dynamic power allocation for multicore application processors
Co-evaluation of FPGA architectures and the CAD system for telecommunication
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface
Fault-tolerant resynthesis with dual-output LUTs
High throughput hardware architecture for accurate semi-global matching
Optimizing intra-task voltage scheduling using data flow analysis
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection
On effective criterion of path selection for delay testing
Efficient early stage resonance estimation techniques for C4 package
A current-mode DC-DC converter using a quadratic slope compensation scheme
Advanced tools for simulation and design of oscillators/PLLs
A 200-MHz 4-phase fully integrated voltage regulator with local ground sensing dual loop ZDS hysteretic control using 6.5nH package bondwire inductors on 65nm bulk CMOS
Formal methods for coverage analysis of architectural power states in power-managed designs
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up
A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm
Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects
Extending Neural Processing Unit and Compiler for Advanced Binarized Neural Networks
23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands
A Generic FPGA Accelerator for Minimum Storage Regenerating Codes
Resource-constrained low-power bus encoding with crosstalk delay elimination
Evaluation of multiple-output logic functions using decision diagrams
A Robust FPGA Router with Concurrent Intra-CLB Rerouting
KAPLA: Scalable NN Accelerator Dataflow Design Space Structuring and Fast Exploring
Implementation of double arbiter PUF and its performance evaluation on FPGA
Checker-pattern and shared two pixels LOFIC CMOS image sensors
Design rule optimization of regular layout for leakage reduction in nanoscale design
MaizeRouter: Engineering an effective global router
A hardware/software partitioning algorithm for SIMD processor cores
Timing closure: the solution and its problems
Comparison of schemes for encoding unobservability in translation to SAT
A 128-way FPGA platform for the acceleration of KLMS algorithm
Search-free Accelerator for Sparse Convolutional Neural Networks
Current and charge estimation in CMOS circuits
Designing and optimizing compute kernels on NVIDIA GPUs
Annotation and analysis combined cache modeling for native simulation
Optimal placement by branch-and-price
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits
A novel LCD driver testing technique using logic test channels
Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory
Spectral approach to verifying non-linear arithmetic circuits
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs
Power minimization techniques on distributed real-time systems by global and local slack management
An overview of spin-based integrated circuits
Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic
Dead via minimization by simultaneous routing and redundant via insertion
New directions for learning-based IC design tools and methodologies
Fast Thermal Analysis for Chiplet Design based on Graph Convolution Networks
Design and evaluation of variable stages pipeline processor chip
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework
An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation
Symbolic debugging of globally optimized behavioral specifications
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units
Exploring Architectural Implications to Boost Performance for in-NVM B+-Tree
Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults
Buffering global interconnects in structured ASIC design
Emulator-oriented tiny processors for unreliable post-silicon devices: A case study
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation
Synthesis of quantum logic circuits
Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum Computers
An analog front-end IP for 13.56MHz RFID interrogators
A scorchingly fast FPGA-based Precise L1 LRU cache simulator
Low standby power CMOS delay flip-flop with data retention capability
Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
Improved crosstalk modeling for noise constrained interconnect optimization
H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications
CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors
Establishing Reachset Conformance for the Formal Analysis of Analog Circuits
A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits
Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning
On efficient message passing in energy harvesting based distributed system
A machine learning attack resistant multi-PUF design on FPGA
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis
A software solution for dynamic stack management on scratch pad memory
High-level architecture exploration for MPEG4 encoder with custom parameters
Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks
SLOGAN: SDC Probability Estimation Using Structured Graph Attention Network
Analytical minimization of half-perimeter wirelength