yusuke1997/dblp-id-title huggingface dataset:
A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application
15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power
A 0.55nW/0.5V 32kHz Crystal Oscillator Based on a DC-Only Sustaining Amplifier for IoT
A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX
Session 22 Overview: Terahertz for Communication and Sensing Wireless Subcommittee
25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm 2 Current Density
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology
A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting
A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications
15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX
A 512Gb 3-bit/Cell 3D 6 th -Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
A 38µm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent Reference
50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoring
Session 24 overview: Energy-aware digital design
A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology
Ultra-Thin Chips on Foil for Flexible Electronics
A 26dB-gain 100GHz Si/SiGe Cascaded Constructive-Wave Amplifier
2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine
A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS
A compact SAW-less multiband WCDMA/GPS receiver front-end with translational loop for input matching
A 9-band WCDMA/EDGE transceiver supporting HSPA evolution
A 20Gb/s NRZ/PAM-4 1V transmitter in 40nm CMOS driving a Si-photonic modulator in 0.13µm CMOS
A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction
A Biased-SECE Interface for Piezoelectric Energy Harvesting with Geometric-Mean-Computational MPPT Achieving 99.9% MPPT Efficiency, 8.75Cycles/ΔV OC Tracking, and 9.3x Energy Extraction
37.4 SHINSAI: A 586mm 2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver
A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security
A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS
A 32MHz Crystal Oscillator with Fast Start-up Using Synchronized Signal Injection
A 27-to-41GHz MIMO Receiver with N-Input-N-Output Using Scalable Cascadable Autonomous Array-Based High-Order Spatial Filters for Instinctual Full-FoV Multi-Blocker/Signal Management
A digitally controlled DC-DC converter for SoC in 28nm CMOS
A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator
34.1 A 65fsrms-Jitter and -272dB-FoMjitter, N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration
15.8 A permanent digital archive system based on 4F 2 x-point multi-layer metal nano-dot structure
An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS
On-chip image rejection in a low-if cmos receiver
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management
8.5 A 60%-efficiency 20nW-500µW tri-output fully integrated power management unit with environmental adaptation and load-proportional biasing for IoT systems
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits
Session 7 overview: Nonvolatile memory solutions
5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit
A 0.25mm 2 resistor-based temperature sensor with an inaccuracy of 0.12°C (3σ) from -55°C to 125°C and a resolution FOM of 32fJK 2
An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic Cells
CMOS phase-locked loops for frequency synthesis
A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHz
1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication
A chopper current-feedback instrumentation amplifier with a 1mHz 1/ƒ noise corner and an AC-coupled ripple-reduction loop
7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence
A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC
An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS
An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication
A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for Classic-Quantum Interface
9.5 A 1.2nJ/b 2.4GHz receiver with a sliding-IF phase-to-digital converter for wireless personal/body-area networks
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
A gamma, x-ray and high energy proton radiation-tolerant CIS for space applications
EE3: Quantum engineering: Hype, spin or reality?
11.6 A multi-channel neural-recording amplifier system with 90dB CMRR employing CMOS-inverter-based OTAs with CMFB through supply rails in 65nm CMOS
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput
A 36.3-to-38.2GHz -216dBc/Hz 2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter
13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40 th Mask Cost
13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry
Active circuits for ultra-high efficiency micropower generators using nickel-63 radioisotope
21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms Latency
A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS
SE7 Implantable and Prosthetic Devices: Life-Changing Circuits
9.2 A 400MHz Symbol-Power-Tracking (SPT) Supply Modulator with SPT-Adaptive-Biasing Network Supporting 5G FR2 CMOS PA
A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance
A 50Gb/s PAM-4 Bi-Directional Plastic Waveguide Link with Carrier Synchronization Using PI-Based Costas Loop
26.5 A 977μW Capacitive Touch Sensor with Noise-Immune Excitation Source and Direct Lock-In ADC Achieving 25.2pJ/step Energy Efficiency
3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS
Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dB
UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems
A 100Gbaud 4Vppd Distributed Linear Driver with Cross-Folded Transmission Lines and Cross-Coupled Gm Cells for Built-in 5-Tap FFE in 0.13µm SiGe BiCMOS
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range
13.4: Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6µV Precision and 4.1nV/Hz 0.5 Noise Co-Integrated with the Single Electron Transistor at 60mK
Session 15 overview: Data converter techniques
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis
Augmented Reality - The Next Frontier of Image Sensors and Compute Systems
9.5 efficient digital quadrature transmitter based on IQ cell sharing
20.8 A 20mW GSM/WCDMA receiver with RF channel selection
16.8 1GHz GaN-MMIC monolithically integrated MEMS-based oscillators
A 4.9Mpixel Programmable-Resolution Multi-Purpose CMOS Image Sensor for Computer Vision
A 21.8b sub-100μHz 1/f corner 2.4μV-offset programmable-gain read-out IC for bridge measurement systems
32.1 A 47GHz 4-way Doherty PA with 23.7dBm P1dB and 21.7% / 13.1% PAE at 6 / 12dB Back-off Supporting 2000MHz 5G NR 64-QAM OFDM
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency
A 1μW voice activity detector using analog feature extraction and digital deep neural network
33.4: A Wideband Bidirectional Calibration-Free Frequency/Switching-Staggering 360° D-Band Phase Shifter with Frequency-Invariant Codes Achieving lt; 2.38°/0.63dB RMS-Errors Over 24% Bandwidth
5.3 An Up-to-1400nm 500MHz Demodulated Time-of-Flight Image Sensor on a Ge-on-Si Platform
The Tall Thin Molecular Programmer
4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control
A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation
A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications
Session 4 overview: RF techniques: RF subcommittee
33.2 A 216-to-226GHz Watt-Level GaN Solid-State Power Amplifier with Multiband Large-Signal Impedance Correction and Circuit-Package Co-Design Technique
A 28GHz Low-Phase-Noise CMOS VCO Using an Amplitude-Redistribution Technique
A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mWPower and 2.5Mb/s Forward Data Delivery
4.1 22nm Next-generation IBM System z microprocessor
4.8 A 28nm x86 APU optimized for power and area efficiency
1.1 Semiconductor Industry: Present & Future
Nanoelectronics in retrospect, prospect and principle
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology
24.5 A 15b Quadrature Digital Power Amplifier with Transformer-Based Complex-Domain Power-Efficiency Enhancement
A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels
28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS
10-40 Gb/s I/O design for data communications
6.1 memory and system architecture for 400Gb/s networking and beyond
A leakage current replica keeper for dynamic circuits
A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network
A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor
5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM
A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET
A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications
17.4 CMOS impedance analyzer for nanosamples investigation operating up to 150MHz with Sub-aF resolution
A $4\times 4$ 607GHz Harmonic Injection-Locked Receiver Array Achieving $4.4\text{pW}/\surd\text{Hz}$ NEP in 28nm CMOS
A 189x600 Back-Illuminated Stacked SPAD Direct Time-of-Flight Depth Sensor for Automotive LiDAR Systems
A 0.92/5.3nJ/b UWB impulse radio SoC for communication and localization
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS
1.3 How chips pave the Road to the Higgs particle and the attoworld beyond
31.4 A 91.25% Peak Power-Conversion-Efficiency Capacitive Power-Management IC Supporting up to 5.68mJ Burst Energy Delivery Using a Single External Capacitor for mm-Scale IoT Applications
SciCNN: A 0-Shot-Retraining Patient-Independent Epilepsy-Tracking SoC
4.8 3-phase 6/1 switched-capacitor DC-DC boost converter providing 16V at 7mA and 70.3% efficiency in 1.1mm 3
Silicon 3D-integration technology and systems
Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial Links
A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification
A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array
A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy-Harvesting and Power-Management Platform with 1.2×10 5 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up
2.1 mm-Wave 5G Radios: Baseband to Waves
15.2 A 1024-Channel 0.00029mm 2 /ch 74nW/ch Online Spatial Spike-Sorting Chip with Event-Driven Spike Detection and Self-Organizing Map Clustering
A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$
26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience
15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS
9.2 A 134µW 24kHz-BW 103.5d8-DR CT ΔΣ Modulator with Chopped Negative-R and Tri-Level FIR DAC
An injection-locked ring PLL with self-aligned injection window
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits
A harmonic rejection mixer robust to RF device mismatches
A 40A Shunt-Based Current Sensor with ±0.2% Gain Error from -40°C to 125°C and Self-Calibration
7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET
3.8 A 0.65V 900µm² BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -25°C to 125°C
A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection
22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors
A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance
A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level
A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12
A 253mW/channel 4TX/4RX pulsed chirping phased-array radar TRX in 65nm CMOS for X-band synthetic-aperture radar imaging
IRIS: A 8.55mJ/frame Spatial Computing SoC for Interactable Rendering and Surface-Aware Modeling with 3D Gaussian Splatting
An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications
Session 6 overview: Emerging medical and sensor technologies technology directions subcommittee
A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor
31.8 A 11.7W 9mV/A-Cross-Regulation Single-Inductor Triple-Output Buck Converter Using Unordered Power-Distributive Control for a 2A Load Transient
SE4 Automotive Signal Processing Technologies
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS
Organic CMOS circuits for RFID applications
A 100mW 10MHz-BW CT ΔΣ Modulator with 87dB DR and 91dBc IMD
Analog Signal Processing with Organic FETs
9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS
A Reconfigurable Bidirectional 28/37/39GHz Front-End Supporting MIMO-TDD, Carrier Aggregation TDD and FDD/Full-Duplex with Self-Interference Cancellation in Digital and Fully Connected Hybrid Beamformers
A 240ps 64b carry-lookahead adder in 90nm CMOS
33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing
A 10MHz-Bandwidth 2mV-Ripple PA-Supply Regulator for CDMA Transmitters
A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback
A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression
5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology
A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction
A 23-to-29GHz Receiver with mm-Wave N-Input-N-Output Spatial Notch Filtering and Autonomous Notch-Steering Achieving 20-to-40dB mm-Wave Spatial Rejection and -14dBm In-Notch IP1 dB
5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWM
Cellular and wireless LAN transceivers: From systems to circuit design
Session 22 overview: Sensors & displays
2.4 A 0.028mm 2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS
5.4 A 32nW bandgap reference voltage operational from 0.5V supply for ultra-low power systems
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission
Session 5 overview: Analog techniques
23.8 A 34V charge pump in 65nm bulk CMOS technology
A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS
A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude
A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm 2 /Ch and $1.78\mu \text{W/ch}$
18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
24.6 A CMOS micro-flow cytometer for magnetic label detection and classification
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution
A double-loop control LED backlight driver IC for medium-sized LCDs
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method
Session 11 overview: Sensors and displays
A 256kb Sub-threshold SRAM in 65nm CMOS
12.3 A 240Hz-reporting-rate 143×81 mutual-capacitance touch-sensing analog front-end IC with 37dB SNR for 1mm-diameter stylus
An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications
28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction
An Organic Imager for Flexible Large Area Electronics
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10 -6 Native Bit Error Rate
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage
A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection
A 335Mb/s 3.9mm 2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems
F4: Scientific imaging
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5 th -Generation 10nm DRAM Process
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS
A robust wireless sensor node for in-tire-pressure monitoring
A CMOS-Control Rectifier for DiscontinuousConduction Mode Switching DC-DC Converters
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture
A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applications
A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS
A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit
An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGE
Session 13 overview: Energy-efficient RF systems: RF & wireless subcommittees
EE5: When will we stop driving our cars?
A 24GS/s 6b ADC in 90nm CMOS
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors
A Single-Inductor Dual-Band VCO in a 0.06mm 2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging
8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring
Continuing to shrink: Next-generation lithography - Progress and prospects