yusuke1997/dblp-id-title huggingface dataset:
A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications
A Meaningful Infinite-Valued Switching Function - Fuzzy Threshold Function and Its Application to Process Control
Simulation of Gate Circuits with Feedback in Multi-Valued Algebras
Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA
Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors
Centralizers of Monoids Containing the Symmetric Group
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions
Weight Structures for Approximate Reasoning with Weighted Expressions
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic
A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm
Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and Multipliers
On the Efficient Decoding of Reed-Solomon Codes Based on GMD Criterion
On the Partial Hyperclone Lattice
Rectangular Algebras
Upper and Lower Bounds on the Number of Disjunctive Forms
Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor
Uniform Description of Calculi for All t-Norm Logics
Computational Neurobiology Meets Semiconductor Engineering
Representing the Genetic Code as a Function on a Galois Field Using the Reed-Muller Expansion
Multiple-Valued Logic Minimization by Genetic Algorithms
Complexity of Many-Valued Logics
A Framework for the Design and Realization of Alternative Superconducting Quantum Architectures
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions
Chrestenson Spectrum Computation Using Cayley Color Graphs
Some Properties of Generalized State Operators on Residuated Lattices
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI
CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits
Higher-Order Boolean Masking Does Not Prevent Side-Channel Attacks on LWE/LWR-based PKE/KEMs
Design of a Multiple-Valued VLSI Processor for Digital Control
Multiple-Valued Logic Design Tools
Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems
Fault Tolerant CMOS Logic Using Ternary Gates
Some Results on the Centralizers of Monoids in Clone Theory
Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding
Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit
The Automorphism Group of Finite Godel Algebras
A Study of the Haar Spectra of Ternary Bent Functions
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters
Proposed CMOS VLSI Implementation of an Electronic Neuron Using Multivalued Signal Processing
On Constructing Secure and Hardware-Efficient Invertible Mappings
Linear Reversible Circuit Synthesis in the Linear Nearest-Neighbor Model
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation
Cut Elimination and Normalization in Intermediate Connexive Logics
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels
Mixed Discrete Optimization of Multiple-Valued Systems
Data Mining of Weak Functional Decompositions
Mining Multi Human Locations Using Thermopile Array Sensors
On the Size of Multiple-Valued Decision Diagrams
Multiple-Valued Logic Design Using Multiple-Valued EXOR
An Algebra for Current-Mode CMOS Multivalued Circuits
An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations
Complex Spectral Decision Diagrams
Neural Networks: Binary Monotonic and Multiple-Valued
Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme
On the Implementation of Set-Valued Non-Boolean Switching Functions
Revisiting Ultraproducts in Fuzzy Predicate Logics
Minimization of Multivalued Multithreshold Perceptrons using Genetic Algorithms
An Algebraic Method to Decide the Deduction Problem in Many-Valued Propositional Calculus
Binary Input/Ternary Output Switching Circuits Designed Via the Sign Transformation
An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy Inference
Structures with Many-Valued Information and Their Relational Proof Theory
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link
The Inclusion Structure of Boolean Weak Bases
A New Approach to Machine Learning Based on Functional Decomposition of Multi -Valued Functions
Model-Characterizing Formulas and Normal Forms in Godel Logics
Fuzzy Rule Extraction from Nursing-Care Texts
Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum
A Proposal of Fault-Checking Fuzzy Control
Symmetric Paraconsistent Quantum Logic
On the Concept of Qualitative Fuzzy Set
Generation of Ternary Bent Functions by Spectral Invariant Operations in the Generalized Reed-Muller Domain
Behavior Expressions for Social and Entertainment Robots
Mining Approximative Descriptions of Sets Using Rough Sets
A Consideration on Ternary Adversarial Generative Networks
Many Valued Paraconsistent Logic
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices
Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations
Testability Analysis of CMOS Temary Circuits
An FPGA Implementation of 4×4 Arbiter PUF
Information-Theoretical Mining of Determining Sets for Partially Defined Functions
A Table Look-Up Based Ternary Neural Network Processor
Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions
Capacity Limits of Fully Binary CNN
A Fast Algorithm for the Disjunctive Decomposition of m -Valued Functions Part II: Time Complexity Analysis
Non-binary Successive Approximation Analog-to-Digital Converters: A Survey
Quaternary Multiplier Circuit
Reversible Circuit Optimization Based on Tabu Search
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
On Periodic Patterns and their Spectra
Wearable Human Activity Recognition by Electrocardiograph and Accelerometer
Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous Two-Layered Neural Network
What Is Many-Valued Logic?
Commodious Axiomatization of Quantifiers in Multiple-Valued Logic
Time-Domain Multi-bit DeltaSigma Analog-to-Digital Converter
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation
Commuting Hyperoperations
Polynomially Closed Co-clones
An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition
Representation Theorems and Theorem Proving in Non-Classical Logics
Galois Connection for Hyperclones
Mining Latency Guarantees for RTL Designs
Step-Wise Synthesis of CCD MVL Functions
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits
A Qualitative Modal Representation of Quantum Register Transformations
Enumeration of Function and Bases of Three-Valued Set Logic under compositions with Boolean Functions
Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups
A Mature Methodology for Implementing Multi-Valued Logic in Silicon
Low Voltage Semi Floating-Gate Binary to Multiple-Value and Multiple-Value to Binary Converters
50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020, Miyazaki, Japan, November 9-11, 2020
Analysis and Improvement of Transformation-Based Reversible Logic Synthesis
Using Hasse Diagrams to Synthesize Ternary Quantum Circuits
A Survey on Intersections of Maximal Partial Clones of Boolean Partial Functions
Efficient PAM-4 Data Transmission with Closed Eye Using Symbol Distribution Estimation
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders
Secure Key Storage Using State Machines
Relevance implication and orthomodular posets
Delta-Sigma Domain Signal Processing: A Review with Relevant Topics in Stochastic Computing
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit
Extending Ideal Paraconsistent Four-Valued Logic
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI
Generating Sets for Clones and Partial Clones
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions
Minimal Partial Hyperclones on a Two-Element Set
Automatic Teeth Recognition in Dental X-Ray Images Using Transfer Learning Based Faster R-CNN
Iterative realization of multivalued logic systems
Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age
46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016, Sapporo, Japan, May 18-20, 2016
Some Results on the Decision and Construction for Sheffer Functions in Partial K-Valued Logic
A two-valued semantics for infectious logics
Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
On a Graded Notion of t-Norm and Dominance
Set Representation of Partial Dynamic De Morgan Algebras
Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results
Enhanced Simulated Bifurcation for MIMO Detection
Polynomial-Time Algorithms for Verification of Some Properties of k-Valued Functions Represented by Polynomials
A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks
Classes of Operations Closed under Permutation, Cylindrification and Composition
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format
Reconstruction of Additive Generators from Partial Derivatives of Continuous Archimedean t-Norms
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy
Relations between Clones and Full Monoids
Signed Formulas and Annotated Logics
Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems
Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter Applications
Multiple-Valued Problem Solvers - Comparison of Several Approaches
On Detection of Stenosis-Type Sections in Fallopian Tubal Models Using Support Vector Machines
Dynamic Current-Mode Multi-Valued MOS Memory with Error Correction
Galois Theory for Partial Clones and Some Relational Clones
Functional-Device-Based VLSI for Intelligent Electronic Systems
Decomposition-Based Representation of Symmetric Multiple-Valued Functions
On the Complexity of Classification Functions
CNOT Gate Mappings to Clifford+T Circuits in IBM Architectures
Functions of multiple-valued logic and the complexity of constraint satisfaction: A short survey
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions
Minimal Resolution Proof Systems for Finitely-Valued Lukasiewicz Logics
Soft Computing Methods for Prediction of Replication Origins in Caudoviruses
A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach
Completions in Subvarieties of BL-Algebras
Ternary Logic Network Justification Using Transfer Matrices
Soft Computing Perspective
On Yager's Aggregation Operators
Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits
On the Number of S-Threshold Functions on Not Necessarily Binary Input
48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, Linz, Austria, May 16-18, 2018
A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions
Novel Instrumentation Amplifier Architectures Insensitive to Resistor Mismatches and Offset Voltage for Biological Signal Processing
Study of GPU Acceleration in Genetic Algorithms for Quantum Circuit Synthesis
Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI
Gibbs Characterization of Binary and Ternary Bent Functions
Hereditarily Rigid Relations: Dedicated to Professor I.G. Rosenberg on the Occasion of His 80-th Birthday
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications
On Some Classes of Fuzzy Information Relations
Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction
Synthesis of Multi-valued Literal Using Lukasiewicz Logic
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions
On the Axiomatization of Generalized Entropic Metrics
T-depth Optimization for Fault-Tolerant Quantum Circuits
A Novel Weighted Hierarchical Adaptive Voting Ensemble Machine Learning Method for Breast Cancer Detection
Permutations under Spectral Transforms
Elucidation of Brain Activities by Electroencephalograms and Its Application to Brain Computer Interface
Characterization of the Axiomatizable Prenex Fragments of First-Order Gödel Logics
Generating Synthetic MVL Benchmarks from Random MDDs Under Restrictions
Clarifying the Systems of Axioms Based on the Method of Indeterminate Coefficients
Characteristic Vectors of Reversible Boolean Functions with Threshold Components
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Fault Diagnosis System Based on Sensitivity Analysis and Fuzzy Logic
A delta-sigma-modulator feedforward network for a non-binary analog-to-digital converter
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices
Error-Correcting Decision Diagrams for Multiple-Valued Functions
Mosaics, Fermat, Walsh (Aller guten Dinge sind drei)
B-ternary Logic Based Asynchronous Micropipeline
On the Number of Fixed Points of the Reed-Muller-Fourier Transform
Belief Network Support via Decision Diagrams
VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products
Ternary/MV Reversible Functions with Component Functions from Different Equivalence Classes
An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the p-Valued Logical Networks
The Alleged Limitations of Fuzzy Control
Posets of Minors of Functions in Multiple-Valued Logic
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications
Fast Transforms for Multiple-Valued Input Binary Output PLI Logic
Inference in Fuzzy Logic via Generalized Constraint Propagation
Error Bounded Exact BDD Minimization in Approximate Computing
Spectral Transformation of Multiple-Valued Decision Diagrams
Synthesis Techniques for Ternary Quantum Logic
Ternary Logic by 3rd Subharmonics and its Application to Multiway Switches
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic
Evaluation of Inconsistency in a 2-Way Fuzzy Adaptive System Using Shadowed Sets
Ternary Toffoli-type Reversible Gates: Control Alternatives and Quantum Models
An Equational Logic Approach for Mapping Multiple-Valued Rule-Based Expert Systems into Hardware Specification Rules
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis
Applying Rough Sets to Information Tables Containing Missing Values
Optimizing the Defuzzifier Timing for the Fuzzy Control of a Servodrive
Reasoning in Inconsistent Stratified Knowledge Bases
Entanglement in Higher-Radix Quantum Systems
On the Combinatorics of Tolerance Relations
Comparison Look-Ahead and Design of Fast Fuzzy Operation Units
Interband-Tunneling III-V Semiconductor Structures for Multiple-Valued Literal and Arithmetic Functions
Free Three-valued Lukasiewicz, Post and Moisil Algebras over a Poset
An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs
Assumption based multi-valued semantics for extended logic programs
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells
Enzyme Transistor Circuits for Biomolecular Computing
On Neural-Network-Based Detection for Hypertensive Subjects Using Classification of Retinal Fundus Photographs
Comparison of Influence of Two Data-Encoding Methods for Grover Algorithm on Quantum Costs
Polynomial Ring Calculus for Many-Valued Logics
41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011, Tuusula, Finland, May 23-25, 2011
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams
Falsification-aware Semantics for Description Logics
Partial R-Clones
Paradigms for Many-sorted Non-classical Substitutions
Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices
Functional Decision Diagrams for Multiple-Valued Functions
e-Bases of Triadic Logic Operations
An Improved Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems
Switching Activity in Stochastic Decoders
Towards the Realization of 4-Valued CMOS Circuits
Approximate Ternary Quantum Error Correcting Code with Low Circuit Cost
Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups
On the Construction of Multiple-Valued Decision Diagrams
Evaluation of Static Variable Ordering Heuristics for MDD Construction
Sequential Fuzzy Description Logic: Reasoning for Fuzzy Knowledge Bases with Sequential Information
Test Pattern Generation for Combinatorial Multi-Valued Networks Based on Generalized D-Algorithm
The Generation Circulation Method to Generalized Reed-Muller Coefficients over GF(3)
Multi-valued Modal Fixed Point Logics for Model Checking
Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions
Prime Filters on Residuated Lattices
A Ternary Fuzzy Extractor for Efficient Cryptographic Key Generation
Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits
A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors
Study of Reversible Ternary Functions with Homogeneous Component Functions
Impact of Interconnection-Free Biomolecular Computing
Finding Composition Trees for Multiple-Valued Functions
Research on the Similarity among Precomplete Sets Preserving m-ary Relations in Partial K-Valued Logic
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
Keynote III: Boolean Logic Networks for Machine Learning
Index Generation Functions: Recent Developments
The Tensor PMV-algebra of an MV-algebra
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams
On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras
Remarks on Similarities Among Ternary Bent Functions
Strength of the Rule of Inference
A Note on Triangulation of PostAlgebras and "Leibnizian" Lattices
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space
Two typical representation theorems for symmetrical Heyting algebras of order n
A Synthesis Flow for Sequential Reversible Circuits
Discovering Emerging Applications of Multi-Valued Logic: Protocols for Human-Autonomy Teaming
Noise-Tolerant Model of a Ternary Inverter Based on Markov Random Field
Quantum Logic Implementation of Unary Arithmetic Operations
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams
Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators
Improved Complexity of Quantum Oracles for Ternary Grover Algorithm for Graph Coloring
Multiple-Valued Logic Physically Unclonable Function in Photonic Integrated Circuits
A Design of Multiple-Valued Logic Neuron
Uniform Notation of Tableau Rules for Multiple-Valued Logics
Efficient Hardware Realization of Convolutional Neural Networks Using Intra-Kernel Regular Pruning
On Distinguishing Sequences of Several Classes of Reversible Finite State Machines
A Design of 10-GHz Delta-Sigma Modulator using a 4-Level Differential Resonant-Tunneling Quantizer
2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices
Properties of the Zhang-Watari Transform
Computing Uniform Interpolants in Nilpotent Minimum Logic
Relationship between UCHT and FFT
Attribute Reduction as Calculation of Focus in Granular Reasoning
An Ontology Mediated Multimedia Information Retrieval System
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits
Approaching the Physical Limits of Computing
Notes on the Exclusive Disjunction
Binary, Multi-Valued and Quantum Board and Computer Games to Teach Synthesis of Classical and Quantum Logic Circuits
A Survey on the Arity Gap
Message from the Symposium Chair
Finding Hard Instances of Satisfiability in Lukasiewicz Logics
Design of Multivalued Circuits using Genetic Algorithms
Towards Solving Many-Valued MaxSAT
Consequence and Complexity in Infinite-Valued Logic: A Survey
Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices
Family of Fast Transforms over GF(3) Logic
A multi-level cascaded delta-sigma modulator with reduced quantization noise leakage
Undecidability in the Completion of Truth-Function Logic
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model
Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output
Non-deterministic Multi-valued Logics--A Tutorial
On Multiple-Valued Logic Functions Monotonic with Respect to Ambiguity
On Key Relations Preserved by a Weak Near-Unanimity Function
2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019
Fault-Recovery and Intelligent Distributed System
Automated generation of models and counterexamples and its application to open questions in Ternary Boolean algebra
Hyperclones Determined by Total-Parts of Hyper-relations
Integrator-Chain Multiplier
Recognition of Blurred Images Using Multilayer Neural Network Based on Multi-valued Neurons
Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit
Hierarchies of Local Monotonicities and Lattice Derivatives for Boolean and Pseudo-Boolean Functions
IEEE 44th International Symposium on Multiple-Valued Logic, ISMVL 2014, Bremen, Germany, May 19-21, 2014
Fast Synthesis for Ternary Reed-Muller Expansion
Reducing T-count When Decomposing Many MPMCT Gates Simultaneously
On a Realization of Multi-terminal Universal Interconnection Networks using Contact Switches
Hypersequents as a Uniform Framework for Urquhart's C, MTL and Related Logics
Multiple-Valued Logic as a Programming Language
On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation
Visualization of the Waveform Shaping Effect of Higher-order FFEs Using Multi-Valued Symbol Mapping
A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors
An Efficient Multi-Level Multi-Wire Differential Interface
Honouring Ivo G. Rosenberg: His Contributions to ISMVL
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic