yusuke1997/dblp-id-title huggingface dataset:
Dynamic error tracking and supply voltage adjustment for low power
A low-power, radiation-hardened Single Event Effect rate detection System on a Chip for Real Time Monitoring of Single Event Effects on Low Earth Orbit satellites
Novel input coding technique for high-precision LUT-based multiplication for DSP applications
Optimized Quantum Circuit Implementation of Payoff Function
A 45° compaction algorithm handling overconstraints
Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing
Dynamic voltage scaling for SEU-tolerance in low-power memories
Basic Block Encoding Based Run-time CFI Check for Embedded Software
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers
Time Efficient Dual-Field Unit for Cryptography-Related Processing
Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits
Impact of task migration in NoC-based MPSoCs for soft real-time applications
Fabrication of a flexible neural interface device with CMOS-based smart electrodes
Hardware Algorithms for VLSI Systems
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets
An HDTV H.264 deblocking filter in FPGA with RGB video output
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors
Physical design and mask optimization for directed self-assembly lithography (DSAL)
abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory
An Instruction Set Architecture for Low-power, Dynamic IoT Communication
A Wideband High-Gain Power Amplifier Operating in the D Band
Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital Converters
Library Compatible Variational Delay Computation
A 18-27 GHz Programmable Gain Amplifier in 65-nm CMOS technology
Prefetch-based dynamic row buffer management for LPDDR2-NVM devices
Embedded low power analog CMOS Fuzzy Logic Controller chip for industrial applications
A Two-Layer Connected Component Algorithm for Target Extraction Using K-means and Morphology
Design Co-Processor Based on Partially Homomorphic Encryption Execution Using Open-Source Tool
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates
DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities
A multilayer channel router based on optimal multilayer net assignment
Analysis and Design Strategy of On-Chip Charge Pumps for Micro-power Energy Harvesting Applications
Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications
Routability-Driven Detailed Placement Using Reinforcement Learning
Noise modeling using look-up tables and DC measurements for cryogenic applications
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs
Gate sizing in the presence of gate switching activity and input vector control
Embedded MRAM for high-speed computing
SEARS: A Statistical Error and Redundancy Analysis Simulator
Design and Optimization of Multiple-Mesh Clock Network
A Compressed Page Management Scheme for NAND-Type Flash Memory
Foundation of Quantum Capacity
GPFP: A SIMD PE for Higher VLSI Densities
EXOR Projected Sum of Products
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR
A compact, ultra-low power AES-CCM IP core for wireless body area networks
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis
Designing and Testing High Dependable Memories for Aerospace Applications
Speeding up safety verification by fault abstraction and simulation to transaction level
Step response analysis of third order OpAmps With slew-rate
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits
Automatically comparing analog behavior using Earth Mover's Distance
SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures
Pseudo Floating-Gate Inverter with Feedback Control
A 13.56 MHz Active Rectifier with PMOS AC-DC Interface for Wireless Powered Medical Implants
Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC
IP-core protection for a non-volatile Self-reconfiguring SoC environment
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy
An adaptive genetic algorithm for dynamically reconfigurable modules allocation
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness
Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices
New scan-based attack using only the test mode
Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems
Partition-Based Faults Diagnosis of a VLIW Processor
Bi-Directional Time Domain Duplexing (TDD) Amplifier for 5G Applications
Evaluation of fault tolerant technique based on homogeneous FPGA architecture
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing
On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms
KAVUAKA: A Low Power Application Specific Hearing Aid Processor
Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip
Power-aware partitioning of data converters
Low noise front-end amplifier design for medical ultrasound imaging applications
An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates
CAT platform for analogue and mixed-signal test evaluation and optimization
An optimal operating point by using error monitoring circuits with an error-resilient technique
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge
Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations
Low power on-chip thermal sensors based on wires
Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect
Locality-aware vertex scheduling for GPU-based graph computation
Architectural Support for Functional Programming
The implementation of a MCM associative string processor
A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection
Co-synthesis of custom on-chip bus and memory for MPSoC architectures
A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power Applications
Top-down VLSI Design Experiments on a Picture Database Computer
Study of a BIST Technique for CMOS Active Pixel Sensors
From Assertion-Based Verification to Assertion-Based Synthesis
Probabilistic Models for Off-Line Arbiters in Embedded Systems
OSHDA: A Containerized CAD Tool for the Design and Analysis of Behavioral FSM Logic Locking
A 1mm 2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS
Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm
Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices
Toward Large Scale All-Optical Spiking Neural Networks
Generating fast logic circuits for m-select n-port Round Robin Arbitration
An inverter-based neural amplifier for neural spike detection
Exploring Approximate Computing Approaches to Design Power-efficient Multipliers
Speculative guardband: exploiting critical-delay variations across cached instructions
Emerging Technologies and Nanoscale Computing Fabrics
Post-Quantum, Order-Preserving Encryption for the Confidential Inference in Decision Trees: FPGA Design and Implementation
A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs
Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical Neuromodulation
Prospects of 3D inductors on through silicon vias processes for 3D ICs
Switching Windows Computation in Presence of Crosstalk Noise
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector
Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design
Real-Time Biologically-Inspired Image Exposure Correction
Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications
Oversampled Time Estimation Techniques for Precision Photonic Detectors
VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA
Breaking ACORN at Bitstream Level
Behavioral Simulation of Relative Timed Asynchronous Circuits
High Performance SoC Design Using Magnetic Logic and Memory
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation
Automated Logic Synthesis
Design of a Highly Pipelined 2nd Order IIR Filter Chip
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation
A Customizable Neural Processor for Distributed Neural Network
Pushing the Limits Further: Sub-Atomic AES
Arithmetic encoding for memristive multi-bit storage
Lower Bounds for Query Complexity of Some Graph Problems
Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder
A VLSI architecture for real-time gradient guided image filtering
Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators
Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework: Dataset optimization Techniques for Anomaly Detection
WCET overapproximation for software in the context of a Cyber-Physical System
Symbolic Model Checking with Partitioned Transistion Relations
Estimating lower hardware bounds in high-level synthesis
Optimizing SOC Test Resources Using Dual Sequences
A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC
Benchmarking Microfluidic Design Automation Flows
Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis
Pareto Points in SRAM Design Using the Sleepy Stack Approach
A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm
Automatic addition of reset in asynchronous sequential control circuits
31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023
Earth Mover's Distance as a Comparison Metric for Analog Behavior
On the accuracy of Monte Carlo yield estimators
SoCGuard: A runtime verification solution for the functional correctness of SoCs
A VLSI Module for Analog Adaptive Neural Architectures
A 230mV 8-bit sub-threshold microprocessor for wireless sensor network
Hardware Design Using CASE Tools
Decimal engine for energy-efficient multicore processors
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework
An Efficient Light-weight Configurable Approximate Adder Design
An Incremental Timing-Driven flow using quadratic formulation for detailed placement
Interface model based cyber-physical energy system design for smart grid
FeFET versus DRAM based PIM Architectures: A Comparative Study
APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models
PhD forum: Heterogeneous interconnection of ICs using stitch-chips
Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity
Software-Based Self-Test for Delay Faults
On the Reliability of RRAM-Based Neural Networks
FortBoot: Fortifying Rooted-in-Device-Specific Security Through Secure Booting
Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations
Interval arithmetic based input vector control for RTL subthreshold leakage minimization
On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields
Laser-induced fault effects in security-dedicated circuits
The Design and Implementation of a 2048-Bit RSA Encryption/Decryption Chip
Reducing ATE Cost in System-on-Chip Test
Minimum Depth Quantum Modular Addition Through Carry-Save Architecture
Towards sustainable exascale computing
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis
Wide-band piezoresistive aero-acoustic microphone
SWORD: A SAT like Prover Using Word Level Information
Electromigration Analysis of VLSI Circuits Using the Finite Element Method
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI
Soft error effects analysis and mitigation in VLIW safety-critical applications
Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation
Design and implementation of MPSoC single chip with butterfly network
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction
A Self-referenced and regulated sensing solution for PCM with OTS selector
Optimizing SOC Test Resources using Dual Sequences
Circuit simulation for large interconnected IC networks
3D-IC floorplanning: Applying meta-optimization to improve performance
A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier
Integration of Formal Methods with System Design
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs
An improved RNS generator 2 n +/- k based on threshold logic
18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications
IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006
Implementation-Independent Functional Test Generation for MSC Microprocessors
A Steep Slope Sub-10nm Armchair Phosphorene Nanoribbon FET with Intrinsic Cold Contact
VLSI 93, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Grenoble, France, 7-10 September, 1993
A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing
Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging
Improved Test Solutions for COTS-Based Systems in Space Applications
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor
In Hardware We Trust? From TPM to Enclave Computing on RISC-V
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies
Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study
New tool support and architectures in adaptive reconfigurable computing
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops
On the optimized generation of Software-Based Self-Test programs for VLIW processors
Stuck-At-Fault Testability of SPP Three-Level Logic Forms
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays
Virtual prototype based on Aldebarn CPU core
Soft Error Resilient System Design through Error Correction
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip
Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor
A high performance band-pass DAC architecture and design targeting a low voltage silicon process
FPGA-Implementation Techniques to Efficiently Test Application Readiness of Mixed-Signal Products
Dual-mode double precision / two-parallel single precision floating point multiplier architecture
VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Sharjah, United Arab Emirates, October 16-18, 2023, Revised Extended Selected Papers
A family of module generators for the layout synthesis of I/O buffers
5G-and-Beyond Scalable Machines
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study
State space optimization within the DEVS model of computation for timing efficiency
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation
A clock-less transceiver for global interconnect
Logic design with unipolar memristors
Confidential Inference in Decision Trees: FPGA Design and Implementation
Integrating Simulink, OpenVX, and ROS for Model-Based Design of Embedded Vision Applications
Hardware Trojans in Reconfigurable Computing
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor
The Connection Layout in a Lattice of Four-Terminal Switches
A novel soft error tolerant FPGA architecture
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines
2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits
RAT: A Lightweight System-level Soft Error Mitigation Technique
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
Pushing the limits further: Sub-atomic AES
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms
GMS: Generic memristive structure for non-volatile FPGAs
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic
GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN Inference
Dynamic clock synchronization scheme between voltage domains in multi-core architecture
Designing Application Specific Networks-On-Chip: Five easy pieces
An automatic framework for dynamic data structures optimization in C
Computing and design for software and silicon manufacturing
3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect
Force-Directed List Scheduling for Digital Microfluidic Biochips
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications
A wearable neuro-degenerative diseases detection system based on gait dynamics
Test data compression and TAM design
Architecture exploration of 3D FPGA to minimize internal layer connection
Issues in Model Reduction of Power Grids
Compression-based SoC Test Infrastructures
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans
Low-Power High-CMRR CMOS Instrumentation Amplifier for Biomedical Applications
Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cycles
Multithreaded parallel VLSI Leaf Cell Generator Using Agents 2
Exact Redundant State Registers Removal Based on Binary Decision Diagrams
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS
Two-levels of adaptive buffer for virtual channel router in NoCs
A Predictable Communication Scheme for Embedded Multiprocessor Systems
3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis
Testability of Switching Lattices in the Stuck at Fault Model
Designs for improving the performance of an electro-thermal in-plane actuator
Compensating the Load Effect in Quadrature All-Pass Filters
Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model
Multiplierless Design of Linear DSP Transforms
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors
Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput
Parametric Equivalent Circuit Extraction for VLSI Structures
AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN
Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling
Thermal-aware test scheduling for NOC-based 3D integrated circuits
2017 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017
A graph-based approach for mobile localization exploiting real and virtual landmarks
A Fully Integrated Systolic Spelling Co-Processor
Post-silicon failing-test generation through evolutionary computation
A Traffic Injection Methodology with Support for System-Level Synchronization
Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling
Advances on the state of the art in QDI design
Trinocular disparity processor using a hierarchic classification structure
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow
Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation
Generation of Formal CPU Profiles for Embedded Systems
Control Electronics Integration toward Endoscopic Capsule Robot Performing Legged Locomotion and Illumination
SanaSolo 2.0: Edge-Based Monitoring and Management of Soil Fertility Using IoT
FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context
Domain-Specific Architecture for IMU Array Data Fusion
Meta-model Based Automation of Properties for Pre-Silicon Verification
Channel Routing with Crosstalk Consideration
Aspect-Oriented Design Automation with Model Transformation
Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems
ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections
A Network for Parallel Searching
Architecture and design of a programmable 3D-integrated cellular processor array for image processing
An area-efficient minimum-time FFT schedule using single-ported memory
Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions
Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator
Capture the Pulse: Impact of FPGA Resource Utilization on EM Fault Injection Attacks Detection
High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks
Transmission Channel Noise Aware Energy Effective LDPC Decoding
Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices
Supporting circuitry for a fully integrated micro electro mechanical (MEMS) oscillator in 45 nm CMOS technology
Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures
Design of a Fully Parallel Viterbi Decoder
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space