yusuke1997/dblp-id-title huggingface dataset:
Race Logic: A hardware acceleration for dynamic programming algorithms
The Mozart reuse exposed dataflow processor for AI and beyond: industrial product
A recursive computer architecture for VLSI
Using SMT to accelerate nested virtualization
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Branch regulation: Low-overhead protection from code reuse attacks
Architecting to achieve a billion requests per second throughput on a single key-value store server platform
FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion
Advantages of Structured Hardware
Architecture of a VLSI Instruction Cache for a RISC
Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation
DISE: A Programmable Macro Engine for Customizing Applications
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs
Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches
LAORAM: A Look Ahead ORAM Architecture for Training Large Embedding Tables
MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization
The TLB Slice - A Low-Cost High-Speed Address Translation Mechanism
Architecting Efficient Multi-modal AIoT Systems
Performance Analysis of Circuit Switching Baseline Interconnection Networks
Scan Line Array Processors for Image Computation
GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent
η-LSTM: Co-Designing Highly-Efficient Large LSTM Training via Exploiting Memory-Saving and Architectural Design Opportunities
Optimizing Memory System Performance for Communication in Parallel Computers
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture
Online Estimation of Architectural Vulnerability Factor for Soft Errors
Phi: Leveraging Pattern-based Hierarchical Sparsity for High-Efficiency Spiking Neural Networks
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference
What Kinds of Applications Can Benefit from Transactional Memory?
Retrospective: An Instruction Timing Model of CPU Performance
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations
Methods for Handling Structures in Data-Flow Systems
Crosshatch Disk Array for Improved Reliability and Performance
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors
NVOverlay: Enabling Efficient and Scalable High-Frequency Snapshotting to NVM
Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers
AC-DIMM: associative computing with STT-MRAM
SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers
The Impact of Performance Asymmetry in Emerging Multicore Architectures
BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs
The Microprogramming of Pipelined Processors
The XOR Cache: A Catalyst for Compression
Threaded Multiple Path Execution
Hardware overhead analysis of programmability in ARX crypto processing
Don't Use the Page Number, But a Pointer To It
Computer Display of Colored Three-Dimensional Objects
Scaling Datacenter Accelerators with Compute-Reuse Architectures
Jericho: A Professional's Personal Computer System
LightNobel: Improving Sequence Length Limitation in Protein Structure Prediction Model via Adaptive Activation Quantization
Multiprocessor Cache Design Considerations
35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product
Using Scan Side Channel for Detecting IP Theft
Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms
The Importance of Being Square
A Cost-Effective Entangling Prefetcher for Instructions
A Hierarchical, Restructurable Multi-Microprocessor Architecture
K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks
Trade-offs Between Devices and Paths in Achieving Disk Interleaving
Morphable memory system: a robust architecture for exploiting multi-level phase change memories
Retrospective: A Processor for a High-Performance Personal Computer
Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference
Programmable Olfactory Computing
RAID-II: A High-Bandwidth Network File Server
A Modular Memory Scheme for Array Processing
The Maya Cache: A Storage-efficient and Secure Fully-associative Last-level Cache
A dual processor VAX 11/780
A simple method for extracting models for protocol code
A Bus Authentication and Anti-Probing Architecture Extending Hardware Trusted Computing Base Off CPU Chips and Beyond
On the Validity of Trace-Driven Simulation for Multiprocessors
The NYU Ultracomputer - Designing a MIMD, Shared-Memory Parallel Machine
Data Buffer Performance for Sequential Prolog Architectures
High-Speed Buffering for Variable Length Operands
Vector instruction set support for conditional operations
Dynamically allocating processor resources between nearby and distant ILP
Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997
Accelerating distributed reinforcement learning with in-switch computing
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip
Computer Architecture - ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers
Directory-based cache coherency protocol for a ring-connected multiprocessor-array
ASIC Clouds: Specializing the Datacenter
Array Processor with Multiple Broadcasting
A Modular Systolic Architecture for Image Convolutions
A Hardware Pipeline Algorithm for Relational Database Operation and Its Implementation Using Dedicated Hardware
DIMMining: pruning-efficient and parallel graph mining on near-memory-computing
Necromancer: enhancing system throughput by animating dead cores
Performance Optimization of Pipelined Primary Caches
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems
Performance of an OLTP Application on Symmetry Multiprocessor System
A Multi-Neural Network Acceleration Architecture
Performance Measurement of Paging Behavior in Multiprogramming Systems
Computer performance microscopy with Shim
Analyzing Multiple Register Sets
Deadlock Avoidance for Systolic Communication
A Novel Cache Design for Vector Processing
An Efficient Routing Control Unit for the SIGMA Network E(4)
Tradeoffs in Two-Level On-Chip Caching
Memory Model = Instruction Reordering + Store Atomicity
Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module
PS-ORAM: efficient crash consistency support for oblivious RAM on NVM
DHTM: Durable Hardware Transactional Memory
Chaos Router: Architecture and Performance
Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017
Power and energy reduction via pipeline balancing
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks
Achieving Out-of-Order Performance with Almost In-Order Complexity
The Design and Analysis of a Cache Architecture for Texture Mapping
Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses
Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU
SpecTLB: a mechanism for speculative address translation
Fetch-Criticality Reduction through Control Independence
Heracles: improving resource efficiency at scale
HA2lloc: Hardware-Assisted Secure Allocator
Accurate Indirect Branch Prediction
Experimenting With EPILOG: Some Results and Preliminary Conclusions
Implications of hierarchical N-body methods for multiprocessor architecture
Alternate Path Fetch
RETCON: transactional repair without replay
Fast Execution of Loops With IF Statements
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
Focusing processor policies via critical-path prediction
Unidirectional Error Correction/Detection for VLSI Memory
Piranha: a scalable architecture based on single-chip multiprocessing
A Comparison of Architectural Support for Messaging in the TMC CM-5 and the Cray T3D
Recency-based TLB preloading
Dead-block prediction & dead-block correlating prefetchers
The Transputer
Adaptive Cache Compression for High-Performance Processors
Temperature-constrained power control for chip multiprocessors with online model estimation
A Communication Structure for a Multiprocessor Computer with Distributed Global Memory
MagiCache: A Virtual In-Cache Computing Engine
A Model of Interference in a Shared Resource Multiprocessor
ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories
Retrospective: Implementing Precise Interrupts in Pipelined Processors
BlockChop: Dynamic squash elimination for hybrid processor architecture
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture
Setting an error detection infrastructure with low cost acoustic wave detectors
Architectural Supports to Protect OS Kernels from Code-Injection Attacks
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
Measuring VAX 8800 Performance with a Histogram Hardware Monitor
ML computation patterns in production systems
An Educational Laboratory in Contemporary Digital Design
Correlated Load-Address Predictors
GraFBoost: Using Accelerated Flash Storage for External Graph Analytics
Half-Price Architecture
Reducing cache power with low-cost, multi-bit error-correcting codes
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures
DDDP: A Distributed Data Driven Processor
Generative and multi-phase learning for computer systems optimization
Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks
A case for exploiting subarray-level parallelism (SALP) in DRAM
Cache Memories for PDP-11 Family Computers
Execution Control and Memory Management of a Data Flow Signal Processor
Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocol
Ghost Routing to Enable Oblivious Computation on Memory-centric Networks
Speculative precomputation: long-range prefetching of delinquent loads
Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique
PolyGraph: Exposing the Value of Flexibility for Graph Processing Accelerators
Vector Multiprocessors with Arbitrated Memory Access
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer
Performance of multiple-bus multiprocssor under non-uniform memory reference model
A New String Search Hardware Architecture for VLSI
Accelerating Personalized Recommendation with Cross-level Near-Memory Processing
Performance Measurements on a Commercial Multiprocessor Running Parallel Code
Trading Conflict and Capacity Aliasing in Conditional Branch Predictors
Value Prediction in VLIW Machines
A Simulation Based Study of TLB Performance
Comparison of Sparing Alternatives for Disk Arrays
COP: to compress and protect main memory
Performance Prediction and Tuning on a Multiprocessor
Dynamic performance tuning for speculative threads
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
Early load address resolution via register tracking
Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization
Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks
Dynamic Instruction Reuse
An Object Oriented Architecture
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator
Write-Light Cache for Energy Harvesting Systems
Soft Error Correction for Increased Densities in VLSI Memories
A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, MES@ISCA 2016, Seoul, Republic of Korea, June 19, 2016
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks
An Analysis of Dynamic Branch Prediction Schemes on System Workloads
The White Dwarf: A High-Performance Application-Specific Processor
Timed Petri Nets and Preliminary Performance Evaluation
AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures
A Salable Dataflow Structure Store
Software Implementation of a Recursive Fault Tolerance Algorithm on a Network of Computers
Future Vector Microprocessor Extensions for Data Aggregations
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013
Tailored Page Sizes
Increasing the Number of Strides for Conflict-Free Vector Access
Enhancing and Exploiting Contiguity for Fast Memory Virtualization
Implementation of Precise Interrupts in Pipelined Processors
On Deadlocks in Interconnection Networks
Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988
Cracking Randomized Coalescing Techniques with An Efficient Profiling-Based Side-Channel Attack to GPU
Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
Whare-map: heterogeneity in "homogeneous" warehouse-scale computers
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
A Primlinary Architecture for a Basic Data-Flow Processor
The Architecture of a Fault-Tolerant Cached RAID Controller
Microprogrammable Processor for Object-Oriented Architecture
Splitwise: Efficient Generative LLM Inference Using Phase Splitting
Modeling critical sections in Amdahl's law and its implications for multicore design
A Programmable Hardware Accelerator for Simulating Dynamical Systems
Mystique: Enabling Accurate and Scalable Generation of Production AI Benchmarks
CRIB: consolidated rename, issue, and bypass
Charm: A Language for Closed-Form High-Level Architecture Modeling
Cambricon-SR: An Accelerator for Neural Scene Representation with Sparse Encoding Table
OmniOrder: Directory-based conflict serialization of transactions
Echo: Compiler-based GPU Memory Footprint Reduction for LSTM RNN Training
ThermoGater: Thermally-Aware On-Chip Voltage Regulation
Frameworks for a Taxonomy of Fault-Tolerance Attributes in Computer Systems
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors
Evaluation of the WM Architecture
A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution
Dynamo: Facebook's Data Center-Wide Power Management System
Semantic locality and context-based prefetching using reinforcement learning
Managing distributed UPS energy for effective power capping in data centers
EdgePC: Efficient Deep Learning Analytics for Point Clouds on Edge Devices
Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay
Thermometer: profile-guided btb replacement for data center applications
Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures
The Design and Implementation of a VLSI Chess Move Generator
Wattch: a framework for architectural-level power analysis and optimizations
Performance Comparison of ILP Machines with Cycle Time Evaluation
Instruction-level Parallelism in Prolog: Analysis and Architectural Support
Flowware - A Flow Charting Procedure to Describe Digital Networks
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC
UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space
QPlacer: Frequency-Aware Component Placement for Superconducting Quantum Computers
Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture
The Energy Efficiency of IRAM Architectures
End-to-end register data-flow continuous self-test
Concert: Design of a Multiprocessor Development System
The Universality of Various Types of SIMD Machine Interconnection Networks
The Piecewise Data Flow Architecture Control Flow and Register Management
An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs
Analysis of Memory Referencing Behavior For Design of Local Memories
A Technique for Reducing Synchronization Overhead in Large Scale Multiprocessors
LIA: A Single-GPU LLM Inference Acceleration with Cooperative AMX-Enabled CPU-GPU Computation and CXL Offloading
Conditional Memory Ordering
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation
An Architecture for High Volume Transaction Processing
Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity
Biscuit: A Framework for Near-Data Processing of Big Data Workloads
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
Finding an extremum in a network
Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog
Towards energy-proportional datacenter memory with mobile DRAM
TCEP: Traffic Consolidation for Energy-Proportional High-Radix Networks
An Efficient LISP-Execution Architecture with a New Representation for List Structures
DICE: Compressing DRAM Caches for Bandwidth and Capacity
The Performance Enhancement of Descriptor-Based Virtual Memory Systems Through The Use of Associative Registers
QIsim: Architecting 10+K Qubit QC Interfaces Toward Quantum Supremacy
Evaluation of Multithreaded Uniprocessors for Commercial Application Environments
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip
Probabilistic Shared Cache Management (PriSM)
Exploring the potential of heterogeneous von neumann/dataflow execution models
Design and Evaluation of a Relational Data Base Machine Employing Advanced Data Structures and Algorithms
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors
In-Storage Acceleration of Retrieval Augmented Generation as a Service
Prophet/Critic Hybrid Branch Prediction
Reducing access latency of MLC PCMs through line striping
XPC: architectural support for secure and efficient cross process call
Demand-driven software race detection using hardware performance counters
Auto-Predication of Critical Branches
A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance Servers
Detailed Design and Evaluation of Redundant Multithreading Alternatives
Sibyl: adaptive and extensible data placement in hybrid storage systems using online reinforcement learning
An Approach to Using VLSI in Digital Systems
Designing High Bandwidth On-Chip Caches
Interface, A Dispersed Architecture
X-Tree: A Tree Structured Multi-Processor Computer Architecture
Clean: a race detector with cleaner semantics
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
A Multi-Microprocessor Implementation of a General Purpose Pipelined CPU
DSAGEN: Synthesizing Programmable Spatial Accelerators
Distributed Fault-Tolerance For Large Multiprocessor Systems
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
Using hardware vulnerability factors to enhance AVF analysis
ActivePointers: A Case for Software Address Translation on GPUs
Bypass and insertion algorithms for exclusive last-level caches
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
An Array Processor for Petroleum Exploration
MegIS: High-Performance, Energy-Efficient, and Low-Cost Metagenomic Analysis with In-Storage Processing
(MC) 2 : Lazy MemCopy at the Memory Controller
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism
Clifford-based Circuit Cutting for Quantum Simulation
Rapid identification of architectural bottlenecks via precise event counting
KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency
Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays
Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling
A Hardware Architecture for Controlling Information Flow
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers
Filter caching for free: the untapped potential of the store-buffer
Analysis of Cray-1S Architecture
Enabling High Performance Debugging for Variational Quantum Algorithms using Compressed Sensing
Improvements in Multiprocessor System Design
Architecture and Evaluation of High-Speed Networking Subsystem for Distributed-Memory Systems
Dancing the Quantum Waltz: Compiling Three-Qubit Gates on Four Level Architectures
Decoupled SSD: Rethinking SSD Architecture through Network-based Flash Controllers
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
The Hardware Architecture of the CRISP Microprocessor
Retrospective: The Cedar System
Inexpensive Implementations of Set-Associativity
Scaling Intel® Software Guard Extensions Applications with Intel® SGX Card
Tolerating Multiple Failures in RAID Architectures with Optimal Storage and Uniform Declustering
GT-EP: A Novel High-Performance Real-Time Architecture
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs
Design of Fault-Tolerant Associative Processors
Fine-grained warm water cooling for improving datacenter economy
Virtual-Channel Flow Control
SynFull: Synthetic traffic models capturing cache coherent behaviour
Pseudo-Randomly Interleaved Memory
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller
SLIP: reducing wire energy in the memory hierarchy
Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments
Aérgia: exploiting packet latency slack in on-chip networks
Computer Architecture Courses in Electrical Engineering Departments
BlockMaestro: Enabling Programmer-Transparent Task-based Execution in GPU Systems
Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015
Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
SARA: Scaling a Reconfigurable Dataflow Accelerator
An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors
InvisiFence: performance-transparent memory ordering in conventional multiprocessors
Cohesion: a hybrid memory model for accelerators
Decoupled access/execute computer architectures
Efficient methods and hardware for deep learning
SoftSKU: optimizing server architectures for microservice diversity @scale
On-Line Algorithms for the Design of Pipeline Architectures