yusuke1997/dblp-id-title huggingface dataset:
Complete instrumentation requirements for performance analysis of Web based technologies
Understanding Data Compression in Warehouse-Scale Datacenter Services
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators
Impact of System Resources on Performance of Deep Neural Network
TPNM: A CXL Based General Purpose Tiered Process Near Memory Framework
2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
Performance implications of chipset caches in web servers
Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture
An efficient solver for Cache Miss Equations
Empirical Investigation of Stale Value Tolerance on Parallel RNN Training
Microarchitecture level reliability comparison of modern GPU designs: First findings
ParTejas: A parallel simulator for multicore processors
µqSim: Enabling Accurate and Scalable Simulation for Interactive Microservices
Mobile functionality in a pervasive world
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
Evaluating the importance of virtual memory for Java
Proctor: Detecting and Investigating Interference in Shared Datacenters
Accelerating network-on-chip simulation via sampling
X-Mem: A cross-platform and extensible memory characterization tool for the cloud
Analysis of the TRIPS prototype block predictor
FPGA modeling of diverse superscalar processors
lfbench: a lock-free microbenchmark suite
An Application-Oriented Approach to Designing Hybrid CPU Architectures
Characterizing Massively Parallel Polymorphism
Characterizing the Runtime Effects of Object-Oriented Workloads on GPUs
Differentiating the roles of IR measurement and simulation for power and temperature-aware design
A comprehensive analysis and parallelization of an image retrieval algorithm
Critical-path candidates: scalable performance modeling for MPI workloads
Keynote I: The era of heterogeneity: Are we prepared?
Pareto Rank Surrogate Model for Hardware-aware Neural Architecture Search
Evaluating Compute in Memory Architectures for Matrix Multiplication: A Dataflow-Centric Perspective
SGXGauge: A Comprehensive Benchmark Suite for Intel SGX
Profiling Concurrent Vision Inference Workloads on NVIDIA Jetson
Power signature analysis of the SPECpower_ssj2008 benchmark
Fast IPC estimation for performance projections using proxy suites and decision trees
BTBench: A Benchmark for Comprehensive Binary Translation Performance Evaluation
HMMer-Cell: High Performance Protein Profile Searching on the Cell/B.E. Processor
Exascale workload characterization and architecture implications
An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases
Docker characterization on high performance SSDs
On the Impact of Instruction Address Translation Overhead
Cache implications of aggressively pipelined high performance microprocessors
Characterization and architectural implications of big data workloads
Interconnect Performance Estimation for ML Accelerators via Lightweight Analytical Model
QTrace: An interface for customizable full system instrumentation
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors
An FPGA-based multi-core platform for testing and analysis of architectural techniques
Forward to the Past: An Alternative to Hybrid CPU Design
Supply voltage emulation platform for DVFS voltage drop compensation explorations
Sunstone: A Scalable and Versatile Scheduler for Mapping Tensor Algebra on Spatial Accelerators
PMAL: Enabling lightweight adaptation of legacy file systems on persistent memory systems
The Future of Instruction-Level Parallelism (ILP)
Characterization of Data Compression in Datacenters
Machine learning for performance and power modeling/prediction
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Predicting memory page stability and its application to memory deduplication and live migration
MESA: reducing cache conflicts by integrating static and run-time methods
Horus: A Modular GPU Emulator Framework
Structures for phase classification
A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems
Modeling and Characterizing Power Variability in Multicore Architectures
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
Profiling gem5 Simulator
FastCap: An efficient and fair algorithm for power capping in many-core systems
Sockets Direct Protocol over InfiniBand in clusters: is it beneficial?
Advancing Near-Data Processing with Precise Exceptions and Efficient Data Fetching
Evaluating Intel 3D-Xpoint NVDIMM Persistent Memory in the Context of a Key-Value Store
Characterization of MPC-based Private Inference for Transformer-based Models
Using cache mapping to improve memory performance handheld devices
Tango: A Deep Neural Network Benchmark Suite for Various Accelerators
The effects of context switching on branch predictor performance
MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration
SuperSim: Extensible Flit-Level Simulation of Large-Scale Interconnection Networks
2015 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2015, Philadelphia, PA, USA, March 29-31, 2015
Thermal-Aware Overclocking for Smartphones
Graph-matching-based simulation-region selection for multiple binaries
Accurate simulation and evaluation of code reordering
Accurately approximating superscalar processor performance from traces
Evaluating Memory Performance of Emerging Scale-Out Applications Using C-AMAT
2003 IEEE International Symposium on Performance Analysis of Systems and Software, March 6-8, 2003, Austin, Texas, USA, Proceedings
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation
Zatel: Sample Complexity-Aware Scale-Model Simulation for Ray Tracing
Locality-aware predictive scheduling of network processors
Balancing Performance and Reliability in the Memory Hierarchy
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies
Anatomy and Performance of SSL Processing
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity
SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads
A new approach in the analysis and modeling of disk access patterns
Performance modelling of distributed e-business applications using Queuing Petri Nets
ISA-independent workload characterization and its implications for specialized architectures
Analysis of Network Processing Workloads
Keynote: Parallelism, heterogeneity, communication: Emerging challenges for performance analysis
OS-level Implications of Using DRAM Caches in Memory Disaggregation
Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs
Aiding Microprocessor Performance Validation with Machine Learning
Fused: Closed-Loop Performance and Energy Simulation of Embedded Systems
Evaluating trace aggregation for performance visualization of large distributed systems
Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization
FOURST: A code generator for FFT-based fast stencil computations
Evaluation and Comparison of the Energy Efficiency of Several Intel Multicore Processors
GeST: An Automatic Framework For Generating CPU Stress-Tests
Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory
Altis: Modernizing GPGPU Benchmarks
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation
Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads
Manifold: A parallel simulation framework for multicore systems
Applying the roofline model
StatStack: Efficient modeling of LRU caches
Meterstick: Benchmarking Performance Variability in Cloud and Self-hosted Minecraft-like Games
Data Direct I/O Characterization for Future I/O System Exploration
Detecting race conditions in asynchronous DMA operations with full system simulation
HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators
Exploring Constrained Dataflow Accelerators for Real-Time Multi-Task Multi-Model Ml Workloads
Balancing thoughput and fairness in SMT processors
Precise computer comparisons via statistical resampling methods
The Indigo Program-Verification Microbenchmark Suite of Irregular Parallel Code Patterns
Characterizing a Commercial Multidimensional Heterogeneous Processor Under GPGPU Workloads
Lonestar: A suite of parallel irregular programs
Distributed Software Defined Networking Controller Failure Mode and Availability Analysis
Degree-Aware Kernel Mapping for Graph Processing on GPUs
DNA Storage Toolkit: A Modular End-to-End DNA Data Storage Codec and Simulator
Performance analysis using pipeline visualization
RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors
Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation
Program Phase Detection based on Critical Basic Block Transitions
A Defense-Inspired Benchmark Suite
About the sensitivity of the HLRC-DU protocol on diff and page sizes
Concurrent PIM and Load/Store Servicing in PIM-Enabled Memory
Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application
Pinpointing the Memory Behaviors of DNN Training
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures
Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine Learning Accelerator
Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels
Algorithmic Performance-Accuracy Trade-off in 3D Vision Applications
Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions
Characterization and analysis of a web search benchmark
Characterizing Compute-Communication Overlap in GPU-Accelerated Distributed Deep Learning: Performance and Power Implications
DB2 for OS/390 V5 vs. V6 outer join performance
Efficient architectural design of high performance microprocessors
PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments
Dynamically reducing pressure on the physical register file through simple register sharing
Friendly fire: understanding the effects of multiprocessor prefetches
Library of Networks: An Online Tool for Design and Analysis of Network Topologies
A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity
Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification
Characterizing the Scalability of Graph Convolutional Networks on Intel ® PIUMA
Scaling OLTP applications on commodity multi-core platforms
DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator
Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures
Parallel GPU architecture simulation framework exploiting work allocation unit parallelism
Evaluating Performance Tradeoffs on the Radeon Open Compute Platform
Instruction overhead and data locality effects in superscalar processors
Simulating Noisy Channels in DNA Storage
Workloads, Scalability, and QoS Considerations in CMP Platforms
Weak execution ordering - exploiting iterative methods on many-core GPUs
Characterization of GPGPU workloads on a multidimensional heterogeneous processor
DVFS performance prediction for managed multithreaded applications
A reconfigurable simulator for large-scale heterogeneous multicore architectures
Increasing the Transparent Page Sharing in Java
2012 IEEE International Symposium on Performance Analysis of Systems & Software, New Brunswick, NJ, USA, April 1-3, 2012
Geomancy: Automated Performance Enhancement through Data Layout Optimization
Explaining the Impact of Network Transport Protocols on SIP Proxy Performance
Revisiting symbiotic job scheduling
A statistical multiprocessor cache model
Demystifying Bayesian Inference Workloads
Pro-active Page Replacement for Scientific Applications: A Characterization
OpenSoC Fabric: On-chip network generator
High-Performance Deployment of Text Detection Model: Compression and Hardware Platform considerations
Anatomy of microarchitecture-level reliability assessment: Throughput and accuracy
Identifying Important Data Transformations for Synthesizing Effective Lossless Compressors
E3: A HW/SW Co-design Neuroevolution Platform for Autonomous Learning in Edge Device
Performance modeling and prediction for scientific Java applications
Evaluating the Impact of Optimizations for Dynamic Binary Modification on 64-bit RISC-V
Modeling Architectural Support for Tightly-Coupled Accelerators
Toolbox for exploration of energy-efficient event processors for human-computer interaction
Infrastructure for Exploring SIMT Architecture in General-Purpose Processors
Sieve: Stratified GPU-Compute Workload Sampling
CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (TinyML) Acceleration on FPGAs
Impact of LTE precoding for fixed and adaptive rank transmission in moving relay node system
Theoretical analysis and measurements: Doppler spectra of vehicular communication channels
Broadband communication solutions for maritime ITSs: Wider and faster deployment of new e-navigation services
Real-time DSP implementation of Pedestrian Detection algorithm using HOG features
A Preliminary Apportionment of Safety Targets for Virtual Balise Detection using GNSS in Future Evolutions of ERTMS
A Complete Transmission Acknowledgement Scheme for VANETs
Real time delay estimation for signalized intersection using transit vehicle positioning data
Modulation spectrum exponential weighting for robust speech recognition
eCall implementation roadmap for Finland
Vessel route analysis by in situ measurements A pre-requisite for Maritime Spatial Planning
Controlling signature verification of network coded packet on VANET
A proposal of the rendezvous navigation system
Design and experiment of a small boat auto-berthing control system
An unbiased average traffic speed estimation method for intelligent transportation system
A multi-level cooperative perception scheme for autonomous vehicles
Improving GPS-based road network constructions in a post-processing step of global optimization
Onboard integration of maritime safety information for navigation display and route safety
Real-time urban traffic sensing with GPS equipped Probe Vehicles
Deriving the vehicle speeds from mobile telecommunications network
Region segmentation and labeling in aerial surveillance applications
Introduction of Prototype of Remote Type Automated Vehicle System by using Communication between Operator and Vehicles in Real Environment
A novel design for full automatic parking system
Road environment recognition method in complex traffic situations based on stereo vision
Sidelink Technologies Comparison for Highway High-Density Platoon Emergency Braking
Building representative velocity profiles using FastDTW and spectral clustering
A love of travel - Demonstration project of Sun-Moon Lake importing ITS/telematics
Analysis of average packet acquisition time on wireless butterfly-typed network coding scheme
Study of channel selection strategies in cognitive radio networks
A Group User Location Management Scheme Based on the Stochastic Time Delay
Image registration among UAV image sequence and Google satellite image under quality mismatch
Cloud-based mobile system for biometrics authentication
Analysis of the Optimal Cooperation Scope of Bandwidth Sharing in vehicular networks
Chunk-based resource allocation under user rate constraints in multiuser MIMO-OFDM systems
Application of MBSE as a support to the definition of the port informer service in the Italian ports
Rapid changing channel estimation and equalisation based on hyperbolic modelling for OFDM systems
Reducing the environmental impact of taxi operation: The taxi-sharing use case
A novel multicore SDR architecture for smart vehicle systems
Navigation system using ZigBee wireless sensor network for parking
Extended electronic horizon for automated driving
Comparative evaluation of information dissemination method for Dynamic Vehicular Route Planning
Comparison of travel times estimation using intelligent infrastructure and floating car data
Analysis of a high-performance mobile access to a computing cloud using MPTCP protocol and IEEE 802.11ac network
VLSI implementation of a real-time vision based lane departure warning system
MIMO antenna configuration for LTE in railway
Enhanced wireless broadcasting systems employing network coding
Performance Evaluation of an Emergency Vehicle in a Simulated Traffic Scenario
Block-coded 16TAPSK and 16QAM for generalized differential encoding
Research on building computation of ontology-based knowledge base
An emergency earthquake warning system using mobile terminals with a built-in accelerometer
Stabilization time comparison of CSMA and Self-Organizing TDMA for different channel loads in VANETS
Bandwidth efficient turbo coded OFDM systems
Study for the effect of hasty state while driving on potential risks
A smartphone-based heart rate variability analysis system for vehicle drivers
Novel blind identification of LDPC codes using average LLR of syndrome a posteriori probability
Insights in costing of continuous broadband internet on trains to allow delivering value via services
Safe and Reliable Spatio-temporal Model for Roundabouts and Road Intersections using Vehicular Communication System
Development of LTE-based channel tester for high-speed scenario
Emergency incident management system for community safety services (EIMS)
WRTA - Wake-Up-Receiver optimised routing and topology optimisation approach
Vehicle clustering algorithm for sharing information on traffic congestion
A sample-mode packet delay variation filter for IEEE 1588 synchronization
Holistic approach to future green mobile communications
A cross-layer design for P2P live streaming with graceful handover in mobile IP network
GNSS based train localization for automatic train operation
An iterative ICI equalization and cancellation scheme for LTE SC-FDMA systems in multipath channels
Ground traffic surveillance system for Air Traffic control
Novel proposal for V2X systems and WBAN cooperation to improve road safety
Impact of omnidirectional and directive antennas on WLAN link performance under in-band interference
Measurements-Based Research on Correlation of MIMO Channel in High-Speed Scenario
An optical CDMA method for in-vehicle information service
A farthest-first forwarding algorithm in VANETs
Resolving TCP re-ordering issues on a multi-homed NEMO-based network
Can V2X communication help electric vehicles save energy?
Exploiting the forecast channels for power allocation in High-Speed Railway communications
Mitigating location and speed errors in floating car data using context-based accuracy estimation
A passenger-based adaptive traffic signal control mechanism in Intelligent Transportation Systems
Performance evaluation of a Wireless LAN positioning system using spot information
An efficient and reliable multi-hop geographical broadcast protocol in Vehicular Ad-hoc Networks
High precision testbed to evaluate ethernet performance for in-car networks
Micro-VMS: A VMS Mobile Unit for Artisanal Fishing Vessels
A traffic information dissemination mechanism based on DSRC/WAVE and its applications
Adage mobile services for ITS infrastructure
On the coverage of LPWANs: range evaluation and channel attenuation model for LoRa technology
The effects of moving speed on handover performances with measurement data
Management of Transitions of Control in Mixed Traffic with Automated Vehicles
Performance evaluation of AODV, DSR, GRP and OLSR for VANET with real-world trajectories
A non-stationary geometry-based stochastic model for MIMO high-speed train channels
13th International Conference on ITS Telecommunications, ITST 2013, Tampere, Finland, November 5-7, 2013
Speed estimation based on multiple kernel learning
Examining Human Factors for marine casualties using HFACS - maritime accidents (HFACS-MA)
Vehicle speed estimation using video data and acceleration information of a drive recorder
A study of DSRC jammer in vehicle safety application testbed
An approach to increase fuel economy with traffic signals
An effective multi-hop broadcast control mechanism for emergency alert message in VANET
Implementation of car-following system using LiDAR detection
An overview of GSM-R technology and its shortcomings
Multistage wiener filter based spectrum sensing in cognitive radio
IoT approach applied in the context of ITS: monitoring highways through instant messaging
Integration of PLMN and satellite networks for train control and traffic management via MPTCP
Under-exposed image enhancement using exposure compensation
Immediate feedback to increase the throughput of full duplex networks based on IEEE 802.11p
Sum-rate based relay selection with feedback delay for a multiple half/full-duplex two-way relaying
A surface-based vacant space detection for an intelligent parking lot
A registration system for aiding in localization and routing in hybrid VANETs
An anti-interference method for radio signals based on matching pursuit algorithm
Context-aware service composition in cyber physical human system for transportation safety
A complex modulo-and-forward strategy for two-way relay systems
A study on estimation method of pedestrian's walking status for GPS positioning correction
Reliability Maximization with Location-Based Scheduling for Cellular-V2X Communications in Highway Scenarios
Distributed source coding for mobile ECG signal monitoring
The Autonomous Train: a game changer for the railways industry
An adaptive driving assistance system for electric vehicle
An approach to evaluating digital transmission under electromagnetic disturbance using joint statistical parameters
Modified selective mapping technique for PAPR reduction in OFDM systems
Estimation of channel variation and its applications in OFDM-based systems
Performance evaluation of real-time MEMS INS/GPS integration with ZUPT/ZIHR/NHC for land navigation
Detection of Texting While Walking by Using Smartphone's Posture and Acceleration Information for Safety of Pedestrians
Virtual testing of the on-board ETCS with GNSS based Train integrity determination
Field trial of cellular warning for automobiles using geomessaging in Japan
Estimation of pedestrian's action by using pressure sensor and moving record for ITS
Performance of the max-dmin precoder in impulsive noise for railway communications in tunnels
Recovering noncoherent MPSK signal with unknown delay and Doppler using its ambiguity function
Novel frequency offset estimation for IEEE 802.11p standard in V2V channels
Visual saliency-aware radio resource allocation for image transmission in SC-FDMA systems
Channel Analysis and Performance Evaluation for Inter-Vehicle Communication in 700 MHz Band at Intersection with Low Visibility
Cluster-based spatial planning and evaluation of maritime mesh network using vessel traffic data
WINNER model for subway tunnel at 5.8 GHz
Fast and Reliable Hybrid routing for Vehicular Ad hoc Networks
Evaluation of DS/SS-IVC based on location oriented code allocation considering propagation delay
Automatic fault detection and execution monitoring in cooperative maneuvering
Two-tier receiver-initiated secure scheme for hierarchical wireless sensor networks
Policies for efficient usage of an EV charging infrastructure deployed in city parking facilities
Maritime awareness through data sharing in VTS systems
Spray and Locate Routing for Vehicular Delay-Tolerant Networks
Agent based simulation applied to the design of control systems for emergency vehicles access
Making channel hopping sequences for self-organized mobile networks