yusuke1997/dblp-id-title huggingface dataset:
Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization
Arithmetic Interactions: From Hardware to Applications
Self Checking in Current Floating-Point Units
On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal
Multi-fault Attack Detection for RNS Cryptographic Architecture
Delay optimization of carry-skip adders and block carry-lookahead adders
Systolic solution of linear systems over GF(p) with partial pivoting
Evaluating Straight-Line Programs over Balls
A CRC-Based Concurrent Fault Detection Architecture for Galois/Counter Mode (GCM)
Rounding algorithms for IEEE multipliers
Roundings in floating point arithmetic
Single Precision Natural Logarithm Architecture for Hard Floating-Point and DSP-Enabled FPGAs
Fast multipliers for two's-complement numbers in serial form
Accelerating Matrix Processing with GPUs
Efficient Function Approximation Using Truncated Multipliers and Squarers
Higher Radix Squaring Operations Employing Left-to-Right Dual Recoding
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands
Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB
IEEE Interval Standard Working Group - P1788: Current Status
Arithmetic for Relative Accuracy
Scaled and Unscaled Residue Number System to Binary Conversion Techniques using the Core Function
Certified and Fast Computation of Supremum Norms of Approximation Errors
Accurate and Fast Evaluation of Elementary Symmetric Functions
Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme
A Formally-Verified C Compiler Supporting Floating-Point Arithmetic
A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator
High-Radix Implementation of IEEE Floating-Point Addition
An asymptotically faster version of FV supported on HPR
Synchronous Up/Down Counter with Clock Period Independent of Counter Size
Continued fractions for high-speed and high-accuracy computer arithmetic
Combining Precision Tuning and Rewriting
Faster Arbitrary-Precision Dot Product and Matrix Multiplication
Desirable floating-point arithmetic and elementary functions for numerical computation
A feasibility analysis of binary fixed-slash and floating-slash number systems
Incompletely specified numbers in the residue number system-definition and applications
21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013
Implementation Evaluation of Fixed-Point Multipliers for Complex Numbers
Solving Range Constraints for Binary Floating-Point Instructions
Base conversion in residue number systems
Fast Arithmetic Modulo 2 x p y ± 1
9th Symposium on Computer Arithmetic, ARITH 1989, Santa Monica, CA, USA, September 6-8, 1989
DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference
Numerical limitations on the design of digit online networks
Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
On Various Ways to Split a Floating-Point Number
Fast hardware units for the computation of accurate dot products
A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications
A novel floating-point online division algorithm
Fast Modular Reduction
Fast multiplication of binary polynomials with the forthcoming vectorized VPCLMULQDQ instruction
Precise and Concise Graphical Representation of the Natural Numbers
Structured arithmetic tiling of integrated circuits
Hardware provisions for extended precision floating-point arithmetic
Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography
Constant time arbitrary length synchronous binary counters
Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli
Towards quantitative comparison of computer number systems
FPU Generator for Design Space Exploration
The Unary Arithmetical Algorithm in Bimodular Number Systems
On combinational logic for sign detection in residue number systems
A Hardware Algorithm for Integer Division
Fast division using accurate quotient approximations to reduce the number of iterations
Application of fast layout synthesis environment to dividers evaluation
A parallel compensated Horner scheme for SIMD architecture
Correctly Rounded Multiplication by Arbitrary Precision Constants
Optimizing Matrix Multiplication on Intel® Xeon Phi TH x200 Architecture
Arithmetic algorithms for operands encoded in two-dimensional low-cost arithmetic error codes
Semi-Automatic Implementation of the Complementary Error Function
High-Speed Inverse Square Roots
Design of residue generators and multioperand modular adders using carry-save adders
Long Number Bit-Serial Squarers
Fast evaluation of polynomials and inverses of polynomials
Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms
Design of arithmetic elements for Burroughs Scientific Processor
Parallel adders using standard plas
A simulator for on-line arithmetic
Improved normalization results for digit on-line arithmetic
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
Fast implementations of RSA cryptography
A polarizer for negative binary numbers
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector
A realistic model for error estimates in the evaluation of elementary functions
Pipelining of arithmetic functions
Precise and Fast Computation of Elliptic Integrals and Functions
IEEE 32nd Symposium on Computer Arithmetic, ARITH 2025, El Paso, TX, USA, May 4-7, 2025
VAX hardware for the proposed IEEE floating-point standard
Approximate Floating-Point Operations with Integer Units by Processing in the Logarithmic Domain
Higher Order Computer Arithmetic
Fast Reproducible Floating-Point Summation
Complex SLI arithmetic: Representation, algorithms and analysis
Formal systems of numerals
ROM-less LNS
A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration
A negative-binary adder-subtracter
On the Design of High-Radix On-Line Division for Long Precision
Towards Correctly Rounded Transcendentals
Privacy-Preserving Deep Learning via Additively Homomorphic Encryption
On the numerical algorithms formulated in computer arithmetic
Towards a correctly-rounded and fast power function in binary64 arithmetic
Efficient SIMD Arithmetic Modulo a Mersenne Number
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition
Multivariable polynomial processing - Applications to interpolation
On the Computation of Correctly-Rounded Sums
A Priori Worst-Case Error Bounds for Floating-Point Computations
Standards for computer arithmetic
Accurate Complex Multiplication in Floating-Point Arithmetic
Algorithm partition for a fixed-size VLSI architecture using space-time domain expansion
Improved Table Lookup Algorithms for Postscaled Division
The Classical Relative Error Bounds for Computing Sqrt(a^2 + b^2) and c / sqrt(a^2 + b^2) in Binary Floating-Point Arithmetic are Asymptotically Optimal
Solving Constraints on the Invisible Bits of the Intermediate Result for Floating-Point Verification
Hardware Implementations of Denormalized Numbers
30th IEEE Symposium on Computer Arithmetic, ARITH 2023, Portland, OR, USA, September 4-6, 2023
An underflow-induced graphics failure solved by SLI arithmetic
Toward an ideal computer arithmetic
Digit Recurrence Floating-Point Division under HUB Format
Montgomery Reduction Algorithm for Modular Multiplication Using Low-Weight Polynomial Form Integers
Efficient Word Size Modular Multiplication over Signed Integers
Under- and Overflow Detection in the Residue Logarithmic Number System
A Sum Error Detection Scheme for Decimal Arithmetic
A parallel method for computing the generalized singular value decomposition
A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks
Shadow computation with BFloat16 to estimate the numerical accuracy of summations
The IBM zEnterprise-196 Decimal Floating-Point Accelerator
Another Look at Inversions over Binary Fields
Efficient Data Structure and Algorithms for Sparse Integers, Sets and Predicates
Representation and processing of fractions in a residue system
Robust, End-to-end Correctness Proofs of Industrial Divide and Square Root RTL Designs
Exploiting trivial and redundant computation
A unified numeric data type in Pascal
Merged arithmetic for signal processing
Hybrid Position-Residues Number System
Higher radix on-line division
An Empirical Study of Microscaling Formats for Low-Precision LLM Training
The conversion of Hensel codes to rational numbers
Significance arithmetic: Application to a partial differential equation
A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point
Radix-8 Digit-by-Rounding: Achieving High-Performance Reciprocals, Square Roots, and Reciprocal Square Roots
On the Flop and Flap Counts of the 2, 8-Split-Radix FFT
Vector reduction methods for arithmetic pipelines
Matrix processors using p-ADIC arithmetic for exact linear computations
APyTypes: Algorithmic Data Types in Python for Efficient Simulation of Finite Word-Length Effects
4th IEEE Symposium on Computer Arithmetic, ARITH 1978, Santa Monica, CA, USA, October 25-27, 1978
Compatible number representations
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
Montgomery Modular Multiplication via Single-Base Residue Number Systems
Small moduli replications in the MRRNS
Redundant Binary Booth Recoding
MATLAB Simulator of Level-Index Arithmetic
Large Scale Numerical Simulations of the Climate
Computing floating-point logarithms with fixed-point operations
A Perspective into Squarer Optimization
Precision, Accuracy, and Rounding Error Propagation in Exascale Computing
Variable-Radix Coding of the Reals
Solving Constraints on the Intermediate Result of Decimal Floating-Point Operations
$a \cdot(x\cdot\ x)$ or $(a\cdot x)\cdot x?$
Reproducible Summation Under HUB Format
Dither computing: a hybrid deterministic-stochastic computing framework
Efficient multiprecision floating point multiplication with optimal directional rounding
11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings
Anomalies in the IBM ACRITH package
On the implementation of shifters, multipliers, and dividers in VLSI floating point units
14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia
Rounding Error Analysis of an Orbital Collision Probability Evaluation Algorithm
Compile-Time Generation of Custom-Precision Floating-Point IP using HLS Tools
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
A closed computer arithmetic
A Q-Coder Algorithm with Carry Free Addition
A Reverse Converter for the 4-moduli Superset {2 n-1 , 2 n , 2 n+1 , 2 n+1 +1}
Parallel multipliers based on horizontal compressors
Latency Sensitive FMA Design
Accelerating Computations on FPGA Carry Chains by Operand Compaction
The Gauss machine: A Galois-enhanced quadratic residue number system systolic array
Worst Cases and Lattice Reduction
On-the-fly rounding for division and square root
A high-radix hardware algorithm for calculating the exponential M E modulo N
On arithmetic inter-relationships and hardware interchangeabiltty of negabinary and binary systems
On error analysis in arithmetic with varying relative precision
Issues with rounding in the GCC implementation of the ISO 18037: 2008 standard fixed-point arithmetic
Scalable architecture of constant division on FPGA
The modified CORDIC algorithm
Floating point Cordic
On-line CORDIC algorithms
Fast Software Exponentiation in GF(2^k)
Automatic Datapath Optimization using E-Graphs
Division by Constant for the ST100 DSP Microprocessor
A Study of the Effects and Benefits of Custom-Precision Mathematical Libraries for HPC Codes
The CORE-MATH Project
Decimal Floating-Point: Algorism for Computers
Round-off Error Analysis of Explicit One-Step Numerical Integration Methods
Some Improvements on Multipartite Table Methods
Implementation and Performance Evaluation of an Extended Precision Floating-Point Arithmetic Library for High-Accuracy Semidefinite Programming
On-Line Multiplication in Real and Complex Base
Pipeline Optimization using a Cost Extension of Timed Petri Nets
The UNRAU a Unified Numeric Representation Arithmetic Unit
A Family of Adders
A systematic approach to the design of structures for arithmetic
Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units
A unified approach to a class of number systems
Spectral Modular Exponentiation
A Parallel Method for the Computation of Matrix Exponential Based on Truncated Neumann Series
Algorithms for parallel addition and parallel polynomial evaluation
n × n carry-save multipliers without final addition
ARM Floating Point 2019: Latency, Area, Power
Generating Residue Number System Bases
On the Design of Fast IEEE Floating-Point Adders
On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations
Formally verified 32- and 64-bit integer division using double-precision floating-point arithmetic
Challenges in Automatic Optimization of Arithmetic Circuits
Unified Approach to the Design of Modulo-(2 n +/- 1) Adders Based on Signed-LSB Representation of Residues
Redundant CORDIC Rotator Based on Parallel Prediction
Multiplications of Floating Point Expansions
Worst Cases of a Periodic Function for Large Arguments
Highly Optimized Montgomery Multiplier for SIKE Primes on FPGA
Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation
Multi - Input residue arithmetic utilizing read - Only associative memory
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip
The Residue Logarithmic Number System: Theory and Implementation
A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
Fault-tolerant systolic arrays: An approach based upon residue arithmetic
Systolic up/down counters with zero and sign detection
Applications for arithmetic error codes in large, high-performance computers
High-Performance Hardware for Function Generation
A formal approach to rounding
On an interval arithmetic and its applications
3rd IEEE Symposium on Computer Arithmetic, ARITH 1975, Dallas, TX, USA, November 19-20, 1975
Semi-Automatic Floating-Point Implementation of Special Functions
Higher radix, non-restoring division: History and recent developments
Fast area-efficient VLSI adders
An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2)
SVD by constant-factor-redundant-CORDIC
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores
A simulative study of correlated error propagation in various finite arithmetics
A 17 × 69 bit multiply and add unit with redundant binary feedback and single cycle latency
Automatic Generation of Code for the Evaluation of Constant Expressions at Any Precision with a Guaranteed Error Bound
Representation of numbers in nonclassical numeration systems
A Less Recursive Variant of Karatsuba-Ofman Algorithm for Multiplying Operands of Size a Power of Two
High Degree Toom'n'Half for Balanced and Unbalanced Multiplication
Exploiting redundancy in bit-pipelined rational arithmetic
FastTwoSum revisited
A Unidirectional Bit Serial Systolic Architecture for Double-Basis Division over GF(2m)
In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32
The Interval Logarithmic Number System
Excvate: Spoofing Exceptions and Solving Constraints to Test Exception Handling in Numerical Libraries
Algorithms and Arithmetic: Choose Wisely
Multiple error correction and additive overflow detection with magnitude indices in residue code
Complement representations in the Fibonacci computer
Accurate and monotone approximations of some transcendental functions
The Return of Silicon Efficiency
Lexicographic encoding of numeric data fields
Floating-Point Fused Multiply-Add under HUB Format
Optimal purely systolic addition
1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features
Combining Restoring Array and Logarithmic Dividers into an Approximate Hybrid Design
Fast Modular Reduction for Large Wordlengths via One Linear and One Cyclic Convolution
Chromatic Analysis of Numerical Programs
Conditions for the distributivity of multiplication with respect to set addition and their effect on the design of array multipliers
Efficient Additions and Montgomery Reductions of Large Integers for SIMD
Parallel Montgomery Multiplication in GF(2 k ) Using Trinomial Residue Arithmetic
Decimal Floating-Point Multiplication Via Carry-Save Addition
27th IEEE Symposium on Computer Arithmetic, ARITH 2020, Portland, OR, USA, June 7-10, 2020
Optimal Word-Length Allocation for the Fixed-Point Implementation of Linear Filters and Controllers
Logical design of a redundant binary adder
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition
On-line algorithms for division and multiplication
The Exact Real Arithmetical Algorithm in Binary Continued Fractions
A complex-number multiplier using radix-4 digits
A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding
The Case for a Redundant Format in Floating Point Arithmetic
Polyphase convolvers
The FELIN arithmetic coprocessor chip
Computer Arithmetic - A Programmer's Perspective
Estimating the power consumption of CMOS adders
Application of continued fractions for fast evaluation of certain functions on a digital computer
Useful applications of correctly-rounded operators of the form ab + cd + e
Teraflop FPGA Design
23nd IEEE Symposium on Computer Arithmetic, ARITH 2016, Silicon Valley, CA, USA, July 10-13, 2016
A class of A(N + C) codes and its properties
Efficient Reduction Algorithms for Special Gaussian Integer Moduli
Range Extension with Supernormals for Mixed-Precision 8-bit DNN Training
Computer Arithmetic Research to Accelerate Privacy-Protecting Encrypted Computing Such as Homomorphic Encryption
Multi-parallel convolvers
ULPs and Relative Error
On the Componentwise Accuracy of Complex Floating-Point Division with an FMA
Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder
An arithmetic module for efficient evaluation of functions
Adaptive beamforming using RNS arithmetic
SRT Division Algorithms as Dynamical Systems
A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor
Faithful Interpolation in Reciprocal Tables
25th IEEE Symposium on Computer Arithmetic, ARITH 2018, Amherst, MA, USA, June 25-27, 2018
A Hole in the Ladder : Interleaved Variables in Iterative Conditional Branching
Regular, area-time efficient carry-lookahead adders
Design and Implementation of An RNS Division Algorithmm
High-precision computation: Applications and challenges [Keynote I]
Floating Point Tangent Implementation for FPGAs
Mixing Condition Numbers and Oracles for Accurate Floating-point Debugging
Analysis of Column Compression Multipliers
Tight Certification Techniques for Digit-by-Rounding Algorithms with Application to a New 1/sqrt(x) Design
Symmetric Bipartite Tables for Accurate Function Approximation
An accurate, high speed implementation of division by reciprocal approximation
A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
Groupoids and computer arithmetic
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability
Approximate Recursive Multipliers Using Low Power Building Blocks
How to Square Floats Accurately and Efficiently on the ST231 Integer Processor
Developing large binary to BCD conversion structures
Synthesis of area-efficient VLSI architectures for vector and matrix multiplication
Redundancy in number representations as an aspect of computational complexity of arithmetic functions
Optimal group distribution in carry-skip adders
Improved Montgomery Multiplication
Evaluating elementary functions with Chebyshev polynomials on pipeline nets
A division algorithm with prediction of quotient digits
Some tricks of the (floating point) trade
Faithful Bipartite ROM Reciprocal Tables
Foundations of finite precision arithmetic
On Stochastic Rounding with Few Random Bits
Short Division of Long Integers
High-speed double precision computation of nonlinear functions
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata
Floating-point L 2 -approximations to functions
On Lifting-Based Fixed-Point Complex Multiplications and Rotations
Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs
Design for a recursive parallel multiplier
On the efficient implementation of higher radix square root algorithms
Finite precision lexicographic continued fraction number systems
OCAPI: architecture of a VLSI coprocessor for the GCD and the extended GCD of large numbers
Binary paradigm and systolic array implementation for residue arithmetic
Efficient Computation of Multiplicative Inverses for Cryptographic Applications
Efficient Combinational Circuits for Division by Small Integer Constants
Very-high radix combined division and square root with prescaling and selection by rounding
Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator
Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
Algorithms for extracting square roots and cube roots
Programming a vector computer
CORDIC Vectoring with Arbitrary Target Value
Fully Redundant Decimal Arithmetic
Multiple-Precision Evaluation of the Airy Ai Function with Reduced Cancellation
Sign detection in the Symmetric Residue Number System
Extracting low-precision floating-point adders from embedded hard FP DSP Blocks on FPGAs
Multiprecision Division on an 8-bit Processor
On design and performance of VLSI based parallel multiplier
17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA
Random Digit Representation of Integers
Boosting Very-High Radix Division with Prescaling and Selection by Rounding
On-line multiplicative normalization
Experience with a high level language that supports interval arithmetic
An Overview of Floating-Point Support and Math Library on the Intel XScale TM Architecture
Improved Architectures for a Floating-Point Fused Dot Product Unit
Newton-Raphson Integer Division for Area-Constrained Microcontrollers
Case study of a VLSI design project: A simple inner product machine
Code Generators for Mathematical Functions
Enhanced Floating-Point Adder with Full Denormal Support
A comparison of ALU structures for VLSI technology
A bibliography on computer arithmetic
Minimization methods for macrocellular arithmetic networks
SIPE: Small Integer Plus Exponent
Quad Precision Floating Point on the IBM z13
A Design of Radix-2 On-line Division Using LSA Organization
On Improving the Performance Per Area of ASTC with a Multi-output Decoder
Efficient Modular Exponentiation Based on Multiple Multiplications by a Common Operand
Floating Point Architecture Extensions for Optimized Matrix Factorization
The CORDIC Householder algorithm
PAPIA: Pyramidal architecture for parallel image analysis
Energy and Delay Improvement via Decimal Floating Point Units
A unified view of approximate rational arithmetic and rational interpolation
Measuring the accuracy of ROM reciprocal tables
Error-Free Arithmetic for Discrete Wavelet Transforms Using Algebraic Integers
Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2^4)^2 of GF(2^8)
Numerical challenges in long term integrations of the solar system
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension
Analog techniques for residue operations
Big Numbers for a Big Universe
Algorithms for Stochastically Rounded Elementary Arithmetic Operations in IEEE 754 Floating-Point Arithmetic
Contributions to the Design of Residue Number System Architectures
Hardware-Aware Training for Multiplierless Convolutional Neural Networks
Some schemes for fast serial input multipliers
Design and Implementation of an Embedded FPGA Floating Point DSP Block