yusuke1997/dblp-id-title huggingface dataset:
Phase Locked Loop with Ramp Generator for FMCW LiDAR TX in 28-nm CMOS
LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture
Korean Traffic Sign Detection Using Deep Learning
Automorphism Architecture for Bootstrapping Homomorphic Encryption
Asymmetric Charge Transfer Scheme Model in ML-SSHC with Consistent Power Extraction Improvement for Piezoelectric Energy Harvesters
Ultra-Low Power Rectangular Field Programmable Analogue Arrays For Biomedical Applications
Effect of Coupling Strength on Synchronization Phenomena in Chaotic Circuits with Unidirectional Coupling
Low-noise amplifiers with robust ESD protection for RF SOC
A Dynamic Power Transistor-Based CL-LDO with Wide Load Range and -53 dB PSRR Improvement
Wide Dynamic Range Temperature Sensor Using High Sensitivity PTAT Current Generator
Novel pixel calibration circuit for bolometer-type uncooled infrared image sensor
CNN Acceleration based on Dynamic Pruning and FPGAs Implementation
Pavlovian Conditioning Modeling Using Wireless Spiking Neural Network
A Wearable Electrocardiogram Monitoring System Robust to Motion Artifacts
Machine Learning for Indoor Localization using CSI Technique
Low-Complexity Phase Shift Design for IRS-Aided SU-MIMO Wireless Systems
Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system
A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators
Function-Level Module Sharing in High-Level Synthesis
Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology
A design of rectifier for 13.56MHz wireless power transfer receiver with all digital delay-locked loop
A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic
Effect of Random Modulation Switching Schemes on Harmonics and CE Levels of a Buck Converter
Mapping table-based fisheye image correction for low computational complexity
Nighttime image enhancement applying dark channel prior to raw data from camera
An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC Applications
Study on Crest Factor Controlled Multi-Tone Signal for Analog RF Circuit Testing
ECG Heartbeat Classification Using a Single Layer LSTM Model
Design of 66.5dB IRR Baseband Analog with Filter Tuning
Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM
Real-time digital image stabilization using motion sensors for search range reduction
Scalable deep neural network accelerator cores with cubic integration using through chip interface
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology
A High-Efficiency High-Data-Rate Wireless Power and Data Transfer IC Using Orthogonal Codes for Miniatureized Multi-Channel Neural Interface Systems
Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion
A fast-locking clock multiplying DLL
Adaptive frequency-controlled ultra-fast hysteretic buck converter for portable devices
Energy-efficient spread second capacitor capacitive-DAC for SAR ADCs
Solving Traveling Salesman Problems Using Ising Models with Simulated Bifurcation
Spur suppression in frequency synthesizer using switched capacitor array
Practical and efficient SOC verification flow by reusing IP testcase and testbench
Hardware feasible offset and gain error correction for time-interleaved ADC
Pitch-Shift Effects of an Ergodic Sequential Logic Nonlinear Cochlear Model Induced by Three Tones
A low leakage retention LDO and leakage-based BGR with 120nA quiescent current
An efficient FPGA implementation for odd-even sort based KNN algorithm using OpenCL
Isolation performance of sub-harmonic Gilbert mixers
Temperature Sensor with 292.3 nA/°C Sensitivity Using Double Current Subtraction
A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting Applications
A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations
Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture
Synchronization Phenomena in Coupled van der Pol Oscillators with Memristor Couplings as Ladder Structure
A Layer-wise Training and Pruning Method for Memory Efficient On-chip Learning Hardware
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM
Customized SRAM design for low power video code applications
High Speed, Approximate Arithmetic Based Convolutional Neural Network Accelerator
Study on Intel CPU-FPGA Architecture : Security Perspective
Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing
A Design of Charge Pump for Low Noise Phase-Locked Loops using Clock Quadrature
3D 2 processing architecture - High reliability and low power computing for novel nano tactile sensor array
Convolutional Neural Network-based Jaywalking Data Generation and Classification
Minimizing MOSFET power losses in near-field electromagnetic energy-harnessing ICs
A Low-Power Gesture Recognition System utilizing Hybrid Tiny Classifiers
FPGA implementation of stereoscopic image proceesing architecture base on the gray-scale projection
Efficient program control schemes for Motion Estimation specific processor
Advanded Design Verification and Debugging Techniques Based on Optical Fault Isolation Method
Evaluations of Electronic Neuron Model for Low Power VLSI Implementation
Implementation of Integrating a High Resolution Time-to-Digital Converter with an Embedded Processor System on Low-Cost FPGA
High Bandwidth Efficiency FPGA-based Underwater Acoustic Transceiver with Adaptive-SFDR DDFS
SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration
Software design for GUI display in the wearable device
Exploring GEMM Operations on Different Configurations of the Gemmini Accelerator
A Three-Level Boost Converter With Peak Current Mode Control for Flying Capacitor Self-Balancing
Design of power-efficient class-D CMOS power amplifier with resistor feedback
Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)
A Real-time Tracking Algorithm for Human Following Mobile Robot
Components Analysis on Audio Signal Mixtures
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees
High DC gain and wide output swing class-C inverter
Dataflow and Hardware Design for The Sharing of Feature Maps
Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications
Comparative Study of Nonlinear Dynamics in DC-DC Converter with TEM
Batteryless DC-DC Boost Converter for Thermoelectric Energy Harvesting Devices
State of Charge Estimation for Lithium-Ion Batteries Based on Informer-LSTM Hybrid Network
An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration
Miniaturization of bandwidth extension circuit for ESD I/O pad using bridged T-coil
Reduction of Processing Time for Wireless Spiking Neural Network Using Wireless Communication Devices for IoT
A new approach to binarizing neural networks
Reduced power consumption Current-mode ADC using SAR logic for AI application
A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond
Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks
A Digitally Controlled Analog kernel for Convolutional Neural Networks
A 4.86 µW/Channel Fully Differential Multi-Channel Neural Recording System
Simple Reference Voltage Generation Circuit Insensitive to Temperature
Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation
FPGA Design Duplication based on the Bitstream Extraction
Clock design techniques considering circuit reliability
Noise Tolerance of an Energy-Scalable Deep Learning Model with Two Extreme Bit-Precisions
Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance
CAN Data Compression Based on Sorting and Mapping Method
A digitally enhanced low-distortion delta-sigma modulator for wideband application
A 1.2 GHz Bandwidth Baseband Analog Circuit in 65nm CMOS for Millimeter-Wave Radio
Optimizing the Performance of a Low Power - Area Efficient OTA Design that is Based on Hybrid Current Shunting Technique
Design of Two Template Cellular Neural Networks for Color Image Processing
Toward Heterogeneous Virtual Platforms For Early SW Development
Application-specific Instruction-Set Processor design methodology for wireless image transmission systems
FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI
A programmable delay-locked loop based clock multiplier
Memory efficient decoder design of nonbinary LDPC codes
A High Speed OOK Modulator at 300 GHz using LO Cancellation Technique
Transmitter antennas for wireless capsule endoscopy
On-Chip Memory Optimization of High Efficiency Accelerator for Deep Convolutional Neural Networks
Design of a 12-b asynchronous SAR CMOS ADC
Exploring Trustable Paths in Network-on-Chip for Low-Slack Packets
Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logic
An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction
An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels
Design of Energy Harvesting System with Piezoelectric Device for Onetime-High-Energy Applications
Resource Utilization Optimized Design Method for Matched Filter of PSS Searcher
System-on-Chip iot for Smart Poultry Manufacturing
Latency-Insensitive Controller for Convolutional Neural Network Accelerators
Single-flux-quantum cache memory architecture
A high-speed, low-offset and low-power differential comparator for analog to digital converters
CAN FD controller for in-vehicle system
Neuromorphic Properties of Memristor towards Artificial Intelligence
Halo effect suppression for single image haze removal method
Impact of processor cache memory on storage performance
Bioinspired Solution-processed Artificial Synaptic Thin-Film Transistor
A design approach of a Parametric Measurement Unit on to a 600MHz DCL
A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices
Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip
Hybrid loopfilter sigma-delta modulator with NTF zero compensation
Discussion of cost-effective redundancy architectures
Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC
Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing
A Gain Boosted Single-Ended 300 GHz InP HBT Oscillator for Terahertz Applications
Low-cost concurrent error detection schemes for logarithmic converters
A design of NFC analog front-end with the frequency selector
A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications
Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes
A newton raphson method based approximate divider design for color quantization application
Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations
Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design
Multi-Mode LSTM Network for Energy-Efficient Speech Recognition
Scheduling of Rigid Tasks on Heterogeneous Multicores
A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits
Process variation-aware bridge fault analysis
An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips
1-kS/s 12-bit SAR ADC with Burst Conversion
Inductor-less CMOS TIA Based on MSTA for Low-power and Low-noise Optical Communication
A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors
A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications
Physical hierarchy exploration of 3D processors
A Wideband Distributed Demodulator at 100 GHz
Simplified Real-time Categorized Vehicle Counting and Speed Estimation
Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme
Radar Based Real-Time Fall Detection System with Low Power Consumption
Efficient Reed-Solomon based LDPC decoders
A 10.12μW 101.98dB-SNDR Three-step Incremental Analog-to-Digital Converter
A Configurable Linear PA Ramp Controller for DSRC Applications in 130 nm CMOS Technology
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier
A low-offset, low-noise, fully differential receiver with a differential signaling method for fingerprint mutual capacitive touch screen
Design of Wafer Vision Alignment System using Hardware Simulator
A K-band VCO-based Impulse Generator for UWB Radar Sensors
Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture
Botnet Classification using Machine Learning
A Simple Circuit Model for PWM-1-Controlled DC-DC Converter and Its Analysis
Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY Receiver
Low Complexity License Plate Recognition System
High-performance and energy-efficient approximate multiplier for error-tolerant applications
A Biopotential Amplifier IC with Active Common-Mode Cancellation for Closed-Loop Neural Interfaces
A highly integrated IR-UWB transceiver for communication and localization
Energy-Efficient AI at the edge for Biomedical Applications
A new stochastic mutiplier for deep neural networks
FACTGen: Framework for Automated Circuit Topology Generator
A hardware-efficient sequential logic biochemical switch model toward biosystem simulator
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration
Resource-efficient FPGA architecture of Canny edge detector
On Reconfiguring Memory-Centric AI Edge Devices for CIM
Delay Impact on Process Variation of Interconnect throughout technology scaling
Effect of Lateral Connection on Synchronization Phenomena in Chaotic Circuits Coupled with Non-Uniform Coupling Strength
Estimating the Angle of Arrival from Multiple RF Sources using Phase Interferometry
An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme
A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems
TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search
Experimental Assessment of 1D-DCT Based Display Field Communication Scheme
Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS
An electrical chromatic dispersion emulator using digital signal processing
Data Gathering and Application to Building Energy Optimization with Sensitivity Analysis for IoT Applications
Operation and Stability Analysis of Temperature-Insensitive MOS Reference Current Source with Self-Bias Circuit
Timing Analysis with Analytical Sensitivity
A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers
Area Efficient Multi-Threshold Null Convenction Logic
Unpredictable 16 bits LFSR-based true random number generator
Impact of Variability Issues of Resistive Memory Synapses on Pattern Recognition Systems
An Integrator Time-Constant Calibration Scheme with Modified Voltage to Digital Converter
LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System
Improved nonlocal means denoising for images with tone gradients
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1 st speculative tap
Phase-Locked Loop-Based Nanoresonator Integrated Circuit for Motional Resistance Sensing with Automatic Gain Control
A lightweight metric for the evaluation of network congestion in NoC-based MPSoC
An efficient on-chip network with packet compression capability
On-chip epilepsy detection: Where machine learning meets patient-specific healthcare
Efficient Cardiovascular Disease Diagnosis System for an Wearable Device based on Multi Stage BCResNet
High energy efficient ultra-low voltage SRAM design: Device, circuit, and architecture
A Fast Full-System Simulation Environment for Memory System Evaluation
A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs
Unseen Named Entity Recognition for Thai Language
High-Speed FPGA-to-FPGA Interface for a Multi-Chip CNN Accelerator
An address remapping algorithm to reduce power consumption in NoC-based chip-multiprocessors
A Low Noise MEMS Based CMOS Resonator Using Magnetoelectric Sensor
Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices
Compact Inductor-less CMOS PAM4 VCSEL Driver for High-speed Optical Communications
Adaptive Mode-Switching for Write-amplification Reduction of SMR Disks
RF-DC Converter Using Loss Compensation and Adaptive Matching Network
Digital image preprocessing and hair artifact removal by using Gabor wavelet
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine
A High-Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting
MHC : Multi-flit HBM Crossbar with Enhancing Performance and Resource Utilization
A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems
Confidence Score based Mini-batch Skipping for CNN Training on Mini-batch Training Environment
Implementation of deep learning neural network for real-time object recognition in OpenCL framework
Nano-second scale dynamic voltage scaler based on charge-pump and BW-DAC
Analysis and Design of Phase-Controlled Class-D ZVS Inverter
Design of an area-efficient hardware filter for embedded system
Intrinsic Capacitance based Multi bit Computing in Memory
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks
Dynamic power estimation for ROM-less DDFS designs using switching activity analysis
Flipping Rectifiers for Piezoelectric Vibration Energy Harvesting
A 2.5-12.3 Gb/s continuous-rate referenceless CDR with counter-based unlimited frequency detection
An efficient built-in self-repair scheme for area reduction
A dimmable and power-compensated AC direct LED driver with high efficiency
A low voltage capacitor based current controlled sense amplifier for input offset compensation
A Novel Area Efficient Approximate Stochastic Computing Approach for Edge Devices
A LoRaWAN Enabled Sensor-Based System for Detecting Rodent Activity
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique
Bayesian Optimization for Parameter Tuning in Placement-Aware Logic Synthesis
Continuous-time Delta-Sigma Modulators: Single-loop versus MASH
A 28.4 nV/√Hz Chopper Stabilized Current Feedback Instrumentation Amplifier with Auto Offset Calibration DAC for Resistive Bridge Sensor
An on-chip hot pixel identification and correction approach in CMOS imagers
Aspect enhanced functional coverage driven verification in the SystemC HDVL
FPGA-based Scalable Road Image Stochastic Denosing Approach
CTT-based Non-Volatile Deep Neural Network Accelerator Design
Optimal Efficiency True Random Number Generator with Discrete-time Chaos for Low-Cost Applications
Prediction-based latency compensation technique for head mounted display
Temperature Compensation on SRAM-Based Computation in Memory Array
Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed
Impact of Oscillator Phase Noise on Time-Domain SNN Performance
Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications
Time Series Analysis with Noise-Mixing Effects Using Neural Networks
Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops
Trust-minimized Integration of Third-Party Intellectual Property Cores
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application
Strategic Improvements in CNN Accelerators: Optimizing PE Utilization for MobileNetV2
A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology
Fast Prototyping of a Deep Neural Network on an FPGA
Clusteling Methods Using Synchronization of Chaotic Circuit Networks
A Voting Phase Detector Design with Mitigated Process Variation
A chopper-type mixed gait controller based on ergodic cellular automaton central pattern generator
A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler
Wireless power transfer to stacked modules for IoT sensor nodes
High Accuracy Abnormal ECG Detection Chip Using a Simple Neural Network
Electrical performance analysis of biogas fuelled generator with purifier
A Programmable Gain Amplifier with Fast Transient Response for Medical Ultrasound System
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU
A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore
Compact implementation IIR filter in FPGA for noise reduction of sensor signal
CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength
HMD-based virtual multi-screen control system and its gesture interface
True Random Number Generator Using Bio-related Signals in Wearable Devices
Scheduling with Variable-Cycle Approximate Functional Units in High-Level Synthesis
PROG: Per-Row Output Generator for BOST
Memcapacitor based Minimum and Maximum Gate Design
Synchronization Phenomena of Two Coupled Chaotic Circuits Using Stochastic Coupling
Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder
Study on Reservoir Computing Combining Chaotic Circuits and Periodic Oscillators
Human Visual Attention Analysis-based Image Segmentation using Color Histogram
A low power reconfigurable SAR ADC for CMOS MEMS sensor
Advancements in Metal Passivation Process for Low-Temperature Cu-Cu Direct Bonding
A design of new voltage to current converter with high linearity and wide tuning
A bandgap reference with low TC of 1.363ppm/°C across wide temperature range for PMICs
An All-Digital Standard-Cell-Based Resistive-Sensing Display Panel/Chip Crack Detector
Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN
Power-efficient partially-adaptive routing in on-chip mesh networks
Software-based embedded core test using multi-polynomial for test data reduction
Distortion analysis for a DC-DC buck converter
Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA
Fast Estimation of NTT/INTT Accelerator Costs for RNS-Based Homomorphic Encryption
Refinement of depth maps generated by low-cost depth sensors
Crosstalk-Based Hardware Trojan In Low Power Designs
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter
All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface
Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators
An Im2col Architecture Using The Benes Network For Deep Learning Hardware Accelerators
Skew control methodology for useful-skew implementation
A low power CMOS receiver front-end for long term evolution systems
Design of 28GHz CMOS phased array T/R circuits for 3-dimensional beamforming applications
Low-Power Frequency-Mode Temperature Sensing Circuit with Subthreshold Operational Amplifier
Stochastic Circuit Design of Image Contrast Stretching
Multi-point search method for system identification based on chaotic dynamics
A low-complexity bio-medical signal receiver for wireless body area network
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
Implementation of AI characteristic motion detecting for improper-photography prevention system
Mask-Soft Filter Pruning for Lightweight CNN Inference
A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links
Embedded system-on-chip design of atrial fibrillation classifier
Sensitivity improvement in FSI CIS using the M1ToP™ smart process technique
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS