yusuke1997/dblp-id-title huggingface dataset:
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS
Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering
An 80-117V Pseudo-Adiabatic Drive Circuit for Microrobotic Actuators with Optical Power Delivery and Peak Power Reduction Factor over 14×
Short to Medium-Reach Wireline Transceivers Using Single-Ended Signaling, Clock Forwarding, and Spatial Encoding for Die-to-Die Applications
A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation
Synchronous Die-to-Die Signaling Using Aeonic Connect
Session 18 - Data converter techniques
A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes
A 24.4μW Room Temperature Gas Sensor Based on Molecularly Imprinted Polymers Demonstrating SARS-Cov-2 and D-Glucose Aerosol Sensing
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration
Session 3 - Clocking techniques
CMOS field-modulated color sensor
An integrated MESFET voltage follower LDO for high power and PSR RF and analog applications
A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities
A PN-acquisition ASIC for wireless CDMA systems
Digital phase-locked loops
A 550μm 2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuracies
Converting an SRAM from bulk Si to partially depleted SOI
A continuous-time hierarchical field programmable analogue array
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000
Utilizing surplus timing for power reduction
Platform IC with embedded via programmable logic for fast customization
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications
A 0.015mm 2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction
Modeling, design and optimization of hybrid electromagnetic and piezoelectric MEMS energy scavengers
Video-rate D/A converter using reduced rate sigma-delta modulation
A 13.1mm 2 512 × 256 Multimodal CMOS Array for Spatiochemical Imaging of Bacterial Biofilms
A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR
Reducing switching activity on datapath buses with control-signal gating
Mixed-Order Correlated Dual-loop Sturdy MASH CT ΔΣ Modulator with Distributed Signal Feed-in and VCO based Quantizer
A Si/SiGe HBT timing generator IC for high-bandwidth impulse radio applications
1.5-GHz CMOS voltage-controlled oscillator based on thickness-field-excited piezoelectric AlN contour-mode MEMS resonators
The highly integrated mobile WiMAX module using embedded PCB & SIP technology
The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver
Cascaded noise-shaping modulators for oversampled data conversion
A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation
A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance
An 8-channel 2.1 μ W0.017 mm 2 0.04% Gain Mismatch Bio-potential Recording AFE using Group-Chopping Technique
A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers
A 53 GHz DCO for mm-wave WPAN
A locally-clocked dynamic logic serial/parallel multiplier
Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter
A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999
A 120 MHz, 12 mW CMOS current feedback opamp
Miniaturized energy-harvesting piezoelectric chargers
System-on-chip (SoC) requires IC and package co-design and co-verification
A 1.2V, 10MHz, low-pass Gm-C filter with Gm-cells based on triode-biased MOS and passive resistor in 0.13μm CMOS technology
A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification
Intermodulation analysis of mixer circuits based on frequency domain relaxation method
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing
A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE
An area- and power-efficient monolithic Buck converter with fast transient response
A107 µW MedRadio Injection-Locked Clock Multiplier with a CTAT-biased 126 ppm/°C Ring Oscillator
A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS
A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR
Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T
A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-μm CMOS process
A fully synthesizable parameterized Viterbi decoder
Design and implementation of a 1024-point pipeline FFT processor
Radio receiver techniques
Integrated 155M-10Gbps Framer with 22.5Gbps Low/High Order Cross Connect SoC
A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction
A 28-GHz 189.2-dBc/Hz FoM 360° Phase-Shifting Quadrature Oscillator Without Phase Ambiguity Achieving 0.13° RMS Phase Error Under 2° Phase Resolution
A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applications
ISPI: A 2-Wire Improved Serial Peripheral Interface with Automatic Routing Algorithm for 2-D In-Textile Distributed Computing and Storage Systems
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET
An 11.1nJ-Start-up 16/20MHz Crystal Oscillator with Multi-Path Feedforward Negative Resistance Boosting and Optional Dynamic Pulse Width Injection
A mm-wave power harvesting RFID tag in 90nm CMOS
Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth
A Verilog piecewise-linear analog behavior model for mixed-signal validation
Will BiCMOS stay competitive for mmW applications ?
Another Inconvenient Truth: Snails Are More Intelligent Than Us
Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions
CIFER: A 12nm, 16mm 2 , 22-Core SoC with a 1541 LUT6/mm 2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA
An energy harvesting 2×2 60GHz transceiver with scalable data rate of 38-to-2450Mb/s for near range communication
Modeling and synthesis of wide-band switched-resonators for VCOs
CMOS millimeter wave phase shifter based on tunable transmission lines
A non-coherent versatile DPSK receiver for high channel-density neural prosthesis
The Superchip: Innovative teaching of IC design and manufacture
A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology
Estimation of average switching power under accurate modeling of signal correlations
A 65 nm 2.02 mW 50 Mbps Direct Analog to MJPEG Converter for Video Sensor Nodes using low-noise Switched Capacitor MAC-Quantizer with automatic calibration and Sparsity-aware ADC
A 45.6-GHz matrix distributed amplifier in 0.18-nm CMOS
Integrated VCO Design for MICS Transceivers
An 87.2%-peak efficiency 4.1 W-output power switchedcapacitor 3-level inverting buck-boost dc-dc converter
A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection
A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET
An Up-to-70-V Output Hybrid Boost Converter with Halved Voltage Stress Achieving 7-W Output Power and 73.8% Peak Efficiency at CR of 14
A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D converters
Distributed Microscale Brain Implants with Wireless Power Transfer and Mbps Bi-directional Networked Communications
22-nm fully-depleted tri-gate CMOS transistors
A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]
Interconnect and package design of a heterogeneous stacked-silicon FPGA
A 2-in-1 Temperature and Humidity Sensor Achieving 62 fJ·K 2 and 0.83 pJ·(%RH) 2
A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor
High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS
Practical timing analysis of asynchronous circuits using time separation of events
Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability
A Large-Scale Reconfigurable Analog Signal Processor (RASP) IC
An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique
A high OIP3 quadrature mixer using cross-coupled transconductor
Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology
In Situ Evaluation Method for On-Chip Inductors Using Oscillator Response
Digital Signal Processing for RF at 45-nm CMOS and Beyond
Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations
Multi-dimensional model reduction of VLSI interconnects
A model-agnostic technique for simulating per-element distortion contributions
A Wearable Backscatter System Featuring Concurrent RF Harvesting and Bidirectional Communication with Commodity BLE Transceivers
An ultra-low power power management unit with -40dB switching-noise-suppression for a 3×3 thermoelectric generator array with 57% maximum end-to-end efficiency
A deep sub-micron timing measurement circuit using a single-stage Vernier delay line
A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation
A 16-bit Incremental ADC Enabled by An Efficient Shooting Integrator with Inherent Noise Reduction
Demonstration of Fast OTA Chirp-Based Beam Training Using Analog TTD Array with Millimeter Wave Testbed for Applications in Radar Systems
A 100kb/s, 4 GHz, 267 μW fully integrated low power FM-UWB transceiver with multiple channels
Millimeter-wave ICs
Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them
Robust ultra-low voltage ROM design
CMOS-based flexible multi-site retinal stimulator toward retinal prosthesis technology
Integrated circuits for 3GPP mobile wireless systems
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET
A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer
A customized design of DRAM controller for on-chip 3D DRAM stacking
The Backward-traversing Relaxation Algorithm for Circuit Simulation
A Compact Wideband Joint Bidirectional Class-G Digital Doherty Switched-Capacitor Transmitter and N-Path Quadrature Receiver through Capacitor Bank Sharing
SAR ADCs in parallel [time-interleaved] converter arrays
Silicon photonics for on-chip interconnections
A 90nm power optimization methodology and its' application to the ARM 1136SF-S microprocessor
D-band CMOS transmitter and receiver for multi-giga-bit/sec wireless data link
A Battery-Connected Inductor-First Flying Capacitor Multilevel Converter Achieving 0.77W/mm 2 and 97.1% Peak Efficiency
A 65nm CMOS current controlled oscillator with high tuning linearity for wideband polar modulation
A Pseudo-Adiabatic Switched-Capacitor Gate Driver for Si and GaN FETs Achieving >5x Power Reduction
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop
Unified non-quasi-static MOSFET model for large-signal and small-signal simulations
Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges
Capacitive proximity communication with distributed alignment sensing for origami biomedical implants
A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications
A breakdown voltage doubler for high voltage swing drivers
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS
mmWave LO distribution insights
Frequency Synthesizers
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
Using cache to reduce power in content-addressable memories (CAMs)
A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters
A 0.9 V, 0.51 μA rail-to-rail CMOS operational amplifier
A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming
On-chip Digitally Tunable High Voltage Generator for Electrostatic Control of Micromechanical Devices
A 0.5V supply, 49nW band-gap reference and crystal oscillator in 40nm CMOS
Non-destructive IC defect localization using optical beam-based imaging
Vibrating RF MEMS for next generation wireless applications
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications
A single-chip universal burst receiver for cable modem/digital cable-TV applications
Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques
A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS
A Fully Integrated DC/DC Converter for Tunable RF Filters
Merging hardware and software: intellectual property cores for Internet applications
Field programmable SONOS ESD protection design
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices
A stackable switched-capacitor DC/DC converter IC for LED drivers with 90% efficiency
A 2.3Gb/s fully integrated and synthesizable AES Rijndael core
An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation
Reconfigurable logic in SoC systems
A high-PSR LDO using a feedforward supply-noise cancellation technique
An 8.5-11 GHz CMOS Transmitter with >19 dBm OP1dB and 24 % Efficiency
A Monolithic 3-Level Single-Inductor Multiple-Output Buck Converter with State-Based Non-Linear Control Capable of Handling 1A/1.5ns Transient with On-Die LC
A 0.2-V 10-bit 5-kHz SAR ADC with Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition
A 44V Driver Array for Ultrasonic Haptic Feedback in Display Compatible Thin-Film Low Temperature Poly-Silicon
A SOI-BiCMOS 800 Mbps write driver for hard disk drives
A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing
A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA
A 1 V, 1 mW, 434 MHz FSK receiver fully integrated in a standard digital CMOS process
A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array
Quantum Technology Overview
Wireline clocking and equalization
A 65nm 21.9pJ/Sa Pixel to PWM Conversion SoC with Time-domain Body Communication for ULP Body-Worn Video Sensor Nodes with Distributed Real-Time Inference
Session 20 - High-performance low-power wireless receivers
A direct conversion receiver for the 3G WCDMA standard
Timing qualification of a 0.25-μm CMOS ASIC library using BSIM3 FET models
GSM DAC with new segmented mismatch shaping technique
Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards
A Timing-Robust 10b 13GS/s ADC with Analog Fourier Transform Based Frequency Interleaving
A 1mJ/frame unified media application processor with a 179.7pJ mixed-mode feature extraction engine for embedded 3D-media contents processing
Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications
A 0.65mW 20MHz 5 th -order low-pass filter with +28.8dBm IIP3 using source follower coupling
Nested feed-forward Gm-stage and ing resistor plus nested-Miller compensation for multistage amplifiers
Thermal diffusivity sensing: A new temperature sensing paradigm
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS
Balanced Low Noise High Dynamic Photodiode Interface for Automotive
A CMOS 228-324GHz RF Domain Quadrature Receiver with a Broadband Harmonic-Enhanced LO Generator
Efficient generation of 1/f α noise using a multi-rate filter bank
A digital DFT technique for verifying the static performance of A/D converters
A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS
ASIC Design and Verification in an FPGA Environment
A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics
D-Band Dicke Switch Based Passive Imager with 0.13K NETD in 28nm CMOS Technology
Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path
A CMOS Image Sensor for DNA Microarrays
A voltage scalable 0.26V, 64kb 8T SRAM with Vmin lowering techniques and deep sleep mode
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation
Behavioral modeling for timing, noise, and signal integrity analysis
A voice processing and control module for cable telephony applications
Variation and analog modeling
A Transient-Enhanced 20μA-Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation
A digital clock and data recovery architecture for multi-gigabit/s binary links
Technology trends and challenges for CMOS/system LSIs for the next 10-15 years
A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors
A 65nm and 130nm CMOS Programmable Analog Standard Cell Library for Scalable System Synthesis
High-Speed Optical Links
A CMOS g m -C IF filter for Bluetooth
Reconfigurable SDR front-end techniques
A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]
Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders
A 1.8 V pseudo-differential switched-capacitor amplifier
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
EDA Challenges in Nano-scale Technology
Equalizer design and performance trade-offs in ADC-based serial links
An EEPROM Programming Controller for Passive UHF RFID Transponders with Gated Clock Regulation Loop and Current Surge Control
A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppression
A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking
Session 3 - Power management
A 1.8 V ΔΣ modulator interface for electret microphone with on-chip reference
A 7GHz ERBW 1.1GS/s 6-bit PVT Tolerant Asynchronous CI-SAR with only 8.5fF Input Capacitance
Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs
Advanced Sensing Systems Exploiting the Integration of Flexible and Large-Area TFTs with Si-CMOS Technology
Energy-efficient bridge-to-digital converters
A fully integrated 28nm CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mv startup voltage
An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator
A new approach to fully integrated CMOS LC-oscillators with a very large tuning range
Hardware for machine learning: Challenges and opportunities
An (8158, 7136) low-density parity-check encoder
An energy-recycling (ER) technique for field color sequential LCD backlight driving
A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCO
BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of -247.9dB at 3GHz with a Ring Oscillator
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC TM microprocessor
A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS
A 900 MHz, 0.9 V low-power CMOS downconversion mixer
Techniques for in-band phase noise suppression in re-circulating DLLs
A 3.5mW 900MHz Down-converter with Multiband Feedback and Device Transconductance Reuse
Session 5 - Memory for emerging applications
Addressing link-level design tradeoffs for integrated photonic interconnects
A 1.8V Input, 96.5% Efficiency, 4.05A/mm 2 FoM, Three-Level Dual-Path Hybrid Buck Converter with Mitigated Capacitive Inrush Current and Seamless DVS Across a Wide 0.4-to-1.5V Output Range
Comparative Studies of Common Control Schemes for Reference Tracking and Application of End-point Prediction
RF transmitter architectures and circuits
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC
HTOL SRAM Vmin shift considerations in scaled HKMG technologies
65-nm CMOS, W-Band Receivers for Imaging Applications
A novel audio playback chip using digitally driven speaker architecture with 80%@-10dBFS power efficiency, 5.5W@3.3V supply and 100dB SNR
Design challenges for prototypical and emerging memory concepts relying on resistance switching
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC
Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS
On-package decoupling optimization with package macromodels
Signal Processing Architectures for Low-Noise High-Resolution CMOS Image Sensors
A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter
Polar modulator for multi-mode cell phones
Inter-die signaling in three dimensional integrated circuits
82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction
SAW-less software-defined radio transceivers in 40nm CMOS
Analysis of digital bang-bang clock and data recovery for multi-gigabit/s serial transceivers
Transforming small-signal modeling into control system modeling
Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique
A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters
A Single-Channel RF-to-Bits 36Gbps 8PSK RX with Direct Demodulation in RF Domain
A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS
Inverting buck-boost DC-DC converter for mobile AMOLED display with real-time self-tuned minimum power-loss tracking scheme
A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation
A FPGA vernier digital-to-time converter with 3.56ps resolution and -0.23∼+0.2LSB inaccuracy
A partitioned wavelet-based approach for image compression using FPGA's
Hybrid transformer-based tunable integrated duplexer with antenna impedance tracking loop
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range
Timing inaccuracy of clocks
A dither-less all digital PLL for cellular transmitters
A 1 V, 25 μW speech recognizer for portable systems
A Low Power Carbon Nanotube Chemical Sensor System