yusuke1997/dblp-id-title huggingface dataset:
A Fast FPGA (FFPGA) Using Active Interconnect (Abstract)
Hierarchical Placement Directives for Parametric IP Blocks
Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation
Hierarchical library-based power estimator for versatile FPGAs (abstract only)
HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform
High-Performance FPGA Network Switch Architecture
LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs
BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only)
Universal Logic Modules for Series-Parallel Functions
FPGA-Targeted Development System for Embedded Applications
Application-specific customization of soft processor microarchitecture
A FPGA prototype design emphasis on low power technique
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009
A Survey of CORDIC Algorithms for FPGA Based Computers
On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture
Single-Batch CNN Training using Block Minifloats on FPGAs
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only)
A 475 MHz Manycore FPGA Accelerator for RTL Simulation
Reconfigurable target recognition system (poster abstract)
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping
Efficient packet classification for network intrusion detection using FPGA
Towards Accelerator Customization in Real-time Safety-critical Systems
Enhancements in UltraScale CLB Architecture
AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only)
Challenges in CAD for the One Million Gate FPGA
Unlocking FPGAs Using High Level Synthesis Compiler Technologies
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
FPGA-based Distributed Edge Training of SVM
A novel FPGA logic block for improved arithmetic performance
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs
Temporal Thermal Covert Channels in Cloud FPGAs
Architecture Considerations for Mixed Signals FPGAs
Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only)
Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only)
Application-dependent testing of FPGAs for bridging faults
The case for registered routing switches in field programmable gate arrays
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
A high-performance FPGA architecture for restricted boltzmann machines
MATCHUP: Memory Abstractions for Heap Manipulating Programs
Application specific processor with high level synthesized instructions (abstract only)
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Self-Organizing Kohonen Maps for FPL Placement
Implementation of IEEE Single-Precision Floating-Point Operations on FPGAs (Abstract)
Simultaneous logic decomposition with technology mapping in FPGA designs
DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only)
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Revisiting bitwidth optimizations
Modular multi-ported SRAM-based memories
Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis
A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs
Track placement: orchestrating routing structures to maximize routability
Interactive Debugging at IP Block Interfaces in FPGAs
ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only)
A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only)
200 MS/s ADC implemented in a FPGA employing TDCs
A Novel Coefficient Address Generation Algorithm for Split-Radix FFT (Abstract Only)
Dynamic hardware multiplexing for coarse grain reconfigurable architectures
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only)
CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers
An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only)
Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture
A novel full coverage test method for CLBs in FPGA (abstract only)
An FPGA based parallel architecture for music melody matching
FPGA power reduction by guarded evaluation
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)
An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions
Towards Adaptable Hierarchical Placement for FPGAs
Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only)
A physical retiming algorithm for field programmable gate arrays
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores
FPGA-based supercomputing: an implementation for molecular dynamics
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
Lithographic aerial image simulation with FPGA-based hardwareacceleration
An OpenCL™ Deep Learning Accelerator on Arria 10
CSAIL2019 Crypto-Puzzle Solver Architecture
Fast Compilation for Pipelined Reconfigurable Fabrics
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006
Sequencing Run-Time Reconfigured Hardware with Software
Flat FPGA Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with Optimizations and Enhancements
Coarse-grained carry architecture for FPGA (poster abstract)
A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)
Implementation of a genetic algorithm on a virtex-ii pro FPGA
Performance-constrained pipelining of software loops onto reconfigurable hardware
FPGA-based implementation of single-precision exponential unit
Near-memory Acceleration for Scalable Phylogenetic Inference
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only)
Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks
Real-time, frame-rate face detection on a configurable hardware system (poster abstract)
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling
FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers
RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs
FCache: a system for cache coherent processing on FPGAs
Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only)
Synchronization Constraints for Interconnect Synthesis
A quantitative analysis of the speedup factors of FPGAs over processors
Top-down Physical Design of Soft Embedded FPGA Fabrics
F5-HD: Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional Computing
A programmable majority logic array using molecular scale electronics
A modular NFA architecture for regular expression matching
A 2005 review of FPGA arithmetic (abstract only)
Automated synthesis for asynchronous FPGAs
Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator
Automatic bus macro placement for partially reconfigurable FPGA designs
Performance-driven mapping for CPLD architectures
SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function
An FPGA implementation and performance evaluation of the Serpent block cipher
Configuration compression for FPGA-based embedded systems
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997
A Fractal Astronomical Correlator Based on FPGA Cluster with Scalability
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only)
A soft error vulnerability analysis framework for Xilinx FPGAs
Buffer Placement and Sizing for High-Performance Dataflow Circuits
Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only)
Formal Verification ATPG Search Engine Emulator (Abstract Only)
Impact and compensation of correlated process variation on ring oscillator based puf
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems
CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures
Fine-grained island style architecture for molecular electronic devices
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs
Accelerator compiler for the VENICE vector processor
FPGA Routing and Routability Estimation via Boolean Satisfiability
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017
A framework for rule processing in reconfigurable network systems (abstract only)
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only)
Designing hardware with dynamic memory abstraction
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)
Synthesized Garbage Collection for FPGA Accelerators
Regularity Matters: Designing Practical FPGA Switch-Blocks
Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators
FPL Based Self-Test with Deterministic Test Patterns
Highly pipelined asynchronous FPGAs
Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network
An SBus Monitor Board
Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only)
Optimality study of logic synthesis for LUT-based FPGAs
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing
Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures
Improved double angle complex rotation QRD-RLS
An FPGA-based transient error simulator for evaluating resilient system designs (abstract only)
Variation-aware routing for FPGAs
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
Streaming implementation of a sequential decompression algorithm on an FPGA
FreezeTime: Towards System Emulation through Architectural Virtualization
Reconfigurable computing for learning Bayesian networks
Combining multicore and reconfigurable instruction set extensions
FPMR: MapReduce framework on FPGA
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware
Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract)
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)
The RLOC is dead - long live the RLOC
An estimation and exploration methodology from system-level specifications: application to FPGAs
A routing fabric for monolithically stacked 3D-FPGA
An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)
FPGA implementation of neighborhood-of-four cellular automata random number generators
Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier
High Speed Calculation of Cyclic Redundancy Codes
GlitchLess: an active glitch minimization technique for FPGAs
Using reconfigurability to achieve real-time profiling for hardware/software codesign
Design of FPGA interconnect for multilevel metalization
Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals
Sparse Winograd Convolutional Neural Networks on Small-scale Systolic Arrays
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays
Using Architectural "Families" to Increase FPGA Speed and Density
FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method
Architectural Enhancements in Intel® Agilex™ FPGAs
An LPGA with Foldable PLA-style Logic Blocks
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only)
Software Hardware Co-Optimized BFS on FPGAs
A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract)
An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA
FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only)
Improved delay measurement method in FPGA based on transition probability
An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only)
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs
Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks
FPGA-2010 pre-conference workshop on open-source for FPGA
An adaptive Reed-Solomon errors-and-erasures decoder
A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis
A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA
Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption
Modeling FPGA-Based Systems via Few-Shot Learning
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs
Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis
Hardware co-simulation in system generator of the AES-128 encryption algorithm
Efficient Acceleration of CNNs for Semantic Segmentation on FPGAs
FPGA-Accelerated Transactional Execution of Graph Workloads
Maximizing area-constrained partial fault tolerance in reconfigurable logic
AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators
X-ORCA: FPGA-based wireless localization in the sub-millimeter range
The Case for Hard Matrix Multiplier Blocks in an FPGA
Speculative Dataflow Circuits
Buffer schemes for runtime reconfiguration of function variants in communication systems
Performance and toolchain of a combined GPU/FPGA desktop (abstract only)
Multiple FPGA Partitioning with Performance Optimization
Interconnect pipelining in a throughput-intensive FPGA architecture
Regular fabric for regular FPGA (abstract only)
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA
Polyhedral-based data reuse optimization for configurable computing
HMMer acceleration using systolic array based reconfigurable architecture
INCAME: INterruptible CNN Accelerator for Multi-robot Exploration
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters
More Wires and Fewer LUTs: A Design Methodology for FPGAs
On-chip FPGA Debug Instrumentation for Machine Learning Applications
Faithful single-precision floating-point tangent for FPGAs
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors
An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only)
Towards automated optimisation of tool-generated HW/SW sopc designs (abstract only)
Post-silicon debugging targeting electrical errors with patchable controllers (abstract only)
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only)
RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach
SwitchAgg: A Further Step Towards In-Network Computation
DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-FPGA Heterogeneous Platform
Memory-efficient and scalable virtual routers using FPGA
Exploration of pipelined FPGA interconnect structures
Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation
Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only)
OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption
FPGA technology mapping with encoded libraries andstaged priority cuts
A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only)
Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization
A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications
Improving Performance of Graph Processing on FPGA-DRAM Platform by Two-level Vertex Caching
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
Efficient FPGA Modular Multiplication Implementation
Synthesis for FPGAs with embedded memory blocks
Efficient Memory Partitioning for Parallel Data Access via Data Reuse
Design and evaluation of a parameterizable NoC router for FPGAs (abstract only)
A pipelined configurable gate array for embedded processors
Programming Abstractions for Configurable Hardware: Survey and Research Directions
An architecture for graphics processing in an FPGA (abstract only)
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
64-bit floating-point FPGA matrix multiplication
A novel methodology for designing high-performance and low-energy FPGA routing architecture
Virtualization of FPGA via segmentation (poster abstract)
Clock power reduction for virtex-5 FPGAs
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation
A CMOS Continuous-Time Field Programmable Analog Array
MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement
An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only)
Low power FPGA design using post-silicon device aging (abstract only)
t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only)
Scalable don't-care-based logic optimization and resynthesis
FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only)
An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only)
DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only)
A reconfigurable multi-function computing cache architecture
A VHDL MPEG-7 shape descriptor extractor
Energy-efficient signal processing using FPGAs
I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning
A parallel/vectorized double-precision exponential core to accelerate computational science applications
GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract)
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015
Impact of Memory Architecture on FPGA Energy Consumption
Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design
Low-Swing Signaling for FPGA Power Reduction (Abstract Only)
FPGA implementation and analysis of image restoration
Testing embedded RAM modules in SRAM-based FPGAs
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
Designing efficient input interconnect blocks for LUT clusters using counting and entropy
Mixing buffers and pass transistors in FPGA routing architectures
ACTS: A Near-Memory FPGA Graph Processing Framework
Multi-tenant FPGA Security: Challenges and Opportunities
Compressed CNN Training with FPGA-based Accelerator
FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping
Compute-Efficient Neural-Network Acceleration
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003
Power estimation tool for system on programmable chip based platforms (abstract only)
Synthesis of reconfigurable high-performance multicore systems
Dynamic reconfiguration in FPGA-based SoC designs (abstract only)
Cross-platform FPGA accelerator development using CoRAM and CONNECT
Parallel placement for field-programmable gate arrays
Formal Verification of Source-to-Source Transformations for HLS
Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only)
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
FPGAs in critical hardware/software systems
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)
A novel multithread routing method for FPGAs (abstract only)
ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines
Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only)
Network-on-Chip Programmable Platform in Versal TM ACAP Architecture
HUMA: Heterogeneous, Ultra Low-Latency Model Accelerator for The Virtual Brain on a Versal Adaptive SoC
Efficient circuit clustering for area and power reduction in FPGAs
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs
The amorphous FPGA architecture
Location, location, location: the role of spatial locality in asymptotic energy minimization
Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement
APCNN: Explore Multi-Layer Cooperation for CNN Optimization and Acceleration on FPGA
Multi-input Serial Adders for FPGA-like Computational Fabric
Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer
CReconfigurable finite field instruction set architecture
Accelerating ncRNA homology search with FPGAs
Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only)