yusuke1997/dblp-id-title huggingface dataset:
System Level Design of Embedded Controllers: Knock Detection, A Case Study in the Automotive Domain
Panel session - Consolidation, a modern "Moor of Venice" tale
Proactive recovery for BTI in high-k SRAM cells
Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Design challenges for wearable EMG applications
Low power interconnects for SIMD computers
Time Budgeting in a Wireplanning Context
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
A Performance Analysis of Chiplet-Based Systems
MATLAB/Simulink for automotive systems design
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM
Modeling and Simulation of Energy-Aware Adaptive Policies for Automatic Weather Stations
MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems
Soft Errors: System Effects, Protection Techniques and Case Studies
Applied design and analysis of microsystems
Classification trees for random tests and functional coverage
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits
Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper
Modeling of an analog recording system design for ECoG and AP signals
DC-CNN: Computational Flow Redefinition for Efficient CNN through Structural Decoupling
P/G TSV planning for IR-drop reduction in 3D-ICs
A TDM NoC supporting QoS, multicast, and fast connection set-up
Analysis of EME produced by a microcontroller operation
Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs
Emulation of Non-volatile Digital Logic for Batteryless Intermittent Computing
Bandwidth-efficient controller-server co-design with stability guarantees
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs
Reliable System Specification for Self-Checking Data-Paths
Exploring Dendritic Computation in Bio-Inspired Architectures for Dynamic Programming
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design
Polyglot Modal Models through Lingua Franca
Flexible energy-aware simulation of heterogenous wireless sensor networks
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator
Table Re-Computation Based Low Entropy Inner Product Masking Scheme
Slack-based resource arbitration for real-time Networks-on-Chip
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems
Energy parsimonious circuit design through probabilistic pruning
Fine Grain QoS Control for Multimedia Application Software
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing
Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors
Design automation for obfuscated circuits with multiple viable functions
Dim Sum: Light Clock Tree by Small Diameter Sum
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures
Is there a Market for SystemC Tools?
PS-GS: Group-Wise Parallel Rendering with Stage-Wise Complexity Reductions for Real-Time 3D Gaussian Splatting
Asymmetry of MTJ switching and its implication to STT-RAM designs
Memory-map selection for firm real-time SDRAM controllers
Impact of Data Transformations on Memory Bank Locality
How many decomposition types do we need? [decision diagrams]
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits
Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions
Identification of Hazardous Driving Scenarios Using Cross-Channel Safety Performance Indicators
Energy minimization at all layers of the data center: The ParaDIME project
Efficient Approximate Logic Synthesis with Dual-Phase Iterative Framework
Energy-efficient hardware acceleration through computing in the memory
Path Verification Using Boolean Satisfiability
Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
Confident leakage assessment - A side-channel evaluation framework based on confidence intervals
Optimal scheduling of switched FlexRay networks
Two-stage PCB Routing Using Polygon-based Dynamic Partitioning and MCTS
Automated rectification methodologies to functional state-space unreachability
3dID: a low-power, low-cost hand motion capture device
Optical look up table
Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems
GraphHD: Efficient graph classification using hyperdimensional computing
An Approximation-based Fault Detection Scheme for Image Processing Applications
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation
Test architecture design and optimization for three-dimensional SoCs
Ultra low-power 12-bit SAR ADC for RFID applications
Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices
BMP-SD: Marrying Binary and Mixed-Precision Quantization for Efficient Stable Diffusion Inference
On the Characterization of Hard-to-Detect Bridging Faults
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques
Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithms
Exploration and Design of Low-Energy Logic Cells for 1 kHz Always-on Systems
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures
The future of electronics, semiconductors, and design in Europe: panel
Constraint Refinement for Online Verifiable Cross-Layer System Adaptation
IoT security assessment through the interfaces P-SCAN test bench platform
Empirical design bugs prediction for verification
An 830mW, 586kbps 1024-bit RSA chip design
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances
Design and evaluation of fine-grained power-gating for embedded microprocessors
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems
Efficient synchronization methods for LET-based applications on a Multi-Processor System on Chip
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
SelectDirectory: a selective directory for cache coherence in many-core architectures
Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks
A block-diagonal structured model reduction scheme for power grid networks
Configurability in IP subystems: baseband examples
Graph-Based Functional Test Program Generation for Pipelined Processors
A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example
Efficient Latency Bound Analysis for Data Chains of Real-Time Tasks in Multiprocessor Systems
Visualization of Partial Order Models in VLSI Design Flow
A Formal Description of VHDL-AMS Analogue Systems
Towards Best-effort Approximation: Applying NAS to General-purpose Approximate Computing
VLSI Design of a High Speed Soft Decision Viterbi Detector
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem
Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology
Optimizing Data-Flow Graphs with min/max, adding and relational operations
Improving performance guarantees in wormhole mesh NoC designs
Clock gating optimization with delay-matching
CMOS-Based Biosensor Arrays
Deterministic, predictable and light-weight multithreading using PRET-C
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs
Dynamic Realization of Multiple Control Toffoli Gate
Analog neuromorphic computing enabled by multi-gate programmable resistive devices
Automatic and efficient heap data management for limited local memory multicore architectures
Statistically Aware Buffer Planning
Embedded Social Insect-Inspired Intelligence Networks for System-level Runtime Management
Low-power smart industrial control
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search
Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks
System-level power estimation methodology using cycle- and bit-accurate TLM
Large scale, high density integration of all spin logic
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing
Battery-aware code partitioning for a text to speech system
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon
Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-Skipping
NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks
Applying Behavioural Level Test Generation to High-Level Design Validation
Flexible Cache Partitioning for Multi-Mode Real-Time Systems
A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative
Software security: Vulnerabilities and countermeasures for two attacker models
An Automatic Hardware-Software Partitioner Based on the Possibilistic Programming
BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes
Equivalence checking for function pipelining in behavioral synthesis
On automatic analysis of geometrically proximate nets in VSLI layout
Flexible Software Protection Using Hardware/Software Codesign Techniques
A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory
Circumventing Restrictions in Commercial High-Level Synthesis Tools
Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests
FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems
MULTI-POS: Marie Curie network in multi-technology positioning
Introduction to Hardware Abstraction Layers for SoC
Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support
ObfusGate: Representation Learning-Based Gatekeeper for Hardware-Level Obfuscated Malware Detection
Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic
Optimization of Design Flows for Multi-Core x86 Microprocessors in 45 and 32nm Technologies under Productivity Considerations
Fault Localization in Programmable Microfluidic Devices
Environmental Microchanges in WiFi Sensing
Using Reconfigurable Logic to Optimise GPU Memory Accesses
VHDL Teamwork, Organization Units and Workspace Management
Exploiting data-dependence and Flip-Flop asymmetry for zero-overhead system soft error mitigation
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs
Rate-based vs delay-based control for DVFS in NoC
Efficient AC analysis of oscillators using least-squares methods
Simplified programming of faulty sensor networks via code transformation and run-time interval computation
Cross-contamination avoidance for droplet routing in digital microfluidic biochips
Watermarking of Behavioral IPs: A Practical Approach
An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architecture
SSMDVFS: Microsecond-Scale DVFS on GPGPUs with Supervised and Self-Calibrated ML
Improving the error behavior of DRAM by exploiting its Z-channel property
On testing prebond dies with incomplete clock networks in a 3D IC using DLLs
Fast, low power evaluation of elementary functions using radial basis function networks
PUFs at a glance
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method
Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks
Scheduling for register file energy minimization in explicit datapath architectures
Extended Control Flow Graph Based Performance Optimization Using Scratch-Pad Memory
Integrated Electronics in the Car and the Design Chain Evolution or Revolution?
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components
Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs
A work-stealing scheduling framework supporting fault tolerance
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk
Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures
A dynamically adaptive DSP for heterogeneous reconfigurable platforms
A low complexity stopping criterion for reducing power consumption in turbo decoders
Formal approaches to analog circuit verification
Thermal-Aware Task Allocation and Scheduling for Embedded Systems
High-efficiency logarithmic number unit design based on an improved cotransformation scheme
A Case for Emerging Memories in DNN Accelerators
A Low-Cost Methodology for EM Fault Emulation on FPGA
Formal Synthesis of Monitoring and Detection Systems for Secure CPS Implementations
Design and Test Space Exploration of Transport-Triggered Architectures
Automatic generation of power state machines through dynamic mining of temporal assertions
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
A 622/155 mbps ATM line terminator mono-chip
An Environment for Dynamic Component Composition for Efficient Co-Design
De 2 r: Unifying DVFS and Early-Exit for Embedded AI Inference via Reinforcement Learning
Efficient Design Rule Checking with GPU Acceleration
Enhanced Diameter Bounding via Structural
A spectral method for Boolean function matching
Approximate hardware generation using symbolic computer algebra employing grobner basis
Using Universal Composition to Design and Analyze Secure Complex Hardware Systems
A New Paradigm for Dichotomy-based Constrained Encoding
Design Space exploration of FPGA-based accelerators with multi-level parallelism
Predictive control of networked control systems over differentiated services lossy networks
Correct-by-construction multi-component SoC design
Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
CATALYST: planning layer directives for effective design closure
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Dynamic Reconfigurable Security Cells Based on Emerging Devices Integrable in FDSOI Technology
Clock-modulation based watermark for protection of embedded processors
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Radar signature in multiple target tracking system for driver assistant application
Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation
A small non-volatile write buffer to reduce storage writes in smartphones
Spintronic memristor devices and application
Low Power Error Resilient Encoding for On-Chip Data Buses
Towards Automated Detection of Higher-Order Memory Corruption Vulnerabilities in Embedded Devices
Structured Optimized Architecting of Full-Stack Quantum Systems in the NISQ era
Efficient testbench code synthesis for a hardware emulator system
FPGA Placement by Thermodynamic Combinatorial Optimization
Exploiting subarrays inside a bank to improve phase change memory performance
Panel: What is EDA doing for trailing edge technologies?
Timing Correction and Optimization with Adaptive Delay Sequential Element
Algorithm-Hardware Co-Design for Energy-Efficient A/D Conversion in ReRAM-Based Accelerators
Using randomization to cope with circuit uncertainty
Verilog2SMV: A tool for word-level verification
Design of Fault-Secure Parity-Prediction Booth Multipliers
Towards the formal analysis of microresonators based photonic systems
UML for Embedded Systems Specification and Design: Motivation and Overview
A Deeper Look at the Energy Consumption of Lightweight Block Ciphers
An analytical state dependent leakage power model for FPGAs
A System-Level Synthesis Algorithm with Guaranteed Solution Quality
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core
Fast statistical circuit analysis with finite-point based transistor model
A variant of Cooley-Tuckey algorithm with local memory management
FPGA-based failure mode testing and analysis for MLC NAND flash memory
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation
Automotive System Design - Challenges and Potential
A q-gram birthmarking approach to predicting reusable hardware
EBIST: A Novel Test Generator with Built-In Fault Detection Capability
n-bit Data Parallel Spin Wave Logic Gate
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
Glitch Power Minimization by Gate Freezing
Potential applications based on NVM emerging technologies
Gate Sizing: A General Purpose Optimization Approach
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Multi-temperature testing for core-based system-on-chip
Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer
Modelling SoC devices for virtual test using VHDL
At-Speed Logic BIST for IP Cores
Wire-Bonding Finger Placement for FBGA Substrate Layout Design with Finger Orientation Consideration
4G applications, architectures, design methodology and tools for MPSoC
Design of AI Trojans for Evading Machine Learning-based Detection of Hardware Trojans
Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing
Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications
A 3 PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader
DDI: A novel technology and innovation model for dependable, collaborative and autonomous systems
Crosstalk-aware domino logic synthesis
A general mathematical model of probabilistic ripple-carry adders
Fast Field Solvers for Thermal and Electrostatic Analysis
ICP and IC3
BITMAN: A tool and API for FPGA bitstream manipulations
Enhancing Two-Phase Cooling Efficiency through Thermal-Aware Workload Mapping for Power-Hungry Servers
VERIFUL: VERIfication using FUnctional Learning
A design tool for high performance image processing on multicore platforms
Improving fast charging efficiency of reconfigurable battery packs
Incremental Diagnosis and Correction of Multiple Faults and Errors
Image Computation for Quantum Transition Systems
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level
A flexible ASIP architecture for connected components labeling in embedded vision applications
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems
Cross-layer resilience challenges: Metrics and optimization
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches
Performance Analysis and Auto-tuning for SPARK in-memory analytics
A procedure for improving the distribution of congestion in global routing
Malware detection using machine learning based analysis of virtual memory access patterns
Power-efficient control of thermoelectric coolers considering distributed hot spots
Mission Specification and Execution of Multidrone Systems
Accurate Power Density Map Estimation for Commercial Multi-Core Microprocessors
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation
Codex-dp: Co-design of Communicating Systems Using Dynamic Programming
A reconfigurable multiprocessor architecture for a reliable face recognition implementation
A methodology for hardware architecture trade-off at different levels of abstraction
Functional units with conditional input/output behavior in VLIW processors
Real-Time Energy Monitoring in IoT-enabled Mobile Devices
A real-time compressed sensing-based personal electrocardiogram monitoring system
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches
Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads
Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs
Monolithic verification of deep pipelines with collapsed flushing
Protecting RISC-V Processors against Physical Attacks
Transistor-level gate model based statistical timing analysis considering correlations
Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA
FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring
Porting a Network Cryptographic Service to the RMC2000: A Case Study in Embedded Software Development
An optimized task-based runtime system for resource-constrained parallel accelerators
Quick error detection tests with fast runtimes for effective post-silicon validation and debug
Implementation of A MEMS Resonator-based Digital to Frequency Converter Using Artificial Neural Networks
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications
Spiking neural network with RRAM: can we use it for real-world application?
Procedure cloning: a transformation for improved system-level functional partitioning
Platform-Based Testbench Generation
Gradient-based Bit Encoding Optimization for Noise-Robust Binary Memristive Crossbar
Low complexity QR-decomposition architecture using the logarithmic number system
Method for reducing jitter in multi-gigahertz ATE
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes
Modeling the SL-LET Paradigm in AUTOSAR Adaptive
Satisfiability-based framework for enabling side-channel attacks on cryptographic software
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015
Pasta on Edge: Cryptoprocessor for Hybrid Homomorphic Encryption
Analysis and optimization of variable-latency designs in the presence of timing variability
MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction
Hardware Check of Arithmetic Devices with Abridged Execution of Operations
Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search
Power Balanced Gates Insensitive to Routing Capacitance Mismatch
Full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniques
Early detection of system-level anomalous behaviour using hardware performance counters
Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems
Compromising the Intelligence of Modern DNNs: On the Effectiveness of Targeted RowPress
Analysis of short-circuit conditions in logic circuits
A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks *