yusuke1997/dblp-id-title huggingface dataset:
Improving Static Branch Prediction in a Compiler
17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008
Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code
The compiler TwoL for the design of parallel implementations
STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems
MicroSpec: Speculation-Centric Fine-Grained Parallelization for FSM Computations
Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems
POSTER: Leveraging Run-Time Feedback for Efficient ASR Acceleration
Simple and fast biased locks
A loop parallelization technique for linear dependence vector
A Software-Managed Approach to Die-Stacked DRAM
DMO-DB: Mitigating the Data Movement Bottlenecks of GPU-Accelerated Relational OLAP
DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems
A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design
Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997
Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems
MASR: A Modular Accelerator for Sparse RNNs
GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near-Memory Processing
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
Log(graph): a near-optimal high-performance graph representation
Dynamic Branch Prediction for a VLIW Processor
Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads
TO-Lock: Removing Lock Overhead Using the Owners' Temporal Locality
RSVM: A Region-based Software Virtual Memory for GPU
26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017, Portland, OR, USA, September 9-13, 2017
Dynamic Allocation of Processor Cores to Graph Applications on Commodity Servers
High-performance analysis of filtered semantic graphs
Edge-centric modulo scheduling for coarse-grained reconfigurable architectures
The Forward Slice Core Microarchitecture
Redesigning Go's Built-In Map to Support Concurrent Operations
Transformation of functional specifications of finite difference methods to parallel distributed codes
TPE: XPU-Point: Simulator-Agnostic Sample Selection Methodology for Heterogeneous CPU-GPU Applications
Implementation techniques for a parallel relative debugger
Handling the problems and opportunities posed by multiple on-chip memory controllers
Intelligent Data Placement on Discrete GPU Nodes with Unified Memory
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
Twin peaks: a software platform for heterogeneous computing on general-purpose and graphics processors
Speculative Sequential Consistency with Little Custom Storage
Understanding and Reaching the Performance Limit of Schedule Tuning on Stable Synchronization Determinism
Direct Generation of Data-Driven Program for Stream-Oriented Processing
Madeleine: An Efficient and Portable Communication Interface for RPC-Based Multithreaded Environments
Strategies based on green policies to the grid resource allocation
Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency
Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic
POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications
SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers
Specialization Opportunities in Graphical Workloads
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors
Compiler Optimizations for Fault Tolerance Software Checking
Error Detection Using Dynamic Dataflow Verification
Off-chip access localization for NoC-based multicores
Program Lifting using Gray-Box Behavior
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
NVMMU: A Non-volatile Memory Management Unit for Heterogeneous GPU-SSD Architectures
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency
A yoke of oxen and a thousand chickens for heavy lifting graph processing
Top500 versus sustained performance: the top problems with the top500 list - and what to do about them
Reducing task creation and termination overhead in explicitly parallel programs
Miss Rate Prediction across All Program Inputs
Analyzing and Leveraging Shared L1 Caches in GPUs
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores
A simple algorithm for the generation of efficient loop structures
VW-SLP: auto-vectorization with adaptive vector width
UWOmppro: UWOmp++ with Point-to-Point Synchronization, Reduction and Schedules
Design for scalability in enterprise SSDs
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
Optimizing Tensor Computation Graphs with Equality Saturation and Monte Carlo Tree Search
Performance Characteristics of a Network of Commodity Multiprocessors for the NAS Benchmarks Using a Hybrid Memory Model
Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems
LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power
High-End Computing Technology: Where is it Heading?
Bandwidth-Aware Loop Tiling for DMA-Supported Scratchpad Memory
Enforcing Last-Level Cache Partitioning through Memory Virtual Channels
Exploiting Method-Level Parallelism in Single-Threaded Java Programs
Breaking the Vendor Lock: Performance Portable Programming through OpenMP as Target Independent Runtime Layer
POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core
Automatic optimization of thread-coarsening for graphics processors
Energy-efficient cache partitioning for future CMPs
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics
POSTER: Memory Hotspot Optimization for Data-Intensive Applications
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries
Using dead blocks as a virtual victim cache
Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators
Outer-loop vectorization: revisited for short SIMD architectures
Speculatively Exploiting Cross-Invocation Parallelism
BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models
Energy-efficient workload mapping in heterogeneous systems with multiple types of resources
Lower Bounding Techniques for the Multiprocessor Scheduling Problem with Communication Delay
Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory
Core-Selectability in Chip Multiprocessors
Probing the Efficacy of Hardware-Aware Weight Pruning to Optimize the SpMM Routine on Ampere GPUs
RSTM : A Relaxed Consistency Software Transactional Memory for Multicores
A GPU-Friendly Skiplist Algorithm
Redundancy elimination revisited
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers
NUcache: a multicore cache organization based on next-use distance
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
Ribbon: High Performance Cache Line Flushing for Persistent Memory
Autotuning of OpenCL Kernels with Global Optimizations
HaLock: hardware-assisted lock contention detection in multithreaded applications
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems
PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System
Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators
HeTM: Transactional Memory for Heterogeneous Systems
End-to-End Deep Learning of Optimization Heuristics
RCS: runtime resource and core scaling for power-constrained multi-core processors
PIM-DL: Boosting DNN Inference on Digital Processing In-Memory Architectures via Data Layout Optimizations
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors
Self-checking instructions: reducing instruction redundancy for concurrent error detection
FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology
HPS: Hybrid Profiling Support
GMOD: a dynamic GPU memory overflow detector
Helix: Algorithm/Architecture Co-design for Accelerating Nanopore Genome Base-calling
An OpenCL Framework for Homogeneous Manycores with No Hardware Cache Coherence
Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing
Model-Based Warp Overlapped Tiling for Image Processing Programs on GPUs
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance
Chimera: Leveraging Hybrid Offsets for Efficient Data Prefetching
Generating Portable High-Performance Code via Multi-Dimensional Homomorphisms
Riposte: a trace-driven compiler and parallel VM for vector code in R
Rollback-free value prediction with approximate loads
DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture
Looking at History to Filter Allocations in Prediction Tables
2015 International Conference on Parallel Architectures and Compilation, PACT 2015, San Francisco, CA, USA, October 18-21, 2015
An efficient graph accelerator with parallel data conflict management
Ordered multithreading: a novel technique for exploiting thread-level parallelism
A model for fusion and code motion in an automatic parallelizing compiler
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
Polyhedral-Model Guided Loop-Nest Auto-Vectorization
Multithread execution mechanisms on RICA-1 for massively parallel computation
Proceedings of the Sixth Workshop on Data-Flow Execution Models for Extreme Scale Computing, DFM@PACT 2016, Haifa, Israel, September 15, 2016
The case for a scalable coherence protocol for complex on-chip cache hierarchies in many-core systems
Vector Parallelism in JavaScript: Language and Compiler Support for SIMD
Cache-Friendly Implementations of Transitive Closure
Just-In-Time Java? Compilation for the Itanium® Processor
Two-level mapping based cache index selection for packet forwarding engines
VTensor: Using Virtual Tensors to Build a Layout-oblivious AI Programming Framework
12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA
SURFNet: Super-Resolution of Turbulent Flows with Transfer Learning using Small Datasets
Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures
Domain-specific models for innovation in analytics
Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex Applications
POSTER: Precise Capacity Planning for Database Public Clouds
Efficient JavaVM Just-in-Time Compilation
Language and Virtual Machine Support for Efficient Fine-Grained Futures in Java
MEPHESTO: Modeling Energy-Performance in Heterogeneous SoCs and Their Trade-Offs
Ring Prediction for Non-Uniform Cache Architectures
L1-bandwidth aware thread allocation in multicore SMT processors
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture
Efficient Edge Profiling for ILP-Processors
Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures
AM++: a generalized active message framework
Online cache modeling for commodity multicore processors
Can lock-free and combining techniques co-exist? A novel approach on concurrent queue
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
Efficient Parallel Graph Exploration on Multi-Core CPU and GPU
Unified Identification of Multiple Forms of Parallelism in Embedded Applications
Effects of data bundling in non-strict data structures
Workload and power budget partitioning for single-chip heterogeneous processors
A compiler transformation to improve memory access time in SIMD systems
Partitioning of Code for a Massively Parallel Machine
Region array SSA
POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems
Introducing Control Flow into Vectorized Code
Analysis of communications and overhead reduction in multithreaded execution
System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks
A Framework for Parallelizing Load/Stores on Embedded Processors
A Multithreaded Java Microcontroller for Thread-Oriented Real-Time Event Handling
SLIDEX: Sliding Window Extension for Image Processing
Reducing control overhead in dataflow architectures
INSPIRE: The insieme parallel intermediate representation
Power-efficient time-sensitive mapping in heterogeneous systems
A Generalized Framework for Automatic Scripting Language Parallelization
A New Parallel Gauss-Seidel Method by Iteration Space Alternate Tiling
Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution
Cooperative cache scrubbing
HERO: an open-source research platform for HW/SW exploration of heterogeneous manycore systems
Power and thermal characterization of POWER6 system
TIDeFlow: A Parallel Execution Model for High Performance Computing Programs
Design and implementation of the PLUG architecture for programmable and efficient network lookups
Polyhedral Optimizations of Explicitly Parallel Programs
POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation
Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels
kMAF: automatic kernel-level management of thread and data affinity
Stadium Hashing: Scalable and Flexible Hashing on GPUs
Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR
Picking Statistically Valid and Early Simulation Points
Optimizing Persistent Memory Transactions
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems
Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers
Instruction Based Memory Distance Analysis and its Application
POSTER: Application-Driven Near-Data Processing for Similarity Search
An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition
A Task-Centric Memory Model for Scalable Accelerator Architectures
OpenMDSP: Extending OpenMP to Program Multi-Core DSP
POSTER: Domain-Specialized Cache Management for Graph Analytics
MemoDyn: exploiting weakly consistent data structures for dynamic parallel memoization
Avoiding deadlock avoidance
Hybrid Parallel Circuit Simulation Approaches
Communication Optimizations for Fine-Grained UPC Applications
Benefits in Relaxing the Power Capping Constraint
Towards a science of parallel programming
Data flow analysis of parallel programs
Tree-based Read-only Data Chunks for NVRAM Programming
COUNTDOWN: a run-time library for application-agnostic energy saving in MPI communication primitives
Mileage-based contention management in transactional memory
The Stream Virtual Machine
Scalable Proximity-Aware Cache Replication in Chip Multiprocessors
ILP and TLP in shared memory applications: a limit study
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
Studying Asynchronous Shared Memory Computations
PGCapping: exploiting power gating for power capping and core lifetime balancing in CMPs
Visualizing potential parallelism in sequential programs
Architecture-Aware Currying
Com-CAS: Effective Cache Apportioning under Compiler Guidance
nuKSM: NUMA-aware Memory De-duplication on Multi-socket Servers
Data layout transformation exploiting memory-level parallelism in structured grid many-core applications
Compiler assisted coalescing
EAR: ECC-aided refresh reduction through 2-D zero compression
Using Compiler Techniques to Improve Automatic Performance Modeling
SpongeDirectory: flexible sparse directories utilizing multi-level memristors
Keynote talk: A comprehensive approach to HW/SW codesign
A Methodology for Characterizing Sparse Datasets and Its Application to SIMD Performance Prediction
BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons
Register allocation sensitive region scheduling
POSTER: Space and Time Optimal DNN Primitive Selection with Integer Linear Programming
MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement
Divergence Analysis and Optimizations
POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads
Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory
POSTER: Fly-Over: A Light-Weight Distributed Power-Gating Mechanism For Energy-Efficient Networks-on-Chip
Vectorization past dependent branches through speculation
Improving the effectiveness of software prefetching with adaptive executions
An empirical characterization of stream programs and its implications for language and compiler design
Parallel Programming and Parallel Abstractions in Fortress
Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler
Localizing Non-Affine Array References
Graphphi: efficient parallel graph processing on emerging throughput-oriented architectures
Improving performance of streaming applications with filtering and control messages
ATAC: a 1000-core cache-coherent processor with on-chip optical network
Parallelization of Benchmarks for Scalable Shared-Memory Multiprocessors
RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees
Do inputs matter? using data-dependence profiling to evaluate thread level speculation in BG/Q
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
Reshaping cache misses to improve row-buffer locality in multicore systems
Criticality-driven superscalar design space exploration
International Conference on Parallel Architectures and Compilation Techniques, PACT '12, Minneapolis, MN, USA - September 19 - 23, 2012
Workload Design: Selecting Representative Program-Input Pairs
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs
An Alternative Memory Access Scheduling in Manycore Accelerators
POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS
Compiling for stream processing
ACE: Efficient GPU Kernel Concurrency for Input-Dependent Irregular Computational Graphs
POSTER: Automatic Parallelization Targeting Asynchronous Task-Based Runtimes
An Algorithmic Approach to Communication Reduction in Parallel Graph Algorithms
POSTER: NUMA-Aware Power Management for Chip Multiprocessors
Compiling Chapel: Keys to Making Parallel Programming Productive at Scale
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware
Optimizing Compiler for the CELL Processor
On Index Set Splitting
Efficient Task-Mapping of Parallel Applications Using a Space-Filling Curve
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs
Bridging Inputs and Program Dynamic Behavior
Memory-centric system interconnect design with Hybrid Memory Cubes
Scalable and reliable communication for hardware transactional memory
Transactional pre-abort handlers in hardware transactional memory
Fast, Accurate and Flexible Data Locality Analysis
Storage Consolidation on SSDs: Not Always a Panacea, but Can We Ease the Pain?
Two Techniques for Static Array Partitioning on Message-Passing Parallel Machines
AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance
Managing shared last-level cache in a heterogeneous multicore processor
TSUNAMI: A GPU Implementation of the WFA Algorithm
Instance-Wise Reaching Definition Analysis for Recursive Programs using Context-Free Transductions
Architecting a Novel Hybrid Cache with Low Energy
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
VAST: the illusion of a large memory space for GPUs
The Automatic Transformation of Linked List Data Structures
cuSZ: An Efficient GPU-Based Error-Bounded Lossy Compression Framework for Scientific Data
Linearly compressed pages: a main memory compression framework with low complexity and low latency
Comparing Hypergraphs by Areas of Hyperedges Drawn on a Convex Polygon
Distance Geometry on the Sphere
Chvátal-Erdős Theorem: Old Theorem with New Aspects
On Reconfiguring Radial Trees
The Minimum Manhattan Network Problem: A Fast Factor-3 Approximation
On the Number of Views of Polyhedral Scenes
Constrained Equitable 3-Cuttings
Counting 2-Factors of 4-Regular Bipartite Graphs is #P-Complete
Approximating Uniform Triangular Meshes for Spheres
Decomposing Octilinear Polygons into Triangles and Rectangles
Discrete and Computational Geometry, Japanese Conference, JCDCG 2004, Tokyo, Japan, October 8-11, 2004, Revised Selected Papers
Geometric p-Center Problems with Centers Constrained to Two Lines
Grouping and Querying: A Paradigm to Get Output-Sensitive Algorithms
Long Paths through Specified Vertices in 3-Connected Graphs
On Convex Decompositions of Points
Dissection with the Fewest Pieces is Hard, Even to Approximate
A General Framework for Coloring Problems: Old Results, New Results, and Open Problems
An Efficient Solution to the Corridor Search Problem
Some Conditions for the Existence of ( d , k )-Digraphs
Living with lrs
Mario Kart Is Hard
Previous Player's Positions in Impartial Three-Dimensional chocolate-Bar Games with Constrained chocolate Size
The Construction of Delaunay Diagrams by Lob Reduction
Negative Instance for the Edge Patrolling Beacon Problem
Find Routes on a Doughnut
Volume Queries in Polyhedra
A Characterization of Link-2 LR-visibility Polygons with Applications
Piano-Hinged Dissections: Now Let's Fold!
Discrete and Computational Geometry, Graphs, and Games - 24th Japanese Conference, JCDCGGG 2022, Virtual Event, September 9-11, 2022, Revised Selected Papers
Topological Graph Layouts into a Triangular Prism
Memorial for Mari-Jo P. Ruiz - A Colleague and Friend in Art and Math
Computational Complexity of Two Pencil Puzzles: Kurotto and Juosan
Regular Factors Containing a Given Hamiltonian Cycle
Complexity of Solo Chess with Unlimited Moves
An Optimal Algorithm for the 1-Searchability of Polygonal Rooms
Dudeney Dissection of Polygons
Single-Player and Two-Player Buttons & Scissors Games - (Extended Abstract)
Antimagic Valuations for the Special Class of Plane Graphs
Geometric Transformations in Plane Triangulations
Tight Bounds for Visibility Matching of f-Equal Width Objects
Delta-Optimum Exclusive Sum Labeling of Certain Graphs with Radius One
Sliding Disks in the Plane
New Formulation for Coloring Circle Graphs
Approximation Algorithms for Maximum Independent Set Problems and Fractional Coloring Problems on Unit Disk Graphs
Grid Vertex-Unfolding Orthostacks
The Decycling Number of Cubic Graphs
Visual Pascal Configuration and Quartic Surface
An Interpolant Based on Line Segment Voronoi Diagrams
On the Number of Intersections of Three Monochromatic Trees in the Plane
Structure Theorems for Systems of Segments
Spanning Trees of Multicoloured Point Sets with Few Intersections
Universal Measuring Devices without Gradations
Matching Points with Circles and Squares
Illuminating Both Sides of Line Segments
Algorithms for Burning Schedule Reconfiguration Problem on Path Forests
On the Complexity of Testing Hypermetric, Negative Type, k-Gonal and Gap Inequalities