yusuke1997/dblp-id-title huggingface dataset:
Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration
Power invariant vector sequence compaction
Design of analog circuits using organic field-effect transistors
Invited Paper: CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing
Verification through the principle of least astonishment
Efficient analog platform characterization through analog constraint graphs
Statistical critical path analysis considering correlations
Doubly folded transistor matrix layout
Temporal Vectorization: A Compiler Approach to Automatic Multi-Pumping
DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design
A chip-level electrostatic discharge simulation strategy
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993
Design-hierarchy aware mixed-size placement for routability optimization
MT-spike: A multilayer time-based spiking neuromorphic architecture with temporal error backpropagation
Performance analysis of carbon nanotube interconnects for VLSI applications
Algorithms for address assignment in DSP code generation
Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference
MC-Sim: an efficient simulation tool for MPSoC designs
Bi-decomposition of large Boolean functions using blocking edge graphs
A statistical approach for full-chip gate-oxide reliability analysis
A simultaneous bus orientation and bused pin flipping algorithm
Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications
Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999
Automatic test pattern generation for delay defects using timed characteristic functions
Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
Test generation for delay faults in non-scan and partial scan sequential circuits
Slicing floorplans with pre-placed modules
Run-time requirement tracing
Side Channel-Assisted Inference Attacks on Machine Learning-Based ECG Classification
Robust reconfigurable filter design using analytic variability quantification techniques
A grid-based approach for connectivity binding with geometric costs
System-level process-driven variability analysis for single and multiple voltage-frequency island systems
Strengthening the Foundations for IC Physical Design and ML EDA Research
Automatic modeling of switch-level networks using partial orders
AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design Quality
Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication
Large Scale Delocalized Federated Learning Over a Huge Diversity of Devices in Emerging Next-Generation Edge Intelligence Environments
A Uniform Modeling Methodology for Benchmarking DNN Accelerators
IES3: a fast integral equation solver for efficient 3-dimensional extraction
Invited Paper: 2025 ICCAD CAD Contest Problem A: Hardware Trojan Detection on Gate-Level Netlist
HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware
The A to Z of SoCs
Robust system level design with analog platforms
Performance driven routing for modern FPGAs
An effective methodology for functional pipelining
Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays
CTL model checking based on forward state traversal
Incremental deductive & inductive reasoning for SAT-based bounded model checking
LP-Spec: Leveraging LPDDR PIM for Efficient LLM Mobile Speculative Inference with Architecture-Dataflow Co-Optimization
An IDDQ-based source driver IC design-for-test technique
Post-route optimization for improved yield using a rubber-band wiring model
Mining mutation testing simulation traces for security and testbench debugging
On rewiring and simplification for canonicity in threshold logic circuits
FLOP: A Flexible Memory-Optimized Processor for Parallel Graph Mining on FPGA
Formulating customized specifications for resource allocation problem of distributed embedded systems
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
ReCon: Reconfiguring Analog Rydberg Atom Quantum Computers for Quantum Generative Adversarial Networks
Battery optimization vs energy optimization: which to choose and when?
Invited Paper: Machine Learning Based Blind Side-Channel Attacks on PQC-Based KEMs - A Case Study of Kyber KEM
Timing distribution in VHDL behavioral models
SETGAN: Scale and Energy Trade-off GANs for Image Applications on Mobile Platforms
A timing analysis algorithm for circuits with level-sensitive latches
Application-specific customization of parameterized FPGA soft-core processors
Performance-driven simultaneous place and route for island-style FPGAs
Generative AI Agents in Autonomous Machines: A Safety Perspective
Heterogeneous Manycore In-Memory Computing Architectures
Efficient breadth-first manipulation of binary decision diagrams
Automated refinement checking of concurrent systems
MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
Synthesis of customized loop caches for core-based embedded systems
Improving the computational performance of ILP-based problems
Data Path Placement with Regularity
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM
Generalized Symmetries in Boolean Functions
SiGNoR: Similarity-based Graph Partitioning and Node Reuse for Memory Efficient GNN Acceleration
A controller-based design-for-testability technique for controller-data path circuits
On the generation of small dictionaries for fault location
From molecular interactions to gates: a systematic approach
VeriSAT: the Hardware Design of Modern SAT Solver
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
Buildings to Grid Integration: A Dynamic Contract Approach
(Invited Paper) Overview of 2025 CAD Contest at ICCAD
Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling
Boolean decomposition in multi-level logic optimization
ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite
Consistency-based characterization for IC Trojan detection
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms
An efficient algorithm for layout compaction problem with symmetry constraints
SPIRE: A retiming-based physical-synthesis transformation system
PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network
Global interconnect sizing and spacing with consideration of coupling capacitance
Reverse engineering camouflaged sequential circuits without scan access
A practical detailed placement algorithm under multi-cell spacing constraints
2024 ICCAD CAD Contest Problem C: Scalable Logic Gate Sizing Using ML Techniques and GPU Acceleration
TGPA: tile-grained pipeline architecture for low latency CNN inference
SpectrePrefetch: Undermining Cache-Centric Secure Speculation with Modern Hardware Prefetchers
IPR: In-Place Reconfiguration for FPGA fault tolerance
Retiming with non-zero clock skew, variable register, and interconnect delay
THRIFTY: Training with Hyperdimensional Computing across Flash Hierarchy
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
TRAIN: A Reinforcement Learning Based Timing-Aware Neural Inference on Intermittent Systems
Factor cuts
A formal approach to nonlinear analog circuit verification
A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool
Circuit valorization in the IC design ecosystem
A Probabilistic Constructive Approach to Optimization Problems
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
Integrated circuit design with NEM relays
ATPG Aspects of FSM Verification
Designing adaptive neural networks for energy-constrained image classification
Vdd programmability to reduce FPGA interconnect power
Design and manufacturing of organic RFID circuits: Coping with intrinsic parameter variations in organic devices by circuit design
Approximate symbolic analysis of large analog integrated circuits
Multilevel Approach to Full-Chip Gridless Routing
Guaranteed stable projection-based model reduction for indefinite and unstable linear systems
Application-independent defect-tolerant crossbar nano-architectures
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design
JKQ: JKU Tools for Quantum Computing
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding
Test generation for sequential circuits using individual initial value propagation
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation
An efficient non-enumerative method to estimate path delay fault coverage
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks
Optimization of custom MOS circuits by transistor sizing
Invited Paper: Synthesizing Analog & Mixed-Signal Floating-Gate enabled Reconfigurable Fabrics using Analog Standard Cells
Defensive dropout for hardening deep neural networks under adversarial attacks
GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm
Verifying correct pipeline implementation for microprocessors
Diffusion - An Analytic Procedure Applied to Macro Cell Placement
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications
Framework designs to enhance reliable and timely services of disaster management systems
Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM Inference
A general model for performance optimization of sequential systems
1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)
Designing and Training Neural Networks for Analog In-Sensor Deployment: A Hardware-Aware Analysis
SAM: A Scalable Accelerator for Number Theoretic Transform Using Multi-Dimensional Decomposition
Error recovery in a micro-electrode-dot-array digital microfluidic biochip?
Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper)
Invited Paper: Heterogeneous Acceleration for Design Rule Checking
Simulation of random telegraph Noise with 2-stage equivalent circuit
A study of routability estimation and clustering in placement
Design and algorithm for clock gating and flip-flop co-optimization
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering
Logic Simulation and Parallel Processing
DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO
Steep coverage-ascent directed test generation for shared-memory verification of multicore chips
Adaptive methods for netlist partitioning
Interconnect Resource-Aware Placement for Hierarchical FPGAs
Towards a standard flow for system level power modeling
Post global routing crosstalk risk estimation and reduction
Verification of large synthesized designs
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
A robust cell-level crosstalk delay change analysis
The Munich Microfluidics Toolkit: Design Automation and Simulation Tools for Microfluidic Devices
A Probabilistic-Based Design Methodology for Nanoscale Computation
Security and privacy threats to on-chip non-volatile memories and countermeasures
Static power optimization of deep submicron CMOS circuits for dual VT technology
BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks
A statistical framework for post-silicon tuning through body bias clustering
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel)
Hybrid floorplanning based on partial clustering and module restructuring
Input don't care sequences in FSM networks
A trace compression algorithm targeting power estimation of long benchmarks
Diagnosis of realistic bridging faults with single stuck-at information
Delay noise pessimism reduction by logic correlations
Overview of 2024 CAD contest at ICCAD
An optimal algorithm for area minimization of slicing floorplans
Time-Division Multiplexing Based System-Level FPGA Routing
Thermal-aware reliability analysis for platform FPGAs
Pattern generation for a deterministic BIST scheme
Maze routing algorithms with exact matching constraints for analog and mixed signal designs
A Novel Way to Authenticate Untrusted Integrated Circuits
An ATPG-Based Approach to Sequential Logic Optimization
A layout defect-sensitivity extractor
Privacy protection via appliance scheduling in smart homes
The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip
DeltaSyn: An efficient logic difference optimizer for ECO synthesis
Symbolic Uniform Sampling with XOR Circuits
Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications
TRIAD: A triple patterning lithography aware detailed router
Improved SAT-based ATPG: more constraints, better compaction
Direct Transistor-Level Layout for Digital Blocks
Statistical sampling and regression analysis for RT-level power evaluation
Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs
Reliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge Devices
Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper)
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Optimisation Problems for Dynamic Concurrent Task-Based Systems
Accurate estimation of global buffer delay within a floorplan
Co-designing 2.5D Silicon Photonic Accelerators for Distributed Transformer at the Edge
Zamlog: a parallel algorithm for fault simulation based on Zambezi
Analysis of production data manipulation attacks in petroleum cyber-physical systems
Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs
Why Doesn't EDA Get Enough Respect?
Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization
Constrained conditional resource sharing in pipeline synthesis
Retiming with Interconnect and Gate Delay
Automated error prediction for approximate sequential circuits
Maze router without a grid map
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Clock mesh synthesis with gated local trees and activity driven register clustering
Placement based multiplier rewiring for cell-based designs
An energy and power-aware approach to high-level synthesis of asynchronous systems
Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems
3D Acceleration for Mixture-of-Experts and Multi-Head Attention Spiking Transformers with Dynamic Head Pruning
A robust architecture for post-silicon skew tuning
Boolean algebraic test generation using a distributed system
A closed-loop design to enhance weight stability of memristor based neural network chips
Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical Interconnects
Practical placement and routing techniques for analog circuit designs
Advances in transistor timing, simulation, and optimization (tutorial abstract)
TimingSAT: timing profile embedded SAT attack
Current path analysis for electrostatic discharge protection
Thermally-Aware Multi-Core Chiplet Stacking
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
Adar: Adversarial Activity Recognition in Wearables
Area-I/O flip-chip routing for chip-package co-design
Routability Prediction and Optimization Using Explainable AI
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library
Practical techniques to reduce skew and its variations in buffered clock networks
Security Policy Enforcement in Modern SoC Designs
Technology mapping for domino logic
Industrial experiences with resource management under software randomization in ARINC653 avionics environments
A new integer linear programming formulation for the scheduling problem in data path synthesis
Noise Analysis of Phase-Locked Loops
Sustainable High-Performance Instruction Selection for Superscalar Processors
Built-in current testing-feasibility study
Estimation of circuit activity considering signal correlations and simultaneous switching
Incorporating cut redistribution with mask assignment to enable 1D gridded design
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Timing model extraction for sequential circuits considering process variations
A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis
IC/IP piracy assessment of reversible logic
NetBench: A Benchmarking Suite for Network Processors
Security against hardware Trojan through a novel application of design obfuscation
Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems
Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach
An accurate and efficient performance analysis approach based on queuing model for network on chip
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
Fast physics-based electromigration checking for on-die power grids
GPCAD: a tool for CMOS op-amp synthesis
BITLUME: Precision-Flexible Photonic Computing for Ultra-Fast and Energy-Efficient DNN Acceleration
HAML-SSD: A Hardware Accelerated Hotness-Aware Machine Learning based SSD Management
Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs
Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management
New Simulation Methods for MOS VLSI Timing and Reliability
PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning Workloads
Compiled symbolic simulation for systemC
Approximation-aware rewriting of AIGs for error tolerant applications
Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation Platform
SLIM: A System for ASIC Library Management
Over-the-cell channel routing
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise
Detecting Hardware Trojans in Manufactured Chips without Reference: A GMM-Based Approach
A flow-based user interface for efficient execution of the design cycle
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs
Accelerating high-level bounded model checking
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation
Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography
Analysis of watermarking techniques for graph coloring problem
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's
Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
Resilience in computer systems and networks
Configurable analog routing methodology via technology and design constraint unification
Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures
TritonRoute: an initial detailed router for advanced VLSI technologies
Weighted control scheduling
RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats
Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
Vulnerability-tolerant secure architectures
Toward Metrics of Design Automation Research Impact
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
Graph Neural Networks for Idling Error Mitigation
Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture
A novel net weighting algorithm for timing-driven placement
Power-switch routing for coarse-grain MTCMOS technologies
Automatic compositional minimization in CTL model checking
From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance
An exact solution to simultaneous technology mapping and linear placement problem
Invited Paper: Towards the Efficiency, Heterogeneity, and Robustness of Edge AI
A spike-based long short-term memory on a neurosynaptic processor
Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel
Physics-Aware Differentiable Discrete Codesign for Diffractive Optical Neural Networks
Correct-by-construction microarchitectural pipelining
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks
Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
Application of Boolean Unification to Combinational Logic Synthesis
On diagnosis and correction of design errors
A clock distribution scheme for nonsymmetric VLSI circuits
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations
NID: processing binary convolutional neural network in commodity DRAM
Transforming an arbitrary floorplan into a sliceable one
PTrace: Derivative-free local tracing of bicriterial design tradeoffs
Metrics, techniques and recent developments in mixed-signal testing
Constraints-aware Adaptive Routing with Hybrid Waveguides for Photonic Integrated Circuits
FATE: fast and accurate timing error prediction framework for low power DNN accelerator design
Analog circuit synthesis for performance in OASYS
Synthesizing sequential register-based computation with biochemistry
A Processing-using-Memory Architecture for Commodity DRAM Devices with Enhanced Compatibility and Reliability
Fast IR Drop Estimation with Machine Learning : Invited Paper
Efficient modeling of switch-level networks containing undetermined logic node states
Archer: a history-driven global routing algorithm
On average power dissipation and random pattern testability of CMOS combinational logic networks
Data locality enhancement for CMPs
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Network coding for routability improvement in VLSI
Phase noise in oscillators: DAEs and colored noise sources
CAMA: A Multi-Valued Satisfiability Solver
Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients
ForTER: a forward error correction scheme for timing error resilience
Analog Macromodeling using Kernel Methods
High-level synthesis with distributed controller for fast timing closure
FedSwap: A Federated Learning based 5G Decentralized Dynamic Spectrum Access System
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels
Probabilistic Design Verification
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms
Minimum crosstalk channel routing
TASA: toolchain-agnostic static software randomisation for critical real-time systems