yusuke1997/dblp-id-title huggingface dataset:
Accelerate NDN name lookup using FPGA: Challenges and a scalable approach
UltraSONIC: A Reconfigurable Architecture for Video Image Processing
An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Self-Testing of Linear Segments in User-Programmed FPGAs
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA
Specialized Hardware for Deep Network Packet Filtering
A 11 GHz FPGA with Test Applications
MILP-based Placement and Routing for Dataflow Architecture
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication
A two step hardware design method using CλaSH
FastPath: Towards Wire-Speed NVMe SSDs
A case study of partially evaluated hardware circuits: Key-specific DES
FPGA Implemenation of Multi-layer Perceptrons for Speech Recognition
Gene Matching Using JBits
Real-Time Computation of the Generalized Hough Transform
Run-time power gating in hybrid ARM-FPGA devices
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor
Mutable Codesign for Embedded Protocol Processing
Generating high-performance custom floating-point pipelines
A Processor for Artificial Life Simulation
Speed Records in Network Flow Measurement on FPGA
Morphable Multipliers
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata
Robust and flexible FPGA-based digital PUF
Model Checking Reconfigurable Processor Configurations for Safety Properties
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology
A Superscalar and Reconfigurable Processor
Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM Arrays
Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
FPGA QAM Demodulator Design
A Scalable Architecture for RSA Cryptography on Large FPGAs
Implementation Approaches for Reconfigurable Logic Applications
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs
Extra-dimensional Island-Style FPGAs
Packet processing on FPGA SoC with DPDK
Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification
Compiling Application-Specific Hardware
Caching in Real-time Reconfiguration Port Scheduling
A General Hardware Design Model for Multicontext FPGAs
FSM Decomposition for Low Power in FPGA
FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric
An implementation of list successive cancellation decoder with large list size for polar codes
Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller
Adaptive precision technique for genetic algorithms
CPU-independent Assembler in an FPGA
FPGA-Based Simulated Bifurcation Machine
TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs
Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms
The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns
Stochastic Simulation for Biochemical Reactions on FPGA
Coarse-grained dynamically reconfigurable architecture with flexible reliability
Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs
Using island-style bi-directional intra-CLB routing in low-power FPGAs
FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding
High-speed regular expression matching engine using multi-character NFA
High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform
An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay
A radix-8 complex divider for FPGA implementation
Optimising explicit finite difference option pricing for dynamic constant reconfiguration
An FPGA Solver for Very Large SAT Problems
The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures
FPGA Implementations of the RC6 Block Cipher
EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits
Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators
Specification and Synthesis of Complex Arithmetic Operators for FPGAs
Communication Synthesis in a multiprocessor environment
Self-Healing Circuits for Space-Applications
Heterogeneous Platform for Stream Based Applications on FPGAs
Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits
The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer
Low-cost, high-performance branch predictors for soft processors
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures
An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics
Dynamic Memory Sub-System for Reconfigurable Platforms
Dataflow supercomputing
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use
Integer Programming for Partitioning in Software Oriented Codesign
Applying the Small-World Network to Routing Structure of FPGAs
Reconfigurable Hybrid Architecture for Web Applications
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA
High Speed Computation of Three Dimensional Cellular Automata with FPGA
A Segmentation Model for Partial Run-Time Reconfiguration
Using Multiplexers for Control and Data in D-Fabrix
Wormhole Computing in Networks-on-Chip
Exploring FPGA network on chip implementations across various application and network loads
Loop unrolling and shifting for reconfigurable architectures
Measuring Long Wire Leakage with Ring Oscillators in Cloud FPGAs
Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks
Compiling Regular Arrays onto FPGAs
Area-Optimized Technology Mapping for Hybrid FPGAs
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches
REFLIX: A Processor Core for Reactive Embedded Applications
SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs
Analytical Framework for Switch Block Design
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function
A soft-core processor for finite field arithmetic with a variable word size accelerator
Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA
Fault Characterization Through FPGA Undervolting
Equivalence Verification of FPGA and Structured ASIC Implementations
High Throughput Serpent Encryption Implementation
Arithmetic core generation using bit heaps
Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs
Spiking Row-by-Row FPGA Multi-Kernel and Multi-Layer Convolution Processor
Exploiting run-time reconfiguration in stencil computation
A Parallel Pipelined SAT Solver for FPGAs
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry
A Design Flow to Map Parallel Applications onto FPGAs
A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware
A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis
Stress-Aware Module Placement on Reconfigurable Devices
An image processing library for C-based high-level synthesis
Storing Parquet Tile by Tile: Application-Aware Storage with Deduplication
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons
FPGA-Aware Garbage Collection in Java
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices
Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p)
Confiuartion Management in the Context of Self Adapative Systems
CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools
A Dynamically Reconfigurable Queue Scheduler
Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition
Configurable and scalable belief propagation accelerator for computer vision
A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs
High-level synthesis for medical image processing on Systems on Chip: A case study
StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs
A survey on reconfigurable accelerators for cloud computing
Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations
A single-precision compressive sensing signal reconstruction engine on FPGAs
A Thermal Management and Profiling Method for Reconfigurable Hardware Applications
System-Level Modelling for Performance Estimation of Reconfigurable Coprocessors
The Proper Use of Hierarchy in HDL-Based High Density FPGA Design
Disjoint Pattern Enumeration for Custom Instructions Identification
DyRACT: A partial reconfiguration enabled accelerator and test platform
Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming
Over effective hard real-time hardware tasks scheduling and allocation
A new self-adapting architecture for feature detection
Real-Time Evaluation of Remote Sensing Data on Board of Satellites
Evaluation and Design of Processor-Like Reconfigurable Architectures
Hardware Support for Broadcast and Reduce in MPSoC
Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
A hardware security scheme for RRAM-based FPGA
FPGA Interconnect Fault tolerance
Self-organizing multi-cue fusion for FPGA-based embedded imaging
Generating Layouts for Self-implementing Modules
An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor
The Proteus Processor - A Conventional CPU with Reconfigurable Functionality
LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators
Fast Region Labeling on the Reconfigurable Platform ACE-V
FPGA Implementations of Neural Networks - A Survey of a Decade of Progress
Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA
An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction
Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform
Scavenger: Automating the construction of application-optimized memory hierarchies
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs
Ready PCIe data streaming solutions for FPGAs
ILP-Based Modulo Scheduling and Binding for Register Minimization
A Runtime Reconfigurable Implementation of the GSAT Algorithm
Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
A comparison of real-time 4K/UltraHD connected component labelling architectures
Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions
Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations
Branch Optimisation Techniques for Hardware Compilation
JBits TM Implementations of the Advanced Encryption Standard (Rijndael)
A Congestion Driven Placement Algorithm for FPGA Synthesis
High Speed Computation of Lattice gas Automata with FPFA
Rapid and Reliable Routability Estimation for FPGAs
On Computing Maximum Likelihood Phylogeny Using FPGA p
DiAD - Distributed Acceleration for Datacenter FPGAs
A Karatsuba-Based Montgomery Multiplier
An XDL alternative for interfacing RapidSmith and Vivado
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter
FPGA Accelerated FPGA Placement
FPGA Implementation of Biometric Authentication System Based on Hand Geometry
FPGA acceleration of short read mapping based on sort and parallel comparison
Failure Probability and Fault Observability of SRAM-FPGA Systems
Formal Modeling of Process Migration
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers
Power and Area Optimization for Multiple Restricted Multiplication
Ultrasmall: The smallest MIPS soft processor
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS
Increasing Flexibility of Cloud FPGA Virtualization
Pipelined FPGA Adders
Exploration of Design Space in ECDSA
Memory efficient IP lookup in 100 GBPS networks
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core
Architecture and CAD for FPGA Clock Networks
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System
Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case
Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools
A semi-supervised modeling approach for performance characterization of FPGA architectures
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
Floating-Point Trigonometric Functions for FPGAs
doppioDB: A hardware accelerated database
Testable Clock Routing Architecture for Field Programmable Gate Arrays
Executing Hardware as Parallel Software for Picoblaze Networks
Comparing throughput and power consumption in both sequential and reconfigurable processors
The evolution of architecture exploration of programmable devices
22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012
The Design of a Stack-Based Microprocessor
Numerical function generators using bilinear interpolation
A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications
An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution
Design Experience with Fine-Grained FPGAs
DIF-LUT: A Simple Yet Scalable Approximation for Non-Linear Activation Function on FPGA
Sliding block Viterbi decoders in FPGA
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware
A New Placement Method for Direct Mapping into LUT-Based FPGAs
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance
Automated synthesis of FPGA-based heterogeneous interconnect topologies
Accurate power control and monitoring in ZYNQ boards
Hardware-software implementation of a DNN for 3D object detection using FINN - a demo
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs
FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning
An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Energy efficient architecture for matrix multiplication on FPGAs
A Smith-Waterman Systolic Cell
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates
On-FPGA Communication Architectures and Design Factors
Mapping of DSP Algorithms on Field Programmable Function Arrays
Runtime assertions and exceptions for streaming systems
A high performance and low energy intra prediction hardware for High Efficiency Video Coding
Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers
Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays
Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer
Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
Demonstration of Flow-in-Cloud: A Multi-FPGA System
The XC6200DS development system
High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic
Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors
Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs
High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration
Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays
Reconfigurable DSP Demonstrators for the Development of Spacecraft Payload Processors
Profiling FPGA floor-planning effects on timing closure
A combination of multi-edge coding and independent coding lines for time-to-digital conversion
An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration
Dual MicroBlaze rekeying processor for group key management
Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters
A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC
Evolutionary Search Applied to Reconfigurable Analogue Control
A Self-Validating Temperature Sensor Implemented in FPGAs
An operating system for custom computing machines based on the Xputer paradigm
Hthreads: A Computational Model for Reconfigurable Devices
Object Oriented Programming Paradigms for the VHDL
Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs
FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head
Multi-core for K-means clustering on FPGA
Automated Trust Negotiation for Cloud Applications in Identity-as-a-Service
Statistical Characterization of the Multicluster Two-Wave Fading Model
Towards Enhancement of Network Communication Architectures and Routing Protocols for FANETs: A Survey
Physical-Layer Security over Generalized SIMO Multipath Fading Channels
Managing Security Policies within Cloud Environments Using Aspect-Oriented State Machines
Performance Evaluation of Relaying with Different Relay Selection Schemes in 5G NR V2X Communications
A Constructive Analysis on Machine Learning Integration in High Delay Tolerant Networking (HDTN)
Triple-Layer Image Security Using a Zigzag Embedding Pattern
Achievable Fixed Rate Capacity in Emerging Wireless Systems (Invited Paper)
Dynamics of network connectivity in tactical MANETs
A Wind Speed-Driven Approach to Round Earth Loss Modeling for Maritime Communications
Developing Mask R-CNN Framework for Real-Time Object Detection
Generalization of Space-Time Block Coded-Spatial Modulation for High Data Rate VLC Systems (Invited Paper)
Smart Nest Box: IoT Based Nest Monitoring In Artificial Cavities
A Comparative Study of Supervised Learning Algorithms for Spiking Neural Networks
Analysis of Blockchain Integration in the e-Healthcare Ecosystem
Early Malware Characterization based on Online Social Networks
Feedback overhead comparison between frequency SVD and time domain beamforming in WLAN context
Capacity Higher-Order Statistics Analysis for κ - µ Fading Channels with Correlated Shadowing
Uplink Spectral Efficiency of Cell Free Massive MIMO based on Stochastic Geometry Approach
Substitution Box Design Based on Chaotic Maps and Cuckoo Search Algorithm
An Importance Sampling Method for Monte-Carlo Integration Model for Ultraviolet Communication
Performance Analysis of DF Based Cascaded VLC-FSO-VLC System
A Note on an elementary Operator with Quasi-M-Hyponormal Operator Entries
Effect of Generalized Multipath/Shadowing Channels on Fixed Rate Wireless Systems
Statistical Analysis Of Uplink Massive MIMO Systems For MRC Linear Receivers Over Weibull Fading Channels
Simulations of Indoor Transmission in 73-142 GHz
Analysis of Superimposed LoRa in Multi-User Networks
David and Goliath: Asymmetric Advantage in MIoT
An SDN Solution For a GEO and LEO Satellite Transceiver Based on GNU Radio Companion
Towards an SDN-based Reconfigurable Edge Architecture for Railway Environment
Channel Impulse Response Peak Clustering Using Neural Networks
Sign Language Recognition of Autistic Children using Wearable Sensors Signals Features Selection
Point Cloud Streaming over HTTP/2
7th International Conference on Advanced Communication Technologies and Networking, CommNet 2024, Rabat, Morocco, December 4-6, 2024
Novel Lightweight Method for Detecting Backdoor Attacks in Edge-Deployed Neural Networks
Security Challenges in Integrating BIoT Systems: A Comprehensive Review
Towards a Clustering-Based Approach to Speed up IaaS Service Discovery Process
Smart Sensor Node of WSNs for River Water Pollution Monitoring System
MQTT-MTD: Integrating Moving Target Defense into MQTT Protocol as an Alternative to TLS
Edge Computation for SDR-SDN
5th International Conference on Advanced Communication Technologies and Networking, CommNet 2022, Marrakech, Morocco, December 12-14, 2022
On Order Gelfand-Phillips Property And Order Limited Completely Continuous Operators
IoT and Blockchain Integration Security
4th International Conference on Advanced Communication Technologies and Networking, CommNet 2021, Rabat, Morocco, December 3-5, 2021
Interoperability Between Heterogeneous Multi-agent Systems Recommended by FIPA: Towards a Weakly Coupled Approach Based on a Network of Recurrent Neurons of the LSTM type
Accurate Approximations for the Ratio of Sums of Independent Rayleigh Random Variables
Crowdsourcing: Modeling Techniques and Comprehensive Studies
A Classifier to Detect Number of Machines Performing DoS Attack Against Arduino Oplà Device in IoT Environment
RRI Adaptive: A Standards Compliant Approach for Equitable and Stable Congestion Control in C-V2X Networks
Performance Assessment of Intelligent Reflective Surfaces-aided Network with Residual Hardware Impairments
On the Class of Absolutely Weakly Compact Operators
Blockchain-based Model Against selfish Attacks in Mobile ad hoc Networks
Modulation Schemes for Visible Light Communications
Impulsive Noise Parameter Estimation: A Deep CNN-LSTM Network Approach
Evaluating Machine Learning Algorithms for Intrusion Detection: A Step Toward Securing Real-Time Big Data
Secrecy outage probability in cognitive radio networks subject to Rayleigh fading channels
Performance Evaluation of Mixed RF-UOWC System with Residual Hardware Impairments
Suppression of calculi growth based on the mathematical model of the pathogenesis of urolithiasis
An Inexpensive but Smart MAC-Address Based Attendance Monitoring System
RevoCampus: a Distributed Open Source and Low-cost Smart Campus
Bit error probability analysis for majority logic decoding of CSOC codes over fading channels
An Enhanced Authentication Protocol based Group for Vehicular Communications over 5G Networks
Network Traffic Monitoring and Analysis Using Packet Sniffer
Optimized Energy Management with Fuzzy Clustering for Heterogeneous Fog-Mist-IoT Networks
Simulations of Point-to-Point Outdoor Transmission in 95-110 GHz
Workload Allocation in Fog Environment Using Multi-Objective Evolutionary Algorithms for Internet of Things
On the Performance of NOMA-Enabled V2V Communications Under Joint Impact of Nodes Mobility and Channel Estimation Error
Complexity analysis on 5G Candidate waveforms for DVB-T2: A survey