yusuke1997/dblp-id-title huggingface dataset:
A 1.13μJ/Classification Spiking Neural Network Accelerator with a Single-Spike Neuron Model and Sparse Weights
An Analog Smart Sensor for Active Obstacle Detection
An audio signal scaling technique harmonic grouping and shifting
Design of High Accuracy Video Comparator
A 1-D local image velocity sensor using Gabor filtering
Energy-Efficient Data Symbol Detection via Boosted Learning for Multi-Actuator Data Storage Systems
A compensation technique for compact low-voltage low-power active-RC filters
Memory optimization techniques for UMTS code generation
Low-Power Ethanol Sensor Read-Out Circuit using a-InGaZnO TFTs
A genetic approach to analog module placement with simulated annealing
A simple modeling of the early voltage of MOSFETs in weak and moderate inversion
An efficient finite precision realization of the block adaptive decision feedback equalizer
Using Filters for Chaotic Synchronization for Communications
Characterization and modeling of reliability issues in nanoscale devices
Performance of a multiple-access DCSK-CC system over Nakagami-m fading channels
Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area
Design and analysis of skewed-distribution scan chain partition for improved test data compression
3-Coil Inductive-Link for Capsule-Sized Cardiac Leadless Pacemaker and Endoscopy Systems
Design of a spatiotemporal correlation filter for event-based sensors
HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules
An Improved Algorithm for Real-Time Dual-View Display
Analysis of time-controlled switched systems using stability preserving mappings
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML
Live demonstration: High fill factor CIS based on single inverter architecture
Low swing TSV signaling using novel level shifters with single supply voltage
Terminal dynamics approach to cellular neural networks
Sequential blind extraction of instantaneous mixtures with arbitrary rank
Efficient Transmitter Self-Calibration and Amplifier Linearization Techniques
Bifurcation Phenomena from a Simple Hysteresis Network
D 2 Buck Converter With Delay-Insensitive Response and Adaptive On-Time Extension During Load Transient
Analytical design of digital nonrecursive maximally flat fractional Hilbert transformer
Multiplierless implementation of recursive digital filters based on coefficient translation methods in low sensitivity structures
A 172.5dB-FoM Hybrid CT/DT Incremental Σ∆Modulator for Direct Current-to-Digital Conversion
A VLSI chip for wavelet image compression
Epistemic utility estimation with valuational convexity
A Body Channel Communication Transceiver System Utilizing Manchester Code for WBAN with Multi-sensor Nodes
Floating gate synapses with spike time dependent plasticity
Two-Dimensional Paraunitary Cosine Modulated Perfect Reconstruction Filter Banks
Delta-sigma modulated class D ZCS series resonant inverter with an inductive load
Bluetooth low energy receiver system design
A 6.42 mW low-power feed-forward FxLMS ANC VLSI design for in-ear headphones
An asynchronous time-based image sensor
Redefining the relationship between scalar and parallel units in SIMD architectures
Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field Sensing
A Scalable Built-in Self-test/Self-diagnosis Architecture for 2D-Mesh based Chip Multiprocessor Systems
A 1-V 12-bit switched-op amp pipelined ADC with power optimization
FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-photon Avalanche Diode Array
A CMOS Image Sensor with Improved Readout Speed using Column SAR ADC with Digital Error Correction
On the fault diagnosis in the presence of unknown fault models using pass/fail information
A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm
An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots
Non-average performance of chaos-based DS-CDMA: a tensor approach to analytical any-order correlation of spreading sequences
High-Speed and Low-Cost Structures for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters
High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding
Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic Approach
Improving the power-delay product in SCL circuits using source follower output stage
A subharmonic detrending or data-smoothing approach for longitudinal road profile measurements
Security analysis of rakeness-based compressed sensing
Generating Adversarial Patches Using Data-Driven MultiD-WGAN
Synchronization in arrays of fuzzy chaotic oscillators
Improvement in Stability and Convergence Speed on Normalized LMS Algorithm
Novel oversampled A/D converters based on error spectrum shaping
Ultra Low Power SIMON Core for Lightweight Encryption
A frequency domain based TEQ design for DSL systems
Distributed control for link failure based on tie-sets in information networks
Summation Invariant Multi-region Fusion Comparison
Spike timing dependent adaptation for mismatch compensation
A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta Modulator
An efficiency-enhanced wireless power transfer system with segmented transmitting coils for endoscopic capsule
Adaptation algorithms for a class of continuous time analog equalizers with application to serial links
A Single Signal Controlled Dual-band VCO for WiMAX Applications
A multiple-candidate-regeneration-based object tracking system with enhanced learning capability by nearest neighbor classifier
A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability
A Simultaneous Div-Curl 2D Clifford Fourier Transform Filter for Enhancing Vortices, Sinks and Sources in Sampled 2D Vector Field Images
Stochastic Resonance Mixed-Signal Processing: Analog-to-Digital Conversion and Signal Processing Employing Noise
A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors
A low-power motion compensation IP core design for MPEG-1/2/4 video decoding
Low complexity adaptive step-size filtered gradient-based per-tone DMT equalisation
A fully differential CMOS self-biased two-stage preamplifier-latch threshold detection comparator
A high-speed converter with light-load improvement circuit and transient detector
Equivalent circuit models for stacked spiral inductors in deep submicron CMOS technology
Reconstruction of nonuniform sampled bandlimited signals using digital fractional filters
Nullators and norators in circuits education: A benefit or an obstacle?
An I DDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs)
Identification of soft error glitch-propagation paths: Leveraging SAT solvers
SNDR sensitivity analysis for cascaded ΣΔ modulators
Cluster Synchronization and Associative Memory in Adaptive Networks with Neural Plasticity
Gated direct sequence spread spectrum clocking scheme for multimedia systems
A novel technique for the design and DCGA optimization of bilinear-LDI lattice-based digital IF filters
Extortion Strategies with Mutation Promote Cooperation on High Clustered Scale-Free Networks
Trajectory kinematics descriptor for trajectory clustering in surveillance videos
A 20 Gbps 1-tap decision feedback equalizer with unfixed tap coefficient
A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery
Dichromatic spectral measurement circuit in vanilla CMOS
A high-speed low-power calibrated flash ADC
A Stimulation Artifacts Removal Technique Employing VCO and Phase Detector for Simultaneous Neural Stimulation and Recording
On explicit solutions of nonlinear dynamic systems
Digitized n-scroll attractor model for secure communications
Improved wavelet based a-priori SNR estimation for speech enhancement
Multilevel error correction scheme for MLC flash memory
Optimal resource allocation under TCP Reno and Vegas in complex communication networks
New algorithm for minimax design of sparse IIR filters
A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators
Low Complexity Deep Learning Aided Channel Estimation Architecture for Vehicular Networks
Scalable and Real-Time Power System Simulation Based on Heterogeneous CPU-FPGA Co-operation
Lost transform domain data concealment in GenLOT based coders
Blind dereverberation using correlation coefficients considering periodicity of voiced speech
Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction
A neural networks based system for post pulse fault detection and disruption data validation in tokamak machines
A new Petri net based model of data transfers in the PC workstation memory hierarchy for MPEG encoding
Sequential Node Attack of Complex Networks Based on Q-Learning Method
An Overshoot Voltage Reduction Technique with Improved Speed for Zero-Crossing Detector in Pipeline ADCs
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators
A 150nW CMOS novel temperature sensor for remote patient monitoring based on an auto-resonant active inductor architecture
Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs
An S-band SiGe BiCMOS Transmitter for an NV Center Based Quantum Magnetometer
Light Field Image Quality Assessment Based on Disentangling Bayesian Theory
Region Motion-based Adaptive Composite Long-Term Reference Coding for VVC
Adjustable Output CMOS Voltage Reference Design
Region-based weighted prediction algorithm for H.264/AVC video coding
Scavenging thermal-noise energy for implementing long-term self-powered CMOS timers
Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems
An arbitrarily skewable multiphase clock generator combining direct interpolation with phase error average
A hierarchical IP protection approach for hard IP cores
Design and Implementation of 0.8-V Active RC Polyphase Filter using 0.18-µm CMOS Inverters with Resistive Level Shifter
Time borrowing in high-speed functional units using skew-tolerant domino circuits
A comparison of architectures for a programmable fuzzy logic chip
A 94.1dB-DR 40kHz-BW Continuous-Time Delta-Sigma Modulator with Current-reused Amplifiers
Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs
A unified design methodology for a hybrid wireless 2-D NoC
A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication
Authentication Protocol for Secure Automotive Systems: Benchmarking Post-Quantum Cryptography
Design and implementation of a direct RF-to-digital UHF-TV multichannel transceiver
DeepTune: Robust Global Optimization of Electronic Circuit Design Via Neuro-Symbolic Optimization
Single underwater image restoration using attenuation-curve prior
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC
Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads
Cellular Automata with Large Channel Separations
Hybrid color compensation for virtual view synthesis in multiview video applications
Optimal design of FIR filter with discrete coefficients based on integer semi-infinite linear programs
Implementation of Structural Synchrony and Linear Measures of Brain Network Connectivity for Real-Time State Estimation
Hyperchaotic 3D-scroll attractors via Hermite polynomials: the Adomian decomposition approach
Current-mode memory cell with power down phase for discrete time analog iterative decoders
On Multidimensional Linear Phase Perfect Reconstruction Filter Banks
Automated Detection and Rectification of Defects in Fluid-Based Packaging using Machine Vision
Efficiency-oriented switching frequency tuning for a buck switching power converter
Territorial Marking for Improved Area Coverage in Anti-Flocking-Controlled Mobile Sensor Networks
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method
Live Demonstration: A Pencil Balancing Robot using a Pair of AER Dynamic Vision Sensors
A Linear Model for YUV 4: 2: 0 Chroma Intra Prediction
A traffic aware, energy efficient MAC protocol for wireless sensor networks
Training Radial Basis Function Networks with Perturbation Methods
Leveraging Image Difficulty for Run-Time Adaptive DNN Inference on Embedded Devices
New Charge-Steering Latches in 28nm CMOS for Use in High-Speed Wireline Transceivers
1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology
A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm
A Two-Stage Scheme for Lossless Compression of Images
Towards Efficient Hardware Implementation of NTT for Kyber on FPGAs
CMOS current-mode analog circuit building blocks for rf DC-DC converter controllers
B-spline factorization-based architecture for inverse discrete wavelet transform
Fast block-size partitioning using empirical rate-distortion models for MPEG-2 to H.264/AVC transcoding
Power System Emulator Based on PLL Architecture
A novel affine projection algorithm for superdirective microphone array beamforming
A New Decimal Antilogarithmic Converter
Controlling an integrator through data networks: stability in the presence of unknown time-variant delays
PUF-based Edge DNN Model IP Protection with Self-obfuscation and Publicly Verifiable Ownership
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit
A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement
A 24nW, 0.65-V, 74-dB SNDR, 83-dB DR, class-AB current-mode sample and hold circuit
Performance improvements on MEFX-LMS based noise cancellation system in vehicle cabin
Design and evaluation of a microcantilever aptasensor
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling
A crosstalk aware two-pin net router
Sliding window online Kernel-based classification by projection mappings
Roundoff noise minimization for 2-D separable-denominator digital filters using jointly optimal high-order error feedback and realization
NeuroBus - Architecture and Communication Bus for an Ultra-Flexible Neural Interface
Computational method of stability investigation for large analog circuits
FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements
Characteristics and modelling of PEM fuel cells
A Vision-based People Counting Approach based on the Symmetry Measure
Building Blocks for a Temperature-Compensated Analog VLSI Neural Network with On-Chip Learning
A new congestion and crosstalk aware router
Low-effort high-performance viterbi-based receiver for Bluetooth LE applications
Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization
Low-Complexity Systolic Multiplier for GF(2 m ) using Toeplitz Matrix-Vector Product Method
Live demonstration: A CMOS-based ISFET array for rapid diagnosis of the Zika virus
A design of error robust scalable coder based on MPEG-4/Audio
A simple CMOS bandgap reference circuit with sub-1-V operation
An Ultra Low Power CMOS MPPT Power Conditioning Circuit for Energy Harvesters
A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process
Pulse-excited RC nonautonomous chaotic oscillator structures
Enhancing SNN Training Performance: A Mixed-Signal Triplet Reconfigurable STDP Circuit with Multiplexing Encoding
Ultra-low power sensor platform with wireless charging system
Frequency Estimation for Resonant MEMS Sensors
VLSI Architectures for Hierarchical Block Matching
Using Deep Learning to Extract Scenery Information in Real Time Spatiotemporal Compressed Sensing
Global image representation using Locality-constrained Linear Coding for large-scale image retrieval
Colour calibration for colour reproduction
A CMOS imager for light blobs detection and processing
On-chip RC measurement and calibration circuit using Wheatstone bridge
Development of a dynamic routing system for a fault tolerant solid state mass memory
Efficient event-driven approach using synchrony processing for hardware spiking neural networks
A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm
At-speed testing of data communications transceivers
Software based separation of amplitude and phase noises in time domain
Real-time inference in a VLSI spiking neural network
Super-regeneration-inspired time-based testing of LC-tank oscillators
An analogue SIMD focal-plane processor array
Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method
Flexible hydrogel actuated graphene-cellulose biosensor for monitoring pH
A 49.7-fs, 10.29-to-12.75 GHz Fractional-N ADPLL with a New Quad-Core Class-F3 Oscillator
A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications
CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter
A 6.78MHz Dual-Output Wireless Transfer System With Adaptive Global Power Control for Efficiency Enhancement
Local-Aware Intra Block Copy for Video Coding
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array
A Switched-Current Sigma Delta Converter for Direct Photodiode Interfacing
Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP
Cascode and transconductance with capacitances feedback compensation for multistage amplifiers driving no load and 1nF capacitive load
Block-Interleaved Error-Resilient Entropy Coding
An optimization-based tool for the high-level synthesis of discrete-time and continuous-time ΣΔ modulators in the Matlab/Simulink environment
Direct Sequential Evaluation of Hermite-Gaussian-like Eigenvectors of the DFT Matrix
A high-performance low-power SoC for mobile one-time password applications
Model and design considerations for multistage electrostatic microgenerators
Hardware acceleration of the robust header compression (RoHC) algorithm
Frequency-Domain Analysis of DC/DC Converters Using a Symbolic Approach
A regulated 3.1-10.6 GHz linear dual-tuning differential ring oscillator for UWB applications
Distortion analysis of periodically switched nonlinear circuits
Performance optimization for high-order continuous-time ΣΔ modulators with extra loop delay
New switch-mode topology for VAR compensation
Content adaptive motion estimation for mobile video encoders
CMOS monolithic chemiresistor array with microfluidic channel for micro gas chromatograph
Why area might reduce power in nanoscale CMOS
VMAF Oriented Perceptual Optimization for Video Coding
Design procedure for wireless power transfer system with inductive coupling-coil optimizations using PSO
Live Demonstration: 4 × 4 Memristive Cellular Nonlinear Network in EDGE detection operation
Haze Removal with Fusion of Local and Non-Local Statistics
On-chip active power rectifiers for biomedical applications
Filter structures for decimation: a comparison
Wide linear range voltage-controlled delay unit for time-mode signal processing
Low leakage power NoC switch using AVC
A set-membership NLMS algorithm with time-varying error bound
4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality
Adaptive Video Coding using Mixed-Domain Filter Banks having Optimal-Shaped Subbands
An ultra low-power low-voltage class AB CMOS fully differential OpAmp
A low-power low-noise CMOS voltage reference with improved PSR for wearable sensor systems
A high temporal resolution multiscale recording system for in vivo neural studies
Optimizing bandwidth power efficiency of a CMOS transconductor
NURODE: In-Memory Crossbar Core for Hodgkin-Huxley Model ODE-Based Computations
A switched gain cell parametric amplifier
A new approach of group-based VLC codec system
Ultra-low-power 2.4 GHz Colpitts oscillator based on double feedback technique
A 128-Point Multi-Path SC FFT Architecture
Ultra-low power flip-flops for MTCMOS circuits
Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication Applications
OMP-based transform for inter coding in HEVC
Combined NIRS-EEG remote recordings for epilepsy and stroke real-time monitoring
Intelligent approach for PET volume analysis
Macroblock-based reverse play algorithm for MPEG video streaming
On Securing Scan Design Through Test Vector Encryption
An efficient VLSI architecture for rate disdortion optimization in AVS video encoder
On the reuse of existing error tolerance circuitry for low power scan testing
Energy-Efficient Spiking-CNN-Based Cross-Patient Seizure Detection
Stochastic resonance of a threshold detector: image visualization and explanation
A novel reseeding mechanism for pseudo-random testing of VLSI circuits
A 12-B 10-msamples/s CMOS switched-current delta-sigma modulator
Performance Driven Routing with Mulitiple Sources
Analysis of Calibration Requirements in Image Recognition Tasks with Time-Encoded ANNs
High-Efficient Reed-Solomon Decoder Based on Deep Learning
Design of a Single-Event Upset Tolerant Low-Power Double-Tail Comparator
A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique
Synthesizing checkers for on-line verification of System-on-Chip designs
A New Block-Oriented Model for Reduced Complexity Digital Predistortion in Wideband Applications
Computation of unstable limit cycles in large-scale power system models
Live Demonstration: Capturing Short-Lived Currency Arbitrage Opportunities with a Simulated Bifurcation Algorithm-Based Trading System
Analysis of Coil Misalignment Issue in Resonance-based Wireless Power Transmission System for Implantable Biomedical Applications
Theory and Implementation of an Analog-to-Information Converter using Random Demodulation
Efficiency enhancement techniques and a dual-band approach in RF rectifiers for wireless power harvesting
A zerotree stereo video encoder
A new orthogonal online digital calibration for time-interleaved analog-to-digital converters
Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach
Analysis of template matching prediction and its application to parametric overlapped block motion compensation
Leakage power reduction for clock gating scheme on PD-SOI
A sub-ranging 2-Step 7-bit self-calibrated comparator-based binary-search ADC
Design and Implementation of a Memristor-Based Oscillator
A low-voltage MOSFET-only Sigma-Delta modulator for speech band applications using depletion-mode MOS-capacitors in combined series and parallel compensation
Self-biasing low power adaptive photoreceptor
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering
Content Distribution Network for Streaming Using Multiple Galois Fields
Multi-frame motion estimation: application to motion compensated prediction
VLSI implementation of wireless bi-directional communication circuits for micro-stimulator
An Adaptive Optimization Method for LFOD Enhancement in DFIG Integrated Smart Grids
A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor
A compact ultra-low power physical unclonable function based on time-domain current difference measurement
A generic programmable arbiter with default master grant
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process
Tidbits on tunable analog filters and image demosaicing
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration
Conversion of analog to spiking neural networks using sparse temporal coding
Scalability of weak consistency in NoC based multicore architectures
DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking
A system-on-chip FPGA design for real-time traffic signal recognition system
Automatic word-level abstraction of datapath
A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor
Prototype implementation of a WWW based analog circuit design tool
Map automatic input based on NN and GAs