yusuke1997/dblp-id-title huggingface dataset:
Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers
Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits
Crosstalk aware coupled line delay tree construction for on-chip interconnects
Saving Time and Energy Using Partial Flash Memory Operations in Low-Power Microcontrollers
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Cell shifting aware of wirelength and overlap
AxBy-ViT: Reconfigurable Approximate Computation Bypass for Vision Transformers
A QoS Scheduler for Real-Time Embedded Systems
Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations
Low-overhead implementation of logic encryption using gate replacement techniques
On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond
Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits
TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning
How to Retrieve PUF Response from a Fabricated Chip Securely?
Approximate Decision Trees For Machine Learning Classification on Tiny Printed Circuits
Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint
EDA-Debugger: An LLM-Based Framework for Automated EDA Runtime Issue Resolution
Luncheon Keynote Speech
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability
An efficient current-based logic cell model for crosstalk delay analysis
Evening Panel Discussion: DFM PDK's: Where Do They Belong To? Are Process Design Kits (PDKs) the Answer for Modern Design for Manufacturing (DFM) Issues?
Analyzing Internal-Switching Induced Simultaneous Switching Noise
Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test
Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation
Modeling Crosstalk Induced Delay
Stack based sense amplifier designs for reducing input-referred offset
Minimizing Inter-Clock Coupling Jitter
Towards more reliable embedded systems through a mechanism for monitoring driver devices communication
Energy efficient analog spiking temporal encoder with verification and recovery scheme for neuromorphic computing systems
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design
Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization
Quantified Impacts of Guardband Reduction on Design Process Outcomes
DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization
Hetero 2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors
Optimization in an Integrated Physical Design Flow (Tutorial Abstract)
Energy efficient biopotential acquisition unit for wearable health monitoring applications
Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System
MEMS Failure Probability Prediction and Quality Enhancement Using Neural Networks
Quantum Prometheus: Defying Overhead with Recycled Ancillas in Quantum Error Correction
IP protection platform based on watermarking technique
Static Electromigration Analysis for Signal Interconnects
Performance Limitations of Devices and Interconnects and Possible Alternatives for Nanoelectronics
Design for Manufacturing? Design for Yield!!!
Aliasing-Free Space and Time Compactions with Limited Overhead
Slack-based approach for peak power reduction during transition fault testing
Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry
sLLM: Accelerating LLM Inference using Semantic Load Balancing with Shared Memory Data Structures
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates
Strong Anti-SAT: Secure and Effective Logic Locking
A simple array-based test structure for the AC variability characterization of MOSFETs
Functional composition: A new paradigm for performing logic synthesis
A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking
Simplicity and Executability: Cornerstones of Quality
Interconnect Delay and Slew Metrics Using the First Three Moments
Yield improvement of 3D ICs in the presence of defects in through signal vias
RTL Simulation Acceleration with Machine Learning Models
Process mismatch analysis based on reduced-order models
Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology
Overview of SiGe Technology Modeling and Application
Enabling sizing for enhancing the static noise margins
METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs
Integrated CAM-RAM Functionality using Ferroelectric FETs
A low-power configurable adder for approximate applications
Microwave III-V Semiconductors for Telecommunications and Prospective of the III-V Industry
Retrospective on electronics technology and prospective methods for co-design of IC packaging and manufacturing improvements
Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder
Effective thermal control techniques for liquid-cooled 3D multi-core processors
FPGA-based Reservoir Computing with Optimized Reservoir Node Architecture
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
Quality SoC Design and Implementation for Real Manufacturability
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition
Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics
A design-for-test apparatus for measuring on-chip temperature with fine granularity
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic
Constructive AIG optimization considering input weights
Analytical Model for the Propagation Delay of Through Silicon Vias
10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA
System Verilog for Quality of Results (QoR)
Hotspot detection using machine learning
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise
Floorplanning for high utilization of heterogeneous FPGAs
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
Sub-threshold custom standard cell library validation
Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning
Adding Manufacturability to the Quality of Results
Analysis of the Effect of Off-chip Memory Access on the Performance of an NPU System
Analysis of within-die process variation in 65nm FPGAs
A Package Design Perspective, "It will be BGA and Flip-Chip"
New electrical design verification approach for 2.5D/3D package signal and power integrity
Steering/Advisory Committee
A High-Performance Bus Architecture for Strongly Coupled Interconnects
Separation of concerns for hardware components of embedded systems in BIP
Reliability and energy-aware cache reconfiguration for embedded systems
An EDA Perspective, "Let's do it Concurrently!
Timing and Design Closure in Physical Design Flows (invited)
Closing the Gap between ASIC and Full Custom: A Path to Quality Design
Split-Slope Chaotic Map Providing High Entropy Across Wide Range
Coupling timing objectives with optical proximity correction for improved timing yield
Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature
Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural Nets
Comparative Framework for the Analysis of Thermal and Resource Management Algorithms for Multi-Core Architectures
Core Network Interface Architecture and Latency Constrained On-Chip Communication
An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools
Design Space Exploration Driven by Lifetime Concerns due to Electromigration
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur
Enhancing system-wide power integrity in 3D ICs with power gating
A Methodology for Reusable Physical Design
Extracting hardware assertions including word-level relations over multiple clock cycles
Cross-Layer EM Fault Injection Assessment Framework
Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality
Integrated circuit identification and true random numbers using 1.5-transistor flash memory
Delay insensitive code-based timing and soft error-resilient and adaptive-performance logic
Reducing the Data Switching Activity on Serial Link Buses
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range
Quality Memory Blocks -- Balancing the Trade-Offs
A Unified Statistical Analysis of Comprehensive Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs Induced by RDF, ITF, and WKF Simultaneously
Domino gate with modified voltage keeper
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis
Testing and Yield of Integrated Circuits
Low-power programmable-logic cell arrays using nonvolatile complementary atom switch
Communication limits of on-chip graphene plasmonic interconnects
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
Synthesis of Selectively Clocked Skewed Logic Circuits
Design of a Band-Pass Pseudo-2-Path Switched Capacitor Ladder Filter
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
Ultra-thin Gate Oxide Reliability and Implications for Design (Tutorial Abstract)
Comparative study of path selection and objective function in replacing NBTI mitigation logic
On the write energy of non-volatile resistive crossbar arrays with selectors
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design
DK Lock: Dual Key Logic Locking Against Oracle-Guided Attacks
Behavioral IP Specification and Integration Framework for High-Level Design Reuse
Manufacturable nanometer designs using standard cells with regular layout
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach
SpotOn: A Gradient-based Targeted Data Poisoning Attack on Deep Neural Networks
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs
A Minimum Cut Based Re-Synthesis Approach
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution
Tutorial 1: The Promise of High-Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications
Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks
Minimizing FPGA Reconfiguration Data at Logic Level
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
Tool Interoperability is Key to Improved Design Quality
Deterministic Stochastic Computation Using Parallel Datapaths
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations
Fundamental Methods to Enable SoC Design and Reuse
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks
When Machine Learning Meets Hardware Cybersecurity: Delving into Accurate Zero-Day Malware Detection
FinFET SRAM - Device and Circuit Design Considerations
Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning
A Passive 915 MHz UHF RFID Tag
Formal Verification Aware Redundant Sequential Logic Optimization to Improve Design Utilization
Design and Evaluation of Parametric NTT Hardware Unit using different Multiplier based Modular Reduction Techniques
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
Optimizing energy in a DRAM based hybrid cache
Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design
Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime
Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion
A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and Their Impact on the Design of Multi-Giga Hertz Processors (Tutorial Abstract)
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization
A survey on memristor modeling and security applications
Piecewise-Linear Approximation of Self-Attention and Its Accuracy-Aware Training for Area-Efficient Vision Transformer Inference Accelerator
Fine-Grained Redundancy in Adders
Delivering Quality Delivers Profits
Design and implementation of a sub-threshold BFSK transmitter
A 1.3µW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications
TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits
Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling
A fast and ultra low power time-based spiking neuromorphic architecture for embedded applications
Machine Learning Approach to Characteristic Fluctuation of Bulk FinFETs Induced by Random Interface Traps
Practical Clock Tree Robustness Signoff Metrics
Reliable Express-Virtual-Channel-based network-on-chip under the impact of technology scaling
Exploring Hardware Activation Function Design: CORDIC Architecture in Diverse Floating Formats
SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion
XORed Carry Chain Ring Oscillator Factored True Random Number Generator
Optimizing Quantum Embedding using Genetic Algorithm for QML Applications
High Output Resistance and Wide Swing Voltage Charge Pump Circuit
Clock routing for structured ASICs with via-configurable fabrics
SRAM supply voltage scaling: A reliability perspective
Error Protected Data Bus Inversion Using Standard DRAM Components
ESD event simulation automation using automatic extraction of the relevant portion of a full chip
Future Platform for Mobile Communication
Enabling True Design for Manufacturability
FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization
Systematic analyses for latching probability of single-event transients
Focus on Quality of Design: Does it Help or Hinder Time to Market?
Scripting for EDA Tools: A Case Study
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches
An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems
Machine Learning Assisted Magnetic-Core Coupled Inductor Design for Interleaved Buck Converter
FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training
Thermal-Aware IR Drop Analysis in Large Power Grid
Elastic Timing Scheme for Energy-Efficient and Robust Performance
Efficient trace signal selection using augmentation and ILP techniques
An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes
Efficient Hierarchical Approach to Test Generation for Digital Systems
0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives
7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA
Deep Learning-Based ASM-ESD Forward I-V Parameter Extraction
A technique to construct global routing trees for graphene nanoribbon (GNR)
Fast characterization of parameterized cell library
Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications
The combined effect of process variations and power supply noise on clock skew and jitter
Design for Testability in Nanometer Technologies; Searching for Quality
Challenges in Evaluations for a Typical-Case Design Methodology
Power Grid Planning for Microprocessors and SOCS
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
A New Flexible Algorithm for Random Yield Improvement
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix
Multi-ALM: Run-time Multi-Level Reconfigurable Approximate Logarithmic Multiplier
Quality of EDA CAD Tools: Definitions, Metrics and Directions
Efficient translation validation of high-level synthesis
SHA-3 implementation using ReRAM based in-memory computing architecture
3D-NOCET: A tool for implementing 3D-NoCs based on the Direct-Elevator algorithm
Welcome to ISQED 2013
Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations
MEMESTAR: A Simulation Framework for Reliability Evaluation over Multiple Environments
Characterization of Standard Cells for Intra-Cell Mismatch Variations
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques
Design of low-power, scalable-throughput systems at near/sub threshold voltage
Circuit-level approach to improve the temperature reliability of Bi-stable PUFs
Runtime 3-D stacked cache management for chip-multiprocessors
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning
Generic system-level modeling and optimization for beyond CMOS device applications
BCH code based multiple bit error correction in finite field multiplier circuits
Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock
Is Quality a Design Constraint for Sub 100nm Designs?
Low temperature endurance failures on flash memory
ISQED quality award recipient (IQ-Award 2010)
Incremental power optimization for multiple supply voltage design
A top-down design methodology using virtual platforms for concept development
Device- and system-level performance modeling for graphene P-N junction logic
Nanoelectronics: Evolution or Revolution?
Rehabilitation System for Limbs using IMUs
Hellfire: A design framework for critical embedded systems' applications
Thermal Modeling and Design Exploration for Monolithic 3D ICs
Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking
Yield evaluation of analog placement with arbitrary capacitor ratio
Power-yield optimization in MPSoC task scheduling under process variation
Efficient Selection of Observation Points for Functional Tests
Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs
Compact circuit modeling of RF characteristics of 1-D nanostructures
Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes
A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits
SRAM bit-line electromigration mechanism and its prevention scheme
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes
An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology
On Testability of Multiple Precharged Domino Logic
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology
Optimizing simulated annealing on GPU: A case study with IC floorplanning
QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis
Negotiation-based resource provisioning and task scheduling algorithm for cloud systems
Minimizing Ohmic Loss in Future Processor IR Events
Lightweight Multicast Authentication in NoC-based SoCs
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity
Scaled LTPS TFTs for low-cost low-power applications
Modeling and Design of Chip-Package Interface
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache
A Generalized Hardware-Efficient Gabor Wavelet Architecture for Medical Image Processing
Adding virtualization support in MIPS 4Kc-based MPSoCs
EASI-CiM: Event-driven Asynchronous Stream-based Image classifier with Compute-in-Memory kernels
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs
Speculative Energy Scheduling for LDPC Decoding
Architecture for monitoring SET propagation in 16-bit Sklansky adder
Lookup Table-Based Adaptive Body Biasing of Multiple Macros
Side channel attacks in embedded systems: A tale of hostilities and deterrence
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP
Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model
Electromigration Reliability Issues in High-Performance Circuit Design (Tutorial Abstract)
An enhanced debug-aware network interface for Network-on-Chip
Achieving the Quality of Verification for Behavioral Models with Minimum Effort
Accelerating Reliability Analysis for Aging and Self-Heating using Machine Learning
OPAQUE: Obfuscating Phase in Quantum Circuit Compilation for Efficient IP Protection
AI-Driven Reverse Engineering of QML Models
9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design
HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
A generalized V-shaped multilevel method for large scale floorplanning
A path to energy-efficient spiking delayed feedback reservoir computing system for brain-inspired neuromorphic processors
Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects
An integrated precision clock generator for implanted electronics with superior long-term stability
Crossover Ring Oscillator PUF
Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design
Compression or Corruption? A Study on the Effects of Transient Faults on BNN Inference Accelerators
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing
Nanowire transistor solutions for 5nm and beyond
Write Intensity based Foresightful Page Migration for Hybrid memories
Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects
Defect characterization in magnetic field coupled arrays
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound
Design of a sigma-delta modulator in standard CMOS process for wide-temperature applications
Methodologies to exploit ATPG tools for de-camouflaging