yusuke1997/dblp-id-title huggingface dataset:
A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
A 5.8GHz power-harvesting 116μmx116μm "dielet" near-field radio with on-chip coil antenna
5.5 A forward-body-bias tuned 450MHz Gm-C 3 rd -order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply
Session 24 overview: Wireless receivers and synthesizers
A Passive Bidirectional BLETag Demonstrating Battery-Free Communication in Tablet/Smartphone-to-Tag, Tag-to-Tablet/Smartphone, and Tag-to-Tag Modes
A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs
14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems
30.6 A Low-Power BLE Transceiver with Support for Phase-Based Ranging, Featuring 5µs PLL Locking Time and 5.3ms Ranging Time, Enabled by Staircase-Chirp PLL with Sticky-Lock Channel-Switching
14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC
A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation
A 0.18µm CMOS Dual-Band Direct-Conversion DVB-H Receiver
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet
12.5 A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface
9.8 A Low-Cost 4-Channel Reconfigurable Audio Interface for Car Entertainment Systems
6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling
A Single-Inductor-Based High-Voltage Transmit Beamformer for Wearable Ultrasound Devices Achieving 88% fCV 2 Power Reduction
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone
27.3 A 90.8%-Efficiency SIMO Resonant Regulating Rectifier Generating 3 Outputs in a Half Cycle with Distributed Multi-Phase Control for Wirelessly-Powered Implantable Devices
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration
28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS
2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC
A fully integrated successive-approximation switched-capacitor DC-DC converter with 31mV output voltage resolution
31.4 A Chopper-Stabilized Amplifier with -107dB IMD and 28dB Suppression of Chopper-Induced IMD
8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers
A Fully Integrated Quad-Band GPRS/EDGE Radio in 0.13μm CMOS
Reconfigurable RF and data converters
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS
A 2.6mW 10pTI √ Hz 33kHz Magnetoimpedance-Based Magnetometer with Automatic Loop-Gain and Bandwidth Enhancement
A 0.01mm 2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
A 1.2V 67mW 4mm 2 mobile ISDB-T tuner in 0.13µm CMOS
A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated Power-Management
9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNR
25.9 A ±3ppm 1.1mW FBAR frequency reference with 750MHz output and 750mV supply
22.7 A 966-electrode neural probe with 384 configurable channels in 0.13µm SOI CMOS
Spurious-noise-free buck regulator for direct powering of analog/RF loads using PWM control with random frequency hopping and random phase chopping
5.4 A 22.4-to-30.7GHz Phased-Array Receiver with Beam-Pattern Null-Steering and Beam-Tracking Techniques Achieving >30.2dB OTA-Tested Spatial Rejection
21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications
Palm NMR and one-chip NMR
An 11Gb/s Inductive-Coupling Link with Burst Transmission
A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications
DL-VOPU: An Energy-Efficient Domain-Specific Deep-Learning-Based Visual Object Processing Unit Supporting Multi-Scale Semantic Feature Extraction for Mobile Object Detection/Tracking Applications
A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time
A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET
Session 26 overview: Wireless for IoE
A 24mW 1.25Gb/s 13kΧ transimpedance amplifier using active compensation
A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS
A 4GS/s Fully Analog 256×256 MP-Based Cross-Correlator with 1000TOPS/W Compute Efficiency and 1.3TOPS/mm 2 Compute Density in 22nm SOI CMOS
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling
A CMOS electrochemical impedance spectroscopy biosensor array for label-free biomolecular detection
A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs
A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW
A Spatial-Temporal Multi-Resolution CMOS Image Sensor with Adaptive Frame Rates for Moving Objects in the Region-of-Interest
Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM
Session 20 overview: Frequency generation
30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs
F3: Emerging technologies for wireline communication
A64FX: 52-Core Processor Designed for the 442PetaFLOPS Supercomputer Fugaku
An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS
Multi-GB/s Transceivers
24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET
Little-known features of well-known creatures
26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS
22.2 A 176-channel 0.5cm3 0.7g wireless implant for motor function recovery after spinal cord injury
A ±1.5% nonlinearity 0.1-to-100A shunt current sensor based on a 6kV isolated micro-transformer for electrical vehicles and home automation
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers
A 1.25mW 75dB-SFDR CT filter with in-band noise reduction
36.5 An Automatic Self-Checking and Healing Physically Unclonable Function (PUF) with <3 × 10⁻⁸ Bit Error Rate
Session 5 overview: Audio and power converters: Analog subcommittee
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance
36.5 A Low-Latency 200Gb/s PAM-4 Heterogeneous Transceiver in 0.13μm SiGe BiCMOS and 28nm CMOS for Retimed Pluggable Optics
A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems
A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
24.8 A W-Band Power Amplifier with Distributed Common-Source GaN HEMT and 4-Way Wilkinson-Lange Combiner Achieving 6W Output Power and 18% PAE at 95GHz
Session 2 overview: RF frequency synthesis techniques
A 512Gb 3b/Cell 7 th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver
31.6 A SIDO/DISO VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio SC Converter Achieving 91.4%/92.6% Peak Efficiency and Almost-lossless Channel Switching
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS
31.10 A Fully integrated 500V, 6.25MHz GaN-IC for Totem-Pole PFC Off-Line Power Conversion
Neurons to Silicon: Implantable Prosthesis Processor
A short-range UWB impulse-radio CMOS sensor for human feature detection
A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology
17.6 Envelope modulator for multimode transmitters with AC-coupled multilevel regulators
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS
Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology
21.6 A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control
A 0.24nJ/b wireless body-area-network transceiver with scalable double-FSK modulation
CMOS-on-Plastic Technology using Sequential Laterally Solidified Silicon Thin-Film Transistors
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking
A 4b/cell NROM 1Gb Data-Storage Memory
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$
2.6 Class-0: A highly linear class of power amplifiers in 0.13μm CMOS for WCDMA/LTE applications
A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer
27.5 A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth
8.2: Run-Time Power Management System by on-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core CPU
29.4 High-Performance Isolators and Notch Filters Based on N-Path Negative Transresistance
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS
20.4 MEMS-Free 4096-Pixel CMOS E-Nose Gas-Sensor Array with Molecular-Selective Metal-Organic-Framework Sensing and In-Pixel Thermodynamic Modulation for Fast Sensor Regeneration
An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery
Capacitive Power-Management Circuit for Micropower Thermoelectric Generators with a 2.1μW Controller
8-Path tunable RF notch filters for blocker suppression
3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver
2.1 A highly linear inductorless wideband receiver with phase- and thermal-noise cancellation
Green Electronics: Environmental Impacts, Power, E-Waste
26.6 A 6.5µW 10kHz-BW 80.4dB-SNDR Continuous-Time ΔΣ Modulator with Gm-Input and 300mVpp Linear Input Range for Closed-Loop Neural Recording
A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration
30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution
Optical receivers using DFE-IIR equalization
7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate
2020 IEEE International Solid- State Circuits Conference, ISSCC 2020, San Francisco, CA, USA, February 16-20, 2020
A 4Ω 2.3W class-D audio amplifier with embedded DC-DC boost converter, current-sensing ADC and DSP for adaptive speaker protection
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity
A Self-Calibrated On-chip Phase-Noise-Measurement Circuit with -75dBc Single-Tone Sensitivity at 100kHz Offset
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver
A 0.18μm CMOS 802.15.4a UWB Transceiver for Communication and Localization
A 2GHz 52 μW Wake-Up Receiver with -72dBm Sensitivity Using Uncertain-IF Architecture
11.2 A Fully Integrated Resonant Switched-Capacitor Converter with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current
34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word
15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm 2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation
A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power Switch
A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µS 1% Settling Time for a 3A/20ns Load Transient
A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI
A GHz spintronic-based RF oscillator
33.11 A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition
36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS
A Current Driver IC using a S/H for QVGA FullColor Active-Matrix Organic LED Mobile Displays
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology
A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS
Session 19 Overview: Optical Systems for Emerging Applications Technology Directions Subcommittee
A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM
Electronic THz Pencil Beam Forming and 2D Steering for High Angular-Resolution Operation: A 98×98-Unit 265GHz CMOS Reflectarray with In-Unit Digital Beam Shaping and Squint Correction
A closed-loop SC interface for a ±1.4g accelerometer with 0.33% nonlinearity and 2µg/vHz input noise density
A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm 2 Density with a Peripheral Circuit Under Cell Array Architecture
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector
Fully Integrated Buck Converter with 78% Efficiency at 365mW Output Power Enabled by Switched-Inductor Capacitor Topology and Inductor Current Reduction Technique
32GHz resonant-fin transistors in 14nm FinFET technology
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee
A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+
A 24x16 CMOS-Based Chronocoulometric DNA Microarray
A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode
2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS
8.1 Dynamic Guard-Band Features of the IBM zNext System
17.9 A 0.6V 70MHz 4 th -order continuous-time Butterworth filter with 55.8dB SNR, 60dB THD at +2.8dBm output signal power
A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression
Heterodyne Phase Locking: A Technique for High-Frequency Division
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS
28.2 A 0.29mm 2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC
A Single-Inductor Switching DC-DC Converter with 5 Outputs and Ordered Power-Distributive Control
A 0.021mm 2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency
A 0.42nW 434MHz -79.1dBm Wake-Up Receiver with a Time-Domain Integrator
Session 16 Overview: Computation in Memory Memory Subcommittee
A 43.7mW 96GHz PLL in 65nm CMOS
A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS
A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receivers
6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias
16.2 A large-area image sensing and detection system based on embedded thin-film classifiers
Short Course
A 40nm 16-core 128-thread CMT SPARC SoC processor
Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization
A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1 st -order ΔΣ modulator
8.6 An Integrated Dual-side Series/Parallel Piezoelectric Resonator-based 20-to-2.2V DC-DC Converter Achieving a 310% Loss Reduction
Ultra-low-voltage-circuit design
A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor Applications
A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS
28.5 A 94.1%-Efficiency Parallel-SC Hybrid Buck Converter Designed Using VCR-Aware Topology Optimizer for a 4.2A/mm² Current-Density FoM
14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and < -30 Loss for Compound AI
A CMOS Temperature-to-Digital Converter with an Inaccuracy of ± 0.5° C (3σ)from -55 to 125°C
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer
A 22nm IA multi-CPU and GPU System-on-Chip
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology
A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power
15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS
Fully printed organic CMOS technology on plastic substrates for digital and analog applications
A 64Mpixel CMOS Image Sensor with 0.50µm Unit Pixels Separated by Front Deep-Trench Isolation
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs
A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95e - Random Noise
A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS
SE5 Highlights of IEDM 2006
A 0.18μm CMOS 91%-efficiency 0.1-to-2A scalable buck-boost DC-DC converter for LED drivers
A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique
34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications
A CMOS adaptive antenna-impedance-tuning IC operating in the 850MHz-to-2GHz band
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer
90.6% efficient 11MHz 22W LED driver using GaN FETs and burst-mode controller with 0.96 power factor
20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR
A 4-channel 4-beam 24-to-26GHz spatio-temporal RAKE radar transceiver in 90nm CMOS for vehicular radar applications
Distributed Loss Compensation for Low-latency On-chip Interconnects
A 1.12mW Continuous Healthcare Monitor Chip Integrated on a Planar Fashionable Circuit Board
A 10.5mW Automotive Touch AFE IC Featuring Radiated EMI Reduction Based on Pipelined Dual-Frequency Modulation and Sine 2 Waveform Shaping for CISPR 25 Class 5 Compliance
A -91 dB THD+N Resistor-Less Class-D Piezoelectric Speaker Driver Using a Dual Voltage/ Current Feedback for LC Resonance Damping
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs
17.10 A 0.4V, 750nW, Individually Accessible Wireless Capacitive Sensor Interface IC for a Tactile Sensing Network
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS
A Physically Unclonable Function Combining a Process Mismatch Amplifier in an Oscillator Collapse Topology
A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC
20.5 A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement
A 16MHz X0 with 17.5μs Startup Time Under 10 4 ppm-ΔF Injection Using Automatic Phase-Error Correction Technique
A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS
A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis
Distributed active radiation for THz signal generation
A Single-Chip Bluetooth EDR Device in 0.13μm CMOS
A 445F 2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security
A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistance
Medical image sensors
A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber
A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning
10.2 A 139 µ W 104.8dB-DR 24 kHz-BW CT ΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs
A CMOS 10kpixel baseline-free magnetic bead detector with column-parallel readout for miniaturized immunoassays
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS
2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory
A Direct-Type Fast Feedback Current Driver for Medium-to Large-Size AMOLED Displays
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers