yusuke1997/dblp-id-title huggingface dataset:
SaGraph: A Similarity-aware Hardware Accelerator for Temporal Graph Processing
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge
From Homogeneous to Heterogeneous: Leveraging Deep Learning based Power Analysis across Devices
Timing model extraction of hierarchical blocks by graph reduction
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine
An interactive testability analysis program - ITTAP
Generalized information system - a tool for design automation
Global forced hierarchical router
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction
Collective computing based on swarm intelligence
Reducing the overhead of authenticated memory encryption using delta encoding and ECC memory
A low-energy chip-set for wireless intercom
Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes
On finding most optimal rectangular package plans
Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs
Parametric yield estimation considering leakage variability
Lookup table based simulation and statistical modeling of Sigma-Delta ADCs
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation
Area and performance co-optimization for domain wall memory in application-specific embedded systems
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits
A Data-Centric Hardware Accelerator for Efficient Adaptive Radix Tree
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems
PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning
Closed-form modeling of layout-dependent mechanical stress
New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements
Parallel Algorithms for Power Estimation
BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs
Lyra: A new approach to geometric layout rule checking
Resource usage templates and signatures for COTS multicore processors
Integration of multi-sensor occupancy grids into automotive ECUs
INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive Transformers
A multiprocessor implementation of relaxation-based electrical circuit simulation
JouleTrack - A Web Based Tool for Software Energy Profiling
Logic Verification Algorithms and Their Parallel Implementation
High-Level Synthesis from VHDL with Exact Timing Constraints
Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction
A Partitioned Ring Structure Processor
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
GENIE: a generalized array optimizer for VLSI synthesis
MeG 2 : In-Memory Acceleration for Genome Graphs Analysis
Multi-shift quadratic alternating direction implicit iteration for high-speed positive-real balanced truncation
Architecture decomposition in system synthesis of heterogeneous many-core systems
Certified Timing Verification and the Transition Delay of a Logic Circuit
Rewiring for robustness
A Novel Approach to Accurate Timing Verification Using RTL Descriptions
AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration
The use of carry-save representation in joint module selection and retiming
Soft Scheduling in High Level Synthesis
Comparison-Free Bit-Stream Generation for Cost-Efficient Unary Computing
Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips
Compact thermal modeling for temperature-aware design
Equivalence checking paradigms in quantum circuit design: a case study
Verification of Electronic Systems
Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach
Electronic Component Information Exchange (ECIX)
Performance analysis of a memristive crossbar PUF design
RC-Interconnect Macromodels for Timing Simulation
Ensembler: Protect Collaborative Inference Privacy from Model Inversion Attack via Selective Ensemble
Architecting ASIC libraries and flows in nanometer era
Structured design verification: Function and timing
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology
Min-cost Partitioning on a Tree Structure and Applications
GENERIC: a silicon compiler support language
Verification of Arithmetic Circuits with Binary Moment Diagrams
Selective gate-length biasing for cost-effective runtime leakage control
Design integrity and immunity checking: A new look at layout verification and design rule checking
Efficient error detection, localization, and correction for FPGA-based debugging
Maze routing with buffer insertion and wiresizing
Duet: A Collaborative User Driven Recommendation System for Edge Devices
DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis
Information flow isolation in I2C and USB
iClaire: A Fast and General Layout Pattern Classification Algorithm
An adaptive and evolutive tool for describing general hierarchical models, based on frames and demons
Specify-explore-refine (SER): from specification to implementation
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
Logic Clause Analysis for Delay Optimization
Design automation challenges for scalable quantum architectures
A low-energy computation platform for data-driven biomedical monitoring algorithms
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service
Invited: Compute Express Link™ (CXL™): An Open Interconnect for Cloud Infrastructure
Formal verification of a real-time hardware design
Detecting malicious modifications of data in third-party intellectual property cores
FPGA Design Principles (A Tutorial)
Toward a methodology for manufacturability-driven design rule exploration
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
Parallel Hierarchical Reachability Analysis for Analog Verification
A "grid-free" channel router
Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems?
High-level synthesis of multiple-precision circuitsindependent of data-objects length
Digital Aetection of Analog Parametric Faults in SC Filters
HIMap: a heuristic and iterative logic synthesis approach
Sparse Hamming Graph: A Customizable Network-on-Chip Topology
Actors Revisited for Time-Critical Systems
Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizations
CLIC - computer layout of integrated circuits
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Scheduler-based DRAM energy management
Dynamic Communication Models in Embedded System Co-Simulation
OPC-Free and Minimally Irregular IC Design Style
CascadeHD: Efficient Many-Class Learning Framework Using Hyperdimensional Computing
Surf-Bless: A Confined-interference Routing for Energy-Efficient Communication in NoCs
Benefits and challenges for platform-based design
Memory-CPU Size Optimization for Embedded System Designs
Transition Density, A Stochastic Measure of Activity in Digital Circuits
Effective-Resistance Preserving Spectral Reduction of Graphs
DGR: Differentiable Global Router
Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers
Parallelizing CAD: a timely research agenda for EDA
Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract)
SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures
Layering algorithms for single row routing
On-line interactive graphics the designer's dream or the production manager's nightmare
Design Automation concerns (Position Paper)
Energy exploration and reduction of SDRAM memory systems
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability
LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks
Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing
FHE-CGRA: Enable Efficient Acceleration of Fully Homomorphic Encryption on CGRAs
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks
Microprocessor synthesis
Fault diagnosis based on effect-cause analysis: An introduction
Rapid Prototyping of ASIC Based Systems
An Architecture for Learning Stream Distributions with Application to RNG Testing
Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal Circuits
The SCALD physical design subsystem
A pattern matching coprocessor for network security
An Extension to Basis-Hypervectors for Learning from Circular Data in Hyperdimensional Computing
Design rule checking and analysis of IC mask designs
PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic Identification
Efficient partitioning of components
Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning
Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?
Statistical waveform and current source based standard cell models for accurate timing analysis
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment
Exploiting operation level parallelism through dynamically reconfigurable datapaths
The role of custom design in ASIC Chips
High-Quality Operation Binding for Clustered VLIW Datapaths
Invited: The Magnificent Seven Challenges and Opportunities in Domain-Specific Accelerator Design for Autonomous Systems
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
REMU: Memory-aware Radiation Emulation via Dual Addressing for In-orbit Deep Learning System
The use of engineering documentation in support of a high density logic test system
EBT: A comprehensive test generation technique for highly sequential circuits
Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level
The next chip challenge: effective methods for viable mixed technology SoCs
Space plan: A user oriented package for the evaluation and the generation of spatial inter-relationships
A meta-compiler as a design automation tool
A Re-engineering Approach to Low Power FPGA Design Using SPFD
A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement Learning
The Architecture of a Highly Integrated Simulation System
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management
An Interconnect Energy Model Considering Coupling Effects
Robots in design (Panel Discussion)
DA PUF: dual-state analog PUF
Design methodology for IC manufacturability based on regular logic-bricks
EXCL: A circuit extractor for IC designs
Attackboard: a novel dependency-aware traffic generator for exploring NoC design space
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
An expert systems approach to completing partially routed printed circuit boards
Routing the 3-D Chip
"There Is More Than Moore In Automotive ..."
S2FA: an accelerator automation framework for heterogeneous computing in datacenters
A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU
DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm
Early-Stage Power Grid Design: Extraction, Modeling and Optimization
Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations
High performance encryption cores for 3G networks
OPAL: Outlier-Preserved Microscaling Quantization Accelerator for Generative Large Language Models
Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD - CCS7E Processor System Simulation
Optimizing sequential verification by retiming transformations
Applying passive RFID system to wireless headphones for extreme low power consumption
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups
Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Logic verification system for very large computers using LSI's
Energy estimation and optimization of embedded VLIW processors based on instruction clustering
Low-Overhead Power Trace Obfuscation for Smart Meter Privacy
Bounded-lifetime integrated circuits
A placement algorithm for array processors
S-Tree: a technique for buffered routing tree synthesis
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion
Trends in the use of re-configurable platforms
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method
Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design
PRUID: Practical User Interface Distribution for Multi-surface Computing
Merging nodes under sequential observability
The iCOREtm 520 MHz synthesizable CPU core
XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification
An efficient algorithm for finding empty space for online FPGA placement
A Path Selection Algorithm for Timing Analysis
A logic partitioning procedure by interchanging clusters
A collaborative defense against wear out attacks in non-volatile processors
HERCULES - a System for High-Level Synthesis
Late Breaking Results: Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited
Early Power-Aware Design & Validation: Myth or Reality?
Enhancing LLM-based Quantum Code Generation with Multi-Agent Optimization and Quantum Error Correction
GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUs
DPS: dynamic precision scaling for stochastic computing-based deep neural networks
Flip-flop clustering by weighted K-means algorithm
HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands
Analysis of Operation Delay and Execution Rate Constraints for Embedded Systems
Accurate and Efficient Macromodel of Submicron Digital Standard Cells
A declarative design approach for combining macrocells by directed placement and constructive routing
Dynamic management of key states for reinforcement learning-assisted garbage collection to reduce long tail latency in SSD
A functional partitioning expert system for test sequences generation
PatLabor: Pareto Optimization of Timing-Driven Routing Trees
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
MIDAS: integrated CAD for total system design
A low cost hierarchical system for VLSI layout and verification
Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling
A practical circuit fingerprinting method utilizing observability don't care conditions
ChronOS Linux: a best-effort real-time multiprocessor Linux kernel
A set of programs for MOS design
The planar package planner for system designers
Power-conscious High Level Synthesis Using Loop Folding
Concurrent fault simulation and functional level modeling
Revisiting an operational graphic design system
On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits
Live Region Mutation Testing for Commercial Cyber-Physical System Development Tool Chain
Boolean Matching for Large Libraries
GarbledCPU: a MIPS processor for secure computation in hardware
Can CAD cure cancer?
System-Level Design Flow Based on a Functional Reference for HW and SW
Memory partitioning for multidimensional arrays in high-level synthesis
A prestructuring model for system arrangement problems
An organizational approach to routing printed circuit boards
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator
57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020
An hierarchical language for the structural description of digital systems
Towards Optimal System-Level Design
Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions
Wear leveling for crossbar resistive memory
Logic soft errors in sub-65nm technologies design and CAD challenges
ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization
Efficient dynamic information flow tracking on a processor with core debug interface
VeriCDF: a new verification methodology for charged device failures
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency
Overview of Microelectromechanical Systems and Design Processes
SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Lightning Talk: All Routes to Timing Closure
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering
Performance verification of circuits
Dos and don'ts of CTL state coverage estimation
Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip
NBTI-Aware Synthesis of Digital Circuits
Taming Noise in Deep Submicron Digital Integrated Circuits (Panel)
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization
Seed encoding with LFSRs and cellular automata
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation
Automatic test generation for large digital circuits
Automatic layout algorithms for function blocks of CMOS gate arrays
Electrical optimization of PLAs
Tamper-resistant pin-constrained digital microfluidic biochips
A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams
Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits
Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware
Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography
A green function-based parasitic extraction method for inhomogeneous substrate layers
Race-condition-aware clock skew scheduling
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization
Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
HAPPI: a chip compiler based on double-level-metal technology
Emulation based high-accuracy throughput estimation for high-speed connectivities: case study of USB2.0
ALVEARE: a Domain-Specific Framework for Regular Expressions
Issues in IC implementation of high level, abstract designs
Energy-aware MPEG-4 FGS streaming
Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic
Novel full-chip gridless routing considering double-via insertion
Constraint Generation for Routing Analog Circuits
CHORD: Composable Hybrid Optical Reconfigurable Diffractive Framework For Optical Neural Network
TraceFormer: S-parameter Prediction Framework for PCB Traces based on Graph Transformer
Hyperdimensional hashing: a robust and efficient dynamic hash table
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware
Generating Efficient Tests for Continuous Scan
A computer-aided linkage analysis system
AccALS: Accelerating Approximate Logic Synthesis by Selection of Multiple Local Approximate Changes
Exploring Inherent Sensor Redundancy for Automotive Anomaly Detection
Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures
GABRIEL: A Design Environment for Programmable DSPs
The quad-CIF tree: A data structure for hierarchical on-line algorithms
Are there economic benefits in DFM?
Performance Analysis of Embedded Software Using Implicit Path Enumeration
Device hypervisors
SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering
Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping
Budgeting-free hierarchical design method for large scale and high-performance LSIs
A Framework for Scheduling Multi-Rate Circuit Simulation
Petri Net based search directing heuristics for test generation
Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip
Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical Networks
Synthesis and optimization of coordination controllers for distributed embedded systems
DM-Tune: Quantizing Diffusion Models with Mixture-of-Gaussian Guided Noise Tuning
zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM
A robust algorithm for approximate compatible observability don't care (CODC) computation
Addressing library creation challenges from recent Liberty extensions
Issues and Answers in CAD Tool Interoperability
Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016
Boolean Matching Using Generalized Reed-Muller Forms
Automation of re-entry vehicles' preliminary design
MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction
Optimal Clock Skew Scheduling Tolerant to Process Variations
A joint management middleware to improve training performance of deep recommendation systems with SSDs
An Efficient Path Delay Fault Coverage Estimator
Heterogeneous integration of carbon nanotubes and graphene microassemblies for environmental and breath sensing
Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges
Computer Design Language - Version Munich (CDLM) a modern multi-level language
Automated techniques for product-grading systems design
Tools and Methodology for RF IC Design
Gene modification identification under flux capacity uncertainty
Learning from BDDs in SAT-based bounded model checking
Accuracy Is Not Always We Need: Precision-Aware Bayesian Yield Optimization
Optimization of planning and architectural decisions under conditions of uncertain demand
Meta Data Management in the NELSIS CAD Framework
Underpowering NAND flash: profits and perils
On Optimum Switch Box Designs for 2-D FPGAs
Manufacturing Interface (Panel Abstract)
Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations
Late Breaking Results: On the One-Key Premise of Logic Locking
An Approach to Fast Hierarchical Fault Simulation
CoinPurse: A Device-Assisted File System with Dual Interfaces
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project
DAMN - a prototype program for the Dynamic Analysis of Mechanical Networks
A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM
Hammer: a modular and reusable physical design flow tool: invited
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm
Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language Models