yusuke1997/dblp-id-title huggingface dataset:
Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC
Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions
Floorplanning with graph attention
CDL - A tool for concurrent hardware and software development
Cyber-physical systems: the next computing revolution
Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive Latches
NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction
Interactive co-design of high throughput embedded multimedia
A "non-restrictive" artwork verification program for printed circuit boards
TEMP: thread batch enabled memory partitioning for GPU
A circuit comparison system for bipolar linear LSI
Accuracy-configurable adder for approximate arithmetic designs
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip
Spatially distributed 3D circuit models
A hierarchical placement procedure with a simple blocking scheme
Integrated instruction cache analysis and locking in multitasking real-time systems
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing
Federation: repurposing scalar cores for out-of-order instruction issue
On Solving Covering Problems
Delay Optimization of Combinational Static CMOS Logic
Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited
A System for Fault Diagnosis and Simulation of VHDL Descriptions
Design automation's challenge to defense technical data
Automatic generation of functional logic test programs through simulation
DROIDFUZZ: Proprietary Driver Fuzzing for Embedded Android Devices
Synthesis of CFET Cell Library Leveraging Backside Metal Routing
The evolution of SOC interconnect and how NOC fits within it
Circuit Camouflage Integration for Hardware IP Protection
Optimum reduction of programmable logic array
Compositional modeling and analysis of automotive feature product lines
Engineering Workstations: Tools or toys?
Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation
FACT : A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Symbolic Parasitic Extractor for Circuit Simulation (SPECS)
Automatic Synthesis of Pipeline Structures with Variable Data Initiation Intervals
An approach to interactive graphic programming
MGX: An integrated symbolic layout system for VLSI
Information Modelling of EDIF
Clock tree synthesis under aggressive buffer insertion
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
Cellular wiring and the cellular modeling technique
Code Optimization Techniques for Embedded DSP Microprocessors
BEOL Scaling Limits and Next Generation Technology Prospects
Circuit design challenges at the 14nm technology node
Automated inspection of electronic assemblies
SPECRUN: The Danger of Speculative Runahead Execution in Processors
Classes of diagnostic tests
Voltage prediction of drone battery reflecting internal temperature
CASE Environments for Design Automation
A mathematical mockup - engine envelope described by computer
Process variation aware OPC with variational lithography modeling
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Invited - Cross-layer approximate computing: from logic to architectures
Static timing analysis using backward signal propagation
Where in the World Should CAD Software be Made? (Panel Abstract)
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution
Faster and better global placement by a new transportation algorithm
The CAMS preliminary missile design automation program
A New Asynchronous Pipeline Template for Power and Performance Optimization
Control Optimization Based on Resynchronization of Operations
Simultaneous functional and timing ECO
A Practical Moat Router
The design of a dense PCB using an interactive DA system
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults
Efficient Sum-to-One Subsets Algorithm for Logic Optimization
GPU-accelerated Path-based Timing Analysis
Automated mapping for reconfigurable single-electron transistor arrays
Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology
Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices
An algorithm for design rule checking on a multiprocessor
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes
Functional design verification by multi-level simulation
New algorithms for grid-less routing of high density printed circuit boards
Spectral Partitioning: The More Eigenvectors, The Better
Automatic Generation of Compiled Simulations through Program Specialization
A fast and low-cost comparison-free sorting engine with unary computing: late breaking results
On robust task-accurate performance estimation
Privacy-Preserving DNN Training with Prefetched Meta-Keys on Heterogeneous Neural Network Accelerators
Toggle MUX: How X-Optimism Can Lead to Malicious Hardware
Finding deterministic solution from underdetermined equation: large-scale performance modeling by least angle regression
FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N: M Sparsity
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization
Speculative Decoding for Verilog: Speed and Quality, All in One
Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication
Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation
Automatic floorplan design
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
A fast on-chip profiler memory
A New Twisted Differential Line Structure in Global Bus Design
Digital system simulation: Current status and future trends or darwin's theory of simulation
HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCs
Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional Latency
DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosis
An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes
A heuristic procedure for ordering MOS arrays
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing
User Defined Coverage - A Tool Supported Methodology for Design Verification
CIBOL - an interactive graphics program used in the design of printed wiring boards and generation of associated artmasters
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching
Forbidden transition free crosstalk avoidance CODEC design
Joint automatic control of the powertrain and auxiliary systems to enhance the electromobility in hybrid electric vehicles
Invited - Towards fail-operational ethernet based in-vehicle networks
Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015
MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR Lifetime
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Accelerating nonlinear DC circuit simulation with reinforcement learning
Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network
Specifications for a design automation system
Panel: Cell Libraries - Build vs. Buy; Static vs. Dynamic
MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution
An interactive logic synthesis system based upon AI techniques
Escher - a geometrical layout system for recursively defined circuits
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations
A verification technique for hardware designs
Mixed-Dimensional Qudit State Preparation Using Edge-Weighted Decision Diagrams
Basic turorial layout tools - what really is there
Subwavelength Lithography: How Will It Affect Your Design Flow? (Panel)
DFBT: A Design-for-Testability Method Based on Balance Testing
Watermarking integer linear programming solutions
Synchronization for hybrid MPSoC full-system simulation
Software reliability and design: A survey
MASC: A Memory-Efficient Adjoint Sensitivity Analysis through Compression Using Novel Spatiotemporal Prediction
Thermal-aware drone battery management: late breaking results
Statistical path tracing in timing graphs
Computation of power supply nets in VLSI layout
IntellBatt: towards smarter battery design
Inductance 101: Modeling and Extraction
Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor System
The STE-264 accelerated electronic CAD system
A designing system for multi-family housing
Processing-In-Hierarchical-Memory Architecture for Billion-Scale Approximate Nearest Neighbor Search
EnQode: Fast Amplitude Embedding for Quantum Machine Learning Using Classical Data
Digital logic modeling system based on MODLAN
Optical proximity correction (OPC): friendly maze routing
Automatic design with dependence graphs
Topics in design automation data bases
A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together
Invited: Graph Learning for Parameter Prediction of Quantum Approximate Optimization Algorithm
What's smart about the smart grid?
An Automobile Detection Algorithm Development for Automated Emergency Braking System
Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials
HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night
Equivalence checking for behaviorally synthesized pipelines
Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing Efficiency
Passive model order reduction of multiport distributed interconnects
On reliable modular testing with vulnerable test access mechanisms
Timing verification system based on delay time hierarchical nature
SpREM: Exploiting Hamming Sparsity for Fast Quantum Readout Error Mitigation
Modeling Magnetic Coupling for On-Chip Interconnect
Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis
Power-aware Performance Tuning of GPU Applications Through Microbenchmarking
Predictive dynamic thermal management for multicore systems
Mitigating Routability Problems in Complementary-FET-based VLSI Designs
Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access
Mitigating Distribution Shift for Congestion Optimization in Global Placement
Timing macro modeling with graph neural networks
Silicon compilation of gate array bases
On the relation between wire length distributions and placement of logic on master slice ICs
An Approxmimate Algorithm for Delay-Constraint Technology Mapping
Towards Practical Record and Replay for Mobile Applications
Electronic design automation for social networks
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels
Software architecture for the implementation of a Computer-Aided Engineering system
ARGA: Approximate Reuse for GPGPU Acceleration
Crosstalk Minimization Using Wire Perturbations
ApproxIt: An Approximate Computing Framework for Iterative Methods
Finding the Optimal Variable Ordering for Binary Decision Diagrams
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Efficient spare allocation in reconfigurable arrays
Design of robust metabolic pathways
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
A Fresh Look at Retiming Via Clock Skew Optimization
Matlab extensions for the development, testing and verification of real-time DSP software
Combining dictionary coding and LFSR reseeding for test data compression
Panel: Is Nanometer Design Under Control?
Trusted Design in FPGAs
Database Support for Evolving Design Objects
Routing congestion estimation with real design constraints
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays
GLAD - a systems approach to artwork generation
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives
Efficient State Retention through Paged Memory Management for Reactive Transient Computing
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data
System level signal and power integrity analysis methodology for system-in-package applications
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
Representative path selection for post-silicon timing prediction under variability
Tessellation: refactoring the OS around explicit resource containers with continuous adaptation
Automated Composition of Hardware Components
HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI
TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations
A Quadratic Metric with a Simple Solution Scheme for Initial Placement
ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor
High-level synthesis of asynchronous systems by data-driven decomposition
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling
Resource Efficient Mobile Communications for Crowd-Sensing
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003
ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited
Simplified data structure for "mini-based" turnkey CAD systems
Yield estimation via multi-cones
O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation
FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs
An effective DFM strategy requires accurate process and IP pre-characterization
ReForm: Static and Dynamic Resource-Aware DNN Reconfiguration Framework for Mobile Device
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS
VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data
PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA
Designer Controlled Behavioral Synthesis
Orchestrating Measurement-Based Quantum Computation over Photonic Quantum Processors
Function-level power estimation methodology for microprocessors
DECOMPOSER: A Synthesizer for Systolic Systems
Invited: Human-Inspired Distributed Wearable AI
Automatic Verification of External Interrupt Behaviors for Microprocessor Design
Experience with D-BUS Architecture for a Design Automation Framework
A routing procedure for mixed array of custom macros and standard cells
Hierarchical application aware error detection and recovery
Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability
Reconfigurable Computing: What, Why, and Implications for Design Automation
Distributed Timing Analysis at Scale
A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes
AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory
Efficient design space exploration of embedded platforms
Adaptive Layout Decomposition with Graph Embedding Neural Networks
TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited
Cost-Distance Steiner Trees for Timing-Constrained Global Routing
Model order reduction of nonuniform transmission lines using integrated congruence transform
PALACE: A Kayout Generator for SCVS Logic Blocks
Predicting variability in nanoscale lithography processes
A functional language for description and design of digital systems: sequential constructs
Y-architecture-based flip-chip routing with dynamic programming-based bend minimization
Efficiently tolerating timing violations in pipelined microprocessors
Can EDA combat the rise of electronic counterfeiting?
Software quality assurance for CAD (tutorial)
Sizing of Clock Distribution Networks for High Performance CPU Chips
Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems
A Compute-in-Memory Architecture Compatible with 3D NAND Flash that Parallelly Activates Multi-Layers
The complexity of design automation problems
Routability-aware Packing for High-density Nonvolatile FPGAs
A design framework for processing-in-memory accelerator
Data Path Allocation using an Extended Binding Model
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited
SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors
Mechanical design automation in IBM Poughkeepsie
Autonomous Warehouse-Scale Computers
Optimal multi-domain clock skew scheduling
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications
A Digit-Serial Silicon Compiler
Power and Ground Network Topology Optimization for Cell Based VLSIs
Useful-Skew Clock Routing With Gate Sizing for Low Power Design
PathFinder: side channel protection through automatic leaky paths identification and obfuscation
Thermal-aware data flow analysis
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System
Profile-Driven Program Synthesis for Evaluation of System Power Dissipation
Synergically Rebalancing Parallel Execution via DCT and Turbo Boosting
TD-Magic: From Pictures of Timing Diagrams To Formal Specifications
Characterizing Process Variation in Nanometer CMOS
LSIM: Ultra Lightweight Similarity Measurement for Mobile Graphics Applications
PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference
Correlation-guided Placement for Nonvolatile FPGAs
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling
Worst-case response time analysis of resource access models in multi-core systems
Advanced gate-level glitch modeling using ANNs
Design automation at Norden
Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases
Code Generation for Core Processors
ReSMA: accelerating approximate string matching using ReRAM-based content addressable memory
Circuit Enhancement by Eliminating Long False Paths
Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
A preprocessor for structural analysis programs
A simplification heuristic for large flow tables
Microarchitecture evaluation with physical planning
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Goal-oriented stimulus generation for analog circuits
RTL Emulation: The Next Leap in System Verification
Modeling the Function Cache for Worst-Case Execution Time Analysis
BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication
Switch-level delay models for digital MOS VLSI
A general methodology for synthesis and verification of register-transfer designs
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design
MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction
PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators
Speed and accuracy in digital network simulation based on structural modeling
Performance space modeling for hierarchical synthesis of analog integrated circuits
Security aware network controllers for next generation automotive embedded systems
Predicting Lemmas in Generalization of IC3
PowerField: a transient temperature-to-power technique based on Markov random field theory
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect
A 24 GHz phased-array transmitter in 0.18µm CMOS
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing
A Hardware/Software Partitioner Using a Dynamically Determined Granularity
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability
A path analysis approach to the diagnosis of combinational circuits
Design & verification of automotive SoC firmware
CAD and Foundries for Microsystems
Stochastic steady-state and AC analyses of mixed-signal systems
Hardware Metering
GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks
VersaSlot: Efficient Fine-grained FPGA Sharing with Big.Little Slots and Live Migration in FPGA Cluster
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries
A design aids data base for digital components
MemSeer: Leverage Memory Failure Distinctions and Multi-Grained Prediction in Ultra-Scale Heterogeneous X86/ARM Clusters
T. A. G. traffic study in building layouts
Robust test generation algorithm for stuck-open fault in CMOS circuits
Error Diagnosis for Transistor-Level Verification
Timing-driven cell placement optimization for early slack histogram compression
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits
Revisiting context-based authentication in IoT
Proceedings of the 13th Design Automation Conference, DAC '76, San Francisco, California, USA, June 28-30, 1976
High-Level Symbolic Construction Technique for High Performance Sequential Synthesis
Edge-cloud collaborative processing for intelligent internet of things: a case study on smart surveillance
Quantitative evaluation of soft error injection techniques for robust system design
Accelerating real-time embedded scene labeling with convolutional networks
Spider, a chip planner for ISL technology
Neural Network-Based Side Channel Attacks and Countermeasures
TimberWolf3.2: a new standard cell placement and global routing package
SAT with partial clauses and back-leaps
Fast Identification of Robust Dependent Path Delay Faults
A low latency generic accuracy configurable adder
Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring
Custom microcomputers for CAD optimization software
Why is Today's CAD Inadequate for Designing Tomorrow's Computers (Panel Abstract)
AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization
A Prolog-Based Connectivity Verification Tool
Investigation of obfuscation-based anti-reverse engineering for printed circuit boards
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis
Alex: A conversational, hierarchical logic design system
Emerging Hardware Technologies and 3D System Integration for Ubiquitous Machine Intelligence
The design of a data base organization for an electronic equipment DA system
GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process
Simulation based deadlock analysis for system level designs
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Timing-based delay test for screening small delay defects