yusuke1997/dblp-id-title huggingface dataset:
An Event-Driven Load Regulation Enhanced LDO IC with 9.2fs-Transient-FoM and 1.6µA-Quiescent Current for Low Voltage IoT Applications
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits
RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier
Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators
A unified radix-4 partial product generator for integers and binary polynomials
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses
Real Time Feature Extraction of Acoustic Signals with an Analog Neural Computer
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop
A wearable, wireless electronic interface for textile sensors lin shu
A current controlled oscillator based readout front-end for neurochemical sensing in 65nm CMOS technology
A 53.3 Mb/s 4×4 16-QAM MIMO decoder in 0.35-µm CMOS
Delay-guaranteed Interactive Multiview Video Streaming
Design Space Exploration of Memristor-based Delay Cells for Time-domain Neuromorphic Computing
Analysis and comparison of charge-pump conditioning circuits for capacitive electromechanical energy conversion
Harmonic balance analysis and control of period doubling bifurcation in buck converters
FPGA-based architecture for real-time IP video and image compression
A Wide Dynamic Range High Linearity In-pixel Data Acquisition Front-end for Computed Tomography
High resolution distance sensing for mini-robots using Time Difference of Arrival
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits
Power reduction techniques for an OFDM burst synchronization core
Scalable multi-rate iLBC
A novel energy-efficient stimuli generator for very-high impedance intracortical microstimulation
Stream-access-oriented baseband signal processors for SDR
Design and Implementation of complete wearable Low-Intensity Pulsed Ultrasound Therapeutic Device
Application of reverse-active npns for compact, wide-tuning f T -integration-based filters in SiGe HBT BiCMOS technology
Utilization of Field Programmable Analog Arrays (FPAA) to Emulate Power System Dynamics
Programmable analog pulse shaping for ultra-wideband applications
An audio clock regenerator with a wide dividing ratio for HDMI
DCS1800/WCDMA adaptive voltage-controlled oscillator
Embedded a Low Area 32-bit AES for Image Encryption/decryption Application
Using MPEG-4 audio for DRM digital narrowband broadcasting
Generalized LC multiple resonance networks
A low voltage low 1/f noise CMOS bandgap reference
Live demonstration: Event-based image processing on CMOS Mihalas-Niebur neuron array transceiver
Towards Designing a Unified DNN Architecture for Analog and Mixed-Signal Circuit Characterization
An Efficient Hardware Implementation of 2D Convolution based on the Discrete Hirschman Transform
Fast-locking low-jitter integrated CMOS phase-locked loop
A macro-model for the efficient simulation of an ADC-based RNG
On Improving the Robustness of Compressed Video by Slepian-Wolf based Lossless Transcoding
A 5.9mW full-band low-noise-amplifier for ultra-wideband systems
Exact In-Memory Multiplication Based on Deterministic Stochastic Computing
Impact of boost converter parameters on open-loop dynamic performance for DCM
Secure data hiding in binary document images for authentication
A low voltage, high speed, high resolution class AB switched current sample and hold
A Novel Type-based Vector Modulator Self-calibration Technique
An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs
Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator
A framework to study time-dependent variability in circuits at sub-35nm technology nodes
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications
A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links
An image compression scheme based on parametric Haar-like transform
The design and implementation of a chipset for the endoscopic Micro-Ball
An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin
A Frame Level Rate Control Algorithm For Screen Content Coding
Low-voltage micropower multipliers with reduced spurious switching
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX
Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications
A low power asynchronous DES
Dynamic range of allpass filter structures
Towards Hardware Optimal Neural Network Selection with Multi-Objective Genetic Search
A Scalable Multi-Chip YOLO Accelerator With a Lightweight Inter-Chip Adapter
Streaming capacity in multi-channel P2P VoD systems
Designing Variation-tolerance in Mixed-signal Components of a System-on-chip
Unsupervised video orchestration based on aesthetic features
Application-level pipelining on Hierarchical NoC
Design and analysis of a switched-capacitor-based peak detector
Peak Transform for Efficient Image Representation and Coding
Digit-serial/parallel multipliers with improved throughput and latency
A 48 Gbps Communication Link Over D-Band Polymer Microwave Fiber
IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014
The enhancement net power control for lifetime improvement of AMOLED
Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed
Reducing Temperature Induced Unreliability in Sub-Threshold Strong PUFs through Circuit Modeling
Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line
A highly effective error concealment method for whole frame loss
Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matrices
Towards Efficient Structural Health Monitoring: Spike-Encoding in Real-Time Electromechanical Impedance Systems
Low-cost Deployment and Acceleration of Event-based Spiking Convolutional Neural Networks
Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform
Improving SNDR and SFDR in Capacitive DACs using Match Enhancement
Consensus of edge dynamics on complex networks
The Impact of Different Gain Control Methods on Performance of CMOS Variable-Gain LNA
Explainable automated data estimation in Logic State Imaging of embedded SRAM
Integrating Bird's Eye View Fusion and Reinforcement Learning for Efficient Autonomous Intersection Navigation
A Multi-Pixel Compression for Low-Power Imaging System and Architecture
Modeling of Injection Locking in Neurons for Neuromorphic and Biomedical Systems
Correction of transmitter gain and phase errors at the receiver
An NoC-Based Latency Upper-Bound Model for Reducing Timestep Length in SNN Communication
An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
Characterization of regular linear-phase paraunitary filter banks using dyadic-based structures
Statistical image modeling using von Mises distribution in the complex directional wavelet domain
Driver's drowsiness estimation by combining EEG signal analysis and ICA-based fuzzy neural networks
Design of A 10-Bit, 2GS/s Current-Steering Digital-to-Analog Converter with OnLine Current Calibration
Interactive SC multirate compiler applied to multistage decimator design
Reconfigurable Decoder for LDPC and Polar Codes
A Novel 2.7 pJ/bit, Low Supply, Power Efficient, Wide-Range 2.5-6 Gb/s Transmitter for 4-Channel High-Speed Serial Transmit Port (HSSTP) in 28nm FD-SOI Technology
Analysis of power supply gain of CMOS bandgap references
LC quadrature generation in integrated circuits
A compact course on VHDL-AMS
A novel topology in RNMC amplifiers with single miller compensation capacitor
An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only
Power analysis attack of QCA circuits: A case study of the Serpent cipher
A Method for Dynamic Range Maximization for a Class of Integrated Active-RC Filters
A 5-GHz prescaler using improved phase switching
Modeling and simulation of mixed signal systems using a multi-lingual simulator
An IIP2 digital calibration technique for passive CMOS down-converters
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification
A 2-MHZ, process and voltage compensated clock oscillator for biomedical implantable SoC in 0.18-μm CMOS
Development of real-time wireless brain computer interface for drowsiness detection
Parallel architectures for decision-directed RLS-equalization
Design of an ASIC to Implement a New Data Tranfer Protocol for High Energy Physics
Systematic Development of CMOS PTAT Circuits
A DLL-based Configurable Multi-Phase Clock Generator for True-Time-Delay Wideband FMCW Phased-Array in 40nm CMOS
A gigahertz wideband CMOS multiplier for UWB transceiver
Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing
Initial solution for the optimum design delay equalizers
Fundamental limits on energy efficiency performance of VCO-based ADCs
A 0.4-V 410-nW opamp-less continuous-time ΣΔ modulator for biomedical applications
Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance
A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators
A design complexity comparison method for loop-based signal processing algorithms: particle filters
Multi-pass algorithm of motion estimation in video encoding for generic GPU
An input-free NMOS V T extractor circuit in presence of body effects
Automatic dead-time adjustment CMOS mixed-signal circuit for a DCM-operated 3-level switching power converter
An architecture for MPEG-4 binary shape decoder
Distributing Electric Vehicles to the Right Charging Queues
A Novel Ergodic Cellular Automaton Asthma Model: Reproductions of Nonlinear Dynamics of Asthma and Efficient FPGA Implementation
A multi-microchip retinal stimulator for in vitro / in vivo experiments
Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs
Fast motion estimation for video resolution down-conversion using spatial-variant filter
A Process Compensated 3-GHz Ring Oscillator
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs
An integrated design for the front-end of an inductive position sensor
Adaptive Impedance Matching
A Reverse-encoding-based On-chip AHB Bus Tracer Supporting both Post-T and Pre-T Trace
Image transmission over IEEE 802.15.4 and ZigBee networks
Active Compensation of Parasitic Capacitances for Very High Frequency CMOS DACs
Near-threshold Startup Integrated Boost Converter with Slew Rate Enhanced Error Amplifier
Demosaicing with improved edge direction detection
A CMOS RMS-to-DC converter using ΣΔ multiplier-divider
Automatic music genre classification based on wavelet package transform and best basis algorithm
Layer ordering to minimize TSVs in heterogeneous 3-D ICs
Parallelized Hardware Acceleration of Automatic Differentiating Wave Digital Filters
A design strategy for VHF filters with digital programmability
Real-time, color image barrel distortion removal
Metaplasticity in Multistate Memristor Synaptic Networks
A new taxonomy for reconfigurable prefix adders
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks
Low-Noise Optimisation of Current-mode Transimpedance Optical Preamplifiers
Two-dimensional discriminant multi-manifolds locality preserving projection for facial expression recognition
Printing of temperature and humidity sensors on flexible substrates for biomedical applications
A Compensation System using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers
Design of TETRA 2 turbo decoder with minimum memory hardware interleaver
Low power output-capacitorless class-AB CMOS LDO regulator
New results for estimation of Hausdorff dimension
Live Demonstration: W3M Wearable Weight and Walk Monitoring System
Real-Time Extraction of Maximally Stable Extremal Regions on an FPGA
An Integrated Fully-Differential Switched-Current Ladder Filter
Design of discrete-time fractional Hilbert transformer
Adaptation of video encoders for improvement in quality
Removing Image Artifacts From Scratched Lens Protectors
A programmable ENG amplifier with passive EMG neutralization for FES applications
Temperature compensation design for a 2.4 GHz CMOS low noise amplifier
An Improved Data-Driven Memristor Model Accounting for Sequences Stimulus Features
Parameter variation analysis for voltage controlled oscillators in phase-locked loops
A Deep Neural Network Based Kalman Filter for Time Domain Speech Enhancement
Bifurcation in parallel-connected buck converters under current-mode control
Novel Circuit Solutions for Rail-to-Rail CMOS Buffer
STT-RAM write energy consumption reduction by differential write termination method
Broadband Conductor Backed-CPW with Tapered Microstrip Line to Corrugated Via Wall-SIW Transition for Different-Bands (2-40 GHz)
Electromagnetic Simulation Modeling of CMOS Chip in Millimeter-Wave Band
All-Digital Time Integrator with Bi-Directional Gated Ring Oscillator / Shift Register
Hardware Design of Memristor-based Oscillators for Emulation of Neurological Diseases
Microstatistic Recursive Least Squares
Automated synthesis of stochastic computational elements using decision procedures
Towards hardware Implementation of WTA for CPG-based control of a Spiking Robotic Arm
A dynamic calibration scheme for on-chip process and temperature variations
ECG Beat Classification based on Signal Decomposition: a Comparative Study
Forget partitions? Not yet..
Synchronization: a fundamental phenomenon in complex dynamical networks
An Accelerated GPU Library for Homomorphic Encryption Operations of BFV Scheme
An FPGA-based point target detection system using morphological clutter elimination
A 50GHz 130µW inductorless prescaler in 45nm SOI CMOS using ETSPC logic
Quantized chaotic dynamics and communications systems
Eye-gesture controlled intelligent wheelchair using Electro-Oculography
Live demonstration: Event-driven deep neural network hardware system for sensor fusion
Low-power low-noise amplifier IIP3 improvement under consideration of the cascode stage
A Low Power Programmable Switch Supply Dynamic Comparator
DOLFIN-digit online for integration neural networks
Memristive Implementation of Variable Pixel MRI Imaging Using Skywater 130nm PDK
Low-voltage High CMRR OTA for Electrophysiological Measurements
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier
Kernel Aware Warp Scheduler
Hilbert space techniques for reactive power compensation with limited current bandwidth
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement
Circuits Design Optimization Using Symbolic Approach
Space-time diversity for multimedia delivery over wireless channels
Correlation-feedback Approach to Computation of Optical Flow
A hybrid MPPT method for Photovoltaic systems via estimation and revision method
Adaptive 6.78-MHz ISM band wireless charging for small form factor receivers
Dual drain-line distributed cell design for multi-Gbit/s transversal filter implementations
A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers
Low power and roboust FinFET SRAM cell using independent gate control
An Energy-Efficient Asynchronous Hybrid-Searching Algorithm for Auto Frequency Calibration in IEEE 802.11ax Applications
CMOS drive circuit for opto-electronic readout of image sensors
Dynamic-range Analysis and Maximization of Micropower Gm-C Bandpass Filters by Adaptive Biasing
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering
Hardware-oriented image inpainting for perceptual I-frame error concealment
A Ku-band down-converter with perfect differential PLL in 0.18um CMOS
An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology
Nonlinear distortion in current-steering D/A-converters due to asymmetrical switching errors
A Novel Multiple Modes PWM Controller for LEDs
Efficient hardware-oriented cellular active contours
A generalized conflict-free address scheme for arbitrary 2k-point memory-based FFT processors
Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS
A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer
Unequal Error Protection for Backward Compatible 3-D Video Transmission over WiMAX
A wavelet-based semi-fragile watermarking with recovery mechanism
Live demonstration: The "DAVIS" Dynamic and Active-Pixel Vision Sensor
Chaotification of nonlinear systems described by the fuzzy hyperbolic model
Minimized right-half plane zero effect on fast boost DC-DC converter achieved by adaptive voltage positioning technique
A transformer neutralization based 60GHz LNA in 65 nm LP CMOS with 22dB gain and 5.5dB NF
Simplified current and delay models for deep submicron CMOS digital circuits
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies
Full Adder-based Inner Product Step Processors for Residue and Quadratic Residue Number Systems
A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals
High total-ionizing-dose tolerance field programmable gate array
Extraction of Binarized Neural Network Architecture and Secret Parameters Using Side-Channel Information
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks
Bifurcation of multiple-input parallel dc-dc converters with dynamic winner-take-all switching
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis
Active RC networks: what benefit is there in having conjugate real zeros in the second-order transfer function?
Steerable Zero-Shot Neural Architecture Search for Efficient Edge Inference
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration
A Decimation Filter Architecture for GHz Delta-Sigma Modulators
A 5.5-7.9 GHz Double Quadrature Cryo-CMOS Receiver Featuring a Wideband Noise Matching LNA for Quantum Applications
Quantization Noise Improvement of Time to Digital Converter (TDC) for ADPLL
A 3DES implementation especially for CBC feedback loop mode
Direct Hierarchical Symbolic Transient Analysis of Linear Circuits
Analysis of clock buffer phase noise
Machine-learning framework for automatic netlist creation
Low-voltage switched-capacitor circuits
Efficient frequency estimation using the pulse-pair method at different lags
Cort-X II: low power element design of a large-scale spatio-temporal pattern clustering system
Automatic clock tree design with IPs in the system
Small world effects in networks: an engineering interpretation
Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters
Electronic Photonic Integrated Circuits (EPICs): Fundamentals and Applications
A low-power silicon-on-insulator PWM discriminator for biomedical applications
A Conversational Agent based on Large Language Models for Fault Recovery Planning Generation
Bifurcation analysis in a piecewise-smooth system with periodic threshold
An SFBC-OFDM receiver with MLSE equalizer to combat multiple frequency offsets
A hybrid image compression algorithm based on fractal coding and wavelet transform
Dither for chattering reduction in sliding mode control systems
Pulsed activation: Saving power for mixed-signal circuits
Effects of crosstalk noise on H-tree clock distribution networks
On the design and sensitivity of RC sequence asymmetric polyphase networks in RF integrated transceivers
Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning
Breakdown in Polysilicon Resistors Operating in the Deep Cryogenic Regime
Designing an Accurate and Robust LC-Compliant Asynchronous Sigma Delta Boost DC-DC Converter
An Object Enhancement Method for Forward-Looking Sonar Images Based on Multi-Frame Fusion
Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators
3.9G Radio Reception with SC-FDMA Waveforms Under I/Q Imbalance
High performance asynchronous bus for SoC
An analytical mismatch model of nano-CMOS device under impact of intrinsic device variability
Reconfigurable and Computationally Efficient Architecture for Multi-Armed Bandit Algorithms
A neuromorphic ASIC design using one-selector-one-memristor crossbar
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator
Minimum mean squared error time series classification using an echo state network prediction model
A New Offset Cancellation Technique for CMOS Differential Amplifiers
A new anchored normalization technique for score-level fusion in multimodal biometrie systems
Efficient architecture for Reed Solomon block turbo code
Fault recovery protocol for distributed memory MPSoCs
Fourier domain adaptation for nighttime pedestrian detection using Faster R-CNN
Extrinsic data compression method for double-binary turbo codes
Attention-Based Multi-Task Learning for Speech-Enhancement and Speaker-Identification in Multi-Speaker Dialogue Scenario
Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems
Balun LNA with continuously controllable gain and with noise and distortion cancellation
High-speed interfaces for analog, iterative VLSI decoders
A High-Speed Low-Cost Millimeter Wave System with Dual Pulse Shaping Transmission and Symbol Rate Equalization Techniques
Activity Recognition in Wearable ECG Monitoring Aided by Accelerometer Data
A programmable on-chip BP learning neural network with enhanced neuron characteristics
A 15-nA quiescent current capacitor-less LDO for sub-1V μW-powered fully-harvested systems
Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO
A class of downsampled floating tap DFE architectures with application to serial links
A translinear-based RF RMS detector for embedded test
Real-Valued ESPRIT for two-dimensional DOA estimation of noncircular signals for acoustic vector sensor array
A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving
A Lossless Intra Reference Block Recompression Scheme for Bandwidth Reduction in HEVC-IBC
A new NDA timing error detector for BPSK and QPSK with an efficient hardware implementation for ASIC-based and FPGA-based wireless receivers
Robust group-of-picture architecture for video transmission over error-prone channels
ISCAS Special Session Demo: Wireless Video Sensor for Ad-hoc Networks
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration
Trifilar-Transformer-Coupled Series-Resonance Oscillator with Enhanced Tuning Range
Energy metrics for power efficient crosslink and mesh topologies
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop
Single-Inductor Multi-Input Multi-Output DC-DC Converter with High Flexibility and Simple Control
Detection of radar target pulse in the presence of noise and jamming signal using the multiscale wavelet transform
Zero-Voltage Switching in Switched Current Circuits
A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface
Video Decoder Improvements with Near-Data Speculative Motion Compensation Processing
A convergence model for a CORDIC-based ARMA lattice filter
Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router
Quantization errors in committee machine for gas sensor applications
Performance of a DSSS superregenerative receiver in the presence of noise and interference
Exploration of self-healing circuits for timing resilient design using emerging memristor devices