yusuke1997/dblp-id-title huggingface dataset:
A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs
iLog 3.0: Estimating Food Volume from 2D Images Using Mask R-CNN and Monocular Depth Estimation
Ultra-Small Area, Highly Linear, Modified All Mosfet Digital-to-Analog Converters with Novel Real Time Digital Calibration Algorithm
Efficient Hardware Implementation of Discrete Wavelet Transform Based on Stochastic Computing
Memristor-Based Clock Design and Optimization with In-Situ Tunability
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits Testing
Towards Yield Improvement for AI Accelerators: Analysis and Exploration
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures
Towards Data-Driven Approximate Circuit Design
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm
Flip-UnLock: An Anomaly Detection Attack on Flip-Flop-Based Logic Locking
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths
A Markov Performance Model for Buffered Protocol Design
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES
A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface
Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks
A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays
High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages
Hybrid Bayesian Optimization with Early Termination Strategies for Auto Tuning
L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic
Power-Oriented Delay Budgeting for Combinational Circuits
Energy Optimization of Racetrack Memory-Based SIMON Block Cipher
Accuracy Configurable FPGA Implementation of Harris Corner Detection
Novel UHF Passive Rectifier with Tunnel FET Devices
Taylor Series Based Architecture for Quadruple Precision Floating Point Division
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
Modern Floorplanning with Boundary Clustering Constraint
HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCs
gem5-SysXelerator: A Full-System Simulator for Accelerator Architectures
Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture
Structural Testing in MEDA Based Biochips: A New Technique Using Diagonal Route
An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip
NV-SP: A New High Performance and Low Energy NVM-Based Scratch Pad
Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System
A Network Based Functional Verification Method of IEEE 1394a PHY Core
A Timing Error Mitigation Technique for High Performance Designs
An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning
Design of a Safe Convolutional Neural Network Accelerator
A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls
Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis
Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures
A Low-Cost Minimally-Processed Inkjet-Printed Nonlinear Element for Reservoir Computing
STT-MRAM-Based Strong PUF Architecture
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates
A DFT Methodology for Repairing Embedded Memories of Large MPSoCs
Quantum Resource Counts for Operations Constructed from an Addition Circuit
Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing
An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices
A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach
Energy Evaluation Methodology for Platform Based System-on-Chip Design
High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction
Dataset Distillation for Quantum Neural Networks
An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip
Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture
Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association
Achieving Low Power Classification with Classifier Ensemble
ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method
Deep State Encryption for Sequential Logic Circuits
European ICT Research: 2011-2012 Outlook for Components and Systems
FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems
On Reducing Peak Current and Power during Test
Generating Storage-Aware Test Sets Targeting Several Fault Models
2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache
In Situ Design of Register Operations
Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology
Design of Multiplier Circuit Based on Signed-Digit Hybrid Stochastic Computing
A Computational Primitive for Convolution based on Coupled Oscillator Arrays
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs
Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis
Dynamic Fault Tree Models for FPGA Fault Tolerance and Reliability
Area-Efficient Digital Design Using RRAM-CMOS Standard Cells
An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip
Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors
Reconfigurable Hardened Latch and Flip-Flop for FPGAs
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips
Optimizing TCN Inference: A Hardware-Software Co-Design Approach with CGRA Acceleration
Low-Precision Vectorized Arithmetic Unit Designs for Deep Learning
Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder
Wireless NoCs Using Directional and Substrate Propagation Antennas
CosMos: Building A Network Reliability Cost Modeling System for Customer SLA
Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC
Energy and Error Reduction using Variable Bit-width Optimization on Dynamic Fixed Point Format
Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design
Protecting CRT RSA against Fault and Power Side Channel Attacks
Memory-Less Pipeline Dynamic Circuit Design Technique
A Two-Tiered Heterogeneous and Reconfigurable Application Processor for Future Internet of Things
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area
Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline
Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter
An Intelligent Memory Framework for Resource Constrained IoT Systems
X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors
High-Accuracy FIR Filter Design Using Stochastic Computing
Cost-Effective Time-Redundancy Based Optimal Task Allocation for the Edge-Hub-Cloud Systems
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements
In-Sensor Motion Recognition with Memristive System and Light Sensing Surfaces
LImbiC: An adaptable architecture description language model for developing an application-specific image processor
Leveraging Low-Rank Factorization for Compressing DNN Speech Enhancement Models
Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption
Support Vector Machines Classification on Bendable RISC-V
Hardware-Accelerated On-Device Learning: Training, Partitioning, and Compilation for Constrained Edge AI
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement
Power-Efficient Inter-Layer Communication Architectures for 3D NoC
SCARIF: Towards Carbon Modeling of Cloud Servers with Accelerators
A Floating Gate MOSFET Based Current Reference with Subtraction Technique
A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme
A Quantum Pipeline for an Executable Quantum Instruction Set Architecture
CIM for Transformer Models: Enhancing Large Language Model Inference Efficiency
An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices
Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS
Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional Computing
High Level Power Estimation Models for FPGAs
Dependability Analysis of Nano-scale FinFET circuits
Defect-Aware Design Paradigm for Reconfigurable Architectures
Design Approaches and Consideration for a Reliable and Efficient Monolithic 3D Integration
PLAs in Quantum-dot Cellular Automata
A Neural Stimulator Output Stage for Dodecapolar Electrodes
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects
Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions
Anomaly Detection for Real-World Cyber-Physical Security Using Quantum Hybrid Support Vector Machines
Interconnect Power Optimization Based on Timing Analysis
Parametric RISC-V Compliant Floating-Point Arithmetic and Conversion Circuits
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations
Resource and Performance Estimation for CNN Models using Machine Learning
High Level RTOS Scheduler Modeling for a Fast Design Validation
Experimental Evaluation of Resonant Clock Distribution
Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies
Application of Bottom-Up Methodology to RTW VCO
Adversarial Attack Resilient ML-Assisted Hardware Trojan Detection Technique
Evaluating the Data Integrity of Memory Systems by Configurable Markov Models
Quantum Annealing for Automated Feature Selection in Stress Detection
Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems
DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing
PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices
A Fast and Effective Memristor-Based Method for Finding Approximate Eigenvalues and Eigenvectors of Non-negative Matrices
A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing
Depth Optimized Synthesis of Symmetric Boolean Functions
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure
Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories
Off-Chip SDRAM Access Through Spidergon STNoC
Side-channel Leakage Assessment Metrics: A Case Study of GIFT Block Ciphers
On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection
A novel tool flow for increased routing configuration similarity in multi-mode circuits
TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits
Post-Silicon Validation and Calibration of Hardware Security Primitives
Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC
PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT Devices
Equivalence Checking of Array-Intensive Programs
Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs
State Dependent Optimization with Quantum Circuit Cutting
Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window
Performance Improvement of Physical Retiming with Shortcut Insertion
HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration
ConFUSE: Confusion-based Federated Unlearning with Salience Exploration
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach
Visual Analytics of Performance of Quantum Computing Systems and Circuit Optimization
High performance service-time-stamp computation for WFQ IP packet scheduling
PristiQ: A Co-Design Framework for Preserving Data Security of Quantum Learning in the Cloud
A High-Speed GCD Chip: A Case Study in Asynchronous Design
Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes
WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS
An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern
An open-source tool for simulation of partially reconfigurable systems using SystemC
Hardware Security for Critical Infrastructures - The CIPSEC Project Approach
Enabling Scaling of Advanced CMOS Technologies: A Reliability Perspective
Fast Configuration of an Energy-Efficient Branch Predictor
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs
Reliability of n-Bit Nanotechnology Adder
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications
Dual-Mode High-Speed Low-Energy Binary Addition
Towards Thermally Reliable Photonic Links for Multicore Processors
Interconnect Delay Analysis for RRAM Crossbar Based FPGA
Towards Integration of Quadratic Placement and Pin Assignment
On the Detection and Circumvention of Bitstream-level Trojans in FPGAs
Parametric Circuit Optimization with Reinforcement Learning
Securing hard drives with the Security Protocol and Data Model (SPDM)
Comparison between Different Data Buses Configurations
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks
Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications
Water-Wise Computing: Addressing Data Center Water Consumption for a Sustainable Future
Replica-Based Low Drop-Out Voltage Regulator with Assistant Power Transistors for Digital VLSI Systems
Attacking Multi-Tenant FPGAs Without Manual Placement and Routing
Machine Learning Training on a Real Processing-in-Memory System
Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow
Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications
A Parameterizable Convolution Accelerator for Embedded Deep Learning Applications
Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow
Advancing Edge Analog Processing with Photonic In-Memory Computing
Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization
Predicting GPU Performance and System Parameter Configuration Using Machine Learning
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation
Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled Cavity
A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic Cells
Profile Directed Instruction Cache Tuning for Embedded Systems
Using Configurable Bit-Width Voters to Mask Multiple Errors in Integrated Circuits
ACA-CSU: A Carry Selection Based Accuracy Configurable Approximate Adder Design
On Preventing SAT Attack with Decoy Key-Inputs
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits
Physical Design Variation in Relative Timed Asynchronous Circuits
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits
CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS
Supporting QoS in AXI4 Based Communication Architecture
Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility
System Level Design of Complex Hardware Applications Using ImpulseC
A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation
Coverage Driven Verification applied to Embedded Software
PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity Acceleration
Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure
Enduring Non-Volatile L1 Cache Using Low-Retention-Time STTRAM Cells
The Solar Cells and the Battery Charger System Using the Fast and Precise Analog Maximum Power Point Tracking Circuits
A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current Distribution
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression
Logic Switches Operating at the Minimum Energy of Computing
Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow
Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip
Process Algebra Based SoC Test Scheduling for Test Time Minimization
Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm
Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation Approximation
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips
Future Challenges in VLSI Design
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations
An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications
A Closed-Loop Architecture with Digital Output for Convective Accelerometers
A Fast Transient Digitally Assisted Flash-Based Modular LDO for Sensor Nodes in WBAN
Towards Improving Performance Metrics of Minority Majority Inverter Graph (mMIG) Circuits
An Effective Chemical Mechanical Polishing Filling Approach
Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits
Software Support for Heterogeneous Computing
System Level Design Space Exploration for Multiprocessor System on Chip
On the Performance Exploration of 3D NoCs with Resistive-Open TSVs
A Programmable Frequency Divider in 0.18µm CMOS Library
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
Energy Recovery from High-Frequency Clocks Using DC-DC Converters
Design to Introduce On-chip Fine Tunability in Analog Active Inductor
Universal Topological Arrays: An Efficient Solution for Provably Secure Hardware
Analyzing Imprecise Adders Using BDDs - A Case Study
Force-Directed Scheduling for Dynamic Power Optimization
DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation
InsectAgent: Improving Insect Recognition through Dynamic Information Augmentation with Multimodal Large Language Models
A Reconfigurable Memory Management Core for Java Applications
Modeling and Analysis of Switched-Capacitor Converters as a Multi-port Network for Covert Communication
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed
A Web Server Based Edge Detector Implementation in FPGA
Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated Circuits
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC
A General Design Framework for Sparse Parallel Prefix Adders
Analytical Approach to Engineer Strain-Gradient for Magnetic Skyrmion-based LeakyIntegrate and Fire Neuronal Dynamics
A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural Network
Logic-in-Memory: A Nano Magnet Logic Implementation
A BDD-Based Design of an Area-Power Efficient Asynchronous Adder
A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs
A Fast Hypergraph Bipartitioning Algorithm
Unified Model for Contrast Enhancement and Denoising
New Branching Heuristics for Incremental Bounded Model Checking
Pipeline Design Based on Self-Resetting Stage Logic
Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume
Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors
Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks
McPoRA: A Multi-chain Proof of Rapid Authentication for Post-Blockchain Based Security in Large Scale Complex Cyber-Physical Systems
XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation
Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM
Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design
Designing Compatible Analog Circuits for Equilibrium Propagation: Implementations Using The Adjoint Method and Reciprocity Principles
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders
Evaluation of Neuron Parameters on the Performance of Spiking Neural Networks and Neuromorphic Hardware
Design of Quantum Circuits for Galois Field Squaring and Exponentiation
Mixed-Signal Design Using Digital CAD
CMOS Realization of Online Testable Reversible Logic Gates
Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation