yusuke1997/dblp-id-title huggingface dataset:
A word-parallel digital associative engine with wide search range based on Manhattan distance
A wideband quadrature LO generator in digital CMOS
T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training
Miniaturized 3-dimensional transformer design
A Disturb Decoupled Column Select 8T SRAM Cell
A low power, 10-bit CMOS D/A converter for high speed applications
Early prediction of product performance and yield via technology benchmark
Wireless Frequency-Division Multiplexed 3D Magnetic Localization for Low Power Sub-mm Precision Capsule Endoscopy
Compact modeling and simulation of PD-SOI MOSFETs: Current status and challenges
A 19 mW/lane Serdes transceiver for SFI-5.1 application
A 0.144 mm 2 12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation
MPDE methods for efficient analysis of wireless systems
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers
An array-based test circuit for fully automated gate dielectric breakdown characterization
A CMOS pixel design with binary space-time exposure encoding for computational imaging
A 96.6%-Efficiency Inductively Assisted Switched- Capacitor DC-DC Converter with 0.5-to-1.5V Output Voltage Range
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 μm CMOS technology
A bandpass sigma-delta modulator IC with digital branch-mismatch correction
CNT based mechanical devices for ULSI memory
A million cycle 0.13um 1Mb embedded SONOS Flash memory using Successive Approximated Read Calibration
Practical considerations for application specific time interleaved ADCs
A Fourth Order Elliptic Low-Pass Filter with Wide Range of Programmable Bandwidth, Using Four Identical Integrators
A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS
A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC
Bio-systems at Gigahertz
A Unity-Gain Buffer with Reduced Offset and Gain Error
Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies
A 28nm 1.2GHz 5.27TOPS/W Scalable Vision/Point Cloud Deep Fusion Processor with CAM-based Universal Mapping Unit for BEVFusion Applications
The direct skew detect synchronous mirror delay (Direct SMD) for ASICs
A review of substrate coupling issues and modeling strategies
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI
A High Dynamic Range CMOS-MEMS Accelerometer Array with Drift Compensation and Fine-Grain Offset Compensation
Linearization of class D amplifiers
A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS
A highly linear SAW-less CMOS receiver using a mixer with embedded Tx filtering for CDMA
A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation in 40nm CMOS
A minimum decap allocation technique based on simultaneous switching for nanoscale SoC
Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations
A 72.6 dB SNDR 14b 100 MSPS Ring Amplifier Based Pipelined SAR ADC with Dynamic Deadzone Control in 16 nm CMOS
SiP for GSM/EDGE in CMOS technology
An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control
An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR
RF simulations and physics of the channel noise parameters within MOS transistors
A 0.0013mm 2 10b 10MS/s SAR ADC with a 0.0048mm 2 42dB-Rejection Passive FIR Filter
A low power implementation for the transmit path of a UWB transceiver
Compact outside-rail circuit structure by single-cascode two-transistor topology
A Co-Integrated Optical Phased Array, Mach-Zehnder Modulator and Mm-Wave Driver for Free-Space Communication
A 27-Mbps, 0.08-mm 3 CMOS Transceiver with Simultaneous Near-field Power Transmission and Data Telemetry for Implantable Systems
A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap Mixed-Signal FFE in 55nm BiCMOS
SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data
Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory
Verification of Complex Analog Integrated Circuits
A 0.14µJ Per-Acquisition Frequency Domain GPS Correlator Using Adaptive Compressive Sampling
A SAW-less CMOS CDMA receiver with active Tx filtering
IP repository, a Web based IP reuse infrastructure
A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter
A 37 ppm/°C Temperature Compensated CMOS ASIC with ±16 V Supply Protection for Capacitive Microaccelerometers
Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's
POWER8 design methodology innovations for improving productivity and reducing power
An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks
Delay and power model for current-mode signaling in deep submicron global interconnects
A high sensitivity process variation sensor utilizing sub-threshold operation
A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm
ESD protection device issues for IC designs
High-frequency 750mV operational amplifier standard bulk CMOS process
A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS
A power sensor with 80ns response time for power management in microprocessors
A 4 kHz, 25 μg/√Hz, 3-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing
Amorphous silicon TFT circuit integration for OLED displays on glass and plastic
A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors
Session 7 - Data converter techniques
Achieving higher linearity in precision standard products
Microwave CMOS-devices and circuits
A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs
A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N
A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization
An Energy Efficient Fully Integrated 20Gbps OOK Wireless Transmitter at 220GHz
Nearest neighbour interconnect architecture in deep submicron FPGAs
Switched inductor capacitor buck converter with >85% power efficiency in 100uA-to-300mA loads using a bang-bang zero-current detector
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR
A fully integrated DC to 75 MHz current sensing circuit with on-chip Rogowski coil
An ultra-low-power, temperature compensated voltage reference generator
Characterization and modeling of clock skew with process variations
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI
Standard cell power IC design
2D Magnetic Sensor Array for Real-time Cell Tracking and Multi-site Detection with Increased Robustness and Flow-rate
A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS
Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A
An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction
Driving CMOS into the wireless communications arena with technology scaling
A 1.2 mm 2 fully integrated GPS radio with cellular/WiFi Co-existence
A cost-efficient 0.18 μm CMOS RF transceiver using a fractional-N synthesizer for 802.11b/g wireless LAN applications
Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump
A Highly Integrated Power Management IC for Advanced Mobile Applications
A Quad-Output Hybrid Buck Converter with 8-Inductor Helping One Spot from All Quarters for Multi-Core XPUs
An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC
Virtual damping in oscillators
SiGe BiCMOS Trends - Today and Tomorrow
A system LSI utilizing media processor core "MMA"
STAR-SRAM: 43.06-TFLOPS/W, 1.89-TFLOPS/mm 2 , 400-Kb/mm 2 Floating-Point SRAM-Based Digital Computing-in-Memory Macro in 28-nm CMOS
A 450 Mbit/s EPR4 PRML read/write channel
A 1.2 Gbps SOI-BiCMOS write driver for hard disk drives
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space
A unified model and direct extraction methodologies of various CPWs for CMOS mm-wave applications
A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS
Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor
A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communication
Challenges in Designing Low-Power CMOS Wireless Systems-on-a-Chip
High dynamic range CMOS image sensor with conditional reset
Over-sampled data converters
A 0.5V 2.2pW 2-transistor voltage reference
High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS
A 10Gb/s data-dependent jitter equalizer
Amorphous silicon current steering digital to analog converter
A fully integrated multi-mode high-efficiency transmitter for IoT applications in 40nm CMOS
A 4-mm 2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions
An SC-first Hybrid SCVR with 4xCF Continuously Scalable-Conversion Ratio SC Achieving 92.5% Peak Efficiency
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping
Calibration Techniques for Optimizing Performance of High-Speed ADCs
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power
A 3 V-CMOS low distortion class AB line driver suitable for HDSL applications
CMOS (Sub)-mm-Wave System-on-Chip for exploration of deep space and outer planetary systems
Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application
A 188.6-μW Continuous-time Incremental Delta-Sigma ADC with Extended Counting achieving 95.2-dB SNDR and 175.4-dB FoMSNDR
A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS
A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links
A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application
Session 4 - Modeling and measurement of mixed-signal circuits
A digital pulse width modulation closed loop control LDMOS gate driver for LED drivers implemented in a 0.18 μm HV CMOS technology
Cyclone ™: a low-cost, high-performance FPGA
A Pseudo-4-Phase Buck Converter with 94.1 % Efficiency, 1mV Output Ripple and Fast Transient Response
Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells
A 10-Gbps 83 mW GaAs HBT equalizer/detector for coaxial cable channels
Session 25 - 20 Gb/s transmitters and receivers
3D Capacitive Interconnections for High Speed Interchip Communication
A low-power W-CDMA demodulator using specially-designed micro-DSPs
A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS
A Self-Resonant Boost Converter for Solar Energy Harvesting with 97% Tracking Efficiency, 80 mV Self-Startup and Ultra-Wide Range Source Tracking
Automatic tuning of RC filters and fast automatic gain control for CMOS low-IF transceiver
Synthesis of interface controllers from timing diagram specifications
A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet
Substrate cross talk noise characterization and prevention in 0.35 mμm CMOS technology
A fully-integrated low phase-noise nested-loop PLL for frequency synthesis
An efficient method of applying hot-carrier reliability simulation to logic design
Online Reinforcement Learning NoC for portable HD object recognition processor
CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems
Fully Integrated Electronic-Photonic Sensor for Label-Free Refractive Index Sensing in Advanced Zero-Change CMOS-SOI Process
An ASIC implementation of JPEG2000 codec
A soft-error hardened process portable embedded microprocessor
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management
At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?
A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications
A Verilog-A compact model for ESD protection NMOSTs
Session 16 - Embedded memory
A compact pulse-based charge pump in 0.13 μm CMOS
A 0.8GHz-10.6GHz SDR low-noise amplifier in 0.13-μm CMOS
Multi-band, multi-mode, low-power CMOS receiver front-end for sub-GHz ISM/SRD band with narrow channel spacing
A 78.2nW 3-channel time-delay-to-digital converter using polarity coincidence for audio-based object localization
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS
An overview of structured digital ASIC XPressArray©-II I/O
Statistical prediction of circuit aging under process variations
A 4-dB NF GPS receiver front-end with AGC and 2-b A/D
A field-programmable noise-canceling wideband receiver with high-linearity hybrid class-AB-C LNTAs
A methodology for measurement and characterization of substrate noise in high frequency circuits
New System-in-Package (SiP) Integration technologies
A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation
A 90-nm MOS-only 3-11GHz transmitter for UWB
A Low-Power Routing Architecture Optimized for Deep Sub-Micron FPGAs
Recent advances in GaN power electronics
A 14pJ/pulse-TX, 0.18nJ/b-RX, 100Mbps, channelized, IR-UWB transceiver for centimeter-to-meter range biotelemetry
Synthesis of Optimal On-Chip Baluns
Theoretical study of stubs for power line noise reduction [LSI applications]
VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel
A low power adaptive filter using dynamic reduced 2's-complement representation
High-speed data converters
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper)
Resonant wireless power transfer technology & integration roadmap
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads
Event-driven simulation of Volterra series models in SystemVerilog
Millimeter-wave phased array circuits and systems for 5G
Prospective for nanowire transistors
A Sub-1 μW multiparameter injectable BioMote for continuous alcohol monitoring
A 1.8V 16μA 136.5dB DR PPG/NIRS Recording IC using Noise Shaping Triple Slope Light to Digital Converter
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms
Inductor-based ESD protection under CDM-like ESD stress conditions for RF applications
Implications of Proximity Effects for Analog Design
A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm 3 Density
A-117.1dB THD Audio Decoder Utilizing Single Vector Quantizer for Simultaneous Mismatch and ISI Shaping
A single-chip low power DSP/RISC CPU with 0.25 μm CMOS technology
Digital phase tightening for millimeter-wave imaging
Understanding MOSFET mismatch for analog design
A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction
The iFlow design factory infrastructure for a 17M-gate, 0.13μm, 333MHz design [SoC design]
A performance optimized CMOS distributed LNA for UWB receivers
A 250 mW class D design with direct battery hookup in a 90 nm process [audio band switching amplifier]
Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction
A 1-to-4GHz Multi-Mode Digital Transmitter in 40nm CMOS Supporting 200MHz 1024-QAM OFDM signals with more than 23dBm/66% Peak Power/Drain Efficiency
A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz
2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020
High-K/Metal Gate Technology: A New Horizon
BIST controlled variable sense amp timing for 90nm embedded SRAM
A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple
High-Temperature, High Reliability EEPROM Design For Automotive Applications
A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC
The Pursuit of Practical Applications of THz CMOS Chips (Invited)
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers
A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth
Session 11 - Compact modeling
A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory
Compact modeling of noise in CMOS
A 5-GHz silicon bipolar transmitter front-end for wireless LAN applications
A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate
Low-jitter and Large-EMI-reduction Spread-spectrum Clock Generator with Auto-calibration for Serial-ATA Applications
A 10 GHz low phase noise VCO employing current reuse and capacitive power combining
Robust, reconfigurable, and power-efficient biosignal recording systems
BEE-SLAM: A 65nm 17.96 TOPS/W 97.55%-Sparse-Activity Hybrid Mixed-Signal/Digital Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics
Accurate prediction of spectral regrowth and in-channel distortion based on CDMA signal time-domain model
The prospect of 3D-IC
A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation
Low dropout regulators
A monolithically integrated, optically clocked 10 GS/s sampler with a bandwidth of >30 GHz and a jitter of <30 fs in photonic SiGe BiCMOS technology
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration
A 2.5MHz BW and 78dB SNDR delta-sigma modulator using dynamically biased amplifiers
Real-world SoC design methods and applications
Robust multi-GHz (7.4GHz) on-chip image rejection in CMOS
Charge-Based Compact Modeling of Multiple-Gate MOSFET
A 0.5-3 GHz I/Q Interleaved Direct-Digital RF Modulator with up to 320 MHz Modulation Bandwidth in 40 nm CMOS
Thermal modeling methodology for efficient system-level thermal analysis
Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security System
Session 21 - Leveraging the third Dimension
Wideband mmWave CML static divider in 65nm SOI CMOS technology
Power management subsystem with bi-directional DC to DC converter for μ-power biomedical applications
A GaN-on-Si Gate Driver with 14.7X Reduction in Tailing Current Loss and 37.0% Reduction of Reverse Conduction Loss
A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions
MOSFET scaling trends and challenges through the end of the roadmap
3D-IC Chiplet Integrated Power Supply with LDO, SCVR, and Buck DC-DC Converter
Efficiency improvement techniques for RF power amplifiers in deep submicron CMOS
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters
280-GHz schottky diode detector in 130-nm digital CMOS
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications
Process variation tolerant all-digital multiphase DLL for DDR3 interface
Structure-aware high-dimensional performance modeling for analog and mixed-signal circuits
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control
Fully integrated power-efficient AC-to-DC converter design in inductively-powered biomedical applications
A 150MHz-400MHz DLL-Based Programmable Clock Multiplier with -7OdBc Reference Spur in 0.18um CMOS
Probabilistic aspects of crosstalk problems in CMOS ICs
MOSFET modeling for low noise, RF circuit design
A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring
A 1.0 V 40mW 10b 100MS/s pipeline ADC in 90nm CMOS
A near-zero cross-regulation single-inductor bipolar-output (SIBO) converter with an active-energy-correlation control for driving cholesteric-LCD
Firm IP development: methodology and deliverables
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection
Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures
Multi-protocol embedded PCS IP in a FPGA-SOC
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer
MOSFET HF distortion behavior and modeling for RF IC design
A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications
A Sub-1V Analog-Assisted Inverter-Based Digital Low-Dropout Regulator with a Fast Response Time at 25mA/100ps and 99.4% Current Efficiency
A SAR-Assisted DC-Coupled Chopper-Stabilized 20μs-Artifact-Recovery $\Delta \Sigma$ ADC for Simultaneous Neural Recording and Stimulation
A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellation
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process
Data converters
A 90.1dB SNDR, 180.2dB FoMSNDR, 10kHz BW Gm-C-based Δ Σ. ADC with Capacitive Input Feedforward and Duty-Cycled Gm Technique
All-digital 90° phase-shift DLL with a dithering jitter suppression scheme
An Ultra-Low-Power Power Management IC for Wireless Sensor Nodes
A Web Tool for Interactive Exploration of Analog Design Tradeoffs