yusuke1997/dblp-id-title huggingface dataset:
Software Architectural Transformations: A New Approach to Low Energy Embedded Software
Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries
Topology-aware virtual resource management for heterogeneous multicore systems
Parallel probe based dynamic connection setup in TDM NoCs
PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators
Non-Linear Components for Mixed Circuits Analog Front-End
Reconfigurable SoC - What Will it Look Like?
On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages
GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects
Zero-Shot Classification Using Hyperdimensional Computing
Programming quantum computers using design automation
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation
A Fairness Conscious Cache Replacement Policy for Last Level Cache
A Novel Technique for Improving Temperature Independency of Ring-ADC
TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism
Hard Real-Time Scheduling of Streaming Applications Modeled as Cyclic CSDF Graphs
Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning
Topology-agnostic fault-tolerant NoC routing method
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Enabling and supporting car-as-a-service by digital twin modeling and deployment
Layered, Multi-Threaded, High-Level Performance Design
Test Data Compression Based on Output Dependence
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits
Ambient variation-tolerant and inter components aware thermal management for mobile system on chips
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling
ClassONN: Classification with Oscillatory Neural Networks Using the Kuramoto Model
Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocation
Logical Reliability of Interacting Real-Time Tasks
Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochips
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits
An efficient Quantum-Dot Cellular Automata adder
Sequential Permissible Functions and their Application to Circuit Optimization
Availability enhancement and analysis for mixed-criticality systems on multi-core
Analysis of multi-domain scenarios for optimized dynamic power management strategies
Non-intrusive program tracing of non-preemptive multitasking systems using power consumption
Functional test generation using property decompositions for validation of pipelined processors
Optimized model checking of multiple properties
Elimination of multi-cycle false paths by state encoding
Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories
RAGra: Leveraging Monolithic 3D ReRAM for Massively-Parallel Graph Processing
Power-efficient accelerator allocation in adaptive dark silicon many-core systems
TDO-CIM: Transparent Detection and Offloading for Computation In-memory
Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience
A Model for System-Level Timed Analysis and Profiling
Arithmetic Reasoning in DPLL-Based SAT Solving
Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning
Spectral decision diagrams using graph transformations
Bit-Flipping Scan - A unified architecture for fault tolerance and offline test
Effective cache bank placement for GPUs
Analog Circuit Anti-Piracy Security by Exploiting Device Ratings
Property directed invariant refinement for program verification
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
The input pattern fault model and its application
A novel FPGA-based system for Tumor Growth Prediction
Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Diagnostic Testing of Embedded Memories Using BIST
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters
Reconciling QoS and Concurrency in NVIDIA GPUs via Warp-Level Scheduling
Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithm
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
A Compiler Phase to Optimally Split GPU Wavefronts for Safety-Critical Systems
An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode
Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems
Beware of the Bias - Statistical Performance Evaluation of Higher-Order Alphabet PUFs
ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits
Wireless sensor network simulation for security and performance analysis
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks
Heterogeneous systems on chip and systems in package
Hardware Acceleration of Explainable Machine Learning
An Effective General Connectivity Concept for Clustering
Workload-aware voltage regulator optimization for power efficient multi-core processors
Efficient Approximation of Performance Spaces for Analog Circuits via Multi-Objective Optimization
A High-Voltage Low-Power DC-DC buck regulator for automotive applications
Polynomial Formal Verification of Floating Point Adders
A Scalable Architecture for LDPC Decodin
An adaptive approach for online fault management in many-core architectures
Multi-armed bandits for efficient lifetime estimation in MPSoC design
One More Motivation to Use Evaluation Tools This Time for Hardware Multiplicative Masking of AES
De-RISC: A Complete RISC-V Based Space-Grade Platform
Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent Memory
Standard bus vs. bus wrapper: what is the best solution for future SoC integration?
Benefits of green energy and proportionality in high speed wide area networks connecting data centers
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus
Networks on chips for high-end consumer-electronics TV system architectures
Optimizing Majority-Inverter Graphs with functional hashing
Wireless interconnect for board and chip level
A Framework for Efficient and Binary Clustering in High-Dimensional Space
EDA challenges in the converging application world
Exploiting replicated checkpoints for soft error detection and correction
ASIP design and synthesis for non linear filtering in image processing
Auto-tuning Multi-GPU High-Fidelity Numerical Simulations for Urban Air Mobility
AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging
A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
Hybrid side-channel/machine-learning attacks on PUFs: A new threat?
A CMOS low-voltage, high-gain op-amp
Programmable aging sensor for automotive safety-critical applications
System Level Specification in Lava
Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling
Panel session - Architectures and integration for programmable SoC's
Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?
Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores
A novel embedded system for vision tracking
FPGA-Based Acceleration of MCMC Algorithm through Self-Shrinking for Big Data
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
Resolving the memory bottleneck for single supply near-threshold computing
A model for describing communication between aggregate objects in the specification and design of embedded systems
Generating instruction streams using abstract CSP
Designing Secure Space Systems
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation
Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching
SACK: Enabling Environmental Situation-Aware Access Control for Vehicles in Linux Kernel
Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory
PESEC - A Simple Power-Efficient Single Error Correcting Coding Scheme for RRAM
Smart systems at ST
Dude, is my code constant time?
Improving the Schedule Quality of Static-List Time-Constrained Scheduling
Delay analysis of structural real-time workload
Re-configuration of sub-blocks for effective application of time domain tests
An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVM
Variability-aware dark silicon management in on-chip many-core systems
NetCut: Real-Time DNN Inference Using Layer Removal
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
PCASA: Probabilistic control-adjusted Selective Allocation for shared caches
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability
Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink Models
FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, Automation And Test In Europe (DATE 2016), Dresden, Germany, March 18th, 2016
Designing FlexRay-based automotive architectures: A holistic OEM approach
PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy
Online Rare Category Detection for Edge Computing
Error Simulation Based on the SystemC Design Description Language
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
Digital Emulation of Oscillator Ising Machines
Two methods for 24 Gbps test signal synthesis
On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits
A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUs
Sampling-based buffer insertion for post-silicon yield improvement under process variability
Instruction Re-encoding Facilitating Dense Embedded Code
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Using ontologies for dataset engineering in automotive AI applications
Mitigation of NBTI induced performance degradation in on-chip digital LDOs
Optimization of stateful hardware acceleration in hybrid architectures
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints
An improved RF loopback for test time reduction
Power-Aware Network Swapping for Wireless Palmtop PCs
A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training
On Concurrent Error Detection with Bounded Latency in FSMs
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control
Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform
Energy Optimization in NCFET-based Processors
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration
Combinational trace signal selection with improved state restoration for post-silicon debug
Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications
Reversible logic synthesis of k -input, m -output lookup tables
Reconfigurable embedded systems applications for versatile biomedical measurements
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
Øzone: Efficient execution with zero timing leakage for modern microarchitectures
Evaluating the potential of graphics processors for high performance embedded computing
Generating the trace qualification configuration for MCDS from a high level language
Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems
Reuse-based test access and integrated test scheduling for network-on-chip
Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs
PUF modeling attacks: An introduction and overview
NUMANA: a hybrid <u>num</u>erical and <u>ana</u>lytical thermal simulator for 3-D ICs
Accumulator-based BIST approach for stuck-open and delay fault testing
Variation tolerant NoC design by means of self-calibrating links
Interactive presentation: Towards a methodology for the quantitative evaluation of automotive architectures
A robust approach for process variation aware mask optimization
Novel Technique for Testing FPGAs
Hybrid Digital-Digital In-Memory Computing
RAM Testing Algorithm for Detection Linked Coupling Faults
SBQ: Exploiting Significant Bits for Efficient and Accurate Post-Training DNN Quantization
Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs
A production-oriented measurement method for fast and exhaustive Iddq tests
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters
On the Design of Self-Checking Functional Units Based on Shannon Circuits
Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS?
When clusters meet partitions: new density-based methods for circuit decomposition
AsymSAT: Accelerating SAT Solving with Asymmetric Graph-Based Model Prediction
Mathematical approach based on a "Design of Experiment" to simulate process variations
DS-Cache: A Refined Directory Entry Lookup Cache with Prefix-Awareness for Mobile Devices
Decentralized Autonomous Architecture for Resilient Cyber-Physical Production Systems
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations
Mixed-signal design of a digital input power amplifier for automotive audio applications
Architectural Power Optimization by Bus Splitting
System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station
Monolithic 3D integration: a path from concept to reality
Parallel programming with SystemC for loosely timed models: a non-intrusive approach
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Achieving Determinism in Adaptive AUTOSAR
Design Technology for Networked Reconfigurable FPGA Platforms
MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis
Exploiting expendable process-margins in DRAMs for run-time performance optimization
Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs
Automatic Timing Model Generation by CFG Partitioning and Model Checking
Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM
Unifying Temporal and Spatial Locality for Cache Management inside SSDs
Revamping timing error resilience to tackle choke points at NTC systems
Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures
CASCO: Cascaded Co-Optimization for Holistic Neural Network Acceleration
Economics Modelling and Optimisation of MCM Test Strategies
On the correctness, optimality and precision of Static Probabilistic Timing Analysis
Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer
Reliability- and process variation-aware placement for FPGAs
ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis
On reducing busy waiting in autosar via task-release-delta-based runnable reordering
False Path Elimination in Quasi-Static Scheduling
Further improve circuit partitioning using GBAW logic perturbation techniques
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces
An Adaptive UAV Scheduling Process to Address Dynamic Mobile Network Demand Efficiently
Optimal Hardware Pattern Generation for Functional BIST
Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User Experience
Novel inexact memory aware algorithm co-design for energy efficient computation: algorithmic principles
An Arithmetic Structure for Test Data Horizontal Compression
Software implementation of Tate pairing over GF(2 m )
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot
A Single-Package Solution for Wireless Transceivers
FlashPower: A detailed power model for NAND flash memory
Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware
Efficient Hold Buffer Optimization by Supply Noise-Aware Dynamic Timing Analysis
Design techniques for cross-layer resilience
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures
Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC
Adaptive thermal management for portable system batteries by forced convection cooling
Alternating Strategies for Sequential Circuit ATPG
A Bus Delay Reduction Technique Considering Crosstalk
Synthesis for Manufacturability: A Sanity Check
Making the Relationship between Uncertainty Estimation and Safety Less Uncertain
A CNN-inspired mixed signal processor based on tunnel transistors
Effective power network prototyping via statistical-based clustering and sequential linear programming
Machine Learning Based Real-Time Industrial Bin-Picking: Hybrid and Deep Learning Approaches
Adaptive Prefetching for Multimedia Applications in Embedded Systems
Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms
Partial Scan High-Level Synthesis
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation
Receptive-Field and Switch-Matrices Based ReRAM Accelerator with Low Digital-Analog Conversion for CNNs
Using filesystem virtualization to avoid metadata bottlenecks
Fast time-domain simulation for reliable fault detection
Coverage evaluation of post-silicon validation tests with virtual prototypes
MEDEA+ and ITRS Roadmaps
PSP-Cache: A low-cost fault-tolerant cache memory architecture
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures
Exploring the unknown through successive generations of low power and low resource versatile agents
Testing for SoCs with advanced static and dynamic power-management capabilities
DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring
ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s
vProfile: Voltage-Based Anomaly Detection in Controller Area Networks
Segment-Wise Accumulation: Low-Error Logarithmic Domain Computing for Efficient Large Language Model Inference
EDT: A specification notation for reactive systems
A constructive approach towards correctness of synthesis-application within retiming
Worst-Case and Average-Case Analysis of n-Detection Test Sets
March Tests for Word-Oriented Memories
A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
Optimal dimensioning of active cell balancing architectures
SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits
Autonomous System Design Session - Benefits, Challenges and Risks in Various Application Domains
Multi-objective aware extraction of task-level parallelism using genetic algorithms
Cross layer resiliency in real world
Process variation tolerant low power DCT architecture
An adaptable FPGA-based System for Regular Expression Matching
GLA: gate-level abstraction revisited
An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation
DIP Learning on CAS-Lock: Using Distinguishing Input Patterns for Attacking Logic Locking
A workflow for runtime adaptive task allocation on heterogeneous MPSoCs
Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking
Finite Precision bit-width allocation using SAT-Modulo Theory
Testing scheme for IC's clocks
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories
Mitigation of Sense Amplifier Degradation Using Skewed Design
Energy evaluation of software implementations of block ciphers under memory constraints
Fast and efficient construction of BDDs by reordering based synthesis
C-PO: A Context-Based Application-Placement Optimization for Autonomous Vehicles
Technology Mapping and Retargeting for Field-Programmable Analog Arrays
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Architectural exploration for datapaths with memory hierarchy
BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems
Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation
Validating scheduling transformation for behavioral synthesis
OpenSerDes: An Open Source Process-Portable All-Digital Serial Link
Mixed-signal circuits and boards for high safety applications
Combining module selection and replication for throughput-driven streaming programs
AFPR-CIM: An Analog-Domain Floating-Point RRAM -based Compute- In- Memory Architecture with Dynamic Range Adaptive FP-ADC
Detecting Backdoor Attacks in Black-Box Neural Networks through Hardware Performance Counters
Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology
Gate Sizing Using a Statistical Delay Model
A comparative study of algorithms for A/D converter performance evaluation by statistical analysis
Analyzing the impact of process variations on parametric measurements: Novel models and applications
Using Combinational Verification for Sequential Circuits
Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes
SenseDSE: Sensitivity-Based Performance Evaluation for Design Space Exploration of Microarchitecture
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting
Verifying jitter in an analog and mixed signal design using dynamic time warping
Heterogeneous Programmable Logic Block Architectures
FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks
Model-based actor multiplexing with application to complex communication protocols
Probabilistic application modeling for system-level perfromance analysis
Emerging solutions technology and business views for the ubiquitous communication
Design and verification of the sequential systems automata using temporal logic specifications
Embedded Tutorial - Software for Wireless Networked Embedded Systems