yusuke1997/dblp-id-title huggingface dataset:
Emerald: An Architecture-Driven Tool Compiler for FPGAs
Parallel-beam backprojection: an FPGA implementation optimized for medical imaging
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)
FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know It
GraphOps: A Dataflow Library for Graph Analytics Acceleration
Accurately evaluating application performance in simulated hybrid multi-tasking systems
Reducing pin and area overhead in fault-tolerant FPGA-based designs
Implementing a RAKE receiver for wireless communications on an FPGA-based computer system
BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
A Reconfigurable Accelerator for Sparse Convolutional Neural Networks
A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only)
Elastic CGRAs
Visual System Integrator: Invited Tutorial
Constructing Concurrent Data Structures on FPGA with Channels
Tolerating operational faults in cluster-based FPGAs
Spectral-Based Multi-Way FPGA Partitioning
RapidStream: Parallel Physical Implementation of FPGA HLS Designs
Overview of Complex Array-Based PLDs
Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only)
Hardware implemented real-time operating system (abstract only)
FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet
Improving high level synthesis optimization opportunity through polyhedral transformations
Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station
High throughput and large capacity pipelined dynamic search tree on FPGA
SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured Sparsity in Binary Neural Network
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only)
Multi-ported memories for FPGAs via XOR
A compiled accelerator for biological cell signaling simulations
Data reorganization engines for the next generation of system-on-a-chip FPGAs
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
A generic lookup cache architecture for network processing applications
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network
DNNVM: End-to-End Compiler Leveraging Operation Fusion on FPGA-based CNN Accelerators
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000
FPL Based Logic Synthesis of Squarers Using VHDL
An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection
Instruction set extension with shadow registers for configurable processors
Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only)
0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL
Co-synthesis of FPGA-based application-specific floating point simd accelerators
Bridging the GPGPU-FPGA efficiency gap
Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search
HGA: A Hardware-Based Genetic Algorithm
Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA
A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, FPGA 1999, Monterey, CA, USA, February 21-23, 1999
Reprogrammable network packet processing on the field programmable port extender (FPX)
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Effect of fixed-point arithmetic on deep belief networks (abstract only)
The effect of post-layout pin permutation on timing
Armada: timing-driven pipeline-aware routing for FPGAs
An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops
A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow
Parrot: A More Effective Parallel Routing Approach to FPGAs
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing
An FPGA architecture with enhanced datapath functionality
Fast Integrated Tools for Circuit Design with FPGAs
Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs
Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA
High-level modeling and FPGA prototyping of microprocessors
How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms
Design and implementation of packet classification with FPGA (abstract only)
E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural Networks
Test and recovery for fine-grained nanoscale architectures
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
A flexible hardware architecture for 2-D discrete wavelet transform
Low-power technology mapping for FPGA architectures with dual supply voltages
Plasma: An FPGA for Million Gate Systems
Block and IP Wrapping for Efficient Design on FPGAs (Abstract)
I/O placement for FPGAs with multiple I/O standards
Acceleration of the long read mapping on a PC-FPGA architecture (abstract only)
Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers
A Framework for Customizable FPGA-based Image Registration Accelerators
Implementation of digital fixed-point approximations to continuous-time IIR filters
VirtualRC: a virtual FPGA platform for applications and tools portability
Don't Care Discovery for FPGA Configuration Compression
BBFEX: a bloom-bloomier filter extension for long patterns in FPGA-based pattern matching system (abstract only)
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA
32-bit floating-point FPGA gaussian elimination
FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs
On hybrid memory allocation for FPGA behavioral synthesis (abstract only)
Scheduling Data in Neural Network Applications
Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only)
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs
Microblaze: an application-independent fpga-based profiler (abstract only)
High speed FIR filter implementation using add and shift method
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Stratix 10 NX Architecture and Applications
HW/SW methodologies for synchronization in FPGA multiprocessors
Circuit Partitioning for Dynamically Reconfigurable FPGAs
End-to-End Optimization of Deep Learning Applications
Reconfigurable computing with multiscale data fusion for remote sensing
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)
Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs
Performance benefits of monolithically stacked 3D-FPGA
Efficient ASIP design for configurable processors with fine-grained resource sharing
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks
An FPGA generator for multipoint distributed random variables (abstract only)
Exploring duty cycle distortions along signal paths in FPGAs (abstract only)
A Framework for Generating High Throughput CNN Implementations on FPGAs
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Attacking the semantic gap between application programming languages and configurable hardware
DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS
Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems
Real-time high-definition stereo matching on FPGA
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs
A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only)
ORCA: A New Architecture for High-Performance FPLs
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL
An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits
Application-specific instruction generation for configurable processor architectures
ScalaBFS: A Scalable BFS Accelerator on FPGA-HBM Platform
HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication
Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only)
Designing with extreme parallelism
Efficient utilization of heterogeneous routing resources for FPGAs (abstract only)
Performance estimation framework for automated exploration of CPU-accelerator architectures
MORP: makespan optimization for processors with an embedded reconfigurable fabric
Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only)
Entropy, Counting, and Programmable Interconnect
Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs
BiS-KM: Enabling Any-Precision K-Means on FPGAs
Improving FPGA Performance with a S44 LUT Structure
An FPGA-based RNN-T Inference Accelerator with PIM-HBM
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)
Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays
A streaming FPGA implementation of a steerable filter for real-time applications (abstract only)
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM
A novel minloop SB design to improve FPGA routability
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI
Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits
Efficient FPGA Implementation of Conjugate Gradient Methods for Laplacian System using HLS
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology
ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only)
FPGA Power Estimation Using Automatic Feature Selection (Abstract Only)
A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme
Algorithm analysis and mapping environment for adaptive computing systems (poster abstract)
An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs
The shunt: an FPGA-based accelerator for network intrusion prevention
DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity
Degradation in FPGAs: measurement and modelling
A synthesis oriented omniscient manual editor
DynaRapid: From C to FPGA in a Few Seconds
Retrieving 3-d information with FPGA-based stream processing
Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design
FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization
Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective
XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs
Reconfigurable randomized K-way graph partitioning
Fast Inference of Deep Neural Networks for Real-time Particle Physics Applications
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap
Building a faster boolean matcher using bloom filter
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
Folded Integer Multiplication for FPGAs
FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only)
A comparison of via-programmable gate array logic cell circuits
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Automatic SoC design flow on many-core processors: a software hardware co-design approach for FPGAs
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs
Towards automated ECOs in FPGAs
Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data
Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only)
FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract)
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware
FPGA-Oriented Design Space Exploration of a Real-Time Road Scene Semantic Segmentation Deep Neural Network
An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only)
Improvements to technology mapping for LUT-based FPGAs
POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations
Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System
Procedural Texture Mapping on FPGAs
A novel high throughput reconfigurable FPGA architecture
Combining low-leakage techniques for FPGA routing design
No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling
Big data genome sequencing on Zynq based clusters (abstract only)
EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only)
Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial
An FPGA-based Pentium in a complete desktop system
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)
Eliminating the memory bottleneck: an FPGA-based solution for 3d reverse time migration
A power side-channel-based digital to analog converterfor Xilinx FPGAs
Universal Switch-Module Design for Symmetric-Array-Based FPGAs
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
Technologies and Utilization fo Field Programmable Gate Arrays
A real-time stereo vision system using a tree-structured dynamic programming on FPGA
Design and Implementation of a Field Programmable Analogue Array
Efficient multi-ported memories for FPGAs
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
A Novel Predictable Segmented FPGA Routing Architecture
Storage Mirroring for Bare-Metal Systems on FPGA Devices
Flexible FPGA Architecture Realized of General Purpose SOG
FPGA based RAID 6 hardware accelerator
Soft error rate estimation and mitigation for SRAM-based FPGAs
Optimizing effective interconnect capacitance for FPGA power reduction
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators
PipeRoute: a pipelining-aware router for FPGAs
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only)
On Designing ULM-based FPGA Logic Modules
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement
FPGAs in the Cloud
Matching and searching analysis for parallel hardware implementation on FPGAs
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
Line-level incremental resynthesis techniques for FPGAs
Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only)
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only)
A New High Density and Very Low Cost Reprogrammable FPGA Architecture
Performance Driven Floorplanning for FPGA Based Designs
Take the Highway: Design for Embedded NoCs on FPGAs
ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA
Least-significant bit optimization techniques for FPGAs
An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing
Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis
High-speed systolic array for gene matching
FPGA Accelerators for Robust Visual SLAM on Humanoid Robots
A clustering framework for task partitioning based on function-level data usage analysis
Advantages of the XC6000 Architecture for Embedded System Design (Abstract)
Design of programmable interconnect for sublithographic programmable logic arrays
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only)
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)
FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA, February 23-25, 2020
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only)
Skew-programmable clock design for FPGA and skew-aware placement
Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only)
FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only)
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA
Fully-functional FPGA prototype with fine-grain programmable body biasing
A versatile, low latency HyperTransport core
Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware (Abstract Only)
A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators
End-to-End Acceleration of Homomorphic Encrypted CNN Inference on FPGAs
Synthetic circuit generation using clustering and iteration
FPGA-Accelerated Samplesort for Large Data Sets
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract)
Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling
A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only)
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
Floating-point sparse matrix-vector multiply for FPGAs
High-Level Synthesis Using Genetic Algorithms for Dynamically Reconfigurable FPGAs (Abstract)
Practical Applications of Recursive VHDL Components in FPGA Synthesis
Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)
An FPGA-based video compressor for H.263 compatible bit streams
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses
Wire type assignment for FPGA routing
An FPGA-based Fine Tuning Accelerator for a Sparse CNN
FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoC
FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)
TORCH: a design tool for routing channel segmentation in FPGAs
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs
The X-MatchLITE FPGA-Based Data Compressor
A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)
APMC: advanced pattern based memory controller (abstract only)
Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design
Architecture Issues and Solutions for a High-Capacity FPGA
FPGA Implementation of Systolic Sequence Alignment
Constrained clock shifting for field programmable gate arrays
FPGA-based Trainable Autoencoder for Communication Systems
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs
A C compiler for a processor with a reconfigurable functional unit
Placement of repair circuits for in-field FPGA repair
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only)
In-system FPGA prototyping of an itanium microarchitecture
Lattice adaptive filter implementation for FPGA
High-Energy Physics on DECPeRLe-1 Programmable Active Memory
The Design of RPM: An FPGA-based Multiprocessor Emulator
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
Scala Based FPGA Design Flow (Abstract Only)
Defect recovery in nanodevice-based programmable interconnects (abstract only)
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018
BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA
FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only)
Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays
DPGA Utilization and Application
ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA
BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators
Improving bitstream compression by modifying FPGA architecture
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only)
Using sparse crossbars within LUT
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)
Effective clustering technique to optimize routability of outer cluster nets
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs
A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only)
Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
A reconfigurable architecture for network intrusion detection using principal component analysis
High throughput and programmable online trafficclassifier on FPGA
Flexible implementation of genetic algorithms on FPGAs
Communication bottleneck in hardware-software partitioning
ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling