yusuke1997/dblp-id-title huggingface dataset:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management
Al/HfO2/Si Gate Stack with Improved Physical and Electrical Parameters
Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated
EM simulation [ICs and MCMs]
A General Reconfiguration Technique for Fault Tolerant Processor Architectures
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts
Optimal Voltages and Sizing for Low Power
On-Line Synthesis for Partially Reconfigurable FPGAs
Scaling Up Of Wave Pipelines
Advancing Neural Network Performance with Probabilistic Computing for ReLU Function
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU
Bidirectional Spiking Neuron Based Dual-Mode Signal Acquisition Front-End System
Delay Fault Coverage Enhancement Using Multiple Test Observation Times
Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency Circuits
A Generic Implementation of Barriers Using Optical Interconnects
Timing Driven Multi-FPGA Board Partitioning
COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures
Partial Scan Selection Based on Dynamic Reachability and Observability Information
Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports
AI-Driven Anomaly Detection in Oscilloscope Images for Post-Silicon Validation
Statistical Leakage and Timing Optimization for Submicron Process Variation
GLOVE: A Graph-Based Layout Verifier
Assertion Based Verification Using HDVL
Inductive Verification of Sequential Circuits with a Datapath
Processor Modeling for Hardware Software Codesign
Concurrent RF Test Using Optimized Modulated RF Stimuli
Mutual Testing based on Wavelet Transforms
Accurate Constant Transconductance Generation without Off-Chip Components
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes
A Novel CMOS Full Adder
A Simplified High Speed Parallel Input Convolver
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
Power Optimization in Current Mode Circuits
Detailed Routing of Multi-Terminal Nets in FPGAs
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions
An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication
EPLDs - a Milestone in the World of Logic Design
An ECO Technique for Removing Crosstalk Violations in Clock Networks
IC/FPGA-Package-PCB Design Collaboration
Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals
Power Variability and Its Impact on Design
Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems
Invited Paper: Broadband U-NII Wireless Data
Logic Design and Synthesis with IEEE Logic Symbols in the DEMET System
Formal Verification of Synthesized Mixed Signal Designs Using *BMDs
Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation
Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting
A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG
Scalable Pipelined Micro-Architecture for Wavelet Transform
ASIC Design of the Linearisation Circuit of a PTC Thermistor
Parallel concurrent path-delay fault simulation using single-input change patterns
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization
A VLSI ATM Switch Architecture for VBR Traffic
On Test Pattern Compaction Using Random Pattern Fault Simulation
Self-Immunity Technique to Improve Register File Integrity Against Soft Errors
Primitive Path Delay Fault Identification
A Module Checking Based Converter Synthesis Approach for SoCs
Aliasing Analysis of Spectral Statistical Response Compaction Techniques
Intelligent Scheduling of Smart Appliances in Energy Efficient Buildings: A Practical Approach
Adaptive Forward Body Bias Voltage Generator
65nm Omnibudsman
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices
Synthesis of Analog CMOS Circuits
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard
A Built-in-Self-Test Scheme for Digital to Analog Converters
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic
On the Analysis of Reversible Booth's Multiplier
An Efficient State Assignment Technique using Least Commitment and Constraint Propagation Techniques
Combining State Assignment with PLA Folding
Laout Influenced Factorization of Boolean Functions
A Heuristic for Clock Selection in High-Level Synthesis
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
MAVI: An Embedded Device to Assist Mobility of Visually Impaired
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits
Design, Simulation and Synthesis of an ASIC for Fractal Image Compression
Reconfigurable Processing-in-Memory Architecture for Data Intensive Applications
Synthesis of Testable RTL Designs
Modeling Crosstalk in Resistive VLSI Interconnections
A tree matching chip
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
The Ramifications of Making Deep Neural Networks Compact
NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture
Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency
Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization
Interframe Bus Encoding Technique for Low Power Video Compression
Interconnect Statistical Modeling: Structures and Measurement Methodologies
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
Design of Asynchronous Controllers with Delay Insensitive Interface
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits
Formal Techniques for Hardware Allocation
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification
Energy-Efficient Transceiver for Wireless NoC
Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview
Losses in Multilevel Crossover in VLSI Interconnects
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures
Design and Analysis of an Area and Power Efficient Programmable Delay Cell
Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors
Invited Address: Hybrid Reconfigurable Processors - The Road to Low-Power Consumption
Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based Approach
Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs
Test Pattern Generation for Power Supply Droop Faults
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits
Hierarchical Reconfiguration of VLSI/WSI Arrays
A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment
An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test
Architecture of Reconfigurable a Low Power Gigabit AT Switch
A Silicon Testing Strategy for Pulse-Width Failures
A Transistor Level Placement Tool for Custom Cell Generation
Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes
Geometric bipartitioning problem and its applications to VLSI
System in a Package Design of a RF Front End System Using Application Specific Reduced Order Models
Challenges of Merging Digital Imaging and Wireless Communication
Improved NCV Gate Realization of Arbitrary Size Toffoli Gates
ASIP Design Methodologies : Survey and Issues
An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery Computing
Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations
Design and Simulation of Microfluidic Components towards Development of a Controlled Drug Delivery Platform
Voltage Boosted Schmitt Trigger Sense Amplifier (VBSTSA) With Improved Offset And Reaction Time For High Speed SRAMs
Reducing Leakage with Mixed-V_th (MVT)
Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors
Synthesis of Application Specific Multiprocessor Architectures for Process Networks
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design
LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches
Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs
Inline Assertions - Embedding Formal Properties in a Test Bench
Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture
A New Tuning Scheme for Continuous Time Filters
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC
DESSERT: Design Space Exploration of RT Level Components
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance
A New Reliable Method for Delay-Fault Diagnosis
Instruction-Set-Extension Exploration Using Decomposable Heuristic Search
A Simple Model for Lindhard Continuum Potential useful for Channeling Simulation
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design
Testable Realizations of CMOS Combinatorial Circuits for Voltage and Current Testing
An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture
Strategies for Improving Data Locality in Embedded Applications
A new switching-level approach to multiple-output functions synthesis
Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units
System Support for Embedded Applications
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles
Hierarchical Error Diagnosis Targeting RTL Circuits
Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques
Scalable Test Generation by Interleaving Concrete and Symbolic Execution
Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences
An 800µW Peak Power Consumption, 24GHz (K-Band), Super-Regenerative Receiver with 200p J/bit Energy Efficiency, for IoT
WCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad Memories
Machine Learning based Waveform Predictions using Discrete Wavelet Transform for Automated Verification of Analog and Mixed Signal Integrated Circuits
Invited Address: The InfoPad Project: Review and Lessons Learned
Novel Hardware Architectures for PRESENT Block Cipher and its FPGA Realizations
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Combined optimization of area and testability during state assignment of PLA-based FSM's
Methods for Dynamic Test Vector compaction in Sequential Test Generation
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)
Introduction to SystemC
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation
Emerging Frontiers in Embedded Security
Cone Resynthesis ECO Methodology for Multi-Million Gate Designs
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems
Parallel VLSI-Routing Models for Polymorphic Processors Array
Fault Collapsing Using a Novel Extensibility Relation
Parallel Decoder for Cellular Automata Based Byte Error Correcting Code
Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs
Synthesizing A Long Latency Unit Within Vliw Processor
Advancing Functional Safety: Improving Failure Mode Analysis and Fault Injection Using Automation and GNN Algorithms
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels
A Two-dimensional Systolic Array Processor for Image Processing
Channel routing in Manhattan-diagonal model
A Systematic Study on the Hysteresis Behaviour and Reliability of MoS2 FET
Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture
Analysis of the Pull-In Phenomenon in Microelectromechanical Varactors
Design Space Exploration of an Execution-Driven Functional Simulation Methodology
Modeling and Analysis of Noise Margin in SET Logic
Inexact Decision Circuits: An Application to Hamming Weight Threshold Voting
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application
Sizing Consideration for Leakage Control Transistor
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection
Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis
Embedded Memories in System Design: Technology, Application, Design and Tools
Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and Optimization of Back Gate Parameters
Simulated Annealing for Target-Oriented Scan
An Efficient Practical Heuristic For Good Ratio-Cut Partitioning
Lithography Driven Layout Design
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation
ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance
A Test Function Architecture for Interconnected Finite State Machines
Logic Verification of Very Large Circuits Using Shark
Design Of A Universal BIST (UBIST) Structure
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage
Energy-Efficient, High Performance Circuits for Arithmetic Units
InsectEye: An Intelligent Trap for Insect Biodiversity Monitoring
A Fast Algorithm for Performing Vector Quantization and its VLSI Implementation
Post Silicon Validation for I2C (SMBUS) Peripheral
An Optimized Design of Reversible Quantum Comparator
An ASIC for Cellular Automata Based Message Authentication
A Heuristic for Decomposition in Multi-Level Logic Optimization
Hybrid CMOS/Molecular Electronic Circuits
Modeling Usable and Reusable Transactors in System Verilog
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems
Modeling of Nonuniform Interconnects by Using Differential Quadrature Method
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs
Logic minimization based approach for compressing image data
SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks
Soft Error Rates with Inertial and Logical Masking
Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator Design
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits
A modular systolic architecture for delayed least mean squares adaptive filtering
Boosting System-on-Chip Performance Through AI-Assisted Optimization Using Compositional Neural Networks
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis
A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor
Custom Reconfigurable Architecture for Autonomous Fault-Recovery of MEMS Vibratory Sensor Electronics
A Unified Approach for IP Protection across Design Phases in a Packaged Chip
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection
Analyzing Soft Errors in Leakage Optimized SRAM Design
A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer
Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics
A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip
ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure Analysis
Dual rail static CMOS architecture for wave pipelining
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling
Design Of Provably Correct Storage Arrays
Variability-Tolerant Register-Transfer Level Synthesis
A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination
A Nanosensor Array-Based VLSI Gas Discriminator
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality
An asynchronous algorithm for sequential circuit test generation on a network of workstations
Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and Applications
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency
Design of an ASIC for Straight Line Detection in an Image
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures
Analog/RF Physical Layer Issues For UWB Systems
A Library for Passive Online Verification of Analog and Mixed-Signal Circuits
Cubical CAMP for minimization of Boolean functions
A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology
A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor
Exploring Use of NoC for Reconfigurable Video Coding
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair
A 100-nW Sensitive RF-to-DC CMOS Rectifier for Energy Harvesting Applications
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs
Pattern Based Synthetic Benchmark Generation for Hardware Security Applications
On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI Chips
A Modified SRAM Based Low Power Memory Design
Developing A New Approach For Multimedia Design
Hardware-corroborated Variability-Aware SRAM Methodology
Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices
Delay-Balanced Smart Repeaters for On-Chip Global Signaling
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Algorithm-Based Concurrent Error Detection for FFT Networks
Microelectromechanical Longitudinal Resonator for Frequency Reference Applications
GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications
Characteristic polynomial method for verification and test of combinational circuits
A Low Voltage, Low Noise CMOS RF Receiver Front-End
Minimization of Logic Functions Using Essential Signature Sets
Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors
Computing Stress Tests for Gate Oxide Shorts
Challenges in Implementing Cache-Based Side Channel Attacks on Modern Processors
Spectral RTL Test Generation for Microprocessors
Real-time Melodic Accompaniment System for Indian Music Using TMS320C6713
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees
PLATO: A Tool for Computation of Exact Signal Probabilities
A High Voltage Level Shifter for Automotive Buck Converter with a Fast Transient Response
A 3-dimensional FEM Based Resistance Extraction
A Novel BIST Architecture With Built-in Self Check
Electronic Testing for SOC Designers (Tutorial Abstract)
Improved SAT-Based Bounded Reachability Analysis
HD Resolution Intra Prediction Architecture for H.264 Decoder
An Integrated Technology CAD System for Process and Device Designers
On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications
Negative Voltage Generator and Current DAC Based Regulator For Flash Memory
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics
Efficient variable ordering and partial representation algorithm
Behavioral Modeling of a CMOS Compatible High Precision MEMS Based Electron Tunneling Accelerometer
Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime
A CMOS VLSI Chip for Motion Detection
Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test
On Event Driven Modeling of Continuous Time Systems
Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation
A State Assignment Scheme Targeting Performance and Area
Interconnect Energy Dissipation in High-Speed ULSI Circuits
Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage Regulators
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks
Systems, Nano-technology and SiP
Rapid Synthesis of Multi-Chip Systems
Explicit Safety Property Strengthening in SAT-based Induction
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective
A Compact Temperature Sensor at 1.8µA per Hz Conversion Rate and 1.1 °C Accuracy for SOCs
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
A Tuned Wideband LNA in 0.25µm IBM Process For RF Communication Applications
Early Execution for Soft Error Detection