yusuke1997/dblp-id-title huggingface dataset:
A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads
Neural network-based accelerators for transcendental function approximation
A linear programming approach for minimum NBTI vector selection
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
Power-Efficient Approximate Multiplier Using Adaptive Error Compensation
On the Role of Sequential Circuits in Stochastic Computing
IO-Optimized Design-Time Configurable Negacyclic Seven-Step NTT Architecture for FHE Applications
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications
An Accurate Interconnection Length Estimation for Computer Logic
Methodology to achieve higher tolerance to delay variations in synchronous circuits
TinyML Based Stress Detection utilizing PPG Signals: A Lightweight Approach for Smart Wearable Devices
Design of an UHF RFID transponder for secure authentication
Self-Checking of FPGA-Based Control Units
Session details: Session 4B: VLSI for Machine Learning and Artifical Intelligence 2
A chip solution to hierarchical and boundary-scan compatible board level BIST
New technique in design of active rf cmos mixers for low flicker noise and high conversion gain
A Brain-inspired Approach for Malware Detection using Sub-semantic Hardware Features
Performance modeling of virtualized custom logic computations
Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage
An efficient net ordering algorithm for buffer insertion
Design and evaluation of fault tolerance techniques for highly parallel architectures
Partitioned n-detection test generation
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers
Models for power consumption and power grid noise due to datapath transition activity
Energy saving for memory with loop scheduling and prefetching
Aphelios: A Selective Lock-step Neural Processing Unit Design
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
An efficient algorithm for partitioning parameterized polygons into rectangles
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications
A model to exploit power-performance efficiency in superscalar processors via structure resizing
TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
A stacked antenna broad-band RFID front-end for UHF and microwave bands
Innovations in IoT for a Safe, Secure, and Sustainable Future
Probabilistic Bayesian Neural Networks for Efficient Inference
An efficient algorithm for custom instruction enumeration
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning
Design of defect tolerant tile-based QCA circuits
Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration
A General Sign Bit Error Correction Scheme for Approximate Adders
ReX-HD: A Deterministic ReRAM-Based Hyperdimensional Computing Framework for Edge Computing
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits
Congestion reduction in traditional and new routing architectures
Energy Harvesting-assisted Ultra-Low-Power Processing-in-Memory Accelerator for ML Applications
Security Aware Placement for Split Manufactured Integrated Circuit Design Flows
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM
Efficient and Effective Digital Waveform Compression for Large-scale Logic Simulation of Integrated Circuit
High throughput overlapped message passing for low density parity check codes
Efficient selection and analysis of critical-reliability paths and gates
A highly regular multi-phase reseeding technique for scan-based BIST
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates
A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs
A dual-core system solution for wearable health monitors
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits
Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM
Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks
Modeling of communication protocols in VHDL
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008
Feature-driven Approximate Computing for Wearable Health-Monitoring Systems
Securing Machine Learning Architectures and Systems
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Optimal Device Sequencing and Kernel Assignment for Multiple Heterogeneous Machine Learning Accelerators
Wirelength-driven force-directed 3D FPGA placement
A current-mode CMOS/memristor hybrid implementation of an extreme learning machine
Unifying functional and parametric timing verification
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM
Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells
Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs
Reliability aware NoC router architecture using input channel buffer sharing
Floorplanning for mixed macro block and standard cell designs
ATM burst traffic generator
Quantum Leak: Timing Side-Channel Attacks on Cloud-Based Quantum Services
7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA
Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units
Automatic Extraction of Requirements from State-based Hardware Designs for Runtime Verification
Fast and accurate estimation of floorplans in logic/high-level synthesis
Adaptive Hard Disk Power Management on Personal Computers
Investigation and Trade-offs in 3DIC Partitioning Methodologies: N/A
Modeling and Analysis of The Difference-Bit Cache
Via configurable three-input lookup-tables for structured ASICs
Technology, CAD tools, and designs for emerging 3D integration technology
Electronics for a greener planet
Power management of variation aware chip multiprocessors
SSFuzz: Generating syntactic and semantic seeds for RISC-V processors
Automatic cell placement for quantum-dot cellular automata
A Cross-Layer Perspective for Energy Efficient Processing: - From beyond-CMOS Devices to Deep Learning
VLSI implementation of controllers for communication protocols from their Petri net models
Power estimation of dividers implemented in FPGAs
A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs
A Distributed Power Grid Analysis Framework from Sequential Stream Graph
A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints
Synthesis of SEU-tolerant ASICs using concurrent error correction
Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application
Monotonic static CMOS tradeoffs in sub-100nm technologies
Optimization techniques for BDD-based bisimulation computation
On automatic generation of RTL validation test benches using circuit testing techniques
A High Speed VLSI Architecture for Scaleable ATM Switches
Test generation for resistive opens in CMOS
Synthesis of a wideband low noise amplifier
SPARTA: Simulation of Physics on a Real-Time Architecture
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks
A 22nm 96.83-TOPS/W Time-Domain Compute-in-Memory Engine Utilizing Mixed-Fidelity for Edge-AI Applications
Design Exploration of IoT centric Neural Inference Accelerators
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning
HSIM-DNN: Hardware Simulator for Computation-, Storage- and Power-Efficient Deep Neural Networks
Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology
The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications
Integer linear programming based energy optimization for banked DRAMs
Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017
BISM: built-in self map for hybrid crossbar nano-architectures
A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects
Multi-DOF Fusion: A Flexible Fusion Strategy for Reducing Redundancy in CNN Workloads
Thermal-aware compilation for system-on-chip processing architectures
Practical approaches to the verification of a telecom megacell using FormalCheck
UPIM: Unipolar Switching Logic for High Density Processing-in-Memory Applications
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators
Dual-Plane Switch Architecture for Time-Triggered Ethernet
Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in Hardware
How an "Evolving" Fault Model Improves the Behavioral Test Generation
A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation
MYGEN: automata-based on-line test generator for assertion-based verification
Digital LIF Neuron for CTT-Based Neuromorphic Systems
Multi-objective topology synthesis and FPGA prototyping framework of application specific network-on-chip
A Lifetime Extension Framework for Communication-Intensive Systems Based on Wavelength-Routed Optical Networks-on-Chip
A Cryogenic Artificial Synapse based on Superconducting Memristor
Performance Analysis of OFA-NAS ResNet Topologies Across Diverse Hardware Compute Units
Test plan generation and concurrent scheduling of tests in the presence of conflicts
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness
On Configurable Defense against Adversarial Example Attacks
Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation
Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
Stochastic computational models for accurate reliability evaluation of logic circuits
Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core Processors
Line width optimization for interdigitated power/ground networks
A multi-level approach to reduce the impact of NBTI on processor functional units
An all Digital BiCMOS Phase Lock Loop for VLSI Processors
Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design
Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes
Area efficient loop filter design for charge pump phase locked loop
Low power VLSI sequential circuit architecture using critical race control
Ethics in Computing Education: Challenges and Experience with Embedded Ethics
Assessing Defect Coverage of Memory Testing Algorithms
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design
Ultrahigh-Speed Circuits Using Resonant Tunneling Devices
Quality of Service-Aware, Scalable Cache Tuning Algorithm in Consumer-based Embedded Devices
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line
Fine-grain reconfigurable logic cells based on double-gate CNTFETs
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks
Statistical Weight Refresh System for CTT-Based Synaptic Arrays
Alchemy : A Methodology for Scalable RTL Design Space Exploration
The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data
Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems
An optimized linear skewing interleave scheme for on-chip multi-access memory systems
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback
VLSI implementation of CORDIC angle units
Right-Provisioned IoT Edge Computing: An Overview
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
ProACt: A Processor for High Performance On-demand Approximate Computing
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution
Design Space Modeling and Simulation for Physically Constrained 3D CPUs
Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks
Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions
Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS
TEM-cell and surface scan to identify the electromagnetic emission of integrated circuits
Area-efficient two-dimensional architectures for finite field inversion and division
Basic building blocks for asynchronous packet routers
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing
Review of Neuromorphic Processing for Vision Sensors
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
Artificial Neural Network Electronic Nose for Volatile Organic Compounds
Synthesis of Real-Time Recursive DSP Algorithms Using Multiple Chips
Analysis of challenges for on-chip optical interconnects
MnM: A Fast and Efficient Min/Max Searching in MRAM
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs
Cutwidth approximation in linear time
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs
PASTA: Partial Scan to Enhance Test Compaction
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding
A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture
Analysis and verification of interconnected rings as clock distribution networks
Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting System for Non-Volatile Processors
VHDL Design of a Test Processor Based on Mixed-Mode Test Generation
Structured and tuned array generation (STAG) for high-performance random logic
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes
A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons
Hierarchical state machine architecture for regular expression pattern matching
Efficient Off-Policy Reinforcement Learning via Brain-Inspired Computing
Modeling of the charging behavior of li-ion batteries based on manufacturer's data
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits
QPUF 3.0: Sustainable Cybersecurity of Smart Grid through Security-By-Design based on Quantum-PUF and Quantum Key Distribution
Horizontal benchmark extension for improved assessment of physical CAD research
Inductance Effects in RLC Trees
Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study
Structural fault tolerance in VLSI-based systems
A taylor series methodology for analyzing the effects of process variation on circuit operation
SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing
A dual band CMOS VCO with a balanced duty cycle buffer
Timing-driven variation-aware nonuniform clock mesh synthesis
ASF-CRB: an Energy-Efficient Activity-Balanced Charge-Recycling Bus Architecture Based on Alternate Signal Flipping
PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures
Formal hardware verification by integrating HOL and MDG
Reliability-aware cross-point resistive memory design
RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO 2 /Hf 1T1R RRAM Memory Cell
TSV power supply array electromigration lifetime analysis in 3D ICS
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology
DrPIM: An Adaptive and Less-blocking Data Replication Framework for Processing-in-Memory Architecture
Estimating path delay distribution considering coupling noise
AI/ML, Optimization and EDA in the TILOS AI Research Institute
A CAD tool for designing large, fault-tolerant VLSI arrays
Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems
An efficient building block layout methodology for compact placement
MuTaTe: an efficient design for testability technique for multiplexor based circuits
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing
Logic block and design methodology for via-configurable structured ASIC using dual supply voltages
Lithography-aware layout compaction
A design methodology for space-time adapter
Equidistance routing in high-speed VLSI layout design
Energy-delay efficiency of VLSI computations
A flow based approach to the pin redistribution problem for multi-chip modules
A design approach dedicated to network-based and conflict-free parallel interleavers
Wirelength reduction by using diagonal wire
A comparative study of power efficient SRAM designs
Dynamic Real-Time Scheduler for Large-Scale MPSoCs
A linear statistical analysis for full-chip leakage power with spatial correlation
Hardware Security in Advanced Manufacturing
Enhancing debugging of multiple missing control errors in reversible logic
An Integrated Approach for Synthesizing LUT Networks
ML4SODA: A Decision Tree Guided Design Space Exploration for Fast and High Quality MLIR-based HLS
A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
EPEX: Processor Verification by Equivalent Program Execution
HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Compound Logic Gates for Pipeline Depth Minimization in Single Flux Quantum Integrated Systems
Speed Binning Using Machine Learning And On-chip Slack Sensors
The 60° grid: routing channels in width d/√3
Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory
Internet-of-Medical-Things
Graph Neural Network based Netlist Operator Detection under Circuit Rewriting
A novel statistical and circuit-based technique for counterfeit detection in existing ICs
Thoughts on Edge Intelligence
Ambipolar double-gate FETs for the design of compact logic structures
Single molecule electronics
ADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory
Dominant critical gate identification for power and yield optimization in logic circuits
Side Channel Attacks vs Approximate Computing
Digital cell macro-model with regular substrate template and EKV based MOSFET model
Voltage-island driven floorplanning considering level-shifter positions
The MGAP Family of Processor Arrays
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks
Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
An evaluation of the impact of gate oxide tunneling on dual- V t -based leakage reduction techniques
Routing methodology for minimizing 1nterconnect energy dissipation
Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications
Low Power and Trusted Machine Learning
Area, performance, and sensitizable paths [logic design]
SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP
Design of MRAM based logic circuits and its applications
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm
System level design language extensions for timed/untimed digital-analog combined system design
A New Faster Algorithm for Iterative Placement Improvement
MDG-based Verification by Retiming and Combinational Transformations
Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)
Abstraction of data path registers for multilevel verification of large circuits
Low Power Memory Architectures for Video Applications
A CORDIC based array architecture for complex discrete wavelet transform
Thermal-aware phase-based tuning of embedded systems
Secure Computing Systems Design Through Formal Micro-Contracts
Energy recovery clocked dynamic logic
PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing
Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering
Variable gain amplifier with offset cancellation
A process variation tolerant self-compensating FinFET based sense amplifier design
A new state assignment technique for asynchronous finite state machines
A fast hybrid carry-lookahead/carry-select adder design
A graph based simplex method for the integer minimum perturbation problem with sum and difference constraints
Ran$Net: An Anti-Ransomware Methodology based on Cache Monitoring and Deep Learning
Distributed Logic Encryption: Essential Security Requirements and Low-Overhead Implementation
Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit
Tuning Memory Fault Tolerance on the Edge
A new approach for modeling and optimization of analog systems
A pipelined clock-delayed domino carry-lookahead adder
Mixed-Cell-Height Standard Cell Placement Legalization
Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories
SAT-attack Resilience Measure for Access Restricted Circuits
A digit serial algorithm for the integer power operation
A two-stage simulated annealing methodology
An evolutionary approach to timing driven FPGA placement
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy
Read-out schemes for a CNTFET-based crossbar memory
SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks
A self-adaptive scheduler for asymmetric multi-cores
The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
A new method for asynchronous pipeline control
A heuristic for data path synthesis using multiport memories
An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs
Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies
A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm
On-chip Sparse Learning with Resistive Cross-point Array Architecture
Parallel VLSI Architectures for Cryptographic Systems
A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations
Router with centralized buffer for network-on-chip
A hybrid framework for application allocation and scheduling in multicore systems with energy harvesting
An FPGA design of AES encryption circuit with 128-bit keys
From single core to multi-core to many core: are we ready for a new exponential?
MemOReL : A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems
Under-the-Cell Routing to Improve Manufacturability
Sharing Electronic Design Data Via Semantic Spaces