yusuke1997/dblp-id-title huggingface dataset:
Superconductive Single-Flux-Quantum Circuit/System Technology and 40Gb/s Switch System Demonstration
A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners
18.3 A 0.5V 54μW ultra-low-power recognition processor with 93.5% accuracy geometric vocabulary tree and 47.5% database compression
A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS
30.1 A 28Gb/mm 2 4XX-Layer 1Tb 3b/Cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/Pin IOs
Energy-efficient high-speed interfaces
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing
24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs
9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence
A 20Gb/s Embedded Clock Transceiver in 90nm CMOS
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS
A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm 3 pressure-sensing system
9.4 A 0.5V 1.15mW 0.2mm 2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components
A 60GHz transmitter with integrated antenna in 0.18µm SiGe BiCMOS technology
1.1 Computing's energy problem (and what we can do about it)
Gigabit CDRs Equalizers
An 800mW Fully Integrated Galvanic Isolated Power Transfer System Meeting CISPR 22 Class-B Emission Levels with 6dB Margin
A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current
A 32-core RISC microprocessor with network accelerators, power management and testability features
Can Multicore Integration Justify the Increased Cost of Process Scalling?
A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS
25.3 AI-Enabled Design Space Discovery and End-to-End Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demonstrating mm-Wave/sub-THz PAs Between 30 and 120GHz
10.4 A 12Gb/s 0.9mW/Gb/s wide-bandwidth injection-type CDR in 28nm CMOS with reference-free frequency capture
Session 10 overview: High-performance digital: High performance digital subcommittee
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR
12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation
A 36V JFET-input bipolar operational amplifier with 1μV/°C maximum offset drift and -126dB total harmonic distortion
A 93.2%-Efficiency Multi-Input Bipolar Energy Harvester with $17.9\times$ MPPT Loss Reduction
21.6 A smart CMOS assay SoC for rapid blood screening test of risk prediction
A 77GHz Phased-Array Transmitter with Local LO-Path Phase-Shifting in Silicon
19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell
An instrument-on-chip for impedance measurements on nanobiosensors with attoFarad resoution
Where CMOS is going: trendy hype vs. real technology
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU
3.5 A 1.0-to-2.5GHz beamforming receiver with constant-Gm vector modulator consuming
A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology
27.4 A 0.8mm 3 ±0.68psi single-chip wireless pressure sensor for TPMS applications
17.5 A 0.07mm 2 2-channel instrumentation amplifier with 0.1% gain matching in 0.16μm CMOS
A mm-sized implantable power receiver with adaptive link compensation
3.4 A 16MHz CMOS RC Frequency Reference with ±400ppm Inaccuracy from -45°C to 85°C After Digital Linear Temperature Compensation
A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1 MPixel EVS with 4.6GEvent/s Readout, In-Pixel TDC and On-Chip ISP and ESP Function
10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications
A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation
33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology
A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS
A 5.4mW 0.07mm 2 2.4GHz Front-End Receiver in 90nm CMOS for IEEE 802.15.4 WPAN
EE6: Return of survey says!
A 260GHz broadband source with 1.1mW continuous-wave radiated power and EIRP of 15.7dBm in 65nm CMOS
29.1 A 22nm FD-SOI <1.2mW/Active-Qubit AWG-Free Cryo-CMOS Controller for Fluxonium Qubits
Chopped rate-to-digital FM gyroscope with 40ppm scale factor accuracy and 1.2dph bias
A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/Hz
A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability
Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee
17.4 A 18.6-to-40.1GHz 201.7dBc/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET
An asynchronous array of simple processors for dsp applications
A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management
35.4: A Miniature Biomedical Implant Secured by Two-Factor Authentication with Emergency Access
A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization
A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput
A 0.64μm 4-Photodiode 1.28μm 50Mpixel CMOS Image Sensor with 0.98e- Temporal Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower
A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensor
A Clock Duty-Cycle Correction and Adjustment Circuit
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration
A 477mW NoC-based digital baseband for MIMO 4G SDR
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS
2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications
Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control
30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell
72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application
Secure AES engine with a local switched-capacitor current equalizer
17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3 rd -Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability
A resonant regulating rectifier (3R) operating at 6.78 MHz for a 6W wireless charger with 86% efficiency
Foreword: Intelligent Chips for a Smart World
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops
1.22μm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88μm-Pitch Event Pixels and up to 10K Event Frame Rate by Adaptive Control on Event Sparsity
A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz
21.3 A 6.45μW self-powered IoT SoC with integrated energy-harvesting power management and ULP asymmetric radios
A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer
Towards a New Nanoelectronic Cosmology
A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS
21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils
A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication
A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic Checksum
The new era of scaling in an SoC world
A Compact 12V-to-1V 91.8% Peak Efficiency Hybrid Resonant Switched-Capacitor Parallel Inductor (ReSC-PL) Buck Converter
A 0.91mW/element pitch-matched front-end ASIC with integrated subarray beamforming ADC for miniature 3D ultrasound probes
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode
8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur
2.8: A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution
A Self-powering Wireless Soil-pH and Electrical Conductance Monitoring IC with Hybrid Microbial Electrochemical and Photovoltaic Energy Harvesting
A Monolithic 26A/mm 2 Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter
6.4 A Resonant High-Voltage Pulser for Battery-Powered Ultrasound Devices
32.4 A Dual-LC-Resonant Isolated DC-DC Converter Achieving 65.4% Peak Efficiency and Inherent Backscattering
3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8 μ W BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference and an Untrimmed Gain Error of ± 0.26 % from -40°C to 125°C
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC
A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition
An 11mm 2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12μm CMOS
A 90% peak efficiency single-inductor dual-output buck-boost converter with extended-PWM control
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing
21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocation
27.1 A Differential Hybrid Class-ED Power Amplifier with 27W Maximum Power and 82% Peak E2E Efficiency for Wireless Fast Charging To-Go
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator
Session 24 overview: Secure, efficient circuits for IoT: Technology directions subcommittee
A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver
25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving -96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI
A 30nA quiescent 80nW-to-14mW power-range shock-optimized SECE-based piezoelectric harvesting interface with 420% harvested-energy improvement
15.1 A 0.0066mm 2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique
A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia Broadcasting
Foundry Future: Challenges in the 21st Century
A 1.2W 51%-Peak-Efficiency Isolated DC-DC Converter with a Cross-Coupled Shoot-Through-Free Class-D Oscillator Meeting the CISPR-32 Class-B EMI Standard
A Programming-Free Three-Dimensional Resonant Current-Mode Wireless Receiver with Real-Time Link-Adaptivity and a 0.904cm 3 Receiver Coil for Implantable Systems
A 74W/48V Monolithic-GaN Integrated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays
11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees
14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications
3.8 A 23.6ppm/°C Monolithically Integrated GaN Reference Voltage Design with Temperature Range from -50°C to 200°C and Supply Voltage Range from 3.9 to 24V
A ±4A high-side current sensor with 25V input CM range and 0.9% gain error from -40°C to 85°C using an analog temperature compensation technique
Efficient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy Storage
A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOS
A passive-mixer-first receiver with baseband-controlled RF impedance matching, ≪ 6dB NF, and ≫ 27dBm wideband IIP3
14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS
Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller
22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces
A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation
23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication
A 21b ±40mV range read-out IC for bridge transducers
A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit
Power/performance optimization of many-core processor SoCs
Session 25 Overview: DRAM Memory Subcommittee
Session 3 overview: Digital processors
A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic
A 210×340×50µm Integrated CMOS System f0r Micro-Robots with Energy Harvesting, Sensing, Processing, Communication and Actuation
23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction
A 4.6μW 3.3-NEF Biopotential Amplifier with 133VPP Common-Mode Interference Tolerance and 102dB Total Common-Mode Rejection Ratio for Two-Electrode Recording System
A Sub-1mm2 Dynamically Tuned CMOS MB-OFDM 3-to-8GHz UWB Receiver Front-End
A Compact Full-Duplex Receiver with Wideband Multi-Domain Hilbert-Transform-Equalization Cancellation Based on Multi-Stage APFs Achieving 65dB SIC Across 120MHz BW
20.10 A 200GHz 200-Pixel 2D Near-Field Imager for Biomedical Applications
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating
A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration
1.3 Working at the Intersection of Machine Learning, Signal Processing, Sensors, and Circuits
10.3 A D-Band 2D-Scalable 4×4 Active Reflective Relay with Orthogonally Polarized on-Chip TX/RX Antennas and in-Front-End Common-Centroid Fast Azimuth/Elevation Angle-of-Arrival Detection
A 200-to-350GHz SiGe BiCMOS Frequency Doubler with Slotline-Based Mode-Decoupling Harmonic-Tuning Technique Achieving 1.1-to-4.7dBm Output Power
Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters
2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming
Intelligent Sensing: Enabling the Next "Automation Age"
71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency
34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder
7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM
14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS
A 10b Source-Driver IC with LSB-Stacked LV-to-HV-Amplify DAC Achieving 2688μm 2 /channel and 4.8mV DVO for Mobile OLED Displays
5.10 A 3.5mW mm-Wave Low-Noise Active Bandpass Filter Employing an All-Passive Interferer-Cancellation Feedforward Path
A wire-speed power TM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads
A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s
Field-coupled nanomagnets for interconnect-free nonvolatile computing
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices
A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process
A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points
A recursive-memory brain-state classifier with 32-channel track-and-zoom Δ 2 Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators
20.1 A 3.5×3.5mm 2 1.47mW/ch 16-Channel MSS-CMOS Heterogeneous Multi-Modal-Gas-Sensor Chip Stack
32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer
A 1V 16.9ppm/°C 250nA Switched-Capacitor CMOS Voltage Reference
SE3 Last Mile Access Options: PON/DSL/Cable/Wireless
17.11 A 9mW Ultrasonic Through Transmission Transceiver for Non-Invasive Intracranial Pressure Sensing
22.7 An inductively-coupled wireless power-transfer system that is immune to distance and load variations
23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications
A 0.7V 36μW 85dB-DR Audio ΔΣ Modulator Using Class-C Inverter
A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end
A 13.5dBm Fully Integrated 200-to-255GHz Power Amplifier with a 4-Way Power Combiner in SiGe: C BiCMOS
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique
Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitor
A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW
17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI
A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic
A 60GHz outphasing transmitter in 40nm CMOS with 15.6dBm output power
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
5.2 0.25-to-4GHz Harmonic-Resilient Receiver with Built-In HR at Antenna and BB Achieving +14/+16.5dBm 3 rd /5 th IB Harmonic B1dB
A 5.4dBm 42mW 2.4GHz CMOS BAW-based quasi-direct conversion transmitter
A 21W 94.8%-Efficient Reconfigurable Single-Inductor Multi-Stage Hybrid DC-DC Converter
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C
Session 31 Overview: Analog Techniques Analog Subcommittee
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter
A CMOS 2D Micro-Fluxgate Earth Magnetic Field Sensor with Digital Output
Background Capacitor-Current-Sensor Calibration of DC-DC Buck Converter with DVS for Accurately Accelerating Load-Transient Response
A 50GS/s Distributed T/H Amplifier in 0.18μm SiGe BiCMOS
A 40GS/s 6b ADC in 65nm CMOS
36.7 A 1.54pJ/b 64Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28nm CMOS
A 0.3ppm dual-resonance transformer-based drift-cancelling reference-free magnetic sensor for biosensing applications
A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique
7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array
12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS
A 0.45V 423nW 3.2MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms
A 32nm Westmere-EX Xeon ® enterprise processor
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC
A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control
28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power
Analog circuits: Stump the panel
A 0.18µm CMOS SoC for a 100m-range 10fps 200×96-pixel time-of-flight depth sensor
An 8.62μW 75dB-DRSoC End-to-End Spoken-Language-Understanding SoC With Channel-Level AGC and Temporal-Sparsity-Aware Streaming-Mode RNN
Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum)
Dual-band Single-Ended-Input Direct-Conversion DVB-H Receiver
F4: Emerging short-reach and high-density interconnect solutions for internet of everything
A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW Resonator
A frequency-shift CMOS magnetic biosensor array with single-bead sensitivity and no external magnet
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell