yusuke1997/dblp-id-title huggingface dataset:
Bring orders into uncertainty: enabling efficient uncertain graph processing via novel path sampling on multi-accelerator systems
TMModel: Modeling Texture Memory and Mobile GPU Performance to Accelerate DNN Computations
Zwift: A Programming Framework for High Performance Text Analytics on Compressed Data
An early prototype of an autonomic performance environment for exascale
A Hybrid Tensor-Expert-Data Parallelism Approach to Optimize Mixture-of-Experts Training
Author retrospective for optimizing for parallelism and data locality
Warp experience: we can map computations onto a parallel computer efficiently
Reducing energy consumption of NoC by router bypassing
Automatic Parallelization of Kernels in Shared-Memory Multi-GPU Nodes
Leveraging Silicon-Photonic NoC for Designing Scalable GPUs
A Wavefront Array Processor Using Dataflow Processing Elements
FAST: A Fast Stencil Autotuning Framework Based On An Optimal-solution Space Model
Proceedings of the International Conference on Supercomputing, ICS 2017, Chicago, IL, USA, June 14-16, 2017
Exploiting data parallelism in the yConvex hypergraph algorithm for image representation using GPGPUs
Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs
Accurate modelling of interconnection networks in vector supercomputers
AMPT-GA: automatic mixed precision floating point tuning for GPU applications
Prefetching on the Cray-T3E
Adaptive incremental checkpointing for massively parallel systems
Evaluation of Hardware Write Propagation Support for Next-generation Shared Virtual Memory Clusters
Power and energy efficient routing for Mach-Zehnder interferometer based photonic switches
NeurLZ: An Online Neural Learning-based Method to Enhance Scientific Lossy Compression
An evaluation of BitTorrent's performance in HPC environments
Half-Dynamic Scheduling with Data-flow Control
Global link arrangement for practical Dragonfly
Enhancing scalability of parallel structured AMR calculations
Wide and efficient trace prediction using the local trace predictor
Scalar Processor of the VPP500 Parallel Supercomputer
Data traffic reduction schemes for Cholesky factorization on asynchronous multiprocessor systems
MKPipe: a compiler framework for optimizing multi-kernel workloads in OpenCL for FPGA
A distributed system based on web services for computational science simulations
Parallel Additive Lagged Fibonacci Random Number Generators
An idiom-finding tool for increasing productivity of accelerators
Address-stride assisted approximate load value prediction in GPUs
Optimization of horizontal microcode generation for loop structures
OPMOS: Ordered Parallel Algorithm for Multi-Objective Shortest-Paths
Improving virtual function call target prediction via dependence-based pre-computation
DVPP: a VLSI dynamic-graph ensemble machine
Generating Microservice Graphs with Production Characteristics for Efficient Resource Scaling
Impact of self-scheduling order on performance on multiprocessor systems
Detection and Global Optimization of Reduction Operations for Distributed Parallel Machines
PFault: A General Framework for Analyzing the Reliability of High-Performance Parallel File Systems
Design and Performance of the Shasta Distributed Shared Memory Protocol
Givens elimination on systolic arrays
SAMS multi-layout memory: providing multiple views of data to boost SIMD performance
Verifying micro-architecture simulators using event traces
Tornado warning: the perils of selective replay in multithreaded processors
GCaR: Garbage Collection aware Cache Management with Improved Performance for Flash-based SSDs
Multi-GPU Communication Schemes for Iterative Solvers: When CPUs are Not in Charge
Last-level cache deduplication
Fast parallel in-memory 64-bit sorting
Adaptive Java optimisation using instance-based learning
Improving memory hierarchy performance for irregular applications
Vectorization beyond Data Dependences
Real-time High-resolution X-Ray Computed Tomography
Enhancing the performance of assisted execution runtime systems through hardware/software techniques
A compiler approach for reducing data cache energy
Online performance analysis by statistical sampling of microprocessor performance counters
Novel HPC techniques to batch execution of many variable size BLAS computations on GPUs
DALdex: A DPU-Accelerated Persistent Learned Index via Incremental Learning
Improving numerical accuracy for non-negative matrix multiplication on GPUs using recursive algorithms
Predicated Array Data-flow Analysis for Run-time Parallelization
Variation Among Processors Under Turbo Boost in HPC Systems
A Graph Based Approach to Barrier Synchronisation Minimisation
Dynamic Switching of Coherent Cache Protocols and its Effects on Doacross Loops
Parallel SAS multicluster algorithms for solving linear systems with reflexive coefficient matrices
Dynamic Load Balancing for the Simulation of Granular Materials
A Coordinated Strategy for GNN Combining Computational Graph and Operator Optimizations
Autonomous learning for efficient resource utilization of dynamic VM migration
A Comparative Study of Single Hop WDM Interconnections for Multiprocessors
Simplification and runtime resolution of data dependence constraints for loop transformations
A composite and scalable cache coherence protocol for large scale CMPs
clSpMV: A Cross-Platform OpenCL SpMV Framework on GPUs
FEM-TORUS: token driven processor torus array functional simulation and performance evaluation - for processing of finite-element-method matrices
Cancellation of loads that return zero using zero-value caches
Proceedings of the 2nd international conference on Supercomputing, ICS 1988, Saint Malo, France, July 4-8, 1988
Automatic load balanced paritioning strategies for PDE computations
I/O issues for hypercubes
An integrated environment for development and execution of real-time programs
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Partitioning the Statement per Iteration Space Using Non-Singular Matrices
Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling
Speculative Multithreaded Processors
HiRe: using hint & release to improve synchronization of speculative threads
BProc: the Beowulf distributed process space
Prediction-based power estimation and scheduling for CMPs
Design space exploration for multicore architectures: a power/performance/thermal view
Improving parallel system performance by changing the arrangement of the network links
A basic architecture supporting LGDG computation
Improving performance of openSHMEM reference library by portable PE mapping technique
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
Scheduling Sequential Loops on Parallel Processors
Input-adaptive parallel sparse fast fourier transform for stream processing
An experimental evaluation of tiling and shackling for memory hierarchy management
Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor
Fast phylogenetic analysis on a massively parallel machine
Lightweight lock-free synchronization methods for multithreading
Leveraging intra-page update diversity for mitigating write amplification in SSDs
Efficient thread/page/parallelism autotuning for NUMA systems
Author retrospective: compilation techniques for block-cyclic distributions
Communication and Control Costs of Domain Decomposition on Loosely Coupled Multiprocessors
Supercomputing with transputers - past, present and future
CUBA: an architecture for efficient CPU/co-processor data communication
Optimistic Delinearization of Parametrically Sized Arrays
Lifting C semantics for dataflow optimization
Peruse and Profit: Estimating the Accelerability of Loops
Approximate kernel matrix computation on GPUs forlarge scale learning applications
Unified memory optimizing architecture: memory subsystem control with a unified predictor
Fast loop-level data dependence profiling
Data and program restructuring of irregular applications for cache-coherent multiprocessor
Performance Analysis for a Join Processor
Vectorizing a robust inner product algorithm
Evaluating Virtual Channels for Cache-Coherent Shared-Memory Multiprocessors
A benchmark package for sparse matrix computations
CTADEL: A Generator of Multi-Platform High Performance Codes for PDE-Based Scientific Applications
An online quality management framework for approximate communication in network-on-chips
Evaluating on-die interconnects for a 4 TB/s router
Scheduling FFT computation on SMP and multicore systems
On the parallel solution of parabolic equations
Toward a Methodology of Optimizing Programs for High-Performance Computers
Characterizing processor architectures for programmable network interfaces
Next-generation generic programming and its application to sparse matrix computations
Automatic code generation for a turbulence scheme
Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors
A NUCA substrate for flexible CMP cache sharing
CuMAS: Data Transfer Aware Multi-Application Scheduling for Shared GPUs
Automatic generation of executable communication specifications from parallel applications
NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator
Estimating cache misses and locality using stack distances
Solving Elliptic Problems by the Domain Decomposition Method Using Proconditioning Matrices Derived by Multilevel Splitting of the Finite Element Matrix
Karma: scalable deterministic record-replay
Author retrospective improving data cache performance by pre-executing instructions under a cache miss
Globally homogeneous, locally adaptive sparse matrix-vector multiplication on the GPU
ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator
A performance portability framework for Python
Anatomy of High-Performance GEMM with Online Fault Tolerance on GPUs
PARADIGM: A Compiler for Automatic Data Distribution on Multicomputers
The trade-off between implicit and explicit data distribution in shared-memory programming paradigms
BVE: a wafer-scale engine for differential equation computation
Design of a novel SIMD architecture by fusing operations and registers
Author retrospective for PTRAN's analysis and optimization techniques
Advanced Loop Optimizations for Parallel Computers
Adaptive Migratory Scheme for Distributed Shared Memory
CLOVER: A GPU-native, Spatio-graph-based Approach to Exact kNN
SReplay: Deterministic Sub-Group Replay for One-Sided Communication
AMOEBA: a coarse grained reconfigurable architecture for dynamic GPU scaling
The auction: optimizing banks usage in Non-Uniform Cache Architectures
MBCF: A Protected and Virtualized High-Speed User-Level Memory-Based Communication Facility
The effectiveness of caches for vector processors
CMLCompiler: A Unified Compiler for Classical Machine Learning
UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique
Sculptor: Flexible Approximation with Selective Dynamic Loop Perforation
Are There Advantages to High-Dimension Architectures? Analysis of k -ary n -Cubes for the Class of Parallel Divide-and-Conquer Algorithms
A scalable framework for solving fractional diffusion equations
Compiler techniques for data synchronization in nested parallel loops
Fast branch misprediction recovery in out-of-order superscalar processors
The anatomy of efficient FFT and winograd convolutions on modern CPUs
Problem and Machine Sensitive Communication Optimization
Mower: A New Design for Non-blocking Misprediction Recovery
Distributed replay protocol for distributed uniprocessors
Avalon: towards QoS awareness and improved utilization through multi-resource management in datacenters
CTCCL: Cost-Efficient Joint Device-Network Load Balancing for LLM Training in RoCE-based Intelligent Computing Network
Constraint based vectorization
Runtime Coupling of Data-Parallel Programs
Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors
A network-failure-tolerant message-passing system for terascale clusters
TMA: a trap-based memory architecture
CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration
Profile-guided post-link stride prefetching
High performance MPI design using unreliable datagram for ultra-scale InfiniBand clusters
Enhancing Array Dataflow Dependence Analysis with On-demand Global Value Propagation
Architecture implications of high-speed I/O for distributed-memory computers
An Efficient Steepest-Edge Simplex Algorithm for SIMD Computers
Proceedings of the 29th ACM on International Conference on Supercomputing, ICS'15, Newport Beach/Irvine, CA, USA, June 08 - 11, 2015
Compiler Support for Hybrid Irregular Accesses on Multicomputers
A design of hybrid operating system for a parallel computer with multi-core and many-core processors
Bringing together automatic differentiation and OpenMP
A High Resolution Parallel Legendre Transform Algorithm
Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel Computer
Analyzing the Performance of Applications at Exascale
Optimizing Tensor Contractions in CCSD(T) for Efficient Execution on GPUs
Modeling and optimizing NUMA effects and prefetching with machine learning
A GSA-based compiler infrastructure to extract parallelism from complex loops
SnuHPL: high performance LINPACK for heterogeneous GPUs
Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations
BitWeaver: Read-Time Truncation in Memory
Conflict-free access of vectors with power-of-two strides
Cache oblivious parallelograms in iterative stencil computations
Distributed Data Structure Design for Scientific Computation
PELLPACK: a numerical simulation programming environment for parallel MIMD machines
User-guided symbiotic space-sharing of real workloads
Roar: A Router Microarchitecture for In-network Allreduce
Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003
High performance supercomputers: should the individual processor be more than a brick?
Compiler techniques for maximizing fine-grain and coarse-grain parallelism in loops with uniform dependences
Conflict-Free Template Access in k -ary and Binomial Trees
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Matrix-free SBP-SAT finite difference methods and the multigrid preconditioner on GPUs
Low-complexity reorder buffer architecture
PYRROS: static task scheduling and code generation for message passing multiprocessors
Datacenter Efficiency: What's Next?
Software combining to mitigate multithreaded MPI contention
Placement of I/O servers to improve parallel I/O performance on switch-based clusters
Using profiling to reduce branch misprediction costs on a dynamically scheduled processor
Challenges and opportunities in renewable energy and energy efficiency
Simulations of three-dimensional flows with the lattice Boltzmann equation on the IBM 3090/VF
G^3SA: A GPU-Accelerated Gold Standard Genomics Library for End-to-End Sequence Alignment
SortingHat: System Topology-aware Scheduling of Deep Neural Network Models on Multi-GPU Systems
Performance characteristics of the Cray X1 and their implications for application performance tuning
Influence of the stride on the cache utilization in the IBM 3090 VF
Incremental Performance Contributions of Hardware Concurrency Extraction Techniques
Parallel ODE solvers
A file I/O system for many-core based clusters
Exploring pattern-aware routing in generalized fat tree networks
A two-phase recovery mechanism
Optimizing for parallelism and data locality
Evaluation of processor code efficiency for embedded systems
Software-Hardware Co-design of Heterogeneous SmartNIC System for Recommendation Models Inference and Training
Acceleration of the outer conjugate gradient by reorthogonalization for a domain decomposition method for structural analysis problems
NUCAlloc: Fine-Grained Block Placement in Hashed Last-Level NUCA Caches
Markov model prediction of I/O requests for scientific applications
Ouroboros : virtualized queues for dynamic memory management on GPUs
Parameterized Diamond Tiling for Stencil Computations with Chapel parallel iterators
Computer generation of fast fourier transforms for the cell broadband engine
Synchronization optimizations for efficient execution on multi-cores
Counting Solutions to Linear and Nonlinear Constraints Through Ehrhart Polynomials: Applications to Analyze and Transform Scientific Programs
Imbalance optimization in scientific workflows
Chunking loops with non-uniform workloads
SnuSOLVER: Optimizing Sparse Direct Solvers for Heterogeneous Systems
Using complete system simulation to characterize SPECjvm98 benchmarks
Harnessing massive parallelism in the era of parallelism for the masses
Sparse-TPU: adapting systolic arrays for sparse matrices
Proceedings of the Future HPC Systems - the Challenges of Power-Constrained Performance, FutureHPC@ICS 2012, Venezia, Italy, June 25, 2012
Adaptive performance control for distributed scientific coupled models
Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies
Towards more efficient execution: a decoupled access-execute approach
Accelerating relax-ordered task-parallel workloads using multi-level dependency checking
Performance Analysis of Tree VLIW Architecture for Exploiting Branch ILP in Non-Numerical Code
Behavioral characterization of decoupled access/execute architecture
DSMR: A Parallel Algorithm for Single-Source Shortest Path Problem
Accelerator design for protein sequence HMM search
An approach to synchronization for parallel computing
Efficient management of memory hierarchies in embedded DRAM systems
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches
YH-Light: Yielding Hierarchy-aware Partitioner for Large-scale Graph Processing
High-performance regular expression scanning on the Cell/B.E. processor
Data Prefetching for Software DSMs
Towards Efficient SpMV on Sunway Manycore Architectures
MAD7: a memory architecture simulator targeted at design space exploration
Effective stream-based and execution-based data prefetching
Integrating superscalar processor components to implement register caching
Multiprocessor Scheduling with Client Resources to Improve the Response Time of WWW Applications
LAWS: locality-aware work-stealing for multi-socket multi-core architectures
Collective algorithms for sub-communicators
InterferenceRemoval : removing interference of disk access for MPI programs through data replication
A parallel execution environment for a sequential object oriented language
Cache performance for multimedia applications
Page table management in local/remote architectures
An integrated simdization framework using virtual vectors
Performance Improvement through Overhead Analysis: A Case Study in Molecular Dynamics
Performance study of a clustered shared-memory multiprocessor
Techniques for Reducing Overheads of Shared-Memory Multiprocessing
Designing algorithms on hierarchical memory multiprocessors
Enabling accurate power profiling of HPC applications on exascale systems
F 2 BFLY: an on-chip free-space optical network with wavelength-switching
Optimization and Parallelization of a Commodity Trade Model for the IBM SP1/2, using Parallel Programming Tools
CATS: cache aware task-stealing based on online profiling in multi-socket multi-core architectures
Hobbes: composition and virtualization as the foundations of an extreme-scale OS/R
Enhancing data cache reliability by the addition of a small fully-associative replication cache
A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation3
A cache coherence approach for large multiprocessor systems
Hardware-assisted scalable flow control of shared receive queue
Cherry: Breaking the GPU Memory Wall for Large-Scale GNN Training via Micro-Batching
A new "quad-tree-based" sub-system allocation technique for mesh-connected parallel machines
Symbolic Evaluation for Parallelizing Compilers
Integer Sorting on Shared-Memory Vector Parallel Computers
Data-driven fault tolerance for work stealing computations
PATCH - a new algorithm for rapid incremental dependence analysis
Galaxyfly: A Novel Family of Flexible-Radix Low-Diameter Topologies for Large-Scales Interconnection Networks
Workload decomposition for particle simulation applications on hierarchical distributed-shared memory parallel systems with integration of HPF and OpenMP
Unroll-based register coalescing
Implementation of Collective I/O in the Intel Paragon Parallel File System: Initial Experiences
Scheduling in parallel systems with a hierarchical organization of tasks
High throughput multidimensional tridiagonal system solvers on FPGAs
Non-Singular Data Transformations: Definition, Validity and Applications
Towards a Unified Implementation of GEMM in BLIS
Better than native: using virtualization to improve compute node performance
Reorganizing global schedules for register allocation
Parallel Multigrid Methods: Implementation on SUPRENUM-like Architectures and Applications
Optimizing Multi-grid Computation and Parallelization on Multi-cores
Routing and processor allocation on a Hypercycle-based multiprocessor
Compiler algorithms for event variable synchronization
Applications of storage mapping optimization to register promotion
MPI-aware compiler optimizations for improving communication-computation overlap
Impact of far-field interactions on performance of multipole-based preconditioners for sparse linear systems
GridRod: a dynamic runtime scheduler for grid workflows
Optimizing Attention by Exploiting Data Reuse on ARM Multi-core CPUs
Optimizing the datacenter for data-centric workloads
An interleaved cache clustered VLIW processor
Analytical cache models with applications to cache partitioning
Locality & utility co-optimization for practical capacity management of shared last level caches
On the complexity of list scheduling algorithms for distributed-memory systems
Vectorized molecular dynamics algorithms for very large number of particles
Control flow optimization for supercomputer scalar processing
CLAY: CXL-based Scalable NDP Architecture Accelerating Embedding Layers
A compiler framework for optimization of affine loop nests for gpgpus
Paralex: an environment for parallel programming in distributed systems
Array language support for parallel sparse computation
ProMT: optimizing integrity tree updates for write-intensive pages in secure NVMs
Collective operations in application-level fault-tolerant MPI
Leonid: Exploring Automated Kernel Fusion in Performance-Portable Programming Models for Scientific Computation
Automatic topology mapping of diverse large-scale parallel applications
A Proposal of Level 3 Interface for Band and Skyline Matrix Factorization Subroutine
Balanced Hashing and Efficient GPU Sparse General Matrix-Matrix Multiplication
Experimental Evaluation of Efficient Sparse Matrix Distributions
Parallel conjugate gradient algorithms for solving the Neutron Diffusion Equation on SUPERNUM
Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990
Hybrid MPI: a case study on the Xeon Phi platform
Long-term resource fairness: towards economic fairness on pay-as-you-use computing systems
Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures
Address-aware fences
Optimizing supercompilers for supercomputers
Characterization and Improvement of Load/Store Cache-based Prefetching
Hadoop+: Modeling and Evaluating the Heterogeneity for MapReduce Applications in Heterogeneous Clusters
High-throughput Bayesian network learning using heterogeneous multicore computers
DAWN: Matrix Operation-Optimized Algorithm for Shortest Paths Problem on Unweighted Graphs
Block Algorithms for Sparse Matrix Computations on High Performance Workstations
RFAcc: a 3D ReRAM associative array based random forest accelerator
A Multi-GPU Algorithm for Computing Maximal Independent Sets in Large Graphs
Clustered approaches to HPC via commodity HW + highly evolved SW
Performance considerations in software multicasts