yusuke1997/dblp-id-title huggingface dataset:
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format
Improving data cache performance using Persistence Selective Caching
Robust Passivity Analysis of Delayed Singular Systems Subject to Parametric Uncertainties
Design and analysis of full-chip HV ESD protection in BCD30V for mixed-signal ICs
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications
Image processing using approximate datapath units
A Scalable RDMA Network Interface Card with Efficient Cache Management
A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC
All-digital RF frequency modulation
Efficient scissoring scheme for scanline-based rendering of 2D vector graphics
Numerically stable fast sequential calculation for projection approximation subspace tracking
Proving the existence of periodic solutions using global interval Newton method
Hierarchical Statistical Verification of Large Full Custom CMOS Circuits
Mapping quantum algorithms to multi-core quantum computing architectures
A high-parallelism memory-based FFT processor with high SQNR and novel addressing scheme
ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications
Hardware-efficient filterbank design for fast recursive MDST and IMDST algorithms
Optimal single hop multiple bus networks
Pixel-Level Image Fusion Scheme based on Linear Algebra
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis
Decision making and perceptual bistability in spike-based neuromorphic VLSI systems
Near-ML Detection in Massive MIMO Systems with One-Bit ADCs: Algorithm and VLSI Design
A Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique
Robustness in binary cellular non-linear networks analog VLSI resonate-and-fire neuron
Random number generator architecture and VLSI implementation
Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA)
Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR
A biomimetic VLSI architecture for small target tracking
A Pulse Coded Winner-Take-All Circuit
HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture
A technique for designing self-checking logic for FPGAs
Energy harvesting ASIC for autonomous sensors
Variability-Aware Synthesis for Wideband Low Noise Amplifiers
Methodology of layout based schematic and its usage in efficient high performance CMOS design
Multiple outcomes of idealized switching
Screaming Channels Revisited: Encryption Key Recovery from AES-CCM Accelerator
An accurate and efficient estimation of switching noise in synchronous digital circuits
A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions
Normal Optical Flow measurement on a CMOS APS imager
5th order multi-tone Volterra simulator with component-level output
Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing
MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference
Integration of a wireless sensor network project for introductory circuits and systems teaching
A Review of CMOS Non-Foster Circuits
SALSE II: A Fast Transformational Scheduler for High-level Synthesis
Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods
Packet-loss robust scalable speech coding using the discrete wavelet transform
Neuromorphic Perception and Local Multimodal Haptic Feedback Based Immersive Teleoperation
Reduced Precision Redundancy Systems by Approximation (RPA): Design and Analysis
N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks
Suppression of harmonic spikes in asynchronous sigma delta modulation by randomizing hysteresis window
RF-link for cortical neuroprosthesis
Design of SRAM PUF with improved uniformity and reliability utilizing device aging effect
Integrating data converters for picoampere currents from electrochemical transducers
Virtual network embeddings in data center networks
A differential 5 th derivative Gaussian pulse generator for UWB transceivers
BDD-FTEST: Fast, Backtrack-Free Test Generator Based on Binary Decision Diagram Representation
A Pseudo-BiCMOS High Gain-Bandwidth Low Noise Operational Amplifier Using a Darlington Input Stage
A continuous-time level-crossing ADC with 1-bit DAC and 3-input comparator
A fast state-space algorithm to estimate harmonic distortion in fully differential weakly nonlinear G m -C filters
A 1 V, compact, current-mode neural spike detector with detection probability estimator in 65 nm CMOS
How to choose the ADC resolution for short range low power communication?
A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique
Enhanced gm3 cancellation for linearity improvement in CMOS LNAs
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders
Discrete Multitone Signalling for Wireline Communication
Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies
A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit
Improving the coding of regions of interest
A Novel Genetic Algorithm with Cell Crossover for Circuit Design Optimization
Hardware Accelerator Design for Healthcare Applications: Review and Perspectives
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration
On the Cross-terms in LPPs
Design of variable fractional delay allpass filter using weighted least squares method
A 900 mV 25µW high PSRR CMOS voltage reference dedicated to implantable micro-devices
Optimum noncoherent FM-DCSK detector: application of chaotic GML decision rule
A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC
Quality assessment of tone-mapped images based on sparse representation
A 1 st -Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration
Live Demonstration: AI-based System Latchup Detection and Protection for COTS Systems
A new rate allocation scheme for progressive fine granular scalable coding
A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases
Prunging via number of links and neuron activities
Architecture refinements by code refactoring of behavioral VHDL-AMS models
A convolutional neural architecture: an application for defects detection in continuous manufacturing systems
Variation-Aware Analog Circuit Sizing in Carbon Nanotube
Time-constrained packet scheduling optimization for video streaming in wireless ad-hoc networks
Gilbert Based Power Detector for 5G mm-Wave Transceivers Built-in-Self Test
A Field Programmable Analog Array using Floating Gates for High Resolution Tuning
FPGA technology mapping optimization by rewiring algorithms
A 1.5 V CMOS Current-Mode Cyclic Analog-to-Digital Converter with Digital Error Correction
A Set of Youla's Equivalent Constraints on Broadband Matching
Basic-Evolutive Algorithms for Neural Networks Architecture Configuration and Training
A Point Cloud-Based Non-Intrusive Approach for Human Posture Classification by Utilizing 77 GHz FMCW Radar and Deep Learning Models
A Study on Impact of Leakage Current on Dynamic Power
Event-based circuits for controlling stochastic learning with memristive devices in neuromorphic architectures
Design Considerations for DC-DC Voltage Regulators in Distributed Vertical Power Delivery Systems
Blind source extraction of instantaneous noisy mixtures using a linear predictor
Modeling of power distribution networks with signal lines for SPICE simulators
A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry
Sparse approximation using least squares support vector machines
PredictiveNet: An energy-efficient convolutional neural network via zero prediction
High resolution Frequency-based Delta-Sigma Modulator utilizing multi-phase quantizer
High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design
Low-complexity technique for secure storage and sharing of biomedical images
Subsystem size optimization for efficient parallel restoration of power systems
An event-driven ultra-low-current battery management system with reconfigurable linear regulator for multi-cell battery applications
Triple-Tail Common-Mode Insensitive High-Speed Dynamic Comparator for Analog In-Memory Computing Architectures
A variable control system for wireless body sensor network
ATM switch design using code division multiple access techniques
90Db, 90MHz, 30m W OTA with the Gain-Enhancement Implemented by One and Two Stage Amplifiers
Power-delay trade-offs in SCL gates
124dB.Hz 2/3 Dynamic range transimpedance amplifier for electronic-photonic channelizer
Cryo-CMOS Model-Enabled 8-Bit Current Steering DAC Design for Quantum Computing
A novel tracking-by-encoding scheme based on linear programming matching
A CMOS phase-locked loop with an auto-calibrated VCO
On partial synchronization of continuous and discrete-time coupled dynamical systems
Jordan Decomposition Filters
Common-Source Amplifier Based Analog Artificial Neural Network Classifier
Module placement based on quadratic programming and rectangle packing using less flexibility first principle
Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation
Innovative Engineering Education in Circuits & Systems
An improved wide-dynamic range tunable RF interference suppression notch filter
A high voltage battery charger with smooth charge mode transition in BCD process
Low complexity block-based unbiased frequency estimation
Switching methods for linear turbo equalization
An embedded processor based SOC test platform
Improving performance of high precision signal processing algorithms on programmable DSPs
OpenDPD: An Open-Source End-to-End Learning & Benchmarking Framework for Wideband Power Amplifier Modeling and Digital Pre-Distortion
An adaptive ISFET chemical imager chip
Structurally regular integer discrete cosine transform for low-bit-word-length coefficients
Mixed-mode parameter analysis of fully differential circuits
Adaptive Input-to-Neuron Interlink Development in Training of Spike-Based Liquid State Machines
ReBA: A Hybrid Sparse Reconfigurable Butterfly Accelerator for Solving Partial Differential Equations via Hardware and Algorithm Co-Design
A 5.8-GHz 4.8-mW -247.1dB-FoM DTC-free Sampling ∆Σ Fractional-N PLL with Embedded Phase Interpolation
A 10-MHz channel-select filter for a multicarrier WCDMA base-station
An Output-Capacitorless Low-Dropout Regulator with High Slew Rate and Unity-Gain Bandwidth
Location of Exons in DNA Sequences using Digital Filters
Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance
Innovations of Microcontroller Unit Based on Experiment
Double Magnetic Tunnel Junction-Based Nonvolatile Logic
A 1/3-Inch 1.12μm-Pitch 13Mpixel CMOS Image Sensor with a Low-Power Readout Architecture
Comparative analysis of robustness of spin transfer torque based look up tables under process variations
A 10 Gbps eye opening monitor in 65nm CMOS
An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits
Novel single-electron information-processing circuits mimicking behavior of ant groups
Miniature Electromagnetic Sensor Nodes for Wireless Surgical Navigation Systems
A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation
High performance 3D-FFT implementation
Low Power Circuit Techniques for Generating Kilovolt "Staircase" Waveforms
A 172.1dB-FoM 19.5kHz-BW DT ΔΣ ADC Using CLS-Assisted Fast Self-Quenching Floating Inverter Amplifier with Sampling Noise Cancellation
Low-noise low-power allpole active-RC filters minimizing resistor level
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories
A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding
Robust Pinning Synchronization of Complex Network with Non-linear Coupling using Switching Control
An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces
WR-3 Band Integrated Circuits in InP HBT Technology
A Fuzzy Mean Field Approach for Partitioning and Placement
A CMOS analog SiPM front-end for positron emission tomography application
Intermodulation distortion measures in a stochastic resonator
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking
A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme
A Pencil Balancing Robot using a Pair of AER Dynamic Vision Sensors
Gaussian chip shaping enhances the superiority of Markovian codes in DS/CDMA systems
Jitter analysis of general charge sampling amplifiers
A novel digitally controlled low noise ring oscillator
SMT-Based Placement for System-on-Chip Design
A low-power dual-rail inputs write method for bit-interleaved memory cells
The integer MDCT and its application in the MPEG layer III audio
A Ring-Oscillator-based Odometer to Unveil the Actual IC Usage Time
Termination of averaging networks in flash ADCs
A low-noise bandgap reference voltage source with curvature correction
IQ imbalance and phase noise mitigation for wireless OFDM systems
An image reconstruction system by neural network with median filter
High-resolution mismatch-shaping digital-to-analog converters
Neuro-sliding mode control for magnetic levitation systems
Frequency response masking FIR filters with short delay
A signal perturbation free semi-blind MRT MIMO channel estimation approach
A 1.6 GHz downconversion sampling mixer in CMOS
Using Noise-Feedback in Approximating ML Sequence Estimation for Channels with Infinite Intersymbol Interference
Statistical NBTI-effect prediction for ULSI circuits
Experimental results of a type-based predistorter for SSPA linearization
Design and Implementation of FPGA based System for Object Detection and Range Estimation used in ADAS Applications utilizing FMCW Radar
A Photoplethysmography Analog Front-End Model for Rapid Design of Personalized Healthcare Hardware
An efficient adaptive interlace-to-progressive scan conversion scheme and hardware implementation
A flexible transform processor architecture for multi-CODECs (JPEG, MPEG-2, 4 and H.264)
A family of floating-gate adapting synapses based upon transistor channel models
An Area Efficient and Inductorless Implementation of Continuous-Time Linear Equalization Scheme for High Speed and Low Noise TIA Designs
New structures for very high-frequency CMOS clock dividers
1.88 nA Quiescent Current Capacitor-Less LDO with Adaptive Biasing Based on a SSF Absolute Voltage Difference Meter
Stabilization of Fractional-Order Descriptor Time-Delay Systems
Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer
CMOS SRAM scaling limits under optimum stability constraints
Stack memory design for a low-cost instruction folding Java processor
3D monolithic integration
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems
Design of Cryo-CMOS Analog Circuits using the $G_{m}/I_{D}$ Approach
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis
An efficient representation of non-stationary signals using wavelets and mixed-transforms
Hardware synthesis with the Bach system
Parameter Mismatch Estimation in a Parallel Interleaved ADC
Memristive CNN for Wafer defect detection
Live demonstration: A multimodal adaptive wireless control interface for people with upper-body disabilities
Design considerations for band-pass sigma delta modulators
An Improved Exponentiated stochastic gradient algorithm
Fault equivalence and diagnostic test generation using ATPG
A novel methodology for the design of LC tank VCO with low phase noise
A codebook shaping method for perceptual quality improvement of CELP coders
On-chip high-speed solver of inverse problems based on quantum-computing principle
Proving asymptotic stability of equilibrium points of MOS transistor circuits
Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications
Automated dynamic cellular analysis in high throughput drug screens
Sampled-data modeling and analysis of one-cycle control and charge control
Consensus and synchronization of complex networks via proportional-integral coupling
Stereo matching by adaptive weighting selection based cost aggregation
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors
Motion-assisted rate control for ME/MC-based codecs [video coding]
Hybrid feature-based wallpaper visual search
Design of widely tunable Mexican hat wavelet filter for cardiac signal analysis
Linear current-mode ISFET arrays
A novel characterization of saddle-node bifurcation points for general nonlinear systems with decoupled parameters
An automated volumetric segmentation system combining multiscale and statistical reasoning
A Use Case of Iterative Logarithmic Floating-Point Multipliers: Accelerating Histogram Stretching on Programmable SoC
A Recurrent Neural Network for Solving the Shortest Path Problem
Power implications of precision limited arithmetic in floating point FIR filters
Macromodeling of digital libraries for substrate noise analysis
Blended engineering course - Electric Circuit Theory case study
Robust adaptive filtering via convex combination of l 0 -RLS adaptive filters
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers
PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
A novel high-speed and low-power negative voltage level shifter for low voltage applications
Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals
A SiGe 8-channel comparator for application in a synthetic aperture radiometer
New multiresolution motion estimation and compensation scheme
An ultra-low voltage RRAM read-out technique employing dithering principles
3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology
MG-Hybrid: A Strongly Connected Components Detection Algorithm using Multiple GPUs
Feature tracking linear optic flow sensor chip
A fast wake-up power gating technique with inducing a balanced rush current
Design of Robust Molecular Electronic Circuits
IPC-driven energy reduction for low-power design
Bulk-driven DC level shifter
A Hardwired Priority-Queue Scheduler for a Four-Core Java SoC
Low-power Multiplier Optimized by Partial-Product Summation and Adder Cells
Analog Acceleration of the Power Method using Memristor Crossbars
A closed loop transcutaneous power transfer system for implantable devices with enhanced stability
Spirograph on Oscilloscope: Laboratories in Series for EE101
Testable and self-repairable structured logic design
Deep modeling: Circuit characterization using theory based models in a data driven framework
Event-driven simulation and modeling of an RF oscillator
Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC
Fast and Scalable Memristive In-Memory Sorting with Column-Skipping Algorithm
Noise-flow-graph analysis of OTA-C filters
A sensor placement algorithm for redundant covering based on Riesz energy minimization
Headphone Amplifier and its Layout for Education for High School Student
From architecture to implementation of a wireless, multiple antenna testbed
Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures
A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna
Hardware implementation and comparison of new defuzzification techniques in fuzzy processors
Charge-based prediction circuits for focal plane image compression
Receiver echo cancellation with real-time self calibration for passive implanted neuron recorders
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter
CRISP: coarse-grain reconfigurable image signal processor for digital still cameras
Ternary Walsh transform
A 65.1 TOPS/W Digital CIM Processor for Ultra-Low-Bit Transformers with Multiplexer-based Adder and Scaling Factor-based Reordering
A design of 4-operand redundant binary parallel adder using neuron MOS
View direction and bandwidth adaptive 360 degree video streaming using a two-tier system
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Design and implementation of efficient Reed-Solomon decoders for multi-mode applications
A novel wavelet-based analog-to-digital converter
Ordinal Network Measures - Quantifying Determinism in Data
Synchronization in an array of chaotic systems coupled via a directed graph
Live demonstration: FPGA neural array emulation for real-time, event-based simultaneous dewarping and filtering for aerial vehicles
Design of sinusoid-based variable fractional delay FIR filter using weighted least squares method
Optimization of frequency filters via vertex graphs
Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement
A Silicon Retina for 2-D Position and 2-D Motion Computation
A low-power digital PWM DC/DC converter based on passive sigma-delta modulator
Adaptive configuration of cloud video transcoding
Frequency scaling of power reclamation networks in outphasing PA architectures
Video Segmentation with Model-Based Sprite Generation for Panning Surveillance Cameras
Retiming of Circuits Containing Multiplexers
An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications
Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy
Low power speech detector on a FPAA
A simplified lattice factorization for linear-phase paraunitary filter banks with pairwise mirror image frequency responses
A 160-GHz Power Amplifier with 32-dB Gain and 9.8% Peak PAE in 28-nm FD-SOI
Self-timed vertacolor dichromatic vision sensor for low power pattern detection
Non-Invasive Continuous Real-Time Blood Glucose Estimation Using PPG Features-based Convolutional Autoencoder with TinyML Implementation
Large-signal time-domain simulation of class-E amplifier
Design of a robust general-purpose low-offset comparator based on IGZO thin-film transistors
A robust approach to active queue management control in networks
Deep Learning with Augmented Kalman Filter for Single-Channel Speech Enhancement
Ultra-Low Power Wide-Dynamic-Range Universal Interface for Capacitive and Resistive Sensors
Graph-Grammar-Based Analog Circuit Topology Synthesis
Chaotic itinerancy phenomena on coupled n-double scrolls chaotic circuits
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme
Global asymptotic stability of a larger class of delayed neural networks
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC
Current conveyor with very low output impedance voltage buffer for laboratory instrumentation
A 23.5 TOPS/W Depthwise Separable Convolution Accelerator for Event-based Depth Estimation
Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin
Adaptive compensation of frequency response mismatches in high-resolution time-interleaved ADCs using a low-resolution ADC and a time-varying filter
Low-order modeling of head-related transfer functions using wavelet transforms
Features of memristor emulator-based artificial neural synapses
Models of Lava Flow Through the CNN-Based E^3 Architecture
MapLlama: A Two-Stage Approach for Map Question Answering Using a Fine-tuned Large Language Model
Multi-wavelets from spline super-functions with approximation order
A Low Power and Variable-length FFT Processor Design for Flexible MIMO OFDM Systems
A Low-Power Wireless Optical SoC for Fluorescence Monitoring
A high capacity distortion-free data hiding algorithm for palette image
Noise-Coupled Multi-Cell Delta-Sigma ADCs