yusuke1997/dblp-id-title huggingface dataset:
Deep Reinforcement Learning Based Dynamic Sub-Band Full Duplex for 5G-Advanced and 6G
On the Performance of DF Based Dual-Hop Mixed RF/UWOC System
The Fog Balancing: Load Distribution for Small Cell Cloud Computing
Research on Electromagnetic Effect Generated by DC Converter on Human Body in Electric Vehicle
Asymptotic Connectivity of Large-Scale Wireless Networks with a Log-Normal Shadowing Model
Multiuser Scheduling Based on Reduced Feedback Information in Cooperative Communications
Distance-Aware Overlay Routing with AODV in Large Scale Ad Hoc Networks
A Low Complexity Calibration Method for Space-Borne Phased Array Antennas
Performance of Maximal Ratio and Optimum Combining with Channel Estimation Errors and Multiple Interferers in Rayleigh Fading Channels
New Approach to Predict the Quality of Service of Vehicle- Based GPS System in Mobile Environment
Enabling ISAC in Industry 4.0: Challenges and Opportunities
Joint Carrier Synchronization and Equalizaiton Algorithm for OFDM Systems - Loop-Delay Analysis and Complexity Consideration
Proceedings of the 78th IEEE Vehicular Technology Conference, VTC Fall 2013, Las Vegas, NV, USA, September 2-5, 2013
Collaborative Anti-Jamming Broadcast with Uncoordinated Frequency Hopping over USRP
Rigid Body Localization and Environment Sensing with 5G Millimeter Wave MIMO
Graph Coloring-Based Interference Mitigation for Mega Constellations with Multi-Antenna Gateway Stations
On the Performance of Downlink Power-Based Scheduling for Slotted CDMA Networks
Hybrid Global/Local Search Algorithm for Optimization of Wireless Sensor Placement
Adaptive Selection Cooperation Scheme using Prediction-Based Decision in Ad-Hoc Networks
Demonstrator: V2V Communications in Automotive Multi-Sensor Multi-Target Tracking
Distributed Filter-And-Forward Beamforming for Two-Way Relaying Networks under Channel Uncertainties
Non-Colliding First Messages in Slotted ALOHA: Further Insights Toward a Practical Solution
Frequency-Domain Residual Interference Cancellation in Cyclic Prefix Assisted Single-carrier Communications
Beam Squint Effect in Multi-Beam mmWave Massive MIMO Systems
A PHY-Aided Secure IoT Healthcare System with Collaboration of Social Networks
A deterministic outdoor to indoor propagation modelling approach
Efficient Detection Technique for Multiple Packet Collisions in OFDM Systems
Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms
Taking into account indirect jumps or calls in continuous control-flow checking
5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010
Design and implementation of low latency network interface for network on chip
Vivado HLS-based implementation of a fall detection decision core on an FPGA platform
High performance MAC designs
Real-time hardware/software co-design of a traffic sign recognition system using Zynq FPGA
Reconfigurable low-power Concurrent Error Detection in logic circuits
Mapping SMV models to event-B models
FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem
Analysis and design of analog-based voltage controlled oscillator linearization technique
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization
On NOR-2 von Neumann multiplexing
Analog performance prediction based on archimedean copulas generation algorithm
Blurring prediction in monocular SLAM
4-D parity codes for soft error correction in aerospace applications
A study of the bends effects on a meandered dipole tag antenna
A bi-objective heuristic for heterogeneous MPSoC design space exploration
Silicon CMOS interdigitated-MSM photodetector and self-mixer for low-cost crash-avoidance Ladar system
A BIST method for TSVs pre-bond test
On modeling and optimizing cost in 3D Stacked-ICs
SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification
High level NoC modeling using discrete event simulation
Assertion based on-line fault detection applied on UHF RFID tag
A novel bio-inspired coding scheme for wireless sensor networks
Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation
An independent dual gate SOI FinFET soft-error resilient memory cell
Grammar-based program generation based on model finding
Design of DRFM system based on FPGA with high resources
A 0.4V 790μw CMOS low noise amplifier in sub-threshold region at 1.5GHz
Keynote 1: "Analysis of design parameters in safety-critical systems"
TSV-based 3D integration fabrication technologies: An overview
An improved electronic voting machine using a microcontroller and a smart card
Performance and functional test of flip-flops using ring oscillator structure
Modeling sequential circuits with shared structurally synthesized BDDs
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture
Traffic-based virtual channel activation for low-power NoC
Embedded FPGA accelerator for Wireless Sensor Network nodes
Accelerating the debugging of FV traces using K-means clustering techniques
Simulation and experimental verification: Dopant-free Si-nanowire CMOS technology on silicon-on-insulator material
Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologies
BTI analysis of SRAM write driver
Comparison of orthogonal and biorthogonal wavelets for multicarrier systems
Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failures
Chip-level programming of heterogeneous multiprocessors
SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications
On the design of a high-performance digital radar system
RF and non-linearity characterization of porous silicon layer for RF-ICs
Single-ended sense amplifier robustness evaluation for OxRRAM technology
Design, manufacturing & test of integrated circuits in the nanotechnology era
High speed special function unit for graphics processing unit
Efficient data management on 3D stacked memory for big data applications
A 0.9 V low power reconfigurable CMOS folded cascode LNA for multi-standard wireless applications
ZipStream: Improving dependability in dynamic partial reconfiguration
Body contact based TSV equalizer
A blocking probability study for the aethereal network-on-chip
Soft-core reduction methodology for SIMD architecture: OPENRISC case study
Verification of multi decisional reactive agent using SMV model checker
Pipelining the HEVC decoder on ZedBoard plateform
A UVM-based smart functional verification platform: Concepts, pros, cons, and opportunities
Hardware security and split fabrication
Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips
Area efficient implementation of ripple carry adder using memristor crossbar arrays
Fast oriented Anisotropic Diffusion filter
Liquid level monitoring using passive RFID tags
NOCBENCH: NOC synthesis benchmarks
Evaluation of the angle of arrival based techniques
Parasitic memory effect in CMOS SRAMs
Fault-Tolerant in Embedded Systems (MPSoC): Performance estimation and dynamic migration tasks
Improving timing characteristics through Semi-Random Net Reordering
On the impact of fault list partitioning in parallel implementations for dynamic test compaction considering multicore systems
Scalable high speed serial interface for data converters: Using the JESD204B industry standard
High speed low power composite field SBOX
Reaction-diffusion model for interface traps induced by BTS stress including H + , H and H2 as diffusion species
The effectiveness of delay and IDDT tests in detecting resistive open defects for nanometer CMOS adder circuits
An UHF RFID emulation platform with fault injection and real time monitoring capabilities
UML-based reconfigurable middleware for design-level timing verification in model-based approach
Characteristic impedance and propagation constant assessment of Substrate Integrated Waveguide transmission line
Design space exploration and synthesis for digital signal processing algorithms from Simulink models
8th International Design and Test Symposium, IDT 2013, Marrakesh, Morocco, 16-18 December, 2013
An evolutionary approach to reversible logic synthesis using output permutation
A low power low noise amplifier for 2.45GHz ISM receiver for Body Area Network
A flexible RNS-based large polynomial multiplier for Fully Homomorphic Encryption
ReverseAge: An online NBTI combating technique using time borrowing
Process-variation and temperature aware soc test scheduling using particle swarm optimization
Revolutionizing validation: The Intel approach for TTM
RSD based Karatsuba multiplier for ECC processors
NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation
FPGA implementation of the m-ary modular exponentiation
Performance evaluation of ZF and MMSE equalizers for wavelets V-Blast
A multi-scale analysis and compressive sensing based energy aware fall detection system
SimEvents based high level early design space exploration and modeling of a 3D Network on Chip
Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach
Keynote 1: "Merger mania"
Investigation of defect microstructures responsible for NBTI degradation using effective dipole moment extraction
Early reliability evaluation of a biomédical system
Testing of 3D IC with minimum power using genetic algorithm
Reduced dimension Vector Quantization encoding method for image compression
Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity
Non-volatile look-up table based FPGA implementations
Performance and bandwidth optimization for biological sequence alignment
SAT-based speedpath debugging using X traces
MBIST architecture framework based on orthogonal constructs
Bipolar OxRRAM memory array reliability evaluation based on fault injection
iJTAG integration of complex digital embedded instruments
RTL delay macro-modeling with Vt and Vdd variability
Resistive termination low noise amplifier for bio-sensor applications
Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG
Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems
Rebuilding synthesized design hierarchy based on instances path names of flattened netlist
Validation and robustness assessment of an automotive system
Day 2: Invited talk spintronic microsystems: Integrating analog devices with CMOS
Compilation optimization exploration for thermal dissipation reduction in embedded systems
A comparative study of various microstrip bandpass filters topologies for UWB applications
Energy efficient on-chip wireless interconnects with sleepy transceivers
Design tradeoffs for voltage controlled crystal oscillators with built-in calibration mechanisms
A novel wavelet-based method for TSV modeling
BDD based synthesis of Boolean functions using memristors
Facilitating side channel analysis by obfuscation for Hardware Trojan detection
High performance interpolation filter using direct computation
A novel conflict directed jumping algorithm for hardware-based SAT solvers
A survey of GF (2 m ) multipliers on FPGA
An efficient BER-based reliability method for SRAM-based FPGA
Memory profiling for intra-application data-communication quantification: A survey
Voltage island design in multi-core SIMD processors
Reliability analysis of CMOS inverter subjected to AC & DC NBTI stresses
Cost-free low-power test in compression-based reconfigurable scan designs
Low-voltage and low-power OTA using source-degeneration technique and its application in Gm-C filter
Obfuscated arbitrary computation using cryptographic primitives
Design constraints and challenges behind fault tolerance systems in a mobile application framework
Digital circuits verification with consideration of destabilizing factors
Multiple FPGAs based prototyping and debugging with complete design flow
11th International Design & Test Symposium, IDT 2016, Hammamet, Tunisia, December 18-20, 2016
Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck
ARM-based SoC for routing in Wireless Sensors Networks
Automatic test pattern generation for virtual hardware model using constrained symbolic execution
A 1.82-4.44 GHz reconfigurable bandpass filter based on tunable active inductor
Performances analysis of a coupled differential oscillators network using the contour graph approach
Transforming between logic locking and IC camouflaging
Nonvolatile memories: Present and future challenges
Multiband GNSS receiver design, simulation and experimental characterization
An automated design methodology for stress avoidance in analog & mixed signal designs
Through glass via thermomechanical analysis: Geometrical parameters effect on thermal stress
A novel approach for functional verification of memory protocol standard
Embedded adaptation for 3D face analysis using Elastic Riemannian algorithm
Enhanced performances of paper-based Substrate Integrated waveguide (SIW) antenna for Wireless Sensor Network applications
A co-design space exploration tool for avionic high performance heterogeneous embedded architectures
Design of discret time feed-forward cascaded ΔΣ modulator for wireless communication systems
Band-limited 2D Cartesian behavioral modeling of concurrent dual-band RF transmitters
Industrial approaches for performance evaluation using on-chip monitors
6th IEEE International Design and Test Workshop, IDT 2011, Beirut, Lebanon, 11-14 December 2011
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs
NOC synthesis vs ITRS predictions: The challenges of linear programming based synthesis
Challenges in serial protocols Verification on an emulation environment (SATA as an example)
Efficient FPGA implementation of H.264 CAVLC entropy decoder
A design for reliability methodology based on selective overdesign
SystemC TLM2-protocol consistency checker using Petri net
Modeling of silicon MEMS capacitive pressure sensor for biomédical applications
Stepwise SystemC/TLM-2 models structuring and optimizations
Design for security test on cryptographic ICs for design-time security evaluation
A 5-bit 1.5 GS/s ADC using reduced comparator architecture
Universal fused floating-point dot-product unit (UFDP)
9th International Design and Test Symposium, IDT 2014, Algeries, Algeria, December 16-18, 2014
Petri Net Diagnosability Analyzer
Transparent testing for intra-word memory faults
Tutorial 2: "Challenges of FPGA-based prototyping & debugging"
Design and implementation of Wishbone bridge for an iSLIP based NoC
Opportunistic redundancy for improving reliability of embedded processors
Low-cost EVM built-in test of RF transceivers
Macro model analysis of a single mass 6-DOF Inertial Measurement Unit system
Memristor for energy efficient wireless sensor node
Multiprocessor architecture for an optimazed parallel model of covariance based person detection
An electrical-aware parametric DFM solution for analog circuits
Accurate and efficient identification of worst-case execution time for multicore processors: A survey
Keynote 3: "Ensuring robustness in today's IoT era"
A 10 Gbps ADC-based equalizer for serial I/O receiver
Keynote 2: "Embedded systems design for critical applications"
A proposed methodology for designing reconfigurable solutions
Energy-efficient truncated multipliers with scaling
A narrative of UVM testbench environment for interconnection routers: A practical approach
Guiding intelligent testbench automation using data mining and formal methods
Yield enhancement flow for analog and full custom designs reliability-rules automatic application
High throughput asynchronous NoC switch for high process variation
Enhanced bit-width optimization for linear circuits with feedbacks
Experimental evaluation of latency coding for gas recognition
Keynote 4: "Embedded platforms for next-generation autonomous driving systems"
Test set embedding into accumulator-generated sequences targeting hard-to-detect faults
Day 1: Invited talk 2: Dependable mixed-signal integrated systems under aging
NOC based MPSOC directory based cache coherency with OCP-IP protocol
SAT-based ATPG for reversible circuits
Using IoT in breakdown tolerance: PSO solving FJSP
Reliability degradation in the scope of aging - From physical to system level
A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs
A simple digital detection scheme for demodulating QPSK signals in super-regenerative receiver architecture
Improved multi-antenna system capacity using beamformer weights
Stress-aware analog layout devices pattern generation
A survey on security of IoT in the context of eHealth and clouds
Regression modeling for subset selection in rare-event statistical circuit simulation
Translating of MATLAB/SIMULINLK model to synchronous dataflow graph for parallelism analysis and programming embedded multicore systems
Resource reservation technique for handover calls using integrated modeling technique
A TSV-based architecture for AC-DC converters
Day 1 keynote: EDA's key to success: Riding waves of innovation
Fault tolerance on multicore processors using deterministic multithreading
Keynote 3: "Microelectronic systems for improved quality of life"
Impact analysis of resistive bridge within deep submicron Secured CMOS circuits
A proposed methodology to improve UVM-based test generation and coverage closure
Design guidelines for soft implementations to embedded NoCs of FPGAs
Routability driven placement for mesh-based FPGA architecture
Performance comparison between air-gap based coaxial TSV and conventional circular TSV in 3D-ICs
Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann"
An efficient hardware architecture of intra prediction in HEVC standard
A lighting independent vision based system for driver assistance
Multiple fault testing in systems-on-chip with high-level decision diagrams
SoC verification platforms using HW emulation and co-modeling Testbench technologies
Accurate analog/RF BIST evaluation based on SVM classification of the process parameters
WaferCatalyst - Towards promotion of IC design in the middle east using virtual community approach
NVMe Solid State Drive verification solution using HW Emulation and Virtual Device Technologies
High throughput parallel montgomery modular exponentiation on FPGA
Day 2: Mini-tutorial: Challenges to the design and optimization of cyber-physical systems
A new efficient reduction scheme to implement tree multipliers on FPGAs
A method of LFSR seed generation for hierarchical BIST
Rapid prototyping of PVS into FPGA: From model based design to FPGA/ASICs implementation
An L, S and S2 bands, compliant LC-based DCO for amateur Nano-satellite applications
Multi-device layout templates for nanometer analog design
Automated flow for generating CMOS custom memory bit map between logical and physical implementation
Reconfigurable test platform for modular embedded systems in manufacturing processes
Automated formal verification of X propagation with respect to testability issues
Failure and root cause analysis for a system-on-chip: An industrial case study
ZnO based gas sensor testing
On the evaluation of soft-errors detection techniques for GPGPUs
Tutorial 1: "New approaches towards early dependability evaluation of digital integrated systems"
Aging and leakage tradeoff in VLSI circuits
Systolic architecture for hardware implementation of two-dimensional non-separable filter-bank
An area-efficient 2-D convolution implementation on FPGA for space applications
Exploring test opportunities for memory and interconnects in 3D ICs
Day 1: Invited talk 1: IC qualification, testing & manufacturing using advanced package offerings & adequate process technologies
A new binary arithmetic for finite-word-length linear controllers: MEMS applications
Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm
A Python-based layout-aware analog design methodology for nanometric technologies
Formal verification of AUTOSAR FlexRay state manager
Design of high-performance CMOS tunable active inductor
Performance of different wavelet families using DWT and DWPT-channel equalization using ZF and MMSE
High radix montgomery modular multiplication on FPGA
Power constraints test scheduling of 3D stacked ICs
Enabling difference-based dynamic partial self reconfiguration for large differences
Indoor localization using received signal strength
Day 2 keynote: IoT fosters semiconductor innovation
Verifying generic IEC 61508 CPU self-tests with fault injection
Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture
Heterogeneous multi-core architecture for a 4G communication in high-speed railway
An automatic ECG generator for testing and evaluating ECG sensor algorithms
BTI impact on SRAM sense amplifier
Novel Adaptive Virtual Channels technique for NoC switch
10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015
Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters
Memory controller architectures: A comparative study
Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions
Analytical approach of the impact of through silicon via on the performance of MOS devices
A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems
Timed-SDF patterns for applications throughput analysis
Architectural support for runtime verification on ccNUMA multiprocessors
A high radix montgomery multiplier with concurrent error detection
Fault detection and diagnoses methodology for adaptive digitally-calibrated pipelined ADCs
Modulo 2 n +1 addition and multiplication for redundant operands
Validation & Verification of an EDA automated synthesis tool
Computational complexity in test-generation algorithms
RF filter characterization using a chirp
The optimum Booth radix for low power integer multipliers
Design of tunable continuous-time quadrature bandpass delta-sigma modulators
Human action recognition using RGB data
Efficient embedded SoC hardware/software codesign using virtual platform
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition
Welcome to the IDT 2016
Sobel edge detection system design and integration on an FPGA based HD video streaming architecture
Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM
Toward the interfacing of systemC-AMS models with hardware-emulated platforms
Exploiting satisfiability modulo theories for analog layout automation
Integration of STT-MRAM model into CACTI simulator
SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST
Reliability assessment of backward error recovery for SRAM-based FPGAs
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors
Design of a low power Variable Gain Amplifier for WLAN standard
A low propagation delay dispersion comparator for low cost level-crossing ADCs
ECC design for fault-tolerant crossbar memories: A case study
Fostering Sociability in Learning Networks through Ad-Hoc Transient Communities
Inter-organisational Knowledge Transfer and Computer Mediated Social Networking
Computer-Mediated Social Networking for Mentoring of Health Professionals
SME Knowledge Transfer through Social Networking: Leveraging Storytelling for Improved Communication
A Review of Linden Scripting Language and Its Role in Second Life
The Use of Digital Photo Frames as Situated Messaging Appliances
Self-organization in Simulated Social Networks
Towards the Integration of Social Media with Traditional Information Systems
Designing Physical and Virtual Communities
A Social Networking Approach to F/OSS Quality Assessment