yusuke1997/dblp-id-title huggingface dataset:
FPgen - a test generation framework for datapath floating-point verification
Automated debugging with high level abstraction and refinement
An RT-level fault model with high gate level correlation
Formal operator testability methods for behavioral-level DFT using value ranges
Validating families of latency insensitive protocols
Design-for-debug for post-silicon validation: Can high-level descriptions help?
Semi-Formal Verification at IBM
Symbolic simulation techniques-state-of-the-art and applications
Formal verification of the Pentium (R) 4 multiplier
Generating formal system models from natural language descriptions
A method for hunting bugs that occur due to system conflicts
PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis
RTL DFT techniques to enhance defect coverage for functional test sequences
Proving sequential consistency by model checking
Automatic generation of functional coverage models from CTL
Verifying LOC based functional and performance constraints
Mutation-based validation of high-level microprocessor implementations
Functional verification of an embedded network component by co-simulation with a real network
AME: an abstract middleware environment for validating networked embedded systems applications
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model
Test quality for high level structural test
A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip
Error Detection Using Model Checking vs. Simulation
Post-silicon verification and debugging with control flow traces and patchable hardware
FFT Compiler: from math to efficient hardware HLDVT invited short paper
Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies
Functional verification based on the EFSM model
Validating the dependability of embedded systems through fault injection by means of loadable kernel modules
ATPG-based preimage computation: efficient search space pruning with ZBDD
On-chip stimuli generation for post-silicon validation
Panel: Functional coverage - is your design exposed?
TG-PRO: A new model for SAT-based ATPG
Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis
Accelerating assertion assessment using GPUs
Testing ThumbPod: Softcore bugs are hard to find
An approach to high-level synthesis system validation using formally verified transformations
Practical use of sequential ATPG for model checking: going the extra mile does pay off
An approach for computing the initial state for retimed synchronous sequential circuits
Taming the Complexity of STE-based Design Verification Using Program Slicing
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs
Hardware-software covalidation: fault models and test generation
Data flow based cache prediction using local simulation
A functional test generation technique for RTL datapaths
ESL design and multi-core validation using the System-on-Chip Environment
A novel formal approach to generate high-level test vectors without ILP and SAT solvers
Fast and accurate UML State Chart modeling using TLM + control flow abstraction
Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002
Mathematical framework for representing discrete functions as word-level polynomials
Repair techniques for aged TSVs in 3D integrated circuits
Coverage discounting: A generalized approach for testbench qualification
A randomized algorithm for constructing cross-feature tests from single feature tests
A novel SAT-based ATPG approach for transition delay faults
Security evaluation against electromagnetic analysis at design time
Embedded system verification through constraint-based scheduling
Advanced analysis techniques for cross-product coverage
Dynamic analysis of constraint-variable dependencies to guide SAT diagnosis
Analysis of scheduled Latency insensitive systems with periodic clock calculus
MODD for CF: a representation for fast evaluation of multiple-output functions
Constructing reusable testbenches
Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams
Using Aspect-GAMMA in the design of embedded systems
Simulation strategy after model checking: experience in industrial SOC design
Functional coverage measurements and results in post-Silicon validation of Core™2 duo family
Software agnostic approaches to explore pre-silicon system performance
A new method for on-line state machine observation for embedded microprocessors
On the Automatic Transactor Generation for TLM-based Design Flows
Formal analysis and validation of continuous-time Markov chain based system level power management strategies
A proof of correctness for the construction of property monitors
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000
Addressing Test Generation Challenges for Configurable Processor Verification
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)
Formal verification guided automatic design error diagnosis and correction of complex processors
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams
MVP: a mutation-based validation paradigm
An optimum algorithm for compacting error traces for efficient functional debugging
CNF formula simplification using implication reasoning
Compilation-based software performance estimation for system level design
Instruction level test methodology for CPU core software-based self-testing
Control-flow guided clause generation for property directed reachability
Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality
Refactoring digital hardware designs with assertion libraries
RTL functional verification using excitation and observation coverage
Redundant functional faults reduction by saboteurs synthesis [logic verification]
DVGen: Increasing Coverage by Automatically Combining Test Specifications
Interactive presentation abstract: Reusing of properties after discretization of hybrid automata
RTL level trace signal selection and coverage estimation during post-silicon validation
An equivalence checking methodology for hardware oriented C-based specifications
Towards RTL test generation from SystemC TLM specifications
Model-driven test generation for system level validation
Eliminating race conditions in system-level models by using parallel simulation infrastructure
A model checking approach to evaluating system level dynamic power management policies for embedded systems
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip
Towards an efficient assertion based verification of SystemC designs
Emulation in post-silicon validation: It's not just for functionality anymore
An improvement in decomposed reachability analysis for symbolic model checking
Taylor expansion diagrams: a new representation for RTL verification
Applications of decorator and observer design patterns in functional verification
High-level and hierarchical test sequence generation
Multi-level Bounded Model Checking to detect bugs beyond the bound
A software test program generator for verifying system-on-chips
On Chip Instrument application to SoC analysis
Positioning test-benches and test-programs in interaction-oriented system-on-chip verification
In-system silicon validation using a reconfigurable platform
A flexible modeling environment for a NoC-based multicore architecture
A formal method to improve SystemVerilog functional coverage
DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms
Automatic test generation for micro-architectural verification of configurable microprocessor cores with user extensions
A coordinated reachability analysis method for modular verification of asynchronous designs
Proving and disproving assertion rewrite rules with automated theorem provers
Constrained signal selection for post-silicon validation
Specification Language for Transaction Level Assertions
Runtime Deadlock Analysis of SystemC Designs
Effects of property ordering in an incremental formal modeling methodology
Verification of a DSP IP cores by model checking
On identifying functionally untestable transition faults
Reusable On-Chip System Level Verification for Simulation Emulation and Silicon
Activity-based refinement for abstraction-guided simulation
Modular arithmetic decision procedure with auto-correction mechanism
Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility
UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design
High level validation of next-generation microprocessors
Checking temporal properties in SystemC specifications
Establishing latch correspondence for embedded circuits of PowerPC microprocessors
IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Santa Cruz, CA, USA, October 7-8, 2016
Accelerating SystemC simulations using GPUs
Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study
Behavioral-level test vector generation for system-on-chip designs
Software-based self-test methodology for crosstalk faults in processors
Code simulation concept for S/390 processors using an emulation system
Post-silicon verification methodology on Sun's UItraSPARC T2
SAT-based techniques for determining backbones for post-silicon fault localisation
Towards scalable utilization of embedded manycores in throughput-sensitive applications
A symbolic execution framework for algorithm-level modelling
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description
Experimental validation of fault detection and fault tolerance mechanisms
A comparison of BDDs, BMC, and sequential SAT for model checking
Enhancing the control and efficiency of the covering process [logic verification]
Dynamic verification of Multicore Communication applications in MCAPI
The relationship of code coverage metrics on high-level and RTL code
Monitoring distributed reactive systems
B-cubing theory: new possibilities for efficient SAT-solving
Checking temporal properties under simulation of executable system descriptions
High-level modeling and verification of cellular signaling
Utility of transaction-level hardware models in refinement checking
2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011
Trends in Test: Challenges and Techniques
Enhancing sequential depth computation with a branch-and-bound algorithm
Nano, quantum, and molecular computing: are we ready for the validation and test challenges?
Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30 - December 2, 2005
Improvement of fault injection techniques based on VHDL code modification
Test generation for hardware-software covalidation using non-linear programming
IP-XACT based system level mutation testing
Automated synthesis of EDACs for FLASH memories with user-selectable correction capability
GASIM: a fast Galois field based simulator for functional model
Enhancing SAT-based equivalence checking with static logic implications
Modular equivalence verification of polynomial datapaths with multiple word-length operands
Assertion-based Verification of Behavioral Descriptions with Non-linear Solver
DFT and Probabilistic Testability Analysis at RTL
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques
Extracting a simplified view of design functionality via vector simulation
Transactors for parallel hardware and software co-design
Formal modeling of biological systems
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model
Interface based hardware/software validation of a system-on-chip
Polychronous Methodology For System Design: A True Concurrency Approach
Formal semantics of behavior specifications in the architecture analysis and design language standard
Cardio: Adaptive CMPs for reliability through dynamic introspective operation
Breaking an application specific instruction-set processor: the first step towards embedded software testing
A unifying flow to ease smart systems integration
Piparazzi: a test program generator for micro-architecture flow verification
Automatic TLM generation for C-Based MPSoC design
Deciphering cancer biology using boolean methods
Variable ordering for taylor expansion diagrams
Variable size analysis and validation of computation quality
Hardware-in-the-loop model-less diagnostic test generation
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL
IEEE International High Level Design Validation and Test Workshop, HLDVT 2007, Irvine, CA, USA, November 7-9, 2007
Sequential equivalence checking based on k-th invariants and circuit SAT solving
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001
Assertion-based power/performance analysis of network processor architectures
Automatically adjusting system level designs after RTL/gate-level ECO
Framework for fast and accurate performance simulation of multiprocessor systems
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks
On choosing test criteria for behavioral level hardware design verification
HES machine: Harmonic equivalent state machine modeling for cyber-physical systems
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions
High level hardware validation using hierarchical message sequence charts
Hardware Trojan: Threats and emerging solutions
The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems
HIFSuite: Tools for HDL code conversion and manipulation
Improving test quality through resource reallocation
High-level modeling for computer-aided clinical trials of medical devices
Hierarchical cache coherence protocol verification one level at a time through assume guarantee
Formal verification of high-level conformance with symbolic simulation
Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification
Using decision diagrams to compactly represent the state space for explicit model checking
An ontology and constraint based approach to cache preloading
Design centric modeling of digital hardware
Clock domain crossing formal verification: a meta-model
IBM system z functional and performance verification using X-Gen
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties
Adaptive test program generation: planning for the unplanned
Functional testing approaches for "BIFST-able" tlm_fifo
On dynamic switching of navigation for semi-formal design validation
Challenges in post-silicon verification of IBM's Cell/B.E. and other game processors
A simple and effective compression scheme for test pins reduction
Brain-computer interface using P300: a gaming approach for neurocognitive impairment diagnosis
Practical experiences in functional simulation. An integrated method from unit to co-simulation
Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs
Automatic generation of host-compiled timed TLMs for high level design
IEEE International High Level Design Validation and Test Workshop, HLDVT 2009, San Francisco, CA, USA, 4-6 November 2009
Test slice difference technique for low power encoding
A new simulation-based property checking algorithm based on partitioned alternative search space traversal
Timing verification of distributed network systems at higher levels of abstraction
Refining abstract equivalence analysis for embedded system design
Dynamic service synthesis and switching for medical IoT and ambient assisted living
Semi-formal functional verification by EFSM traversing via NuSMV
Cross-layer resilience: are high-level techniques always better?
Analog transaction level modeling
On using a 2-domain partitioned OBDD data structure in verification
Bridging RTL and gate: correlating different levels of abstraction for design debugging
Test and validation of a non-deterministic system - True Random Number Generator
Automatic functional test program generation for pipelined processors using model checking
High-level design verification using Taylor Expansion Diagrams: first results
Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators
Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking
Setting break-points in distributed time-triggered architecture
A language formalism for verification of PowerPC TM custom memories using compositions of abstract specifications
Towards analyzing functional coverage in SystemC TLM property checking
Efficient test-based model generation for legacy reactive systems
Combining complex event models and timing constraints
An enhanced cut-points algorithm in formal equivalence verification
Reliable network-on-chip based on generalized de Bruijn graph
IFRA: Post-silicon bug localization in processors
Dynamic guiding of bounded property checking
Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces
Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, Monterey, CA, USA, Nov 9-10, 2006
Using haloes in mixed-signal assertion based verification
A method for generation of GSTE assertion graphs
Design space exploration for deterministic ethernet-based architecture of automotive systems
An effective and flexible approach to functional verification of processor families
Slightly-off-specification failures in the time-triggered architecture
Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations
Experience with widening based equivalence checking in realistic multimedia systems
Panel: What's the next 'big thing' in simulation-based verification?
Taking the best out of two worlds: prototyping and hardware emulation
Verification of real-time properties for Hardware-dependent Software
An event-based network-on-chip monitoring service
An approach to functional testing of VLIW architectures
Panel: SoC power management implications on validation and testing
Airwolf-TG: A test generator for assertion-based dynamic verification
IEEE International High Level Design Validation and Test Workshop, HLDVT 2008, Incline Village, NV, USA, November 19-21, 2008
VHDL-based simulation environment for Proteo NoC
Formal verification of embedded system designs at multiple levels of abstraction
2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017, Santa Cruz, CA, USA, October 5-6, 2017
Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication
Probabilistic reachability analysis of the tap withdrawal circuit in caenorhabditis elegans
Designing cyber-physical systems from natural language descriptions
Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks
Clock domain verification challenges and scalable solutions
On code coverage measurement for Verilog-A
Formal meaning of coverage metrics in simulation-based hardware design verification
Simplifying design and verification for structural hazards and datapaths in pipelined circuits
Harnessing machine learning to improve the success rate of stimuli generation
Automating the IEEE std.1500 compliance verification for embedded cores
MCBCG: Model Checking Based Sequential Clock-Gating
EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation
FLARE: A design environment for FLASH-based space applications
Integrating CNF and BDD based SAT solvers
Automatic error diagnosis and correction for RTL designs
Coverage metrics for verification of concurrent SystemC designs using mutation testing
Reuse in system-level stimuli-generation
Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits
Reference model based RTL verification: an integrated approach
DVGen: a test generator for the transmeta Efficeon VLIW processor
Leadership Microprocessors: Validation, debug and test
System level simulation guided approach to improve the efficacy of clock-gating
Functional vector generation for assertion-based verification at behavioral level using interval analysis
Verification of in-order execution in pipelined processors
A 1000X speed up for properties completeness evaluation
BDD-based verification of scalable designs
Cosimulation of ITRON-based embedded software with SystemC
Hardware/software co-debugging for reconfigurable computing
STAR: Generating input vectors for design validation by static analysis of RTL
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
Overlap reduction in symbolic system traversal
Integrating Perl, Tcl and C++ into simulation-based ASIC verification environments
Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats
Simulation-based functional test generation for embedded processors
Intel's Post Silicon functional validation approach
Formal model construction using HDL simulation semantics
Automatic functional verification of memory oriented global source code transformations
On statistical behavior of branch coverage in testing behavioral VHDL models
Enhancing the efficiency of Bayesian network based coverage directed test generation
Eighth IEEE International High-Level Design Validation and Test Workshop 2003, San Francisco, CA, USA, November 12-14, 2003
Transaction Routing and its Verification by Correct Model Transformations
Panel: Software practices for verification/testbench management
Using cutwidth to improve symbolic simulation and Boolean satisfiability
Causality analysis of synchronous programs with refined clocks
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators
Model reduction techniques for the formal verification of hardware dependent software
Automatic validation of pipeline specifications
ESL flows are enabled by high-level synthesis with universality
On generation of properties from specification
Prototyping of embedded digital systems from SDL language: a case study
MMV: Metamodeling Based Microprocessor Valiation Environment
Automated clock inference for stream function-based system level specifications
Modeling, synthesis, and validation of heterogeneous biomedical embedded systems
Temporal parallel gate-level timing simulation
Validation of HMI applications for industrial smart display
Sufficiency-based filtering of invariants for Sequential Equivalence Checking
X-Gen: a random test-case generator for systems and SoCs
Top-level validation of system-on-chip in Esterel Studio
Optimized coverage-directed random simulation
Distance-Guided Hybrid Verification with GUIDO
Specification by existing design plus use-cases
On equivalence checking between behavioral and RTL descriptions
Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics
Relating vehicle-level and network-level reliability through high-level fault injection
Panel: Driving the intelligent testbanch: are we there yet?
VERISEC: verifying equivalence of sequential circuits using SAT
Exploiting hypergraph partitioning for efficient Boolean satisfiability
Word-level traversal of finite state machines using algebraic geometry
ATPG based functional test for data paths: application to a floating point unit
3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs
Formal Verifications in Modern Chip Designs