yusuke1997/dblp-id-title huggingface dataset:
HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications
An optimal gate design for the synthesis of ternary logic circuits
Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs
Low power discrete voltage assignment under clock skew scheduling
A fast two-pass HDL simulation with on-demand dump
Physical verification flow for hierarchical analog ic design constraints
FastPass: Fast timing path search for generalized timing exception handling
Opportunities with the open architecture test system
Fast Electrical Correction Using Resizing and Buffering
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs
Standard CMOS technology on-chip inductors with pn junctions substrate isolation
High speed bit-serial parallel processing on array architecture
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures
Contact pitch and location prediction for Directed Self-Assembly template verification
Chain-based pin count minimization for general-purpose digital microfluidic biochips
Optimal planning for mesh-based power distribution
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder
Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory
A path-based timing-driven quadratic placement algorithm
Energy minimization of real-time tasks on variable voltage processors with transition energy overhead
Learning-based prediction of package power delivery network quality
Applications of adaptive computing systems for signal processing challenges
PathGen: An Efficient Parallel Critical Path Generation Algorithm
Risk aversion min-period retiming under process variations
Multithreaded SAT Solving
OCV guided clock tree topology reconstruction
Low-power design of sequential circuits using a quasi-synchronous derived clock
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V V DD applications
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control
Power optimization of wireless video sensor nodes in M2M networks
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
Register allocation for common subexpressions in DSP data paths
A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop
TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
Analog placement with common centroid and 1-D symmetry constraints
Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems
Heterogeneous memory management for 3D-DRAM and external DRAM with QoS
MULTI-PRIDE: a system for supporting multi-layered printed wiring board design
An MILP-based wire spreading algorithm for PSM-aware layout modification
Generation of shorter sequences for high resolution error diagnosis using sequential SAT
A polynomial-time custom instruction identification algorithm based on dynamic programming
EDIF version 350/400 and information modeling
A channel-sharable built-in self-test scheme for multi-channel DRAMs
XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools
BOB-router: A new buffering-aware global router with over-the-block routing resources optimization
Efficient Preparation of Cyclic Quantum States
Application-specific 3D Network-on-Chip design using simulated allocation
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization
Reliability assessment of safety-relevant automotive systems in a model-based design flow
Design considerations and clinical applications of closed-loop neural disorder control SoCs
Accurate and Efficient Simulation of Microfluidic Networks
Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery
Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources
Quantitative Selection of Media Benchmarks
Fast and efficient voltage scheduling by evolutionary slack distribution
Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs
Static power minimization in current-mode circuits
A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NR
Thermal management for dependable on-chip systems
A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs
A real-time high performance edge detector for computer vision applications
Supporting sequential assumptions in hybrid verification
All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units
VCore-based platform for SoC design
Non-stitch triple patterning-aware routing based on conflict graph pre-coloring
VLSI for Multimedia U-NII WLANs
Configurable multi-product floorplanning
ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing
Adaptive supply voltage technique for low swing interconnects
A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies
Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting
A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion
Efficient power grid integrity analysis using on-the-fly error check and reduction
Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound
CrossRouter: a droplet router for cross-referencing digital microfluidic biochips
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories
A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications
A reliable low-power fast skew-compensation circuit
Design of a scalable many-core processor for embedded applications
TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation
Congestion driven incremental placement algorithm for standard cell layout
Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice
Power Reduction in Microprocessor Chips by Gated Clock Routing
Mobile user classification and authorization based on gesture usage recognition
Fast and Accurate OPC for Standard-Cell Layouts
TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning
Customized on-chip memories for embedded chip multiprocessors
High-throughput decoder for low-density parity-check code
Application of Deep Learning in Back-End Simulation: Challenges and Opportunities
Parallel implementation of R-trees on the GPU
PAC duo system power estimation at ESL
A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential
Partitioned bus coding for energy reduction
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS
Emag-Aware ML-Based Layout Optimization for High-Speed IC Design
Register pressure aware scheduling for high level synthesis
An ILP-based automatic bus planner for dense PCBs
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Combining ordered best-first search with branch and bound for exact BDD minimization
Design of a scalable RSA and ECC crypto-processor
On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques
An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
QED post-silicon validation and debug: Frequently asked questions
Algorithm-hardware co-optimization of the memristor-based framework for solving SOCP and homogeneous QCQP problems
An effective legalization algorithm for mixed-cell-height standard cells
Challenges and opportunities of internet of things
Accelerating statistical static timing analysis using graphics processing units
Multi-level placement with circuit schema based clustering in analog IC layouts
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
SAT-based optimal hypergraph partitioning with replication
A multilevel analytical placement for 3D ICs
Binding and Scheduling Algorithms for Highly Retargetable Compilation
Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
A model-based design of Cyber-Physical Energy Systems
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design
Learning heuristics by genetic algorithms
A formal approach to component based development of synchronous programs
A high-speed FIR digital filter with CSD coefficients implemented on FPGA
Variability-aware robust design space exploration of chip multiprocessor architectures
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout
EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit
Synthesis of power- and area-efficient binary machines for incompletely specified sequences
Incremental and on-demand random walk for iterative power distribution network analysis
Performance-preserved analog routing methodology via wire load reduction
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs
ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive Dataflow
Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips
Exploration of VLSI CAD researches for early design rule evaluation
Timing measurement unit with multi-stage TVC for embedded memories
Delay-driven layer assignment for advanced technology nodes
Data privacy in non-volatile cache: Challenges, attack models and solutions
Low power design using dual threshold voltage
Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips
A simplified transmission-line based crosstalk noise model for on-chip RLC wiring
A 686Mbps 1.85mm 2 near-optimal symbol detector for spatial modulation MIMO systems in 0.18μm CMOS
A fast approximation technique for power grid analysis
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design
Audio Adversarial Examples Generation with Recurrent Neural Networks *
NeuralHMC: an efficient HMC-based accelerator for deep neural networks
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation
A tighter recursive calculus to compute the worst case traversal time of real-time traffic over NoCs
Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations
Assessing CPA resistance of AES with different fault tolerance mechanisms
Solving constrained via minimization by compact linear programming
Performance-optimal clustering with retiming for sequential circuits
Narrow bus encoding for low power systems
Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
CMA-2 : The second prototype of a low power reconfigurable accelerator
Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators
Low power implementation of a turbo-decoder on programmable architectures
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction
A high performance reliable NoC router
Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach
TAPHS: thermal-aware unified physical-level and high-level synthesis
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data
A 52-mW 8.29mm 2 19-mode LDPC decoder chip for mobile WiMAX applications
Equivalent circuit model extraction for interconnects in 3D ICs
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems
Post-silicon debugging for multi-core designs
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging
Running sparse and low-precision neural network: When algorithm meets hardware
A fast parallel approach for common path pessimism removal
VLSI block placement using less flexibility first principles
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process
Linux kernel customization for embedded systems by using call graph approach
Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators
FPGA-Accelerated Maze Routing Kernel for VLSI Designs
Memory-efficient interconnect optimization
FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity
Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization
HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor
An efficient multi-port memory controller for multimedia applications
Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues
Two-phase protocol converters for 3D asynchronous 1-of-n data links
Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing
A procedure for software synthesis from VHDL models
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester
Layout-based Logic Decomposition for Timing Optimization
Modeling and forecasting of manufacturing variations (embedded tutorial)
IO connection assignment and RDL routing for flip-chip designs
Piracy prevention of digital microfluidic biochips
Improving simulation-based verification by means of formal methods
A low dynamic power and low leakage power 90-nm CMOS square-root circuit
Learning heuristics for OKFDD minimization by evolutionary algorithms
An application classification guided cache tuning heuristic for multi-core architectures
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
READ-based In-Memory Computing using Sentential Decision Diagrams
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks
Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems
An 8×8 nRERL serial multiplier for ultra-low-power aplications
A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines
An approximation algorithm to the optimal switch control of reconfigurable battery packs
A configurable AES processor for enhanced security
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization
Managing complexity in design debugging with sequential abstraction and refinement
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits
Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability
NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy Traffic
VLSI floorplanning with boundary constraints based on corner block list
Single-track asynchronous pipeline controller design
A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs
ASSURER: A PPA-friendly Security Closure Framework for Physical Design
White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse Engineering
ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors All the Way up Processors
Hierarchical graph reduction approach to symbolic circuit analysis with data sharing and cancellation-free properties
Safe Delay Optimization for Physical Synthesis
Hierarchical Floorplan Design on the Internet
Automated design and optimization of circuits in emerging technologies
Symbolic Model Checking of Analog/Mixed-Signal Circuits
Double edge triggered Feedback Flip-Flop in sub 100NM technology
Log-quantized stochastic computing for memory and computation efficient DNNs
Approximate formulae approach for efficient inductance extraction
Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees
Circuit partitioning with coupled logic restructuring techniques
Exploiting state encoding for invariant generation in induction-based property checking
Application Driven Variable Reordering and an Example Implementation in Reachability Analysis
A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules
SRAM delay fault modeling and test algorithm development
Property Directed Reachability for QF_BV with mixed type atomic reasoning units
Through-silicon-via inductor: Is it real or just a fantasy?
Optimal Evaluation Clocking of Self-Resetting Domino Pipelines
Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Detecting hardware Trojans in unspecified functionality through solving satisfiability problems
A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition
Block remap with turnoff: A variation-tolerant cache design technique
Improving tag generation for memory data authentication in embedded processor systems
HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing
An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range
Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices
Energy-efficient system design for IoT devices
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing
A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna
Micro-bump assignment for 3D ICs using order relation
Simultaneous floorplanning and buffer block planning
Path criticality computation in parameterized statistical timing analysis
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor
Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data
REWIRED - Register Write Inhibition by Resource Dedication
Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution
A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique
Software Tools for Decoding Quantum Low-Density Parity-Check Codes
HyPPO: Hybrid Piece-wise Polynomial Approximation and Optimization for Hardware Efficient Designs
A binary image sensor with flexible motion vector detection using block matching method
A two-step search engine for large scale boolean matching under NP3 equivalence
Realization of semiconductor device synthesis with the parallel genetic algorithm
Crosstalk-aware power optimization with multi-bit flip-flops
Buffered clock tree sizing for skew minimization under power and thermal budgets
Formal verification of distributed controllers using Time-Stamped Event Count Automata
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
On hazard-free implementation of speed-independent circuits
Trojan localization using symbolic algebra
An RTL design-space exploration method for high-level applications
Architecture design with STT-RAM: Opportunities and challenges
TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper)
Synthesis of Reversible Sequential Elements
Fine-grained accelerators for sparse machine learning workloads
On speeding up extended finite state machines using catalyst circuitry
An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing Resources
Timing variation-aware task scheduling and binding for MPSoC
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks
Yield-driven redundant power bump assignment for power network robustness
Low-cost control flow error protection by exploiting available redundancies in the pipeline
Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems
Relaxed hierarchical power/ground grid analysis
Design methodology for approximate accumulator based on statistical error model
Functional modeling techniques for efficient SW code generation of video codec applications
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems
3DIC from concept to reality
Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial)
Redundant-via enhanced maze routing for yield improvement
Detecting non-functional circuit activity in SoC designs
Minimizing energy consumption of multiple-processors-core systems with simultaneous task allocation, scheduling and voltage assignment
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization
Robust analytical gate delay modeling for low voltage circuits
An energy-efficient random number generator for stochastic circuits
On the design and analysis of fault tolerant NoC architecture using spare routers
A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply Systems
Hardware Trojan Detection Using Shapley Ensemble Boosting
A low latency wormhole router for asynchronous on-chip networks
Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems
A sigma-delta modulation based BIST scheme for mixed-signal circuits
Fast, predictable and low energy memory references through architecture-aware compilation
SMYLEref: A reference architecture for manycore-processor SoCs
VLSI Mask Optimization: From Shallow To Deep Learning