yusuke1997/dblp-id-title huggingface dataset:
Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior
Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems
Fault-secure shifter design: results and implementations
Sparrow: Flexible Memory Deduplication in Android Systems with Similar-Page Awareness
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG
Aggressive Memory Speculation in HW/SW Co-Designed Machines
Accuracy Tolerant Neural Networks Under Aggressive Power Optimization
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
Robust Binary Neural Network against Noisy Analog Computation
STAR: An Efficient Softmax Engine for Attention Model with RRAM Crossbar
Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms
Reducing Address Bus Transitions for Low Power Memory Mapping
Future of HPC: Diversifying Heterogeneity
The metamodeling approach to system level synthesis
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
CARAT: a toolkit for design and performance analysis of component-based embedded systems
IoT-GRAF: IoT Graph Learning-Based Anomaly and Intrusion Detection Through Multi-Modal Data Fusion
Functional Verification for SystemC Descriptions Using Constraint Solving
System Level Design Using C++
Joint affine transformation and loop pipelining for mapping nested loop on CGRAs
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Analog design for reuse - case study: very low-voltage sigma-delta modulator
Cut mask optimization for multi-patterning directed self-assembly lithography
Low Static-Power Frequent-Value Data Caches
LARS: Logically adaptable retention time STT-RAM cache for embedded systems
BatchLens: A Visualization Approach for Analyzing Batch Jobs in Cloud Systems
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool
A hardware-software operating system for heterogeneous designs
High level H.264/AVC video encoder parallelization for multiprocessor implementation
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions
Multi-thread graph: a system model for real-time embedded software synthesis
PumpChannel: An Efficient and Secure Communication Channel for Trusted Execution Environment on ARM-FPGA Embedded SoC
Improving Cell-Aware Test for Intra-Cell Short Defects
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams
SMART: a single-cycle reconfigurable NoC for SoC applications
Cache-Aware Kernel Tiling: An Approach for System-Level Performance Optimization of GPU-Based Applications
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses
Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation
Umbra: An Efficient Framework for Trusted Execution on Modern TrustZone-Enabled Microcontrollers
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Soft error-aware design optimization of low power and time-constrained embedded systems
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architectures
Analyzing the effects of peripheral circuit aging of embedded SRAM architectures
Analysis and reduction of glitches in synchronous networks
Defining an Enhanced RTL Semantics
Guaranteed Activation of Capacitive Trojan Triggers During Post Production Test via Supply Pulsing
Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist
A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery Networks
Compiler-Directed Instruction Duplication for Soft Error Detection
LiM-HDL: HDL-Based Synthesis for In-Memory Computing
Low-overhead adaptive constrast enhancement and power reduction for OLEDs
Logic Synthesis for Generalization and Learning Addition
Leveraging power spectral density for scalable system-level accuracy evaluation
Reducing Write Amplification for Inodes of Journaling File System using Persistent Memory
Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits
Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots
ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design
Prediction-Based Task Migration on S-NUCA Many-Cores
Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation
AutoMoDe - Model-Based Development of Automotive Software
Efficient Design of a Hyperdimensional Processing Unit for Multi-Layer Cognition
Gibbon: Efficient Co-Exploration of NN Model and Processing-In-Memory Architecture
Efficient and scalable OpenMP-based system-level design
Predicting bus contention effects on energy and performance in multi-processor SoCs
Semiconductor Challenges
Programming and analysing scenario-aware dataflow on a multi-processor platform
System safety through automatic high-level code transformations: an experimental evaluation
Perspector: Benchmarking Benchmark Suites
Synthesis of approximate coders for on-chip interconnects using reversible logic
Neural Circuit Parameter Prediction for Efficient Quantum Data Loading
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays
CCII+ current conveyor based BIC monitor for I DDQ testing of complex CMOS circuits
Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning
An Incremental Specification Flow for Real Time Embedded Systems
Optimal State Preparation for Logical Arrays on Zoned Neutral Atom Quantum Computers
Efficient Run-Time Environments for System-Level LET Programming
Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint
Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach
SCORE: SPICE COmpatible Reluctance Extraction
Implementation issues in the hierarchical composition of performance models of analog circuits
Architecture and FPGA-implementation of a high throughput K + -Best detector
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network
Pathways to servers of the future
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique
Investigating power outage effects on reliability of solid-state drives
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
OPS: Outlier-Aware Precision-Slice Framework for LLM Acceleration
Self-adaptive hybrid dynamic power management for many-core systems
Mixed-criticality processing pipelines
Resolution-Aware Deep Multi-View Camera Systems
Clocktree RLC Extraction with Efficient Inductance Modeling
Boosting the role of inductive invariants in model checking
Spying on Temperature using DRAM
Memristive devices for computation-in-memory
Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA
Full chip false timing path identification: applications to the PowerPCTM microprocessors
Width minimization in the Single-Electron Transistor array synthesis
Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design
Activation of logic encrypted chips: Pre-test or post-test?
Late Breaking Results: AFS: Improving Accuracy of Quantized Mamba via Aggressive Forgetting Strategy
Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation
Deterministic Fault-Tolerant State Preparation for Near-Term Quantum Error Correction: Automatic Synthesis Using Boolean Satisfiability
Formal specification of networks-on-chips: deadlock and evacuation
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)
Alternative Test Methods Using IEEE 1149.4
Collective Knowledge: Towards R&D sustainability
BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips ∗
An electrical test method for MEMS convective accelerometers: Development and evaluation
A Technique for High Ratio LZW Compression
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study
Robustness analysis of 6T SRAMs in memory retention mode under PVT variations
Functional test for shifting-type FIFOs
Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition
High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms
Evaluation of diverse compiling for software-fault detection
Resilient Dynamic Power Management under Uncertainty
Power-efficient layered turbo decoder processor
Overview of Health Monitoring Techniques for Reliability
Design and implementation of a coprocessor for cryptography applications
IP Day: How to Choose Semiconductor IP?
A Fault Simulation Methodology for MEMS
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories
Placement optimization of power supply pads based on locality
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Contango: Integrated optimization of SoC clock networks
A tool for the assisted design of charge redistribution SAR ADCs
Automatic Routing for Photonic Integrated Circuits Under Delay Matching Constraints
Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC Designs
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking
Optimization intensive energy harvesting
XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique
Assisted generation of frame conditions for formal models
Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions
NFRs early estimation through software metrics
Automatic specification granularity tuning for design space exploration
Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test Environment
Panel and embedded tutorial - Logic synthesis and place and route: After 20 years of engagement, wedding in view?
Accelerating Quantum Approximate Optimization Algorithm using Machine Learning
Faster SAT solving with better CNF generation
TitanCFI: Toward Enforcing Control-Flow Integrity in the Root -of- Trust
A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
Vectorization of Reed Solomon Decoding and Mapping on the EVP
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study
A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication
Workload Characterization Model for Tasks with Variable Execution Demand
Self-heating-aware optimal wire sizing under Elmore delay model
Agglomerative-based flip-flop merging with signal wirelength optimization
3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing
Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection
Power modeling and analysis in early design phases
A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs
1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France
Accelerating Inference of 3D-CNN on ARMMany-core CPU via Hierarchical Model Partition
Multi-Partner Project: Smart Sensor Analog Front-Ends Powered by Emerging Reconfigurable Devices (SENSOTERIC)
Software Streaming via Block Streaming
A New System Design Methodology for Wire Pipelined SoC
GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing
Spoiler-Alert: Detecting Spoiler Attacks Using a Cuckoo Filter
A flexible topology selection program as part of an analog synthesis system
On Functional Test Generation for Deep Neural Network IPs
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach
A hybrid approach for fast and accurate trace signal selection for post-silicon debug
The hidden cost of functional approximation against careful data sizing - A case study
Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology
DPR in high energy physics
Generating finite state machines from SystemC
Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management
Formal reset recovery slack calculation at the register transfer level
Interconnect delay and slew metrics using the beta distribution
An energy-efficient memory hierarchy for multi-issue processors
BB-GC: Basic-Block Level Garbage Collection
Hardware-accelerated dynamic binary translation
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline
Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions
Lookup table allocation for approximate computing with memory under quality constraints
FP-scheduling for mode-controlled dataflow: a case study
A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets
Location detection for navigation using IMUs with a map through coarse-grained machine learning
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing
Resource-Aware Application Execution Exploiting the BarbequeRTRM
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory
Profiling-driven multi-cycling in FPGA high-level synthesis
Effects of cell shapes on the routability of Digital Microfluidic Biochips
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
On the reuse of timing resilient architecture for testing path delay faults in critical paths
Front End Device for Content Networking
Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems
Hardware / software design challenges of low-power sensor nodes for condition monitoring
Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems
State-based full predication for low power coarse-grained reconfigurable architecture
Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing
i-BEP: A non-redundant and high-concurrency memory persistency model
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor
Bridging the gap between dual propagation and CNF-based QBF solving
CPU for PlayStation 2
A flexible inexact TMR technique for SRAM-based FPGAs
A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs
Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study
Fault- Tolerant Cyclic Queuing and Forwarding in Time-Sensitive Networking
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits
Non-intrusive virtualization management using libvirt
Sava: A Spatial- and Value-Aware Accelerator for Point Cloud Transformer
SPHERE-DNA: Privacy-Preserving Federated Learning for eHealth
SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract
Digital design at a crossroads How to make statistical design methodologies industrially relevant
Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approach
Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic
Gradient Boosting-Accelerated Evolution for Multiple-Fault Diagnosis
Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection
State-Preserving vs. Non-State-Preserving Leakage Control in Caches
Efficient Test Generation for Trojan Detection using Side Channel Analysis
Responsible Artificial Intelligence Systems: From Trustworthiness to Governance
HLC: software-based half-level-cell flash memory
40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS
WALL: A writeback-aware LLC management for PCM-based main memory systems
Low complexity LDPC code decoders for next generation standards
Class-Aware Pruning for Efficient Neural Networks
SyncLock: RF Transceiver Security Using Synchronization Locking
Low-Complexity Dynamic Channel Scaling of Noise-Resilient CNN for Intelligent Edge Devices
Shyper: An embedded hypervisor applying hierarchical resource isolation strategies for mixed-criticality systems
VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering
Trace-Enabled Timing Model Synthesis for ROS2-based Autonomous Applications
Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs
Write-once-memory-code phase change memory
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study
Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargeting
TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation
Logic Transformation for Low Power Synthesis
High-fidelity markovian power model for protocols
Exploiting approximate computing for deep learning acceleration
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs
A Mapping of Triangular Block Interleavers to DRAM for Optical Satellite Communication
Optimizing CMOS Circuits for Low Power Using Transistor Reordering
Automatic test vector generation for mixed-signal circuits
A Solution for Hardware Emulation of Non Volatile Memory Macrocells
Utilizing Formal Assertions for System Design of Network Processors
Efficient Embedded Machine Learning applications using Echo State Networks
Pre-bond testing of the silicon interposer in 2.5D ICs
${MC}^{3}$: Memory Contention-Based Covert Channel Communication on Shared DRAM System-on-Chips
Energy and execution time analysis of a software-based trusted platform module
A Parallel Graph Environment for Real-World Data Analytics Workflows
SAFE: Security-Aware FlexRay Scheduling Engine
Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes
Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC
Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores
Energy-efficient FPGA interconnect design
Test set enrichment using a probabilistic fault model and the theory of output deviations
A Comprehensive Inductance-Aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated Circuits
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model
Stochastic Quantum Circuit Simulation Using Decision Diagrams
A methodology for the characterization of process variation in NoC links
Spintronics for low-power computing
Slow write driver faults in 65nm SRAM technology: analysis and March test solution
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques
HyGraph: Accelerating Graph Processing with Hybrid Memory-centric Computing
Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D
An RDL-configurable 3D memory tier to replace on-chip SRAM
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach
Runtime Fault Injection Detection for FPGA-based DNN Execution Using Siamese Path Verification
Nostradamus: Low-cost hardware-only error detection for processor cores
Automated generation of directed tests for transition coverage in cache coherence protocols
Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models
Networks on Chip: A New Paradigm for Systems on Chip Design
SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Exploiting Idle Cycles for Algorithm Level Re-Computing
Portable multimedia SoC design: a global challenge
NIM- a noise index model to estimate delay discrepancies between silicon and simulation
LT-OAQ: Learnable Threshold Based Outlier-Aware Quantization and its Energy-Efficient Accelerator for Low-Precision On-Chip Training
Accurate verification of RC power grids
A 3D reconfigurable platform for 4G telecom applications
Network Processing Challenges and an Experimental NPU Platform
European CAD from the 60's to the New Millenium
moDNN: Memory optimal DNN training on GPUs
Proving testing preorders for process algebra descriptions
DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests
SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars
CRISP: Hybrid Structured Sparsity for Class-Aware Model Pruning
On-line testing of permanent radiation effects in reconfigurable systems
Efficient computation of the worst-delay corner
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS
Event-driven and sensorless photovoltaic system reconfiguration for electric vehicles
Mixed-signal modelling in VHDL for system-on-chip applications
A high-performance parallel implementation of the Chambolle algorithm
Atomic but Lazy Updating with Memory-mapped Files for Persistent Memory
PASTEL: A Parameterized Memory Characterization System
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks
A single photon avalanche diode array fabricated in deep-submicron CMOS technology