yusuke1997/dblp-id-title huggingface dataset:
INTB: A New FPGA Interconnect Model for Architecture Exploration
Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-Package
Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only)
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System
Architecture and Circuit Design of an All-Spintronic FPGA
Dealing with the "itanium effect" (abstract only)
Maverick: A Stand-alone CAD Flow for Xilinx 7-Series FPGAs
A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only)
High Throughput Low Latency Network Intrusion Detection on FPGAs: A Raw Packet Approach
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only)
Bus mastering PCI express in an FPGA
Low energy FPGA interconnect design
Area-efficient near-associative memories on FPGAs
Cad and routing architecture for interposer-based multi-FPGA systems
Power estimation approach for SRAM-based FPGAs
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking
Modeling routing demand for early-stage FPGA architecture development
Post-placement interconnect entropy
Using DSP blocks to compute CRC hash in FPGA (abstract only)
Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware
CMOS vs Nano: comrades or rivals?
Architecture support for custom instructions with memory operations
Incremental reconfiguration of multi-FPGA systems
Communication visualization for bottleneck detection of high-level synthesis applications
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only)
Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
High-Performance QR Decomposition for FPGAs
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond
Logic Partition Orderings for Multi-FPGA Systems
On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011
A synthesizable datapath-oriented embedded FPGA fabric
Managing Pipeline-Reconfigurable FPGAs
Programming high performance signal processing systems in high level languages
Configuration tools for a new multilevel hierarchical FPGA
An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)
Testing for bit error rate in FPGA communication interfaces
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract)
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005
An intermediate hardware model with load/store unit for C to FPGA
Lessons from 40 Years of Reconfigurable Computing
High-quality, deterministic parallel placement for FPGAs on commodity hardware
Building zynq® accelerators with Vivado® high level synthesis
Binary stochastic implementation of digital logic
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture
Impact of Soft Errors on Large-Scale FPGA Cloud Computing
FPCNA: a field programmable carbon nanotube array
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach
Speedy FPGA-based packet classifiers with low on-chip memory requirements
Energy-efficient FPGA interconnect architecture design (abstract only)
Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines
GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms
Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES
Numerical Program Optimization for High-Level Synthesis
Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only)
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays
HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion
Dynamic voltage & frequency scaling with online slack measurement
A fast discrete placement algorithm for FPGAs
Fpga-based data acquisition system for a positron emission tomography (PET) scanner
Architecture Exploration for HLS-Oriented FPGA Debug Overlays
When FPGAs are better at floating-point than microprocessors
SPFD-based one-to-many rewiring
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA
FPGA clock management for low power applications (poster abstract)
What is the right model for programming and using modern FPGAs?
Combining Dynamic & Static Scheduling in High-level Synthesis
A Deep Learning Inference Accelerator Based on Model Compression on FPGA
High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA
Modeling and simulation of nano quantum FPGAs (abstract only)
FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture
Runtime and quality tradeoffs in FPGA placement and routing
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation
The Virtuous Cycles of Determinism: Programming Groq's Tensor Streaming Processor
Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only)
Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL
Parallel FPGA placement based on individual LUT placement (abstract only)
RASP: A General Logic Synthesis System for SRAM-Based FPGAs
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCI
Memory efficient string matching: a modular approach on FPGAs (abstract only)
Energy reduction with run-time partial reconfiguration (abstract only)
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
Techniques for synthesizing binaries to an advanced register/memory structure
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI
Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation
Producing high-quality real-time HDR video system with FPGA (abstract only)
Interconnect enhancements for a high-speed PLD architecture
Secure Function Evaluation Using an FPGA Overlay Architecture
Functionally verifying state saving and restoration in dynamically reconfigurable systems
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation
Floating-Point DSP Block Architecture for FPGAs
A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs
Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization)
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme
Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only)
Parallel placement for FPGAs revisited
Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only)
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019
RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA (Abstract Only)
Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only)
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only)
An FPGA architecture with built-in error correction capability
Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only)
The 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, USA - February 26 - 28, 2014
Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance
A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only)
Fpga-based face detection system using Haar classifiers
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer
Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs
DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only)
Evaluation of low-leakage design techniques for field programmable gate arrays
hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA
REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract)
RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library
3M-AI: A Multi-task and Multi-core Virtualization Framework for Multi-FPGA AI Systems in the Cloud
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference
Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's
FPGA Acceleration for Computational Glass-Free Displays
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs
An iterative division algorithm for FPGAs
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
DYNAMAP: Dynamic Algorithm Mapping Framework for Low Latency CNN Inference
Efficient FPGAs using nanoelectromechanical relays
REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only)
Timing Driven Floorplanning on Programmable Hierarchical Targets
Towards scalable FPGA CAD through architecture
Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding
FPGA-Placement via Quantum Annealing
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions
A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction
ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture
Context-free-grammar based token tagger in reconfigurable devices
A 65nm flash-based FPGA fabric optimized for low cost and power
Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only)
Stealing Neural Network Structure through Remote FPGA Side-channel Analysis
Open-source and FPGAs: Hardware, Software, Both or None?
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms
Dynamic Loop Fusion in High-Level Synthesis
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only)
RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only)
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only)
Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only)
Recursive circuit clustering for minimum delay and area
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only)
Seamless Acceleration of Fortran Intrinsics via AMD AI Engines
Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs
Authenticated encryption for FPGA bitstreams
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV
Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms
Cholesky decomposition using fused datapath synthesis
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization
Configurable decoders with application in fast partial reconfiguration of FPGAs
From Topology to Realization in FPGA/VPR Routing
Implementation of BEE: a real-time large-scale hardware emulation engine
Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007
A type architecture for hybrid micro-parallel computers
Architectures for AI
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001
A reconfigurable unit for a clustered programmable-reconfigurable processor
Automatic Construction of Program-Optimized FPGA Memory Networks
An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only)
Weave: Abstraction for Accelerator Integration of Generated Modules
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
A scalable approach for automated precision analysis
HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs
Revisiting and-inverter cones
A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters
Custom instruction generation and mapping for reconfigurable instruction set processors (abstract only)
Generating highly-routable sparse crossbars for PLDs
Roving testing using new built-in-self-tester designs for FPGAs
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC
FPGA-based fine-grain parallel computing (abstract only)
400-MHz Frequency Counter: A Case Study in Semi-Synchronous Design
SmartOpt: an industrial strength framework for logic synthesis
Scalable interconnect and power distribution for island-style FPGAs (poster abstract)
CoRAM: an in-fabric memory architecture for FPGA-based computing
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture
Speedy: An Accelerator for Sparse Convolutional Neural Networks on FPGAs
Partial FPGA Rearrangement by Local Repacking (Abstract)
Productive Hardware Designs using Hybrid HLS-RTL Development
VEGAS: soft vector processor with scratchpad memory
Exploring PGAS Communication for Heterogeneous Clusters with FPGAs
Techniques for FPGA Implementation of Video Compression Systems
Are We Alone? Searching for ET with FPGAs
PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
Evolving Computer Programs Using Rapidly Reconfigurable Field-Programmable Gate Arrays and Genetic Programming
fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)
HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation
Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration
Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only)
Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform
Acceleration of Synthetic Aperture Radar (SAR) Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)
Combined Spectral Techniques for Boolean Matching
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs
Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only)
Hardware Implementation of Generalized Profile Search on the GENSTROM Machine (Abstract)
Hybrid FPGA Architecture
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger
Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only)
Manifold similarity search of DNA sequences with reconfigurable hardware
FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method
A high performance 32-bit ALU for programmable logic
Theory and algorithm for generalized memory partitioning in high-level synthesis
An Automated Design Framework for Floating Point Scientific Algorithms using Field Programmable Gate Arrays (FPGAs) (Abstract Only)
Optimizing Order-Associative Kernel Computation with Joint Memory Banking and Data Reuse
Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT
FPGA placement by graph isomorphism (abstract only)
Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only)
Architectures and algorithms for synthesizable embedded programmable logic cores
A type system for static typing of a domain-specific language
OmpSs@Zynq all-programmable SoC ecosystem
Silicon Verification using High-Level Design Tools (Abstract Only)
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic
Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract)
Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only)
OCTAVO: an FPGA-centric processor family
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement
Measuring and modeling variabilityusing low-cost FPGAs
Architectural enhancements in Stratix-III TM and Stratix-IV TM
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond
A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)
High-Level Design Tools for Floating Point FPGAs
FPGA-friendly code compression for horizontal microcoded custom IPs
Harnessing the power of FPGAs using altera's OpenCL compiler
Subframe multiplexing for FPGA manufacturing test configuration
Closed-loop modeling of power and temperature profiles of FPGAs
High-performance, energy-efficient platforms using in-socket FPGA accelerators
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing
Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization
On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based system
Efficient Generation of Energy and Performance Pareto Front for FPGA Designs (Abstract Only)
Simultaneous timing-driven placement and duplication
Performance and power of cache-based reconfigurable computing
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only)
Dynamically reconfigurable architecture for high-throughput processing of data centric applications
Dynamically Scheduled High-level Synthesis
FPGA implementation of real-time skin color detection with mean-based surface flattening
FPGA interconnect design using logical effort
FTDL: An FPGA-tailored Architecture for Deep Learning Systems
Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking
A memory coherence technique for online transient error recovery of FPGA configurations
What To Do With Datacenter FPGAs Besides Deep Learning
Fast and accurate resource estimation of automatically generated custom DFT IP cores
The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers
FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs
Agile Co-Design for a Reconfigurable Datacenter
Efficient system-level mapping from streaming applications to FPGAs (abstract only)
Software-Driven Hardware Development
BMP: a fast B*-tree based modular placer for FPGAs (abstract only)
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only)
The P4->NetFPGA Workflow for Line-Rate Packet Processing
Power-aware FPGA logic synthesis using binary decision diagrams
Quantifying the cost and benefit of latency insensitive communication on FPGAs
A Machine Learning Framework for FPGA Placement (Abstract Only)
Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only)
Computation reuse in domain-specific optimization of signal recognition
FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only)
SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC
A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via on-chip Dynamic Tree Management
Symbiosis in Action: Reconfigurable Architectures and EDA
K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only)
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs
High-throughput interconnect wave-pipelining for global communication in FPGAs
Attacking elliptic curve cryptosystems with special-purpose hardware
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder
Rapid Cycle-Accurate Simulator for High-Level Synthesis
Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems
Memory block based scan-BIST architecture for application-dependent FPGA testing
Efficient in-system RTL verification and debugging using FPGAs (abstract only)
Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation
Extra-Dimensional Island-Style FPGAs
Field programmable port extender (FPX) for distributed routing and queuing
A Reconfigurable Arithmetic Array for Multimedia Application
GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only)
Accelerating short read mapping on an FPGA (abstract only)
Maximizing CNN Throughput on FPGA Clusters
Energy efficient sensor node implementations
A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System
A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs
Accelerating Financial Market Server through Hybrid List Design (Abstract Only)
A latency-optimized hybrid network for clustering FPGAs (abstract only)
Saturating the transceiver bandwidth: switch fabric design on FPGAs