yusuke1997/dblp-id-title huggingface dataset:
A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures
A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic
Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits
Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach
2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA
Code-coverage Based Test Vector Generation for SystemC Designs
A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking
Security as an Important Ingredient in Neuromorphic Engineering
MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications
DENA: A DVFS-Capable Heterogeneous NoC Architecture
A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End
Silicon Demonstration of Statistical Post-Production Tuning
Secure-iGLU: A Secure Device for Noninvasive Glucose Measurement and Automatic Insulin Delivery in IoMT Framework
A Fine-Grain Phased Logic CPU
Machine Learning and Polynomial Chaos models for Accurate Prediction of SET Pulse Current
2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures
Real-time low-power task mapping in Networks-on-Chip
Coding for Efficient Caching in Multicore Embedded Systems
A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications
Motion Detection over 5G through Sensing Signal Disturbance Analysis leveraging COTS platform
Low Power High Performance Digitally Assisted Pipelined ADC
A novel optimization method for reversible logic circuit minimization
A Design of Experiment Based Approach to Variance Optimal Design of CMOS OpAmp
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAs
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis
A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning
Reconfigurable Fast Memory Management System Design for Application Specific Processors
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing
Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator Circuit
Simscape Based Ultra-Fast Design Exploration of Graphene-Nanoelectronic Systems
Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units
SNN-ANN Hybrid Networks for Embedded Multimodal Monocular Depth Estimation
A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems
EGaIn-Based Liquid Antennas: Beam Steering and Frequency Reconfiguration Using Microfluidic Control
Compact 6T-SRAM Using Bottom-Gate Transistor in FD-SOI Process for Monolithic-3D Integration
Harnessing Approximate Computing for Machine Learning
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2023, Foz do Iguacu, Brazil, June 20-23, 2023
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures
Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment
SafeController: Efficient and Transparent Control-Flow Integrity for RTL Design
Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits
Semi-Classical Modelling of the Electron Transport in Carbon Nanotubes and Graphene Nanoribbons for THz Range Applications
A Design Space Exploration Methodology for Application Specific MPSoC Design
BDD Variable Ordering for Minimizing Power Consumption of Optical Logic Circuits
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes
Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors
Flow Maximization for NoC Routing Algorithms
End-to-End Industrial Study of Retiming
A High Performance Hybrid Wave-Pipelined Multiplier
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs
Virtual Point-to-Point Links in Packet-Switched NoCs
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride
Efficient implementation of conduction modes for modelling skin effect
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems
Efficient FPGA Implementation of the SHA-3 Hash Function
Adiabatic Logic-based STT-MRAM Design for IoT
A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology
Practical Error Modeling Toward Realistic NISQ Simulation
A VLSI Design for Neuromorphic Computing
Towards Making Private Circuits Practical: DPA Resistant Private Circuits
Task Dispersal Measurement in Dynamic Reconfigurable NoCs
An External Memory Circuit Validation Algorithm for Large VLSI Layouts
Adaptive Multi-Precision Inference for Large-Scale AI Using IEEE P3109 FP8
Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model
Design of Low Power SAR ADC Using Clock Retiming
Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered Systems
ResSen: Imager Privacy Enhancement Through Residue Arithmetic Processing in Sensors
Semiformal Verification of Software-Controlled Connections
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic
Design and Implementation of a Reversible Central Processing Unit
Impact of Technology Scaling on Digital Subthreshold Circuits
A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier
Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons
Design of a Hierarchical Clos-Benes Optical Network-on-Chip Architecture
Tot-Mon: A Real-Time Internet of Things Based Affective Framework for Monitoring Infants
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation
Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning
Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements
Proposal of A Novel Hybrid NAND-Like MRAM/DRAM Memory Architecture
Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops
DREAM: A Chip-Package Co-Design Tool for RF-Mixed Signal Systems
Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs
Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture
AnaIR: A Semi-Analytical Green's Function Inspired Neural Network for Static IR Drop Prediction
Mitigating Reverse Engineering Attacks on Deep Neural Networks
Implementing Data Structure Using DNA: An Alternative in Post CMOS Computing
Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency
Index-Based Round-Robin Arbiter for NoC Routers
Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices
An ESL Environment for Modeling Electrical Interconnect Faults
Hardware/Software Co-Exploration for Graph Neural Architectures on FPGAs
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique
A Side-Channel Attack Resistant AES with 500Mbps, 1.92pJ/Bit PVT Variation Tolerant True Random Number Generator
Ultra-Low-Power Sensor Signal Monitoring and Impulse Radio Architecture for Biomedical Applications
Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR
Towards Efficient Compact Network Training on Edge-Devices
MADel0: A Modelling and Assessment Framework for Delay PUFs leveraging Gradient-based Optimization Techniques
Trojan Taxonomy in Quantum Computing
Area-Efficient Pipelined VLSI Architecture for Polar Decoder
Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications
Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder
A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips
A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing
Harnessing Emerging Technology for Compute-in-Memory Support
On the Potentials of FinFETs for Asynchronous Circuit Design
Memory Locking: An Automated Approach to Processor Design Obfuscation
Design of Quantum Circuits for Random Walk Algorithms
Low Standby Power and Robust FinFET Based SRAM Design
From Device to Application - Integrating RRAM Accelerator Blocks into Large AI Systems
Efficient Tree Architecture for the Design of Static CMOS Magnitude Comparators
Design of a QCA Memory with Parallel Read/Serial Write
Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless Communications
Sub-Threshold Design and Architectural Choices
On-the-fly Validation of Hierarchical Cache Coherence Protocols using Directed Testing
CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCON
IoMT Synthetic Cardiac Arrest Dataset for eHealth with AI-based Validation
Secure PUF-based Authentication and Key Exchange Protocol using Machine Learning
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies
TinyML for ECG Biometrics on Resource Constrained Devices
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages
Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications
VLSI Implementation for MAC-Level DWT Architecture
The Power of Orthogonality
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities
Hardware Design Automation of Convolutional Neural Networks
STCO: Driving the More than Moore Era
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library
Improving the Sustainability of Solid-State Drives by Prolonging Lifetime
Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and Verification
Development of High-Stability, Low-Leakage 6Tr-SRAM with Single Data Line and Single Power Supply Using SOTB Process
On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform
A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits
iMACE: In-Memory Acceleration of Classic McEliece Encoder
Optimization and Security of AI Models for Deployment at Edge: A Comprehensive Review
Layout-Aware Selection of Trace Signals for Post-Silicon Debug
Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization
Input-Output Selection Based Router for Networks-on-Chip
Exploiting Circuit Duality to Speed up SAT
Stealing Machine Learning Parameters via Side Channel Power Attacks
High and low side high voltage switch with over voltage and over current protection
Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication
BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection
Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material
Advanced Channel Decoding Algorithms and Their Implementation for Future Communication Systems
SRAM Beyond FinFET: Performance and Aging Challenges in Nanosheet and CFET
Real-time Padel Strokes Classification
Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters
Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays
A Fully Digital Foreground Calibration Technique of A Flash ADC
Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource Limited Devices
Pasteables: A Flexible, Stick-and-Peel Smart Sensing Platform for Edge Applications
A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient
NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures
Efficient High-Level Power Estimation for Multi-standard Wireless Systems
Retrospective: A CORDIC Based Configurable Activation Function for NN Applications
Mapping Embedded Applications on MPSoCs: The MNEMEE Approach
Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories
5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage Regimes
PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks
FPGA Implementation of High Speed Anti-notch Lattice filter for Exon Region Identification in Eukaryotic Genes
Reliability Analysis and Improvement in Nano Scale Design
Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology
Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow
AIsim: Functional Simulator for Analog-to-Information Perceptual Systems
A Review of Large Parallel Counter Designs
A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio
Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links
Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing
Overview of the Scalable Communications Core
Joint Compression Strategies for CNNs: A Case Study on Low Rank Factorization, Filter-based Pruning and Unstructured Pruning
Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via
Embedding Power Signature Generation into Low Dropout Voltage Regulators for Enhancing IoT Security
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency
Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit
Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology
Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications
A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications
Design Automation and Analysis of Resonant Rotary Clocking Technology
CMOS Analog Programmable Logic Array
Processing-in-Memory with Temporal Encoding
Removing the Root of Trust: Secure Oblivious Key Establishment for FPGAs
Serial ATA Commands Logger for Security Monitoring on FPGA Devices
A VLSI GFP Frame Delineation Circuit
Design and Characterization of the TERO-PUF on SRAM FPGAs
A Comprehensive Electro-Optical Model for Silicon Photonic Switches
Scalable Resonant Power Clock Generation for Adiabatic Logic Design
PPAP and iPPAP: PLL-Based Protection Against Physical Attacks
Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources
Impact of Circuit Degradation on FPGA Design Security
Novel Architecture for Highly Hardware Efficient Implementation of Real Time Matrix Inversion Using Gauss Jordan Technique
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design
The Ternary Quantum-dot Cellular Automata Memorizing Cell
Stochastic Number Generators with Minimum Probability Conversion Circuits
Quantum Divide and Compute: Hardware Demonstrations and Noisy Simulations
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors
Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect
2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures
Ferroelectric FET Based TCAM Designs for Energy Efficient Computing
Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications
An Optimized BIST Architecture for FPGA Look-Up Table Testing
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses
Multiprocessor Systems-on-Chips
A Secure and Sustainable RISC-V Processor with Intrinsic PUF for Edge AI
A New Protocol Stack Model for Network on Chip
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements
Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine
Exploring Image Selection for Self-Testing in Neural Network Accelerators
An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC
Multioperand Decimal Addition
Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM
Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform
Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2 k
Parametric Hierarchy Recovery in Layout Extracted Netlists
A Hardware-Efficient Implementation of CLOC for On-chip Authenticated Encryption
A Power Efficient System Design Methodology Employing Approximate Arithmetic Units
Not All Feed-Forward MUX PUFs Generate Unique Signatures
Code Compression Techniques for Embedded Systems and Their Effectiveness
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing
A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security
A Reconfigurable and Compact Spin-Based Analog Block for Generalizable n th Power and Root Computation
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators
Technological hybridization for efficient runtime reconfigurable FPGAs
Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control
Delay-aware evolutionary optimization of digital circuits
Real Time Bayer Raw Video Projective Transformation System Using FPGA
Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs
Assessing Gaston: Side-channel Security and Hardware Cost Comparison with Ascon-p
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager
Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching
A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers
Reliable Binary Signed Digit Number Adder Design
Recent Research and Challenges in Multiple Patterning Layout Decomposition
Morphed Standard Cell Layouts for Pin Length Reduction
A New Wirelength Model for Analytical Placement
High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor
OFDM Based High Data Rate, Fading Resilient Transceiver for Wireless Networks-on-Chip
A new Multilevel Hierarchical MFPGA and its suitable configuration tools
HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems
Wearable Health Monitoring System for Older Adults in a Smart Home Environment
A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS
Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars
Two exact quantum signal processing results
Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition
System Level Design for Embedded Reconfigurable Systems Using MORPHEUS Platform
Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks
An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-Chip
Hardware-Efficient ECC Processor Design using Non-Homogeneous Split Hybrid Karatsuba Multiplier
Fault recovery communication protocol for NoC-based MPSoCs
A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability
Design of Switched-Current Based Low-Power PIM Vision System for IoT Applications
Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis
New Security Threats on FPGAs: From FPGA Design Tools Perspective
Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security Applications
Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation
Optimization of BDD-based Approximation Error Metrics Calculations
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach
Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning
An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-Resolution
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design
SparseP: Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures
A Programmable Stream Processing Engine for Packet Manipulation in Network Processors
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design
Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process Variability
Quantum Machine Learning for Anomaly Detection in Consumer Electronics
Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture
Analysis of Switching Energy and Delay for Magnetic Logic Devices
Configurable Hardware Module for Low-Power Coding in Heterogeneous-Monolithic 3D NoC Links
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip
Energy-Efficient Basecalling for ONT Long Reads on a Hybrid ASIC-GPU Platform
A Solar Based Power Module for Battery-Less IoT Sensors Towards Sustainable Smart Cities
A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip Communication
Experiments with High Speed Parallel Cubing Units
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach
Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation
Efficient Neural Network Compression for Fast Inference on Hardware
Federated Learning: A Paradigm Shift in Cybersecurity for Smart Grids
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis
Multi-Parameter Power Minimization of Synthesized Datapaths
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators
Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits
Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components
Uncriticality-Directed Low-Power Instruction Scheduling
RAT: RFET-based Analog Hardware Trojan
Hybrid Stochastic Computing of Linear Time O(N) and Its In-Memory Computing for High Performances
A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware
Modeling Subthreshold Leakage Current in General Transistor Networks
Layer-Aware Design Partitioning for Vertical Interconnect Minimization
Sensing Design Issues in Deep Submicron CMOS SRAMs