yusuke1997/dblp-id-title huggingface dataset:
Criticality computation in parameterized statistical timing
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations
Parallel Waveform Relaxation of Circuits with Global Feedback Loops
Performance-driven analog placement considering boundary constraint
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement
An IC manufacturing yield model considering intra-die variations
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks
Virtual memory window for application-specific reconfigurable coprocessors
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization
Beyond verification: leveraging formal for debugging
Design for low test pattern counts
Object Databases in Electronic Design: Implementation Experiences (Panel Abstract)
A solution to line-routing problems on the continuous plane
An integrated algorithm for 3D-IC TSV assignment
Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations
BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning
Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
Incorporating Speculative Execution in Exact Control-Dependent Scheduling
Distributed computation for design aids
Delving into Topology Representation for Layout Pattern: A Novel Contrastive Learning Framework for Hotspot Detection
Emerging markets: design goes global
A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints
Cognitive computing with spin-based neural networks
GEM: GPU-Accelerated Emulator-Inspired RTL Simulation
GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
Representing Circuits More Efficiently in Symbolic Model Checking
Solving difficult SAT instances in the presence of symmetry
Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic
Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures
Scalable crash consistency for secure persistent memory
A Deterministic Approach to Adjacency Testing for Delay Faults
Improving Voltage Assignment by Outlier Detection and Incremental Placement
An MOS digital network model on a modified thevenin equivalent for logic simulation
Library-aware resonant clock synthesis (LARCS)
A module interface specification language
Internet-in-a-Box: emulating datacenter network architectures using FPGAs
RED: Resistance Extraction for Digital Simulation
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs
A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design
Power management and delivery for high-performance microprocessors
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Global Routing Considerations in a Cell Synthesis System
Comparative Design Validation Based on Event Pattern Mappings
Spectral techniques for high-resolution thermal characterization with limited sensor data
Querying Part Hierarchies: A Knowledge-Based Approach
ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided Relocating
Fast falsification based on symbolic bounded property checking
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC
A Topological Search Algorithm for ATPG
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning
Late Breaking Results: A Diffusion-Based Framework for Configurable and Realistic Multi-Storage Trace Generation
Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models
Operational aspects of design automation for the IBM 3081
A quantitative assessment of IBM's programming productivity techniques
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors
On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations
Fast and Efficient Information Transmission with Burst Spikes in Deep Spiking Neural Networks
Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect
Verification of Non-Mainline Functions in Todays Processor Chips
A fault-tolerant NoC scheme using bidirectional channel
Fine-grained I/O access control based on Xen virtualization for 3G/4G mobile devices
LEAF: An Adaptation Framework against Noisy Data on Edge through Ultra Low-Cost Training
SLS - a fast switch level simulator for verification and fault coverage analysis
An efficient channel router
A frame based system for representing knowledge about VLSI design: a proposal
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme
The System Architect's Workbench
Statistical analysis of SRAM cell stability
VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency
Stochastic modeling of a thermally-managed multi-core system
EMGraph: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnect Using Graph Convolution Networks
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design
The MIMOLA design system: Detailed description of the software system
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Single-electron devices for ubiquitous and secure computing applications
GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-centric Rasterization
CoCo: a hardware/software platform for rapid prototyping of code compression technologies
Layout optimization and template pattern verification for directed self-assembly (DSA)
A checking method of wiring
Behavior-level yield enhancement approach for large-scaled analog circuits
Instruction cache locking using temporal reuse profile
LearnGraph: A Learning-Based Architecture for Dynamic Graph Processing
ANN Based Admission Control for On-Chip Networks
Efficient ILT via Multi-level Lithography Simulation
Matching-based minimum-cost spare cell selection for design changes
UCAD: Building Design Automation with general purpose software tools on UNIX
Timing Analysis in Precharge/Unate Networks
Characterization and Applications of Spatial Variation Models for Silicon Microring-Based Optical Transceivers
A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS
Fault Simulation in a Distributed Environment
The genealogical approach to the layout problem
New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals
Compiler-driven register re-assignment for register file power-density and temperature reduction
Safe DNN-type Controller Synthesis for Nonlinear Systems via Meta Reinforcement Learning
ANAS: Asynchronous Neuromorphic Hardware Architecture Search Based on a System-Level Simulator
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC
MAHA: a program for datapath synthesis
Efficient detection and exploitation of infeasible paths for software timing analysis
Full-chip analysis of leakage power under process variations, including spatial correlations
CHOP: A Constraint-Driven System-Level Partitioner
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s Workload
3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM Inference
PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table
Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction
Testability of Asynchronous Timed Control Circuits with Delay Assumptions
DRAW3D: Time sharing graphic interaction using a device-space buffer
Process-level virtualization for runtime adaptation of embedded software
HV/VH Trees: A New Spatial Data Structure for Fast Region Queries
ElasticZRAM: Revisiting ZRAM for Swapping on Mobile Devices
Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation
Design and Implementation of a Dynamic Component Model for Federated AUTOSAR Systems
Standard cell library optimization for leakage reduction
A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control
Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer Partition
60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
CASS: Computer aided schematic system
SLIM-the translation of symbolic layouts into mask data
Reverse-Engineering Deep Neural Networks Using Floating-Point Timing Side-Channels
Tropical: Enhancing SLO Attainment in Disaggregated LLM Serving via SLO-Aware Multiplexing
Timing ECO optimization using metal-configurable gate-array spare cells
An Algorithm for Incremental Timing Analysis
Mode grouping for more effective generalized scheduling of dynamic dataflow applications
Temporal isolation on multiprocessing architectures
PAS-LOP: An automatic module location system for PWB
Integrated biosensors for personalized medicine
ADEPT: automatic differentiable DEsign of photonic tensor cores
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator
Error Bounded Padé Approximation via Bilinear Conformal Transformation
A Human Machine Interface for Silicon Compilation
Efficient Testing of Clock Regenerator Circuits in Scan Designs
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
A vertically organized computer-aided design data base
Power Macromodeling for High Level Power Estimation
Early verification of prototype tooling for IC designs (tutorial)
Test Volume and Application Time Reduction Through Scan Chain Concealment
Programmers workbench, unix and documentation
CFTCG: Test Case Generation for Simulink Model through Code Based Fuzzing
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring
Thick film substrate (Micropackage) design utilizing interactive Computer Aided Design systems
Power-aware issue queue design for speculative instructions
RLAlloc: A Deep Reinforcement Learning-Assisted Resource Allocation Framework for Enhanced Both I/O Throughput and QoS Performance of Multi-Streamed SSDs
Design verification of large scientific computers
A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD
Detection of static and dynamic hazards in logic nets
Benchmarks for Cell-Based Layout Systems
Exploiting shared scratch pad memory space in embedded multiprocessor systems
Efficient Transient Simulation of Lossy Interconnect
High-level design methods for hardware security: is it the right choice? invited
Zero Skew Clock Net Routing
DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications
ABNN 2 : secure two-party arbitrary-bitwidth quantized neural network predictions
Designing robust microarchitectures
Auxiliary Variables for Extending Symbolic Traversal Techniques to Data Paths
Teaching Future Verification Engineers: The Forgotten Side of Logic Design
Statistical characterization of standard cells using design of experiments with response surface modeling
On-chip inductance modeling and analysis
The role of cascade, a cycle-based simulation infrastructure, in designing the anton special-purpose supercomputers
Concept communications with design automation systems
Estimation of Safe Sensor Measurements of Autonomous System Under Attack
An automatic routing system for high density multilayer printed wiring boards
Multi-profile based code compression
An adaptive window-based susceptance extraction and its efficient implementation
Efficient access scheme for multi-bank based NTT architecture through conflict graph
DL2Fence: Integrating Deep Learning and Frame Fusion for Enhanced Detection and Localization of Refined Denial-of-Service in Large-Scale NoCs
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results
EDA in flux: should I stay or should I go?
3D-Carbon: An Analytical Carbon Modeling Tool for 3D and 2.5D Integrated Circuits
Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs
PASK: Cold Start Mitigation for Inference with Proactive and Selective Kernel Loading on GPUs
RISO: relaxed network-on-chip isolation for cloud processors
Automatic application-specific instruction-set extensions under microarchitectural constraints
A design automation system for electronic switching systems
Programming models and HW-SW interfaces abstraction for multi-processor SoC
DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification
Revisiting accelerator-rich CMPs: challenges and solutions
A PulseWidth-IN-PulseWidth-Out Universal Nonlinear Processing Element for Time-Domain In-Memory Computing Systems
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation
Three levels of the wiring interconnection problem
Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration
Stochastic circuits for real-time image-processing applications
An algorithm for modeling saturating magnetic devices
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks
Star's envoling design environment: a user's perspective on CAE
Critical path tracing - an alternative to fault simulation
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures
Optimal procrastinating voltage scheduling for hard real-time systems
NVR: Vector Runahead on NPUs for Sparse Memory Access
"ACCEL" automated circuit card etching layout
NovelRewrite: node-level parallel AIG rewriting
A Lightweight Isolation Mechanism for Secure Branch Predictors
Digital control simulation system
Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU Computation
An object-oriented visual simulator for microprogram development
Predicting DRC Violations Using Ensemble Random Forest Algorithm
Effective Quantum Resource Optimization via Circuit Resizing in BQSKit
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance
The Making of VIVID: A Software Engineering Perspective
Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors
Symbolic simulation for correct machine design
Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure
Layout Driven Re-synthesis for Low Power Consumption LSIs
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling
Design methodology for wireless nodes with printed antennas
An interactive routing program with On-line clean-up of sketched routes
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing
TraiNDSim: A Simulation Framework for Comprehensive Performance Evaluation of Neuromorphic Devices for On-Chip Training
ALPS2: a standard cell layout system for double-layer metal technology
Memory-Bound Proof-of-Work Acceleration for Blockchain Applications
SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation
Fast nonlinear model order reduction via associated transforms of high-order volterra transfer functions
EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components
A new method for verifying sequential circuits
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time
Operator-based model-order reduction of linear periodically time-varying systems
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification
Understanding the impact of power loss on flash memory
Can C.A.D. meet the VLSI design problems of the 80's?(Panel Discussion)
inGRASS: Incremental Graph Spectral Sparsification via Low-Resistance-Diameter Decomposition
Behavior and communication co-optimization for systems with sequential communication media
An interactive man-machine approach to the computer logic partitioning problem
UpDLRM: Accelerating Personalized Recommendation using Real-World PIM Architecture
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch
Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution
Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming
A data structure for interactive placement of rectangular objects
The Silc silicon compiler: language and features
Solving the State Assignment Problem for Signal Transition Graphs
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches
FARM: An Efficient Feed-Through Pin Assignment Algorithm
Jump test for metallic CNTs in CNFET-based SRAM
Logic Verification Methodology for PowerPC Microprocessors
A Preliminary Investigation into Parallel Routing on a Hypercube Computer
Design-Flow and Synthesis for ASICs: A Case Study
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study
Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices
Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator
Hardware/Software Instruction Set Configurability for System-on-Chip Processors
Formal verification of iterative algorithms in microprocessors
A dogleg "optimal" channel router with completion enhancements
Gridless pin access in detailed routing
Parameterized Schematics
Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data
Designing fault tolerant systems into SRAM-based FPGAs
Fast Algorithm for Optimal Layer Assignment
A system for solution of the placement problem
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
Late Breaking Results: Less Sense Makes More Sense: In-Sensor Compressive Learning for Efficient Machine Vision
The VHSIC hardware description language (VHDL) program
Complexity and the challenges of securing SoCs
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications
Circuit recognition and verification based on layout information
Defending Bit-Flip Attack through DNN Weight Reconstruction
Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing
Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited
Electron beam lithography
Coping with buffer delay change due to power and ground noise
A Post-Implementation Performance Prediction Method with HLS Optimization Directives
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip
Fast identification of operating current for toggle MRAM by spiral search
Routability of a Rubber-Band Sketch
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Enhancing FPGA Performance for Arithmetic Circuits
When IC yield missed the target, who is at fault?
Techniques for energy-efficient power budgeting in data centers
CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error Correction
HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design
CEDIF: A Data Driven EDIF Reader
Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions
INVITED: Efficient Synthesis of Compact Deep Neural Networks
A min-cut placement algorithm for general cell assemblies based on a graph representation
A Graph Compaction Approach to Fault Simulation
NONLISA: Nonlinear network simulation and analysis program
A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs
A modular digital VLSI flow for high-productivity SoC design
S2RAM PUF: An Ultra-low Power Subthreshold SRAM PUF with Zero Bit Error Rate
Invited: End-to-End Secure SoC Lifecycle Management
VeriTrust: verification for hardware trust
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited
System design for DSP applications in transaction level modeling paradigm
Circuit Simulation on the Connection Machine
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels
Application/architecture power co-optimization for embedded systems powered by renewable sources
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation
Crosstalk noise in FPGAs
Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement
Automatic bus planner for dense PCBs
A flexible and scalable methodology for GHz-speed structural test
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
Importance of device independence to the CADCAM industry
A Computer Aided System (CAS) for the design, manufacture, test, and documentation of digital Printed Circuit Boards
Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement
Translation of an existing VMM-based SystemVerilog testbench to OVM
A VLSI FSM design system
Double patterning lithography aware gridless detailed routing with innovative conflict graph
SAT sweeping with local observability don't-cares
A Static Estimation Technique of Power Sensitivity in Logic Circuits
Development of a timing analysis program for multiple clocked network
TROY: Track Router with Yield-driven Wire Planning
FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing
SMORE: Similarity-Based Hyperdimensional Domain Adaptation for Multi-Sensor Time Series Classification
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation
An approach to computerized space planning using graph theory
An efficient passivity test for descriptor systems via canonical projector techniques
Post-Silicon Validation of the IBM POWER8 Processor
System-level hardware failure prediction using deep learning
Secure Memristor-based Main Memory
A frequency relaxation approach for analog/RF system-level simulation
An integrated mask artwork analysis system
Dynamic vehicle software with AUTOCONT
HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUs
High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives
An algorithm for building rectangular floor-plans
A solution to closeness checking of non-orthogonal printed circuit board wiring
How to develop module logic using pseudo-code and stepwise refinement
FADIC: Architectural Synthesis applied in IC Design