yusuke1997/dblp-id-title huggingface dataset:
Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode-Based Array
Over-the-Cell Routing Algorithms for Industrial Cell Models
Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
Bridging Fault Detections for Testable Realizations of Logic Functions
VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy
LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore
Techniques for On-Chip Process Voltage and Temperature Detection and Compensation
An Efficient Neural Network Controller for Autonomous Lane-Keeping Assist System
Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate
31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018
Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy
Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm
On NBTI Degradation Process in Digital Logic Circuits
A Robust Level-Shifter Design for Adaptive Voltage Scaling
WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits
SCENIC: An Area and Energy-Efficient CNN-based Hardware Accelerator for Discernable Classification of Brain Pathologies using MRI
Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients
Floorplan Classification Algorithms
Configurable Systolic Matrix Multiplication
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding
The Effect of Built-In Current Sensors (BICS) on Operational and Test Performance
Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs
An Automated Tool for Implementing Deep Neural Networks on FPGA
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases
Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases
An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function
ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors
Improved-Quality Real-Time Stereo Vision Processor
An Approach to Tolerate Process Related Variations in Memristor-Based Applications
Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier
A Feed-Forward Equalizer for Capacitively Coupled On-Chip Interconnect
E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories
A 1.8 - 6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOS
Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique
A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer
Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI
Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview
Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories
A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator
Efficient Analog/RF Layout Closure with Compaction Based Legalization
A High Performance and Low Power Subthreshold Voltage Level Shifter Design
Ant Colony Optimization Technique for Macrocell Overlap Removal
From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits
Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation
TECHMIG: A Layout Tool for Technology Migration
A general graph theoretic framework for multi-layer channel routing
Long Short Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring
Lightweight Forth Programmable NoCs
A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection
Timed Circuit Synthesis Using Implicit Methods
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
CPM Pole-Zero Computation Using The Generalized Eigenproblem Approach
Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel
Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine
Synthesizing Performance-Aware (m, k)-Firm Control Execution Patterns Under Dropped Samples
Enhancing the Phase-Noise-Figure-of-Merit of a Resonator using Frequency Transformations
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits
Customization of Register File Banking Architecture for Low Power
A New Approach to Synthesis of PLA-Based FSM's
Cost Trade-Offs in System On Chip Designs
A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit
Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education
Exploration of Loop Unroll Factors in High Level Synthesis
Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs
Architecting Microprocessor Components in 3D Design Space
Enhancing Reliability and Energy Efficiency in Network-on-Chip Architectures through Hybrid Sorting Algorithm-Based Core Mapping
True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET
Robust System Design
Atrial Flutter Detection System by AdEx Encoded Lead-II ECG
Maximum Power Point Tracking using Buck-Boost converter for EH-PMIC
Synthesis of High Performance Low Power Dynamic CMOS Circuits
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits
Hard versus Soft Software Defined Radio
Watermarking Video Clips with Workload Information for DVS
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters
Application Specific Datapath Extension with Distributed I/O Functional Units
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs
Wide Limited Switch Dynamic Logic Circuit Implementations
Maximizing Wafer Productivity Through Layout Optimization
Efficient Implementation of Floating-Point Reciprocator on FPGA
Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma Architecture
A Code Transition Delay Model for ADC Test
A 1 V, Sub-mW CMOS LNA for Low-Power 1 GHz Wide-Band Wireless Applications
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses
Efficient Post-Silicon Validation of Network-on-Chip Using Wireless Links
Embedded Tutorial ET4: Advanced Techniques for Programming Networked Embedded Systems
NBTI Degradation: A Problem or a Scare?
A Low Phase Noise 30 GHz Oscillator Topology for Resonant-Fin-Transistors Based High-Q On-chip Resonators in 14 nm Technology
Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic Panel
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs
A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM
Efficient Quantum Circuits for Square-Root and Inverse Square-Root
A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan
Variable Resizing for Area Improvement in Behavioral Synthesis
An Energy Efficient Oscillator Frequency Calibration Methodology Using Fraction Phase Computation
ESD protection for the deep sub micron regime - a challenge for design methodology
Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults
On Determining Symmetries in Inputs of Logic Circuits
Scaling the UVM_REG Model towards Automation and Simplicity of Use
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis
Approximate Adders for Deep Neural Network Accelerators
Tutorial T7A: Advanced IC Packaging
Beyond RTL: Advanced Digital System Design
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS
Design of Multi-bit SET Adder and Its Fault Simulation
A Parallel Architecture for Video Compression
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation
Trace Buffer-Based Silicon Debug with Lossless Compression
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies
Live & Seamless Firmware Upgrade in Real Time Control Systems
A 0.75mm 2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices
Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy
A New Methodology for the Design of Asynchronous Digital Circuits
CVD-diamond substrates for multi-chip modules (MCMs)
State-Machine Based Logic Simulation Using Three Logic Values
Defect Aware to Power Conscious Tests - The New DFT Landscape
Design of 3D Antennas for 24 GHz ISM Band Applications
A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories
On-Chip Voltage Regulator with Improved Transient Response
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
VLSI Design 2011: 24th International Conference on VLSI Design, IIT Madras, Chennai, India, 2-7 January 2011
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors
Mirroring Silicon Behaviour in ASIC models- The Issues Involved
Dynamic Trace Signal Selection for Post-Silicon Validation
Energy-efficient and Secure Sensor Data Transmission Using Encompression
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches
Architecture Implementation Using the Machine Description Language LISA
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs
Synthesis of Reversible Circuits Using Heuristic Search Method
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic
A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
Design of Synchronous Action Systems
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor
Challenges in the Design of Embedded Real-time DSP SoCs
System Efficiency Improvement Technique for Automotive Power Management IC Using Maximum Load Current Selector Circuit
Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit
18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India
Digital Imaging with Wireless Data Services
TIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Intersection Cameras
Multi-way partitioning of VLSI circuits
Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams
VLSI Design 2005 Conference Awards
T6: C++/java(Tm)/unix
All Optical Reversible Multiplexer Design Using Mach-Zehnder Interferometer
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules
N-Well Patterning of P-Type CMOS Substrate for Improving Quality Factor of on-Chip Inductors at Millimeter Wave Frequencies
Optimal Clock Period for Synthesized Data Paths
Single Event Upset: An Embedded Tutorial
Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis
A differential built-in current sensor design for high speed IDDQ testing
Multiple Faults: Modeling, Simulation and Test
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis
Invited Talk: Quantum Computation
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator
Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25µm CMOS
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems
FAAR: A Router for Field-Programmable Analog Arrays
Design for Manufacturability and Reliability in Nano Era
A Model of Spurs for Delta-Sigma Fractional PLLs
A "Stitch" in Time: Accurate Timekeeping with On-Chip Compensation
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Quantitative Model for Thermal Behaviour of an Analog Integrated Circuit
On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits
Area & Power Efficient 3.4Gbps/Channel HDMI Transmitter with Single-Ended Structure
Leakage Reduction techniques in a 0.13um SRAM Cell
Model Checking Controllers with Predicate Inputs
On-chip RF to DC Power Converter for Bio-Medical Applications
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies
Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency
Double-Gate SOI Devices for Low-Power and High-Performance Applications
A Power Management Methodology for High-Level Synthesis
A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation
Physics Based Fault Models for Testing High-Voltage LDMOS
Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF energy Harvester
Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits
VLSI Signal Processing in FPGAs
Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops
100KHz-20MHz Programmable Subthreshold G m -C Low-Pass Filter in 0.18µ-m CMOS
A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS
Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols
Intra-Bus Crosstalk Estimation Using Word-Level Statistics
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms
Multiphase Technique to Speed-up Delay Measurement via Sub-sampling
Efficient Simulation for Hierarchical and Partitioned Circuits
Hardware Trojan Detection by Stimulating Transitions in Rare Nets
Stealthy SWAPs: Adversarial SWAP Injection in Multi-Tenant Quantum Computing
High-Speed Optoelectronics Receivers in SiGe
Analysis and Design of Low Phase Noise 20 GHz VCO for Frequency Modulated Continuous Wave Chirp Synthesizers in mmWave Radars
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders
Trojan Localization Using Information Flow Tracking Properties in SoC Designs
A Novel Modeling-Attack Resilient Arbiter-PUF Design
Standards in EDA: An Introduction
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration
Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy
Stall Power Reduction in Pipelined Architecture Processors
Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination
An Upper Bound for 3D Slicing Floorplans
Computing and Communication in the New Millennium
Fully asynchronous, robust, high-throughput arithmetic structures
-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI
Modified Stability Checking for On-line Error Detection
VLSI Architecture of Centroid Tracking Algorithms for Video Tracker
A 44 GHz Quadrature Traveling Wave Oscillator
A Novel AI Based Approach for Performance validation
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
Thermal Extension of the Total Bandwidth Server
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths
Impact of NBTI on FPGAs
A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk Process
Sneak-path Testing of Memristor-based Memories
Common Power Format: A User-driven Ecosystem For Proven Low Power Design Flows
In Situ Latency Monitoring for Heterogeneous Real-Time Systems
Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer Architecture
Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs
An NMOS Low Drop-out Voltage Regulator with -17dB Wide-Band Power Supply Rejection for SerDes in 22FDX
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
Formal Verification of Hardware / Software Power Management Strategies
Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor
An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm
SMT-based Control Safety Property Checking in Cyber-Physical Systems under Timing Uncertainties
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
Digital Design: The components of a new paradigm
The Design of Analog Self-Checking Circuits
Synthesis for Testability by Two-Clock Control
SAT-Based Test Pattern Generation with Improved Dynamic Compaction
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation
Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis
Equivalence Checking of Non-Binary Combinational Netlists
Identifying Redundant Path Delay Faults in Sequential Circuits
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network
A Novel Sustained Vector Technique for the Detection of Hardware Trojans
DFM, DFT, Silicon Debug and Diagnosis - The Loop to Ensure Product Yield
Robust Estimation of FPGA Resources and Performance from CNN Models
True Random Number Generator based on Voltage-Gated Spintronic structure
Low-Power Design by Hazard Filtering
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor
Benchmarking Array Comparators
Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems
Energy Profiler for Hardware/Software Co-Design
Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications
Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation Control
On Full Reset as a Design-For-Testability Technique
FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability
Constraint Allocation in Analog System Synthesis
Superscalar Processor Validation at the Microarchitecture Level
A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs
Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination
Symbolic Analysis of Analog Integrated Circuits
Single Error Correcting Finite Field Multipliers Over GF(2m)
Design for Verification with SystemVerilog
MIPS-Driven Early Design and Analysis of VLSI CPU Chips
Design and Analysis of Power Distribution Networks with Accurate RLC Models
A Genetic Algorithm for the Synthesis of Structured Data Paths
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process
Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects
CMOS Integrated Circuit for Sensing Applications
32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019
A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer
Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming
A 0.27-THz Frequency Multiplier Chain Using Harmonic Mixing with Multiplication of × 18 in 65-nm CMOS
A Wide Range CMOS VCO for PLL Applications
A Reconfigurable Arithmetic Processor
Symptomatic Bug Localization for Functional Debug of Hardware Designs
A New Genetic Algorithm for the Channel Routing Problem
A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
2014 27th International Conference on VLSI Design, VLSID 2014, and 2014 13th International Conference on Embedded Systems, Mumbai, India, January 5-9, 2014
A Highly Stable Leakage-Based Silicon Physical Unclonable Functions
Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic
Extending STL BASOPs Used in 3GPP Codecs to Leverage Features of Modern DSP Architectures
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers
Estimating Crosstalk From Vlsi Layouts
DNA-CIM: DNA Sequence Analysis Using RRAM-Based Compute In-Memory Accelerator
An Object-Oriented Concept for Intelligent Library Functions
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis
Mapping of Boolean Logic Functions onto 3D Memristor Crossbar
Process Synchronization in Multi-core Systems Using On-Chip Memories
Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width Configurability
A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching
Representation and Synthesis of Interface of a Circuit for its Reuse
Fault Tolerance through Invariant Checking for Iterative Solvers
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits
VLSI Design Conference History
Exploiting Hybrid Analysis in Solving Electrical Networks
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications
Verification of an Industrial CC-NUMA Server
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware
A Low Noise Current-mode Readout circuit for CMOS Image Sensing Applications
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Hardware Software Partitioning Using Genetic Algorithm
Preventing Crosstalk Delay using Fibonacci Representation
NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal Simulator
Power Supply Efficiency Aware Server Allocation in Data Centers
Sequential Multi-Valued Network Simplification using Redundancy Removal
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Analog Processing Based Equalizer for 40 Gbps Coherent Optical Links in 90 nm CMOS