yusuke1997/dblp-id-title huggingface dataset:
Iterative floating point computation using FPGA DSP blocks
A Steerable Complex Wavelet Construction and Its Implementation on FPGA
FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor
High Performance Stereo Computation Architecture
Fast toggle rate computation for FPGA circuits
CAD System for ASM and FSM Synthesis
Self-Test and Adaptation for Random Variations in Reliability
Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata
Fault tolerant methods for reliability in FPGAs
HAGAR: Efficient Multi-context Graph Processors
Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry
Optimized Field Programmable Gate Array Based Function Evaluation
A DSL-Based FFT Hardware Generator in Scala
Parallel Graph colouring using FPGAs
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms
Distributed Recommendation Inference on FPGA Clusters
Design of a VME Parametrized Library for FPGAs
RISC-V FPGA Platform Toward ROS-Based Robotics Application
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput
Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine
Sum of Absolute Difference Implementations for Image Processing on FPGAs
A New Arithmetic Unit in GF(2 m ) for Reconfigurable Hardware Implementation
A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems
Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip
On the Reliability Evaluation of SRAM-Based FPGA Designs
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
Submicrosecond Latency Video Compression in a Low-End FPGA-based System-on-Chip
Minimum Sum of Absolute Differences Implementation in a Single FPGA Device
A novel microprocessor-intrinsic Physical Unclonable Function
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design
Efficient Metacomputation Using Self-Reconfiguration
OpenSoC system architect: An open toolkit for building soft-cores on FPGAs
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPGA Implementations of the Round Two SHA-3 Candidates
Partial Run-Time Reconfiguration Using JRTR
An Emulation of Quantum Error-Correction on an FPGA device
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs
Convolutional Error Decoding with FPGAs
Power Optimization Techniques for SRAM-Based FPGAs
Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs
A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation
A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory
Optimized Mappings for Symmetric Range-Limited Molecular Force Calculations on FPGAs
FPGA acceleration of spark applications in a Pynq cluster
Rothko: A three dimensional FPGA architecture, its fabrication, and design tools
Searching for ET with FPGA'S
Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
Comparison of hardware and software implementations of selected lightweight block ciphers
On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware
Remote FPGA Lab with Interactive Control and Visualisation Interface
Monte Carlo Logarithmic Number System for Model Predictive Control
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow
Reconfigurable many-cores with lean interconnect
File system access from reconfigurable FPGA hardware processes in BORPH
Metastability Characteristics Testing for Programmable Logic Design
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs
Cycle-Accurate and Cycle-Reproducible Debugging of Embedded Designs Using Artificial Intelligence
Versatile Imaging Architecture Based on a System on Chip
A Reprogrammable Processor for Fractal Image Compression
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
Prototyping New ILP Architectures Using FPGAs
A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM)
A Whole New World: How to Architect Beyond-FPGA Reconfigurable Acceleration Devices?
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGAs
34th International Conference on Field-Programmable Logic and Applications, FPL 2024, Torino, Italy, September 2-6, 2024
Binary Synthesis with multiple memory banks targeting array references
Challenges Using FPGA Clusters for Distributed CNN Training
Advanced Multithreading Architecture with Hardware Based Scheduling
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
Pipelined NoC router architecture design with buffer configuration exploration on FPGA
ITester: A FPGA based high performance traffic replay tool
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms
In-field vulnerability analysis of hardware-accelerated computer vision applications
Fast dynamically updatable packet classifier on FPGA
Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration
Fine grain reconfigurable architectures
Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems
Using high-level knowledge to enhance data channels in FPGA streaming systems
A New FPGA Technology Mapping Approach by Cluster Merging
Bio-inspiration helps computers: A new machine
Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing
Accelerating DTP with Reconfigurable Computing Engines
Using System Generator to Design a Reconfigurable Video Encryption System
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
Toward Uniform Approach to Design of Evolvable Hardware Based Systems
Memory Synthesis for FPGA-Based Reconfigurable Computers
A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions
An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time
A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA
32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022
FRA-FPGA: Fast Reconfigurable Automata Processing on FPGAs
Search-based synthesis of approximate circuits implemented into FPGAs
Breaking an FPGA-Integrated NIST SP 800-193 Compliant TRNG Hard-IP Core with On-Chip Voltage-Based Fault Attacks
Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA
Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools
Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA
Resource Reduction of BFGS Quasi-Newton Implementation on FPGA Using Fixed-Point Matrix Updating
Hierarchical Placement for Large-scale FPAA
Educational Programmable Hardware Prototyping and Verification System
Stimulation board for automated verification of touchscreen-based devices
Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices
Application Specific Small-Scale Reconfigurability
31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021
Mapping Loops onto Reconfigurable Architectures
Design and Implementation of an XC6216 FPGA Model in Verilog
Timing driven RTL-to-RTL partitioner for multi-FPGA systems
An Environment for Exploring Data-Driven Architectures
Asynchronously assisted FPGA for variability
A scalable design approach for stencil computation on reconfigurable clusters
Energy-Efficient NoC for Best-Effort Communication
Precise Characterizing of FPGAs in Production Systems
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs
Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs
FISH: Linux system calls for FPGA accelerators
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications
A runtime relocation based workflow for self dynamic reconfigurable systems design
FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure
Technology mapping by binate covering
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware
High Performance True Random Number Generator in Altera Stratix FPLDs
A n-Bit Reconfigurable Scalar Quantiser
Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?
Privacy preserving large scale DNA read-mapping in MapReduce framework using FPGAs
PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems
IP Based Configurable SIMD Massively Parallel SoC
Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications
Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies
Image recognition operation on a dynamically reconfigurable vison architecture
A Specialized Memory Hierarchy for Stream Aggregation
A Software-Programmable Neural Processing Unit for Graph Neural Network Inference on FPGAs
Multiplexer-based routing fabric for reconfigurable logic
Increasing the level of abstraction in FPGA-based designs
Modular Partial Reconfiguration in Virtex FPGAs
Fast and Practical Strassen's Matrix Multiplication using FPGAs
An Automatic Compilation Framework for Configurable Architectures
The Integration of SystemC and Hardware-Assisted Verification
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability
Optimal runtime reconfiguration strategies for systolic arrays
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Dynamic reconfiguration system for real-time video processing
Technology Trends and Adaptive Computing
Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA
Cluster architecture based on low cost reconfigurable hardware
A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms
Investigating Trace Transform Architectures for Face Authentication
Model-based Generation of Hardware/Software Architectures for Robotics Systems
An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method
InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing
FPGA implementation of low-power split-radix FFT processors
Dynamic Specialisation of XC6200 FPGAs by Parial Evaluation
Hardware system synthesis from Domain-Specific Languages
Globally Asynchronous Locally Synchronous FPGA Architectures
Implementation in FPGA of Address-Based Data Sorting
Adaptive MRAM-based CGRAs
PAHLS: Towards Run-Time Synthesis for FPGAs
Pharos: a Multi-FPGA Performance Monitor
Area implications of memory partitioning for high-level synthesis on FPGAs
A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor
The Entropy of FPGA Reconfiguration
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
A Model for Hardware Realization of Kernel Loops
AMA: An Analytical Approach to Maximizing the Efficiency of Deep Learning on Versal AI Engine
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
A SAT-based Timing Driven Place and Route Flow for Critical Soft IP
PAAS: A system level simulator for heterogeneous computing architectures
Spade: An HDL Inspired by Modern Software Languages
The educational processor Sweet-16
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver
Compiling for the Molen Programming Paradigm
Speculative Debug Insertion for FPGAs
NEBULA: A Partially and Dynamically Reconfigurable Architecture
Modular, Fabric-Specific Synthesis for Programmable Architectures
Compiling Ruby into FPGAs
Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA
Compact Buffered Routing Architecture
Virtualizing Hardware with Multi-context Reconfigurable Arrays
FPL Demo: An FPGA-IP Prototype Chip for MEC devices
No-break dynamic defragmentation of reconfigurable devices
TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework
An FPGA Network Architecture for Accelerating 3DES - CBC
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic
Debugging Application-Specific Programmable Products
Design of a novel Quantum-dot Cellular Automata Field Programmable Gate Array
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic
Machine-Learning Based Congestion Estimation for Modern FPGAs
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators
Efficient FPGA-Based Security Kernels
On Availability of Bit-Narrow Operations in General-Purpose Applications
Rapid Application Development on Multi-processor Reconfigurable Systems
Reconfigurable Circuits Using Hybrid Hall Effect Devices
Fast hierarchical NPN classification
Dimensionality reduction of hyperspectral images using reconfigurable hardware
Convergence analysis of run-time distributed optimization on adaptive systems using game theory
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime
Defect-robust FPGA architectures for intellectual property cores in system LSI
A dynamic temperature control simulation system for FPGAs
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System
An efficient many-core architecture for Elliptic Curve Cryptography security assessment
Technology mapping of heterogeneous LUT-based FPGAs
Real Time Morphological Image Contrast Enhancement in Virtex FPGA
TPR: Three-D Place and Route for FPGAs
ERDB: An Embedded Routing Database for Reconfigurable Systems
A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures
High throughput channel tracking for JTRS wireless channel emulation
A Simulation Platform for Reconfigurable Computing Research
FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application
On-chip and Off-chip Real-Time Debugging for Remotely-Accessed Embedded Programmable Systems
Multigigabit network traffic processing
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals
Building a distributed key-value store with FPGA-based microservers
Real Time Optical Flow Processing System
Pipelined compressor tree optimization using integer linear programming
FBNA: A Fully Binarized Neural Network Accelerator
A Better Kyber Butterfly for FPGAs
Compact FPGA implementation of Camellia
Fast Emulation of Permanent Faults in VLSI Systems
A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup
Implementation of Virtual Circuits by Means of the FIPSOC Devices
FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design
Seamless design flow for reconfigurable systems
Efficient processing of phased array radar in sense and avoid application using heterogeneous computing
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
IP Validation for FPGAs Using Hardware Object Technology
Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration
Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems
FPGA-based accelerator design from a domain-specific language
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning
Seeking (the right) Problems for the Solutions of Reconfigurable Computing
Online Routing Fault Detection for Reconfigurable NoC
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
A scalable pipelined architecture for biomimetic vision sensors
Capacitive Boosting for FPGA Interconnection Networks
Reconfigurable Systems Enabled by a Network-on-Chip
Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA
DIME - The First Module Standard for FPGA Based High Performance Computing
Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency
Evaluating FPGA clusters under wide ranges of design parameters
FPGA challenges and opportunities at 40nm and beyond
HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler
A Fast Constant Coefficient Multiplier for the XC6200
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
Fast digital rendering for special effects
High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences
Snow 2.0 IP Core for Trusted Hardware
A scalable, high-performance customized priority queue
Reconfigurable Hardware as Shared Resource in Multipurpose Computers
The SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservices
FPGA-based all-digital Software Defined Radio receiver
FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family
The HercuLeS high-level synthesis environment
Optically Reconfigurable FPGAs: Is this a Future Trend?
Proteus: An architectural synthesis tool based on the stream programming paradigm
FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit
On Tool Integration in High-Performance FPGA Design Flows
Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA
Incremental distributed trigger insertion for efficient FPGA debug
Random numbers generation: Investigation of narrowtransitions suppression on FPGA
A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning
Using C-to-gates to program streaming image processing kernels efficiently on FPGAs
Semi-dense SLAM on an FPGA SoC
XC6200 Fastmap TM Processor Interface
Ambient hardware and the case for transcoding media streams
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization
Compact Spiking Neural Network Implementation in FPGA
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research
Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems
An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration
Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks
Managing the FPGA memory wall: Custom computing or vector processing?
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits
Efficient sum of absolute difference computation on FPGAs
Area/performance evaluation of digit-digit GF(2 K ) multipliers on FPGAS
Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture
HALF: Holistic Auto Machine Learning for FPGAs
Median Filtering with Very Large Windows: SKA Algorithms for FPGAs
Fault detection and avoidance of FPGA in various granularities
Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine
FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems
Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology
Performance Tuning of Iterative Algorithms in Signal Processing
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA
Achieving portability and efficiency over chip heterogeneous multiprocessor systems
Propose of a Hardware Implementation for Fingerprint Systems
Feature dimensionality in CNN acceleration for high-throughput network intrusion detection
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs
Building partial systems with GoAhead
Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining.
REAPR: Reconfigurable engine for automata processing
Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-Chip
CIDPro: Custom Instructions for Dynamic Program Diversification
FPGA-Based Acceleration of Block Matching Motion Estimation Techniques
ParaLaR: A parallel FPGA router based on Lagrangian relaxation
The Bank Nth Chance Replacement Policy for FPGA-Based CAMs
A Distributed Model of Computation for Reconfigurable Devices Based on a Streaming Architecture
FPGA implementation of an interior point method for high-speed model predictive control
High-quality view interpolation based on depth maps and its hardware implementation
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off
Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform
Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor
Integration of Reconfigurable Hardware into System-Level Design
Mixed-architecture process scheduling on tightly coupled reconfigurable computers
Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching
FPGA Modular Multipliers using Hybrid Reduction Techniques
Dynamic Cache Switching in Reconfigurable Embedded Systems
Latency Insensitive Design Styles for FPGAs
Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA
FPGA architecture support for heterogeneous, relocatable partial bitstreams
LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks
A Novel Hardware Accelerator of NeRF Based on Xilinx UltraScale and UltraScale+ FPGA
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function
An FPGA-Based Image Connected Component Labeller
Connected components analysis of streamed images
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
Compilation and Management of Phase-Optimized Reconfigurable Systems
Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
Computing 2-D DFTs Using FPGAs
A Study on the Design of Floating-Point Functions in FPGAs
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems
An efficient FPGA-based hardware framework for natural feature extraction and related Computer Vision tasks
RACE: Reconfigurable and Adaptive Computing Environment
Towards GCC-based automatic soft-core customization
Software Managed Distributed Memories in MPPAs