yusuke1997/dblp-id-title huggingface dataset:
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm
Investigating Simple Low Latency Reliable Multiported Register Files
Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design
Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits
A Secure Design Methodology to Prevent Targeted Trojan Insertion during Fabrication
Synthesis of Analog IC Building Blocks
Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC
A Hardware/Software Co-design Method for Approximate Semi-Supervised K-Means Clustering
Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit
Self-Freeze Linear Decompressors for Low Power Testing
A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd
Adaptive Stackable 3D Cache Architecture for Manycores
Reproducibility in Quantum Computing
Nonvolatile Memory and Computing Using Emerging Ferroelectric Transistors
Two-Dimensional Folding Strategies for Improved Layouts of Cyclic Shifters
How Many Trials Do We Need for Reliable NISQ Computing?
Challenges and Perspectives of Computer Architecture at the Nano Scale
On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery
Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs
Autonomous Design in VLSI: Growing and Learning on Silicon
Fault Diagnosis and Fault Model Aliasing
Embedded systems design for smart system integration
Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic
More Effective Randomly-Designed Microfluidics
Dynamic Exit Selection for Comprehensive and Energy Efficient Gait-Based User Authentication on IoT Devices
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator
Diagnosis of Delay Faults Considering Hazards
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
Minimalistic Perspective to Public Key Implementations on FPGA
Modeling Hardware Trojans in 3D ICs
Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps
Power andPerformance Analysis for Early Design Space Exploration
Test Point Insertion Using Artificial Neural Networks
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications
Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy
Gate Sizing Minimizing Delay and Area
Secure and Scalable Collaborative Edge Computing using Decision Tree
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs
Context-aware Post Routing Redundant Via Insertion
Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs
An Adaptive Lockstep Architecture for Mixed-Criticality Systems
A Hierarchical and Programmable OTA-C Filter
Advancing PUF Security Machine Learning Assisted Modeling Attacks
Towards Future 6G Telecommunications: Research at the THz Domain in Intracom Telecom
High-Average and Guaranteed Performance for Wireless Networks-on-Chip Architectures
Multilevel Modeling Methodology for Reconfigurable Computing Systems Based on Silicon Photonics
SymmTop: A Symmetric Circuit Topology for Ultra Low Power Wide Temperature-Range Applications
A Low-Cost and High-Performance Embedded System Architecture and an Evaluation Methodology
Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS
Embracing Privacy, Robustness, and Efficiency with Trustworthy Federated Learning on Edge Devices
Towards Automated Superconducting Circuit Calibration using Deep Reinforcement Learning
OBO: An Output-by-Output Scoring Algorithm for Fault Diagnosis
Locating Open-Channels in Octagon Networks on Chip-Microprocessors
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
Achieving High-Performance Video Analytics with Lightweight Cores and a Sea of Hardware Accelerators
Space-Saving Layout for Passive Components
Conservatively Analyzing Transient Faults
Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
Design for Embedded Reconfigurable Systems Using MORPHEUS Platform
Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors
System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Incorporating Power Reduction Mechanism in Arithmetic Core Design
A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks
Compact Multiplexer Design with Multi-threshold Ferroelectric FETs
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective
Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier
Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ?S Modulator
Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC
GenStore: In-Storage Filtering of Genomic Data for High-Performance and Energy-Efficient Genome Analysis
Heartbeat Classification with Spiking Neural Networks on the Loihi Neuromorphic Processor
A Scalable Bandwidth-Aware Architecture for Connected Component Labeling
AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier
Frequency Domain Approach for CMOS Ultra-Wideband Radios
Energy Recovering ASIC Design
HEDGY: Heterogeneous Design Management for Multi-Tenant Multi-FPGA Edge Systems
Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking
Robust Perception Architecture Design for Automotive Cyber-Physical Systems
A Quantum Variational Approach to Debugging Combinational Logic Circuits
Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture
On Benchmarking Pin Access for Nanotechnology Standard Cells
Implementation of AES Using NVM Memories Based on Comparison Function
Boost Logic: A High Speed Energy Recovery Circuit Family
"Green" On-chip Inductors in Three-Dimensional Integrated Circuits
Enabling Real-Time Streaming Temporal Convolution Network Inference on Ultra-Low-Power Microcontrollers
Congestion Estimation for 3D Routing
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack
Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving
Oscillatory Neural Networks for Edge AI Computing
RG-SRAM: A Low Gate Leakage Memory Design
On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional Properties
A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs
Voltage Pump Based on Self Clocked Cells
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024, Knoxville, TN, USA, July 1-3, 2024
A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching
A Virtual Channel Network-on-Chip for GT and BE traffic
Hardware Acceleration for Machine Learning
An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL
Accelerating Retiming Under the Coupled-Edge Timing Model
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS
VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display Processing
Analysis of Incremental Communication for Multilayer Neural Networks on a Field Programmable Gate Array
1-D Robust Chaotic Maps Through Systematic Shifting and Halfway Shifted Product
Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices
Verification of Register Transfer Level Low Power Transformations
TQHD: Thermometer Encoding Based Quantization for Hyperdimensional Computing
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz
MOTIM - A Scalable Architecture for Ethernet Switches
Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware
A Novel Marketplace Perspective Promoting Customized Low Energy Computing and IoT: The SMART4ALL Approach
Side Channel Attacks Cryptanalysis against Block Ciphers Based on FPGA Devices
High Level Modeling of Memristive Crossbar Arrays
Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA
Variation Aware Design of Post-Silicon Tunable Clock Buffer
Hybrid Parallel Counters - Domino and Threshold Logic
CmpctArch: A Generic Low Power Architecture for Compact Data Structures in Energy Harvesting Devices
Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications
PUF Interfaces and their Security
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021
Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage
Lossless Compression Using Efficient Encoding of Bitmasks
A Simplified Phase Model for Oscillator Based Computing
SDVM-R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test
BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip
A yield-driven regular layout synthesis
On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project
Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips
Determining the test sources/sinks for NoC TAMs
A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration
Formal Hardware Verification of InfoSec Primitives
VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key Cryptography
Design of A Double-Precision Floating- Point Multiply-Add-Fused Unit with Consideration of Data Dependence
Guiding Template-Induced Design Challenges in DSA-MP Lithography
Application of Formal Methods for System-Level Verification of Network on Chip
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise
Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB
Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder
When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design
Communication-Aware Module Placement for Power Reduction in Large FPGA Designs
High Speed Power Efficient Carry Select Adder Design
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects
Identification of IP Control Units by State Encoding
Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression
Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language Processing
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
An Efficient Test Vector Ordering Method for Low Power Testing
Compilation Accelerator on Silicon
MRAM-on-FDSOI Integration: A Bit-Cell Perspective
Reliability-Aware Dynamic Voltage and Frequency Scaling
Fall-Sense: An Enhanced Sensor System to Predict and Detect Elderly Falls using IoMT
Hardware Optimized Approximate Adder with Normal Error Distribution
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance
Leveraging Compiler Support on VLIW Processors for Efficient Power Gating
Exact Mapping of Quantum Circuit Partitions to Building Blocks of the SAQIP Architecture
Behavioral model of integrated qubit gates for quantum reversible logic design
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction
Efficient Federated Learning Through Distributed Model Pruning
Scalable Superconductor Ising Machine for Combinatorial Optimization Problems
BTB Access Filtering: A Low Energy and High Performance Design
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate Quantization
Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications
A Low Power Lookup Technique for Multi-Hashing Network Applications
Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array
Power Analysis of Rotary Clock
A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion
Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM
Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations
Mitigation of Tampering Attacks for MR-Based Thermal Sensing in Optical NoCs
Iterative remapping respecting timing constraints
Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders
Multi-GHz Zeptojoule Computing Using Emerging Adiabatic Superconductor Circuits
Design of Quantum Circuits for Cryptanalysis and Image Processing Applications
Formal Temporal Characterization of Register Vulnerability in Digital Circuits
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects
Adaptive Filter Design Using Stochastic Circuits
Ultra Low Power Circuit Design Using Tunnel FETs
Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems
Bitstream Efficiency of Field Programmable One-Hot Arrays
NoC Power Estimation at the RTL Abstraction Level
GAAMP: Automatic Thread Count/Affinity and DVFS Tuning for Asymmetric Multicores
Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture
High Performance Array Processor for Video Decoding
A 375 nA Input Off Current Schmitt Triger LDO for Energy Harvesting IoT Sensors
Overdrive Power-Gating Techniques for Total Power Minimization
Multi-Output Timed Shannon Circuits
Predicting Stress in Older Adults with RNN and LSTM from Time Series Sensor Data and Cortisol
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory
An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division
Efficient Logic Evaluation Using RRAM-Based In-Memory Computing
System Design Approach To Power Aware Mobile Computers
Efficacious Qubit Mappings for Quantum Simulations of the 12 C Rotational Band
Harnessing the Effects of Process Variability to Mitigate Aging in Cloud Servers
Post-Synthesis Circuit Techniques for Runtime Leakage Reduction
Efficient Hardware Looping Units for FPGAs
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs
Architectures for Simultaneous Coding and Encryption Using Chaotic Maps
FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs
MINLP Based Power Optimization for Pipelined ADC
Design of a MCML Gate Library Applying Multiobjective Optimization
Towards Efficient On-Board Deployment of DNNs on Intelligent Autonomous Systems
Voltage Noise Analysis with Ring Oscillator Clocks
PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison
High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam
Delay Analysis for an N-Input Current Mode Threshold Logic Gate
HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications
Borrow Select Subtractor for Low Power and Area Efficiency
Impact of Autocorrelation on Stochastic Circuit Accuracy
Design and Analysis of an Electronically Tunable VDTA-Based Quadrature Oscillator
Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)
Automated Generation of Dual Rail Adiabatic Gates from Binary Decision Diagrams
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit
Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology
All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex
Dynamic Power Management on LDPC Decoders
Verification of Scheduling in High-level Synthesis
CAPSL: The Component Authentication Process for Sandboxed Layouts
A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test Set
A Framework for Security on NoC Technologies
An Extensible Evaluation Platform for FPGA Bitstream Obfuscation Security
Lightweight ASIC Implementation of AEGIS-128
A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow
Sustainable AI in the Cloud-to-Thing Continuum: A Bibliometric Review on Lightweight, Small-Sample, and Federated Learning Approaches
A Low-Complexity XOR-Based BCH Decoder for PAM4 Modulation Systems
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs
QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
FSMD Partitioning for Low Power Using ILP
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits
Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor
A Low-Cost Conflict-Free NoC Architecture for Heterogeneous Multicore Systems
The DRACON Embedded Many-Core: Hardware-Enhanced Run-Time Management Using a Network of Dedicated Control Nodes
A Reconfigurable Layered-Based Bio-Inspired Smart Image Sensor
Random Characterization of Design Automation Algorithms
MOHSKM: Meta-Heuristic Optimization Driven Hardware-Efficient Heterogeneous-Split Karatsuba Multipliers for Large-Bit Operations
Differential Power Analysis of CAST-128
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle
Using Statistical Models to Improve the Reliability of Delay-Based PUFs
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform
HELP: Highly Efficient and Low-Latency Hardware Accelerator for Integer Polynomial Multiplication
HO-FPIA: High-Order Field-Programmable Ising Arrays with In-Memory Computing
Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs
Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub Perspective
Automated Synthesis of Standard Cells using Genetic Algorithms
A Permutation Challenge Input Interface for Arbiter PUF Variants Against Machine Learning Attacks
Towards Quantum-Resistant Security: Pre-Silicon Power Side-Channel Leakage Analysis of CRYSTALS-Kyber
Automated Flag Qubit Insertion for Reliable Quantum Circuit Output
Thermal Analysis of Advanced 3D Stacked Systems
Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan
Metal Stack and Partitioning Exploration for Monolithic 3D ICs
Revolutionizing Cyber Security: Exploring the Synergy of Machine Learning and Logical Reasoning for Cyber Threats and Mitigation
Security in Many-Core SoCs Leveraged by Opaque Secure Zones
Fortified-Edge 2.0: Machine Learning based Monitoring and Authentication of PUF-Integrated Secure Edge Data Center
ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies
Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases
A Memory Aware High Level Synthesis Tool
An Improvement in Partial Order Reduction Using Behavioral Analysis
Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function
Defect Tolerance Inspired by Artificial Evolution
ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing
UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM
A Response Surface Method for Design Space Exploration and Optimization of Analog Circuits
A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC
Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering
Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV
A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator
A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°C
Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture
Exploration on Task Scheduling Strategy for CPU-GPU Heterogeneous Computing System
RWT: Suppressing Write-Through Cost When Coherence is Not Needed
Natural Language Processing Meets Hardware Trojan Detection: Automating Security of FPGAs
A Novel Firmware Architecture leveraging Race to Sleep paradigm for Ultra-Low-Power CPS
From Pixels to Reasoning: A Cross-Layer Photonic Design for Edge Visual Intelligence
Nano-PPUF: A Memristor-Based Security Primitive
Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK
A Detailed Routing-Aware Detailed Placement Technique
Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor
A Novel Approach to Quantum Circuit Partitioning
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
SUT-RNS Forward and Reverse Converters
Evaluating Alternative Implementations for LDPC Decoder Check Node Function
Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits Using Independent N2-Transistor Structures
Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach
Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing
Dynamic Early-Exit Convolutional Neural Networks for Edge Vision: The Benefits, The Challenges, and the Road Ahead