yusuke1997/dblp-id-title huggingface dataset:
Design and verification of large-scale computers by using DDL
Internal connection problem in large optimized PLAs
Verification of timing constraints on large digital systems
A logic minimizer for VLSI PLA design
Topological analysis for VLSI circuits
Fast Printed Circuit Board Routing
Challenges in sleep transistor design and implementation in low-power designs
High level cache simulation for heterogeneous multiprocessors
Moore's Law: another casualty of the financial meltdown?
An Analysis of Accelerator Coupling in Heterogeneous Architectures
Timing Verification on a 1.2M-Device Full-Custom CMOS Design
A Unified Approach to Canonical Form-based Boolean Matching
A parametric approach for handling local variation effects in timing analysis
Threadmill: a post-silicon exerciser for multi-threaded processors
Multi-level Logic Simplification Using Don't Cares and Filters
Hybrid modeling of non-stationary process variations
Quixote: Improving Fidelity of Quantum Program by Independent Execution of Controlled Gates
A generalized channel router
CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology
An industrial world channel router for non-rectangular channels
General Purpose Router
NACU: A Non-Linear Arithmetic Unit for Neural Networks
Resistance calculation from mask artwork data by finite element method
Automatic data migration for reducing energy consumption in multi-bank memory systems
AdaptiveFL: Adaptive Heterogeneous Federated Learning for Resource-Constrained AIoT Systems
Power Management Techniques for Control-Flow Intensive Designs
Panel: The Next HDL: If C++ is the Answer, What was the Question?
A generic micro-architectural test plan approach for microprocessor verification
GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning
Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints
Design closure (panel session): hope or hype?
Improving the energy efficiency of hardware-assisted watchpoint systems
Chaff: Engineering an Efficient SAT Solver
Multi-Level Logic Minimization Based on Multi-Signal Implications
A Study in Coverage-Driven Test Generation
QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders
ShuntFlow: An Efficient and Scalable Dataflow Accelerator Architecture for Streaming Applications
Timing-driven placement by grid-warping
A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors
On a general synthesis algorithm of logical circuits using a restricted inventory of integrated circuits
Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits
PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams
Automatic multithreaded pipeline synthesis from transactional datapath specifications
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration
ATPG Based on a Novel Grid-Addressable Latch Element
Process variation tolerant SRAM array for ultra low voltage applications
CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools
Time-Mapped Harmonic Balance
Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems
Lightning Talk: Efficient Embedded Machine Learning Deployment on Edge and IoT Devices
Closing the gap between ASIC and custom: an ASIC perspective
A system of computer programs for efficient test generation for combinational switching circuits
Projection frameworks for model reduction of weakly nonlinear systems
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Fast and accurate parasitic capacitance models for layout-aware
Interactive knitted textile design: A computer tool for designers and manufacturers
A Parallel Pattern Mixed-Level Fault Simulator
Realizing reversible circuits using a new class of quantum gates
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis
Design Management Using Dynamically Defined Flows
A design methodology based upon symbolic layout and integrated cad tools
Exact Memory Size Estimation for Array Computations without Loop Unrolling
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits
Directions to Watch in Design Technology (Tutorial Abstract)
A new algorithm for floorplan design
Panel: Complex System Verification: The Challenge Ahead
Low Power GPGPU Computation with Imprecise Hardware
A Geographically Distributed Framework for Embedded System Design and Validation
Verification of the cell broadband engine TM processor
Automated Micro-Roll-back Self-Recovery Synthesis
Transmission Line Synthesis
Accelerated synthesis of neural network-based barrier certificates using collaborative learning
A Gate-Delay Model for high-Speed CMOS Circuits
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores
A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits
Fast power grid simulation
BEVSA: A Real-Time Bird's-Eye-View Semantic Segmentation Accelerator for Multi-Camera System
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs
Range-Invariant Approximation of Non-Linear Operations for Efficient BERT Fine-Tuning
A Probabilistic Testability Measure for Delay Faults
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures
CognitiveArm: Enabling Real-Time EEG-Controlled Prosthetic Arm Using Embodied Machine Learning
Pre-RTL formal verification: an intel experience
A-TEAM: Automatic template-based assertion miner
A scalable symbolic simulation tool for low power embedded systems
MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices
A Framework for User Assisted Design Space Exploration
Functional Approaches to Generating Orderings for Efficient Symbolic Representations
Decomposition of logic networks into silicon
Improving gate-level simulation accuracy when unknowns exist
ILS - interactive logic simulator
Exploiting Power Side-Channel Vulnerabilities in XGBoost Accelerator
PEP: proactive checkpointing for efficient preemption on GPUs
Concepts of a microcomputer design language
Scheduling Using Behavioral Templates
The impact of electromigration in copper interconnects on power grid integrity
CAD system for VLSI
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits
Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference
Mixed signal design space exploration through analog platforms
MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction
BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-Precision
An Efficient Algorithm for Sparse Quantum State Preparation
Graphic applications subroutine packages
Automatic test-generation and test-verification of digital systems
How to make computers that work like the brain
An accurate functional level concurrent fault simulator
Bit-Parallel Vector Composability for Neural Acceleration
Predicting fault detectability in combinational circuits - a new design tool?
VLSI design methodology workshop
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units
A system for online power prediction in virtualized environments using Gaussian mixture models
Statistical timing for parametric yield prediction of digital integrated circuits
Publicly Detectable Techniques for the Protection of Virtual Components
Games are up for DVFS
MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy Compression
A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays
Speculation in elastic systems
TETA: Transistor-Level Engine for Timing Analysis
A Negative Reinforcement Method for PGA Routing
SEU tolerant device, circuit and processor design
Exact Width and Height Minimization of CMOS Cells
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations
A Full-system, Programmable, and Extensible In-Memory Computing Simulation Framework for Deep Learning
Plane Parallel a Maze Router and Its Application to FPGAs
How Much Analog Does a Designer Need to Know for Successful Mixed-Signal Design? (Panel)
Content-centric Display Energy Management for Mobile Devices
Ultrafast CPU/GPU Kernels for Density Accumulation in Placement
A Cost-Based Approach to Partial Scan
Hierarchical Optimization of Asynchronous Circuits
A Path Selection Global Router
A recursive paradigm to solve Boolean relations
A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop Prediction
An IP-Agnostic Foundational Cell Array Offering Supply Chain Security
"Building polyonimoes; an approach to the space layout problem"
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM
Flexible 2D layout decomposition framework for spacer-type double pattering lithography
An efficient algorithm to verify generalized false paths
A Fully Implicit Algorithm for Exact State Minimization
Cayman: Custom Accelerator Generation with Control Flow and Data Access Optimization
Timed compiled-code simulation of embedded software for performance analysis of SOC design
The mixed signal optimum energy point: voltage and parallelism
Automatic circuit analysis based on mask information
Manipulation of design data
A Methodology to Reduce the Computational Cost of Behavioral Test Pattern Generation
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits
Algorithms for Synthesis of Hazard-Free Asynchronous Circuits
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware
Methods for generalized deductive fault simulation
Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter
A Design for Testability Scheme with Applications to Data Path Synthesis
Some properties of a probabilistic model for global wiring
PAPP: Prefetcher-Aware Prime and Probe Side-channel Attack
Synthesis of feedback decoders for initialized encoders
ZXNet: ZX Calculus-Driven Graph Neural Network Framework for Quantum Circuit Equivalence Checking
Lithography at 14nm and beyond: choices and challenges
VGAUA: The Variable Geometry Automated Universal Array layout System
Trace-driven workload simulation method for Multiprocessor System-On-Chips
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators
An introduction into fault-tolerant quantum computing
VRL-DRAM: improving DRAM performance via variable refresh latency
GEMS: an automatic layout tool for MIMOLA schematics
Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors
RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning
Late Breaking Results: FRIENDS - Finding Related Interesting Events via Neighbor Detection
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits
HaDeS: architectural synthesis for <u>h</u>eterogeneous <u>d</u>ark <u>s</u>ilicon chip multi-processors
The application of integer programming in design automation
GLEAM/1130-a production system base for computer-aided design
A monitor for complex CAD systems
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences
An Efficient Assertion Checker for Combinational Properties
Avoiding game over: bringing design to the next level
Invited: Chipyard - An Integrated SoC Research and Implementation Environment
Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance
NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN
Designing gate arrays using a silicon compiler
A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW
OEsim: A Simulator for Timing Behavior
Zeroth-Order Optimization of Optical Neural Networks with Linear Combination Natural Gradient and Calibrated Model
Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits
Wall street evaluates EDA
EANeM: Energy-Aware Network Stack Management for Mobile Devices
A Lightweight Early Arbitration Method for Low-Latency Asynchronous 2D-Mesh NoC's
Locality-conscious workload assignment for array-based computations in MPSOC architectures
A General Framework for Spatial Correlation Modeling in VLSI Design
PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors
Formal Verification of a Superscalar Execution Unit
A critical path delay check system
RF IC Design Challenges
A Resynthesis Approach for Network Optimization
Automated diagram drafting
Parallel Channel Routing
Framework Standards: How Important are They? (Panel Abstract)
On the use of the linear assignment algorithm in module placement
A High-Precision and Low-Cost Approximate Transform Accelerator for Video Coding
System-Level Synthesis of Low-Power Hard Real-Time Systems
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform
Power-centric design of high-speed I/Os
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits
DFM in practice: hit or hype?
Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs
A system simulation framework
The complete VLSI design system
Optimizing Designs Containing Black Boxes
Automating the design of microprocessor-based real time control systems
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Scaled-CBSC: scaled counting-based stochastic computing multiplication for improved accuracy
CRITIC - an integrated circuit design rule checking program
Scheduling and analysis of real-time tasks with parallel critical sections
Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design
The Case for the Precision Timed (PRET) Machine
A survey of space allocation algorithms in use in architectural design in the past twenty years
Statistical Timing Analysis considering Multiple-Input Switching
The literature of software engineering: Description and guide
Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems
Frequency-based code placement for embedded multiprocessors
The rectangle placement language
"Minimizing PWB NC drilling"
Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision
EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency
Dimetrodon: processor-level preventive thermal management via idle cycle injection
BDD-based synthesis of reversible logic for large functions
Design perspectives on 22nm CMOS and beyond
A robust constraint solving framework for multiple constraint sets in constrained random verification
Concurrency Control in a VLSI Design Database
Equivalent Elmore Delay for RLC Trees
Integrated design system for supercomputer SX-1/SX-2
Invited: Drug Discovery Approaches using Quantum Machine Learning
INVITED: A 0.26% BER, Machine-Learning Resistant 10 28 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection
An MIG-based compiler for programmable logic-in-memory architectures
Leakage power reduction of embedded memories on FPGAs through location assignment
Stochastic variational analysis of large power grids considering intra-die correlations
Late Breaking Results: Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints
Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system
A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing
Design Automation philosophies (Position Paper)
Modeling and design description of hierarchical hardware/software systems
Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision
Routing-architecture-aware analytical placement for heterogeneous FPGAs
A Graph Theoretic Technique to Speed up Floorplan Area Optimization
Corezilla: Build and Tame the Multicore Beast?
Improving energy gains of inexact DSP hardware through reciprocative error compensation
A new approach to structural partitioning of computer logic
BooM: a decision procedure for boolean matching with abstraction and dynamic learning
The Design of Mixed Hardware/Software Systems
Computer aided design in North American Schools of Architecture
ASAP: reconciling asynchronous real-time operations and proofs of execution in simple embedded systems
ILP-based engineering change
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
To Tackle Cost-Skew Tradeoff: An Adaptive Learning Approach for Hub Node Selection
Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks
Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints
System Chip Test Challenges, Are There Solutions Today? (Panel)
Testing of MOS combinational networks a procedure for efficient fault simulation and test generation
DANCE: Differentiable Accelerator/Network Co-Exploration
Structured trace diagnosis for LSSD board testing - an alternative to full fault simulated diagnosis
Fast vectorless power grid verification using an approximate inverse technique
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits
Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems
Accurate Estimation of Combinational Circuit Activity
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools
Building a standard ESL design and verification methodology: is it just a dream?
Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver
How Secure are Deep Learning Algorithms from Side-Channel based Reverse Engineering?
Transaction based pre-to-post silicon validation
An automated method for designing logic circuit diagnostic programs
Thermal-Sustainable Power Budgeting for Dynamic Threading
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture
Why should we do 3D integration?
Sequential Circuit Verification Using Symbolic Model Checking
High-Level specification and automatic generation of IP interface monitors
Thermal-aware optimizations of reRAM-based neuromorphic computing systems
XFC: A Framework for eXploitable Fault Characterization in Block Ciphers
Layout Driven Logic Synthesis for FPGAs
Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement
Power Estimation in Sequential Circuits
Optimal Layout to Avoid CMOS Stuck-Open Faults
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques
VLIW: a case study of parallelism verification
Fast, Small, and Static Combinatorial CMOS Circuits
Computer methods of network analysis
Floorplanning with alignment and performance constraints
Technology Mapping for Large Complex PLDs
SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies
Tutorial on parallel processing for design automation applications (tutorial session)
Chip layout optimization using critical path weighting
"Views of a vendor" (Position Paper)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
A Transitive Closure Based Algorithm for Test Generation
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications
InterArch: Video Transformer Acceleration via Inter-Feature Deduplication with Cube-based Dataflow
Design automation for DNA self-assembled nanostructures
In-circuit temporal monitors for runtime verification of reconfigurable designs
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing
Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
The system bal: a technique for spreading the use of CAD techniques within an industrial environment
SIEVE: Speculative Inference on the Edge with Versatile Exportation
Three dimensional graphical display system
Synthesis techniques for digital systems design
GTX: the MARCO GSRC technology extrapolation system
Specialization meets Flexibility: a Heterogeneous Architecture for High-Efficiency, High-flexibility AR/VR Processing
FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA
Designer's Workbench: Delivery of cad tools
Specification-driven automated conformance checking for virtual prototype and post-silicon designs
Improved post-silicon power modeling using AC lock-in techniques
A new two-dimensional routing algorithm
Modeling repeaters explicitly within analytical placement
Symbolic Evaluation of Performance Models for Tradeoff Visualization
Formal semantics for the automated derivation of micro-code
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
A principle of algorithm design on limited problem domain
Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
DAGON: Technology Binding and Local Optimization by DAG Matching
Integrated techniques for functional and gate-level digital logic simulation
Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices
Open-Source EDA Tools and IP, A View from the Trenches
A practical technique for benefit-cost analysis of Computer-Aided Design and Drafting Systems
Automatic routing of double layer gate arrays using a moving cursor
Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions
Low-swing clock domino logic incorporating dual supply and dual threshold voltages
Dynamic thermal management via architectural adaptation
Architecture support for accelerator-rich CMPs
AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
Sniper: cloud-edge collaborative inference scheduling with neural network similarity modeling
Three levels of accuracy for the simulation of different fault types in digital systems
Current trends in the development of integrated general purpose CAD systems
"OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDX
An Entropy Measure for the Complexity of Multi-Output Boolean Functions
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Permutation-Write: Optimizing Write Performance and Energy for Skyrmion Racetrack Memory
April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators
Multisource illumination & shadowing
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
Coding approach for low-power 3D interconnects
Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros
Practical statistical static timing analysis with current source models
Model checking algorithms for analog verification
On Design Space Exploration of Cache System in Multi-Chiplet Systems
LA-MTL: Latency-Aware Automated Multi-Task Learning