yusuke1997/dblp-id-title huggingface dataset:
A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier Architectures
Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
Designing and Evaluating High Speed Elliptic Curve Point Multipliers
Musculoskeletal Model Analysis for Underwater Assist Suit for Elbow Joint
CMOS Illumination Discloses Processed Data
Implementation of Microprogrammed Hard Disk Drive Servo Sequencer
Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops
A Portable System for Measuring Human Body Movement
A Framework for Comprehensive Automated Evaluation of Concurrent Online Checkers
Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology
CFD for Microfluidics: A Workflow for Setting Up the Simulation of Microfluidic Devices
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications
On Designing All-Optical Multipliers Using Mach-Zender Interferometers
Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications?
FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications
PROCOMON: An Automatically Generated Predictive Control Signal Monitor
An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication
Bit-Level Allocation of Multiple-Precision Specifications
A Security-Enhanced UHF RFID Tag Chip
Crop Type Classification based on Machine Learning with Multitemporal Sentinel-1 Data
Life-Inspired Systems
One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems
ShapeFuture - Technical Progress After Year 1
Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA
A Resilient System Design to Boot a RISC-V MPSoC
Decision Diagram Optimization Using Copy Properties
Assessment of the Performance of a Commercial Spectral Sensor for Portable and Cost-Effective Multispectral Applications
Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving Arrangements
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture
Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm
Using Model-Based Testing for Manufacturing and Integration-Testing of Embedded Control Systems
A Model-Driven Approach for Validating Safe Adaptive Behaviors
Scalability Study of Polymorphic Register Files
Safety and Security-driven Design of Networked Embedded Systems
Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking
The DeSyRe Project: On-Demand System Reliability
Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Sensor Platform Design for Automotive Applications
Integrated Sensor: A Backdoor for Hardware Trojan Insertions?
Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL
Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems
FPGA-Centric High Performance Embedded Computing: Challenges and Trends
Flexible Radio Interface for NoC RF-Interconnect
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator
Model Checking on Hybrid Automata
A Modular Open-Source Cryptographic Co-Processor for Internet of Things
Active learning for fast and slow modeling attacks on Arbiter PUFs
Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip
Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures
23rd Euromicro Conference on Digital System Design, DSD 2020, Kranj, Slovenia, August 26-28, 2020
Low-Temperature Data Remanence Attacks Against Intrinsic SRAM PUFs
Fast, Quantization Aware DNN Training for Efficient HW Implementation
Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels
A Non Profiled and Profiled Side Channel Attack Countermeasure through Computation Interleaving
P2I: An Innovative MDA Methodology for Embedded Real-Time System
Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation
An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation
Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson Iteration
Low-Cost Software Control-Flow Error Recovery
A Verifiable High Level Data Path Synthesis Framework
RISC-V Extension for Lightweight Cryptography
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems
Inference Time Reduction of Deep Neural Networks on Embedded Devices: A Case Study
High-Level Synthesis of Geant4 Particle Transport Application for FPGA
2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016
Deep Learning Side-Channel Attack Against Hardware Implementations of AES
Exact Numerical Processing
Adaptive Networks-on-Chip Routing with Fuzzy Logic Control
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming
EUROSERVER: Energy Efficient Node for European Micro-Servers
Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE
Message from the General Chair DSD 2022
Customizable Composition and Parameterization of Hardware Design Transformations
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration
Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism
A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip
VLSI Reverse Converter for RNS Based on the Moduli Set
FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash
DSL-Based SNN Accelerator Design Using Chisel
Smart Sensing of Multi-bit Resistive Memory using a Single Reference
A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms
POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network Accelerators
A Mechanism for Implementing Precise Exceptions in Pipelined Processors
Design for Dependability and Autonomy of a Wearable Cardiac and Coronary Monitor
Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing
A Survey on Open-Source Flight Control Platforms of Unmanned Aerial Vehicle
Adaptive Beamforming Using the Reconfigurable MONTIUM TP
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures
An Ambient Temperature Variation Tolerance Scheme for an Ultra Low Power Shared-L1 Processor Cluster
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding
Delay Fault Coverage Increasing in Digital Circuits
FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training
Kamel: IP-XACT compatible intermediate meta-model for IP generation
Building Blocks and Interaction Patterns of Unmanned Aerial Systems
An Ontological Approach for the Dependability Analysis of Automated Systems
A hardware accelerator for entropy estimation using the top-k most frequent elements
A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor
Counter Power Leakage for Frequency Extraction of Ring Oscillators in ROPUF
The Story of NextPerception - A survey of the project vision and realisation with examples
Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs
An efficient FPGA-based co-processor for feature point detection and tracking
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption
Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC
Program Generation Through a Probabilistic Constrained Grammar
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms
Embedded Software: How To Make It Efficient?
21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018
Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems
Collision Based Attacks in Practice
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip
Wireless Multi-channel Quasi-digital Tactile Sensing Glove-Based System
Generic Self Repair Architecture with Multiple Fault Handling Capability
Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine
Application Dependent FPGA Testing Method
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits
Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles
SmartDelta: Automated Quality Assurance and Optimization in Incremental Industrial Software Systems Development
Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs
Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits
Resynthesis of logic circuits using machine learning and reconvergent paths
Use of the Autocorrelation Function in the Classification of Switching Functions
NoCs: A new Contract between Hardware and Software
Towards a Safe Software Development Environment
Composable Virtual Memory for an Embedded SoC
Measuring the Distribution of Metastable Upsets over Time
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit
Bi-Decomposition Using Boolean Relations
A streaming algorithm and hardware accelerator for top-K flow detection in network traffic
GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations
A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing
Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL
SAT-Based ATPG for Zero-Aliasing Compaction
FPGA Design of an Open-Loop True Random Number Generator
Model-Driven Design of Embedded Multimedia Applications on SoCs
An Efficient BIST Scheme for Non-Restoring Array Dividers
A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming
Adaptive Control of the Heating System for Optimized Energy Consumption in Electric Vehicles
Hardware-Level Adaptive Scheduling for Reconfigurable Accelerators on Virtualized FPGAs
Temperature Influence on Power Consumption and Time Delay
Customizable Embedded Processor Architectures
Development Framework for Model Driven Architecture to Accomplish Power-Aware Embedded Systems
A Low Power 15-Bit Decimator in 0.18um CMOS for Biomedical Applications
An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem
Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract)
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits
Composable Resource Sharing Based on Latency-Rate Servers
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller
ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications
Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches
Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis
Design Guides for a Correct DC Operation in RTD-based Threshold Gates
Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoC
On the Construction of Small Fully Testable Circuits with Low Depth
Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs
A CFI Verification System based on the RISC-V Instruction Trace Encoder
Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory
Multi-modal Building Energy Management System for Residential Demand Response
Automatic Control Flow Generation for OpenVX Graphs
IRIS: A Firmware Design Methodology for SIMD Architectures
A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms
Wireless and Portable System for the Study of in-vitro Cell Culture Impedance Spectrum by Electrical Impedance Spectroscopy
Optimized HW/FW Generation from an Abstract Register Interface Model
ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing
Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System
Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic
Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller
An Efficient Approach for Soft Error Rate Estimation of Combinational Circuits
Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures
System-Aware Performance Monitoring Unit for RISC-V Architectures
Designing Energy Efficient Approximate Multipliers for Neural Acceleration
Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output Functions
Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array
Fault-Tolerant Irregular Topology Design Method for Network-on-Chips
Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs
Architecture of Effective High-Speed Network Stream Merger
Semi-distributed Control for FPGA-based Reconfigurable Systems
Testability Based Metric for Hardware Trojan Vulnerability Assessment
A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems
FPGA-tidbits: Rapid Prototyping of FPGA Accelerators in Chisel
MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BIST
Combination of ROP Defense Mechanisms for Better Safety and Security in Embedded Systems
HMMER Performance Model for Multicore Architectures
Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration
Low Power Free Space Optical Communication in Wireless Sensor Networks
Linking the Physical with the Perceptual: Health and Exposure Monitoring with Cyber-physical Questionnaires
Instruction Selection and Scheduling for DSP Kernels on Custom Architectures
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits
An Extensible Simulator for Dynamic Control of Residential Area: Case Study on Heating Control
Transmittance Hyperspectral Capture System and Methodology Assessment for Blood-Liquid Serum Samples Analysis
Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices
Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies
Ultra-Low Power Estimation of Heart Rate Under Physical Activity Using a Wearable Photoplethysmographic System
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design
Interconnect-Driven Short-Circuit Power Modeling
On the Importance of Analysing Microarchitecture for Accurate Software Fault Models
Online GPUAnalysis using Adaptive DMA Controlled by Softcore for 2D Detectors
14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland
On the Risk of Fault Coupling over the Chip Substrate
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
New Directions in Mobile Device Architectures
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization
Classifying Acoustic Signals for Wildlife Monitoring and Poacher Detection on UAVs
Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design
HW/SW Collaborative Techniques for Accelerating TinyML Inference Time at No Cost
Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal
A Control of Electric Wheelchair Using an EMG Based on Degree of Muscular Activity
Three-Dimensional Design Space Exploration for System Level Synthesis
Application-Specific Topology Design Customization for STNoC
A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems
High Performance Computing for Embedded System Design: A Case Study
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
A Fast Estimator of Performance with Respect to the Design Parameters of Self Re-Entrant Flowshops
5G Security: FPGA Implementation of SNOW-V Stream Cipher
Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation
Design and Implementation of an HCI Based Peer to Peer APDU Protocol
High-Level Decision Diagram based Fault Models for Targeting FSMs
Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver
RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two
HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
A Priority-Based Budget Scheduler with Conservative Dataflow Model
Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations
Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time Monitoring
Integrating Task Migration Capability in Software Tool-Chain for Data-Flow Applications Mapped on Multi-tiled Architectures
Quantization: how far should we go?
Optimal 2D Data Partitioning for DMA Transfers on MPSoCs
Polynomial Based NUC Implemented on FPGA
A Flexible Radio Transmitter for TVWS Based on FBMC
Miscellaneous Types of Partial Duplication Modifications for Availability Improvements
Formal Communication Semantics of SystemC FL
Architecture of a Power-Gated Wireless Sensor Node
Metrics for the Evaluation of Approximate Sequential Streaming Circuits
The Conical-Fishbone Clock Tree: A Clock-Distribution Network for a Heterogeneous Chip Multiprocessor AI Chiplet
TextBack: Watermarking Text Classifiers using Backdooring
Development of Autonomous Drones for Adaptive Obstacle Avoidance in Real World Environments
Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures
Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical Threats
A Wearable Intelligent System for the Health of Expectant Mom's and of Their Children
On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators
Design of a Low-Level Radar and Time-of-Flight Sensor Fusion Framework
Technology Mapping for PAIG Optimised Polymorphic Circuits
Towards an Energy-Efficient RISC-V Core Architecture with Dynamic Dual-Issue and Clock Gating
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems
Open-Source Research on Time-predictable Computer Architecture
On the Design of Configurable Modulo 2n±1 Residue Generators
On Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems
Smart Chair System for Posture Correction
Fault Latencies of Concurrent Checking FSMs
Adaptive Equalizer Training for High-Speed Low-Power Communication Systems
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System
Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow Applications
External Memory Protection on FPGA-Based Embedded Systems
COMP4DRONES: Key Enabling Technologies for Drones to enhance Mobility and Logistics Operations
DistriMuSe - Distributed Multi-Sensor Systems for Human Safety and Health
A Flexible Hardware Platform for Mobile Cognitive Radio Applications
Compiling Esterel for Multi-core Execution
Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip Multiprocessor
Design of a Distributed Embedded System for Domotic Applications
A Clustering-Based Scoring Mechanism for Malicious Model Detection in Federated Learning
The Criteria of Functional Delay Test Quality Assessment
Energy Based Design Space Exploration of Multiprocessor VLIW Architectures
Exploring Graphics Processor Performance for General Purpose Applications
Implementation of a block based neural branch predictor
Dependable Design for FPGA Based on Duplex System and Reconfiguration
MISRs for Fast Authentication of Long Messages
A Scenario-Aware Dataflow Programming Model
Java to Hardware Compilation for non Data Flow Applications
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms
A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks
Design of Compact Integrated Photonic Crystal NAND and NOR Logic Gates
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes
TAP: Task-Aware Profiling on Integrated Systems
PBO-Based Test Compression
Hyperparameter Optimization for Brain Tumor Classification with Hyperspectral Images
Medical Data Over Sound for Vital Signs Monitoring
Hard and Soft Logic Trade-offs for Multipliers in VTR
PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register Files
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks
Handel-C implementation of Classical Component Labelling Algorithm
Cascade Scheme for Concurrent Errors Detection
Coherency Traffic Reduction in Manycore Systems
Transition Fault Test Reuse
In-Context Learning for Microcontroller Performance Screening Using Tabular Foundation Models
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and Synthesis
An FPGA Hardware Trojan Detection Approach Based on Multiple Parameter Analysis
System Performance Modelling of Heterogeneous HW Platforms: An Automated Driving Case Study
22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019
An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm
Evaluating the Impact of Communication Network Performance on Supervisory Supermarket Control
A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection Applications
Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering
Dual-Mode Quadruple Precision Floating-Point Adder
In-Sensor Self-Calibration Circuit of MEMS Pressure Sensors for Accurate Localization
Towards Resilient QDI Pipeline Implementations
An Interactive Design Space Exploration Tool for Dependable Integrated Circuits
Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits
17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
High-Throughput One-Channel RS(255, 239) Decoder
Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm
Comparison of three counter value based ROPUFs on FPGA