yusuke1997/dblp-id-title huggingface dataset:
Breaking Confidentiality of XTS-AES Encrypted Data at Rest on Microprocessors Using Electromagnetic Side-Channel Attacks
Secure IP-Block Distribution for Hardware Devices
Using Multiple Processors in a Single Reconfigurable Fabric for High-assurance Applications
Transistor-level camouflaged logic locking method for monolithic 3D IC security
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures
Detour: Layout-aware Reroute Attack Vulnerability Assessment and Analysis
A High Efficiency Hardware Design for the Post-Quantum KEM HQC
Building trusted ICs using split fabrication
TrustZoneTunnel: A Cross-World Pattern History Table-Based Microarchitectural Side-Channel Attack
Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs
Register leakage masking using Gray code
DWM-PUF: A low-overhead, memory-based security primitive
Parameter biasing obfuscation for analog IP protection
Towards an Antivirus for Quantum Computers
Covert Communication Channels Based On Hardware Trojans: Open-Source Dataset and AI-Based Detection
Evaluating the Impact of Hardware Faults on Program Execution in a Microkernel Environment
Hardware Trojan Detection Using Path Delay Fingerprint
TinyPower: Side-Channel Attacks with Tiny Neural Networks
Explainability to the Rescue: A Pattern-Based Approach for Detecting Adversarial Attacks
When good protections go bad: Exploiting anti-DoS measures to accelerate rowhammer attacks
Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter
NoiseHopper: Emission Hopping Air-Gap Covert Side Channel with Lower Probability of Detection
Dual Channel EM/Power Attack Using Mutual Information and its Real-time Implementation
Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor
Global Attack and Remedy on IC-Specific Logic Encryption
MagHop: Magnetic Spectrum Hopping for Securing Voltage and Current Magnetic Sensors
AccessShadow: Leveraging Adversarial Samples to Counter Deep Learning-Assisted Cache Timing Attacks
Comparing Sboxes of ciphers from the perspective of side-channel attacks
Formal security evaluation of hardware Boolean masking against second-order attacks
Analysis and Design of Active IC Metering Schemes
IP core protection using voltage-controlled side-channel receivers
ML-EMFI: A Machine Learning-Driven Pre-Silicon Electromagnetic Fault Injection Security Evaluation for Robust IC Design
Threshold voltage defined multi-input complex gates
CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core
Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography
Circuit CAD Tools as a Security Threat
A noise bifurcation architecture for linear additive physical functions
Trust games: How game theory can guide the development of hardware Trojan detection methods
Trusted RTL: Trojan Detection Methodology in Pre-silicon Designs
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs
Intrinsic Rowhammer PUFs: Leveraging the Rowhammer effect for improved security
Upper bounds on the min-entropy of RO Sum, Arbiter, Feed-Forward Arbiter, and S-ArbRO PUFs
The Conjoined Microprocessor
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2024, Tysons Corner, VA, USA, May 6-9, 2024
A novel security technique to generate truly random and highly reliable reconfigurable ROPUF-based cryptographic keys
SpongePUF: A Modeling Attack Resilient Strong PUF with Scalable Challenge Response Pair
Hardware trojan detection by symmetry breaking in path delays
Functional polymorphism for intellectual property protection
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2022, McLean, VA, USA, June 27-30, 2022
SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Tysons Corner, VA, USA, December 12-15, 2021
Going Deep: Using deep learning techniques with simplified mathematical models against XOR BR and TBR PUFs (Attacks and Countermeasures)
Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise
Localized electromagnetic analysis of RO PUFs
SIN 2 : Stealth infection on neural network - A low-cost agile neural Trojan attack methodology
Performance evaluation of protocols resilient to physical attacks
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2 m ) based on MSPB
Low Voltage Fault Attacks to AES
Direct read of idle block RAM from FPGAs utilizing photon emission microscopy
A Solution for On-Line TRUST Validation
Using image sensor PUF as root of trust for birthmarking of perceptual image hash
Attack of the Genes: Finding Keys and Parameters of Locked Analog ICs Using Genetic Algorithm
On state encoding against power analysis attacks for finite state controllers
Validation of RTL laser fault injection model with respect to layout information
A systematic M safe-error detection in hardware implementations of cryptographic algorithms
Improving reliability of weak PUFs via circuit techniques to enhance mismatch
Efficient and Side-Channel Resistant Design of High-Security Ed448 on ARM Cortex-M4
Improving Single-Trace Attacks on the Number-Theoretic Transform for Cortex-M4
HERMES: Hardware-Efficient Speculative Dataflow Architecture for Bonsai Merkle Tree-Based Memory Authentication
Key extraction from the primary side of a switched-mode power supply
A Fetching Tale: Covert Communication with the Hardware Prefetcher
3D Unclonable Optical Identity for Universal Product Verification
Security Threats and Countermeasure Deployment Using Partial Reconfiguration in FPGA CAD Tools
EnclaveSim: A Micro-architectural Simulator with Enclave Support
EC-CFI: Control-Flow Integrity via Code Encryption Counteracting Fault Attacks
Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists
Detection of probing attempts in secure ICs
A key-centric processor architecture for secure computing
ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity
On-Demand Transparency for Improving Hardware Trojan Detectability
Improving on State Register Identification in Sequential Hardware Reverse Engineering
Lightweight Encryption Using Chaffing and Winnowing with All-or-Nothing Transform for Network-on-Chip Architectures
A Lightweight Mutual Authentication Protocol Based on Physical Unclonable Functions
RLFuzz: Accelerating Hardware Fuzzing with Deep Reinforcement Learning
Cloning Physically Unclonable Functions
Machine learning resistant strong PUF: Possible or a pipe dream?
Hardware security in practice: Challenges and opportunities
Prefetch-guard: Leveraging hardware prefetches to defend against cache timing channels
Disassembling Software Instruction Types through Impedance Side-channel Analysis
An Embedded Flash Memory Vault for Software Trojan Protection
Case study: Detecting hardware Trojans in third-party digital IP cores
Partial Reconfiguration for Run-time Memory Faults and Hardware Trojan Attacks Detection
ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs
Input-Triggered Hardware Trojan Attack on Spiking Neural Networks
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers
Too Hot to Handle: Novel Thermal Side-Channel in Power Attack-Protected Intel Processors
A novel fault attack against ECDSA
Creating security primitive by nanoscale manipulation of carbon nanotubes
FTC: A Universal Sensor for Fault Injection Attack Detection
System on Chip (SoC) Security Architecture Framework for Isolated Domains Against Threats
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines
RTL-Spec: RTL Spectrum Analysis for Security Bug Localization
Defeating drone jamming with hardware sandboxing
Platform agnostic, scalable, and unobtrusive FPGA network processor design of moving target defense over IPv6 (MT6D) over IEEE 802.3 Ethernet
DiSPEL: A Framework for SoC Security Policy Synthesis and Distributed Enforcement
Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers
DOME: Automated Validation of Data-Oblivious Program Execution
Translating circuit behavior manifestations of hardware Trojans using model checkers into run-time Trojan detection monitors
Hardware-based workload forensics: Process reconstruction via TLB monitoring
RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack
Extended Abstract: Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting
On design of a highly secure PUF based on non-linear current mirrors
Take a moment and have some t: Hypothesis testing on raw PUF data
SpecPref: High Performing Speculative Attacks Resilient Hardware Prefetchers
CryptoML: Secure outsourcing of big data machine learning applications
A look into SIMON from a side-channel perspective
Physical unclonable functions and dynamic partial reconfiguration for security in resource-constrained embedded systems
Evaluating the Effectiveness of Hardware Trojan Detection Approaches at RTL
ACBuilder: A tool for hardware architecture security evaluation
A Modeling Attack on the Sub-threshold Current Array PUF
Enhancing security via provably trustworthy hardware intellectual property
Application-Specific Instruction Set Architecture for an Ultralight Hardware Security Module
A Security Assessment of Protected Execute-Only Firmware in Microcontrollers Through Selective Chemical Engraving
Stability analysis of a physical unclonable function based on metal resistance variations
RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan
Interacting with Hardware Trojans over a network
OMT: A Run-time Adaptive Architectural Framework for Bonsai Merkle Tree-Based Secure Authentication with Embedded Heterogeneous Memory
Exploiting resistive cross-point array for compact design of physical unclonable function
FPGA Implementations of the Hummingbird Cryptographic Algorithm
An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms
Efficient and secure intellectual property (IP) design with split fabrication
Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network
Anti-tamper JTAG TAP Design Enables DRM to JTAG Registers and P1687 on-chip Instruments
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols
ENTT: A Family of Emerging NVM-based Trojan Triggers
New clone-detection approach for RFID-based supply chains
Synthesis of hardware sandboxes for Trojan mitigation in systems on chip
Secuirty Metrics for Logic Circuits
Adaptive real-time Trojan detection framework through machine learning
Securing Smart Manufacturing: Detection of Cyber-Physical Attacks in CNC-Based Systems
The other side of the coin: Analyzing software encoding schemes against fault injection attacks
Security Analysis of Delay-Based Strong PUFs with Multiple Delay Lines
Detection of counterfeit ICs using public identification sequences
Side-channel countermeasure for SHA-3 at almost-zero area overhead
Fault Round Modification Analysis of the advanced encryption standard
Michscan: Black-Box Neural Network Integrity Checking at Runtime Through Power Analysis
HW2VEC: a Graph Learning Tool for Automating Hardware Security
ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist
Algorithmic collision analysis for evaluating cryptographic systems and side-channel attacks
Electronic forensic techniques for manufacturer attribution
Performance of Delay-Based Trojan Detection Techniques under Parameter Variations
MARVEL - Malicious alteration recognition and verification by emission of light
LAPD: Lifecycle-Aware Power-Based Malware Detection
2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013
New security threats against chips containing scan chain structures
UCR: An unclonable chipless RFID tag
A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher
Securing interconnected PUF network with reconfigurability
On the Feasibility of Training-time Trojan Attacks through Hardware-based Faults in Memory
Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help
Security Aspects of Masking on FPGAs
Undermining Quantum Circuit Obfuscation: Insights from Structural Analysis
BitJabber: The World's Fastest Electromagnetic Covert Channel
Towards Practical Fabrication Stage Attacks Using Interrupt-Resilient Hardware Trojans
CTR+: A High-Performance Metadata Access Scheme for Secure Embedded Memory in Heterogeneous Computing Systems
GenMatch: Secure DNA compatibility testing
Slicing Up a Perfect Hardware Masking Scheme
Entropy loss in PUF-based key generation schemes: The repetition code pitfall
Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning
The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates
Photonic side channel attacks against RSA
Fault-assisted side-channel analysis of masked implementations
Towards a memristive hardware secure hash function (MemHash)
RUDBA: Reusable User-Device Biometric Authentication Scheme for Multi-service Systems
Reverse Engineering DVFS Mechanisms
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach
Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level
A layout-driven framework to assess vulnerability of ICs to microprobing attacks
Prototyping Platform for Performance Evaluation of SHA-3 Candidates
TZSlicer: Security-aware dynamic program slicing for hardware isolation
The Role of Platform Integrity in Trustworthy Systems
On the Impact of Metastability in Jitter Based TRNG
Redirecting DRAM memory pages: Examining the threat of system memory Hardware Trojans
Revisit fault sensitivity analysis on WDDL-AES
Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores
Exploring timing side-channel attacks on path-ORAMs
Remote attestation of IoT devices via SMARM: Shuffled measurements against roving malware
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2025, San Jose, CA, USA, May 5-8, 2025
Template attacks using classification algorithms
Low-area hardware implementations of CLOC, SILC and AES-OTR
Dividing the threshold: Multi-probe localized EM analysis on threshold implementations
NREPO: Normal basis Recomputing with Permuted Operands
All Your Base Are Belong To Us: Stealing VRP Secrets from Quantum Circuit Structures
Circuit Level Techniques for Reliable Physically Uncloneable Functions
NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing
Bit 2 RNG: Leveraging Bad-page Initialized Table with Bit-error Insertion for True Random Number Generation in Commodity Flash Memory
Voltage Noise-Based Adversarial Attacks on Machine Learning Inference in Multi-Tenant FPGA Accelerators
Scalable SoC trust verification using integrated theorem proving and model checking
A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality
PhenoAuth: A Novel PUF-Phenotype-Based Authentication Protocol for IoT Devices
Analyzing security vulnerabilities of three-dimensional integrated circuits
TRUST in Integrated Circuits and 3rd Party IP
Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography
New scan attacks against state-of-the-art countermeasures and DFT
Enhancing fault sensitivity analysis through templates
Evaluating security requirements in a general-purpose processor by combining assertion checkers with code coverage
Rowhammer Cache: A Last-Level Cache for Low-Overhead Rowhammer Tracking
Toward automatic proof generation for information flow policies in third-party hardware IP
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2023, San Jose, CA, USA, May 1-4, 2023
A Large Scale Characterization of RO-PUF
PCB Component Detection for Hardware Assurance: A Feature Selection-based Approach
WaveSleuth: Retrospective PLC Memory for Anomaly Detection in Industrial Control Systems
Data-Oblivious ML Accelerators Using Hardware Security Extensions
Post-layout estimation of side-channel power supply signatures
TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks
Verification of untrusted chips using trusted layout and emission measurements
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection
Secure chip odometers using intentional controlled aging
Methodology of Assessing Information Leakage through Software-Accessible Telemetries
Chosen ciphertext Simple Power Analysis on software 8-bit implementation of ring-LWE encryption
POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly
Improving FPGA based SHA-3 structures
DESIV: Differential Fault Analysis of SIV-Rijndael256 with a Single Fault
Round gating for low energy block ciphers
Quantization Schemes for PUFs: The Entropy-Area Trade-Off
B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection
Lowering the barrier to online malware detection through low frequency sampling of HPCs
Template attack on masking AES based on fault sensitivity analysis
Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs
MACPruning: Dynamic Operation Pruning to Mitigate Side-Channel DNN Model Extraction
Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF
SAT-based reverse engineering of gate-level schematics using fault injection and probing
Reverse engineering circuits using behavioral pattern mining
On hardware Trojan design and implementation at register-transfer level
Sensor Physical Unclonable Functions
Physically secure and fully reconfigurable data storage using optical scattering
LightEMU: Hardware Assisted Fuzzing of Trusted Applications
Exploiting safe error based leakage of RFID authentication protocol using hardware Trojan horse
Cryptographic Least Privilege Enforcement for Scalable Memory Isolation
Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs
Cross-VM Information Leaks in FPGA-Accelerated Cloud Environments
A survey of frequently identified vulnerabilities in commercial computing semiconductors
FaultLine: Software-Based Fault Injection on Memory Transfers
Thwarting Control Plane Attacks with Displaced and Dilated Address Spaces
SecSoC: A Secure System on Chip Architecture for IoT Devices
Detecting Laser Fault Injection Attacks via Time-to-Digital Converter Sensors
Sparse Polynomial Multiplication-Based High-Performance Hardware Implementation for CRYSTALS-Dilithium
Performance metrics and empirical results of a PUF cryptographic key generation ASIC
Simulation and analysis of negative-bias temperature instability aging on power analysis attacks
A Novel Attack on Machine-Learning Resistant Physical Unclonable Functions
Contact PUF: Highly Stable Physical Unclonable Functions Based on Contact Failure Probability in 180 nm, 130 nm, and 28 nm CMOS Processes
Automatic obfuscated cell layout for trusted split-foundry design
Gadgets of Gadgets in Industrial Control Systems: Return Oriented Programming Attacks on PLCs
Split-fabrication obfuscation: Metrics and techniques
Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP
Cuot: Accelerating Oblivious Transfer on Gpus for Privacy-Preserving Computation
LISA: Maximizing RO PUF's Secret Extraction
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses
Repurposing SoC analog circuitry for additional COTS hardware security
Neural network based attack on a masked implementation of AES
Designer's Hardware Trojan Horse
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance
On-chip lightweight implementation of reduced NIST randomness test suite
Malicious CAN-message attack against advanced driving assistant system
A Novel Golden-Chip-Free Clustering Technique Using Backscattering Side Channel for Hardware Trojan Detection
Hardware-Software Co-design for Side-Channel Protected Neural Network Inference
Model building attacks on Physically Unclonable Functions using genetic programming
High precision fault injections on the instruction cache of ARMv7-M architectures
Increasing the efficiency of laser fault injections using fast gate level reverse engineering
Inverse gating for low energy encryption
Reassessing the TCG Specifications for Trusted Computing in Mobile and Embedded Systems
Breaking active-set backward-edge CFI
SARLock: SAT attack resistant logic locking
Controlling your control flow graph
EM-based detection of hardware trojans on FPGAs
Malicious circuitry detection using fast timing characterization via test points
Security Order of Gate-Level Masking Schemes
LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity
Towards Attack Resilient Delay-Based Strong PUFs
MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation
Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core
Power supply glitch attacks: Design and evaluation of detection circuits
Hardware Trojan Detection at LUT: Where Structural Features Meet Behavioral Characteristics
TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms
Experiences in Hardware Trojan Design and Implementation
Parsimonious design strategy for linear layers with high diffusion in block ciphers
Cache timing attacks on recent microarchitectures
Fault Analysis of Grain-128
pHGen: A pH-Based Key Generation Mechanism Using ISFETs
LWE-based lossless computational fuzzy extractor for the Internet of Things
Self-authenticating secure boot for FPGAs
Iterating Von Neumann's post-processing under hardware constraints
Error Correction Attacks on BACnet MS/TP
Design solutions for securing SRAM cell against power analysis
$\mathcal{RRR}$: Rethinking Randomized Remapping for High Performance Secured NVM LLC
2020 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2020, San Jose, CA, USA, December 7-11, 2020
FanBleed: Stealing Your Secrets via Observing Your Cooling Fan
Securing Hardware Accelerator during High-level Synthesis
Targeted Bitstream Fault Fuzzing Accelerating BiFI on Large Designs
Using computational game theory to guide verification and security in hardware designs
E-LoQ: Enhanced Locking for Quantum Circuit IP Protection
A Comparison of Power-analysis-resistant Digital Circuits
2016 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2016, McLean, VA, USA, May 3-5, 2016
An area-optimized serial implementation of ICEPOLE authenticated encryption schemes
Trojan Localization in Generic AMS Circuits from Combined Power and Functional Queries
QNAD: Quantum Noise Injection for Adversarial Defense in Deep Neural Networks
CPU and GPU Accelerated Fully Homomorphic Encryption
A Pre-Silicon Physical Design Study Towards Mitigating EMSCA on Cryptographic ICs
Information leakage behind the curtain: Abusing anti-EMI features for covert communication
Cryptographic Fault Diagnosis using VerFI
INFECT: INconspicuous FEC-based Trojan: A hardware attack on an 802.11a/g wireless network
Golden Gates: A New Hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging
SURF: Joint Structural Functional Attack on Logic Locking
Model checking to find vulnerabilities in an instruction set architecture
On-chip substrate-bounce monitoring for laser-fault countermeasure