yusuke1997/dblp-id-title huggingface dataset:
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
Contention Minimized Bypassing in SMART NoC
A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications
Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics
System level performance analysis and optimization for the adaptive clocking based multi-core processor
Hardware-Software Co-Design for On-Chip Learning in AI Systems
Scalable design for field-coupled nanocomputing circuits
DeepIncept: Diversify Performance Counters with Deep Learning to Detect Malware
Soft error rate reduction using redundancy addition and removal
Space-planning: placement of modules with controlled empty area by single-sequence
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes
Vector extraction for average total power estimation
Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
Simultaneous slack budgeting and retiming for synchronous circuits optimization
A Side-Channel Hardware Trojan in 65nm CMOS with 2μW precision and Multi-bit Leakage Capability
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
SAADI: a scalable accuracy approximate divider for dynamic energy-quality scaling
Run-time adaptable on-chip thermal triggers
Aging-aware high-level physical planning for reconfigurable systems
A unified online directed acyclic graph flow manager for multicore schedulers
Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs
A trace-driven approach for fast and accurate simulation of manycore architectures
New Multilevel and Hierarchical Algorithms for Layout Density Control
Boosting the Search Performance of B+-tree with Sentinels for Non-volatile Memory
Reliable in-memory neuromorphic computing using spintronics
Reuse and Blend: A Weight-Sharing Energy-Efficient Optical Neural Network
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
Modeling, analysis, and optimization of Electric Vehicle HVAC systems
Low-leakage robust SRAM cell design for sub-100nm technologies
Embedded architectural simulation within behavioral synthesis environment
An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs
A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation
Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs
FPGA for High-Performance Bit-Serial Pipeline Datapath
Limits of using signatures for permutation independent Boolean comparison
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
A resilient on-chip router design through data path salvaging
A full-synthesizable high-precision built-in delay time measurement circuit
The required technologies for Automotive towards 2020
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer
Dynamic voltage scaling of periodic and aperiodic tasks in priority-driven systems
CLASS: Combined logic and architectural soft error sensitivity analysis
Prefetching techniques for STT-RAM based last-level cache in CMP systems
Efficient analytical determination of the SEU-induced pulse shape
Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Invited paper: Bridging EDA and Silicon Photonics Design: Enabling Robust-by-Design Photonic Integrated Circuits
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Energy-aware register file re-partitioning for clustered VLIW architectures
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
Design and verification tools for continuous fluid flow-based microfluidic devices
STORM: A nonlinear model order reduction method via symmetric tensor decomposition
System accuracy estimation of SRAM-based device authentication
CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS
TNPU: an efficient accelerator architecture for training convolutional neural networks
An MIP-based Force-directed Large Scale Placement Refinement Algorithm
Process variation robust clock tree routing
FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Learning-based prediction of embedded memory timing failures during initial floorplan design
Assessing the feasibility of interface designs before their implementation
GRA-LPO: Graph Convolution Based Leakage Power Optimization
Robust power gating reactivation by dynamic wakeup sequence throttling
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis
TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures
Jitter decomposition in ring oscillators
A system level memory power optimization technique using multiple supply and threshold voltages
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators
SCBench: A benchmark design suite for SystemC verification and validation
SGXCrypter: IP protection for portable executables using Intel's SGX technology
Prefetching-aware cache line turnoff for saving leakage energy
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
SimEval: Investigating the Similarity Obstacle in LLM-based Hardware Code Generation
An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar
The data center as a grid load stabilizer
In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis
A new global router for modern designs
Power estimation starategies for a low-power security processor
A New Global Routing Algorithm Independent Of Net Ordering
Invasive manycore architectures
OPAL: A multi-layer hybrid photonic NoC for 3D ICs
Bisection Based Placement for the X Architecture
Graph partition based path selection for testing of small delay defects
Depth-driven verification of simultaneous interfaces
On process-aware 1-D standard cell design
Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments
Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models
Design of a high-performance Millimeter-wave amplifier using specific modeling
Multi-core DSP for base stations: Large and small
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults
Bug localization techniques for effective post-silicon validation
Timing anomalies in multi-core architectures due to the interference on the shared resources
Interconnect estimation without packing via ACG floorplans
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU
Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial)
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter
Optimization of Arithmetic Datapaths with Finite Word-Length Operands
Forward symbolic model checking for real time systems
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks
Reaching the limits of low power design
Improved weight assignment for logic switching activity during at-speed test pattern generation
Minimizing leakage power in aging-bounded high-level synthesis with design time multi- V th assignment
Cross-domain security of cyber-physical systems
ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns
Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization
Hybrid LZA: a near optimal implementation of the leading zero anticipator
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges
Area-IO DRAM/logic integration with system-in-a-package (SiP)
Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency Hiding
A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components
A hardware simulation engine based on decision diagrams (short paper)
Control-Flow Aware Communication and Conflict Analysis of Parallel Processes
The synthesis of linear Finite State Machine-based Stochastic Computational Elements
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro
Logic optimization by an improved sequential redundancy addition and removal techniques
Node Mergers in the Presence of Don't Cares
An innovative Steiner tree based approach for polygon partitioning
DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level
Dynamic symmetry-breaking for improved Boolean optimization
A domain specific reconfigurable Viterbi fabric for system-on-chip applications
Current trends in flash memory technology: invited paper
ML-augmented Methodology for Fast Thermal Side-channel Emission Analysis
Real Time Fault Injection Using Logic Emulators
wearMeter: an Accurate Wear Metric for NAND Flash Memory
Nonlinear distortion analysis via linear-centric models
Verifying dynamic power management schemes using statistical model checking
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations
LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking
A brand new wireless day
VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA
Design of a CMOS test chip for package models and I/O characteristics verification
Design and verification using high-level synthesis
DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input
SHarPen: SoC Security Verification by Hardware Penetration Test
A Reconfigurable Inference Processor for Recurrent Neural Networks Based on Programmable Data Format in a Resource-Limited FPGA
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs
Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization
Benchmark Circuits Improve the Quality of a Standard Cell Library
Layout techniques for on-chip interconnect inductance reduction
Machine Learning Based Online Full-Chip Heatmap Estimation
FPBA: Flexible Percentile-Based Allocation for Multiple-Bits-Per-Cell RRAM
Majority logic circuits optimisation by node merging
Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements
An LSI implementation of the simple serial synchronized multistage interconnection network
Optimizing DSA-MP decomposition and redundant via insertion with dummy vias
Synthesis-for-testability using transformations
SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration
Post-silicon patching for verification/debugging with high-level models and programmable logic
Power grid analysis benchmarks
Macromodelling oscillators using Krylov-subspace methods
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating
Design of an application-specific PLD architecture
Virtual Java/FPGA interface for networked reconfiguration
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology
HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs
Latent Weight-Based Pruning for Small Binary Neural Networks
Automata-theoretic modeling of fixed-priority non-preemptive scheduling for formal timing verification
An Efficient Variable-Length Tap FIR Filter Chip
Multi-metric and multi-entity characterization of applications for early system design exploration
Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme
Fine-grained runtime power budgeting for networks-on-chip
Abstract system-level models for early performance and power exploration
Advanced power management techniques: going beyond intelligent shutdown
Accelerated processing and the Fusion System Architecture
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators
Challenging device innovation
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic
A criticality-driven microarchitectural three dimensional (3D) floorplanner
TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm
Block based statistical timing analysis with extended canonical timing model
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures
Low-power digital CDMA receiver
Reliability-aware design for nanometer-scale devices
Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge Devices
Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS
A self-testing and calibration method for embedded successive approximation register ADC
SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep Learning
DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
Fast Buffer Insertion for Yield Optimization Under Process Variations
A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching
Branch predictor design and performance estimation for a high performance embedded microprocessor
Multi-hit time-to-digital converter VLSI for high-energy physics experiments
Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection
MIPAC: Dynamic Input-Aware Accuracy Control for Dynamic Auto-Tuning of Iterative Approximate Computing
An extensible perceptron framework for revision RTL debug automation
A Fail-Slow Detection Framework for HBM Devices
Row Planning and Placement for Hybrid-Row-Height Designs
Bounding buffer space requirements for real-time priority-aware networks
DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives
Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution
Word level functional coverage computation
The design of an i8080A instruction compatible processor with extended memory address
Automating Logic Rectification by Approximate SPFDs
Enabling RTOS simulation modeling in a system level design language
Stability analysis of active clock deskewing systems using a control theoretic approach
Large Forests and Where to "Partially" Fit Them
Diagonal routing in high performance microprocessor design
Rethink before Releasing Your Model: ML Model Extraction Attack in EDA
Use Cases and Deployment of ML in IC Physical Design
MuCCRA-3: a low power dynamically reconfigurable processor array
ALook: adaptive lookup for GPGPU acceleration
Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data
Layout recognition attacks on split manufacturing
Invited paper: Si Photonic Ring-Resonator-Based WDM Transceivers
Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique
An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic
Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB
Gate sizing and threshold voltage assignment for high performance microprocessor designs
A novel approach for digital waveform compression
The tangram framework (embedded tutorial): asynchronous circuits for low power
Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processors
On-chip thermal gradient analysis and temperature flattening for SoC design
Shared cache aware task mapping for WCRT minimization
Low power memristor-based ReRAM design with Error Correcting Code
CGTA: current gain-based timing analysis for logic cells
Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems
Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM code
Considering Testability during High-level Design (Embedded Tutorial)
Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays
Performance-driven circuit partitioning for prototyping by using multiple FPGA chips
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony
System-level verification of CDMA modem ASIC
A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS
Automatic design for analog/RF front-end system in 802.11ac receiver
Flexible processor based on full-adder/ d-flip-flop merged module
Non-slicing floorplans with boundary constraints using generalized polish expression
Multiple Independent Gate FETs: How many gates do we need?
Development of low power and high performance application processor (T6G) for multimedia mobile applications
Multithreaded coprocessor interface for multi-core multimedia SoC
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction
VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack
Machine learning and pattern matching in physical design
Crosstalk-aware statistical interconnect delay calculation
Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules
Flexible Spatio-Temporal Energy-Efficient Runtime Management
Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization
An overview of a compiler for mapping MATLAB programs onto FPGAs
Thread affinity mapping for irregular data access on shared Cache GPGPU
The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015
Practical Synthesis of Speed-Independent Circuits Using Unfoldings
Low-power design methodology and applications utilizing dual supply voltages
Cut-demand based routing resource allocation and consolidation for routability enhancement
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits
Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines
Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits
Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement
A novel memory size model for variable-mapping in system level design
On the futility of statistical power optimization
An efficient algorithm for stencil planning and optimization in E-beam lithography
A functional memory type parallel processor for vector quantization
Battery-aware task scheduling in distributed mobile systems with lifetime constraint
Analytical thruchip inductive coupling channel design optimization
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit
Building energy-efficient multi-level cell STT-RAM caches with data compression
High performance on-chip differential signaling using passive compensation for global communication
An unconditional stable general operator splitting method for transistor level transient analysis
Mathematical limits of parallel computation for embedded systems
Design Methodology for 2.4GHz Dual-Core Microprocessor
A CSIC implementation with POCSAG decoder and microcontroller for paging applications
XPPE: cross-platform performance estimation of hardware accelerators using machine learning
ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis
Area-constrained technology mapping for in-memory computing using ReRAM devices
ATM Cell Modelling using Objective VHDL
Anatomy of platform-based design: is it the savior of UDSM SoC design crisis?
CANNA: Neural network acceleration using configurable approximation on GPGPU
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs
Stitch aware detailed placement for multiple e-beam lithography
A dual-band image-reject mixer for GPS with 64dB image rejection
Programmable Neuromorphic Circuit based on Printed Electrolyte-Gated Transistors
Algorithms for compacting error traces
An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs
Pin Access-aware Multiple Via Pillar Co-Design for Routability Optimization
Mpache: Interaction Aware Multi-level Cache Bypassing on GPUs
ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier
Semi-supervised hotspot detection with self-paced multi-task learning
An optimized design for serial-parallel finite field multiplication over GF (2 m ) based on all-one polynomials
Search space reduction in high level synthesis by use of an initial circuit
Collaboration between university and industry
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology
Footfall - GPS polling scheduler for power saving on wearable devices
Extending pitchmaking algorithms to layouts with multiple grid constraints
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation
Efficient LUT-based FPGA technology mapping for power minimization
In-vehicle vision processors for driver assistance systems
Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars
Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variation
Test data compression technique using selective don't-care identification
VCore-based design methodology
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003
Redundant-via-aware ECO routing
Multi-Precision Deep Neural Network Acceleration on FPGAs
HAMPER: high-performance adaptive mobile security enhancement against malicious speech and image recognition
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms
A sub-mW MPEG-4 motion estimation processor core for mobile video application