yusuke1997/dblp-id-title huggingface dataset:
On Logical Fiberings and Decomposition of Many-Valued Operations: A Brief Survey
Fourier Decision Diagrams on Finite Non-Abelian Groups with Preprocessing
Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair Shaped I-V Curved Device as a Coupling Element
Realizing 4-input Functions with the Minimum Toffoli Gate Count
Logic Expressions of Monotonic Multiple-Valued Functions
Using Formal Verification and Robotic Evolution Techniques to Find Contradictions in Laws Concerning Police Rules of Engagement
Non-Binary Analog-to-Digital Converter Based on Amoeba-Inspired Neural Network
Positive Primitive Structures
On Many-Valued Modal Probabilistic Logics
Probabilistic and Truth-Functional Many-Valued Logic Programming
Multiple-Valued Decision Diagrams with Symmetric Variable Nodes
Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources
Inadmissible Class of Boolean Functions under Stuck-at Faults
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic
Efficiently Irreducible Bases in Multiple-Valued Logic
Remarks on the Structure of Matrix-Valued Spectral Transforms on Finite Non-Abelian Groups
A Study of Practical Causality Acquisition among Vital Signals
Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions
Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form
The Use of Arithmetic Operators in a Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Architecture
On a Logic Based on Fuzzy Modalities
Quaternary Generalized Boolean Bent Functions Obtained Through Permutation of Binary Boolean Bent Functions
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control
Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply Voltage
Unique Folding and Hysteresis Characteristics of RTD for Multi-Valued Logic and Counting Applications
On Hyper Co-Clones
Parallel and serial decompositions of multi-valued sequential machines
A Non-Commutative Multiple-Valued Logic
Multiple-Valued Combinational Circuits with Feedback
Bounding the Phase Transition on Edge Matching Puzzles
Dynamic Template Matching with Mixed-Polarity Toffoli Gates
First-Order Nelsonian Paraconsistent Quantum Logic
On the Synthesis of MVMT Functions for PLA Implementation Using CCDs
Algebraic Properties of a Learning Multiple-Valued Logic Network
Several Remarks on the Complexity of Set-Valued Switching Functions
Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead
Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis
Compact Propositional Gödel Logics
Arithmetic-Haar Spectral Transform Decision Diagrams
An Algebraic Approach Towards the Fine-Grained Complexity of Graph Coloring Problems
Bit-Level and Word-Level Polynomial Expressions for Functions in Fibonacci Interconnection Topologies
Computing Prime Implicants/Implicates for Regular Logics
A suggested approach to computer arithmetic for designers of multi-valued logic processors
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture
A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC
Ternary Decision Diagrams: Survey
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture
On Some Basic Aspects of Ternary Reversible and Quantum Computing
De Morgan Bisemilattices
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--
Lessons Learnt in the Implementation of Quantum Circuit Simulation Using Decision Diagrams
Energy Efficiency of Multi-bit delta-sigma Modulators Using Inverter-based Integrators
Amplification of the Functional Closure Operation
The Designing and Training of a Fuzzy Neural Hamming Classifier
A New Approach to Verification of Threshold Functions in Ternary Logic
Multiple-Valued Logic Computation Circuits Using Micro- and Nanoelectronic Devices
Properties of Independent Components of Self-Motion Optical Flow
Notes on Avron's Self-extensional Four-valued Paradefinite Logic
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs
Analog CMOS Spiking Neural Network for Time-Series Signal Recognition
An Axiomatization of Generalized Entropy of Partitions
Intersections of Isotone Clones on a Finite Set
Essentially Minimal Clones of Rank 3 on a Three-Element Set
Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions
Supplementary Symmetrical Logic Circuit Structure
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic
Kidney Tumor Recognition from Abdominal CT Images using Transfer Learning
Testability of Generalized Multiple-Valued Reed-Muller Circuits
Controlling the Memory During Manipulation of Word-Level Decision Diagrams
The Cardinality of the Set of All Clones Containing a Given Minimal Clone
Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters
Formal Design of Galois-Field Arithmetic Circuits Based on Polynomial Ring Representation
A Note on Realizing Multiple-Valued Logic Functions using Akers' Cells - Cell Sizes and Path Lengths
54th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2024, Brno, Czech Republic, May 28-30, 2024
Fast Logic Synthesis Based Upon Ternary Universal Logic Module f
A Novel Technology Mapping Method for AND/XOR Expressions
A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories
Aliasing in Multiple-Valued Test Data Compaction
Hardware-Compatible U-Net for Low-Dose PET Reconstruction
Exploiting Many-Valued Variables in MaxSAT
Weak bases for maximal clones
Discovery of Multiple-Valued Bent Functions in Galois Field and Reed-Muller-Fourier Domains
The Learning Aspects of the Fault Finder Expert System
Reasoning About Digital Systems
52nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2022, Dallas, TX, USA, May 18-20, 2022
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells
Online Monitoring of Distributed Systems with a Five-Valued LTL
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions
Evaluation and Symbol Classification of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping with Linear Mixture Model
Dreams for New-Device-Based Superchips: From Transistors to Enzymes
Automated Diagnosis of the Frequency of Uterine Peristalsis for Female Infertility
Generation of the Post Lattice by Irreducible Clones
On the Structure of Maximal Closed Sets of P K2
51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021, Nur-Sultan, Kazakhstan, May 25-27, 2021
Several Remarks on Non-Boolean Functions over Boolean Algebras
PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions
Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits
Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic
Generalized finite Post algebras
Multiple Peak Resonant Tunneling Diode for Multi-Valued Memory
Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial)
Analog-to-Digital Converters Using Not Multi-level But Multi-bit Feedback Paths
Matrix-Valued EXOR-TDDs in Decompositon of Switching Functions
Term Models of Horn Clauses over Rational Pavelka Predicate Logic
A Graph-Based Approach to Designing Parallel Multipliers over Galois Fields Based on Normal Basis Representations
Prefilters over an arbitrary Boolean Algebra
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures
On the Centralizers of Monoids in Clone Theory
Completeness Criteria in Set-Valued Logic Under Compositions with Union and Intersection
Infinite-Valued Lukasiewicz Logic Based on Principal Lattice Filters
A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic
Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra
On the Complexity of Enumerations for Multiple-Valued Kleenean Functions and Unate Functions
Petri Net Representation of Fuzzy Reasoning under Incomplete Information
Co-stone Residuated Lattices
Weakly Associative Functions on [0, 1] as Logical Connectives
Hyperoperations on {0, 1, 2} Based on Min, Max, and Universal Literal Operations
Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID)
Solution of the Last Open Four-Colored Rectangle-Free Grid: An Extremely Complex Multiple-Valued Problem
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits
Truth-Functionality, Rough Sets and Three-Valued Logics
A Deductive Neural-Logic System
An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction
Monoidal Intervals of Partial Clones
Controlling Uncertainty in Discretization of Continuous Data
Debugging of Reversible Circuits Using pDDs
A Four-Valued Modal Logic Arising from Monteiro's Last Algebras
Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation
Quotient Structures of Non-Commutative Residuated Lattices
Signal processing with delta-sigma modulated bitstreams for artificial neurons
On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults
Towards an Automated Framework for Realizing Quantum Computing Solutions
From Continuous to Multiple-valued Data
Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch
Normalization Theorem for Extended Intuitionistic Belnap-Dunn Logic
The Impact of Address Arithmetic on the GPU Implementation of Fast Algorithms for the Vilenkin-Chrestenson Transform
The Invariance of Spectral-Kolmogorov-Type Statistics for Estimating Genomic Similarity
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors
On the Clones Containing a Near-Unanimity Function
On Synthesis and Verification from Event Diagrams in a Robot Theatre Application
Paraconsistent Double Negation That Can Simulate Classical Negation
Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field
Linking Łukasiewicz Logic and Boolean Maximum Satisfiability
The Satisfiability Problem in Multiple-Valued Horn Formulae
Quaternary Cyclic AN Codes for Burst Error Correction
Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs
On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary MOS Bridge Circuits and Dynamic Circuits
Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group
Hyperclones on a Finite Set
Centralizing Monoids on a Three-Element Set Related to Binary Idempotent Functions
On Maximal Hyperclones on {0, 1} - A New Approach
Experiences of Parallel Processing with Direct Cover Algorithms for Multiple-Valued Logic Minimization
Quantum Pseudo-Fractional Fourier Transform Using Multiple-Valued Logic
ESOP-Inspired Synthesis Method for Ternary Permutative Quantum Circuits
Random Pattern Fault Simulation in Multi-Valued Circuits
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization
Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process
Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays
On the Mutual Definability of Fuzzy Tolerance Relations and Fuzzy Tolerance Coverings
Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer
A New Balanced Gate for Structural Testing
A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes
Frozen Boolean Partial Co-clones
Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic
A Design Method for Multiclass Classifiers
An Algorithm for the Solution of Multi-Valued Logic Programming
A Realization of Index Generation Functions Using Multiple IGUs
Digital Circuit Verification Using Partially-Ordered State Models
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits
Learning of the Non-threshold Functions of Multiple-Valued Logic by a Single Multi-valued Neuron with a Periodic Activation Function
On Some Classes of Fuzzy Information Granularity and Their Representations
A Filed Programmable Analog Array for Continuous, Fuzzy, and Multi-Valued Logic Applications
Clones of Incompletely Specified Operations
One Class of Maximal Binary Monomials
Layered MVL Neural Networks Capable of Recognizing Translated Characters
Qudit non-Clifford interleaved benchmarking
An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence
Some Properties of Local Partial Clones on an Infinite Set
Secure Design Flow for Asynchronous Multi-valued Logic Circuits
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators
An Overview of a Software Tool in Rough Non-deterministic Information Analysis
System for Automatic Generation of Parallel Multipliers over Galois Fields
Rational Transitivity and its Models
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades
The arithmetic properties of certain number systems
Synthesis of Ternary Grover's Algorithm
16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin
A Solution to a Problem of D. Lau: Complete Classification of Intervals in the Lattice of Partial Boolean Clones
Recursive Evaluation of the Generalized Reed-Muller Coefficients
From a Fuzzy Flip-Flop to a MVL Flip-Flop
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
Counting Problems and Clones of Functions
Logic Synthesis of Controllers for B-Ternary Asynchronous Systems
QSweep: Pulse-Optimal Single-Qudit Synthesis
Comparative Analysis of Full Adder Custom Design Circuit using Two Regular Structures in Quantum-Dot Cellular Automata (QCA)
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors
Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams
Properties of the Reed-Muller-Fourier Spectra of Maiorana-McFarland Bent Functions
Schauder Hats for the Two-Variable Fragment of BL
Tense Operators and Dynamic De Morgan Algebras
Implementation of Multiple-Valued CAM Functions by LUT Cascades
On Designing of 4-Valued Memory with Double-Gate TFT
On the Interval of Boolean Strong Partial Clones Containing Only Projections as Total Operations
Paraconsistent Circumscription: First-Order Case
Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits
A Quantum Photonic TRNG based on Quaternary Logic
Spectral Techniques: The First Decade of the XXI Century (Invited Paper)
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams
Concerning the Maximum Size of the Terms in the Realization of Symmetric Functions
A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean Functions
New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design
A Multilevel-Cell 32MB Flash Memory
Logical Model for Representing Uncertain Statuses of Multiple-Valued Logic Systems Realized by Min, Max and Literals
On Functions Defined on Free Boolean Algebras
Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions
On the Structures of Weak Interlaced Bilattice
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions
An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net
The Analysis of One Dimensional Multiple-Valued Linear Cellular Automata
Sierpinski Gaskets for Logic Functions Representation
A Proof Method for the Six-Valued Logic for Incomplete Information
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits
An Abstract Axiomatization of the Notion of Entropy
A Universal Logic Machine
Predicting the Development of Chronic Lung Disease in Neonataes from Chest X-ray Images Using Deep Learning
Realization of Associative Image Search: Development of Image Retrieval Platform for Enhancing Serendipity
NPN Calculi: A Family of Three Strict Q-Algebras
Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams
Implementation of Multiple-Valued Functions Using Literal-Splitting Technique
Topological Soft Algebra for the S5-Modal Fuzzy Logic
Specific Health Examination Data Prediction for Female Subjects with Unhealthy-Level Visceral Fat Using Self-Organizing Maps
Kleene-Stone Logic Functions
Biomorphic Analog Devices based on Reaction-Diffusion Systems
4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture
Many-Valued Tense Logic and the Problem of Determinism
Identification of Incompletely Specified Fuzzy Unate Logic Function
On Complete Residuated Many-Valued Logics with T-Norm Conjunction
Restriction-Closed Hyperclones
Rigidity Problem of Autodual Clones
On Functional Entropy
On Endoprimal Monoids in Clone Theory
Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates
Multiple-Valued Programmable Logic Arrays with Universal Literals
Projective Measurement-Based Logic Synthesis of Quantum Circuits
Helena Rasiowa - A View of the Academic Trajectory and the Influence upon Polish and the International Scientific Community
A Metasemantics to Refine Fuzzy If-Then Rules
Selection of Efficient Re-Ordering Heuristics for MDD Construction
Associativeness versus Recursiveness
MDD-Based Synthesis of Multi-Valued Logic Networks
Reversible Fast Permutation Transforms for Quantum Circuit Synthesi
Arrays vs. Decision Diagrams: A Case Study on Quantum Circuit Simulators
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture
Synthesis of Multiple-Valued Decision Diagrams using Current-Mode CMOS Circuits
On Equational Definability of Function Classes
Multi-Valued Decoder Based on Resonant Tunneling Diodes in Current Tapping Mode
Proof Systems for Gödel Logics with an Involution
Analysis of Faults in Reversible Computing
Mathematical properties of Boolean transformations
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4)
Synthesis of Reversible Synchronous Counters
Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions
MDD with Added Null-Value and All-Value Edges
A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares
A Predicate Variant of Two-Layered Many-Valued Probability Logic
Symbolic Algorithms for Token Swapping
Properties of the Two-Sided RMF Spectrum of Matrices
New Two-Qubit Gate Library with Entanglement
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control
A Formal Approach to Identifying Hardware Trojans in Cryptographic Hardware
Soft-Delay-Error Evaluation in Content-Addressable Memory
Entropies on Bounded Lattices
A simultaneous, radix four, I2L multiplier mechanized via repeated addition
A Characterization of r-Valued Functions Monotonic in an Order Based on Regularity
Fault Analysis of the Multiple Valued Logic Using Spectral Method
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH
An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD
Resonant Tunneling Diodes for Multi-Valued Digital Applications
Logic design of multi-valued I2L logic circuits
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model
Approximate Reasoning in Strength Logic
Multiple Valued Logic Algebra for the Synthesis of Digital Circuits
A Necessary and Sufficient Condition for Lukasiewicz Logic Functions
Notes on Majority Boolean Algebra
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm
A Novel Machine Learning Algorithm to Reduce Prediction Error and Accelerate Learning Curve for Very Large Datasets
On the Optimisation of Reed-Muller Expressions
Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore
Gaze Estimation Using Electrooculogram Signals and Its Mathematical Modeling
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k -Ary Operations
Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions
Learning subjective probabilities from a small data set
Multiple-Valued Logics for Theorem-Proving in First Order Logic with Equality
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic
The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit
HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays
Debiasing Method for Efficient Ternary Fuzzy Extractors and Ternary Physically Unclonable Functions
Minimal Cut Vectors and Logical Differential Calculus
Polynomial Functions on a Central Relation
Worst Case Number of Terms in Symmetric Multiple-Valued Functions
Gate Model Networks for Minimization of Multiple-Valued Logic Functions
A Finite Basis of the Set of All Monotone Partial Functions Defined over a Finite Poset
Power of Enumeration - BDD/ZDD-Based Techniques for Discrete Structure Manipulation
Complex spectral logic
Note on Resolution Approximation of Many-Valued Logics
Contributions of K. C. Smith in Applications of Multiple-Valued Logic
On the Generation of (Minimal) Clones Containing Near-Unanimity Operations
The Incidence Propagation Method
Development of Patient Information Extraction Method by Sequence Labeling using Electronic Medical Records
Equations in the Algebra of Logic
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Semirigid Systems of Equivalence Relations
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits
Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator
Efficient Simulation-Based Debugging of Reversible Logic
Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique
Fine-Grained Complexity of Constraint Satisfaction Problems through Partial Polymorphisms: A Survey
Representation Theorems and the Semantics of (Semi)Lattice-Based Logics
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
Completeness Theory for Vector Partial Multiple-Valued Logic Functions
An Investigation into the Implementation Costs of Residue and High Radix Arithmetic
Fault Simulation in Sequential Multi-Valued Logic Networks
On Input Permutation Technique for Multiple-Valued Logic Synthesis
On the Lattice of Partial Clones on a Finite Set
Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits
Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables
Using SPIN to Check Nondeterministic Simulink Stateflow Models
A Proposal and an Application of a Career-Mode Membership Function