yusuke1997/dblp-id-title huggingface dataset:
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c
Duty Cycle and Input-to-Output Voltage Transfer Functions of Tapped-Inductor Buck DC-DC Converter
CMOS adaptive TIA with embedded single-ended to differential conversion for analog optical links
CAMEL: Capacitive Analog In-Memory Equalization for RF Signal Processing
Speech pitch detection in noisy environment using multi-rate adaptive lossless FIR filters
A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching
Detection of biochemical molecules using CM-SOFFET based biosensor
A 24-mW 28-Gb/s wireline receiver with low-frequency equalizing CTLE and 2-tap speculative DFE
Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks
Design of optimum interpolation filters for digital demodulators
Improved modeling of sigma-delta modulator non-idealities in Simulink
TDD-based Asymmetrical Ethernet Physical Layer for Automotive Applications
Project-Based Learning: Bridging the Gap Between Algorithm and Architecture in Neural Network Course
Design of a low-power pulse-triggered flip-flop with conditional clock technique
Towards accurate visual information estimation with Entropy of Primitive
On an implementation of differential and quadrature Colpitts injection-locked frequency dividers
Interactive visual information retrieval
A Batteryless Electrochemical Sensing System IC Based on Intra-Body Power and Data Transfer Towards Miniaturized Wearable Sensor Nodes
A New Algorithm for Sorting Problem with Reformed CAM
Importance Splitting Sample Point Reuse for Efficient Memory Yield Estimation
Complete controllability of power system dynamics
Live demonstration: Off-chip learning for hardware hand-sign recognition system
A scalable and fault-tolerant routing algorithm for NoCs
Process variation independent built-in current sensor for analogue built-in self-test
On the Benefit of Adopting Saturable Inductors in Switching-Mode Power-Supplies: A Case Study
Two-step quantization architectures for multibit ΔΣ-modulators
A Multi-Load Capacitive Power Transfer System Using Class-E Inverter
AES design improvement towards information safety
An 80 A, 2 to 25 ns Configurable Pulse-Width Integrated CMOS Pulsed Laser Driver with On-Chip Mounted Laser Diode
A Portable Electronic Nose System that Can Detect Fruity Odors
New compact and power efficient dynamically biased cascode mirrors and telescopic op-amps
AER Auditory Filtering and CPG for Robot Control
Two-step Classification Neuron Circuits for Low-power and High-integration SNN Systems
Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power
Synthesis of partition-codec architecture for low power and small area circuit design
Litho-driven layouts for reducing performance variability
An accurate small-signal modelling approach for switching DC-DC converters
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability
Human Activity Recognition Using Wi-Fi Signals based on Tokenized Signals with Attention
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects
Neural Network Architecture Using Random-Pulse Data Processing
Blind MLSE based on the matched filter estimation using the CMA
A gm/Id based methodology to estimate OTA requirements in low-pass discrete time Σ∆-ADCs
Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power
A 200ns settling time fully integrated low power LDO regulator with comparators as transient enhancement
High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor
A 96×64 intelligent digital pixel array with extended binary stochastic arithmetic
Design of class DE amplifier with nonlinear shunt capacitances for any output Q
Hardware-efficient random sampling of fourier-sparse signals
SAR-MemPipe: A Hybrid Pipeline-SAR Memristive ADC for Analog Resistive Arrays
A 2.4 GHz CMOS power amplifier using internal frequency doubling
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator
Design-oriented Characterisation of Adaptive Asynchronous SigmaDelta Modulation Switching Power Amplifiers for Bandlimited Signals
Optical Flow-Guided Mask Generation Network for Video Segmentation
Live Demonstration: Event-Driven Serial Communication on Optical Fiber
A saliency detection model based on sparse features and visual acuity
A 28-nm, 0.5-V, 78.5-nA Switched Capacitor Current Reference with Active Trimming for sub-1V Implantable Medical Devices
Evolution of Locality on Ethereum Transaction Network
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems
A family of redundant multipliers dedicated to fast computation for signal processing
Low complexity digital PLL for instant acquisition CDR
A 0.74 μJ/decision and 22.59 TOPS/W Keyword Spotting CIM Processor with Short-Current-Free Multi-level ReRAM and Adaptive-Decision-Level Nonlinear ADC
A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range
A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications
Extreme Generative Human-Oriented Video Coding via Motion Representation Compression
Improving dictionary based image super-resolution with nonlocal total variation regularization
An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing
Analog Deep Neural Network Based on NOR Flash Computing Array for High Speed/Energy Efficiency Computation
Semi-blind data-selective algorithms for channel equalization
Multi-stage delta-sigma modulator with a relaxed opamp gain using a back-end digital integrator
Linear prediction using homomorphic deconvolution in the autocorrelation domain
Thermo-visual video fusion using probabilistic graphical model for human tracking
Resource Efficient Pre-processor for Drift Removal in Neurochemical Signals
Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced Dataset
RF circuit and system innovations for a new generation of wireless terminals
Obtaining Partial Solutions for Divergent State Estimation Problems in Large Power Systems
Novel design technique for highly linear current mode amplifiers. Analysis, design, simulations
A BiCMOS time-to-digital converter with 30 ps resolution
Clonable PUF: on the Design of PUFs That Share Equivalent Responses
A High-Speed and Compact On-Chip CMOS Temperature Sensor for 3D-NAND Flash Memory
A dual-field elliptic curve cryptographic processor based on a systolic arithmetic unit
Low-power CDMA analog matched filters based on floating-gate technology
Enabling phase-change memory for data-centric computing: Technology, circuitand system
Maximum Power Point Tracking MPPT Algorithm for Kinetic Energy Harvesters
A Low-power Pyramid Motion Estimation Engine for 4K@30fps Realtime HEVC Video Encoding
Fully Scalable Multiview Wavelet Video Coding
Phase Noise Integration Limits for Jitter Calculation
A current limiter for LDO regulators with internal compensation for process and temperature variations
Benchmarking Analogue Performance of Emerging Random Access Memory Technologies
Bounding of thermal Sigma-Delta modulators output for sensors
A side-channel resistant implementation of AES combining clock randomization with duplication
Design and implementation of high-speed arbiter for large scale VOQ crossbar switches
Side Match Distortion based Adaptive Error Concealment order for 1Seg Video Broadcasting Application
Parallel multi-level simulation of wireless sensor networks
Analysis of Deep Learning Models Towards High Performance Digital Predistortion for RF Power Amplifiers
Improved performance estimation and optimization for chaos-based asynchronous DS-CDMA systems
The design of asymmetrical square-root pulse-shaping filters with wide eye-openings
An improved push-pull driver using 0.13μm CMOS
Blind closed-form DOA estimation for distributed sources
A new approach for electrothermal analysis of electronic circuits
Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers
Joint Barcode and Text Orientation Detection Model for Unmanned Retail System
Online Feedback Region Detection and Flying Capacitor Balancing Technique for Multi-Level Converters
A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling
Learning-based occupancy behavior detection for smart buildings
Gate-level netlist reverse engineering for hardware security: Control logic register identification
Harmonic Control Network for 2.6 GHz CMOS Class-F Power Amplifier
EAS-CiM 2.0: Event-driven Asynchronous Stream-based Compute-in-Memory Kernels with Scalable Precision
Video Motion Estimation Using a Neural Network
Characterization and design of oversampled linear phase filterbanks with rational oversampling ratio
Low-voltage sigma-delta modulator topologies for broadband applications
The Algorithmic and Architectural Optimizations for Highly Efficient Tensor Decomposition Engines
Design and Characterization of Radiation-Hardened MCU for Space Application using Error Correction SRAM and Glitch Removal Clock Buffer Cell
Algorithm for fault localization on a digital microfluidic biochip using particle swarm optimization technique
Roundoff noise minimization in two-dimensional state-space digital filters using error feedback
Complex dynamics in a class of nearly-symmetric competitive CNNs
Minimum mean square error receive filters for carrierless amplitude and phase modulation
A DEM Structure Based on Random Combination Group Encoding toward a Reduced Circuit Area
Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps
General-purpose ripple-based fast-scale instability prediction in switching power regulators
Theoretical and experimental analysis of Dickson charge pump output resistance
An SRAM Compute-In-Memory Macro Based on Direct Coupling SAR ADC and DAC Reuse
Stability analysis of the class of delayed neural networks
Live demonstration: An ultra-low power PFM IR-UWB system for short-range audio streaming
Limit cycle counting based smart background calibration of continuous time sigma delta ADCs
Si Memristive devices applied to memory and neuromorphic circuits
A New Handheld Biochip-based Microsystem
A Novel Driver Circuit on Crosstalk Suppression in SiC MOSFETs
Estimation of range-Doppler radar images
Decentralized H infinity load frequency control using LMI control toolbox
Suppression of acoustic oscillations in hearing aids using minimum phase techniques
Quaternion neural networks towards Real-time image processing
A piecewise-linear simplicial coupling cell for CNN gray-level image processing
A high throughput CAVLC design for HEVC
Timing error measurement for highly linear wideband Digital to Analog Converters
A 0.9-V 22.7-ppm/°C Sub-Bandgap Voltage Reference with Single BJT and Two Resistors
A low voltage CMOS bandgap reference circuit
A power scalable receiver front-end at 2.4 GHz
Power modeling and low-power design of content addressable memories
A CMOS Direct-Digital BPSK Modulator Using an Active Balun and Common-Gate Switches
On designing OTA-C graphic-equalizers with MOSFET-triode transconductors
A power-aware ME architecture using subsample algorithm
Bayesian Source Localization Using Stochastic Computation
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme
A simple analog CMOS design tool using transistor dimension-independent parameters
Analysis on an alternative structure of damping-factor-control frequency compensation
A one-shot digital correlated double sampling with a differential difference amplifier for a high speed CMOS image sensor
Training-Based Estimation of Correlated MIMO Fading Channels in the Presence of Colored Interference
A 2-pin input multi frequency power scavenging unit for wireless sensor nodes and RFID tags
A memristor based image sensor exploiting compressive measurement for low-power video streaming
Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding
A new design method to modulo 2 n -1 squaring
The Dynamic Locking Heuristic - A New Graph Partitioning Algorithm
Measuring Dependence of Bin-wise Separated Signals for Permutation Alignment in Frequency-domain BSS
Dynamic SIMD re-convergence with paired-path comparison
A New Approach for Estimation of RDS(on) of Power Arrays: Extensions and Experimental Results
Reflection and transmission of phase-inversion-waves in oscillators coupled by two kinds of inductors
Controlling Chaos in Duffing System using Impulsive Parametric Perturbations
Live Demonstration: A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Low-power Applications
On the performance analysis of the subband adaptive digital filter
Implementation of Farrow structure based interpolators with subfilters of odd length
A statistical MAC protocol for heterogeneous-traffic human body communication
A 5.7µW/Channel Folded-Current-Mirror-Based Reconfigurable Multimodal Neural Recording IC with Improved Hardware Availability
Automated placement of reconfigurable regions for relocatable modules
A Power-Saving Technique for Bit-Serial DSP ASICs
Reference-less SAR ADC for on-chip thermal monitoring in CMOS
A piezoelectric actuator driver circuit for automatic focusing of mobile phone cameras
From Circuit to Mechatronic System Tolerance Optimization
Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU
Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs
A Parallel Trimming Method of Offset Reduction for Comparators and Amplifiers
CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients
On passive and active compatible impedances
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP
Interface design approach for system on chip based on configuration
A wide dynamic range CMOS image sensor with the optimum photoresponse per pixel
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway
Minimizing charge injection errors in high-precision, high-speed SC-circuits
RMS voltage control with harmonic compensation for parallel-connected inverters feeding non-linear loads
Amalgamating Knowledge for Comprehensive Classification with Uncertainty Suppression
A 72-µW 90-dB Wide-Range Potentiostatic CMOS ΔΣ Modulator with Flicker Noise Cancellation for Smart Electrochemical Sensors
Concurrent error detection in Reed Solomon decoders
Techniques for Dual-Band LNA Design using Cascode Switching and Inductor Magnetic Coupling
On the density of periodic windows for the Rössler system
An LPTV Programmable Bandpass True-time-delay Line Without External Clock-phase Shifter
Live demonstration: Unipolar symmetrical variable-capacitance generators for energy harvesting
Time-Mulitplexing CNN Simulator
Class E isolated DC-DC converter using PWM synchronous rectifier
Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing
D-PET: A direct 6 DoF pose estimation and tracking system on graphics processing units
Fast tracking conjugate gradient algorithm
Nonuniform sampling driver design for optimal ADC utilization
Exploiting Self-Capacitances for Wireless Power Transfer
Efficient simulation model for DAC dynamic properties
Resistors layout for enhancing yield of R-2R DACs
An Eleven-Leads ECG recording SoC for Ultralow-Power Wearable Applications
A high speed centroid computation circuit in analog VLSI
Using motion primitives to enforce vehicle motion constraints in sampling-based optimal planners
A DLL-based injection-locked frequency synthesizer for WiMedia UWB
Hardware Implementation of a Low-complexity Detector for Large MIMO
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation
A low-power monolithically stacked 3D-TCAM
MPEG-4 codec based uplink resource allocation scheme for the video telephony service in WiBro/WiMAX systems
A Hybrid Meta-heuristic Method for Optimal Allocation of UPFCs
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant
Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging
A Low-Power, Versatile Capacitance Interface ASIC Based on Pulse-Width Modulation with Real-Time Dynamic Range Matching
Mismatch-shaping serial digital-to-analog converter
Limitations of the classical phase-locked loop analysis
A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradation
Machine Learning for Respiratory Detection Via UWB Radar Sensor
Accelerating massive MIMO in 6G communications by analog in-memory computing circuits
Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators
Neuromorphic FeRAM-Based Co-Design for Imaging Enhancement in Handheld Photoacoustic Systems
Applications of nonlinear dynamics to the turbo decoding algorithm
Lossless Two-Layer Coding using Histogram Packing Technique for HDR Images
Power-aware implementation of ASIC/SOC in 0.13 micron CMOS technology
AI-based System for Brain Tumor Segmentation and 3D Visualization
A 12.1-16.5GHz Resistance Self-biased Inverse Class-F23 VCO Achieving 20-54kHz 1/f 3 Corner Frequency
A compact, programmable, 17 mV to 10 V compliant, current source for neural stimulation
Distributed LC resonant clock tree synthesis
A hybrid space-time and collaborative coding scheme for wireless communications
A minimum variance filter for discrete-time linear systems perturbed by unknown nonlinearities
Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition
Optimal placement of multi-type FACTS devices by hybrid TS/SA approach
A novel low-power reconfigurable FFT processor
Hopfield networks with an infinite number of cells
Pipeline AER arbitration with event aging
Linear-phase Filters Configured as a Combination of Sigma-delta Modulator, SC Transversal Filter and a Low- Q Biquad
Cache Miss-Aware Dynamic Stack Allocation
Finite Gain-Bandwidth of Q Enhancement in Bandpass CT ΣΔ Modulator and Compensation
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]
A generalized approach to design CT ΣΔMs based on FIR DAC
FGS+: optimizing the joint SNR-temporal video quality in MPEG-4 fine grained scalable coding
Design for an intelligent surveillance system based on system-on-a-programmable-chip platform
Compression performance of high efficiency video coding (HEVC) working draft 4
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints
New algorithms for computing the minimum eigenpair of the generalized symmetric eigenvalue problem
Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit
Design of high order audio sigma-delta modulators with minimum weighted noise
A multi-input multi-output adaptive FIR filter with guaranteed convergence for feedforward ANC system
A new mesochronous clocking scheme for synchronization in SoC
Dual Graph Regularized Sparse Nonnegative Matrix Factorization for Data Representation
Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms
Sparse linear arrays for estimating and tracking DOAs of signals with known waveforms
Pulse-mode link for robust, high speed communications
Area-Efficient Matrix-Vector Polynomial Multiplication Architecture for ML-KEM Using Interleaving and Folding Transformation
Design and realisation of a nano-inductance for integrated power converters
Glass Break Detector Analog Front-End Using Novel Classifier Circuit
Synchronization of first-order time-delay systems generating n-scroll chaotic attractors
An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators
A low-power high-linearity CMOS baseband filter for wideband CDMA applications
Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis
High-level design synthesis with redundancy removal for high speed testable adders
A memory mapping approach for parallel interleaver design with multiples read and write accesses
Rate-distortion and energy performance of HEVC and H.264/AVC encoders: A comparative analysis
Space-time Rake receiver with optimal beamforming for the uplink of CDMA-based wireless systems
Two-dimensional angle and polarization estimation using ESPRIT without pairing
A 1 GHz 27 mW Low-Power Direct Digital Synthesizer for RF Carrier Signal Generation in Trapped-Ion Quantum Computer Operating at 9.4K
Optimal circuit clustering with variable interconnect delay
A Low-Voltage CMOS Op Amp with Rail-to-Rail Constant-gm Input Stage and High-Gain Output Stage
An error-controlled methodology for approximate hierarchical symbolic analysis
Generalized 2D lattice structure for causal and noncausal modeling of random fields
Reinforcement learning neural network circuits for electronic nose
Design of Motion Compensation Filters for Frequency Scalable Coding - Drift Reduction
A comparison of two adaptive equalizers: DFE and ACE
A Method of Representative Fault Selection in Digital Circuits for ATPG
Adaptive multimedia access: from user needs to semantic personalisation
Cascade/Parallel Form FIR Filters with Power-of-Two Coefficients
Analysis of PCB interconnects using electromagnetic reduction technique
High-Level Specification of Behavioural Hardware Models with MODES
Built-in self testing of high-performance circuits using twisted-ring counters
A novel 12-bit current-steering DAC with two reference currents
Enhancement of blind watermark retrieval in drift-compensated MPEG video
Watermarking in Conjugate Ordered Dither Block Truncation Coding Images
C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs
A Hybrid SST-CML Full Duplex Simultaneous Bi-Directional Signaling Link
Portable Sensor System for Real-Time Monitoring of Dust Deposition in Space Applications
Bifurcation analysis of arcing in DC automotive 48 V power supply systems
Enhanced chaotic image encryption algorithm based on Baker's map
Machine Learning-Driven Multiple Transform Selection for Low-Complexity VVC Encoding
Rate-distortion optimized bit allocation for error resilient video transcoding
Poisson models for noisy nonlinear devices
De-Noising via Wavelet Transforms Using Steerable Filters
Fundamental frequency parabolic PWM controller for lossless soft-switching boost power factor correction
Low-power global/rolling shutter image sensors in silicon on sapphire technology
Jitter in oscillators with 1/f noise sources
A CMOS infrared optical signal processor for remote control
Mismatch Compensation Technique for Inverter-Based CMOS Circuits
A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation
Charge pump optimization and output spur reduction in VCO-based OTAs for active-RC analog filters
A Sub-1pJ/bit Laser Power Independent 32Gb/s Silicon Photonic EAM Driver in 65nm CMOS
On the Implementation of Data Security for Neurostimulation Devices
Early Characterization of Soil Microbial Fuel Cells
eSSpMV: An Embedded-FPGA-based Hardware Accelerator for Symmetric Sparse Matrix-Vector Multiplication
Achieving optimal rate-distortion performance in arbitrarily-shaped transform coding
Channel Operating Margin as Transceiver Architecture Design Tool
A feature-based image registration technique for images of different scale
A Wideband Open-Loop Residue Amplifier for a 7-bit 10GS/s Two-Step Flash ADC in 22nm SOI CMOS Process
1.5-V 900-µW 40-dB CMOS variable gain amplifier
Inference of Parameterized Fourier Transforms
Rank identification for an analog ranked order filter
Design of nonlinear-phase FIR digital filters: a semidefinite programming approach
Spurious emissions reduction using multirate RF transmitter
Voltage regulation with power curtailment in a single-phase grid-connected PV inverter
Influence of the conductor design on the temperature field in a high voltage gas insulated switchgear