yusuke1997/dblp-id-title huggingface dataset:
Threshold-based obfuscated keys with quantifiable security against invasive readout
Multiple tunable constant multiplications: Algorithms and applications
Efficient Exploration of the SoC Communication Architecture Design Space
Closing the Gap: Advantages of Block-Level over Gate-Level in 3D IC Design for Advanced Nodes
Timing and security analysis of VANET-based intelligent transportation systems: (Invited paper)
SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memories for Energy Efficient Associative Search
AI-Driven Multi-Die Architecture Exploration
Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits
AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search
Vectorless Analysis of Supply Noise Induced Delay Variation
MOSFET modeling for 45nm and beyond
A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring
Simulation-based techniques for dynamic test sequence compaction
Security-aware mapping for TDMA-based real-time distributed systems
Nonvolatile memristor memory: Device characteristics and design implications
Intellectual property protection by watermarking combinational logic synthesis solutions
Peak Power and Dynamic IR-drop Assessment via Waveform Augmenting
Timing models in VAL/VHDL
Topologically constrained logic synthesis
Residual-INR: Communication Efficient On-Device Learning Using Implicit Neural Representation
Analog behavior in custom IC variation-aware design
PURE: Using Verified Remote Attestation to Obtain Proofs of Update, Reset and Erasure in low-End Embedded Systems
Hierarchical compiled event-driven logic simulation
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system
Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016
Software-Assisted Cache Replacement Mechanisms for Embedded Systems
Process variability-aware transient fault modeling and analysis
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
Improving last level cache locality by integrating loop and data transformations
Efficient Boolean characteristic function for fast timed ATPG
Application-driven synthesis of core-based systems
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
Automated Design Space Exploration in High-Level Physical Synthesis
Design automation towards reliable analog integrated circuits
A polynomial time algorithm for solving the word-length optimization problem
PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization
Exploiting STI stress for performance
Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits
Principle Hessian direction based parameter reduction with process variation
Optimizing data layout and system configuration on FPGA-based heterogeneous platforms
A specified delay accomplishing clock router using multiple layers
Width minimization of two-dimensional CMOS cells using integer programming
Noise Analysis for Optical Fiber Communication Systems
Barber: Balancing Thermal Relaxation Deviations of NISQ Programs by Exploiting Bit-Inverted Circuits
An efficient method for hot-spot identification in ULSI circuits
Analyzing and Improving Resilience and Robustness of Autonomous Systems
A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits
Challenges for Building a Cloud Native Scalable and Trustable Multi-tenant AIoT Platform
Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic Synthesis
An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0
E-PROOFS: a CMOS bridging fault simulator
Tautology Checking Using Cross-Controllability and Cross-Observability Relations
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects
SpikeSynth: Energy-Efficient Adaptive Analog Printed Spiking Neural Networks
On interactions between routing and detailed placement
DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks
Channel-driven global routing with consistent placement (extended abstract)
A novel scan architecture for power-efficient, rapid test
Mixed-Mode Incremental Simulation and Concurrent Fault Simulation
Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation
ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs
Statistical based link insertion for robust clock network design
Localized watermarking: methodology and application to operation scheduling
Planning and placing power clamps for effective CDM protection
Decomposition and factorization of sequential finite state machines
LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling
Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation
On the numbers of variables to represent sparse logic functions
Optimal wafer probe testing and diagnosis of k-out-of-n structures
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration
Invited Paper: BitMedViT: Ternary-Quantized Vision Transformer for Medical AI Assistants on the Edge
Power estimation for cycle-accurate functional descriptions of hardware
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns
MPME-DP: multi-population moment estimation via dirichlet process for efficient validation of analog/mixed-signal circuits
A flexibility aware budgeting for hierarchical flow timing closure
A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design
VLSI design parsing (preliminary version)
ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceivers
Differentiable Edge-based OPC
SALSA: A New Approach to Scheduling with Timing Constraints
Rethinking split manufacturing: An information-theoretic approach with secure layout techniques
PowerRush: A linear simulator for power grid
ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-Decomposition
Towards formal verification of analog designs
LLM-on-the-Palm: Mobile LLM Inference with PIM-Enhanced NAND Flash Memory
Fortifying the NAND Flash Supply Chain with Innovative Security Primitives
H3D: Heterogeneous Resources Aware Global Router for Face-to-Face Bonded 3D ICs
Boolean techniques for low power driven re-synthesis
Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications
Yoda: a framework for the conceptual design VLSI systems
SpOctA: A 3D Sparse Convolution Accelerator with Octree-Encoding-Based Map Search and Inherent Sparsity-Aware Processing
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors
Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors
Fast Poisson solvers for thermal analysis
Simulation of high-Q oscillators
Tagged Sentential Decision Diagrams: Combining Standard and Zero-suppressed Compression and Trimming Rules
GPU acceleration of RSA is vulnerable to side-channel timing attacks
Unlocking fine-grain parallelism for AIG rewriting
PLA decomposition with generalized decoders
RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis
HLScope+, : Fast and accurate performance estimation for FPGA HLS
Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking method
Domino logic synthesis using complex static gates
NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction
A fault simulation method based on stem regions
Asymptotic probability extraction for non-normal distributions of circuit performance
Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors
A high efficiency full-chip thermal simulation algorithm
Decomposition methods for library binding of speed-independent asynchronous designs
Optimization of interconnects between accelerators and shared memories in dark silicon
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018
One-Dimensional Deep Image Prior for Curve Fitting of S-Parameters from Electromagnetic Solvers
Improved flop tray-based design implementation for power reduction
Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip
Acceleration Method for Learning Fine-Layered Optical Neural Networks
Alternative design methodologies for the next generation logic switch
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams
Core integration: overview and challenges
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Statistical path selection for at-speed test
Memory organization and data layout for instruction set extensions with architecturally visible storage
BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural Networks
Vectorless verification of RLC power grids with transient current constraints
An Event-driven Neuromorphic System with Biologically Plausible Temporal Dynamics
An integrated algorithm for combined placement and libraryless technology mapping
TAP-CAM: A Tunable Approximate Matching Engine based on Ferroelectric Content Addressable Memory
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
On optimal extraction of combinational logic and don't care sets from hardware description languages
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning
Design and CAD challenges in 45nm CMOS and beyond
Power-Down Circuit Synthesis for Analog/Mixed-Signal
Security Analysis of Proactive Participation of Smart Buildings in Smart Grid
Automatic test generation for linear digital systems with bi-level search using matrix transform methods
Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI Segmentation
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications
Verifying Conformance of Neural Network Models: Invited Paper
WireLisp: combining graphics and procedures in a circuit specification language
Overview of 2019 CAD Contest at ICCAD
BOOM - A Heuristic Boolean Minimizer
PHDD: an efficient graph representation for floating point circuit verification
Software synthesis through task decomposition by dependency analysis
An Effective Analytical Placement Approach to Handle Fence Region Constraint
Online fault detection and tolerance for photovoltaic energy harvesting systems
A power modeling and characterization method for the CMOS standard cell library
Automatic Verification and Identification of Partial Retention Register Sets for Low-Power Designs
Energy-Efficient Control Adaptation with Safety Guarantees for Learning-Enabled Cyber-Physical Systems
CODECS: a fixed mixed-level device and circuit simulator
Touch and Cross Router
Architecture driven circuit partitioning
LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration
High-level variable selection for partial-scan implementation
Diff-DiT: Temporal Differential Accelerator for Low-bit Diffusion Transformers on FPGA
HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline
A timing dependent power estimation framework considering coupling
Automatic memory reductions for RTL model verification
Manufacturing-Aware Physical Design
Simulation methods for RF integrated circuits
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications
FlexTEE: Dynamically Enhancing Metadata Locality Through Affine Address Transformation for Heterogeneous & Secure AI Platforms
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
Optimal layout via Boolean satisfiability
Making Fourier-envelope simulation robust
Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines
Analytical modeling of crosstalk noise waveforms using Weibull function
Redundancy-aware electromigration checking for mesh power grids
LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate Networks
Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic Circuits
A fast band-matching technique for interconnect inductance modeling
Fault modeling and simulation for crosstalk in system-on-chip interconnects
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing
SHILPA: a high-level synthesis system for self-timed circuits
Energy-optimal dynamic thermal management for green computing
A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural Network
Multithreaded pipeline synthesis for data-parallel kernels
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Simultaneous information flow security and circuit redundancy in Boolean gates
A self-adjusting clock tree architecture to cope with temperature variations
Concurrent Weight Encoding-based Detection for Bit-Flip Attack on Neural Network Accelerators
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow
Rubber Band Routing and Dynamic Data Representation
Observation Point Insertion Using Deep Learning
PLA optimization using output encoding
Routability-Aware Pin Access Optimization for Monolithic 3D Designs
Synthesizing Petri nets from state-based models
Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors
CAD challenges in multimedia computing
Design automation methodology and tools for superconductive electronics
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes
A new approach for factorizing FSM's
TAG: Learning Circuit Spatial Embedding from Layouts
On proving the efficiency of alternative RF tests
Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Power optimization in disk-based real-time application specific systems
Virtual screening: a step towards a sparse partial inductance matrix
SimPL: An effective placement algorithm
NearUni: Near-Unitary Training for Efficient Optical Neural Networks
Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor
HYPER-LP: a system for power minimization using architectural transformations
Explainable and Layout-Aware Timing Prediction
Testing automotive embedded systems under X-in-the-loop setups
Boolean factoring and decomposition of logic networks
Hardware Computation Graph for DNN Accelerator Design Automation without Inter-PU Templates
High-level synthesis: an essential ingredient for designing complex ASICs
Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs
Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction
System Level Design with Spade: an M-JPEG Case Study
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching
A write-time based memristive PUF for hardware security applications
Topological Routing Using Geometric Information
DeepFreeze: Cold Boot Attacks and High Fidelity Model Recovery on Commercial EdgeML Device
DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints
Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration
Fast lithographic mask optimization considering process variation
Critical path issue in VLSI design
Energy optimization for a two-device data flow chain
Knowledge Based Design Flow Management
SEFOP: a novel approach to data path module placement
ICCAD Special Session Paper: Quantum Variational Methods for Quantum Applications
Characterizing within-die variation from multiple supply port IDDQ measurements
Cryptoraptor: high throughput reconfigurable cryptographic processor
NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data
Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits
VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology
Invited Paper: Unitho: A Unified Multi-Task Framework for Computational Lithography
Single flux quantum circuit technology and CAD overview
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control
Approximate timing analysis of combinational circuits under the XBD0 model
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs
Response shaper: a novel technique to enhance unknown tolerance for output response compaction
SPRoute: A Scalable Parallel Negotiation-based Global Router
Efficient solution space exploration based on segment trees in analog placement with symmetry constraints
The Effects of False Paths in High-Level Synthesis
SAT Solving using FPGA-based Heterogeneous Computing
Gate-size selection for standard cell libraries
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
A framework for predictive dynamic temperature management of microprocessor systems
Security for safety: a path toward building trusted autonomous vehicles
Efficient mixed-domain analysis of electrostatic MEMS
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction
Simulating mixed analog-digital circuits on a digital simulator
Neuromorphic modeling abstractions and simulation of large-scale cortical networks
GPU-Accelerated Rectilinear Steiner Tree Generation
SETS: Stochastic execution time scheduling for multicore systems by joint state space and Monte Carlo
Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise
Fast physics-based electromigration analysis for multi-branch interconnect trees
An efficient technique for synthesis and optimization of polynomials in GF(2 m )
Pessimism reduction in crosstalk noise aware STA
A combined hierarchical placement algorithm
Cooperative parallelization
CAD for displays!
Functional modeling compiler for system-level design of automotive cyber-physical systems
FastRoute: a step to integrate global routing into placement
Mixed-size placement via line search
PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design
Fast and robust quadratic placement combined with an exact linear net model
Enabling exact delay synthesis
On testing delay faults in macro-based combinational circuits
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks
Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
Defect Clustering-Aware Spare-TSV Allocation for 3D ICs
A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance
Incremental formal design verification
REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect
Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling
Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens
HyperEF: Spectral Hypergraph Coarsening by Effective-Resistance Clustering
Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells
SRAM dynamic stability: theory, variability and analysis
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
UST/DME: A Clock Tree Router for General Skew Constraints
Efficient statistical validation of machine learning systems for autonomous driving
Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs
Multiple clock domain synchronization in a QBF-based verification environment
Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuits
An enhanced flow model for constraint handling in hierarchical multi-view design environments
LOT: logic optimization with testability-new transformations using recursive learning
Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces
CoXplorer: Multi-Staged Co-Exploration Framework for AI Model Compression and Accelerator Design
Accurate on-chip router area modeling with Kriging methodology
Energy reduction for STT-RAM using early write termination
NORNS: Three Guides for Efficient Automatic Post-Fabrication Optimization of Modern NAND Flash Memory
LEAP: Learning guided Quality Cut selection for faster Technology Mapping
Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental Uncertainties
Design and optimization of a digital microfluidic biochip for protein crystallization
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
SDC-based modulo scheduling for pipeline synthesis
Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization
Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing
Synthesis of Standard Cells of Minimum Delay
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors
The overview of 2014 CAD contest at ICCAD
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information
Evaluation and improvement of Boolean comparison method based on binary decision diagrams
Timing optimization by restructuring long combinatorial paths
Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring
Fast Test Application Technique Without Fast Scan Clocks
Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization
Weibull Based Analytical Waveform Model
ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation
Searching toward pareto-optimal device-aware neural architectures
A fast and memory-efficient diagnostic fault simulation for sequential circuits
MOLES: Malicious off-chip leakage enabled by side-channels
FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects
Adaptable and Divergent Synthetic Benchmark Generation for Hardware Security
An improved objective function for mincut circuit partitioning
Benchmarking of mask fracturing heuristics
Hardware obfuscation using PUF-based logic
Double patterning technology friendly detailed routing
Optimizing Memory Latency and Bandwidth of Spiking Neural Network Accelerators on FPGA via Sparse Hashing
Automated Synthesis for In-Memory Computing
A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
Mixed-precision Neural Networks on RISC-V Cores: ISA extensions for Multi-Pumped Soft SIMD Operations