yusuke1997/dblp-id-title huggingface dataset:
An adaptive scheme for estimating and correcting RF amplifiers' non-linearities
A 197 dBc/Hz FoMT 24.8-28.97 GHz Class-F VCO Using Single-Turn Multi-Tap Inductor
A spiking neural network chip for odor data classification
Closed-form design of fixed fractional hubert transformer using discrete sine transform
Live Demonstration: A Study on Monitoring Canine Emotional Changes through Heart Rate Variability
Architecture of WLAN channel estimators
A high efficiency boost white LED driver with an integrated Schottky diode
Recurrent type ANFIS using local search technique for time series prediction
Detailed Behavioral Modeling of Bang-Bang Phase Detectors
Variable step-size speech blind separation employing Laplacian normal mixture distribution model
Environmental taxonomy of power scavenging techniques for autonomous self powered wireless sensors
Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement
Tracking radar digital matched-filter ASIC design and its error analysis
Subpixel Interpolation Disparity Refinement for Semi-Global Matching
A High-speed Event-based Object Tracking with Heterogeneous Computing Hardware
Optimized three scores combination for image quality assessment
A Broadband Tri-Coil Based Transformer Design for mm-wave Cascode Amplifiers
Experimental investigation of the operation characteristics of 3-phase 3-wire active power filter
Adaptive rate control for real-time video streaming over the mobile WiMAX
A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse
Post-Filtering Techniques For Directive Non-Stationary Source Combined With Stationary Noise Utilizing Spatial Spectral Processing
Research on harmonic penetration between different voltage levels
A 40.6 ppm/°C 368 nW 10 kHz Relaxation Oscillator with Temperature-Sensor-based Piece-Wise Compensation Technique
A 65-nm Clock-Domain-Crossing Controller for Digital LDO Regulator with 1.7-ns Response Time
A real-time architecture of multiple features extraction for vehicle verification
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting
Novel realization of voltage transfer function with fractional characteristics using CFAs
Implementation of lane detection system using optimized hough transform circuit
A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers
High throughput 32-bit AES implementation in FPGA
Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator
An Eigen-decomposition Free Method for Computing Graph Fourier Transform Centrality
ECG Artifacts Suppression Using the NLSRA-Based Cascaded Fixed Point Interference Canceller
Architecture for Heart Rate measurement
Incremental delta-sigma A/D converter for ion-sensitive system application
A Li-ion battery charging design for biomedical implants
An analysis of output ripples for PMOS charge pumps and design methodology
Accelerator Design for Convolutional Neural Network with Vertical Data Streaming
Social Distancing Surveillance System via Inverse Perspective Mapping and Fixed-point Quantization
Throughput analysise of cooperative multiple packet reception based on NDMA
A single on/off reference tracking buck converter using turning point prediction for DVFS application
Live Demonstration: Portable Stimulation System for Transcutaneous Auricular Vagus Nerve Stimulation
Using Neuroevolved Binary Neural Networks to solve reinforcement learning environments
Fast Conversion for Large Canonical OR-Coincidence Functions
An FPGA-based quality filter for de novo sequence assembly pipeline
Optimal design method for chip-area-efficient CMOS low-dropout regulator
Joint channel estimation and interference cancellation for multipath long-code DS-CDMA
A low power 12-bit 40MS/s pipelined ADC with digital calibration
Comparative Analysis of SPAD Models for Low-Light Imaging
Low Power Bootstrapped CMOS Differential Cross Coupled Driver
Design of a Long-Range Wireless Sensor Node
Design of a Wideband 8-20 GHz Receiver Front-End with Reduced Local Oscillator Phase-Error in 4-Path Mixer
Determination of wide-area PSS locations and feedback signals using improved residue matrices
A Multi-Channel Decoupling Method for Feedforward Active Noise Control Using Neural Networks
A novel optical mesh network-on-chip for gigascale systems-on-chip
An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopy
An Efficient Self-Transposing Memory Structure for 32-bit Video Processors
A technique of automatic monitor generation based on FSM
An Area Efficient True Random Number Generator Based on Modified Ring Oscillators
A 4.8-Gb/s mixed-mode CMOS QPSK demodulator for 60-GHz wireless personal area networks
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches *
Cycle-time-aware sequential way-access set-associative cache for low energy consumption
ASIC design of a low-complexity K-best Viterbi decoder for IoT applications
Synthesis of a Complex Filter Excluding Inductors with Transmission Zeros at an Arbitrary Frequency
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications
Embedded compiler optimization for communication applications
A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS
Multiple Description Image Coding With Hybrid Redundancy
A simplified approach for baseband recovery in SDR architectures
Study on the performance of Bluetooth™ transmissions in electromagnetic interference environment from the 800 MHz mobile phone
A signal permutation method for cyclic-prefix-free OFDM channel estimation
Gesture recognition based on 3D accelerometer for cell phones interaction
Design of a novel 3.3 V CMOS logarithmic amplifier with a two step linear limiting architecture
Broadband Beamforming of Bandpass Plane Waves using 2D FIR Trapezoidal Filters at Baseband
Review and Comparison of Integrated Inductive-Based Hybrid Step-Down DC-DC Converter Under CCM Operation
Accurate Geometric Programming-Compatible Slew Rate Modeling for Two-Stage Operational Amplifier Design Optimization
GPU-based Ising Machine for Solving Combinatorial Optimization Problems with Enhanced Parallel Tempering Techniques
OL-SVR based soft-sensor for real-time estimation of solar irradiance
Design of ultra-low voltage and low-power CMOS current bleeding mixer
A 22nm CMOS 0.2V 13.3nW 16T SRAM Using Dynamic Leakage Suppression and Half-Selected Free Technique
A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC
A high performance peak detector sample and hold circuit for detecting power supply noise
Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System
Stochastic verification of run-time performance adaptation with field delay testing
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs
Non-negative matrix factorization for images with Laplacian noise
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM
Evaluation of quasi-resonant dc-link technique on generalized three-level inverter
Improving the immunity to substrate noise using active noise cancellation circuit in mixed-signal integrated circuits
A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping
FACTS Devices Applications on Power System to Improve the Angle Stability
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit
An Iterative Super-Resolution Reconstruction of Image Sequences using Fast Affine Block-Based Registration with BTV Regularization
Edge preserving super-resolution with details based on similar texture synthesis
Matched Block Detection and Motion Vector Salvage Methods for Fast H.264/AVC Inter Mode Decision
Adaptive filter-based reconstruction engine design for compressive sensing
Cost effective hardware sharing architecture for fast 1-D 8×8 forward and inverse integer transforms of H.264/AVC high profile
0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit
Multi-direction search algorithm for block-based motion estimation
A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path Filters
Frequency-Tunable Quasi-Elliptic Filter Using Liquid Metal
A Radiation-Hardened Trench Power MOSFET for Aerospace Applications
Capacity Estimation of Li-ion battery using Constant Current Charging Voltage
An advanced 3D format generation architecture for video and depth
Real time accelerometer-based gait recognition using adaptive windowed wavelet transforms
A new algorithm for updating adaptive system
An Implementation of H.264 Intra Predictor Based on Sub-sampling
Design of a High Voltage Level Shift with High dV/dt Immunity and High Speed
A new decoder for binary quadratic residue code with irreducible generator polynomial
A self biased full range current sensor for buck regulator
A new BPSK demodulation circuit for command transmission in wireless implantable neural recording system
Motion Assisted Video-based Stereo Matching
Yield and power improvement method by post-silicon delay tuning and technology mapping
Design-Technology Co-optimization for Cryogenic Tensor Processing Unit
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique
A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends
VLSI Realization of Adaptive Equalizers of SIMO FIR Second Order Volterra Channels
Random clock against differential power analysis
Multi-view video prediction architecture using faster prediction order
Finding All Solutions of Piecewise-Linear Resistive Circuits Using Triangular LP Test
Digitally assisted low dropout regulator design for low duty cycle IoT applications
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits
Body channel communication for low energy BSN/BAN
Low cost hardware implementation for traffic sign detection system
A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application
Optimizing APT product in MBFA topologies
A 0.6-V 1.8-μW automatic gain control circuit for digital hearing aid
100-MHz CMOS direct digital synthesizer with 10-bit DAC
Chaos propagation in coupled chaotic circuits with multi-ring combination
A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC
Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions
A 1V low noise amplifier for WiMAX / UWB applications
Interface control based on power flow tracing and generator re-dispatching
A vision sensor with background subtraction processor using mixed analog-digital architecture
Printed circuit antenna for UWB systems
A study on using microcontroller to design active noise control systems
A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification
Outage probability, throughput and delay analysis of cellular DS-CDMA system in the presence of correlated signal and interference
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA
Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch
MAMI: Majority and Multi-Input Logic on Memristive Crossbar Array
MPOE Based Prefiltering and MRT Beamforming for DS-CDMA Systems
Efficient architecture for the Tate pairing in characteristic three
Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions
A simplified PV model for low power MPPT controller design
A novel dynamic reconfigurable VLSI architecture for H.264 transforms
Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders
Characterization of nonlinear behavior of GaAs HFET power amplifier IC based on multitone measurement and simulation
Improving Source-Follower Buffer for High-Speed ADC Testing
Current-mode Active-only Universal Filter
A Readily Driven Zoom ADC with Least-Significant Bit First Quantization for Brain-Computer Interface
A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications
Monolithic Implementation of Chaos Modulated VCO-based Random Number Generator
Low-Complexity Dynamic Single-Minimum Min-Sum Algorithm and Hardware Implementation for LDPC Codes
Endothelial Cell Image Enhancement using Decimation-Free Directional Filter Banks
An overview of vertical handoff decision policies for next generation wireless networks
Ambiguity function of non-stationary signals using wavelet transform
Steady-State Performance Analysis of Cascade Boost Converters
A distributed framework to improve high-performance IP
An output-capacitor-free cascode low-dropout regulator with low quiescent current and high power supply rejection
A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation
Interference Suppression in DS-SS Systems with Modified Discrete Fourier Transform
An approach for generating n×m-scroll attractors in hyperchaotic coupled Chua circuits
A 8-resistor SU-8 accelerometer with reduced cross axis sensitivity
Synthetic circuit elements of higher order with current conveyors
Monolithic quasi-sliding-mode controller for SIDO buck converter in PCCM
A high speed and low power 4∶1 multiplexer with cascoded clock control
Enhanced Degree Computationless Modified Euclid's Algorithm
Normal-form state-space realization of single frequency IIR notch filters and its application to adaptive notch filters
Digital Filter Design: Global Solutions via Polynomial Optimization
Design and implementation of digital image processing techniques in pulse-domain
A CMOS sinusoidal signal generator based on mixed-time processing for electrical bioimpedance spectroscopy supporting beta dispersion range
A Novel Digitally-Controlled DC Offset Calibration Circuit for the Chopper Instrumentation Amplifier
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers
Model-Order Reduction Algorithm with Structure Preserving Techniques
An Optimisation Approach to Robust Estimation of Multicomponent Polynomial Phase Signals in Non-Gaussian Noise
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification
Adaptive intra mode bit skip in intra coding
Vehicle tracking in multi- sensor networks by fusing data in particle filter framework
Detecting clones in wireless sensor networks using Single Stage Memory Random Walk with Network Division
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers
Hardware-Aware Quantization for Multiplierless Neural Network Controllers
A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS
Sufficient conditions and error analysis on radial equivalent circuit of multi-winding isolating transformers used in power electronic devices
Integration of active noise control and other acoustic signal processing techniques
Power Baseline Modeling for Split-Type Air Conditioner in Building Energy Management Systems Using Deep Learning
Design and simulation of a wideband channelized transceiver for DRFM applications
Low Power Current-Mode Algorithmic ADC in Half Flash (BCD)
Thermal Driven Module Placement Using Sequence-pair
Firefly algorithm existing leader fireflies
Design of variable fractional-delay 2-D FIR digital filters by weighted least-squares approach
Design of CNN cell with low-power variable-gm OTA and its application
An On-chip High-resolution Delay Measurement Scheme for TSVs in 3DIC
Embedded DC-DC Voltage Down Converter for Low-Power VLSI Chip
Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory
Using asynchronous circuits for communications in wireless endoscopic capsule
System-level failure simulation and memory allocation scheme in 3D memory
A low power and low noise CMOS chopper amplifier for use in capacitive type accelerometer
Datapath oriented codesign method of application specific DSPs using retargetable compiler
A Level Shifter for CMRR-Enhanced Biopotential Acquisition Systems with Human-Body-Coupled Floating Supply Domain
A novel two-channel time-interleaved forth-order sigma-delta modulator topology
A generalized Volterra series method for reconstructing deterministic dynamics from noisy chaotic time series
A method for measuring switching frequency using complex asynchronous logic circuits
A digital low-dropout-regulator with steady-state load current (SLC) estimator and dynamic gain scaling (DGS) control
Influence of buffers on RISC core performance [HDTV source decoder system]
A 0.6V 10-bit 20kHz Capacitor Splitting Bypass Window SAR ADC for Biomedical Applications
Modelling the Effect of Output-Dependent Integrator Gain on the Unadjusted Error of Inverter Based 1 st Order $\Sigma\Delta$ ADC
Cumulative electrostatic discharge induced degradation of power-rail ESD clamp device in high-voltage CMOS/DMOS technologies
Low-quiescent-current fast-response current-feedback shunt regulator
Energy Harvester Powered Fully Digital ECG Front End Acquisition with Integrated TDC
Field experiments of wide area damping controllers for multiple HVDC links
Design of IIR fractional differentiator With Peano kernel
A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique
Affective pattern analysis of image in frequency domain using the Hilbert-Huang Transform
Applications of the Superposition Theorem to Nonlinear Resistive Circuits
Analysis of shape from shading algorithms for fast and realistic 3D face reconstruction APCCAS2002
ΔΣAD modulator for low power application
A memory-efficient architecture for intra predictor and de-blocking filter in video coding system
A Generic Architecture for Intelligent System Hardware
Fault-tolerance design of memory systems based on DBL structures
A Bandwidth-Tracking Self-Biased 5-to-2800 MHz Low-Jitter Clock Generator in 55nm CMOS
Live Demonstration: Defect Detection in Material Extrusion with Multimodal Large Language Model
Cluster validation for subspace clustering on high dimensional data
Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning
Optimizing Interconnect for Performance in Standard Cell Library
Immerse™: An alternative approach to 3D graphics performance
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics
Random Clock Gating for Side-channel Protection
Linear Adaptive Blind Equalizers of Non Linear SIMO FIR Channels
A combined method to reduce motion artifact and power line interference for wearable healthcare systems
A ROM-less DDFS using a nonlinear DAC with an error compensation current array
Time Domain Analysis of WPT System with Parallel Resonant Secondary Stage Driving Rectifier Load
Level Selection Based 4-PAM Transmitter for Chip to Chip Communication
Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study
Mobility patterns of human population among university campuses
A fast and low-cost fractional motion estimation for H.264/AVC HD1080p coding
Low voltage regulated cascode current mirrors suitable for sub-1V operation
Array blind calibration criterions for low-angle tracking
3D map building based on projection of virtual height line
Finding all solutions of piecewise-linear resistive circuits using excel
Subband adaptive filtering using approximately alias-free cosine modulated filterbanks
Analytical design procedure for resonant inductively coupled wireless power transfer system with class-DE inverter and class-E rectifier
An edge-preserving blind image restoration using hierarchical Bayesian model
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction
An illumination aware single solar-cell VCO CCO based charge-pump energy harvesting system for SoC integration
First-Order Recursive CIC Filters in Time-Interleaved VCO-Based ADCs for Direct-RF Sampling Receivers
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
A low-power 6-bit successive approximation register ADC using a new split capacitor array method
A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link
On the algorithm for adaptive noise canceller with parallel block structure
A low-power MICS fractional-N frequency synthesizer for implantable biomedical systems
Development of low power DAC with pseudo Fibonacci sequence
Methods for measuring loop-gain function of high-frequency DC-DC converters
Novel hybrid approach combining ANN and MRA for PET volume segmentation
Synthesis of Finite State Machines for Low Power and Testability
An I/Q channel 12 bit 120MS/s CMOS DAC with three stage thermometer decoders for WLAN
A Highly Linear Amp-Less Interface Circuit for Capacitive Sensors with ΔΣ C-DAC
Incremental statistical static timing analysis with gate timing yield emphasis
Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM
COLEA: A Low-light Enhancement Accelerator with Memory-usage Reducing Strategy
A reconfigurable arbiter for SOC applications
Large DC gain nonisolated converter based on a new L-C-D step-up switching cell
Design and characterisation of 16×1 parallel outputs SPAD array in 0.18 um CMOS technology
Adiabatic Smart Card
A Subthreshold Folded-Cascode Lowpass Biquad for Biopotential Acquisition
Real-time correction of wide-angle lens distortion for images with GPU computing
Skew variation compensating technique for clock mesh networks
Dynamic Tail Biased Class-C Voltage-Controlled-Oscillator with Double-Balanced Mixer Design
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor
Effect of impedance variation around the fundamentals on PA distortions characteristics under wideband multi-tone stimulus
A Wideband three-stage rail-to-rail power amplifier driving large capacitive load
A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application
Live Demonstration: Low Cost AES-256 Circuit Design and Application
Exploiting Concurrency in System-on-Chip Verification
A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms
Intelligent human-machine cooperative robot for orthopaedic surgery
A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS
Analog integrated audio frequency synthesizer
A low voltage current mirror based on quasi-floating gate MOSFETs
High speed JPEG2000 encoder by configurable processor
Real-time implementation of Wave Field Synthesis for sound reproduction systems
A new ZCT precoding based SLM technique for PAPR reduction in OFDM systems
CoLPUF : A Novel Configurable LFSR-based PUF
Input characteristic impedance technique of power converters circuits applied to the maximum power point tracker of photovoltaic panels
A Novel Low Power NOR gate in SOI CMOS Technology
Privacy preserving face recognition in encrypted domain
Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping
A Precision-Scalable Energy-Efficient DNN Accelerator for Robotic Grasping
An insertion loss control method for supplementing cancellation effect deteriorated by echo path change in hands free telecommunication system
New class-E rectifier with low voltage stress
DC-20 GHz differential transmit/receieve DP4T switching matrix for radar-based target detection
A 77 nW bioamplifier with a tunable bandwidth for neural recording systems
SimSoC: A SystemC TLM integrated ISS for full system simulation
Sharpening the response of the (9, 7) filter pair by multiple use of half-band subfilter
A non-expansive one-dimensional DWT with perfect reconstruction via simultaneous multi-octave analysis