yusuke1997/dblp-id-title huggingface dataset:
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Safe Automotive Software Development
Leveraging Processor Modeling and Verification for General Hardware Modules
Paired Training Framework for Time-Constrained Learning
Task concurrency management methodology summary
Solver technology for system-level to RTL equivalence checking
A novel way to efficiently simulate complex full systems incorporating hardware accelerators
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
A MILP-based approach to path sensitization of embedded software
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model
Exploiting process variation for retention induced refresh minimization on flash memory
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis
Towards a better understanding of failure modes and test requirements of ADCs
Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPs
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor
A dynamic computation method for fast and accurate performance evaluation of multi-core architectures
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems
A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing
A Hierarchical Test Scheme for System-On-Chip Designs
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR
Challenges in verifying an integrated 3D design
Driving Autonomy with Event-Based Cameras: Algorithm and Hardware Perspectives
A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation
SPARROW: A Low-Cost Hardware/Software Co-designed SIMD Microarchitecture for AI Operations in Space Processors
Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step
Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip
Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits
A UML 2-based hardware-software co-design framework for body sensor network applications
Instruction Set Extensions for secure applications
SRing: A Sub-Ring Construction Method for Application-Specific Wavelength-Routed Optical NoCs
Securing Programmable Analog ICs Against Piracy
Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage
Exploiting temporal independence in distributed preemptive circuit simulation
High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
An MDE methodology for the development of high-integrity real-time systems
Highly-Bespoke Robust Printed Neuromorphic Circuits
Characterizing and Optimizing EDA Flows for the Cloud
Exploring Micro-architectural Side-Channel Leakages through Statistical Testing
VHDL-AMS Library Development for Pacemaker Applications
Full-credit Flow Control: A Novel Technique to Implement Deadlock-free Adaptive Routing
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits
MEMHD: Memory-Efficient Multi-Centroid Hyperdimensional Computing for Fully-Utilized In-Memory Computing Architectures
Low-cost fault detection method for ECC using Montgomery powering ladder
Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation
A network-flow based algorithm for power density mitigation at post-placement stage
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder
Chip-to-Cloud: an Autonomous and Energy Efficient Platform for Smart Vision Applications
An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition
Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective
Mapping multi-dimensional signals into hierarchical memory organizations
Clock Distribution Scheme using Coplanar Transmission Lines
A low-cost concurrent error detection technique for processor control logic
Semi-symbolic analysis of mixed-signal systems including discontinuities
Finite precision processing in wireless applications
ASIP architecture for multi-standard wireless terminals
Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques
LC Oscillator Driver for Safety Critical Applications
A Scalable Algorithmic Framework for Row-Based Power-Gating
A Gauss-elimination based PRPG for combinational circuits
C3CIM: Constant Column Current Memristor-Based Computation-in-Memory Micro-Architecture
A System to Validate and Certify Soft and Hard IP
Cell delay analysis based on rate-of-current change
On-Chip Stochastic Communication
Fluid Dynamic DNNs for Reliable and Adaptive Distributed Inference on Edge Devices
(Self-)reconfigurable Finite State Machines: Theory and Implementation
Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC's
Aging-aware standard cell library design
HELCFL: High-Efficiency and Low-Cost Federated Learning in Heterogeneous Mobile-Edge Computing
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Refinement Maps for Efficient Verification of Processor Models
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking
Functional constraints vs. test compression in scan-based delay testing
Memory Trojan Attack on Neural Network Accelerators
Formal Verification of Word-Level Specifications
Panel session - ESL methodology for SoC
Scalable Logic Rewriting Using Don't Cares
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA
Automated debugging of SystemVerilog assertions
Automatic Behavioural Model Calibration for Efficient PLL System Verification
Design reuse through high-level library mapping
Constraint-Aware Resource Management for Cyber-Physical Systems
OTA Amplifiers Design on Digital Sea-of-Transistors Array
Enabling dynamic assertion-based verification of embedded software through model-driven design
Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms
Optimization of standard cell based detailed placement for 16 nm FinFET process
M2M-Routing: Environmental Adaptive Multi-agent Reinforcement Learning based Multi-hop Routing Policy for Self-Powered IoT Systems
VaMV: Variability-aware Memory Virtualization
Optimization of secure embedded systems with dynamic task sets
Perspectives on Emerging Computation-in-Memory Paradigms
Design of low-power high-speed maximum a priori decoder architectures
HotR: Alleviating Read/Write Interference with Hot Read Data Replication for Flash Storage
On the numerical verification of probabilistic rewriting systems
Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification
Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits
Circuit partitioning for efficient logic BIST synthesis
A formal approach for specification-driven AMS behavioral model generation
Scalable Boolean Methods in a Modern Synthesis Flow
Taming Data Caches for Predictable Execution on GPU-based SoCs
Robust 6T Si tunneling transistor SRAM design
MultimodalHD: Federated Learning Over Heterogeneous Sensor Modalities using Hyperdimensional Computing
An EDA-friendly protection scheme against side-channel attacks
Application of Mission Profiles to enable cross-domain constraint-driven design
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Rapid Gate Matching with Don't Cares
Wire Placement for Crosstalk Energy Minimization in Address Buses
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools
ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning
Mapping of local and global synapses on spiking neuromorphic hardware
An application-based EDF scheduler for OSEK/VDX
RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery
Accurate CEGAR-based ATPG in presence of unknown values for large industrial designs
A DAG-Based Design Approach for Reconfigurable VLIW Processors
Combining PDR and reverse PDR for hardware model checking
TLM+ modeling of embedded HW/SW systems
2nd International Workshop on Autonomous Systems Design, ASD 2020, Grenoble, France (Virtual Conference), March 13, 2020
Verifying the Conformance of a Driver Implementation to the VirtIO Specification
SPDF: A schedulable parametric data-flow MoC
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
Reuse-aware modulo scheduling for stream processors
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits
Brisk and limited-impact NoC routing reconfiguration
Integrated circuits processing chemical information: Prospects and challenges
An Accurate SER Estimation Method Based on Propagation Probability
Working with process variation aware caches
SystemC Analysis of a New Dynamic Power Management Architectur
Real-time system-level implementation of a telepresence robot using an embedded GPU platform
Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core
Minimum current consumption transition time optimization methodology for low power CTS
Visual quality analysis for dynamic backlight scaling in LCD systems
CrossOver: Clock domain crossing under virtual-channel flow control
TinyTimber, Reactive Objects in C for Real-Time Embedded Systems
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units
Generating production quality software development tools using a machine description language
DRAM selection and configuration for real-time mobile systems
Improving SRAM test quality by leveraging self-timed circuits
From Transistor to PLL - Analogue Design and EDA Methods
Device-Aware Test for Back-Hopping Defects in STT-MRAMs
Variability-aware duty cycle scheduling in long running embedded sensing systems
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs
OpenJ: An Extensible System Level Design Language
Design-Reliability Flow and Advanced Models Address IC-Reliability Issues
Power management of multi-core chips: Challenges and pitfalls
VLSI legalization with minimum perturbation by iterative augmentation
MicroFaaS: Energy-efficient Serverless on Bare-metal Single-board Computers
Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method
An embedded platform for privacy-friendly road charging applications
Buffer Insertion Considering Process Variation
Formal analysis of steady state errors in feedback control systems using HOL-light
A cyber-physical systems approach to personalized medicine: challenges and opportunities for noc-based multicore platforms
Integration of an advanced emergency call subsystem into a car-gateway platform
PT-AMC: integrating preemption thresholds into mixed-criticality scheduling
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers
Exploring Deep Learning for In-Field Fault Detection in Microprocessors
Schedulability bound for integrated modular avionics partitions
Optimizing instruction-set extensible processors under data bandwidth constraints
Efficient and scalable compiler-directed energy optimization for realtime applications
BandiTS: Dynamic timing speculation using multi-armed bandit based optimization
System-level modeling of a mixed-signal System on Chip for Wireless Sensor Networks
Architectural exploration of 3D FPGAs towards a better balance between area and delay
RATAN: A tool for rate analysis and rate constraint debugging for embedded systems
A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores
Static Analysis Tools for Soft-Core Reviews and Audits
Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays
Realizing Reproducible and Reusable Parallel Floating Random Walk Solvers for Practical Usage
Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTL
Software-based Pauli tracking in fault-tolerant quantum circuits
Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM
Para-ZNS: Improving Small-Zone ZNS SSDs Parallelism Through Dynamic Zone Mapping
Early Functional Safety and PPA Evaluation of Digital Designs
Repeater block planning under simultaneous delay and transition time constraints
Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate Estimation
p-OFTL: An object-based semantic-aware parallel flash translation layer
Automatic success tree-based reliability analysis for the consideration of transient and permanent faults
Global fan speed control considering non-ideal temperature measurements in enterprise servers
Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude
DropHD: Technology/Algorithm Co-Design for Reliable Energy-Efficient NVM-Based Hyper-Dimensional Computing Under Voltage Scaling
Busy man's synthesis: Combinational delay optimization with SAT
Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver
Verification-guided soft error resilience
Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
Multiple-Precision Circuits Allocation Independent of Data-Objects Length
Middleware services for network interoperability in smart energy efficient buildings
Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators
Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown
Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS
CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs
Design of high-resolution MOSFET-only pipelined ADCs with digital calibration
Automatic transition between structural system views in a safety relevant embedded systems development process
HDCluster: An Accurate Clustering Using Brain-Inspired High-Dimensional Computing
SC4MEC: Automated Implementation of A Secure Hierarchical Calculus for Mobile Edge Computing
Improved Constraints for Multiprocessor System Scheduling
Value Similarity Extensions for Approximate Computing in General-Purpose Processors
Automatic generation of functional models for embedded processor extensions
ONE-SA: Enabling Nonlinear Operations in Systolic Arrays For Efficient and Flexible Neural Network Inference
SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects
Symbolic assertion mining for security validation
A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN
Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units
A DTCO Framework for 3D NAND Flash Readout
Security Assertions for Trusted Execution Environments
Intent-leveraged optimization of analog circuits via homotopy
Construction of dual mode components for reconfiguration aware high-level synthesis
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors
R-LDPC: Refining Behavior Descriptions in HLS to Implement High-throughput LDPC Decoder
Reversible logic synthesis through ant colony optimization
Simultaneously improving code size, performance, and energy in embedded processors
Modeling and testing of interference faults in the nano NAND Flash memory
Analyzing the impact of injected sensor data on an Advanced Driver Assistance System using the OP2TIMUS prototyping platform
System-level modeling of energy in TLM for early validation of power and thermal management
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation
Stochastic modeling and optimization for robust power management in a partially observable system
Layout-aware optimization of stt mrams
Current source based standard cell model for accurate signal integrity and timing analysis
Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis
EM SCA & FI Self-Awareness and Resilience with Single On-chip Loop & ML Classifiers
Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-Preserving Federated Learning Aggregation
Software Structure and WCET Predictability
Exploiting Architecture Advances for Sparse Solvers in Circuit Simulation
A Knowledge-based System for Hardware-Software Partitioning
Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage)
Design of an ultra-low power device for aircraft structural health monitoring
Automatic generation and targeting of application specific operating systems and embedded systems software
picoArray Technology: The Tool's Story
Software-based self-test of processors under power constraints
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales
Improve CAM power efficiency using decoupled match line scheme
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric
VEDLIoT: Very Efficient Deep Learning in IoT
Islands of Synchronicity, a Design Methodology for SoC Design
Sub-clock power-gating technique for minimising leakage power during active mode
FPGA Architecture for Multi-Style Asynchronous Logic
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores
Irradiance-Driven Partial Reconfiguration of PV Panels
Approximate computing for biometrie security systems: A case study on iris scanning
Dynamic Power Management Using Data Buffers
Compositional design of isochronous systems
BISD: Scan-based Built-In self-diagnosis
PFASware: Quantifying the Environmental Impact of Per- and Polyfluoroalkyl Substances (PFAS) in Computing Systems
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications
Resource Manager for Scalable Performance in ROS Distributed Environments
Automated feature localization for dynamically generated SystemC designs
A Unified Vector Processing Unit for Fully Homomorphic Encryption
Bitstream Modification Attack on SNOW 3G
FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation
Efficient on-line testing method for a floating-point adder
Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations
An event-guided approach to reducing voltage noise in processors
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement
SAHARA: a security-aware hazard and risk analysis method
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems
Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF)
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
Maximizing common idle time on multi-core processors with shared memory
Adaptive test optimization through real time learning of test effectiveness
In-Memory Computing based Accelerator for Transformer Networks for Long Sequences
Test solution for data retention faults in low-power SRAMs
Operation Serializability for Embedded Systems
ZeroPowerTouch: Zero-Power Smart Receiver for Touch Communication and Sensing in Wearable Applications
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
PaLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
A divide and conquer based distributed run-time mapping methodology for many-core platforms
Advanced receiver algorithms for MIMO wireless communications
Built-in self-test methodology for A/D converters
Simulations on Consumer Tests: A Perspective for Driver Assistance Systems
Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor
Optimizing equivalence checking for behavioral synthesis
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints
An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes
INSPEX: Design and integration of a portable/wearable smart spatial exploration system
Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT
Nano-electronics challenge chip designers meet real nano-electronics in 2010s?
Reliable mode changes in real-time systems with fixed priority or EDF scheduling
Vehicle electric/electronic architecture - one of the most important challenges for OEM's
OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems
Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing
Variation-aware near threshold circuit synthesis
Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory
Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model
Blind identification of power sources in processors
Near-optimal metastability-containing sorting networks
The effect of pin constraints on layout area
Coordinated resource optimization in behavioral synthesis
Dynamic Stochastic Computing for Digital Signal Processing Applications
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020
Analyzing and eliminating the causes of fault sensitivity analysis
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Fast and accurate computation using stochastic circuits
MatEx: efficient transient and peak temperature computation for compact thermal models
Experiences during the Experimental Validation of the Time-Triggered Architecture
Systems Engineering Roadmap for Dependable Autonomous Cyber-Physical Systems
Projective Convolution: RLC Model-Order Reduction Using the Impulse Response
Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches
Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables