yusuke1997/dblp-id-title huggingface dataset:
ARM HPC Ecosystem and the Reemergence of Vectors: Invited Paper
Hardware Security: state of the art: Keynote
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005
A portable parallel finite element simulation system
Compile-Time Optimization of the Energy Consumption of Numerical Computations
Toward a quantum process algebra
Optimizing general purpose compiler optimization
Using Tweaks To Design Fault Resistant Ciphers (Full Version)
Cyber-physical firewall: monitoring and controlling the threats caused by malicious analog signals
Processing units in the age of AI
Virtual base station pool: towards a wireless network cloud for radio access networks
Run-time performance monitoring of hardware accelerators: POSTER
Application-specific network-on-chip design space exploration framework for neuromorphic processor
Holistic RISC-V Virtualization: CVA6-based SoC
Application Level Architecture Design
Toward a graph-based dependence analysis framework for high level design verification
A DNN-based Background Segmentation Accelerator for FPGA-equipped satellites
Low-latency implementation of the GIFT cipher on RISC-V architectures
On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits
Quantum Circuit Design for Finding k-Cliques via Quantum Amplitude Amplification Strategies
Dynamic run-time architecture techniques for enabling continuous optimization
A Large-Scale Malleable Tsunami Simulation Realized on an Elastic MPI Infrastructure
DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators
Towards truly integrated photonic and electronic computing
SPANIDS: a scalable network intrusion detection loadbalancer
Benchmarking and feasibility aspects of machine learning in space systems
An opportunistic reconfiguration strategy for environmentally powered devices
Towards realistic battery-DoS protection of implantable medical devices
SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference
DFShards: effective construction of MRCs online for non-stack algorithms
Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures
Enhancing an x86_64 multi-core architecture with data-flow execution support
Stitching FPGA Fabrics with FABulous and OpenLane 2
A new memory reliability technique for multiple bit upsets mitigation
Building a portable deeply-nested implicit information flow tracking
Meet Monte Cimone: exploring RISC-V high performance compute clusters
Dysource: a high performance and scalable NAND flash controller architecture based on source synchronous interface
Introduction to reversible computing: motivation, progress, and challenges
Simulation with skeletons of applications using dimemas
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
Modeling SSD RAID reliability under general settings
Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection
Exploiting the GPU to accelerate DSS query execution
Kinship: efficient resource management for performance and functionally asymmetric platforms
NTTGen: a framework for generating low latency NTT implementations on FPGA
Sparse matrix storage revisited
Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing
Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system
Multi-Task Collaborative Learning for Robust Diabetic Retinopathy Grading on Low-Quality Fundus Images
SPADA: a statistical program attack detection analysis
Computing Frontiers Conference, CF'14, Cagliari, Italy - May 20 - 22, 2014
Transition aware scheduling: increasing continuous idle-periods in resource units
Dynamic percolation: a case of study on the shortcomings of traditional optimization in many-core architectures
DEEP: an exascale prototype architecture based on a flexible configuration
Assessment of RISC-V Processor Suitability for Satellite Applications
Enabling a highly-scalable global address space model for petascale computing
PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core
Improving energy efficiency for mobile platforms by exploiting low-power sleep states
Reconstructing Cut Quantum Circuits Maximising Fidelity between Quantum States
Selective search of inlining vectors for program optimization
Supporting lock-free composition of concurrent data objects
Physical design methodologies for performance predictability and manufacturability
An efficient wakeup design for energy reduction in high-performance superscalar processors
A file system bypassing volatile main memory: towards a single-level persistent store
Realizing parallelism in quantum MISD architecture
Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications
GA-GPU: extending a library-based global address spaceprogramming model for scalable heterogeneouscomputing systems
Hardware-Software Co-Design for Supporting Shared Distributed Virtual Memory
SARP: producing approximate results with small correctness losses for cloud interactive services
Efficient fault tolerance in multi-media applications through selective instruction replication
Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007
Approximating trigonometric functions for posits using the CORDIC method
Classification of S-Boxes According to Hardware Implementation Cost
Larrabee: a many-core Intel architecture for visual computing
An IT-infrastructure capability model
Studying the impact of application-level optimizations on the power consumption of multi-core architectures
Parametrizing multicore architectures for multiple sequence alignment
Compiler analysis for OpenMP tasks correctness
AXIOM project: from applied research towards embedded systems
Accelerated high-performance computing through efficient multi-process GPU resource sharing
Where replacement algorithms fail: a thorough analysis
High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators
Dependability in an evolving world
Just-in-time component-wise power and thermal modeling
Stop Wasting your Cache! Bringing Machine Learning into Cache Computing
An Enhanced Image Reconstruction Tool for Computed Tomography on CPUs
D 3 NoC: a dynamic data-driven hybrid photonic plasmonic NoC
Reversible logic for supercomputing
Reconfigurable universal SAD-multiplier array
REC: REtime convolutional layers in energy harvesting ReRAM-based CNN accelerators
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units
A multithread AES accelerator for Cyber-Physical Systems
PowerSecBench: reveal microarchitectural power leakages using generic RISC-V microbenchmarks
A multi-streaming SIMD architecture for multimedia applications
Optimizing sparse matrix-vector multiplication using index and value compression
APPàre: smart and secure livestock farm APPlications to boost data-driven innovation along the food chain: Invited Paper
Scalability of continuation-based fine-grained multithreading in handling multiple I/O requests on FUCE
Analytical Performance Modeling and Validation of Intel's Xeon Phi Architecture
A modular 3d processor for flexible product design and technology migration
An FPGA framework for edge-centric graph processing
Fault Awareness in the MPI 4.0 Session Model
Universal optical multi-drop bus for heterogeneous memory architecture
Performance prediction for convolutional neural networks on edge GPUs
Controlling leakage power with the replacement policy in slumberous caches
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies
Similarity-aware popularity-based caching in wireless edge computing
Removing duplicated writes at DB checkpointing with file system-level block remapping
Cache-conscious graph collaborative filtering on multi-socket multicore systems
Principles of a reversible programming language
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
To cache or not to cache: a trade-off analysis for locally cached database systems
Big Data Analytics on Large-Scale Scientific Datasets in the INDIGO-DataCloud Project
APAT: an access pattern analysis tool for distributed arrays
A light-weight fairness mechanism for chip multiprocessor memory systems
ETD-Cache: an expiration-time driven cache scheme to make SSD-based read cache endurable and cost-efficient
POSTER: Performance Comparison of GPU Programming Models Using HeCBench Benchmarks
Just TestIt! An SBST Approach To Automate System-Integration Testing
Evaluating fork after withholding (FAW) attack in Bitcoin
Evaluation of dynamic voltage and frequency scaling for stream programs
NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology
Streaming graph analysis: new models, new architectures
A framework for resource discovery in pervasive computing for mobile aware task execution
MemComputing: Fundamentals and Application
Lazy direct-to-cache transfer during receive operations in a message passing environment
Accelerating parallel graph computing with speculation
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
An architectural framework and a middleware for cooperating smart components
From volunteer to cloud computing: cloud@home
Bridging the programming gap between persistent and volatile memory using WrAP
Data buffering optimization methods toward a uniform programming interface for gpu-based applications
SoundFactory: a framework for generating datasets for deep learning SELD algorithms
Object-centric bank partition for reducing memory interference in CMP systems
IO-SEA: Storage I/O and Data Management for Exascale Architectures
StoneCutter: a very high level instruction set design language
Coordinating Instruments for Multi-Messenger Astrophysics: Invited Paper
Concurrent page migration for mobile systems with OS-managed hybrid memory
CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF
Analysis of control and sensing interfaces in a photonic integrated chip solution for quantum computing
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
A high performance reliable dataflow based processor for space applications
Automatic tuning of MPI runtime parameter settings by using machine learning
Achieving high throughput and low delay in mobile data networks by accurately predicting queue lengths
Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems
The quantum challenge to computer science
Design space exploration for PIM architectures in 3D-stacked memories
Partially ordered epochs for thread-level speculation
ProductiveC: enabling high productivity in C-family languages
A matrix multiplier case study for an evaluation of a configurable dataflow-machine
Pattern Matching, Transformation and Code Replacement on a Polyhedral Representation of Nested Loops
Towards Big Data Visualization for Monitoring and Diagnostics of High Volume Semiconductor Manufacturing
SoC design of Ogg Vorbis decoder using embedded processor
Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment
An empirical high level performance model for future many-cores
SparkBench: a comprehensive benchmarking suite for in memory data analytic platform Spark
Time, space, and energy in reversible computing
Methodological Challenges in Conducting a Screening Life Cycle Assessment of Dense Electronic Devices: The Case of Smartphones
A perspective on the future of massively parallel computing: fine-grain vs. coarse-grain parallel models comparison & contrast
Performance analysis and predictability of the software layer in dynamic binary translators/optimizers
Big data analytics for climate change and biodiversity in the EUBrazilCC federated cloud infrastructure
Direction-optimizing label propagation and its application to community detection
An efficient vectorization of linked-cell particle simulations
Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors
IMD security vs. energy: are we tilting at windmills?: POSTER
Towards superior software portability with SHAD and HPX C++ libraries
MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor
Compressed quadratization of higher order binary optimization problems
Parallel Incremental Clustering Algorithms for Massive Dynamic Graphs
Accelerating computing with the cell broadband engine processor
Sorting big data on heterogeneous near-data processing systems
Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009
Private inter-network routing for Wireless Sensor Networks and the Internet of Things
An architecture to support cooperating mobile embedded systems
Quick and Accurate Methodology of Simplified Life Cycle Assessment for Printed Circuit Boards Ecodesign
Performing bitwise logic operations in cache using spintronics-based magnetic tunnel junctions
Mini-batching with Fused Training and Testing for Data Streams Processing on the Edge
Quantum Computing Management of a Cloud/Edge Architecture
SuperCut: Communication-Aware Partitioning for Near-Memory Graph Processing
ShuffleFL: gradient-preserving federated learning using trusted execution environment
A New Approach to Selectively Control Flow Checking Methods Compliant with ISO 26262
CAROL-FI: an Efficient Fault-Injection Tool for Vulnerability Evaluation of Modern HPC Parallel Accelerators
Compilation on the GPU?: a feasibility study
Reversible online BIST using bidirectional BILBO
Exploiting locality to ameliorate packet queue contention and serialization
Active storage revisited: the case for power and performance benefits for unstructured data processing applications
High-performance SIMT code generation in an active visual effects library
Reflections on the memory wall
Addressing Hadoop's Small File Problem With an Appendable Archive File Format
Accordion: A malleable pipeline scheduling approach for adaptive SLO-aware inference serving
Let's Go: a Data-Driven Multi-Threading Support
RTS - an integrated analytic solution for managing regulation changes and their impact on business compliance
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation
Extending the comfort zone: DAVIDE
Data cube and cloud resources as platform for seamless geospatial computation
QuickTree: A Fast Hardware BVH Construction Engine
Computationally unifying urban masterplanning
HOSA: hybrid optical switch architecture for data center networks
Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture
HPC4AI: an AI-on-demand federated platform endeavour
A new technique to calculate dipolar energy and its implementation onto an application specific processor
Reversible computing: from mathematical group theory to electronical circuit experiment
The german informatics society's new ethical guidelines: POSTER
A methodology for efficient code optimizations and memory management
Fighting the memory wall with assisted execution
Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework
Recent technological trends and their impact on system design
Self-replication for reliability: bio-inspired hardware and the embryonics project
Designing Swarms of Cyber-Physical Systems: the H2020 CPSwarm Project: Invited Paper
FPGA acceleration of deep reinforcement learning using on-chip replay management
Approximating the optimal replacement algorithm
GPU-UniCache: Automatic Code Generation of Spatial Blocking for Stencils on CPUs
Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture
Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits
Accelerating the secure remote password protocol using reconfigurable hardware
Strategies for improving performance and energy efficiency on a many-core
Automaton-based methodology for implementing optimization constraints for quantum annealing
Evolving 5G: ANIARA, an edge-cloud perspective
Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006
Dynamic parallelization and mapping of binary executables on hierarchical platforms
Extending concurrency of transactional memory programs by using value prediction
Profile-driven compression scheme for embedded systems
RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects
The able amble: gait recognition using Gaussian mixture model for biometric applications
DECICE: Device-Edge-Cloud Intelligent Collaboration Framework
Higher order side-channel attack resilient S-boxes
DP-Discriminator: A Differential Privacy Evaluation Tool Based on GAN
SnCTM: reducing false transaction aborts by adaptively changing the source of conflict detection
A design methodology for fault-tolerant computing using astrocyte neural networks
An adaptive concurrent priority queue for NUMA architectures
Reducing misspeculation overhead for module-level speculative execution
GPU power prediction via ensemble machine learning for DVFS space exploration
EuroHPC SPACE CoE: Redesigning Scalable Parallel Astrophysical Codes for Exascale. Invited Paper
DCNSim: a unified and cross-layer computer architecture simulation framework for data center network research
Recommending Resources to Cloud Applications based on Custom Templates Composition
Compiler-Injected SIHFT for Embedded Operating Systems
Return-oriented programming protection in the IBM POWER10
Intelligent UAV-aided controller placement scheme for software-defined vehicular networks
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network
GPU acceleration of regular expression matching for large datasets: exploring the implementation space
Combining learning and optimization for transprecision computing
Kilo-instruction processors, runahead and prefetching
An argument for thread-level speculation and just-in-time compilation in the Google's V8 JavaScript engine
Model-based evaluation of a radio resource management system for wireless networks
Analysing the tor web with high performance graph algorithms
TEA-fed: time-efficient asynchronous federated learning for edge computing
Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008
Social Engineering 2.0: A Foundational Work: Invited Paper
Model theft attack against a tinyML application running on an Ultra-Low-Power Open-Source SoC
An algorithm for parallel calculation of trigonometric functions
Nail-it-down: nailing and fixing configuration faults in cloud environments
Parallel graph algorithms by blocks: from I/O to algorithms
Optimization of neural network through genetic algorithm searches for the prediction of international crude oil price based on energy products prices
Lazy repair with temporary redundancy(LRTR): reducing repair network traffic in erasure-coded storage
Composable local memory organisation for streaming applications on embedded MPSoCs
FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable Implementation
Using community detection for spatial networks: POSTER
SRBB-based Quantum State Preparation
A service-based approach for the execution of scientific workflows in grids
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
Efficient pattern matching on GPUs for intrusion detection systems
Scaling analytics applications with OpenCL for loosely coupled heterogeneous clusters
Cloud Workload Prediction by Means of Simulations
Biologically inspired rule-based multiset programming paradigm for soft-computing
Proceedings of the Computing Frontiers Conference, CF'17, Siena, Italy, May 15-17, 2017
Scheduling optimization in multicore multithreaded microprocessors through dynamic modeling
cREAtIve: reconfigurable embedded artificial intelligence
A two level market model for resource allocation optimization in computational grid
A dependability perspective on emerging technologies
Programmability versus performance tradeoff: overcoming the hardware challenges from a task-based approach
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors
Distributed learning-based state prediction for multi-agent systems with reduced communication effort
moTuner: a compiler-based auto-tuning approach for mixed-precision operators
Speculative early register release
Combination of Storage and Accumulation for Synchronous SpMV Acceleration on FPGAs with HBM
Evaluation of extended dictionary-based static code compression schemes
Accelerated Deep-Learning inference on FPGAs in the Space Domain
Understanding the limiting factors of page migration in hybrid main memory
High-level synthesis of throughput-optimized and energy-efficient approximate designs
Accelerating Type Confusion Detection by Identifying Harmless Type Castings
Instruction level energy model for the Adapteva Epiphany multi-core processor
On the decidability of phase ordering problem in optimizing compilation
Machine learning application for patients activity recognition with pressure sensing in bed
Multi- and many-core data mining with adaptive sparse grids
Effect of auto-tuning with user's knowledge for numerical software
FACT: a framework for adaptive contention-aware thread migrations
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
A collaborative divide-and-conquer K-means clustering algorithm for processing large data
A glimpse on the EdgeAI project: Technologies for Optimized Embedded Processing: Invited Paper
A secure authentication scheme based on differential public PUF
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration
A PaaS for composite analytics solutions
Parallel algorithms through approximation: graphs, data privacy and machine learning
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
Unified microprocessor core storage
Always-ON visual node with a hardware-software event-based binarized neural network inference engine
Performance statistics and learning based detection of exploitative speculative attacks
Evaluation of Quantum and Hybrid Solvers for Combinatorial Optimization
AGILE Workflows and Graphs
An analysis of the effects of miss clustering on the cost of a cache miss
Global management of cache hierarchies
Enhancing Bundle Delivery Efficiency in Mobile Ad-hoc Networks with a Multi-protocol Delay-Tolerant Network
Quantum Circuit Cutting Minimising Loss of Qubit Entanglement
HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne Instrument
Energy-efficient approximate least squares accelerator: a case study of radio astronomy calibration processing
Data and model convergence: a case for software defined architectures
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Berserkr: a virtual beowulf cluster for fast prototyping and teaching
Quantum designer and network simulator
Two-level logging with non-volatile byte-addressable memory in log-structured file systems
On the theory of speculative checkpointing: time and energy considerations
Intermediately executed code is the key to find refactorings that improve temporal data locality
Wave field synthesis for 3D audio: architectural prospectives
A Portable Tool to Compare Performance Profiles from GPU Offloading Programming Models
Clustering and Allocation of Spiking Neural Networks on Crossbar-Based Neuromorphic Architecture
An ANN-Guided Multi-Objective Framework for Power-Performance Balancing in HPC Systems