yusuke1997/dblp-id-title huggingface dataset:
An Investigation into the Security of Register Allocation with Spilling and Splitting
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 13-15 May 2009, Tampa, Florida, USA
Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors
Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration
TSV-aware Scan Chain Reordering for 3D IC
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
Accelerating Solar Spectra Analysis:A High-Performance FPGA Framework with Parameterized Filters
Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix Multiplication
AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture
Towards the Optimization of Hardware Efficiency through Machine Learning
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters
Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection
Arithmetic Data Path Optimization Using Borrow-Save Representation
Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits
Analysis of a Mask-Based Nanowire Decoder
A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture
SeReCon: A Secure Dynamic Partial Reconfiguration Controller
WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip
Glitch Resistant Private Circuits Design Using HORNS
Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning
Transparent Management of Reconfigurable Hardware in Embedded Operating Systems
A Linear Comparator-Based Fully Digital Delay Element
Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding
Approximate Swish Activation Function for Low-Energy Yet Low-Error VLSI Implementations
A Novel Technique for Noise-Tolerance in Dynamic Circuits
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits
Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers
Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum
Design Space Exploration for CNN Offloading to FPGAs at the Edge
Tunable Voltage-Mode Subthreshold CMOS Neuron
Implementation of a QPSK Symbol Synchronizer in Xilinx System Generator
On the Limitations of Power Macromodeling Techniques
Design of Low Power 5-Bit Hybrid Flash ADC
Impact of Technology Scaling in the Clock System Power
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles
A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
TiAS: Time Aware Split Computing to Secure AI/ML Workloads for FPGA based Edge Platforms against Unintentional Delays
HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model
Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles
Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks
Two-Phase Resonant Clock Distribution
Exploring Security Solutions and Vulnerabilities for Embedded Non-Volatile Memories
Transfer Learning Based Hybrid Quantum Neural Network Model for Surface Anomaly Detection
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs
Session Based Core Test Scheduling for 3D SOCs
Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms
A Comparative Study on Dicing of Multiple Project Wafers
Towards Independent On-device Artificial Intelligence
Accurate Synthesis of Arithmetic Operations with Stochastic Logic
Design of a Novel CNTFET-based Reconfigurable Logic Gate
Low Power 2.5 Gb/s Serializer for SOC Applications
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing
Variation-aware Design Space Exploration of Mott Memristor-based Neuristors
Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design
Exploring the Correlation Between DRAM Latencies and Rowhammer Attacks
Enhanced Redundant via Insertion with Multi-via Mechanisms
Quantum Anomalous Hall Effect Ternary Content Addressable Memory
A 6T SRAM based reconfigurable in-memory XOR/XNOR and accumulation architecture
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor
Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design
Data extraction from SystemC designs using debug symbols and the SystemC API
Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation
Fault-Tolerant Clock Synchronization with High Precision
Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA Cores
Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems
Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets
Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE Approach
Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing
HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation
Investigating Reliability and Security of Integrated Circuits and Systems
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths
Using electromagnetic emanations for variability characterization in Flash-based FPGAs
WAFER: Wearable, Ambient-Aware Adversarial Fall Event Detection System Using a RISC-V SoC Architecture
Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures
A Memristive Reconfigurable Neuromorphic Array for Neuro-Inspired Dynamic Architectures
TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs
Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage
Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM
A Double-Edge Implicit-Pulsed Level Convert Flip-Flop
SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs
Architecture for Dual-Mode Quadruple Precision Floating Point Adder
Message from the general and program chairs
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders
CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones
QUANTIFY: A Framework for Resource Analysis and Design Verification of Quantum Circuits
A PUF-Enhanced Ring Oscillator-Based Authentication System for IoT Devices
Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than Moore
RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis
Exploiting Routing Asymmetry for APUF Implementation in FPGA: A Proof-of-Concept
Hardware Implementation of Reconfigurable Separable Convolution
A Case Study in Developing an Efficient Multi-threaded EDA Parser: Synopsys SDF Parser
Big Data Processing with FPGA Supercomputers: Opportunities and Challenges
Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs
A novel method to mitigate TSV electromigration for 3D ICs
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model
Bi-Direction Synthesis for Reversible Circuits
ICE TEA: Insertion of Custom Early Exits for Time-, Energy- & Anomaly-Aware Neural Networks
Design of Fractal Image Compression on SOC
2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany
Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference
Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System
Advancing IoT Security Through Run-time Monitoring & Post-Execution Verification
A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking
Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System
Low Power Image Acquisition Scheme Using On-Pixel Event Driven Halftoning
Data-Width-Driven Power Gating of Integer Arithmetic Circuits
MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters
A Flexible Pay-per-Device Licensing Scheme for FPGA IP Cores
ReRise: An Adversarial Example Restoration System for Neuromorphic Computing Security
Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms
Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes
STAIRoute: Global routing using monotone staircase channels
Testing Skew and Logic Faults in SoC Interconnects
Federated Learning with Spiking Neural Networks in Heterogeneous Systems
Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters
Fast quantum circuit simulation using hardware accelerated general purpose libraries
A 2.4 GHz Low-Power Low-Phase-Noise CMOS LC VCO
A New Walsh Hadamard Transform Architecture Using Current Mode Circuit
SDN-Based Circuit-Switching for Many-Cores
High-Performance TSV Architecture for 3-D ICs
Message from the Quantum Computing Workshop Chairs; ISVLSI 2024
Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs
Multi-level, Memory-Based Logic Using CMOS Technology
FF-GFA: Flipped Folded Architecture enabled Power- and Area-Efficient Gabor Filter Design
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti"
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM
A Subword-Parallel Multiplication and Sum-of-Squares Unit
ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies
A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache Module
Self-Timed Thermally-Aware Circuits
A High Performance Unified BCD and Binary Adder/Subtractor
Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits
Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges
Fast and Precise Power Prediction for Combinational Circuits
Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008, 7-9 April 2008, Montpellier, France
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis
Transient Effect Ring Oscillators Leak Too
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization
Neuromemristive Extreme Learning Machines for Pattern Classification
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction
Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits
Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet
Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch
Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks
Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach
Memory subsystem architecture design for multimedia applications
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications
VLSI 2010 Annual Symposium - Selected papers
Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling
Optimization of Convolutional Neural Networks on Resource Constrained Devices
Carbon-Aware Design of DNN Accelerators: Bridging Performance and Sustainability
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Action Evaluation Hardware Accelerator for Next-Generation Real-Time Reinforcement Learning in Emerging IoT Systems
An Event Autoencoder for High-Speed Vision Sensing
Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults
Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication
Block-wise Extraction of Rent's Exponents for an Extensible Processor
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators
A Novel Architecture using Dynamic Computing Nodes to Improve Multi-Access Edge Cluster Productivity
Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL
Write Pulse Scaling for Energy Efficient STT-MRAM
Exploiting Principle of Moving Target Defense to Secure FPGA Systems
Optimal Application Allocation and Wireless User Association for Robust Edge Computing
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training
Implementation of Grover's Algorithm to Solve the Maximum Clique Problem
Operational Quantum Annealers are Cursed by their Qubits Interconnection Topologies
Parallel Simulation-Based Verification of RC Power Grids
Quantitative Comparison of Optical and Electrical H, X, and Y clock Distribution Networks
Machine Learning Intervened RIS-Based RF Interference Management for IoT
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing
2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017
Automatic Validation and Design of Microfluidic Devices Following the ISO 22916 Standard
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects
Glitch Power Reduction via Clock Skew Scheduling
Designing for Security Within and Between IoT Devices
Application Profiling Using Register-Instruction Hardware Performance Counters
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration
Adaptive Porting of Analog IPs with Reusable Conservative Properties
Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip
Statistical Analysis of Resource Usage of Embedded Systems Modeled in EAST-ADL
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices
CT-Cache: Compressed Tag-Driven Cache Architecture
Finite State Machine Implementation with Single-Electron Tunneling Technology
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors
Microplumber: Finding Hidden Sources of Power-Based SCL in Microcontrollers
A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems
Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs
Routing-aware resource allocation for mixture preparation in digital microfluidic biochips
iTPM: Exploring PUF-based Keyless TPM for Security-by-Design of Smart Electronics
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption
Challenges and Perspectives of Nanoelectromagnetics in the THz Range
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
A Multi-grained Reconfigurable Accelerator for Approximate Computing
A Digital Offset Reduction Method for Dynamic Comparators Based on Phase Measurement
IRC Cross-Layer Design Exploration of Intermittent Robust Computation Units for IoTs
Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis
System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms
FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes
Murphy goes 3D
A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory
A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks
The MOSART Mapping Optimization for Multi-Core ARchiTectures
A Low Power Embedded Dataflow Coprocessor
System Exploration of SystemC Designs
Enhancing the Robustness of Deep Neural Networks from "Smart" Compression
Supply Voltage Scalable System Design Using Self-Timed Circuits
Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic
Energy-aware Incremental OTA Update for Flash-based Batteryless IoT Devices
Resource-Efficient Adaptive-Network Inference Framework with Knowledge Distillation-Based Unified Learning
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic
Memristor Crossbar Based Programmable Interconnects
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip
Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing
A CMOS Multi-sensor System for 3D Orientation Determination
Machine Learning Fault Injection Detection in Clock Signals: An Analysis of Frequency Impact
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
LightRoAD: Lightweight Rowhammer Attack Detector
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning
QUKU: A Two-Level Reconfigurable Architecture
On Time Redundancy of Fault Tolerant C-Based MPSoCs
An Improved Dynamic Optically Reconfigurable Gate Array
Efficient Autonomous Driving System Design: From Software to Hardware
Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering
Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
Online Unusual Behavior Detection for Temperature Sensor Networks
A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation
Increasing Data TLB Resilience to Transient Errors
Designing Data-Aware Network-on-Chip for Performance
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays
A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography
A study on polymorphing superscalar processor dynamically to improve power efficiency
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA)
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library
Reverse Engineering Register to Variable Mapping in High-level Synthesis
Fault Tolerant Algorithms for Network-On-Chip Interconnect
A Novel CMOS-Based Fully Differential Operational Floating Conveyor
A Designer's Rationale for Nanoelectronic Hardware Security Primitives
Validating SPARK: High Level Synthesis Compiler
Technology Mapping for Cryogenic CMOS Circuits
Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips
The Future of Nanoelectronics: New Materials, Architectures and Devices
Real-Time Person Recognition Using MoveNet for Pose-Based Identification
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor
Hardware Verification Using Software Analyzers
On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise
Performance Evaluation for Three-Dimensional Networks-On-Chip
Quantum-enhanced optimization for patient stratification in clinical trials
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms
LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization
Methodology for Efficient Multi-threading of Parsers in EDA Tools
Attacking an SRAM-Based PUF through Wearout
A Process Variation Tolerant Self-Compensating Sense Amplifier Design
Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing Optimization
Compiler-Directed Management of Leakage Power in Software-Managed Memories
Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage
An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning
Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications
A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional Networks
On runtime task graph extraction in MPSoC
Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators
Optimal Timing for Skew-Tolerant High-Speed Domino Logic
LLPA: Logic State Based Leakage Power Analysis
Floating-Point Arithmetic Using GPGPU on FPGAs
Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic
Fixed-Load Energy Recovery Memory for Low Power
A NoC Traffic Suite Based on Real Applications
Fine-Grained Fault Tolerance for Process Variation-Aware Caches
Subthreshold Pass Transistor Logic for Ultra-Low Power Operation
Highly Efficient Transforms Module Solution for a H.264/SVC Encoder
SAGE: Shapley Attention Graph nEtwork for Gate-level Trojan Detection and Localization
Statistical Timing-Based Post-Placement Leakage Recovery
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults
Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops
Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation
Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization
Invited: A Hardware-Algorithm Vision for In-Sensor Intelligence
Enhancing Security of Memristor Computing System Through Secure Weight Mapping
Post-Placement Pin Optimiztion
Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic
Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks
Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs
Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper)
Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams
A Compact CMOS Ring Oscillator with Temperature and Supply Compensation for Sensor Applications
LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis
Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips
A Decomposition Method for MCT Gates Considering T-depth of Each Qubit