yusuke1997/dblp-id-title huggingface dataset:
Dynamic learning based scan chain diagnosis
A novel low power 11-bit hybrid ADC using flash and delay line architectures
A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation
High-Speed Non-Linear Asynchronous Pipelines
Package Design for High Performance ICs
GLAsT: Learning formal grammars to translate natural language specifications into hardware assertions
Stochastic circuit reliability analysis
Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications
Distributed fair scheduling for many-cores
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate
Structural Testing Based on Minimum Kernels
MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups
Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors
Scheduling using mixed arithmetic: an ILP formulation
Cognitive Digital Twin for Manufacturing Systems
Clause simplification through dominator analysis
LBICA: A Load Balancer for I/O Cache Architectures
Analysis and evaluation of per-flow delay bound for multiplexing models
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads
PWL: a progressive wear leveling to minimize data migration overheads for nand flash devices
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model
On the premises and prospects of timing speculation
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost
Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture
On the Verification of High-Order Constraint Compliance in IC Design
Controlled timing-error acceptance for low energy IDCT design
Cost-effective decap selection for beyond die power integrity
"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design
A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture
Efficient high-sigma yield analysis for high dimensional problems
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs
A unified online Fault Detection scheme via checking of Stability Violation
Design, Characterization & Modelling of a CMOS Magnetic Field Sensor
RTL-Aware Dataflow-Driven Macro Placement
PowerAdviser: An RTL power platform for interactive sequential optimizations
Evaluating coverage of error detection logic for soft errors using formal methods
BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter
Towards high-performance polarity-controllable FETs with 2D materials
Exploiting transaction level models for observability-aware post-silicon test generation
A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms
High-level modeling and synthesis for embedded FPGAs
STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads
Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime
Managing Variability and Reuse of Extra-functional Control Software in CPPS
RF-BIST: Loopback Spectral Signature Analysis
On the test of microprocessor IP cores
Approximation Trade Offs in an Image-Based Control System
A Lightweight Congestion Control Technique for NoCs with Deflection Routing
A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks
Sequential Equivalence Checking without State Space Traversal
DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation
Correlation controlled sampling for efficient variability analysis of analog circuits
Design flow for embedded FPGAs based on a flexible architecture template
Compiler-driven dynamic reliability management for on-chip systems under variabilities
Thermal-Awareness in a Soft Error Tolerant Architecture
Level of Similarity: A Metric for Fault Collapsing
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets
Emerging Neural Workloads and Their Impact on Hardware
On bounding response times under software transactional memory in distributed multiprocessor real-time systems
Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation
Dynamic Refinement of Hardware Assertion Checkers
WULoRa: An energy efficient IoT end-node for energy harvesting and heterogeneous communication
A framework for fast hardware-software co-simulation
Variability and statistical analysis flow for dynamic linear systems with large number of inputs
Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology
The Post-pandemic Effects on IoT for Safety: The Safe Place Project
User-aware energy efficient streaming strategy for smartphone based video playback applications
Analyzing On-Chip Communication in a MPSoC Environment
SparseInfer: Training-free Prediction of Activation Sparsity for Fast LLM Inference
Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective
Digital circuits reliability with in-situ monitors in 28nm fully depleted SOI
Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing
Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitor
MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior
Stochastic analysis of Bubble Razor
Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy
HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization
Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems
On test conditions for the detection of open defects
A Network-on-Chip-based turbo/LDPC decoder architecture
MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability
Scalable reconfigurable channel decoder architecture for future wireless handsets
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
Smart imagers of the future
Flash read disturb management using adaptive cell bit-density with in-place reprogramming
System Design for Flexibility
Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study
Enabling the heterogeneous accelerator model on ultra-low power microcontroller platforms
Panel: Reliability of data centers: Hardware vs. software
Clock skew scheduling for soft-error-tolerant sequential circuits
Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers
Co-design techniques for distributed real-time embedded systems with communication security constraints
Design space pruning through hybrid analysis in system-level design space exploration
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition
Memristor PUFs: a new generation of memory-based physically unclonable functions
GARDA: a diagnostic ATPG for large synchronous sequential circuits
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections
An analog non-volatile neural network platform for prototyping RF BIST solutions
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITY
Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
A co-design methodology for scalable quantum processors and their classical electronic interface
Reuse distance analysis for locality optimization in loop-dominated applications
Hardware primitives for the synthesis of multithreaded elastic systems
DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems
MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver
Multi-Partner Project: Orchestrating Deployment and Real-Time Monitoring - NEPHELE Multi-Cloud Ecosystem
Maximizing Conditonal Reuse by Pre-Synthesis Transformations
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Scalable liveness checking via property-preserving transformations
Using a Victim Buffer in an Application-Specific Memory Hierarchy
Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs
Systematic Transaction Level Modeling of Embedded Systems with SystemC
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors
Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers
Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform
Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications
SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design
Learning to Mitigate Rowhammer Attacks
SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures
An extension to SystemC-A to support mixed-technology systems with distributed components
Loosely Time-Triggered Architectures for Cyber-Physical Systems
Retargetable Code Optimization for Predicated Execution
Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips
Enabling improved power management in multicore processors through clustered DVFS
Reliable and Energy-Aware Fixed-Priority (m, k)-Deadlines Enforcement with Standby-Sparing
Enabling SNN-Based Near-MEA Neural Decoding with Channel Selection: An Open-HW Approach
A graph based algorithm for optimal buffer insertion under accurate delay models
FlexForge: Efficient Reconfigurable Cloud Acceleration via Peripheral Resource Disaggregation
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization
QoR-aware power capping for approximate big data processing
Extrax: security extension to extract cache resident information for snoop-based external monitors
Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Finding All DC Operating Points Using Interval Arithmetic Based Verification Algorithms
Has anything changed in electronic design since 1983?
Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique
NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing
AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cells
Generalized Data Transformations for Enhancing Cache Behavior
A gridless multi-layer router for standard cell circuits using CTM cells
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C
Enhanced testing performance via unbiased test sets
Lattice Quantization
A multi-core debug platform for NoC-based systems
FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays
ITRS 2011 Analog EDA Challenges and Approaches
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects
Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test
Formal semantics for PSL modeling layer and application to the verification of transactional models
Interactive presentation: Behavioral modeling of delay-locked loops and its application to jitter optimization in ultra wide-band impulse radio systems
Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking
Is TSV-based 3D integration suitable for inter-die memory repair?
Automatic identification of application-specific functional units with architecturally visible storage
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling
An approach for dynamic selection of synthesis transformations based on Markov Decision Processes
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs
A novel criticality computation method in statistical timing analysis
From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time Systems
A Real-Time Streaming Memory Controller
User Interaction Aware Reinforcement Learning for Power and Thermal Efficiency of CPU-GPU Mobile MPSoCs
A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems
Very wide register: an asymmetric register file organization for low power embedded processors
A parameterized timing-aware flip-flop merging algorithm for clock power reduction
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints
Substituting transition faults with path delay faults as a basic delay fault model
A near-future prediction method for low power consumption on a many-core processor
Compact Binaries with Code Compression in a Software Dynamic Translator
Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision
A method for design of impulse bursts noise filters optimized for FPGA implementations
STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra
Cartesian multipole based numerical integration for 3D capacitance extraction
Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits
Functional Validation of System Level Static Scheduling
A novel tag access scheme for low power L2 cache
SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum- Flux - Parametron Superconducting Circuits
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array
Maximum circuit activity estimation using pseudo-boolean satisfiability
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones
Static Aging Analysis Using 3-Dimensional Delay Library
Optimized Generation of Data-Path from C Codes for FPGAs
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
CMOS open defect detection by supply current test
NPSE: A High Performance Network Packet Search Engine
IBM's Qiskit Tool Chain: Working with and Developing for Real Quantum Computers
High-level test synthesis for delay fault testability
Comprehensive Analysis of Hyperdimensional Computing Against Gradient Based Attacks
DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems
HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors
HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systems
An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability
An Overview of Approaches Towards the Timing Analysability of Parallel Architecture
Analysis of High-Level Address Code Transformations for Programmable Processors
Out-of-channel data placement for balancing wear-out and I/O workloads in RAID-enabled SSDs
Dynamic Minimization of Word-Level Decision Diagrams
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation
3D-MMC: a modular 3D multi-core architecture with efficient resource pooling
Context-aware Multi-Model Object Detection for Diversely Heterogeneous Compute Systems
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks
Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles
Verification of Temporal Properties in Automotive Embedded Software
Generation of Interconnect Topologies for Communication Synthesis
Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive Applications
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
A TSV noise-aware 3-D placer
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
A Synthesizable IP Core for DVB-S2 LDPC Code Decoding
A cross-level verification methodology for digital IPs augmented with embedded timing monitors
Use of statistical timing analysis on real designs
Towards Forward-Only Learning for Hyperdimensional Computing
Towards Cycle-based Shuttling for Trapped-Ion Quantum Computers (Extended Abstract)
Approximate Logic Synthesis of Very Large Boolean Networks
EPIC: Ending Piracy of Integrated Circuits
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering
Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks
Latency analysis of self-suspending task chains
SuperRange: Wide operational range power delivery design for both STV and NTV computing
Exploiting assertions mining and fault analysis to guide RTL-level approximation
Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators
Incorporating compiler feedback into the design of ASIPs
Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories
BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory
Towards Formal Verification of Optimized and Industrial Multipliers
Analytical Design Space Exploration of Caches for Embedded Systems
PetaOps/W edge-AI $\mu$ Processors: Myth or reality?
Design challenges at 65nm and beyond
Bayesian Optimized Importance Sampling for High Sigma Failure Rate Estimation
FPGA accelerated DNA error correction
A high-level debug environment for communication-centric debug
Inverters' self-checking monitors for reliable photovoltaic systems
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell
An Automated Design Environment for Micromechanical Sensors
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits
An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain
PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows
Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel
An Efficient Logic Operation Scheduler for Minimizing Memory Footprint of In-Memory SIMD Computation
A Unified Design Space for Regular Parallel Prefix Adders
Placement Using a Localization Probability Model (LPM)
On Programmable Memory Built-In Self Test Architectures
CMOS Structures Suitable for Secured Hardware
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model
The Road towards Predictable Automotive High - Performance Platforms
Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores
Heterogeneous Static Timing Analysis with Advanced Delay Calculator
An instruction scratchpad memory allocation for the precision timed architecture
Unknown blocking scheme for low control data volume and high observability
Design for Verification of SystemC Transaction Level Models
Yield Improvement and Repair Trade-Off for Large Embedded Memories
System-on-a-chip processor synchronization support in hardware
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design
Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks
Detailed-Routability of FPGAs with Extremal Switch-Block Structures
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits
Precise evaluation of the fault sensitivity of OoO superscalar processors
Increasing the accuracy of SAT-based debugging
Schedulability-aware SPM Allocation for preemptive hard real-time systems with arbitrary activation patterns
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing
Inter-IP Malicious Modification Detection through Static Information Flow Tracking
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach
Test exploration and validation using transaction level models
Accurate source-level simulation of embedded software with respect to compiler optimizations
Cache-Aware Scratchpad Allocation Algorithm
Forseti: An Efficient Basic-block-level Sensitivity Analysis Framework Towards Multi-bit Faults
Functional test generation for behaviorally sequential models
Trends and challenges in wireless application processors
Low power mobile internet devices using LTE technology
Programmability and performance portability aspects of heterogeneous multi-/manycore systems
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs
Auto WS: Automate Weights Streaming in Layer-Wise Pipelined DNN Accelerators
Wireless communication - successful differentiation on standard technology by innovation
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths
A systematic approach to the test of combined HW/SW systems
Hardware Accelerated Power Estimation
Fast Hardware-Software Co-simulation Using VHDL Models
AVICA: an access-time variation insensitive L1 cache architecture
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Characterization-Free Behavioral Power Modeling
A fully-digital EM pulse detector
Framework for quantifying and managing accuracy in stochastic circuit design
Secure Intermittent Computing Protocol: Protecting State Across Power Loss
Achieving 100% cell-aware coverage by design
Quantum State Preparation Using an Exact CNOT Synthesis Formulation
Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver
Model driven resource usage simulation for critical embedded systems
Complexity of sequential ATPG
An effective triple patterning aware grid-based detailed routing approach
A new reconfigurable clock-gating technique for low power SRAM-based FPGAs
A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction
Combining MBP-speculative computation and loop pipelining in high-level synthesis
Lens aberration aware timing-driven placement
Solving Constraint Satisfaction Problems Using the Loihi Spiking Neuromorphic Processor