yusuke1997/dblp-id-title huggingface dataset:
Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs
XTW, a parallel and distributed logic simulator
Fast floating random walk algorithm formulti-dielectric capacitance extraction with numerical characterization of Green's functions
A Versatile Mapping Approach for Technology Mapping and Graph Optimization
Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips
Acceleration of mincut partitioning using hardware CAD accelerator TP5000
Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications
Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU
A SAT Encoding for Optimal Clifford Circuit Synthesis
Fast synthesis of threshold logic networks with optimization
Improved symbolic simulation by functional-space decomposition
Spintronics based stochastic computing for efficient Bayesian inference system
An efficient scheduling algorithm for multiple charge migration tasks in hybrid electrical energy storage systems
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology
Adaptive interpolation-based model checking
Efficient FPGA implementation of local binary convolutional neural network
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs
Deriving a new efficient algorithm for min-period retiming
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures
Soft Error Resiliency Characterization on IBM BlueGene/Q Processor
Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems
One-pass Synthesis for Field-coupled Nanocomputing Technologies
Design of an energy-autonomous bio-sensing system using a biofuel cell and 0.19V 53μW integrated supply-sensing sensor with a supply-insensitive temperature sensor and inductive-coupling transmitter
A low-leakage current power 180-nm CMOS SRAM
ASP-DAC 2017 keynote speech I-1: Heterogeneous integration of X-tronics: Design automation and education
Using segmentation to improve schedulability of RRA-based NoCs with mixed traffic
A new congestion-driven placement algorithm based on cell inflation
ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks
Technological exploration of RRAM crossbar array for matrix-vector multiplication
Introduction to H.264 advanced video coding
Design automation for adiabatic circuits
LFF algorithm for heterogeneous FPGA floorplanning
Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoC
Increasing FPGA resilience against soft errors using task duplication
Suspect2vec: a suspect prediction model for directed RTL debugging
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems
A low-overhead PUF based on parallel scan design
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study
An Efficient Approximate Node Merging with an Error Rate Guarantee
Benefits and barriers for probabilistic design
Mapping method for dynamically reconfigurable architecture
Efficient global fanout optimization algorithms
Escape routing of differential pairs considering length matching
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
Adaptive computing: what can it do, where can it go?
Timed circuits: a new paradigm for high-speed design
Theoretical Optimal Specifications of Memcapacitors for Charge-Based In-Memory Computing
A 2.17μW@120fps Ultra-Low-Power Dual-Mode CMOS Image Sensor with Senputing Architecture
WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing
A two-stage genetic algorithm method for optimization the Sigma-Delta modulators
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs
MAIA: a framework for networks on chip generation and verification
Area-Oriented Optimization After Standard-Cell Mapping
Rule-based optimization of reversible circuits
Manipulation of regular expressions under length constraints using zero-suppressed-BDDs
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Optimum PLA folding through boolean satisfiability
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits
An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation
SoC test scheduling using the B-tree based floorplanning technique
Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time
Emerging Non-Volatile Memories for Computation-in-Memory
Back-end-aware Fault-tolerant Quantum Oracle Synthesis
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches
An automatic interconnection rectification technique for SoC design integration
Automatic design for bit-serial MSPA architecture
Is 3D integration an opportunity or just a hype?
Non-intrusive dynamic profiler for multicore embedded systems
SeFAct: selective feature activation and early classification for CNNs
Tool Capabilities Needed for Designing 100 MHz Interconnects
Using data replication to reduce communication energy on chip multiprocessors
Generating high coverage tests for SystemC designs using symbolic execution
Mosaic: an automated synthesis flow for boolean logic based on memristor crossbar
TranGen: a SAT-based ATPG for path-oriented transition faults
iPD: An Open-source intelligent Physical Design Toolchain
Robust spatial correlation extraction with limited sample via L1-norm penalty
Variation-aware voltage island formation for power efficient near-threshold manycore architectures
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization
High-speed GaAs MESFET Digital IC Design for Optical Communication Systems
Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique
A novel O(n) parallel banker's algorithm for System-on-a-Chip
Ultra low-power ANSI S1.11 filter bank for digital hearing aids
CMOS Image Sensors with Video Compression
New electromigration modeling and analysis considering time-varying temperature and current densities
Scheduling multi-rate real-time applications on clustered many-core architectures with memory constraints
An efficient linear time triple patterning solver
Fault Dictionary Size Reduction for Million-Gate Large Circuits
Fine-grained dynamic voltage scaling on OLED display
Large-scale linear circuit simulation with an inversed inductance matrix
Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG Recording
System-level exploration tool for energy-aware memory management in the design of multidimensional signal processing systems
Compilation of Entangling Gates for High-Dimensional Quantum Systems
Arbitrary long digit integer sorter HW/SW co-design
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
Super-K: A SoC for single-chip ultra mobile computer
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing
Deflection routing in 3D Network-on-Chip with TSV serialization
Dark silicon-aware hardware-software collaborated design for heterogeneous many-core systems
On multiple-voltage high-level synthesis using algorithmic transformations
Jitter spectral extraction for multi-gigahertz signal
HielM: Highly flexible in-memory computing using STT MRAM
Designing reliable circuit in the presence of soft errors
Low-power high-level synthesis using latches
The RDT network router chip
Hardware Trojan Detection and High-Precision Localization in NoC-Based MPSoC Using Machine Learning
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
Recent research development and new challenges in analog layout synthesis
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design
Modular scheduling of distributed heterogeneous time-triggered automotive systems
Capacitance Extraction and Power Grid Analysis Using Statistical and AI Methods
Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision
Cross talk driven placement
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method
DECC: Differential ECC for Read Performance Optimization on High-Density NAND Flash Memory
Towards cognitive obfuscation: impeding hardware reverse engineering based on psychological insights
Analysis of communication delay bounds for network on chips
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs
A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architecture
Process design kit for flexible hybrid electronics
A Graph Reduction Approach to Symbolic Circuit Analysis
An on-chip 96.5% current efficiency CMOS linear regulator
Floorplanning with power supply noise avoidance
Space- and Time-Efficient BDD Construction via Working Set Control
Parallel transistor level circuit simulation using domain decomposition methods
Priority directed test generation for functional verification using neural networks
Timing-constrained congestion-driven global routing
Using GALS architecture to reduce the impact of long wire delay on FPGA performance
LibGALS: a library for GALS systems design and modeling
Detectability of internal bridging faults in scan chains
Design and chip implementation of an instruction scheduling free ubiquitous processor
A fast heuristic scheduling algorithm for periodic ConcurrenC models
Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and Augmentation
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)
Integrated algorithmic logical and physical design of integer multiplier
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion
Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers
Robust test generation for power supply noise induced path delay faults
Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing
ASP-DAC 2015 keynote speech III: When and how will an AI be smart enough to design?
A low-power FPGA based on autonomous fine-grain power-gating
HLIFT: A high-level information flow tracking method for detecting hardware Trojans
Improving validation coverage metrics to account for limited observability
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing
"All Programmable SOC FPGA for networking and computing in big data infrastructure"
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node
Power Reduction in Pipelines
Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process
Efficient floating point precision tuning for approximate computing
VLSI implementation of a switch fabric for mixed ATM and IP traffic
Analyzing electrical effects of RTA-driven local anneal temperature variation
Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures
A fast and provably bounded failure analysis of memory circuits in high dimensions
Integrated power supply planning and floorplanning
Timing-driven placement based on monotone cell ordering constraints
Xbox360 TM Front Side Bus - A 21.6 GB/s End-to-End Interface Design
A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system
Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy
Multiple test set generation method for LFSR-based BIST
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations
Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability
Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
A new system partitioning method under performance and physical constraints for multi-chip modules
Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K
Controlling inductive cross-talk and power in off-chip buses using CODECs
Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays
Are we ready for system-level synthesis?
A Fast and Robust Global Router with Capacity Reduction Techniques
Enabling fast preemption via Dual-Kernel support on GPUs
An efficient design-for-verification technique for HDLs
Build reliable and efficient neuromorphic design with memristor technology
Optimizing Data Layout for Racetrack Memory in Embedded Systems
SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency
A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems
Application-specific fault-tolerant architecture synthesis for digital microfluidic biochips
Best ways to use billions of devices on a wireless mobile SoC
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
Linear optimal one-sided single-detour algorithm for untangling twisted bus
Leakage-aware thermal management for multi-core systems using piecewise linear model based predictive control
A buffer planning algorithm with congestion optimization
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits
Design flow and methodology for 50M gate ASIC
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk
SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives
A built-in power supply noise probe for digital LSIs
A physical-location-aware fault redistribution for maximum IR-drop reduction
Improved on-chip router analytical power and area modeling
Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques
Arbitrary and Variable Precision Floating-Point Arithmetic Support in Dynamic Binary Translation
Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device
SWAT: Assertion-based debugging of concurrency issues at system level
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication
Network-on-Chip router design with Buffer-Stealing
A dataflow specification for system level synthesis of 3D graphics applications
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects
Register-transfer level functional scan for hierarchical designs
Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications
CBLO: a clustering based linear ordering for netlist partitioning
Instruction buffering exploration for low energy VLIWs with instruction clusters
A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications
Open architecture tester: what is a key issue of OAT?
A New Design for Double Edge Triggered Flip-flops
The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis
High-Effort Logic Synthesis Using Randomized Transduction
Performance bound and yield analysis for analog circuits under process variations
RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
A unified multi-corner multi-mode static timing analysis engine
Sparse statistical model inference for analog circuits under process variations
Model Checking: Its Basics and Reality (Embedded Tutorial)
Optimal loop bandwidth design for low noise PLL applications
Analysis of MOS cross-coupled LC -tank oscillators using short-channel device equations
Automatic re-coding of reference code into structured and analyzable SoC models
ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator
Improved Boolean function hashing based on multiple-vertex dominators
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies
A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression
Low power design challenges for the decade (invited talk)
LanCe: A Comprehensive and Lightweight CNN Defense Methodology against Physical Adversarial Attacks on Embedded Multimedia Applications
Every test makes a difference: Compressing analog tests to decrease production costs
Power distribution techniques for dual VDD circuits
Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems
Advanced technologies for brain-inspired computing
STLAC: A spatial and temporal locality-aware cache and network-on-chip codesign for tiled many-core systems
A switched-loop-filter PLL with fast phase-error correction technique
Architecture evaluation based on the datapath structure and parallel constraint
Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET's
A bit-write reduction method based on error-correcting codes for non-volatile memories
On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells
A Run-Time Memory Protection Methodology
Exploration of Low Power Adders for a SIMD Data Path
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism
Automatic assume guarantee analysis for assertion-based formal verification
Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies
Quantized deep neural networks for energy efficient hardware-based inference
A flexible hardware barrier mechanism for many-core processors
Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault Transformations
Deep Learning Inspired Capacitance Extraction Techniques
A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles
A 500-MHz low-power five-port CMOS register file
Dependent latch identification in the reachable state space
Efficient parallel GPU algorithms for BDD manipulation
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate
HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines
Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach
ADAPT: An adaptive manycore methodology for software pipelined applications
Jitter amplifier for oscillator-based true random number generator
A three-stage-write scheme with flip-bit for PCM main memory
WIPE: Wearout Informed Pattern Elimination to Improve the Endurance of NVM-based Caches
Logic verification based on diagnosis techniques
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Model-based Programming Environment of Embedded Software for MPSoC
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems
A 64×64 1200fps dual-mode CMOS ion-image sensor for accurate DNA sequencing
A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
Single-chip multi-processor integrating quadruple 8-way VLIW processors with interface timing analysis considering power supply noise
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation
Wake-up protocols for controlling current surges in MTCMOS-based technology
Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits
PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning
Design rewiring based on diagnosis techniques
SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side Channels
Panel III: EDA market in China
Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration
Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming
On properties of Kleene TDDs
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults
Topology selection for energy minimization in embedded networks
ViraEye: An Energy-Efficient Stereo Vision Accelerator with Binary Neural Network in 55 nm CMOS
A three-dimensional millimeter-wave frequency-shift based CMOS biosensor using vertically stacked spiral inductors in LC oscillators
DRuiD: Designing reconfigurable architectures with decision-making support
Novel applications of deep learning hidden features for adaptive testing
Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection
Design techniques for functional-unit power gating in the Ultra-Low-Voltage region
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks
Future direction of synthesizabilty and interoperability of HDL's: part 2
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis
Cryo-CMOS Analog Circuits for Spin Qubit Control
An efficient STT-RAM-based register file in GPU architectures
Qubit placement to minimize communication overhead in 2D quantum architectures
Compiler-assisted refresh minimization for volatile STT-RAM cache
Towards Automated Generation of Chiplet-Based Systems Invited Paper
On mixture density and maximum likelihood power estimation via expectation-maximization
A PUF design for secure FPGA-based embedded systems
An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems