yusuke1997/dblp-id-title huggingface dataset:
Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities
System-in-package (SIP): challenges and opportunities
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier
A wireless power receiver with a 3-level reconfigurable resonant regulating rectifier for mobile-charging applications
Algorithms and DSP implementation of H.264/AVC
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
A 35 dB-linear exponential function generator for VGA and AGC applications
Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions
Function Smoothing with Applications to VLSI Layout
Energy aware real-time scheduling policy with guaranteed security protection
Exact routing for micro-electrode-dot-array digital microfluidic biochips
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region
MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier
A method for linking process-level variability to system performances
Path selection for monitoring unexpected systematic timing effects
Nonvolatile and Energy-Efficient FeFET-Based Multiplier for Energy-Harvesting Devices
Technology modeling and characterization beyond the 45nm node
Efficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation Acceleration
FPGA-Based HPC for Associative Memory System
ArISE: Aging-aware instruction set encoding for lifetime improvement
Implementing neural machine translation with bi-directional GRU and attention mechanism on FPGAs using HLS
A segmentation-based BISR scheme
Processor-core based design and test
Hardware prototyping of novel invasive multicore architectures
Thermal optimization in multi-granularity multi-core floorplanning
TCI Tester: Tester for Through Chip Interface
Skew scheduling and clock routing for improved tolerance to process variations
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs
Spec-based flip-flop and latch repeater planning
Structural planning of 3D-IC interconnects by block alignment
Power-efficient tree-based multicast support for Networks-on-Chip
Efficient symbolic multi-objective design space exploration
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment
Compiler-directed selective data protection against soft errors
A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks
Dependable VLSI Platform using Robust Fabrics
When to forget: A system-level perspective on STT-RAMs
Design tools for 3-D integrated circuits
A design of high-performance multiplier for digital video transmission
JustQ: Automated Deployment of Fair and Accurate Quantum Neural Networks
STEAM: Spline-based tables for efficient and accurate device modelling
Design of an energy-autonomous, disposable, supply-sensing biosensor using bio fuel cell and 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with inductive transmitter
SCGPSim: a fast SystemC simulator on GPUs
Exploiting temporal idleness to reduce leakage power in programmable architectures
Parallel-Log-Single-Compaction-Tree: Flash-Friendly Two-Level Key-Value Management in KVSSDs
A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver
Noise minimization during power-up stage for a multi-domain power network
Training low bitwidth convolutional neural network on RRAM
Realization of frequency-domain circuit analysis through random walk
Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques
Efficiently generating test vectors with state pruning
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings
Preserving synchronizing sequences of sequential circuits after retiming
Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration
CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams
A new design-for-test technique for reducing SOC test time
A transaction-oriented UVM-based library for verification of analog behavior
Energy-efficient, low-latency realization of neural networks through boolean logic minimization
Flexible and abstract communication and interconnect modeling for MPSoC
Effective analytical delay model for transistor sizing
EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper)
Schedule integration for time-triggered systems
Secure storage system and key technologies
QcAssert: Quantum Device Testing with Concurrent Assertions
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking
Efficient minimum spanning tree construction without Delaunay triangulation
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects
Property verification in the design of telecom applications
Exact and fast L1 cache simulation for embedded systems
Robust and efficient baseband receiver design for MB-OFDM UWB system
Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints
Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications
Accelerator-rich architectures: Implications, opportunities and challenges
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial)
Fault tolerant nanoelectronic processor architectures
Maximizing level of confidence for non-equidistant Checkpointing
Synthesis of high performance low power PTL circuits
Crosstalk Reduction by Transistor Sizing
The development of integrated circuit industry in China
PULSE: Progressive Utilization of Log-Structured Techniques to Ease SSD Write Amplification in B-epsilon-tree
PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices
Fast-extract with cube hashing
High-speed low-power FinFET based domino logic
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs
Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling
FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU
Concurrent Technology, Device, and Circuit Development for EEPROMs
Electrothermal analysis and optimization techniques for nanoscale integrated circuits
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits
Modeling and design optimization of ReRAM
A new method for model based frugal OPC
LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits
Event-oriented computing with reconfigurable platform
On-chip dynamic signal sequence slicing for efficient post-silicon debugging
Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and Minimization
5Gbps serial link transmitter with pre-emphasis
DPRoute: Deep Learning Framework for Package Routing
A frequent-value based PRAM memory architecture
On Decomposing Complex Test Cases for Efficient Post-silicon Validation
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training
Energy-Efficient Deep Neural Networks with Mixed-Signal Neurons and Dense-Local and Sparse-Global Connectivity
TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree
Capturing and analyzing requirement: in case of software and applying to hardware
Gate delay estimation in STA under dynamic power supply noise
Write-activity-aware page table management for PCM-based embedded systems
A new approach to assembly software retargeting for microcontrollers
A place and route aware buffered Steiner tree construction
Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs
Rapid prototyping on a structured ASIC fabric
OpenGeMM: A Highly-Efficient GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling
Timing-based anomaly detection in embedded systems
Parametric yield driven resource binding in behavioral synthesis with multi- V th /V dd library
A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC
Improving energy efficiency for energy harvesting embedded systems
Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
Close-to-optimal placement and routing for continuous-flow microfluidic biochips
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Static Probability Analysis Guided RTL Hardware Trojan Test Generation
SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks
Golay and wavelet error control codes in VLSI
An improved P-admissible floorplan representation based on Corner Block List
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function
Accelerator-centric deep learning systems for enhanced scalability, energy-efficiency, and programmability
Detecting multi-layer layout hotspots with adaptive squish patterns
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis
Design methodology for IRA codes
Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
Reconfigurable adaptive FEC system with interleaving
Temperature-aware data allocation strategy for 3D charge-trap flash memory
2D optical imaging using photosystem I photosensor platform with 32x32 CMOS biosensor array
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs
A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS
AxDNN: towards the cross-layer design of approximate DNNs
Efficient On-Device Incremental Learning by Weight Freezing
An Analysis on VLSI Interconnection Considering Skin Effect
High-level area and power-up current estimation considering rich cell library
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme
Improving boundary element methods for parasitic extraction
Statistical analysis of random telegraph noise in digital circuits
Yield enhancement for 3D-stacked ICs: Recent advances and challenges
Predictive power aware management for embedded mobile devices
Area-Driven FPGA Logic Synthesis Using Reinforcement Learning
Approximation-aware scheduling on heterogeneous multi-core architectures
A bandwidth efficient subsampling-based block matching architecture for motion estimation
A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration
DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations
Dependability, power, and performance trade-off on a multicore processor
UEDA: A Universal And Efficient Deformable Attention Accelerator For Various Vision Tasks
JTAG-based robust PCB authentication for protection against counterfeiting attacks
Machine learning based generic violation waiver system with application on electromigration sign-off
An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction
Majority-based synthesis for nanotechnologies
A hybrid approach for core-based system-level power modeling
Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches (Invited Paper)
Towards Read-Intensive Key-Value Stores with Tidal Structure Based on LSM-Tree
Multi-version checkpointing for flash file systems
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons
TITAC-2: An Asynchronous 32-bit Microprocessor
Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systems
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning
H.265/HEVC encoder for UHDTV
Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks
Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores
Evaluation of the statistical delay quality model
The feasibility of Carbon Nanotubes for power delivery in 3-D Integrated Circuits
EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts
Computation-oriented fault-tolerance schemes for RRAM computing systems
A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication
Low power techniques for address encoding and memory allocation
Register placement for low power clock network
Towards a Highly Interactive Design-Debug-Verification Cycle
TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
A simple non-coherent solution to the UWB-IR communication
Exploring power management in multi-core systems
Thermal optimization for memristor-based hybrid neuromorphic computing systems
Reusable embedded in-circuit emulator
Advanced processor design using hardware description language AIDL
A dynamic quality-scalable H.264 video encoder chip
Design for testability using register-transfer level partial scan selection
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform
The polygonal contraction heuristic for rectilinear Steiner tree construction
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs
Minimization of the expected path length in BDDs based on local changes
Automated Test Generation for Activation of Assertions in RTL Models
A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC
Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs
Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platforms
Design methodology of low-power microprocessors
Adaptive wire adjustment for bounded skew Clock Distribution Network
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
Optimal spacing and capacitance padding for general clock structures
Software defined architectures for data analytics
General purpose cross-referencing Microfluidic Biochip with reduced pin-count
Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired Algorithms
Logic foundry: rapid prototyping of FPGA-based DSP systems
A construction of minimal delay Steiner tree using two-pole delay model
Sound valve-control for programmable microfluidic devices
SystemC standard
Extending trace history through tapered summaries in post-silicon validation
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings
ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs
A Fully Synchronous Digital LDO with Built-in Adaptive Frequency Modulation and Implicit Dead-Zone Control
High-Definition Routing Congestion Prediction for Large-Scale FPGAs
An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects
An accurate and low-cost PM2.5 estimation method based on Artificial Neural Network
Minimizing MLC PCM write energy for free through profiling-based state remapping
Fault tolerance in neuromorphic computing systems
Reducing dynamic compilation overhead by overlapping compilation and execution
Semantic Guided Fine-Grained Point Cloud Quantization Framework for 3D Object Detection
Predicting Vt variation and static IR drop of ring oscillators using model-fitting techniques
The design and implementation of a DVB receiving chip with PCI interface
Propagation delay fault: a new fault model to test delay faults
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
A programmable built-in self-test core for embedded memories
Safety-Assured Design and Adaptation of Learning-Enabled Autonomous Systems
Power-performance trade-off using pipeline delays
Memory access driven storage assignment for variables in embedded system design
Techniques for Functional Test Pattern Execution
Lower bounds for dynamic BDD reordering
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs
Concerted wire lifting: Enabling secure and cost-effective split manufacturing
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects
FPGA laboratory system supporting power measurement for low-power digital design
ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges
An Automatic Router for the Pin Grid Array Package
Relay-based key management to support secure deletion for resource-constrained flash-memory storage devices
A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis
Voltage Island Generation under Performance Requirement for SoC Designs
A Write-friendly Arithmetic Coding Scheme for Achieving Energy-Efficient Non-Volatile Memory Systems
Gibbs sampling in power grid analysis
Integer linear programming-based synthesis of skewed logic circuits
A technology mapping algorithm for heterogeneous FPGAs
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks
Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations
Flexible packed stencil design with multiple shaping apertures for e-beam lithography
A new method for constructing IP level power model based on power sensitivity
Device-level placement for analog layout: an opportunity for non-slicing topological representations
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips
A length matching routing method for disordered pins in PCB design
SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power
Floorplanning and topology generation for application-specific network-on-chip
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method
Webpage-based benchmarks for mobile device design
An interconnect topology optimization by a tree transformation
System Architecture for Software Peripherals
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks
Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI
JIT-Based Context-Sensitive Timing Simulation for Efficient Platform Exploration
ChemComp: A Compilation Framework for Computing with Chemical Reaction Networks
Low power synthesis of finite state machines with mixed D and T flip-flops
A Retargetable Software Timing Analyzer Using Architecture Description Language
High-frequency circuit design for 25 Gb/s×4 optical transceiver
Accurate and efficient flow based congestion estimation in floorplanning
Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications
In-band mobile digital TV transmission technology for advanced television systems committee
Optimizing test-generation to the execution platform
Scalable interprocedural register allocation for high level synthesis
Optimizing power and performance for reliable on-chip networks
Decomposition based approach for synthesis of multi-level threshold logic circuits
DraXRouter: global routing in X-Architecture with dynamic resource assignment
RTL Regression Test Selection using Machine Learning
Computing brokerage and its application in VLSI design
Coarse-grained simulation method for performance evaluation a of shared memory system
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics
iEDA: An Open-source infrastructure of EDA
Real-time partitioned scheduling on multi-core systems with local and global memories
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography
Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future"
Automated Design of Wave Pipelined Multiport Register Files
An efficient dynamic task scheduling algorithm for battery powered DVS systems
Communication based FPGA synthesis for multi-output Boolean functions
Autonomous vehicle routing in multiple intersections
Design constraint of fine grain supply voltage control LSI
Efficient pattern relocation for EUV blank defect mitigation
Quality-driven design by bitwidth optimization for video applications
A vector-pipeline DSP for low-rate videophones
Power-Efficient Layer Mapping for CNNs on Integrated CPU and GPU Platforms: A Case Study
High-Level Estimation Techniques for Usage in Hardware/Software Co-Design
A high performance FIR filter dedicated to digital video transmission
Toward stochastic design for digital circuits: statistical static timing analysis
Library cell layout with Alt-PSM compliance and composability
FastPlace 2.0: an efficient analytical placer for mixed-mode designs
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
Simultaneous floorplanning and resource binding: a probabilistic approach
Virtual prototyping of heterogeneous automotive applications: matlab, SystemC, or both?
Dual-loop Digital PLL Design for Adaptive Clock Recovery
Small-area CMOS RF distributed mixer using multi-port inductors
Optimal prescribed-domain clock skew scheduling
A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules
HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN
Configurable multi-processor architecture and its processor element design
Design and test of a scalable security processor
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits
Property mining using dynamic dependency graphs
An approach for reducing dynamic power consumption in synchronous sequential digital designs
Selective time borrowing for DSP pipelines with hybrid voltage control loop
Register allocation for write activity minimization on non-volatile main memory
A low power CMOS circuit with Variable Souce Scheme (VSCMOS)
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS
Area-efficient FPGA logic elements: Architecture and synthesis
Boosting ReRAM-based DNN by Row Activation Oversubscription
An LP-based methodology for improved timing-driven placement
A layout approach to Monolithic Microwave IC
A 4.32 mm 2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications