yusuke1997/dblp-id-title huggingface dataset:
Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS
A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity
Analog/mixed-signal design challenges in 7-nm CMOS and beyond
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD
Look-up table leakage reduction for FPGAs
Design integration, DFT, and verification methodology for an MPEG 1/2 audio layer 3 (MP3) SoC device
A Monolithic GaN Driver and GaN Power Switch with Power-rail Charging Saturation Bootstrap technique achieving gate rising and falling time ratio of 1.28
A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology
A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology
A 95dB SNDR audio ΔΣ modulator in 65nm CMOS
A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shuffling
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules
Understanding the Antikythera Mechanism
Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies
IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019
ADC-based serial I/O receivers
Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters
A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation
A 1.8 mm 2 , 11 mA, 23.2 dB-NF, discrete-time filter for GSM/WCDMA/WLAN using retiming technique
A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector
Technology-design-manufacturing co-optimization for advanced mobile SoCs
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation
A 16 kb 1T1C FeRAM test chip using current-based reference scheme
100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications
A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator
3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014
Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits
A low-noise analog baseband in 65nm CMOS
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond
Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems
Switching noise reduction techniques for switched-capacitor voltage doubler
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC
Micro-robotics and energy harvesting forum
A10.13uJ/classification 2-channel Deep Neural Network-based SoC for Emotion Detection of Autistic Children
A fast-lock mixed-mode DLL using a 2-b SAR algorithm
A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking
Measurement and analysis of variability in 45nm strained-Si CMOS technology
A 1.6nJ/bit, 19.9μA peak current fully integrated 2.5mm 2 inductive transceiver for volume-constrained microsystems
A multi-phase sub-harmonic injection locking technique for bandwidth extension in silicon-based THz signal generation
Loopback architecture for wafer-level at-speed testing of embedded HyperTransport TM processor links
First-Harmonic Injection-Locked Ring Oscillators
A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS
Emerging application opportunities for SiGe technology
Within-die gate delay variability measurement using re-configurable ring oscillator
A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS
Impact of Transistor Level degradation on product reliability
A Low-IF CMOS Simultaneous GPS Receiver Integrated in a Multimode Transceiver
Setup time, hold time and clock-to-Q delay computation under dynamic supply noise
Quantitative characterization of substrate noise for physical design guides in digital circuits
Dynamic push-pull operational amplifier for AMLCD common voltage driver using minimum current limiting circuit
An Analog Neuromorphic On-Chip Training System with IGZO TFT-Based 6T1C 367-State Synaptic Memory Achieving 0.99-R 2 Linearity and 104-Times Enhanced Retention Time
Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis
Transceiver SoC for Wireless Indoor Sensing Data-fusion
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]
Standby voltage scaling for reduced power
SRAM embedded memory with low cost, flash EEPROM-switch-controlled redundancy
A wide-range DC/DC converter with 2 nd order digital compensation and direct battery connection in 40nm CMOS
MAX II: A low-cost, high-performance LUT-based CPLD
A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation
A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS
An improved "soft" eFPGA design and implementation strategy
A 219-to-238-GHz Coupled Standing-Wave VCO with 3.4-dBm Peak Output Power in 65nm CMOS
A Versatile Integrated Circuit for the Acquisition of Biopotentials
ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology
A Multi-Nodes Human Body Communication Sensor Network Control Processor
Advances in programmable logic
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers
Flexible solar-energy harvesting system on plastic with thin-film LC oscillators operating above ft for inductively-coupled power delivery
Power estimation and thermal budgeting methodology for FPGAs
Human++: autonomous wireless sensors for body area networks
A 12 bit 200 MHz low glitch CMOS D/A converter
A full-duplex transceiver front-end RFIC with code-domain spread spectrum modulation for Tx self-interference cancellation and in-band jammer rejection
Angle sensitive pixels in CMOS for lensless 3D imaging
A Multi-Level Power Management Architecture for Battery-Powered SPAD Drivers with Supply Intrinsic Quenching and 10-ns Dead Time
Non-invasion power monitoring with 120% harvesting energy improvement by maximum power extracting control for high sustainability power meter system
Advanced IC technologies I
A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter
A 28nm FDSOI 8192-point digital ASIC spectrometer from a Chisel generator
Just-in-time gain estimation of an RF digitally-controlled oscillator
An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function
A 2-GHz wide band low phase noise voltage-controlled oscillator with on-chip LC tank
Wireline Equalization using Pulse-Width Modulation
A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs
Device sizing for minimum energy operation in subthreshold circuits
A power efficient channel selection filter/coarse AGC with no range switching transients
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi
A voltage-scalable 10-b pipelined ADC with current-mode amplifier
A 40-Gb/s optical transceiver front-end in 45nm SOI CMOS technology
A high current driving charge pump with current regulation method
Evolutions of SAR ADC: From high resolution to high speed regime
BioWAP: A Reconfigurable Biomedical AI Processor with Adaptive Processing for Co-Optimized Accuracy and Energy Efficiency
A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications
Low-Cost Fully Autonomous Piezoelectric Energy Harvesting Interface Circuit with up to 6.14x Power Capacity Gain
A 0.5-3GHz Receiver with a Parallel Preselect Filter Achieving 120dB/dec Channel Selectivity and +28dBm Out-of-Band IIP3
A baseband processor for pulsed ultra-wideband signals
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology
Impact of within-die parameter fluctuations on future maximum clock frequency distributions
65nW CMOS temperature sensor for ultra-low power microsystems
A 10-bit 1GSample/s DAC in 90nm CMOS for Embedded Applications
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL
A novel on-chip voltage generator for low voltage DRAMs and PRAMs
Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables
A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity
A 92 F 2 / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation
Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs
Dual-mode, in-pixel linear and single-photon avalanche diode readout for low-light dynamic range extension in photodetector arrays
An energy efficient 32nm 20 MB L3 cache for Intel ® Xeon ® processor E5 family
Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC
Architecture of cluster-based FPGAs with memory
Nano-amp, active-bulk, weak-inversion analog circuits
Delta-Sigma Modulation in Direct Digital Frequency Synthesis
A monolithic digitally controlled ripple-based DC-DC converter with digital inductor current sensor
C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN
Architectures and circuits for RF CMOS receivers
A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultation
A monolithic 3.125 Gbps fiber optic receiver front-end for POF applications in 65 nm CMOS
An active rectifier/regulator combo circuit for powering biomedical implants
A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration
Pushing the speed limits of SiGe: C HBTs up to 0.5 Terahertz
High mobility channel CMOS technologies for realizing high performance LSI's
The changing landscape of system-on-a-chip design
A single-chip MPEG-2 codec based on customizable media microprocessor
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter
A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture
2-4 GHz Q-tunable LC bandpass filter with 172-dBHz peak dynamic range, resilient to +15-dBm out-of-band blocker
A High Accuracy and Ultra-Low Energy Environmental Sound Recognition Processor with Progressive Spectrogram Processing and Adaptive Weight Clustering Based Online Learning
A 1.8Gb/s 8GHz PSK-UWB Transceiver with Extended PPM/PWM Modulation and Embedded Carrier Spreading
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core
A low-power direct digital frequency synthesizer architecture for wireless communications
A VLSI low power solution for mobile satellite radio receivers
A 14-Cell Battery Monitoring AFE with 1mV Total Measurement Error and Integrated Electrochemical Impedance Spectroscopy
A Compact Reconfigurable 24-29.5/38-43.5GHz Phased Array Transceiver Front-End with Self-Interference Rejection and Wideband IF Supporting TDD/FDD Operation
A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopy
Spatial averaging and ordering in matched element arrays
Challenges for analog nanoscale technology
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007
A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration
A few behavioral modeling options for balancing verification coverage and credibility
A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP
Trend from ICs to 3D ICs to 3D systems
A low-power highly multiplexed parallel PRBS generator
ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, CICC 2001, San Diego, CA, USA, May 6-9, 2001
A 250MHz-2GHz wide range delay-locked loop
A CMOS VCO with 48% tuning range for modern broadband systems
Understanding the regenerative comparator circuit
A one chip super graphics CPU with direct unified memory controller suitable for car information and control system
An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS
Cryogenic CMOS: design considerations for future quantum computing systems
A 180 Kbit Embeddable MRAM Memory Module
On intellectual property protection
An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS
A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $\text{FoM}_{\mathrm{T}}$
Large-scale statistical performance modeling of analog and mixed-signal circuits
Design and implementation of a reconfigurable heterogeneous multiprocessor SoC
A Novel DAC Based Switching Power Amplifier for Polar Transmitter
Cryogenic CMOS for Qubit Control and Readout
Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS
Physical processes of phase noise in differential LC oscillators
Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters
A 13b 2GS/s Time-Domain Pipelined ADC with Split-CDAC Ping-Pong Residue Transfer and PVT-Robust Self-Tracked Time Amplifier
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals
A 16 Gb/s four-wire CDMA-based high speed I/O link with transmitter timing adjustment
Memory circuits and technology
Low-overhead, digital offset compensated, SRAM sense amplifiers
A Lossless and Modeling Attack-Resistant Strong PUF with <4E-8 Bit Error Rate
Wireless data links for next-generation networked micro-implantables
Leveraging the strengths of female engineers in today's business environment
A 333MHz random cycle DRAM using the floating body cell
A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias
Systematic calibration of AC MOSFET model parameters including non-quasi-static effect
A study on process-compatibility in CMOS-first MEMS-last integration
A 1.2-V 2.7-mW 160MHz continuous-time delta-sigma modulator with input-feedforward structure
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
A Process and Temperature Compensated Two-Stage Ring Oscillator
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications
A supposedly clever thing i'll never do again
A 6-Transistor Ultra-Low Power CMOS Voltage Reference with 0.02%/V Line Sensitivity
High-speed contactless I/O for computing devices
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI
A Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)
SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories
Session 23 - Analog techniques
Session 22 - Noise and oscillator simulation
Technology-circuit co-design of asymmetric SRAM cells for read stability improvement
Design-for-manufacturing features in nanometer logic processes - a reverse engineering perspective
An ultra-low-power, radiation-tolerant Reed Solomon encoder for space applications
An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver
1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog
1.5 watt 622/155 Mbps single chip for full ATM-SDH/SONET physical layer in 0.5 μm BiCMOS 3.3 V
An 8-bit 150-MHz CMOS A/D converter
Compact and behavioral modeling of transistors from NVNA measurements: New flows and future trends
Circuit Optimization Using Scale Based Sensitivities
Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process
A 79.1dB-SNDR 20MHz-BW 2 nd -Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture
Deep submicron effects on data converter building blocks
Spark current in charge pump of phase lock loop
An ultra-broadband compact mm-wave butler matrix in CMOS for array-based MIMO systems
A 2.4GHz, 20dBm class-D PA with single-bit digital polar modulation in 90nm CMOS
A robust STF 6mW CT ΔΣ modulator with 76dB dynamic range and 5MHz bandwidth
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System with Level-Adaptive Duty Modulation and Offset Charge Balancing for Muscular Stimulation
Analog in-memory subthreshold deep neural network accelerator
A receiver/antenna co-design for a 1.5mJ per fix fully-integrated 10×10×6mm 3 GPS logger
Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design
A 10 GHz frequency-drift temperature compensated LC VCO with fast-settling low-noise voltage regulator in 0.13 µm CMOS
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration
A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS
A 194-238GHz Fully On-Chip Self-Referenced Frequency Stabilized Radiator for High Range Resolution Imaging
Will CMOS amplifiers ever Kick-GaAs?
Platform design approach for re-configurable network appliances
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage
Session 19 - Power management
A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery
Low power chip & system design for biomedicai applications
A robust large signal non-quasi-static MOSFET model for circuit simulation
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN
A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2 nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM
A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reduction
A 1.2 V Single Supply Hybrid Current-/Voltage-Mode Three-Way Digital Doherty PA with Built-In Large-Signal Phase Compensation Achieving Less-Than 5 ° AM-PM
Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test
An at-speed self-testable technique for the high speed domino adder
A Low Power Sub-harmonic Self-Oscillating Mixer with 16.8dB conversion loss at 310GHz in 65nm CMOS
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer
EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents
A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications
Digitally-Enhanced Phase-Locking Circuits
A 16 GΩ Input Impedance Amplifier with Flicker Noise Reduction for Neural Recording Applications
A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation
Discretization and discrimination methods for design, verification, and testing of analog/mixed-signal circuits
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design
The crazy mixed up world of silicon debug [IC validation]
Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies
Design technology co-optimization for 10 nm and beyond
Differential transmission line interconnect for high speed and low power global wiring
Amorphous silicon 7 bit digital to analog converter on PEN
A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs
Notice of Violation of IEEE Publication PrinciplesA 10.7GHz SiGe BICMOS limiting amplifier using multiple offset cancellation loops
A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm
Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling
A Packaged D-Band Transmitter with a Multifeed Lens Antenna Achieving 25.3dBm Single-Element EIRP for 2-D Scalable Arrays
Noise in passive FET mixers: a simple physical model
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes
A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter
A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications
Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology
System in package "the rebirth of SIP"
An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applications
Design-Space Exploration of Quantum Approximate Optimization Algorithm under Noise
A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from -25 to 85°C
Towards a Wearable Electronic Nose Chip
Digital Gate ICs for Driving and Sensing Power Devices to Achieve Low-Loss, Low-Noise, and Highly Reliable Power Electronic Systems
Ultra-low-power electronics for non-invasive medical monitoring
Charge-borrowing decap: A novel circuit for removal of local supply noise violations
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998
Energy-efficient architecture and enabling technology for advanced SOCs
Design and characterization of a MEMS capacitive switch for improved RF amplifier circuits
A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO
Pseudo-differential analog readout circuit for MEMS microphones performing 135dBSPL AOP and 66dBA SNR at 1Pa
A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability
A 50MHz-BW 168.8dB-FoM 2x Time-Interleaved Bandpass Noise Shaping SAR ADC Using Passive Filter
Broadband transimpedance amplifier in 0.35-μm SiGe BiCMOS technology for 10-Gb/s optical receiver analog front-end application
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading
A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C
A stand-alone integrated excitation/extraction system for analog BIST applications
A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS
The role of monolithic transmission lines in high-speed integrated circuits
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library
A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors
An Analog Low-Power Highly-Accurate Link-Adaptive Energy Storage Efficiency Maximizer for Resonant CM Wireless Power Receivers
Integrated Photonic-electronic Deep Neural Networks: from Sub-nanosecond Image Classification to PVT-tolerant Activation Functions