yusuke1997/dblp-id-title huggingface dataset:
Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware
GAMER: GPU Accelerated Maze Routing
Compiler Optimizations for QAOA
Automatically extracting structure from a logical design
Extracting Local Don't Cares for Network Optimization
Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware Accelerators
A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits
SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs
An electrical-level superposed-edge approach to statistical serial link simulation
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment
Critical technologies and methodologies for systems-on-chips (tutorial)
Fast and accurate transaction level models using result oriented modeling
Peak current reduction by simultaneous state replication and re-encoding
Forward model checking techniques oriented to buggy designs
Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper
Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting
ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity
On-chip test generation for combinational circuits by LFSR modification
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips
Runtime distribution-aware dynamic voltage scaling
Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density
Exact two-level minimization of hazard-free logic with multiple-input changes
Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules
Yield-aware hierarchical optimization of large analog integrated circuits
SAT based ATPG using fast justification and propagation in the implication graph
HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method
A Framework for Explainable, Comprehensive, and Customizable Memory-Centric Workloads
An approach for the yield enhancement of programmable gate arrays
2012 TAU power grid simulation contest: Benchmark suite and results
Coupling-aware high-level interconnect synthesis for low power
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process
On reconfiguration-oriented approximate adder design and its application
Architecture and compilation for data bandwidth improvement in configurable embedded processors
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping
SMTSampler: efficient stimulus generation from complex SMT constraints
MAPS: multi-algorithm parallel circuit simulation
Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices
A coordinated synchronous and asynchronous parallel routing approach for FPGAs
EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing
FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databases
Invited Paper: Multi-Agent Generative Synthesis for Analog/RF Circuit: from Scalable Topology Generation to Efficient Inverse Design
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Expanding the frequency range of AWE via time shifting
Formal verification of distributed dynamic thermal management
A Graph-Based Deep Reinforcement Learning Framework for Quantum Circuit Mapping with Look-Ahead Rewards and Biased Exploration
Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search
2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect
Automating the diagnosis and the rectification of design errors with PRIAM
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
Regularity Driven Logic Synthesis
CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic Computing
The Power of Graph Signal Processing for Chip Placement Acceleration
Embedded software verification: challenges and solutions
Fast thermal simulation for architecture level dynamic thermal management
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON
Process variation aware performance modeling and dynamic power management for multi-core systems
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001
Automatic translation of behavioral testbench for fully accelerated simulation
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
An O(n log n) algorithm for 1-D tile compaction
Scalable, high-quality, SAT-based multi-layer escape routing
Code Transformations Based on Speculative SDC Scheduling
Exact diagnosis using boolean satisfiability
An object-oriented cell library manager
Automatic gate-level synthesis of speed-independent circuits
A new efficient approach to statistical delay modeling of CMOS digital combinational circuits
Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging
Statistical estimation of sequential circuit activity
A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations
Exact Zero Skew
On adaptive diagnostic test generation
Interval-valued statistical modeling of oxide chemical-mechanical polishing
Extraction and LVS for mixed-domain integrated MEMS layouts
Considering Decoherence Errors in the Simulation of Quantum Circuits Using Decision Diagrams
Optimal latch mapping and retiming within a tree
GREMA: Graph reduction based efficient mask assignment for double patterning technology
Efficient partitioning and analysis of digital CMOS-circuits
Scalable segmentation-based malicious circuitry detection and diagnosis
Equivalent Waveform Propagation for Static Timing Analysis
A logic simulation engine based on a modified data flow architecture
Trace driven logic synthesis - application to power minimization
Security Closure of Physical Layouts ICCAD Special Session Paper
A new method for multiparameter robust stability distribution analysis of linear analog circuits
A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation
A high-performance triple patterning layout decomposer with balanced density
Through-silicon-via management during 3D physical design: When to add and how many?
DATC RDF: Robust design flow database: Invited paper
Agent-based distributed power management for kilo-core processors
Word level feature discovery to enhance quality of assertion mining
Leveraging value locality for efficient design of a hybrid cache in multicore processors
A Novel Macro Placement Approach based on Simulated Evolution Algorithm
Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs
Test Generation using Reinforcement Learning for Delay-based Side-Channel Analysis
Dataflow Accelerator Architecture for Autonomous Machine Computing
A linear-time Steiner tree routing algorithm for terminals on the boundary of a rectangle
Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks
EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs
Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube
An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic Gates
Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs
Testing of analog systems using behavioral models and optimal experimental design techniques
Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers
Approximate reachability don't cares for CTL model checking
Leveraging GPU for Better Detailed Placement Quality
PSOFuzz: Fuzzing Processors with Particle Swarm Optimization
SIGMA: a simulator for segment delay faults
SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprinting
HAM-a hardware accelerator for multi-layer wire routing
Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition
Optimization of critical paths in circuits with level-sensitive latches
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
Hybrid state machine model for fast model predictive control: Application to path tracking
JitFilt: Mitigate Jitter-based Side Channel Analysis Attacks
Frequency-centric resonant rotary clock distribution network design
Early P/G grid voltage integrity verification
An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling
ILP Models for the Synthesis of Asynchronous Control Circuits
The impact of device parameter variations on the frequency and performance of VLSI chips
GraPhSyM: Graph Physical Synthesis Model
EI-MOR: A Hybrid Exponential Integrator and Model Order Reduction Approach for Transient Power/Ground Network Analysis
Combining technology mapping and placement for delay-optimization in FPGA designs
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
OWARU: free space-aware timing-driven incremental placement
Scheduling and hardware sharing in pipelined data paths
Delay optimization using SOP balancing
QLMOR: A new projection-based approach for nonlinear model order reduction
Automatic layout generation for CMOS operational amplifiers
Optimal non-uniform wire-sizing under the Elmore delay model
InstantGR: Scalable GPU Parallelization for Global Routing
Bayesian-Informed Hyperdimensional Learning for Intelligent and Efficient Data Processing
Logic verification using binary decision diagrams in a logic synthesis environment
Provably complete hardware Trojan detection using test point insertion
Observability Don't Care Sets and Boolean Relations
On bounding the delay of a critical path
A code refinement methodology for performance-improved synthesis from C
Three-Dimensional Routing for Multilayer Ceramic Printed Circuit Boards
Symbolic pointer analysis
Binding, Allocation and Floorplanning in Low Power High-Level Synthesis
Taming irregular EDA applications on GPUs
Sensitivity analysis for oscillators
Efficient Pole Zero Sensitivity Calculation in AWE
Extraction of Functional Information from Combinatorial Circuits
Perfect-balance planar clock routing with minimal path-length
TACO: temperature aware clock-tree optimization
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options
Synthesis of multiplier-less FIR filters with minimum number of additions
Mixed-signal simulation challenges and solutions
DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs
SATORI - A Fast Sequential SAT Engine for Circuits
A fast, accurate, and non-statistical method for fault coverage estimation
Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow
Towards Timing-Driven Routing: An Efficient Learning Based Geometric Approach
A novel methodology for statistical parameter extraction
Parallel polygon operations using loosely coupled workstations
Data Path Construction and Refinement
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Synthesis of an efficient controlling structure for post-silicon clock skew minimization
Network and system level security in connected vehicle applications
Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs
The art of semi-formal bug hunting
Efficient and accurate transient simulation in charge-voltage plane
More Moore: foolish, feasible, or fundamentally different?
Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-Equipped FPGAs for GNNs
NRG: global and detailed placement
Relaxation-based harmonic balance technique for semiconductor device simulation
Hardware synthesis from guarded atomic actions with performance specifications
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
A net-oriented method for realistic fault analysis
Pseudo-functional testing for small delay defects considering power supply noise effects
Low power logic synthesis for XOR based circuits
Synthesis of concurrent system interface modules with automatic protocol conversion generation
Impulse sensitivity function analysis of periodic circuits
iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing
A general consistency technique for increasing the controllability of high level synthesis tools
Fast FPGA emulation of analog dynamics in digitally-driven systems
Optimal replication for min-cut partitioning
A predictive system shutdown method for energy saving of event-driven computation
A frequency-domain technique for statistical timing analysis of clock meshes
Systematic Use of Random Self-Reducibility in Cryptographic Code against Physical Attacks
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion
Conflict driven learning in a quantified Boolean Satisfiability solver
MARCA: Mamba Accelerator with Reconfigurable Architecture
Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper)
An Algorithm for Rule-based Layout Pattern Matching
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
Transform domain techniques for efficient extraction of substrate parasitics
Real-time Thermal Map Estimation for AMD Multi-Core CPUs Using Transformer
Generation and use of statistical timing macro-models considering slew and load variability
Failure prediction based on anomaly detection for complex core routers
ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering
Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic
Non-tree routing for reliability and yield improvement
Timing analysis with known false sub graphs
Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems
Register assignment through resource classification for ASIP microcode generation
FPGA simulation engine for customized construction of neural microcircuits
The role of EDA in digital print automation and infrastructure optimization
Minimum area retiming with equivalent initial states
Invited Paper: LLM-Enhanced GPU-Optimized Physical Design at Scale
Identification of unsettable flip-flops for partial scan and faster ATPG
Behavioral synthesis for testability
Neural networks designing neural networks: multi-objective hyper-parameter optimization
Aging-aware logic synthesis
Place and route for massively parallel hardware-accelerated functional verification
Hardware-aware machine learning: modeling and optimization
Automated Runtime-Aware Scheduling for Multi-Tenant DNN Inference on GPU
A New Approach to Solving False Path Problem in Timing Analysis
Embedded tutorial: formal equivalence checking between system-level models and RTL
A general approach for regularity extraction in datapath circuits
Accelerated waveform methods for parallel transient simulation of semiconductor devices
A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping Checker
Multi-Million Gate FPGA Physical Design Challenges
An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation
A performance-driven layer assignment algorithm for multiple interconnect trees
Multilevel expansion-based VLSI placement with blockages
Early planning for clock skew scheduling during register binding
Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders
Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998
Iterative algorithms for formal verification of embedded real-time systems
Optimal synthesis of multichip architectures
Efficient Performance Estimation for General Real-Time Task Systems
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis
Simultaneous driver and wire sizing for performance and power optimization
Time domain analysis of nonuniform frequency dependent high-speed interconnects
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods
Real time anomaly detection in wide area monitoring of smart grids
Encoding multi-valued functions for symmetry
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper
From Inverse Design to Implementation of Practical Photonics
On Reducing the Execution Latency of Superconducting Quantum Processors via Quantum Job Scheduling
A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration
Safety model checking with complementary approximations
Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip
HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA
Estimation and bounding of energy consumption in burst-mode control circuits
Extracting RTL models from transistor netlists
PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision Quantization
FCN-engine: accelerating deconvolutional layers in classic CNN processors
Skew sensitivity minimization of buffered clock tree
Interchangeable pin routing with application to package layout
Portable parallel logic and fault simulation
Simultaneous Gate Sizing and Fanout Optimization
SemiHD: Semi-Supervised Learning Using Hyperdimensional Computing
ISO 26262-Aligned Functional Safety Verification Framework with Explainable Graph Neural Network
Aliasing probability of non-exhaustive randomized syndrome tests
2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting
An Algorithm for Simultaneous Pin Assignment and Routing
ACOR: On the Design of Energy-Efficient Autocorrelation for Emerging Edge Applications
Amplification of Ultrawideband Signals
A deductive technique for diagnosis of bridging faults
An Enhanced Multilevel Algorithm for Circuit Placement
Automatic High Level Syntesis of Partitioned Busses
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees
Effective and Efficient Qubit Mapper
SAT based solutions for consistency problems in formal property specifications for open systems
Rerec: In-ReRAM Acceleration with Access-Aware Mapping for Personalized Recommendation
Merging multiple FSM controllers for DFT/BIST hardware
Invited Paper: Hyperdimensional Computing for Resilient Edge Learning
Massively parallel programming models used as hardware description languages: The OpenCL case
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits
An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition
EI-TR: A Versatile Exponential Integrator Framework for Transient Analysis of Generic Nonlinear Circuits
ACG-Engine: An Inference Accelerator for Content Generative Neural Networks
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning
STAVES: Speedy Tensor-Aided Volterra-Based Electronic Simulator
Routability-driven analytical placement for mixed-size circuit designs
Compiler-directed voltage scaling on communication links for reducing power consumption
Multi-terminal routing with length-matching for rapid single flux quantum circuits
Online message delay prediction for model predictive control over controller area network
A framework for double patterning-enabled design
SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits
Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Predicting the Performance of Synchronous Discrete Event Simulation Systems
Hardware protection and authentication through netlist level obfuscation
MoE-OPU: An FPGA Overlay Processor Leveraging Expert Parallelism for MoE-based Large Language Models
A flash-based digital circuit design flow
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults
Deterministic random walk preconditioning for power grid analysis
2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop
Adaptive Graph Learning for Efficient Thermal Analysis of Multi-Stacking Chiplet Systems under Interface Variations
RONet: Scaling GPU System with Silicon Photonic Chiplet
Machine learning IP protection
AxHLS: Design Space Exploration and High-Level Synthesis of Approximate Accelerators using Approximate Functional Units and Analytical Models
Game-theoretic timing analysis
A delay metric for RC circuits based on the Weibull distribution
Accurate net models for placement improvement by network flow methods
Schematic-based lumped parameterized behavioral modeling for suspended MEMS
Simulation-Guided Parameter Synthesis for Chance-Constrained Optimization of Control Systems
Exploring eFPGA-based Redaction for IP Protection
Static timing analysis for self resetting circuits
Waterfall is too slow, let's go Agile: multi-domain coupling for synthesizing automotive cyber-physical systems
Security: the dark side of approximate computing?
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection
Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams
Hierarchical Interconnect Circuit Models
EDA for Autonomous Behavior Assurance
Universal logic gate for FPGA design
LiteHAX: lightweight hardware-assisted attestation of program execution
Improving Memory Energy Using Access Pattern Classification
Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs
Array Composition and Decomposition for Optimizing Embedded Applications
ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions
Clock-aware placement for large-scale heterogeneous FPGAs
Learn-on-the-go: Autonomous cross-subject context learning for internet-of-things applications
An efficient method for terminal reduction of interconnect circuits considering delay variations
Proposal of a timing model for CMOS logic gates driving a CRC load
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Synthesis of Operation-Centric Hardware Descriptions
Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems
Defense in the Reverse Fragment: RL-Based Partial Netlist Hardware Trojan Detection
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration
State assignment for initializable synthesis (gate level analysis)
Analog circuit sizing based on formal methods using affine arithmetic
Layout decomposition with pairwise coloring for multiple patterning lithography
Overview of 2022 CAD Contest at ICCAD
Test generation for path delay faults based on learning
FPD - An Environment for Exact Timing Analysis