yusuke1997/dblp-id-title huggingface dataset:
Effects of process and environmental variations on timing characteristics of clocked registers
A new physical routing approach for robust bundled signaling on NoC links
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices
TFET-based Operational Transconductance Amplifier Design for CNN Systems
A switchable PLL frequency synthesizer and hot carrier effects
Efficient Test Application for Rapid Multi-Temperature Testing
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
Optimization objectives and models of variation for statistical gate sizing
A device-level placement with multi-directional convex clustering
A reconfigurable stochastic architecture for highly reliable computing
Transductive Spiking Graph Neural Networks for Loihi
A compact delay model for series-connected MOSFETs
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025 - 2 July 2025
A prototype chipset for a large scaleable ATM switching node
On-die sensors for measuring process and environmental variations in integrated circuits
Optically leviting dielectrics in the quantum regime
Circuit Synthesis based on Hierarchical Conditional Diffusion
Clockless Spin-based Look-Up Tables with Wide Read Margin
Accurate Fault Detection for Wavelength-Routed Optical Networks-on-Chip Under Thermal Variation
An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset
On Jailbreaking Quantized Language Models Through Fault Injection Attacks
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis
IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning
Identifying High-Level Components in Combinational Circuits
A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networks
Evaluation of FPGA routing architectures under process variation
A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees
SFP: Smart File-Aware Prefetching for Flash based Storage Systems
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
New 4T-based DRAM cell designs
Design and Evaluation of Finite Field Multipliers Using Fast XNOR Cells
Physical unclonable function and true random number generator: a compact and scalable implementation
An EFSM-based approach for functional ATPG
A poly to active region VLSI mask alignment test structure
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002
Create, then innovate
DiffDock-FPGA: A Hardware Accelerator for Molecular Docking with Customized Tensor Product Framework and Sparse-Aware Access Strategy
Mixed-Signal POp/J Computing with Nonvolatile Memories
Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional Computing
Post-Quantum Cryptography on FPGAs: The Niederreiter Cryptosystem: Extended Abstract
Variability modeling and variability-aware design in deep submicron integrated circuits
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool
On the Functions Realized by Stochastic Computing Circuits
Multiple Attempt Write Strategy for Low Energy STT-RAM
Quantitative Modeling of Thermo-Optic Effects in Optical Networks-on-Chip
Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators
RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design
Viewing direction-aware backlight scaling
Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition
He-P2012: architectural heterogeneity exploration on a scalable many-core platform
6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA
Dynamic reconfiguration approach for high speed turbo decoding using circular rings
Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints
A novel power-gating scheme utilizing data retentiveness on caches
A hybrid adiabatic content addressable memory for ultra low-power applications
An analytical approach to placement legalization
Interface constrained processor specification and scheduling
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology
Power macromodeling of global interconnects considering practical repeater insertion
Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference
MuDBN: An Energy-Efficient and High-Performance Multi-FPGA Accelerator for Deep Belief Networks
A New Aging Sensor for the Detection of Recycled ICs
The Evolution of Transient-Execution Attacks
Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration
Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units
Regression-Based Macromodeling for Delay Estimation of Behavioral Components
Design of a cell library for asynchronous microengines
The effect of design parameters on single-event upset sensitivity of MOS current mode logic
A new hardware architecture for performing the gridding of DNA microarray images
ATC: Approximate Temporal Coding for Efficient Implementations of Spiking Neural Networks
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation
Socially-Distant Hands-On Labs for a Real-time Digital Signal Processing Course
Proposal of Data-Driven Processor Architecture Qv-K1
A New Heuristic Algorithm for Estimating Signal and Detection Probabilities
IM3A: Boosting Deep Neural Network Efficiency via In-Memory Addressing-Assisted Acceleration
An Electromigration-Aware Wire Sizing Methodology via Particle Swarm Optimization
Gating internal nodes to reduce power during scan shift
The parallel complexity of minimizing column conflicts
Cognitive Data-Centric Systems
Behavioral-level partitioning for low power design in control-dominated application
Scalable identification of threshold logic functions
AEAS - Towards High Energy-efficiency Design for OpenSSL Encryption Acceleration through HW/SW Co-design
Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability
Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023
Redundant wire insertion for yield improvement
Simultaneous reduction in test data volume and test time for TRC-reseeding
Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection
Hardware interface design for real time embedded systems
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures
Issues in the Design of Domino Logic Circuits
Symbolic traversals of data paths with auxiliary variables
Design Automation for Paper Microfluidics with Passive Flow Substrates
Nanometer-scale standard cell library for enhanced redundant via1 insertion rate
A study of tighter lower bounds in LP relaxation based placement
Lightweight runtime control flow analysis for adaptive loop caching
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
Secure Model Checkers for Network-on-Chip (NoC) Architectures
A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems
Collaborative voltage scaling with online STA and variable-latency datapath
Design of a 54-bit adder using a modified Manchester carry chain
Translation validation of scheduling in high level synthesis
Load Balanced On-Chip Power Delivery for Average Current Demand
Who are the alternative wires in your neighborhood? (alternative wires identification without search)
Circuit/architecture for low-power high-performance 32-bit adder
TURBONFS: turbo nand flash search
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
Custom memory architecture for multi-core implementation of face detection algorithm
Boolean Domain Attack on Corrupt and Correct Based Logic Locking Techniques
DyFORA: Dynamic Firmware Obfuscation and Remote Attestation using Hardware Signatures
Alleviating NBTI-induced failure in off-chip output drivers
Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers
Specification and synthesis of bounded indirection
An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating
CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators
Efficient Exploration in Edge-Friendly Hyperdimensional Reinforcement Learning
A study on the use of parallel wiring techniques for sub-20nm designs
SOFTONIC: A Photonic Design Approach to Softmax Activation for High-Speed Fully Analog AI Acceleration
A high performance CMOS direct down conversion mixer for UWB system
Towards Self-Supervised Learning of ECG Signal Representation for the Classification of Acute Stress Types
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design
Advanced Low Power Spintronic Memories beyond STT-MRAM
Clustered Table-Based Macromodels for RTL Power Estimation
Block alignment in 3D floorplan using layered TCG
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
A low leakage 9t sram cell for ultra-low power operation
EBASA: Error Balanced Approximate Systolic Array Architecture Design
Phase-based Cache Locking for Embedded Systems
RL-Ripper: : A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques
Minimizing peak power in synchronous logic circuits
HSCONN: Hardware-Software Co-Optimization of Self-Attention Neural Networks for Large Language Models
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis
A Simplified Arm Processor for VLSI Education
No-Race Charge-Recycling Differential Logic (NCDL)
Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware
A VLSI High-Performance Encoder with Priority Lookahead
Bus-pin-aware bus-driven floorplanning
HW/SW co-verification of embedded systems using bounded model checking
Thermal-aware floorplanning exploration for 3D multi-core architectures
Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric
Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL
A potential-driven approach to constructing rectilinear Steiner trees
Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank
A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge Nodes
Computing Polynomials with Positive Coefficients using Stochastic Logic by Double-NAND Expansion
A tool flow for predicting system level timing failures due to interconnect reliability degradation
Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits
TOIC: Timing Obfuscated Integrated Circuits
Exploring Processing In-Memory for Different Technologies
Evaluation of silicon-on-sapphire enhancement JFETs for digital applications
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage
Algorithm independent data flow mapping on a unified VLSI architecture
Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking
Silicon Photonic Interconnects: Minimizing the Controller Latency
An approximation algorithm for cofactoring-based synthesis
Optimal partitioning and balanced scheduling with the maximal overlap of data footprints
A CMOS elliptic low-pass switched capacitor ladder filter for video communication using bilinear implementation
Improving Circuit Testability by Clock Control
Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages
Accounting for the skin effect during repeater insertion
Out-of-order issue logic using sorting networks
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching
Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, Kalamazoo, MI, USA, March 5-6, 1993
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology
Computational Thinking Meets Design Thinking: Technology and Arts Collaborations
Scaling of serially-connected MOSFET chains
Security Enhancements for Approximate Machine Learning
9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA
Radiation Hardening by Design Techniques for the Mutual Exclusion Element
Leveraging All-Spin Logic to Improve Hardware Security
Energy Efficient RRAM Spiking Neural Network for Real Time Classification
Comprehensive Analysis of Consistency and Robustness of Machine Learning Models in Malware Detection
Optimizing wiring space in slicing floorplans
Avoiding Malicious Nodes of a 3-D NoC with Security-Aware Priority-Based Routing
A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs
A 1.27 fJ/B/transition Digital Compute-in-Memory Architecture for Non-Deterministic Finite Automata Evaluation
A scalable analog architecture for neural networks with on-chip learning and refreshing
Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology
A custom FPGA for the simulation of gene regulatory networks
Locally clocked microprocessor
Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C Integrators
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
Modeling and Benchmarking Computing-in-Memory for Design Space Exploration
Priority driven channel pin assignment
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS
Breaking the power delivery wall using voltage stacking
Sleep transistor distribution in row-based MTCMOS designs
Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example
An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS
Real-Time and Robust Hyperdimensional Classification
Technology independent arbitrary device extractor
Multi-Parameter Comparative Study of Selective In-Memory Computing Processor Architectures for Performance Optimization in Accelerated Edge Computing
Fingerprinting Quantum Computer Equipment
A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip
Online convex optimization-based algorithm for thermal management of MPSoCs
Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU
Improving Block Management in 3D NAND Flash SSDs with Sub-Block First Write Sequencing
A 0.13 µm CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivity
Macromodeling C- and RC-loaded CMOS inverters for timing analysis
Is It Approximate Computing or Malicious Computing?
Efficient characterization of TSV-to-transistor noise coupling in 3D ICs
Pseudo-Exhaustive Testing of Sequential Circuits
Analyzing and verifying locally clocked circuits with the concurrency workbench
Hand-in-hand verification of high-level synthesis
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor
HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving Applications
Implementation of fault-tolerant sequential circuits using programmable logic arrays
A Design Exploration Environment
A low power direct digital frequency synthesizer with 60 dBc spectral purity
On the automatic synthesis of parallel SW from RTL models of hardware IPs
A layout-aware physical design method for constructing feasible QCA circuits
A new technique for estimating lower bounds on latency for high level synthesis
A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation
Reducing T-Depth and T-Count in Quantum Multiplication Using Compressor Primitives
CESC: a visual formalism for specification and verification of SoCs
Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems
LFSR-based BIST for analog circuits using slope detection
Reliability Analysis of Memristive Reservoir Computing Architecture
Generation of color-constrained spanning trees with application in symbolic circuit analysis
A New Silicon-aware Big Data SoC Timing Analysis Solution: A Case Study of Empyrean University Program
Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits
A Light-Speed Large Language Model Accelerator with Optical Stochastic Computing
Modular Security Evaluation Platform for Physiological Closed-Loop Control Systems
Quantum devices and optical computing: introduction
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory
Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence
An Efficient Maze Routing Algorithm for Fast Global Routing
Proceedings of the Second Great Lakes Symposium on VLSI, Kalamazoo, MI, USA, February 28-29, 1992
An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs
A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments
Synchronization scheme for brick-based rotary oscillator arrays
Design methodology for semi custom processor cores
PREFACE - A Reinforcement Learning Framework for Code Verification via LLM Prompt Repair
GLSVLSI 2008 invited/keynote talk
Energy-Efficient Scheduling for Cattle Collars An Optimized Approach Based on Analytic Hierarchy Process and Preemption Threshold
Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration
Impact of Aging on Template Attacks
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines
Practical slicing and non-slicing block-packing without simulated annealing
How to reduce aliasing in linear analog testing
An Industrial Perspective on ML-Macro Placement Methods: Challenges and Recommendations
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
Using unsatisfiable cores to debug multiple design errors
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V
PrGEMM: A Parallel Reduction SpGEMM Accelerator
A low-power phase change memory based hybrid cache architecture
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system
A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator
Robust Reasoning and Learning with Brain-Inspired Representations under Hardware-Induced Nonlinearities
NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures
Hardware/software partitioning with multi-version implementation exploration
A design flow for physical synthesis of digital cells with ASTRAN
Energy management in software-controlled multi-level memory hierarchies
A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature
ParallelNTT: Maximizing Performance of Forward and Inverse NTT on FPGA for ML-DSA and ML-KEM
Exploiting Disturbance-Aware Read Redirection for Performance Improvement in 3D Flash Memory
Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths
TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator
Transition count testing of CMOS combinational circuits
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN
A Thermal-Balanced Variable-Sized-Bin-Packing Approach for Energy Efficient Multi-Core Real-Time Scheduling
Design of a 5-Gb/s PRBS generator in 0.18µm CMOS process
A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications
Automating the packaging selection of VLSI systems
P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration
Interconnect delay minimization through interlayer via placement in 3-D ICs
NBTI effects on tree-like clock distribution networks
Hardware trojan attacks in FPGA devices: threat analysis and effective counter measures
Incremental buffer insertion and module resizing algorithm using geometric programming
A System Design Methodology for Telecommunication Network Applications
Design Automation for Biological Models: A Pipeline that Incorporates Spatial and Molecular Complexity
A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits
A task-oriented vision system
Deep Learning Processors for On-Device Intelligence
Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain
Scheduling conditional data-flow graphs with resource sharing
Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM
On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core Assignment
Smart nodes of internet of things (IoT): a hardware perspective view & implementation
Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
SCRAMBLE-CFI: Mitigating Fault-Induced Control-Flow Attacks on OpenTitan
From Prompt to Accelerator: A Perspective on LLM-Based Analog In-Memory Accelerator Design Automation
A new approach to the use of satisfiability in false path detection
Security Threats in Approximate Computing Systems
A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition
A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications
Power efficient partial product compression
Session details: Session 5A: Hardware Security
On Optimizing Test Strategies for Analog Cells
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance
LightBench: A Hardware-Aware Trusted Execution Platform for Intelligent Malware Detection at the Edge
VLSUMaP: A High-Performance Matrix Processor with Virtually Expanded LSU Boosting HBM Bandwidth Utilization
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge
MARS: MAximizing throughput for MPPT-based self-sustaining LoRa Systems
Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing
Candidate subcircuits for functional module identification in logic circuits
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
Low power 3-D stacking multimedia platform with reconfigurable memory architecture
On Verifying the Correctness of Retimed Circuits
Routing non-convex grids without holes
Session details: Session 7A: Special Session - 3: Machine Learning-Aided Computer-Aided Design