yusuke1997/dblp-id-title huggingface dataset:
Timely data delivery in sensor networks using whirlpool
Processing nested complex sequence pattern queries over event streams
Towards energy efficient XPath evaluation in wireless sensor networks
SenseSwarm: a perimeter-based data acquisition framework for mobile sensor networks
Stream-based macro-programming of wireless sensor, actuator network applications with SOSNA
Future directions in sensor data management: a panel discussion
PAO: power-efficient attribution of outliers in wireless sensor networks
Adaptive random sensor selection for field reconstruction in wireless sensor networks
DEMS: a data mining based technique to handle missing data in mobile sensor network applications
Region streams: functional macroprogramming for sensor networks
Workflow support for wireless sensor and actor networks: a position paper
Extracting tennis statistics from wireless sensing environments
The threshold join algorithm for top-k queries in distributed sensor networks
Similarity-aware query allocation in sensor networks with multiple base stations
A multi-banked shared-l1 cache architecture for tightly coupled processor clusters
On the credibility of load-latency measurement of network-on-chips
Exploring instruction caching strategies for tightly-coupled shared-memory clusters
Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip
2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010
Implementing a single-processor cellular modem on an SC1000-family core
Synchronizing distributed state machines in a coarse grain reconfigurable architecture
An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS
PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication
SOC logic development using configurable, application-specific processors
Lessons learned from designing the MONTIUM - a coarse-grained reconfigurable processing tile
Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004
Implementation and evaluation of configuration scrubbing on CGRAs: A case study
Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs
Exploring Application-Level Concurrency in SoC Design
Keyed logic BIST for Trojan detection in SoC
Yield-oriented evaluation methodology of network-on-chip routing implementations
Design of a guaranteed throughput router for on-chip networks
Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses
A programmable platform for software-defined radio
Scheduling framework for real-time dependable NoC-based systems
Heap access optimizations for a hardware-accelerated Java virtual machine
Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression
A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects
A guaranteed-throughput switch for network-on-chip
Configuring Smart Objects over cognitive radio
Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms
Efficient distributed memory management in a multi-core H.264 decoder on FPGA
Efficient barrier synchronization mechanism for emulated shared memory NOCs
Evaluation of platform architecture performance using abstract instruction-level workload models
Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores
A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs
The Impact of Communication on the Scalability of the Data-parallel Video Encoder on MPSoC
A system level power consumption estimation for MPSoC
Reconfigurable Fabric Interconnects
Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips
System-level Modeling of Wireless Integrated Sensor Networks
A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs
Co-designs of parallel Rijndael
Application-aware spinlock control using a hardware scheduler in MPSoC platforms
Performance modeling of parallel applications on MPSoCs
Thermal/performance trade-off in network-on-chip architectures
Assertion based verification of PSL for SystemC designs
Crosstalk immune interconnect driver design
Resource-shared custom instruction generation under performance/area constraints
TLMCO-simulation for an open source MPSOC platform under STARSoC environment
On the performance of 3GPP LTE baseband using SB3500
Development of NSoC program in Taiwan
Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures
Program image dissemination protocol for low-energy multihop wireless sensor networks
SOPC Builder, a Novel Design Methodology for IP Integration
Abstract RTOS modeling for multiprocessor system-on-chip
Practical distributed simulation of a network of wireless terminals
Topology design for global link optimization in application specific network-on-chips
Reduce SOC Energy Consumption through Processor ISA Extension
Gamification of System-on-Chip design
Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array
A New Look at Reversible Logic Implementation of Decimal Adder
Performance analysis of multi-channel memories in mobile devices
Sensor Network-On-Chip
Towards a Formal Power Estimation Framework for Hardware Systems
Network-on-Chip: A New Paradigm for System-on-Chip Design
Global routing for multicast-supporting TDM network-on-chip
Evaluation of fully-integrated switching regulators for CMOS process technologies
Ultra-low latency NoC testing via pseudo-random test pattern compaction
Using a communication generator in SoC architecture exploration
Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis
Control and datapath decoupling in the design of a NoC switch: area, power and performance implications
A driver load model for capacitive coupled on-chip interconnect buses
Exploiting the Area X Performance Trade-off with Code Compression
Structural Verification in Minimal Time
Programmability in Dictionary-Based Compression
Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN
An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core
Practical Assertion-based Formal Verification for SoC Designs
Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM
Low noise amplifier architecture analysis for UWB system
A FPGA Implementation of An Open-Source Floating-Point Computation System
Instrumentation-driven model detection for dataflow graphs
Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration
Formal Modelling of Synchronous Hardware Components for System-on-Chip
Evaluating application mapping using network simulation
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view
Lookback BiST for RF front-ends in digital transceivers
A checkpoint/restore framework for systemc-based virtual platforms
Correct and energy-efficient design of SoCs: The H.264 encoder case study
Hardware Cost Analysis for Weakly Programmable Processor Arrays
Overview of the 4S Project
Implementation of an HSDPA Receiver with a Customized Vector Processor
Mapping streaming applications on a reconfigurable MPSoC platform at run-time
Multi-Objective Genetic optimized multiprocessor SoC design
A fully integrated low-IF DVB-T receiver architecture
A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation
An efficient software cache for H.264 motion compensation
The Future of Nanometer SOC Design
System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems
Ec - a compiler for the e-language [NOC applications]
High speed and low power on-chip micro network circuit with differential transmission line
SW and HW speculative Nelder-Mead execution for high performance unconstrained optimization
Soft-core eFPGA for Smart Power applications
Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications
Mapping of the FFT on a reconfigurable architecture targeted to SDR applications
A multi-core signal processor for heterogeneous reconfigurable computing
The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology
A message-level monitoring protocol for QoS flows in NoCs
FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler
Homogeneous MPSoC as baseband signal processing engine for OFDM systems
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates
Clock generation and distribution in high-performance processors
A scalable embedded DSP core for SoC applications
Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell Search
Physical realization oriented area-power-delay tradeoff exploration
Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip
Configurable Hardware/Software Support for Single Processor Real-Time Kernels
Evaluation of current QoS Mechanisms in Networks on Chip
Realizing Multioperations for Step Cached MP-SOCs
Rapid Refinable SoC SDR Design
Comparison of hardware IP components for system-on-chip
Characterising embedded applications using a UML profile
Effects of loop unrolling and use of instruction buffer on processor energy consumption
OpenCL implementation of Cholesky matrix decomposition
Modeling And Performance Analysis of GALS architectures
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs
Exploitation of UML 2.0 - Based Platform Service Model and SystemC Workload Simulation in MPEG-4 Partitioning
Dynamic Verification of OCP-based SoC
A cycle accurate simulation framework for asynchronous NoC design
Parameterized decompression hardware for a program memory compression system
A double data rate 8T-cell SRAM architecture for systems-on-chip
2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013
Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC
Complexity analysis of spatially scalable MPEG-4 encoder
FPGA Prototype of the REALJava Co-Processor
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs
A hybrid model of speculative execution and scout threading for auto-memoization processor
A 65nm CMOS down-sampling micromixer with enhanced DC current capability
Development and Verification of Embedded Firmware using Virtual System Prototypes
Rendezvous-based MoC for untimed TLM
Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs
VLIW operation refinement for reducing energy consumption
Real-time execution monitoring on multi-processor system-on-chip
A flexible platform architecture for Gbps wireless communication
Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization
Using SPIRIT Cores in SonicsStudio
AMBA based multiprocessor system
Proof of Concept for Low-power Digital Asynchronous IC Design
Dataflow-based reconfigurable architecture for streaming applications
Run-time Mapping of Applications to a Heterogeneous SoC
Multilevel MPSoC Performance Evaluation Using MDE Approach
Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture
Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections
Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time Ratio
A code compression scheme for improving SoC performance
Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer
Scalability analysis of release and sequential consistency models in NoC based multicore systems
Minimising Dynamic Power Consumption in On-Chip Networks
A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations
Hybrid on-chip clocking for sensor nodes
Analyzing transport and MAC layer in system-level performance simulation
Stream architectures - efficiency and programmability
RF transmitter architecture investigation for power efficient mobile WiMAX applications
Comparison of analog transactions using statistics
A Configuration Locking Technique to Reduce the Configuration Overhead of Run-Time Reconfigurable Devices
Implementing the conjugate gradient algorithm on multi-core systems
Reusable XGFT interconnect IP for network-on-chip implementations
CRAVE: An advanced constrained random verification environment for SystemC
Enhanced legacy 68000 instruction set architecture as a basis for system on chip development
Automatic calibration of streaming applications for software mapping exploration
A family of modular area- and energy-efficient QRD-accelerator architectures
From Y-chart to seamless integration of application design and performance simulation
Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms
On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs
Congestion-aware task mapping in heterogeneous MPSoCs
H.264/AVC framework for multi-core embedded video encoders
Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systems
MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip
Moonrake chip - GALS demonstrator in 40 nm CMOS technology
Reconfigurable IP blocks: a survey [SoC]
TNODE: A low power sensor node processor for secure wireless networks
Energy Model of Networks-on-Chip and a Bus
Automated instrumentation of FPGA-based systems for system-level transaction monitoring
SoC integration of programmable cores
Formal Modelling of Multiclocked SoC Systems
Energy analysis of re-injection based deadlock recovery routing algorithms
Reconfigurable Security Primitive for Embedded Systems
Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm 2 multi-standard turbo decoder
Analyses of signaling techniques for self-timed systems
Multiprocessor system and software design for distributed control applications
Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization
Design of a parametrizable low cost Ethernet MAC core for SoC solutions
Tiny application-specific programmable processor for BCH decoding
Reduction of design complexity using virtual hardware platforms
Low-Power SOC Design Using Configurable Processors-The Non-Nuclear Option
Evaluating the scalability of test buses
Useful-state encoding: Network control with minimal redundancy
Energy-aware run-time mapping for homogeneous NoC
Dataflow Transformations in High-level DSP System Design
SoC-Mobinet, R&D and education in system-on-chip design
I/O virtualization utilizing an efficient hardware system-level Memory Management Unit
Updating matrix inverse in fixed-point representation: direct versus iterative methods
Automatic generation of memory interfaces
Exploiting control management to accelerate Radix-4 FFT on a reconfigurable platform
Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs
Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip
Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips
WOKE: A novel workflow model editor
UML profile for estimating application Worst Case Execution Time on System-on-Chip
Modeling on-chip communication
An implementation of Auto-Memoization mechanism on ARM-based superscalar processor
Effects of scaling a coarse-grain reconfigurable array on power and energy consumption
Analysis of memory access optimization for motion compensation frames in MPEG-4
Mixed static/dynamic profiling for dictionary based code compression
Application Scenarios in Streaming-Oriented Embedded System Design
Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects
PowerMemo: A power profiling tool for mobile devices in an emulated wireless environment
Interconnect routing of embedded FPGAs using standard VLSI routing tools
Extending IP-XACT to embedded system HW/SW integration
Efficient Link Architecture for On-Chip Serial links and Networks
Architectural and Physical Design Optimizations for Efficient Intra-tile Communication
FPGA implementation of a 2G fibre channel link encryptor with authenticated encryption mode GCM
A delay spread based low power reconfigurable FFT processor architecture for wireless receiver
Dependency analysis and visualization tool for Kactus2 IP-XACT design framework
Multiple-objective backtrace for solving test generation constraints
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network
Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems
Comparative analysis of serial vs parallel links in NoC
Building a RTOS for MPSoC dataflow programming
Multiplierless Reconfigurable Processing Element And Its Applications to DSP Kernels
Design for verification of a PCI bus in SystemC
Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates
MCDA-based methodology for efficient 3D-design space exploration and decision
Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study
A novel SAD architecture for variable block size motion estimation in HEVC video coding
A DSP architecture optimized for wireless baseband
Instruction Folding for an Asynchronous Java Co-Processor
Reliable Asynchronous Links for SoC
Power consumption analysis and energy efficient optimization for turbo decoder implementation
A model for imaging system-on-chip manufacturing costs
High resolution flash time-to-digital converter with sub-picosecond measurement capabilities
SAMOSA: Scratchpad aware mapping of streaming applications
A reconfigurable FPU as IP component for SoCs
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip
Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications
Two phase clocked adiabatic static CMOS logic
3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus
2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011
Statistical timing characterization
A Leak Resistant SoC to Counteract Side Channel Attacks
System-level modeling and validation increase design productivity and save errors
Proceedings of the 2005 International Symposium on System-on-Chip, Tampere, Finland, November 15-17, 2005
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture
Static analysis method for deadlock detection in SystemC designs
A Novel Emulation Technique that Preserves Circuit Structure and Timing
Refinement of on-chip communication channels
Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems
Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders
Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding
Optimizing routing tables on systems-on-chip with Content-Addressable Memories
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources
A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor Architecture
Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management
Balancing wrapper chains of SoC core based on best interchange decreasing
Design reuse and design for reuse, a case study on HDSL2
moviTest: A Test Environment dedicated to multi-core embedded architectures
2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014
Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithm
Analog Television, WiMAX and DVB-H on the Same SoC Platform
Power Management and Clock Generator for a Novel Passive UWB Tag
Impact of proactive temperature management on performance of Networks-on-Chip
System architecture for 3GPP LTE modem using a programmable baseband processor
SoC Leakage Power Reduction Algorithm by Input Vector Control
System-level software performance simulation considering out-of-order processor execution
Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay
International Symposium on System-on-Chip, SoC 2007, Tampere, Finland, November 20-21, 2007
Analysis and design of level-converting flip-flops for dual-V dd /V th integrated circuits
Scheduling of parallelized synchronous dataflow actors
Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototype
Mismatch characterization of high-speed NoC links using asynchronous sub-sampling
Low-power arithmetic unit for DSP applications
Crosstalk avoidance coding for reliable data transmission of network on chips
COFFEE - a core for free
SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-Core
Immediate optimization for compressed transport triggered architecture instructions
Arithmetic processing unit for reciprocal operations
On-line dependability enhancement of multiprocessor SoCs by resource management
Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits
External Memory Controller for Virtex II Pro
System Level Design Experiences and the Need for Standardization
AVISPA: a massively parallel reconfigurable accelerator
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
FlexPath NP - A network processor architecture with flexible processing paths
A 110 dB, 3-mW fourth-order Σ-Δ modulator for atmospheric pressure sensor
Optimizing a high performance 32-bit processor for programmable logic
Customizable Datapath Integrated Lock Unit
A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II
CTL based DFT solution to accelerate design to test development for system on chip devices
Design Methodologies and CAD Tool Flows for Networks on Chips
An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control
Loop Scheduling for Transport Triggered Architecture Processors
Efficient VLSI architectures of QPP interleavers for LTE turbo decoders
Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems
A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect
A state based framework for efficient system-level power estimation of of costum reconfigurable cores
Efficient compensation of delay variations in high-speed network-on-chip data links
A low-power I-cache design with tag-comparison reuse
A flexible modeling and simulation framework for Design Space Exploration
Energy-Optimal Circuit Design
A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip
Study of adaptive detection for MIMO-OFDM systems
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs
2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008
A thermal-aware power management soft-IP for platform-based SoC designs
Flexible DOR routing for virtualization of multicore chips
A highly efficient modeling style for heterogeneous bus architectures
A system-on-a-chip for audio encoding
A system level IP integration methodology for fast SOC design
A 1V current-mode filter in 65nm CMOS using capacitance multiplication
An Effective IP Reuse Methodology for Quality System-on-Chip Design
Algorithms for Leakage Reduction with Dual Threshold Design Techniques
Efficient tile-aware bounding-box overlap test for tile-based rendering
One-chip solution in 0.35 μm standard CMOS for electronic ballasts for fluorescent lamps