yusuke1997/dblp-id-title huggingface dataset:
An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software
Instruction Prefetching Using Branch Prediction Information
Cloud computing: Virtualization and resiliency for data center computing
Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk Faults
Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters
A Case for Software-Based Adaptive Routing in NUMA Systems
CHQ-SC: Compact and High-Quality Stochastic Computing Framework Using Magnetic Tunnel Junction
FASTCHART-Idea and Implementation
Clock controller design in SuperSPARC II microprocessor
Designing Circuits for Disk Drives
Emerging Techologies for Electronic Design and Test
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers
Compiler-Based Frame Formation for Static Optimization
Astraea: Self-Balancing Federated Learning for Improving Classification Accuracy of Mobile Deep Learning Applications
Low-Power Design of 90-nm SuperH Processor Core
Interfacing Hardware and Software Using C++ Class Libraries
Sampling of Cache Congruence Classes
HOLES: Boosting Large Language Models Efficiency with Hardware-Friendly Lossless Encoding
Exploit common source-line to construct energy efficient domain wall memory based caches
ACG-Adjacent Constraint Graph for General Floorplans
A case study in low-power system-level design
Accurate modeling and fault simulation of Byzantine resistive bridges
A parallel IEEE P754 decimal floating-point multiplier
Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors
A high-performance parallel CAVLC encoder on a fine-grained many-core system
Synthesis of Controllers from Interval Temporal Logic Specification
A Low-Power Cache Design for CalmRISC TM -Based Systems
On Retiming for FPGA Logic Module Minimization
Near-memory Caching for Improved Energy Consumption
Implementing low power digital circuits using flash devices
The convergence of HPC and embedded systems in our heterogeneous computing future
Relinquishment coherence for enhancing directory efficiency in chip multiprocessors
Tips: Augment Memory Tagging to Defend Against Prefetcher Side Channels
Post Layout Speed-up by Event Elimination
Real-Time Operating Systems for Embedded Computing
An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory
WidePipe: High-Throughput Deep Learning Inference System on a Cluster of Neural Processing Units
OPAM: an efficient output phase assignment for multilevel logic minimization
A High-performance Post-deduplication Delta Compression Scheme for Packed Datasets
A radix-10 SRT divider based on alternative BCD codings
JMA: The Java-Multithreading Architecture for Embedded Processors
A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs
SHIELDSTRAP: Making secure processors truly secure
Quality Improvement Methods for System-Level Stimuli Generation
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
3D Processing Technology and Its Impact on iA32 Microprocessors
Reliability analysis of a computer system for a data collection application
On the Improvement of Statistical Static Timing Analysis
CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs
Area Efficient Synthesis of Asynchronous Interface Circuits
Improved combined binary/decimal fixed-point multipliers
A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks
Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks
Tango: Low Latency Multi-DNN Inference on Heterogeneous Edge Platforms
SHEEO: Continuous Energy Efficiency Optimization in Autonomous Embedded Systems
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement
Logic decomposition algorithms for the timing optimization of multi-level logic
Digital filter synthesis considering multiple adder graphs for a coefficient
DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube
Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency
Free-space optical crossover interconnects for parallel computers
A Heuristic for Multiple Weight Set Generation
Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization
Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic
VLSI issues in memory-system design for video signal processors
A coprocessor for accurate and reliable numerical computations
A study of reliability issues in clock distribution networks
Statistical timing analysis using Kernel smoothing
Energy-aware Standby-Sparing Technique for periodic real-time applications
OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Fault-tolerant in-memory crossbar computing using quantified constraint solving
General IDS Acceleration for High-Speed Networks
The use of random simulation in formal verification
Multiple-valued Boolean minimization based on graph coloring
Dynamic Cluster Resizing
A new verification method for embedded systems
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
Stealthy-Shutdown: Practical Remote Power Attacks in Multi - Tenant FPGAs
PACE-Lite: Compact and Efficient Piecewise Polynomial Approximation for Transformer Nonlinearity Acceleration
Testing of Analog Neural Array-Processor Chips
DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs
Fast power network analysis with multiple clock domains
Functional Illinois Scan Design at RTL
Memory-Bounded Randomness for Hardware-Constrained Encrypted Computation
PANG: A Pattern-Aware GCN Accelerator for Universal Graphs
EXIST: an interactive VLSI architectural environment
Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation
Design and Implementation of a new Synchronization Method for High-Speed Cell-based Network Interfaces
BarTLB: Barren page resistant TLB for managed runtime languages
An integrated floating point vector processor for DSP and scientific computing
High performance I/O processors for real-time pulse handling
Exploiting correlation in stochastic circuit design
Bridging The Gap: Data Exfiltration In Highly Secured Environments Using Bluetooth IoTs
Parallel digital image restoration using adaptive VLSI neural chips
Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations
Pre-assignment RDL routing via extraction of maximal net sequence
TCFlash: In-Flash Bulk Bitwise Processing via Dynamic Sensing and TLC Encoding in 3D NAND
Bayesian theory oriented Optimal Data-Provider Selection for CMP
A unified addition structure for moduli set {2 n -1, 2 n , 2 n +1} based on a novel RNS representation
Cheap Out-of-Order Execution Using Delayed Issue
Current-Mode Threshold Logic Gates
Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs
M-MAP: Multi-factor memory authentication for secure embedded processors
A power-aware hybrid RAM-CAM renaming mechanism for fast recovery
Luminescent solar concentrator-based photovoltaic reconfiguration for hybrid and plug-in electric vehicles
Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure
Using Disturbance Compensation and Data Clustering (DC)2 to Improve Reliability and Performance of 3D MLC Flash Memory
Scalable Multi-Queue Data Transfer Scheme for FPGA-Based Multi-Accelerators
A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing
Generalized Tree Architecture for Efficient Successive-Cancellation Polar Decoding
Access Frequency-Aware Storage Reduction for Deep Learning Recommendation Model
An Exact Optimization of Two-Level Acyclic Sequential Circuits
REEM: Failure/non-failure region estimation method for SRAM yield analysis
A Two-Layer Bus Routing Algorithm for High-Speed Boards
On finding undetectable and redundant faults in synchronous sequential circuits
Architectures for pipelined Wallace tree multiplier-accumulators
Security Analysis of State-of-the-art Scan Obfuscation Technique
Reliable design of multichip nonblocking crossbars
Optimal design of synchronous circuits using software pipelining techniques
Introduction to Generalized Symbolic Trajectory Evaluation
Frame Buffer Energy Optimization by Pixel Prediction
Reducing register file size through instruction pre-execution enhanced by value prediction
A position-insensitive finished store buffer
Design and Scaling of BiCMOS Circuits
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits
CTP-A family of optimizing compilers for the NS32532 microprocessor
AMULET3: A 100 MIPS Asynchronous Embedded Processor
Constraint Slving for Test Case Generation
Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors
PBCCF: Accelerated Deduplication by Prefetching Backup Content Correlated Fingerprints
Using Scratchpad to Exploit Object Locality in Java
Issues in the implementation of the i486TM cache and bus
Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.
Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic Structures
Recovering QSVT Polynomials from Side-Channel Information on Quantum Computers
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor
On improving the algorithmic robustness of a low-power FIR filter
LifetimeKV: Narrowing the Lifetime Gap of SSTs in LSMT-based KV Stores for ZNS SSDs
Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm
MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture
Memory Hierarchy Synthesis of a Multimedia Embedded Processor
Aurora: A thermally resilient photonic network-on-chip architecture
Bridging the gap between nanomagnetic devices and circuits
Memory organization for video algorithms on programmable signal processors
Low Power Adder with Adaptive Supply Voltage
Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology
System Design: Traditional Concepts and New Paradigms
Side-Channel Leakage Detection Based on Constant Parameter Channel Model
FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controller
RelHD: A Graph-based Learning on FeFET with Hyperdimensional Computing
RTLBench: A Multi-Dimensional Benchmark Suite for Evaluating LLM-Generated RTL Code
VSA: A Hybrid Vector-Systolic Architecture
Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ
The ARM9 family-high performance microprocessors for embedded applications
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults
Scheduling unequal length tests in high performance VLSI system implementations
Identification of undetectable faults in combinational circuits
Enhanced Compression Techniques to Simplify Programm Decompression and Execution
VNet: A Versatile Network for Efficient Real-Time Semantic Segmentation
Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design
Lifelong Disk Failure Prediction via GAN-Based Anomaly Detection
Design Considerations for Digital Circuit Interconnections in a Multilayer Printed Circuit Board
A Novel Low-Power Scan Design Technique Using Supply Gating
Security-Driven Codesign with Weakly-Hard Constraints for Real-Time Embedded Systems
Pica: An Ultra-Light Processor for High-Througput Applications
A Comparison of Synchronous and Asynchronous FSMD Designs
Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing
CMOS logic design with independent-gate FinFETs
Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks
FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper
A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function Evaluation
FlashDAM: Flexible I/O Throttling for the User Experience of Mobile Systems
Exploiting producer patterns and L2 cache for timely dependence-based prefetching
Fast Low-Energy VLSI Binary Addition
An area estimation technique for module generation
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation
Dynamic core scaling: Trading off performance and energy beyond DVFS
Cache design for high performance computers with BiCMOS VLSIs
Path-Delay Fault Simulation for a Standard Scan Design Methodology
Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells
Loop2Recursion: Compiler-Assisted Wear Leveling for Non-Volatile Memory
Advanced modes in AES: Are they safe from power analysis based side channel attacks?
Mid-range wireless energy transfer using inductive resonance for wireless sensors
PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks
Providing cost-effective on-chip network bandwidth in GPGPUs
First Test Results of System Level Fault Tolerant Design Validation Through Laser Fault Injection
LEA: A Lazy Eviction Algorithm for SSD Cache in Cloud Block Storage
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning
High throughput, low set-up time, reconfigurable linear Feedback Shift Registers
Analysis of ×86 instruction set usage for DOS/Windows applications and its implication on superscalar design
PriME: PIM-Aware Efficient Compression for Memory-Bound Embedding Layers in sLLMs
A system simulation environment within Digital
Automatic data path abstraction for verification of large scale designs
Energy-Aware Task Scheduling on Heterogeneous NoC-Based MPSoCs
Simulating Commercial Java Throughput Workloads: A Case Study
Impact analysis of performance faults in modern microprocessors
27th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009
ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network Accelerators
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors
Efficient provably good OPC modeling and its applications to interconnect optimization
Buffered Interconnect Tree Optimization Using Lagrangian Relaxation and Dynamic Programming
Pseudoexhaustive BIST for Sequential Circuits
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification
RFiop: RF-memory path to address on-package I/O pad and memory controller scalability
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations
An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig
Accelerating mobile augmented reality on a handheld platform
Applying speculation techniques to implement functional units
MOSQ: Accelerating Classical Simulation of UCCSD Ansatz Circuits using Merged Operation
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems
Tolerating more hard errors in MLC PCMs using compression
Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor
HiNUMA: NUMA-Aware Data Placement and Migration in Hybrid Memory Systems
Dissecting and Re-Architecting 3D NAND Flash PIM Arrays for Efficient Single-Batch Token Generation in LLMS
The Imagine Stream Processor
Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs
Adaptive Backpressure: Efficient buffer management for on-chip networks
Comparative analysis of NBTI effects on low power and high performance flip-flops
Dynamically reconfigurable soft output MIMO detector
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures
Cost-effective Hardware Acceleration of Multimedia Applications
Exploiting Microarchitectural Redundancy For Defect Tolerance
A fractal compaction algorithm for efficient power estimation
ViTframe: Vision Transformer Acceleration via Informative Frame Selection for Video Recognition
Design for Testability to Combat Delay Faults
pRnR: A Parallel Record-Replay Framework for Virtual Machines
CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks
QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models
Low write-energy STT-MRAMs using FinFET-based access transistors
Hardware support for production run diagnosis of performance bugs
FedNorm: An Efficient Federated Learning Framework with Dual Heterogeneity Coexistence on Edge Intelligence Systems
A Massively Parallel Multithreaded Architecture: DAVRID
Data cache parameter measurements
Grammar-Based Optimization of Synthesis Scenarios
A high-performance asynchronous SCSI controller
Power-Performance Characterization of TinyML Systems
Towards Quantized Stochastic Computing by Leveraging Reduced Precision Binary Numbers through Bit Truncation
The TM3270 Media-Processor Data Cache
SUSTAINPHOT: Sustainable Large-Scale AI Training Using Analog Silicon Photonic Accelerators
Formal Verification of Parametric Multiplicative Division Implementations
Optimizing ML Classification Models for Constrained EDA Resource Budgets
Fault Simulation and Test Generation by Fault Sampling Techniques
Reducing Cache Pollution of Prefetching in a Small Data Cache
Fast CRC Calculation
BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC
A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators
The impact of liquid cooling on 3D multi-core processors
Statistical Timing Optimization of Combinatorial Logic Circuits
A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications
An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum Signature
Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators
A Genetic Algorithm for Global Improvement of Macrocell Layouts
Rational clocking [digital systems design]
A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability
Post-Model Validation of Victim DRAM Caches
SchInFS: A File System Integrating Functions of the Block I/O Scheduler for ZNS SSDs
An 80 MFLOPS floating-point engine in the Intel i860(TM) processor
A Minimal Dual-Core Speculative Multi-Threading Architecture
Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technolog
Systematic design of high-radix Montgomery multipliers for RSA processors
Architecture and design flow for a debug event distribution interconnect
HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model
Design and Evaluation of the High Performance Multi-Processor Server
SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators
Area evaluation metrics for transistor placement
Estimating the Limits of CPU Power Management for Mobile Games
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
Designing ASICs for Use with Multichip Modules
Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics
Methodologies and Tools for Pipelined On-Chip Interconnect
SoftSSD: Software-defined SSD Development Platform for Rapid Flash Firmware Prototyping
An Extended Class of Sequential Circuits with Combinational Test Generation Complexity
SimiEncode: A Similarity-based Encoding Scheme to Improve Performance and Lifetime of Non-Volatile Main Memory
MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores
Fanin Ordering in Multi-Slot Timing Analysis
Using Provenance to boost the Metadata Prefetching in distributed storage systems
Fast Timing Analysis for Hardware-Software Co-Synthesis
Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking
Logic Synthesis of Synchronous Parallel Controllers
POWER2 Architecture and Performance
A Novel Low-Power Microprocessor Architecture
Compiler-Directed Classification of Value Locality Behavior
ROAD : An Order-Impervious Optimal Detailed Router for FPGAs
Minimization of Ordered Pseudo Kronecker Decision Diagrams
An algorithm for voice and data integration on packet-switched local area networks
CHARM: A checkpoint-based resource management framework for reliable multicore computing in the dark silicon era
Extraction of finite state machines from transistor netlists by symbolic simulation
Robust Path Delay-Fault Testability on Dynamic CMOS Circuits
Logic Synthesis of 100-percent Testable Logic Networks
Power-aware mapping for reconfigurable NoC architectures
High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor
The Cray Y-MP-a VLSI supercomputer
A Framework for Specifying and Designing Pipelines
Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms
LLM-Driven Code Generation for Neural Networks on FPGAs: Bridging Python and HLS
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit
Complexity issues in RAM-DFE design for magnetic disk drives
Testing bio-chips
Design and evaluation of an optical CPU-DRAM interconnect
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
A New Traffic Offloading Method with Slow Switching Optical Device in Exascale Computer
TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes
BDD Decomposition for Efficient Logic Synthesis
Power-Time Tradeoff in Test Scheduling for SoCs
DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis
Concurrent Migration of Multiple Pages in software-managed hybrid main memory
NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform
Asnchronous Wrapper for Heterogeneous Systems
Power-Efficient ReRAM-Aware CNN Model Generation
Testing digital to analog converters based on oscillation-test strategy using sigma-delta modulation
Optical interconnects for interprocessor communications in the Connection Machine
Power management of pulsed-index communication protocols
24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA
Propositional approximations for bounded model checking of partial circuit designs
Design and Implementation of Software Objects in Hardware
A strong arbiter PUF using resistive RAM within 1T-1R memory architecture
WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing
Data-Pattern enabled Self-Recovery multimedia storage system for near-threshold computing
Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency
Supply Voltage Degradation Aware Analytical Placement
ReRAM Crossbar-Based Analog Computing Architecture for Naive Bayesian Engine
Improving memristor memory with sneak current sharing
A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems
Using content-aware bitcells to reduce static energy dissipation