yusuke1997/dblp-id-title huggingface dataset:
Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAs
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs
Efficient LTL compilation for SAT-based model checking
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards
(Invited Paper) AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
Macromodeling of the A.C. characteristics of CMOS Op-amps
Enhancing design robustness with reliability-aware resynthesis and logic simulation
On the Security Vulnerabilities of MRAM-based In-Memory Computing Architectures against Model Extraction Attacks
RC-aware global routing
Global harmony: coupled noise analysis for full-chip RC interconnect networks
Skew aware polarity assignment in clock tree
An efficient statistical analysis methodology and its application to high-density DRAMs
A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations
DynamoSim: a trace-based dynamically compiled instruction set simulator
Energy-Efficient Accelerator for Scalable Point Transformer Networks with Reduced Data Access
Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line Folding
Circuit optimization via adjoint Lagrangians
Quantum Machine Learning Applications in High-Energy Physics
Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging
Carbon nanotube transistor circuits: models and tools for design and performance optimization
Efficient encoding for exact symbolic automata-based scheduling
Timing model reduction for hierarchical timing analysis
A Transfer Learning Framework for High-Accurate Cross-Workload Design Space Exploration of CPU
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion
A vectorless framework for power grid electromigration checking
Automatic synthesis and technology mapping of combinational logic
Delay bounded buffered tree construction for timing driven floorplanning
PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits
(Invited) Generalized GPU-Accelerated Dynamic Programming with Application to Mixed-Cell-Height Detailed Placement
Scaling Microfluidics to Complex, Dynamic Protocols: Invited Paper
Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement
Flip-flop State Driven Clock Gating: Concept, Design, and Methodology
Computing quadratic approximations for the isochrons of oscillators: A general theory and advanced numerical methods
Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax
ASPPLN: Accelerated Symbolic Probability Propagation in Logic Network
Minimum replication min-cut partitioning
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Design of DNA origami
Area optimization of multi-functional processing units
Exploring Performance Tradeoffs for Clustered VLIW ASIPs
Minimizing leakage power in sequential circuits by using mixed V t flip-flops
Using CAD to shape experiments in molecular QCA
Modeling, optimization and control of rotary traveling-wave oscillator
Improving scratch-pad memory reliability through compiler-guided data block duplication
A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips
Error Catch and Analysis for Semiconductor Memories Using March Tests
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
Scalable and scalably-verifiable sequential synthesis
Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration
TSO-Flow: A Topology Synthesis and Optimization Workflow for Operational Amplifiers with Invertible Graph Generative Model
The Compositional Far Side of Image Computation
Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction Method
Circuit Folding: Scalable and Graph-Based Circuit Cutting via Modular Structure Exploitation
Integrating loop and data optimizations for locality within a constraint network based framework
A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization
GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
Lifetime optimization for real-time embedded systems considering electromigration effects
The EVE VLSI information management environment
Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks
SubtreeLU: High-Performance Parallel Sparse LU Factorization for Circuit Simulation
Stepping forward with interpolants in unbounded model checking
On capture power-aware test data compression for scan-based testing
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic
Property specific information flow analysis for hardware security verification
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Package Modeling and Analysis for Heterogeneous Integration
Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans
A manufacturing-oriented environment for synthesis of fabrication processes
iCOACH: a circuit optimization aid for CMOS high-performance circuits
Voltage-based electromigration immortality check for general multi-branch interconnects
Thermal-aware synthesis of integrated photonic ring resonators
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation
Optimal Layout Synthesis for Quantum Circuits as Classical Planning
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Clock-driven performance optimization in interactive behavioral synthesis
A minimum separation algorithm for river routing with bounded number of jogs
Hotspot Detection via Attention-based Deep Layout Metric Learning
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers
NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting
Garbled EDA: Privacy Preserving Electronic Design Automation
A new methodology for the design centering of IC fabrication processes
GORDIAN: a new global optimization/rectangle dissection method for cell placement
A fast and high-capacity electromagnetic solution for highspeed IC design
ACV: an arithmetic circuit verifier
Marsh: min-area retiming with setup and hold constraints
Least fixpoint approximations for reachability analysis
Interconnect layout optimization under higher-order RLC model
Fine-grained hardware/software methodology for process migration in MPSoCs
DiffSAT: Differential MaxSAT Layer for SAT Solving
Analog placement with common centroid constraints
Full chip impact study of power delivery network designs in monolithic 3D ICs
Delay and Crosstalk Simulation of High-Speed VLSI Interconnects with Nonlinear Terminations
Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs
Rapid gate sizing with fewer iterations of Lagrangian Relaxation
Compatible Equivalence Checking of X-Valued Circuits
FEMTO: Fast Error Analysis in Multipliers through Topological Traversal
Design of heterogeneous ICs for mobile and personal communication systems
A framework for early and systematic evaluation of design rules
An approach for improving the levels of compaction achieved by vector omission
Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement
Buffer block planning for interconnect-driven floorplanning
Tight integration of combinational verification methods
Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies
G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and Efficiency
Synthesis of parallel binary machines
ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms
An efficient method for statistical circuit simulation
Timing-driven placement for heterogeneous field programmable gate array
RITUAL: Performance Driven Placement Algorithm for Small Cell ICs
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential
Efficient programming of reconfigurable radio frequency (RF) systems
Automatic Detection of MOS Synchronizers for Timing Verification
Thermal modeling for 3D-ICs with integrated microchannel cooling
A quantitative approach to functional debugging
Placement: Hot or Not?
Embedded Java: techniques and applications (tutorial abstract)
Metrics for structural logic synthesis
A cache-defect-aware code placement algorithm for improving the performance of processors
Simulation of temporal stochastic phenomena in electronic and biological systems: a comparative review, examples and synergies
Context-sensitive static transistor-level IR analysis
An Assembly-Level Execution-Time Model for Pipelined Architectures
Thermal-aware Steiner routing for 3D stacked ICs
GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs
Maximum projections of don't care conditions in a Boolean network
Multi-level approximate logic synthesis under general error constraints
Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization
A new algorithm for the binate covering problem and its application to the minimization of Boolean relations
Automated Hardware Trojan Detection at LUT Using Explainable Graph Neural Networks
AI Analog Circuit Design Agents : On Knowledge Extraction and Transfer with Knowledge Graphs
GPlace: a congestion-aware placement tool for ultrascale FPGAs
Performance estimation and slack matching for pipelined asynchronous architectures with choice
Computing the observable equivalence relation of a finite state machine
Routing using a pyramid data structure
Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper)
Repeater insertion in tree structured inductive interconnect
Layout methods for digital optical computing
Transient circuit simulation for differential algebraic systems using matrix exponential
Acyclic modeling of combinational loops
The circuit design of the synergistic processor element of a CELL processor
MVP: Capture-power reduction with minimum-violations partitioning for delay testing
Edge-BiT: Software-Hardware Co-design for Optimizing Binarized Transformer Networks Inference on Edge FPGA
Inverter minimization in multi-level logic networks
ReTransformer: ReRAM-based Processing-in-Memory Architecture for Transformer Acceleration
Macromodeling of analog circuits for hierarchical circuit design
A novel intensity based optical proximity correction algorithm with speedup in lithography simulation
Library-less synthesis for static CMOS combinational logic circuits
Circuit partitioning with logic perturbation
Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories
PolySA: polyhedral-based systolic array auto-compilation
Congestion Reduction During Placement Based on Integer Programming
Enhancing high-level control-flow for improved testability
An improved method for RTL synthesis with testability tradeoffs
A hybrid linear equation solver and its application in quadratic placement
Algebraic decision diagrams and their applications
Approximate algorithms for time separation of events
Reduction of interpolants for logic synthesis
Boolean matching of function vectors with strengthened learning
Approximate image storage with multi-level cell STT-MRAM main memory
CROP: Fast and effective congestion refinement of placement
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
A Cell-Replicating Approach to Minicut-Based Circuit Partitioning
2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections
Scheduling in Programmable Video Signal Processors
Synthesis for Power-Aware Clock Spines
Observability Relations and Observability Don't Cares
HS: A Hierarchical Search Package for CAD Data
A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping
Low-power timing closure methodology for ultra-low voltage designs
An energy-conscious algorithm for memory port allocation
System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications
Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
On behavioral model equivalence checking for large analog/mixed signal systems
Duplex: simultaneous parameter-performance exploration for optimizing analog circuits
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training
A new built-in self-test approach for digital-to-analog and analog-to-digital converters
Manufacturing and characteristics of low-voltage organic thin-film transistors
Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits
Automated and quality-driven requirements engineering
Personalized Deep Learning for Ventricular Arrhythmias Detection on Medical loT Systems
WCET Guarantees for Opportunistic Runtime Reconfiguration
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization
HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array
Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation
A hybrid local-global approach for multi-core thermal management
Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization
A scheduling method by stepwise expansion in high-level synthesis
PARAS: system-level concurrent partitioning and scheduling
Power estimation tool for sub-micron CMOS VLSI circuits
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity
HiSIM: hierarchical interconnect-centric circuit simulator
Preform: A Process Independent Symbolic Layout System
Achieving Design Closure Through Delay Relaxation Parameter
Fast two-level logic minimizers for multi-level logic synthesis
Unified analytical global placement for large-scale mixed-size circuit designs
A machine learning approach to fab-of-origin attestation
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
SSDe: FPGA-Based SSD Express Emulation Framework
The use of inverse layout trees for hierarchical design verification
Optimization techniques for high-performance digital circuits
Effective simple-power analysis attacks of elliptic curve cryptography on embedded systems
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits
Timing macro-modeling of IP blocks with crosstalk
1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects
An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology
Embedded systems design for low energy consumption
A grid generation system for process and device simulation
Smoothed form of nonlinear phase macromodel for oscillators
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction
Coflex: Enhancing HW-NAS with Sparse Gaussian Processes for Efficient and Scalable DNN Accelerator Design
Multiway partitioning with pairwise movement
A formal instruction-level GPU model for scalable verification
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing
FPGA acceleration of enhanced boolean constraint propagation for SAT solvers
Guaranteeing performance yield in high-level synthesis
Achieving Analog Layout Integrity through Learning and Migration Invited Talk
Don't Cares and Multi-Valued Logic Network Minimization
Yield-driven near-threshold SRAM design
dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUs
Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation
Gate-level simulation of digital circuits using multi-valued Boolean algebras
A unified framework for simultaneous layout decomposition and mask optimization
Automatic concolic test generation with virtual prototypes for post-silicon validation
Incremental Placement for Timing Optimization
Quantum State Preparation Circuit Optimization Exploiting Don't Cares
BoMaNet: Boolean Masking of an Entire Neural Network
Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs
Min-Area Retiming on Dynamic Circuit Structures
Generalized matching from theory to application
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Linear constraint graph for floorplan optimization with soft blocks
Clocking design automation in Intel's Core i7 and future designs
A tensor-based volterra series black-box nonlinear system identification and simulation framework
Optimal CMOS cell transistor placement: a relaxation approach
Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips
Automatic mixed-mode timing simulation
A fast fault simulation algorithm for combinational circuits
A Mixed Discrete-Continuous Optimization Scheme for Cyber-Physical System Architecture Exploration
The logic automation approach to accurate and efficient gate and functional level simulation
Digital RF processor (DRP™) for cellular phones
A data model and architecture for VLSI/CAD databases
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops
Test generation for comprehensive testing of linear analog circuits using transient response sampling
Thermal modeling and design on smartphones with heat pipe cooling technique
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Integrating program transformations in the memory-based synthesis of image and video algorithms
Design of robust test criteria in analog testing
RT-NeRF: Real-Time On-Device Neural Radiance Fields Towards Immersive AR/VR Rendering
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations
Rectangle-packing-based module placement
HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks
Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor
An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs
Comprehensive lower bound estimation from behavioral descriptions
Verification of Delta-Sigma Converters Using Adaptive Regression Modeling
An envelope-following method for the efficient transient simulation of switching power and filter circuits
A detailed router based on simulated evolution
Concurrent D-algorithm on reconfigurable hardware
Secure Token Pruning Mechanism and Accelerator for Vision Transformer
Physical aware frequency selection for dynamic thermal management in multi-core systems
Analytical modeling of SRAM dynamic stability
CIMWise: An IREE-based End-To-End AI Compiler with Auto-Tuning for CIM Processors
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Error-Tolerant Processors: Formal Specification and Verification
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
ScaleHD: Robust Brain-Inspired Hyperdimensional Computing via Adapative Scaling
A polynomial time triple patterning algorithm for cell based row-structure layout
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT
Energy management for real-time embedded systems with reliability requirements
P 4 : Phase-based power/performance prediction of heterogeneous systems via neural networks
Mixed-cell-height legalization considering technology and region constraints
Modeling hierarchical combinational circuits
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators
Automatic Design for Modular Microfluidic Routing Blocks
Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper)
Accurate calculation of bit-level transition activity using word-level statistics and entropy function
Speeding up technology-independent timing optimization by network partitioning
Synthesis of delay fault testable combinational logic
A Hypergraph Partitioner Utilizing a Novel Graph Generative Model
Sparse-T: Hardware Accelerator Thread for Unstructured Sparse Data Processing
Static Verification of Test Vectors for IR Drop Failure
Model-based and data-driven approaches for building automation and control
2024 ICCAD CAD Contest Problem A: Reinforcement Logic Optimization for a General Cost Function
Accurate logic simulation in the presence of unknowns
HAPI: Hardware-Aware Progressive Inference
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning
EasySO: Exploration-enhanced Reinforcement Learning for Logic Synthesis Sequence Optimization and a Comprehensive RL Environment
A sliding window scheme for accurate clock mesh analysis
A low-swing crossbar and link generator for low-power networks-on-chip
ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper
Common path pessimism removal: an industry perspective
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs
2021 ICCAD CAD Contest Problem B: Routing with Cell Movement Advanced: Invited Paper
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
Power grid correction using sensitivity analysis
Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil
AdaLearner: An adaptive distributed mobile learning system for neural networks
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
Automatic memory partitioning and scheduling for throughput and power optimization
Post-placement voltage island generation under performance requirement
Binary time-frame expansion
Latch optimization in circuits generated from high-level descriptions
Sequential logic optimization by redundancy addition and removal
FELIX: fast and energy-efficient logic in memory
Inaccuracies in power estimation during logic synthesis
High-level synthesis of distributed logic-memory architectures
Simplification of non-deterministic multi-valued networks
Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search (Special Session Paper)
Interconnection length estimation for optimized standard cell layouts
Hardware/software managed scratchpad memory for embedded system