yusuke1997/dblp-id-title huggingface dataset:
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2021, AB, Canada, November 8-10, 2021
Complementary Arranged Graphene Nanoribbon-based Boolean Gates
Foundations of memristor based PUF architectures
Analysis of STT-RAM cell design with multiple MTJs per access
AOI-based data-centric circuits for near-memory processing
A supply voltage-dependent variation aware reliability evaluation model
Compression architecture for bit-write reduction in non-volatile memory technologies
Analogue auto-associative memory using a multi-valued memristive memory cell
Memcapacitive reservoir computing
Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar
Analytical study of complementary memristive synchronous logic gates
Irreversibility induced density limits and logical reversiblity in nanocircuits
Energy effective 3D stacked hybrid NEMFET-CMOS caches
Memristor panic - A survey of different device models in crossbar architectures
Low-cost stochastic number generator based on MRAM for stochastic computing
Absolute Subtraction and Division Circuits Using Uncorrelated Random Bitstreams in Stochastic Computing
Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETs
Approximate computing in MOS/spintronic non-volatile full-adder
Non Volatile Operators Emulation Platform
HSB-GDM: a Hybrid Stochastic-Binary Circuit for Gradient Descent with Momentum in the Training of Neural Networks
Nanofabric power analysis: Biosequence alignment case study
System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors
From kekule cells to molecular switches
A fully parallel approximate CORDIC design
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs
On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing
A Markovian, variation-aware circuit-level aging model
Multiplexer-Majority Chains: Managing Correlation and Cost in Stochastic Number Generation
A PCM-based TCAM cell using NDR
Experimental Investigation of Memristance Enhancement
RRAM-based Analog In-Memory Computing : Invited Paper
Robust self-assembly of interconnects by parallel DNA growth
Defect consideratons for robust sparse coding using memristor arrays
Reconfigurable processing in memory architecture based on spin orbit torque
Floating-point unit design with nano-electro-mechanical (NEM) relays
Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing
On brain-inspired connectivity and hybrid network topologies
A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Low area overhead in-situ training approach for memristor-based classifier
Memristor based programmable threshold logic array
Joint Optimization of Randomizer and Computing Core for Low-Cost Stochastic Circuits
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures
Electrical Properties of Proteinoids for Unconventional Computing Architectures
Non-temporal logic performance of an atomic switch network
A ballistic nanoelectronic device simulator
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture
Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization loss
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism
Integrated Synthesis Methodology for Crossbar Arrays
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Design of a Goldschmidt iterative divider for quantum-dot cellular automata
Polymorphic spintronic logic gates for hardware security primitives - Device design and performance benchmarking
A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact
An Efficient Stochastic Convolution Accelerator based on Pseudo-Sobol Sequences
Variation-tolerant Computing with Memristive Reservoirs
Magnetoresistance implications for complementary magnetic tunnel junction logic (CMAT)
Determining fundamental heat dissipation bounds for transistor-based nanocomputing paradigms
Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing
Size Optimization of MIGs with an Application to QCA and STMG Technologies
Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop
Energy management on DVS based coarse-grained reconfigurable platform
Synthesizing HDL to memristor technology: A generic framework
Parallel Computing in Memory Paradigm based on Reconfigurable Spin-Orbit Torque
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013, Brooklyn, NY, USA, July 15-17, 2013
Residue-based code for reliable hybrid memories
Emitter-coupled spin-transistor logic
Sub-crosspoint RRAM decoding for improved area efficiency
Low-power functionality enhanced computation architecture using spin-based devices
Multiplexer Optimization for Adders in Stochastic Computing
Understanding the impact of diode parameters on sneak current in 1Diode 1ReRAM crossbar architectures
Pipeline design in spintronic circuits
NEMS based thermal management for 3D many-core system
A Multi-Level Simulation of GeH FETs: From Nanomaterial and Device Characteristics to Circuit Performance Optimization
Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits
Memristor-based reservoir computing
On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware
Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs
Memory Processing Unit for in-memory processing
Energy efficient many-core processor for recognition and mining using spin-based memory
Hierarchical design of robust and low data dependent FinFET based SRAM array
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch
Plasma Modified Silicon Nitride Resistive Switching Memories
Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures
Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar
Ultra low energy analog image processing using spin based neurons
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires
Hybrid MTJ-CMOS Integration for Sigma-Delta ADC
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, NANOARCH 2023, Dresden, Germany, December 18-20, 2023
On the impact of OxRAM-based synapses variability on convolutional neural networks performance
Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric
A Robust Time-based Error-Proofing Readout Scheme for MRAM
NanoV: Nanowire-based VLSI design
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction
Evaluation of spin-Hall-assisted STT-MRAM for cache replacement
RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer
Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
SkyNet: Memristor-based 3D IC for artificial neural networks
A comparative evaluation of approximate multipliers
CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs
Improved circuit model for all-spin logic
Concept paper on novel radio frequency resistive switches
A scheme for computation in nanoscale dynamical systems: Gated discrete phase-shift interactions
Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Design and operational assessment of an intra-cell hybrid L2 cache
Introducing OVP awareness to achieve an efficient permanent defect locating
rFGA: CMOS-nano hybrid FPGA using RRAM components
Performance assessment of partially unzipped carbon nanotube field-effect transistors
ToPoliNano: nanoarchitectures design made real
Matrix multiplication by an inexact systolic array
A Novel Analog to Digital Conversion Concept with Crosstalk Computing
Design exploration methodology for memristor-based spiking neuromorphic architectures with the Xnet event-driven simulator
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures
Stochastic neuron design using conductive bridge RAM
Spatio-temporal learning with arrays of analog nanosynapses
Learning with memristive devices: How should we model their behavior?
Design-space exploration of fault-tolerant building blocks for large-scale quantum computing
Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural Networks
Transmission gate-based approximate adders for inexact computing
An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications
Fine-grained 3D reconfigurable computing fabric with RRAM
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
Verilog - A compact model of a ME-MTJ based XNOR/NOR gate
Challenges in scalable fault tolerance
Impact of the switching mode on the read noise of ReRAM devices
Naive Bayesian inference of handwritten digits using a memristive associative memory
A logic-in-memory design with 3-terminal magnetic tunnel junction function evaluators for convolutional neural networks
Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations
SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT
Efficient Multi-Path Signal Routing for Field-coupled Nanotechnologies
Monte Carlo simulations of carbon nanotube networks for optoelectronic applications
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Nanomechanical non-volatile memory for computing at extreme
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
Error Correction Code protected Data Processing Units
HDCOG: A Lightweight Hyperdimensional Computing Framework with Feature Extraction
Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Design of high-yield defect-tolerant self-assembled nanoscale memories
Validating cascading of crossbar circuits with an integrated device-circuit exploration
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes
A CMOS-memristive self-learning neural network for pattern classification applications
Reading spin-torque memory with spin-torque sensors
Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices
Integrated Control Addressing Circuits for a Surface Code Quantum Computer in Silicon
Self-timed nano-PLA
Neural Network Modeling Bias for Hafnia-based FeFETs
Design of 8T-nanowire RAM array
Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM
Throughput-dissipation tradeoff in partially reversible nanocomputing: A case study
A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge
Crossbar architecture based on 2R complementary resistive switching memory cell
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, July 18-20, 2016
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing
Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS
VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors
Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Athens, Greece, July 17-19, 2018
Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution
Online test and fault-tolerance for nanoelectronic programmable logic arrays
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation
Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Regular Expression Matching with Memristor TCAMs for Network Security
Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Low-power design technique with ambipolar double gate devices
Architecting connectivity for fine-grained 3-D vertically integrated circuits
FeFET-based Process-in-Memory Architecture for Low-Power DNN Training
A pageable, defect-tolerant nanoscale memory system
Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Low cost multi-error correction for 3D polyhedral memories
Minimization of a reversible quantum 2 n -to-n BCD priority encoder
Nonvolatile online CMOS trimming with magnetic tunnel junctions
Transient model with interchangeability for dual-gate ambipolar CNTFET logic design
Using carbon nanotube in digital memories
Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance
Cell design and comparative evaluation of a novel 1T memristor-based memory
Automatic Place&Route of Nano-magnetic Logic circuits
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, USA, June 8-9, 2011
A coding framework for DNA self-assembly
Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Ex-situ training of dense memristor crossbar for neuromorphic applications
Fundamental limits of energy dissipation in spintronic interconnects using optical spin pumping
Experimental Verification of EMPA Fault Mechanism
Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations
A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA)
Robust In-Memory Computing with Hyperdimensional Stochastic Representation
NEM relay design with biconditional binary decision diagrams
Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices
Lossy frequency selective surfaces for gas sensing using ZnO films
Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network
Minimal Disturbed Bits in Writing Resistive Crossbar Memories
Experimental prototyping of beyond-CMOS nanowire computing fabrics
Inversion optimization in Majority-Inverter Graphs
Multi-context non-volatile content addressable memory using magnetic tunnel junctions
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Stochastic nanoscale addressing for logic
Stateful implication logic with memristors
Low-power multiplexer designs using three-independent-gate field effect transistors
CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019, Qingdao, China, July 17-19, 2019
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014
MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories
Skeleton-based design and simulation flow for Computation-in-Memory architectures
Power Analysis of an mRNA-Ribosome System
Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database
Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology
Supervised learning with organic memristor devices and prospects for neural crossbar arrays
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique
Locality aware redundancy allocation in nanoelectronic systems
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processors
Towards logic functions as the device
MECRO: A local processing computer architecture based on memristor crossbar
Architecting energy efficient crossbar-based memristive random-access memories
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm
2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits
An STT-MRAM based strong PUF
Charge distribution in a molecular QCA wire based on bis-ferrocene molecules
A Recursive Growing & Featuring Mechanism for Nanocomputing Structures
Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition
Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits
TFET NDR skewed inverter based sensing method
Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ
Doped HfO2 based nanoelectronic memristive devices for self-learning neural circuits and architecture
Ambipolar double gate CNTFETs based reconfigurable logic cells
Error Resilience and Recovery of Process Induced Stuck-at Faults in MLP Neural Networks using Emerging Technology
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
Real-Time Trainable Data Converters for General Purpose Applications
Memristor content addressable memory
A T-depth two Toffoli gate for 2D square lattice architectures
Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery
Effect of potential disorder on shot noise suppression in nanoscale devices
Graphene nanoribbon crossbar nanomesh
Design of approximate Redundant Binary multipliers
Proposal for novel magnetic memory device with spin momentum locking materials
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy
Wave-based multi-valued computation framework
Full-adder circuit design based on all-spin logic device
Automated synthesis of crossbars for nanoscale computing using formal methods
Content-aware encoding for improving energy efficiency in multi-level cell resistive random access memory
Current Characteristics of Defective GNR Nanoelectronic Devices
Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric
Nanoscale Application Specific Integrated Circuits
Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic
Accelerate context switch by racetrack-SRAM hybrid cells
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics
Spin wave nanofabric update
Architecting NP-Dynamic Skybridge
A Probabilistic Error Model and Framework for Approximate Booth Multipliers
Thermally-induced soft errors in nanoscale CMOS circuits
Ambipolar independent double gate FET logic
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation
RRAM-based FPGA for "normally off, instantly on" applications
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions
Analysis of defect tolerance in molecular electronics using information-theoretic measures
2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, San Francisco, CA, USA, July 30-31, 2009
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications
Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices
Volatile memristive devices as short-term memory in a neuromorphic learning architecture
Error Analysis of the Variational Quantum Eigensolver Algorithm
Deep Neural Network Security From a Hardware Perspective
Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
Clocking nanocircuits for nanocomputers and other nanoelectronic systems
A DSP nanosystem with defect tolerance
A memristor-based TCAM (Ternary Content Addressable Memory) cell
Combining 2-level logic families in grid-based nanoscale fabrics
Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon
Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
A voterless strategy for defect-tolerant nano-architectures
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation
Crossbar latch-based combinational and sequential logic for nano FPGA
Interconnect networks for memristor crossbar
Applications of wavelength-fan-in for high-performance distributed processing systems
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches
Ultra-fine grain FPGAs: A granularity study
A novel write-scheme for data integrity in memristor-based crossbar memories
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
A standard cell approach for MagnetoElastic NML circuits
Extending the fundamental error bounds for asymmetric error reliable computation
High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron
Linear regression based multi-state logic decomposition approach for efficient hardware implementation
Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
L 3 EP: Low latency, low energy program-and-verify for triple-level cell phase change memory
Digital-to-analog and analog-to-digital conversion with metal oxide memristors for ultra-low power computing
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs
N3ASICs: Designing nanofabrics with fine-grained CMOS integration
Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction function
Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
Scalability and design-space analysis of a 1T-1MTJ memory cell
2008 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, June 12-13, 2008
Gate-level modeling for CMOS circuit simulation with ultimate FinFETs
Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
A spin Hall effect-based multi-level cell for MRAM
Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraints
Assessing random dynamical network architectures for nanoelectronics
Design methodologies for high density domain wall memory
Macromodeling a phase change memory (PCM) cell by HSPICE
Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator