yusuke1997/dblp-id-title huggingface dataset:
2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors
Performance and hardware complexity tradeoffs in designing multithreaded architectures
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization
GraphMini: Accelerating Graph Pattern Matching Using Auxiliary Graphs
Automatic Analytical Modeling for the Estimation of Cache Misses
Using compilers for heterogeneous system design
Using memory mapping to support cactus stacks in work-stealing runtime systems
SEED: scalable, efficient enforcement of dependences
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
Quantifying the Potential of Program Analysis Peripherals
Hypart: a hybrid technique for practical memory bandwidth partitioning on commodity servers
Scalable Task Scheduling and Synchronization Using Hierarchical Effects
14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 17-21 September 2005, St. Louis, MO, USA
Design of a storage processing unit
Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics
Bridging the Semantic Gaps of GPU Acceleration for Scale-out CNN-based Big Data Processing: Think Big, See Small
Spill Code Minimization by Spill Code Motion
CoreGenesis: erasing core boundaries for robust and configurable performance
Towards a Time and Space Efficient Functional Implementation of a Monte Carlo Photon Transport Code
Dataflow Frequency Analysis Based on Whole Program Paths
Efficient Methods for Multi-Dimensional Array Redistribution
Fine Grain Cache Partitioning Using Per-Instruction Working Blocks
Efficient Atomic Durability on eADR-Enabled Persistent Memory
A Unified Compiler Framework for Control and Data Speculation
Adaptive Scheduling of Computations and Communications on Distributed Memory Systems
The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources
Shuffling: a framework for lock contention aware thread scheduling for multicore multiprocessor systems
Regional Out-of-Order Writes in Total Store Order
Prematerialization: reducing register pressure for free
A Methodology for Principled Approximation in Visual SLAM
PEPSC: A Power-Efficient Processor for Scientific Computing
Branch predictor guided instruction decoding
Design Study of Shared Memory in VLIW Video Signal Processors
Phase-based scheduling and thread migration for heterogeneous multicore processors
Branch prediction and simultaneous multithreading
Revealing parallel scans and reductions in recurrences through function reconstruction
Accelerating Linked-list Traversal Through Near-Data Processing
In Search of Speculative Thread-Level Parallelism
Automatic OpenCL work-group size selection for multicore CPUs
Supporting stateful tasks in a dataflow graph
A Fully Asynchronous Superscalar Architecture
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory
The Modulo Interval: A Simple and Practical Representation for Program Analysis
Cost-Effective Compiler Directed Memory Prefetching and Bypassing
Implementing Malleability on MPI Jobs
Auto-tuning Static Schedules for Task Data-flow Applications
Writeback-aware bandwidth partitioning for multi-core systems with PCM
Parallelizing Maximal Clique Enumeration on GPUs
Data Structure Exploration of Dynamic Applications
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
A fine-grain multithreading superscalar architecture
Building Retargetable and Efficient Compilers for Multimedia Instruction Sets
Multi-optimization power management for chip multiprocessors
Parallel Methods for Verifying the Consistency of Weakly-Ordered Architectures
Evaluating the impact of advanced memory systems on compiler-parallelized codes
Exploring the Limits of Sub-Word Level Parallelism
CoPlace: Effectively Mitigating Cache Conflicts in Modern Clouds
Combining Run-Time Checks and Compile-Time Analysis to Improve Control Flow Auto-Vectorization
Data Flow Analysis for Software Prefetching Linked Data Structures in Java
Revisiting sorting for GPGPU stream architectures
Optimal fine and medium grain parallelism detection in polyhedral reduced dependence graphs
Performance analysis and autotuning setup of the cuFFT library
Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory
Extended Whole Program Paths
POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns
Student Research Poster: Slack-Aware Shared Bandwidth Management in GPUs
An Efficient Online Path Profiling Framework for Java Just-In-Time Compilers
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs
28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019
Using Aggressor Thread Information to Improve Shared Cache Management for CMPs
Optimizing Data Locality for SCI-Based PC-Clusters with the SmiLE Monitoring Approach
The evicted-address filter: a unified mechanism to address both cache pollution and thrashing
A case for NUMA-aware contention management on multicore systems
International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014
Using Dataflow Based Context for Accurate Value Prediction
Concurrent predicates: A debugging technique for every parallel programmer
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures
Memory-Equipped Quantum Architectures: The Power of Random Access
Memory State Compressors for Giga-Scale Checkpoint/Restore
Linear-time Modeling of Program Working Set in Shared Cache
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning
Data Centric Transformations on Non-Integer Iteration Spaces
The OpenTM Transactional Application Programming Interface
Warp-aware trace scheduling for GPUs
Address Partitioning in DSM Clusters with Parallel Coherence Controllers
Doppeladler: Adaptive Tensor Parallelism for Latency-Critical LLM Deployment on CPU-GPU Integrated End-User Device
EFetch: optimizing instruction fetch for event-driven webapplications
Analysis and approximation of optimal co-scheduling on chip multiprocessors
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems
A Parallel Algorithm for Compile-Time Scheduling of Parallel Programs on Multiprocessors
Reactive-Associative Caches
Exploring Memory Persistency Models for GPUs
Automatic partitioning of signal processing programs for symmetric multiprocessors
SumPA: Efficient Pattern-Centric Graph Mining with Pattern Abstraction
CPROB: Checkpoint Processing with Opportunistic Minimal Recovery
tm_db: A Generic Debugging Library for Transactional Programs
Semi-automatic extraction and exploitation of hierarchical pipeline parallelism using profiling information
Multiway Merge Partitioning for Sparse-Sparse Matrix Multiplication on GPUs
In-DRAM near-data approximate acceleration for GPUs
Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?
Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect
Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining
POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling
Exploiting Parallelism with Dependence-Aware Scheduling
An analytical model of high performance superscalar-based multiprocessors
Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications
Generating Two-Level, GPU-Aware Mappings for Distributed Tensor Computations
Nexus: A New Approach to Replication in Distributed Shared Caches
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
CRAIG: a practical framework for combining instruction scheduling and register assignment
Speculative Parallelization in Decoupled Look-ahead
A Unified Scheduler for Recursive and Task Dataflow Parallelism
Characterizing and modeling the behavior of context switch misses
Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines
POSTER: PIMAP: Characterizing a Real Processing-in-Memory System for Analytical Data Processing
Heap Analysis and Optimizations for Threaded Programs
Automatic Code-Generation for Accelerating Structured-Mesh-Based Explicit Numerical Solvers on FPGAs
16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007
On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm
Stencil codes on a vector length agnostic architecture
2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain
Dealing with the Unknown: Resilience to Prediction Errors
RISE: improving the streaming processors reliability against soft errors in gpgpus
(How) can programmers conquer the multicore menace?
Adaptive Receiver Notification for Non-Dedicated Workstation Clusters
Prediction models for multi-dimensional power-performance optimization on many cores
Neighborhood Prefetching on Multiprocessors Using Instruction History
DANBI: Dynamic scheduling of irregular stream programs for many-core systems
PolyGym: Polyhedral Optimizations as an Environment for Reinforcement Learning
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics
Automatic vectorization of tree traversals
Meeting midway: Improving CMP performance with memory-side prefetching
Origin 2000 Design Enhancements for Communication Intensive Applications
StVEC: A Vector Instruction Extension for High Performance Stencil Computation
Making data prefetch smarter: adaptive prefetching on POWER7
Fast Paths in Concurrent Programs
Architectural Support for Enhanced SMT Job Scheduling
Improving Throughput-oriented LLM Inference with CPU Computations
Fine Grained Multithreading with Process Calculi
Salient Store: Enabling Smart Storage for Continuous Learning Edge Servers
Optimizing Regular Expression Matching with SR-NFA on Multi-Core Systems
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities
Collective Affinity Aware Computation Mapping
POSTER: Variable Sized Cache-Block Compaction
Deep Learning Assisted Resource Partitioning for Improving Performance on Commodity Servers
Throttling Automatic Vectorization: When Less is More
Power Tuning HPC Jobs on Power-Constrained Systems
Large Scale Data Clustering Using Memristive k-Median Computation
Constraint Graph Analysis of Multithreaded Programs
Fast Convolutional Neural Networks with Fine-Grained FFTs
Database analytics acceleration using FPGAs
Starchart: Hardware and software optimization using recursive partitioning regression trees
Managing the computing space in the mpC compiler
Exploring Sub-Block Value Reuse for Superscalar Processors
A run-time power manager exploiting software parallelism
Data-Driven execution of the Tile LU Decomposition
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998
Tracking and Reducing Uncertainty in Dataflow Analysis-Based Dynamic Parallel Monitoring
Optimizing Data Layouts for Parallel Computation on Multicores
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
SuperGraph-SLP Auto-Vectorization
Improving Signatures by Locality Exploitation for Transactional Memory
ANG: Accelerating NFA processing on GPUs via Exploring Multi-Level Fine-Grained Parallelism
A compiler algorithm to reduce invalidation latency in virtual shared memory systems
DeSTM: harnessing determinism in STMs for application development
PS-cache: An energy-efficient cache design for chip multiprocessors
Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology
Invyswell: a hybrid transactional memory for haswell's restricted transactional memory
Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
Evaluation of NTP/PTP fine-grain synchronization performance in HPC clusters
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework
CPC: Coordinated Page Cache for Serverless Computing
Complexity-based program phase analysis and classification
BOOM: Use your Desktop to Accurately Predict the Performance of Large Deep Neural Networks
Build Watson: an overview of DeepQA for the Jeopardy! challenge
Bandwidth bandit: quantitative characterization of memory contention
Jigsaw: Scalable software-defined caches
Approximating age-based arbitration in on-chip networks
POSTER: Quantifying the Direct Overhead of Virtual Function Calls on Massively Parallel Architectures
APOGEE: Adaptive prefetching on GPUs for energy efficiency
mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL
DSDP: Dual Stream Data Prefetcher
HugeGPT: Storing Guest Page Tables on Host Huge Pages to Accelerate Address Translation
DAFT: decoupled acyclic fault tolerance
Cameron: High level Language Compilation for Reconfigurable Systems
A Parallel Hash Table for Streaming Applications
POSTER: A Collaborative Multi-Factor Scheduler for Asymmetric Multicore Processors
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation
Exploiting Program Semantics to Place Data in Hybrid Memory
A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors
A New Qubits Mapping Mechanism for Multi-programming Quantum Computing
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor
Pointy: a hybrid pointer prefetcher for managed runtime systems
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
Towards General-Purpose Neural Network Computing
POSTER: Putting the G back into GPU/CPU Systems Research
A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications
GPUPool: A Holistic Approach to Fine-Grained GPU Sharing in the Cloud
Accelerating DCA++ (Dynamical Cluster Approximation) Scientific Application on the Summit Supercomputer
SampleMine: A Framework for Applying Random Sampling to Subgraph Pattern Mining through Loop Perforation
Proceedings of the 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2017, Portland, OR, USA, September 9, 2017
A DSL for Performance Orchestration
Parallel Loop Locality Analysis for Symbolic Thread Counts
Online Scalability Characterization of Data-Parallel Programs on Many Cores
AIBench Scenario: Scenario-Distilling AI Benchmarking
LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers
Unfair Scheduling Patterns in NUMA Architectures
Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG
Automatic vector instruction selection for dynamic compilation
Rinnegan: Efficient Resource Use in Heterogeneous Architectures
PRISM: Architectural Support for Variable-granularity Memory Metadata
WearCore: A Core for Wearable Workloads
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration
McRouter: Multicast within a router for high performance network-on-chips
Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs
PEPON: performance-aware hierarchical power budgeting for NoC based multicores
Scalable High Performance Cross-Module Inlining
Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme
A software-SVM-based transactional memory for multicore accelerator architectures with local memory
Quickloop: An Efficient, FPGA-Accelerated Exploration of Parameterized DNN Accelerators
Using the Compiler to Improve Cache Replacement Decisions
Speculative Alias Analysis for Executable Code
Exploiting Task Order Information for Optimizing Sequentially Consistent Java Programs
Variational Path Profiling
A Compiler-assisted Runtime-prefetching Scheme for Heterogenous Platforms
Decoupled Address Translation for Heterogeneous Memory Systems
Gluon-Async: A Bulk-Asynchronous System for Distributed and Heterogeneous Graph Analytics
Whole-program optimization of global variable layout
PACT 2009, Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, 12-16 September 2009, Raleigh, North Carolina, USA
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications
Call-chain Software Instruction Prefetching in J2EE Server Applications
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour
A Cost Framework for Evaluating Integrated Restructuring Optimizations
Improving Convolution via Cache Hierarchy Tiling and Reduced Packing
Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance
POSTER: BigBus: A Scalable Optical Interconnect
POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses
A Static Cut-off for Task Parallel Programs
Consolidated conflict detection for hardware transactional memory
Bounded memory scheduling of dynamic task graphs
SPACE: sharing pattern-based directory coherence for multicore scalability
Breaking the Barriers: Two Models for MPI Programming
POSTER: Runtime Adaptations for Energy-Efficient VSLAM
FastForward for Efficient Pipeline Parallelism
POSTER: The Performance Impact of Thread Packing on Synchronization-Intensive Applications
Velociraptor: an embedded compiler toolkit for numerical programs targeting CPUs and GPUs
Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches
Global Register Partitioning
Multithreaded Programming of PC Clusters
Measuring flexibility in single-ISA heterogeneous processors
Athena: An Early-Fetch Architecture to Reduce on-Chip Page Walk Latencies
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors
Path Profile Guided Partial Dead Code Elimation Using Predication
Cost effective speculation with the omnipredictor
Graph-based performance accounting for chip multiprocessor memory systems
The Energy Impact of Aggressive Loop Fusion
Caching and Predicting Branch Sequences for Improved Fetch Effectiveness
Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures
An intra-tile cache set balancing scheme
DEP: detailed execution profile
Multiple Page Size Modeling and Optimization
Resolving Register Bank Conflicts for a Network Processor
QeiHaN: An Energy-Efficient DNN Accelerator that Leverages Log Quantization in NDP Architectures
Capturing the Effects of Code Improving Transformations
No More Backstabbing... A Faithful Scheduling Policy for Multithreaded Programs
Performance prediction based on inherent program similarity
Impact of Java Memory Model on Out-of-Order Multiprocessors
Leveraging Difference Recurrence Relations for High-Performance GPU Genome Alignment
Studying Compiler-Microarchitecture Interactions through Interval Analysis
Probabilistic diagnosis of performance faults in large-scale parallel applications
The Paralax infrastructure: automatic parallelization with a helping hand
Drishyam: An Image is Worth a Data Prefetcher
Scalable SIMD-Efficient Graph Processing on GPUs
A Multi-Platform Co-Array Fortran Compiler
Compiler support for selective page migration in NUMA architectures
Exposing ILP in custom hardware with a dataflow compiler IR
Improving Run-Time Scheduling for General-Purpose Parallel Code
Transparent runtime deadlock elimination
Automatic Generation of Actor-based Parallelism from Shared-Memory Parallel Programs
Dynamic memory access monitoring based on tagged memory
Speculative parallelization needs rigor: probabilistic analysis for optimal speculation of finite-state machine applications
Layout-oblivious optimization for matrix computations
Effective Management of DRAM Bandwidth in Multicore Processors
Performance Analysis of System Overheads in TCP/IP Workloads
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy
Profiler and compiler assisted adaptive I/O prefetching for shared storage caches
Polygeist: Raising C to Polyhedral MLIR
Adding Limited Reconfigurability to Superscalar Processors
Power-aware multi-core simulation for early design stage hardware/software co-optimization
Improving support for locality and fine-grain sharing in chip multiprocessors
Vectorization of Multibyte Floating Point Data Formats
Testing implementations of transactional memory
Linux Alighted: Down to Earth Clusters
Efficient Personalized Communication on Wormhole Networks
Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments
Generating efficient data movement code for heterogeneous architectures with distributed-memory
A Software-Managed Coherent Memory Architecture for Manycores
POSTER: DaPPA: A Data-Parallel Programming Framework for Processing-in-Memory Architectures
Automatic Parallelization of Recursive Procedures
15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs
A proposal of self-cleanup cache
Transparent Dual Memory Compression Architecture
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks
Scalable hardware support for conditional parallelization
Fine-grained parallel traversals of irregular data structures
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors
I-Structure Software Cache: a split-phase transaction runtime cache system
Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs
Allocating registers in multiple instruction-issuing processors
Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help
A compiler algorithm that reduces read latency in ownership-based cache coherence protocols
Skywalker: Efficient Alias-Method-Based Graph Sampling and Random Walk on GPUs
ReCaP: a region-based cure for the common cold cache
Runtime Value Numbering: A Profiling Technique to Pinpoint Redundant Computations
Effective Compilation Support for Variable Instruction Set Architecture
POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework
POSTER: Cutting the Fat: Speeding Up RBM for Fast Deep Learning Through Generalized Redundancy Elimination
Wavelet-based phase classification
Tiled-MapReduce: optimizing resource usages of data-parallel applications on multicore with tiling
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Making it practical and effective: fast and precise may-happen-in-parallel analysis
Compiler Directed Data Locality Optimization for Multicore Architectures
Hybrid Specialization: A Trade-off Between Static and Dynamic Specialization
Cimple: instruction and memory level parallelism: a DSL for uncovering ILP and MLP
Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU
Barad-dur: Near-Storage Accelerator for Training Large Graph Neural Networks
Latency Hiding in Multi-Threading and Multi-Processing of Network Applications
Poster: HeteroSched: Co-Optimizing Scheduling and Parallelization for Deep Learning Workloads
CAF: Core to Core Communication Acceleration Framework
Address generation of dataflow fine-grain parallel data-structures on a distributed-memory computer
Multi-Core to the Masses
Coalition threading: combining traditional andnon-traditional parallelism to maximize scalability