yusuke1997/dblp-id-title huggingface dataset:
Adaptive Shared Memory Control for Multimedia Systems-on-Chip
Exception handling in microprocessors using assertion libraries
AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic Units
System design for 3D Silicon integration
A Semi-Automated Sizing Tool for CMOS Analog Building Blocks Integrated into EDA Environment
A SystemC profiling framework to improve fixed-point hardware utilization
Full-Virtualization on MIPS-based MPSOCs embedded platforms with real-time support
A SiGe HBT limiting amplifier for fast switching of mm-wave super-regenerative oscillators
Issues in parallelizing multigrid-based substrate model extraction and analysis
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing
Low-power test in compression-based reconfigurable scan architectures
A Charge Correction Cell for FGMOS-Based Circuits
Verification and test challenges in SoC designs
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures
Failure Assessment of NASA cFS Case-Study Flight Software on RISC-V via Fault Injection
An All-digital Programmable Current-limited Discharge Circuitry for a Safe Electrical Stimulation
Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs
Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies
Low-Power Fully-Testable Flow Meter in CMOS ASIC
A cyborg beetle: wireless neural flight control of a free-flying insect
MDA-based approach for embedded software generation from a UML/MOF repository
Optimized sizing of analog circuits using the interior-point method for nonconvex nonlinear functions under MATLAB
Impact of Circuit-Level Radiation-Hardening Techniques in Adders on a RISC-V Design
A Temporal Logic for Data-Flow VHDL
A design methodology for low-noise CMOS transimpedance amplifiers based on shunt-shunt feedback topology
Experiences on Analog Circuit Technology Migration and Reuse
A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32
Analog Decimator IC in Direct-form Polyphase Structure
An FPGA-based accelerator for multiple real-time template matching
Deep Nibble: A 4-bit Number Format for Efficient DNN Training and Inference in FPGA
Transforms and quantization design targeting the H.264/AVC intra prediction constraints
Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification
Exploring Adaptive Design Mapping and Device Activation in Multi-FPGA Edge Environments
TheoSim: combining symbolic simulation and theorem proving for hardware verification
Test and design-for-test of mixed-signal integrated circuits
Radial basis function network applied to the linearization of a voltage controlled oscillator
A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC)
A Current Limiter for Linear Regulators Based on Power-Dissipation Threshold
Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGA
Voltage Regulator with Ellipsoidal Transistors
Challenges of the nanoscale era
Fault tolerance overhead in network-on-chip flow control schemes
A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension
A 0.55-V Oscillator with Improved Stability Against Temperature and Supply-Voltage Variations
HW/SW Codesign of Handoff Protocol for Wireless ATM Networks Based on Performance Optimization Using Genetic Algorithm
Floating gate MOSFET circuit design for a monolithic MEMS GAS sensor
Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization
An Input-Output Encoding Approach for Serial Decomposition
Low-frequency passive RFID systems implementation in CMOS technology: design considerations and tradeoffs
Evaluating the robustness of secure triple track logic through prototyping
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor
Memory Controller with Adaptive ECC for Reliable System Operation
A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs
Hardware/software debugging of large scale many-core architectures
Total leakage power optimization with improved mixed gates
Direction-Based Fast Mode Decision and Hardware Design for the AV1 Intra Prediction
An efficient implementation of montgomery powering ladder in reconfigurable hardware
Energy-speed exploration for very-wide range of dynamic V-F scaling
Design of a digital FM demodulator based on a 2nddegree order all-digital phase-locked loop
Parallel prefix adder design using quantum-dot cellular automata
New insight for next generation SRAM: tunnel FET versus FinFET for different topologies
Exception Handling with Petri Net for Digital Systems
CVF ¾ Coverification Framework
Resource-and-time-aware test strategy for configurable quaternary logic blocks
A current limiter for DC/DC regulators with internal compensation for process and temperature
A 125-kHz 4th-order Continuous-Time Sigma-Delta Modulator with Single Amplifier Resonator
Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator
Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI
Balanced Prefetching Aggressiveness Controller for NoC-based Multiprocessor
High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding
A security-aware routing implementation for dynamic data protection in zone-based MPSoC
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits
An efficient, low-cost ECC approach for critical-application memories
Testing RF Signal Paths Using Spectral Analysis and Subsampling
Algorithms and Structures for Reconfigurable Multiplication Units
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique
High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation
An RF-powered temperature sensor designed for biomedical applications
An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder
Design of High-Voltage Level Shifters Based on Stacked Standard Transistors for a Wide Range of Supply Voltages
First-pass-silicon radio IPs for B3G wireless networks
An Integrated CMOS Instrumentation Amplifier with Improved CMRR
A Resistorless Low-Power Differentiator for MPPT Adjustment of Energy Harvesting Systems
Bee Colony Algorithm Applied to Memory Architecture Exploration intended for Energy Reduction
Low-Power Control Architecture for Embedded Processors
Dynamic Approximate Storage Scheme for VVC Intra-Frame Prediction
Toward nanometric scale integration: an automatic routing approach for NML circuits
Efficient Hardware Design for Compressed Blocks SAD Calculation in VVC Motion Estimation
Techniques and Mechanisms for Dynamic Reconfiguration in an Image Processor
A 14b threshold configurable dynamically latched comparator for SAR ADCs
Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits
A Versatile, Low-Power Platform for PHS Silicon Integration
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection
Implementation of an Edge Detection Algorithm in a Reconfigurable Computing System
Design of a radix-2 m hybrid array multiplier using carry save adder format
The LRD traffic impact on the NoC-based SoCs
Design of a decompressor engine on a SPARC processor
SDDS-NCL Design: Analysis of Supply Voltage Scaling
A fast SAT solver algorithm best suited to reconfigurable hardware
A High-level Model to Leverage NoC-based Many-core Research
A power-predictive environment for fast and power-aware ASIC-based FIR filter design
RS5-SoC: A Flexible Open-Source RISC-V Platform for Embedded Systems
On Generating Compact, Passive Models of Frequency-Described Systems
On the design of ultra low noise amplifiers for ENG recording
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design
LEGAL: An Algorithm for Simultaneous Net Routing
Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW Processors
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy
Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers
BANCS: Bidirectional Alternating Nanomagnetic Clocking Scheme
Linear AGC for conditioning applications with adaptive time constant and frequency dependency
The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput
Design and Analysis of Approximate Hardware Accelerators for VVC Intra Angular Prediction
PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration
Reconfigurable Group-Wise Security Architecture for NoC-Based MPSoCs Protection
A 0.55-V 0.1°C-Accuracy All-CMOS Temperature Sensor for Implanted Devices
A 37 nW MOSFET-Only Voltage Reference in 0.13 μm CMOS
Design and Synthesis of Row-Stationary Hardware Accelerators for 2D Convolution
A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter
Fast disjoint transistor networks from BDDs
Improving the Statistical Variability of Delay-based Physical Unclonable Functions
HoneyComb: an application-driven online adaptive reconfigurable hardware architecture
VLSI Design of a Fast and Reprogrammable Decision Tree Inference Accelerator
RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities
Hybrid filter for high-power converter systems
FPGA hardware linear regression implementation using fixed-point arithmetic
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
Estimating Software and Hardware Video Decoder Energy Using Software Decoder Profiling
Computing at the ultimate low-energy limits
A Low-Cost FPGA Implementation of the Advanced Encryption Standard Algorithm
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification
Reconfigurable Hardware for Tomographic Processing
Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology
A Placement and routing algorithm for Quantum-dot Cellular Automata
A FPGA parameterizable multi-layer architecture for CNNs
Segmented spline hardware design for high dynamic range video pre-processor
Statistical analysis and design: from picoseconds to probabilities
A Temperature Compensated Fully Trimmable On-Chip IC Oscillator
Design of RF CMOS low noise amplifiers using a current based MOSFET model
Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard
A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero-VT active loads
Power Optimized Viterbi Decoder Implementation through Architectural Transforms
A pixel concept that simultaneously enables high dynamic range, high sensitivity and operation in intense backgrounds
A fully integrated physical activity sensing circuit for implantable pacemakers
Modeling and designing high performance analog reconfigurable circuits
Synthesis of CMOS Operational Amplifiers through Genetic Algorithms
A path-load based adaptive routing algorithm for networks-on-chip
MorphoSys: A Reconfigurable Architecture for Multimedia Applications
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer
Bandwidth Efficient Gaussian Minimum Frequency-Shift Keying Approach for Software Defined Radio
Voltage Coefficient of Resistance Effect in the Harmonic Distortion of Active-RC Continuous-Time Sigma-Delta Modulators
Operational Amplifier Performance Degradation and Time-to-Failure due to Electromigration
Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor
Low-area ASIC implementation for configurable coefficients FIR pulse shape filters of digital TV systems
A Time-Efficient Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits
Integrated Cmos Linear Dosimeter
Software-Defined Radio design based on GALS architecture for FPGAs
Prototyping a Pager-Like Device Using FPGAs: Design of an Object Finder
A Modular Power Switches Layout Strategy to a SiC Gate Driver Development
Differential mixer with NMOS/PMOS stack at switching stage
Cache performance impacts for stack machines in embedded systems
Signal Processing Applications for Embedded Java Systems
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic
Design of crest factor reduction techniques based on clipping and filtering for wireless communications systems
A Low Ripple Fully Integrated Charge Pump Regulator
A 50MHz-lGHz wideband low noise amplifier in 130nm CMOS technology
Algorithm and hardware design of a fast intra-frame mode decision module for h.264/AVC encoders
Advanced Thermal Management using Approximate Computing and On-Chip Thermoelectric Cooling
Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology
A standard cell characterization flow for non-standard voltage supplies
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack
A FPGA Implementation of a DCT-Based Digital Electrocardiographic Signal Compression Device
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms
Register Binding for Predicated Execution in DSP Applications
France-Brazil Cooperative Actions
PTAT CMOS current sources mismatch over temperature
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
Synthesis Tools and Design Environment for Dynamically Reconfigurable FPGAs
A -60dB THD/100MHz true unity-gain voltage buffer CMOS circuit
26th Symposium on Integrated Circuits and Systems Design, SBCCI 2013, Curitiba, Brazil, September 2-6, 2013
Edge AI Dependability: Is Bit-flip Direction the Right Concern in Trustworthiness Reinforcement?
A 24.25-30.5GHz Fully Integrated SiGe Phase Shifter/VGA/Power Amplifier in 0.13µm BiCMOS Technology for 5G Beamforming Applications
Design Landscape of VVC Binary Arithmetic Decoder using Multiple Bypass Bins Processing
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements
Process Variation Sensing and Compensation Employing a Ring Oscillator-Based Architecture in SkyWater 130nm Technology
High PSRR Nano-Watt MOS-Only Threshold Voltage Monitor Circuit
A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change
Area optimization algorithms in high-speed digital FIR filter synthesis
Implementation of Image Averaging on DRRA and DiMArch Architectures
A methodology for tuning two-level cache hierarchy considering energy and performance
Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels
Leakage power optimization in standard-cell designs
Edge GPU based on an FPGA Overlay Architecture using PYNQ
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Advanced power management of SoC platforms
Using a software testing technique to identify registers for partial scan implementation
1.2 nW Neuromorphic Enhanced Wake-Up Radio
High level design: the future is now
Analysis of Representative Critical Path as Delay Line for Bundled-Data Circuits
Silicon-Proven Synchronous and Asynchronous Frequency-to-Digital Converters Using Open-Source EDA Tools
Compression and Technology Mapping of Logic Circuits
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
A 9.78-ENOB 10 MS/s SAR ADC with a Common Mode Compensation Technique in a 28nm CMOS Node
Firefly: An Open-source Rocket-based Intermittent Framework
Development process for MEMS pressure sensors for standarized CMOS read-out circuitry
Solving the I/O Bandwidth Problem in System on a Chip Testing
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures
A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture
A Tool to Design Circuits with Statistics
Design and Simulation of Heterogeneous Embedded Systems
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications
A multi-standard channel-decoder for base-station applications
Parametric Yield Estimation for Deep Sub- Micron VLSI Circuits
Image Steganography Based on Chaotic Systems and Finite-Precision Error
A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique
Study of an Avalanche Compensation Mirror for SiGe High Performance Power Amplifiers Dedicated to 5G Applications
Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs
A Virtual Board Approach for Prototyping and Teaching Digital Design
Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier
Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models
Hardware design for the 32×32 IDCT of the HEVC video coding standard
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
A Management Technique for Concurrent Access to a Reconfigurable Accelerator
Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE)
Characterization and nonlinear modeling of MASMOS ® transistor in order to design power amplifiers for LTE applications
A 65nm VLSI implementation for the LTE turbo decoder
Fault-tolerance in FPGA's through CRC voting
Analysis of single-module and cascade molecular analog circuits for approximate computing based on DNA Strand Displacement
An automatic testbench generation tool for a SystemC functional verification methodology
Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture
Lightweight security mechanisms for MPSoCs
A Universal High-Performance Analog Interface for Signal Processing SOCs
CMOS encoder for scale-independent pattern recognition
Exploring memory organization in virtual MP-SoC platforms
Hardware implementation of a shape recognition algorithm based on invariant moments
Evaluating the impact of task migration in multi-processor systems-on-chip
Latency reduction of fault-tolerant NoCs by employing multiple paths
Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding
Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits
Transistor Reordering for Electrical Improvement in CMOS Complex Gates
A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems
Integrated CMOS class-E power amplifier for self-sustaining wireless power transfer system
38th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, SBCCI 2025, Manaus, Brazil, August 25 - Sept. 1, 2025
A Repartitioning and HW/SW Partitioning Algorithm to the Automatic Design Space Exploration in the Co-Synthesis of Embedded Systems
Comparison between direct and indirect learnings for the digital pre-distortion of concurrent dual-band power amplifiers
Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction
A 0.3 to 5-MHz Low-Voltage Digitally-Controlled Oscillator for Energy Harvesting Applications
Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter
A design methodology for analogue CMOS circuits
Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors
Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection
HARA: Hardware-Aware Resource Allocation for FPGA-Based Neural Network Acceleration
Self-biased CMOS Current Reference based on the ZTC Operation Condition
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools
A 3-V 12-Bit Second Order Sigma-Delta Modulator Design in 0.8µm CMOS
A New Continuous Switching Window Computation with Crosstalk Noise
Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domain
An ultra low-power class-AB sinh integrator
A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip
Circuit Reliability Analysis with Considerations of Aging Effect
A formal software synthesis approach for embedded hard real-time systems
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002
IPNoSys II: A New Architecture for IPNoSys Programming Model
Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits
Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration
Full-chip routing system for reducing Cu CMP & ECP variation
Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV
Analog Circuit Design Using Graded-Channel SOI NMOSFETS
Panel Statement
A Novel Single Propagation Path Multimode PA
Fast and Energy-Efficient 2D Convolution: Inspection-Based Methods for Hardware Acceleration
A Physical Layer Controller for Wireless Infrared Networks
IDCT Design for JPEG Decompression in an Electronic Ballot Box
Disjunctive Decomposition of Switching Functions Using Symmetry Information
Key issues for the design of high power RF amplifiers
EMC-EMI optimized high speed CAN line driver
A resistorless switched bandgap voltage reference with offset cancellation
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process
A partial reconfigurable architecture for controllers based on Petri nets
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing
A concurrent dualband distributed impedance-matching network
Design of a Classification System for Rectangular Shapes Using a Co-Design Environment
Instantaneous de-embedding of the on-wafer equivalent-circuit parameters of acoustic resonator (FBAR) for integrated circuit applications
Early Neutron Reliability Assessment of an Arm Cortex-M4 through Emulated Fault Injection
Advances and trends in FPGA design
Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems
36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1, 2023
Lightweight Machine-Learning-driven Security Threat Detection in NoC-based Manycores
Cell placement on graphics processing units
Automatic layout integration of Bulk Built-In Current Sensors for detection of soft errors
Fault Models and Compact Test Vectors for MOS OpAmp circuits
Miniaturized Sign-Magnitude Stochastic-Binary FIR Filter Architecture with Enhanced Accuracy
Flexible and efficient co-simulation of networked embedded devices
Segmented Precharge Free Content Addressable Memory for Energy Efficiency
FPGA architecture for static background subtraction in real time
Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder
An improved and automated design tool for the optimization of CMOS OTAs using geometric programming
A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution
TrACS: transceiver architecture and wireless channel simulator
Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications
Voltage Regulation System for UHF RFID Tags
Nanotechnology and emerging memories
Synthesis and Optimization of Majority Expressions through a Mathematical Model