yusuke1997/dblp-id-title huggingface dataset:
Optimal Backgrounds Selection for Multi Run Memory Testing
Supporting analog design for reliability by efficient provision of reliability information to designers
Analysis and Mitigation of Soft-errors in GPU-accelerated Hyperspectral Image Classifiers
Early-stage verification of power-management specification in low-power systems design
A Partial Scan Based Test Generation for Asynchronous Circuits
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs
Nonlinear Compression Codes Used In IC Testing
A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS
Self-refreshing Multiple Valued Memory
0.5V 160-MHz 260uW all digital phase-locked loop
Cost effective scaling to 22nm and below technology nodes
Design for three-dimensional sound processor using high-level synthesis
Synthesizing simulators for model checking microcontroller binary code
Communication modelling and synthesis for NoC-based systems with real-time constraints
Generation of non-overlapping clock signals without using a feedback loop
NoCDepend: A Flexible and Scalable Dependability Technique for 3D Networks-on-Chip
A new user-friendly ATPG platform for digital circuits
SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse
Timing-aware ATPG for critical paths with multiple TSVs
A novel method for test and calibration of capacitive accelerometers with a fully electrical setup
A Proposal for ASM++ Diagrams
Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs
The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features
Energy-aware application-specific topology generation for 3D Network-on-Chips
Experience in Virtual Testing of RSD cyclic A/D converters
Architecture Design for the Context Formatter in the H.264/AVC Encoder
Design of Wireless Sensor Network for Real-Time Structural Health Monitoring
Self-timed full adder designs based on hybrid input encoding
High Precision Digital Based 3.8GHz Phase Shifter
HLS design of a hardware accelerator for Homomorphic Encryption
Lightweight benchmarking of platforms for network traffic processing
Fault-Tolerant Reconfigurable Low-Power pseudoRandom number Generator
Application of Evolutionary Algorithms for Regression Suites Optimization
Power-Management Specification in SystemC
Versatile Hardware Framework for Elliptic Curve Cryptography
Fault collapsing of multi-conditional faults
A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013
Redundancy algorithm for embedded memories with block-based architecture
On the in-field test of Branch Prediction Units using the correlated predictor mechanism
Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits
Multistage low ripple charge pump
Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers
Design methodology of configurable high performance packet parser for FPGA
Domain-Specific Design Abstraction with Emphasis on Neural Networks
Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing
VHDLVisualizer: HDL model visualization with simulation-based verification
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies
Establishing a New Course in Reconfigurable Logic System Design
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm
Hardware architecture for packet classification with prefix coloring
Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology
Approximation of Hardware Accelerators driven by Machine-Learning Models : (Embedded Tutorial)
An integrated low power buck converter with a comparator controlled low-side switch
VARMA - VARiability modelling and analysis tool
TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms
The LSI implementation of a memory based field programmable device for MCU peripherals
A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs
IP-based Systematic Design of Power-and Matching-limited Circuits
A New Design Technique for Weakly Indicating Function Blocks
Sequential test decompressors with fast variable wide spreading
Comparative BTI analysis for various sense amplifier designs
HLS-DoNoC: High-level simulator for dynamically organizational NoCs
A Build-In Self-Test technique for RF Mixers
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing
CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector
The design features of low-temperature radiation-hardened instrumentation amplifiers and sensor interfaces
FPGA Implementation of a Fast MDCT Algorithm
On analysis of fabricated polymorphic circuits
EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design
Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications
Characterization of Printed Humidity Sensor Based on Nanoparticle Copper Oxide
An Overview of Oxide Materials for Gas Sensors
Productivity and Code Quality Improvement of Mixed-Signal Test Software by Applying Software Engineering Methods
NetCOPE: Platform for Rapid Development of Network Applications
Analog Circuitry for BLDC Motor Magnetic Saturation Diagnostic
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS
Frequency injection attack on a random number generator
Verification of JPEG2000 encoder based on rate and distortion curve analysis
Equivalence Checking on System Level Using a Priori Knowledge
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing
Gm-C filter with automatic calibration scheme
Bridging Quantization and Deployment: A Fixed-Point Workflow for FPGA Accelerators
HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration
Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking
Safety features of SoCs: How can they be re-used?
Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models
Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network Traffic
LLM-assisted Performance Estimation of Embedded Software on RISC-V Processors
A better-than-worst-case robustness measure
Energy-aware software development for embedded systems in HW/SW co-design
Logic Diagnosis and Yield Learning
Implementation of a real time unit for satellite applications
28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2025, Lyon, France, May 5-7, 2025
Generic Error Localization for the Electronic System Level
Characterization of Interconnect Fault Effects in SRAM-based FPGAs
Hardware Accelerated FrodoKEM on RISC-V
Adaptive Input Normalization for Quantized Neural Networks
Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS
Intrusion Detection System Intended for Multigigabit Networks
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits
Automated synthesis and design-error repair of systems
Self-Adaptive mechanism for cache memory reliability improvement
FPGA architecture for fast floating point matrix inversion using uni-dimensional systolic array based structure
Test vector overlapping based compression tool for narrow test access mechanism
Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties
A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits
Assertion based verification using PSL-like properties in Haskell
Minimization of Large State Spaces using Symbolic Branching Bisimulation
Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering
Low-area boundary BIST architecture for mesh-like network-on-chip
SoC Symbolic Simulation: a case study on delay fault testing
Sample synchronization of multiple multiplexed DA and AD converters in FPGAs
Activity Profiling and Power Estimation for Embedded Wireless Sensor Node Design
Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips
An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs
A general approach for comparing metastable behavior of digital CMOS gates
Power Consumption Analysis of New Generation of Polymorphic Gates
Decoupling capacitance boosting for on-chip resonant supply noise reduction
DEAR-CNN: Data-Efficient Assessment of Resiliency in Convolutional Neural Networks
Microwave Selective Amplifiers with High Asymptotic Attenuation in the Range of Subresonance Frequencies
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023
Multiple-Vector Column-Matching BIST Design Method
Power consumption traces realignment to improve differential power analysis
Capacitive-sensing module with dynamic gesture recognition for automotive applications
KL-cuts influence on optimization of polymorphic circuits based on PAIG rewriting
Proof certificates and non-linear arithmetic constraints
Die Attach Quality Testing by Fully Contact-less Measurement Method
Probabilistic equivalence checking based on high-level decision diagrams
Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition
Efficient Allocation of Verification Resources using Revision History Information
Development of 3D space partitioning and design rule check for smart system solutions
BIST assisted wideband digital compensation for MB-UWB transmitters
Automatic and reliable electrical characterization of MOSFETs
Blind image deconvolution algorithm on NVIDIA CUDA platform
Fault detection and self repair in Hsiao-code FEC circuits
Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization
Study of an OPTO-ASIC for a Functionally Safe Speed Sensor Using the Spatial Frequency Filter Method
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC
Memory optimizations for packet classification algorithms in FPGA
Error recovery technique for coarse-grained reconfigurable architectures
Generic Self Repair Architecture with On-Line Fault Diagnosis
Abstract modeling and simulation based selective estimation
Low-power quadrature VCO design for medical implant communication service
Mapping Trained Neural Networks to FPNNs
A Flexible SoPC-based Fault Injection Environment
Reliable execution of statechart-generated correct embedded software under soft errors
A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology
Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology
Design of stochastic Viterbi decoders for convolutional codes
Fault-based attacks on cryptographic hardware
A Reliability-aware Environment for Design Exploration for GPU Devices
A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency Divider
Generation and Propagation of Single Event Transients in CMOS Circuits
Debugging HDL designs based on functional equivalences with high-level specifications
Fast congestion-aware timing-driven placement for island FPGA
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
FPGA-based SIFT implementation for wearable computing
Defect-oriented module-level fault diagnosis in digital circuits
A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0
The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies
A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope
Case study: BISR for a processor multiplier
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties
Duality and resonance in RLC-circuits. Exact formulas for phase, amplitude resonance and bandwidth
Efficient Neural Network Approximation via Bayesian Reasoning
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling
A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates
A low jitter delay-locked-loop applied for DDR4
A Cost Effective BIST Second-Order Sigma-Delta-Modulator
A temperature compensated MOSFET-C band-pass filter in 0.35 um CMOS technology
Extensible open-source framework for translating RTL VHDL IP cores to SystemC
Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications
A three-dimensional DRAM using floating body cell in FDSOI devices
An approach towards selection of the oscillation frequency for oscillation test of analog ICs
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips
Advanced fault tolerant bus for multicore system implemented in FPGA
A Rare Event Based Yield Estimation Methodology for Analog Circuits
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing
Integrated Sensors for Early Breast Cancer Diagnostics
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology
An indirect technique for estimating reliability of analog and mixed-signal systems during operational life
2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique
SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design
Stabilization methods for integrated high voltage charge pumps
Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design
Design of In AlN/GaN Heterostructure-Based Logic Cells
Genetic method for compressed skewed-load delay test generation
Tree-model based mapping for energy-efficient and low-latency Network-on-Chip
Multi-objective BDD optimization for RRAM based circuit design
CDMA technique for Network-on-Chip
Hardware architecture for the fast pattern matching
RL-Agent-based Early-Exit DNN Architecture Search Framework
Power devices current monitoring using horizontal and vertical magnetic force sensor
A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded System
An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform
Automated simulation-based verification of power requirements for Systems-on-Chips
Fast lookup for dynamic packet filtering in FPGA
NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures
Small scale energy harvesting - principles, practices and future trends
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430
Wireless Heart Rate Monitor in Personal Emergency Response System
Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts
Emerging Technologies: Challenges and Opportunities for Logic Synthesis
A deterministic approach for hardware fault injection in asynchronous QDI logic
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS
HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package
On the in-field test of the GPGPU scheduler memory
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata
Lissajous Based Mixed-Signal Testing for N-Observable Signals
Evolutionary circuit design: Tutorial
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories
Formal verification meets robustness checking - Techniques and challenges
Improving the iterative power of resynthesis
Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter
Fault tolerance of SRAM-based FPGA via configuration frames
Analyzing Multilevel Stochastic Circuits using Correlation Matrices
Multiple Valued Counter
Feasibility of Image Compression in FPGA-based Neural Networks
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints
A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations
Requirement Phrasing Assistance Using Automatic Quality Assessment
Calculation of LFSR Seed and Polynomial Pair for BIST Applications
Utilizing the Bulk-driven technique in analog circuit design
Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes
SAT-based analysis of sensitisable paths
Triangular Modulation Using Switched-Capacitor Scheme for Spread-Spectrum Clocking
Low-voltage indoor energy harvesting using photovoltaic cell
Exploration of the FlexRay signal integrity using a combined prototyping and simulation approach
Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits
Approximate computing for energy-efficient error-resilient multimedia systems
Introduction to the SystemC AMS extension standard
Xoodyak Under SCA Siege
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules
Modeling the Coupling through Substrate for Frequencies up to 100GHz
Nonlinear Binary Codes and Their Utilization for Test
A low supply voltage synchronous mirror delay with quadrature phase output
A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic
Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines
Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits
Receiver OEIC using a bipolar translinear loop
Exploring processor parallelism: Estimation methods and optimization strategies
PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog IC
Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits
Current sensing methodology for completion detection in self-timed systems
BTI impact on logical gates in nano-scale CMOS technology
A GHz full-division-range programmable divider with output duty-cycle improved
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions
A ML-Based Approach for Finding the Product Definition Space of Microelectronic Power Switches
Built in Defect Prognosis for Embedded Memories
Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology
A Methodology to Verify Digital IP's within Mixed-Signal Systems
Evolutionary design of approximate multipliers under different error metrics
Multisine signal generation method for a bioimpedance measurement device
Encryption-Based Secure JTAG
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits
On the use of assertions for embedded-software dynamic verification
Cumulative embedded memory failure bitmap display & analysis
An effective approach for functional test programs compaction
Combining Correction of Delay Faults and Transient Faults
Emulation based fault injection on UHF RFID transponder
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications
Efficient digital design for automotive mixed-signal ASICs using simulink
Automatic generation of input-aware approximate arithmetic circuits
Interpolation-based model checking for efficient incremental analysis of software
Combining de-stressing and self repair for long-term dependable systems
SiGe BiCMOS platform - baseline technology for More Than Moore process module integration
Design of Erasure Codes for Digital Multimedia Transmitting
Using Voters May Lead to Secret Leakage
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications
Approximate Multipliers for Optimal Utilization of FPGA Resources
Various MDCT implementations in 0.35µm CMOS
An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA
Design - Time configurable processor basic structure
Rocket Queue: New data sorting architecture for real-time systems
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems
Automated SEU fault emulation using partial FPGA reconfiguration
Ultra low-voltage switched current mirror
Reconfigurable hardware objects for image processing on FPGAs
FPGA design of the computation unit for the semi-global stereo matching algorithm
Fault management in an IEEE P1687 (IJTAG) environment
Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
The novel approach to wideband RFIC receivers in standard CMOS process
Active Wire Fences for Multitenant FPGAs
A CMOS bio-impedance measurement system
A 50 GHz SiGe BiCMOS active bandpass filter
Tutorial: Silicon Systems for Wireless LAN
Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistors
23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2020, Novi Sad, Serbia, April 22-24, 2020
System-level reliability evaluation through cache-aware software-based fault injection
10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology
Probabilistic Model Checking and Reliability of Results
Case Study : A class E power amplifier for ISO-14443A
Optimised AES with RISC-V Vector Extensions
Instance Generation for SAT-based ATPG
2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, Slovakia, April 20-22, 2016
A 3-5GHz UWB CMOS receiver with digital control technique
Comparison of gate-driven and bulk-driven current mirror topologies
An Improved MDCT IP Core Generator with Architectural Model Simulation
Synthesizing multiplier in reversible logic
Using Control Logic Drivers for Automated Generation of System-level Portable Models
S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs
AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems
Effective RT-level software-based self-testing of embedded processor cores
Reduction of power dissipation through parallel optimization of test vector and scan register sequences
Hardware/Software Based Hierarchical Self Test for SoCs
A mixed domain sizing approach for RF circuit synthesis
Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routing
Test Pattern Generator for Delay Faults
Reticle Exposure Plans for Multi-Project Wafers
21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018
Low power voltage sensing through capacitance to digital conversion
SiP design flow and 3D DRC for MEMS
A chaos-based pseudo-random bit generator implemented in FPGA device
Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections
Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes
A Security Verification Template to Assess Cache Architecture Vulnerabilities
MTPP - Modular Traffic Processing Platform
Optimised Power Supply Unit Design
A scalable technique to identify true critical paths in sequential circuits
3D integration: Opportunities, design challenges and approaches
Indoor energy harvesting using photovoltaic cell for battery recharging
ISA Based Functional Test Generation with Application to Self-Test of RISC Processors