yusuke1997/dblp-id-title huggingface dataset:
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs
Cached-code compression for energy minimization in embedded processors
An automated framework for generating variable-accuracy battery models from datasheet information
Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
A charge pump based receiver circuit for voltage scaled interconnect
Reducing cache traffic and energy with macro data load
Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers
Designing power efficient hypermedia processors
Interconnect synthesis of heterogeneous accelerators in a shared memory architecture
A micro power management system and maximum output power control for solar energy harvesting applications
Terahertz Technology and its Applications: Is it All Hype?
QPR.js: a runtime framework for QoS-aware power optimization for parallel JavaScript programs
Power estimation for mobile applications with profile-driven battery traces
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Monitoring system activity for OS-directed dynamic power management
Empirically derived abstractions in uncore power modeling for a server-class processor chip
An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning
A win-win camera: Quality-enhanced power-saving images on mobile OLED displays
Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design
Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits
The design of a low energy FPGA
SAOU: safe adaptive overclocking and undervolting for energy-efficient GPU computing
Power optimization in a repeater-inserted interconnect via geometric programming
Micro-operation cache: a power aware frontend for the variable instruction length ISA
A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications
End-to-end validation of architectural power models
CHARM: a composable heterogeneous accelerator-rich microprocessor
Future of on-chip interconnection architectures
Preemption-aware dynamic voltage scaling in hard real-time systems
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
Dynamic virtual ground voltage estimation for power gating
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators
T-DVS: Temperature-aware DVS based on Temperature Inversion Phenomenon
Approaches to run-time and standby mode leakage reduction in global buses
Statistical estimation of leakage current considering inter- and intra-die process variation
A new algorithm for improved VDD assignment in low power dual VDD systems
TONE: adaptive temperature optimization for the next generation video encoders
Load-Triggered Warp Approximation on GPU
Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
CNN-Based Camera-less User Attention Detection for Smartphone Power Management
Automated di/dt stressmark generation for microprocessor power delivery networks
Re-mapping for low power under tight timing constraints
Efficient query processing in crossbar memory
Level conversion for dual-supply systems
A CMOS even harmonic mixer with current reuse for low power applications
Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices
Low-power fanout optimization using multiple threshold voltage inverters
Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC
Digital Implementation of On-Chip Hebbian Learning for Oscillatory Neural Network
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation
Low power systems for wireless microsensors
Advanced power and thermal management for low-power, high-performance smartphones
An Automated Approximation Methodology for Arithmetic Circuits
Enabling DVFS Side-Channel Attacks for Neural Network Fingerprinting in Edge Inference Services
Low-power micromachined microsystems (invited talk)
Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor
Low power requirements for future digital life style
Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers
ACME: An Energy-Efficient Approximate Bus Encoding for I 2 C
Emerging power management tools for processor design
Synergistic temperature and energy management in GALS processor architectures
Wireless Power Transfer And Data Communication For Low-Power Micro Electronic Devices Deeply Implanted Within The Human Body
Heterogeneous Memory Integration and Optimization for Energy-Efficient Multi-Task NLP Edge Inference
Compiler support for block buffering
A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices
Reducing display power consumption for real-time video calls on mobile devices
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip
Temporal codes in on-chip interconnects
Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC
A low-power VLSI architecture for turbo decoding
Register file write data gating techniques and break-even analysis model
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Leap frog multiplier
Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems
Machine Learning Driven Synthesis of Clock Gating
Synthesis of low-power asynchronous circuits in a specified environment
Evolution of low power electronics and its future applications
Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors
Advances in low power verification
A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor
A programmable power-efficient decimation filter for software radios
Efficient techniques for gate leakage estimation
Commercial low-power EDA tools: a review
Region-level approximate computation reuse for power reduction in multimedia applications
Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer Computation
An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications
Power-optimal encoding for DRAM address bus (poster session)
DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations
Variability-aware device optimization under I ON and leakage current constraints
Inverse polarity techniques for high-speed/low-power multipliers
Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator
A low power unified cache architecture providing power and performance flexibility (poster session)
RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit
Low power soft-output signal detector design for wireless MIMO communication systems
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
N-version temperature-aware scheduling and binding
FPGA-based Acceleration of Binary Neural Network Training with Minimized Off-Chip Memory Access
Approximate compressed sensing: ultra-low power biosignal processing via aggressive voltage scaling on a hybrid memory multi-core processor
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines
Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS
Low-power fixed-width array multipliers
Advances in ultrabook™ platform power management
On reducing energy-consumption by late-inserting instructions into the issue queue
Nanotechnology for low-power and high-speed nanoelectronics applications
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
Evaluation of voltage stacking for near-threshold multicore computing
Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures
Circuit techniques for low-power CMOS GSI
3D super chip technology to achieve low-power and high-performance system-on-a chip
GAS: A Heterogeneous Memory Architecture for Graph Processing
Understanding the energy efficiency of SMT and CMP with multiclustering
Supply and threshold voltage optimization for low power design
Two efficient methods to reduce power and testing time
A software approach for combating asymmetries of non-volatile memories
Design trade-offs for high density cross-point resistive memory
NS-KWS: joint optimization of near-sensor processing architecture and low-precision GRU for always-on keyword spotting
Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps
Substrate noise influence on circuit performance in variable threshold-voltage scheme
Energy efficient proactive thermal management in memory subsystem
Low-power H.263 video CoDec dedicated to mobile computing
Integrated DC/DC converter with digital controller
SOI, interconnect, package, and mainboard thermal characterization
Analysis and optimization of CMOS switched-capacitor converters
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015, Rome, Italy, July 22-24, 2015
Reducing display power in DVS-enabled handheld systems
FinFET-based SRAM design
Technology and design challenges for mobile communication and computing products
Energy harvesting by sweeping voltage-escalated charging of a reconfigurable supercapacitor array
A Flash-Based Multi-Bit Content-Addressable Memory with Euclidean Squared Distance
A 65-nm pulsed latch with a single clocked transistor
Learning from Output Transitions: A Chosen Challenge Strategy for ML Attacks on PUFs
Hybrid approximate multiplier architectures for improved power-accuracy trade-offs
Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection
Wireless beyond the third generation wireless beyond the third generation: facing the energy challenge
A 2.6 µW sub-threshold mixed-signal ECG SoC
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors
Overview of IEEE1801-2015: Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems: Invited Paper
Managing standby and active mode leakage power in deep sub-micron design
High-level power estimation and the area complexity of Boolean functions
Power-aware source routing protocol for mobile ad hoc networks
RecPIM: A PIM-Enabled DRAM-RRAM Hybrid Memory System For Recommendation Models
Why hot chips are no longer "cool"
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits
Efficient Multi-Objective Optimization for PVT Variation-Aware Circuit Sizing Using Surrogate Models and Smart Corner Sampling
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003
Optimizing sensor movement planning for energy efficiency
Time-to-failure estimation for batteries in portable electronic systems
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Power management in energy harvesting embedded systems with discrete service levels
Runtime identification of microprocessor energy saving opportunities
Hierarchical power management with application to scheduling
Power Delivery Resonant Virus: Concept and Applications
An energy-delay efficient 2-level data cache architecture for embedded system
Energy efficient strategies for deployment of a two-level wireless sensor network
A 225 MHz resonant clocked ASIC chip
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology
On-chip detection methodology for break-even time of power gated function units
Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Global register allocation for minimizing energy consumption
Xyloni: Very Low Power Neural Network Accelerator for Intermittent Remote Visual Detection of Wildfire and Beyond
Energy characterization and instruction-level energy model of Intel's Xeon Phi processor
FPRA: A Fine-grained Parallel RRAM Architecture
Green high performance storage class memory & NAND flash memory hybrid SSD system
Towards a high-level power estimation capability
Memristor-based approximated computation
Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator
A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications
Local Learning in RRAM Neural Networks with Sparse Direct Feedback Alignment
The logarithmic number system for strength reduction in adaptive filtering
Constant-load energy recovery memory for efficient high-speed operation
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM
Wakeup synthesis and its buffered tree construction for power gating circuit designs
Power-aware partitioned cache architectures
DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing
PACT: Accurate Power Analysis and Carbon Emission Tracking for Sustainability
Gate-level synthesis for low-power using new transformations
A 1.2-V, 1.8-GHz low-power PLL using a class-F VCO for driving 900-MHz SRD band SC-circuits
Update rate tradeoffs for improving online power modeling in smartphones
Adaptive on-chip power supply with robust one-cycle control technique
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
Battery-Aware Energy Model of Drone Delivery Tasks
The design of a bloom filter hardware accelerator for ultra low power systems
High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control
Design and power management of energy harvesting embedded systems
Energy efficient scheduling for web search on heterogeneous microservers
Asymmetric-frequency clustering: a power-aware back-end for high-performance processors
Coordinated, distributed, formal energy management of chip multiprocessors
FVCAG: A framework for formal verification driven power modeling and verification
Reducing power consumption of turbo code decoder using adaptive iteration with variable supply voltage
A 386-μW, 15.2-bit Programmable-Gain Embedded Delta-Sigma ADC for Sensor Applications
An energy-efficient 5-MHz to 20-MHz, 12-bit reconfigurable continuous-time ΣΔ modulator for 4G-LTE application
A Pulse-Width Modulated Cochlear Implant Interface Electronics with 513 µW Power Consumption
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications
Co-Designing Hardware and Models for Efficient On-Device ML Inference
Low power architecture of the soft-output Viterbi algorithm
Frequency planning for multi-core processors under thermal constraints
AdaGray: An Energy-Efficient Adaptive Gray-Code Strategy for QLC Flash-Memory Storage Systems
Energy-efficient pass-transistor-logic using decision feedback equalization
Holistic approach to low-power system design
A practical low-power memristor-based analog neural branch predictor
A memory rename table to reduce energy and improve performance
Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source
Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings
Elements of low power design for integrated systems
A case for efficient accelerator design space exploration via Bayesian optimization
Keynote: A new Silicon Age 4.0: Generating semiconductor-intelligence paradigm with a Virtual Moore's Law Economics and Heterogeneous technologies
System-level power optimization of special purpose applications: the beach solution
Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs
On the interaction of power distribution network with substrate
Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation
Repurpose Accel-Sim for Next Generation NVIDIA Jetson GPU Architectural Design
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches
Towards a green electronic world: a collaborative approach
EcoLaser: an adaptive laser control for energy-efficient on-chip photonic interconnects
Low-power high-accuracy timing systems for efficient duty cycling
Dynamic thermal clock skew compensation using tunable delay buffers
Variable voltage task scheduling algorithms for minimizing energy
Time-step interleaved weight reuse for LSTM neural network computing
Behavior-level observability don't-cares and application to low-power behavioral synthesis
VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs
Fan-speed-aware scheduling of data intensive jobs
Enabling energy efficient Hybrid Memory Cube systems with erasure codes
Low Power Logic Obfuscation Through System Level Clock Gating
Instruction packing: reducing power and delay of the dynamic scheduling logic
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
SocialHBC: Social Networking and Secure Authentication using Interference-Robust Human Body Communication
A 98 GMACs/W 32-core vector processor in 65nm CMOS
A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study
Power reduction in an H.264 encoder through algorithmic and logic transformations
Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET
Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities
Variation tolerant design of a vector processor for recognition, mining and synthesis
Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor
Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling
Low-power technology mapping for mixed-swing logic
An Instruction-Level Power and Energy Model for the Rocket Chip Generator
A power and resolution adaptive flash analog-to-digital converter
Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper
Minimizing power dissipation during write operation to register files
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node
Active mode leakage reduction using fine-grained forward body biasing strategy
REFROM: Responsive, Energy-Efficient Frame Rendering for Mobile Devices
SceneMan: Bridging mobile apps with system energy manager via scenario notification
Explicit evaluation of short circuit power dissipation for CMOS logic structures
Frequency and yield optimization using power gates in power-constrained designs
DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing
A 16nm Heterogeneous Accelerator for Energy-Efficient Sparse and Dense AI Computing
Sustainably Secure: ChaCha20 Encryption Based on In-Memory Compute
Tutorial: Tiny light-harvesting photovoltaic charger-supplies
Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories
BiasP: a DVFS based exploit to undermine resource allocation fairness in linux platforms
Fast photovoltaic array reconfiguration for partial solar powered vehicles
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement
Efficient thermoelectric cooling for mobile devices
Voltage scheduling in the IpARM microprocessor system
Fast configurable-cache tuning with a unified second-level cache
Energy recovering static memory
Energy minimization with guaranteed quality of service
Tiguan: Energy-aware collision-free control for large-scale connected vehicles
A multi-story power delivery technique for 3D integrated circuits
iSPADE: End-to-end Sparse Architecture for Dense DNN Acceleration via Inverted-bit Representation
Power management solutions for computer systems and datacenters
DIRC-RAG: Accelerating Edge RAG with Robust High-Density and High-Loading-Bandwidth Digital In-ReRAM Computation
Analysis and design of ultra low power thermoelectric energy harvesting systems
Revisiting Reconfigurable Acceleration of Vision Transformer with Patch Pruning
Node normalization and decomposition in low power technology mapping
TFET-based cellular neural network architectures
Swan: a two-step power management for distributed search engines
Compilers for power and energy management
Thinking outside the box: power management at the system level & beyond
Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation
PowerAntz: distributed power sharing strategy for network on chip
Clocking structures and power analysis for nanomagnet-based logic devices
Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques
Green transistors to green architectures
Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs
Workload-driven frequency-aware battery sizing
Design and implementation of correlating caches
Rapid Hardware/Software Design Space Exploration for Efficient Intermittent Systems
A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes
Dynamic backlight scaling optimization for mobile streaming applications
MEbots: Integrating a RISC-V Virtual Platform with a Robotic Simulator for Energy-aware Design
High-level area estimation
A history-based I-cache for low-energy multimedia applications
Statistical static timing analysis considering leakage variability in power gated designs
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering
Energy efficient near-threshold chip multi-processing
Keynote: Architecture and software for emerging low-power systems
Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference
Frequency governors for cloud database OLTP workloads
Power-aware scheduling of conditional task graphs in real-time multiprocessor systems
A novel power optimization technique for ultra-low power RFICs
Energy-efficient renaming with register versioning
Dynamic workload characterization for power efficient scheduling on CMP systems
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
Timing errors in LDPC decoding computations with overscaled supply voltage
Software canaries: software-based path delay fault testing for variation-aware energy-efficient design