yusuke1997/dblp-id-title huggingface dataset:
Restructuring field layouts for embedded memory systems
Sufficient real-time analysis for an engine control unit with constant angular velocities
LRP: Predictive output activation based on SVD approach for CNN s acceleration
High-Efficiency FPGA - Based Approximate Multipliers with LUT Sharing and Carry Switching
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Implementation of a linear histogram BIST for ADCs
Time-Domain 3D Electromagnetic Fields Estimation Based on Physics-Informed Deep Learning Framework
OPACT: Optimization of Approximate Compressor Tree for Approximate Multiplier
Using UML as Front-end for Heterogeneous Software Code Generation Strategies
Yield-aware placement optimization
A Low Device Occupation IP to Implement Rijndael Algorithm
Energy minimization for fault tolerant scheduling of periodic fixed-priority applications on multiprocessor platforms
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator
OTFGEncoder - HDC: Hardware-efficient Encoding Techniques for Hyperdimensional Computing
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access
FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks
IC Design Challenges for Ambient Intelligence
Exploration of hardware sharing for image encoders
Timing Debugging for Cyber-Physical Systems
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Using High-Level Synthesis to model System Verilog procedural timing controls
Highly efficient and accurate seizure prediction on constrained IoT devices
A scan-chain based state retention methodology for IoT processors operating on intermittent energy
Statistical fault injection: Quantified error and confidence
Low-Cost Software-Based Self-Testing of RISC Processor Cores
Panel: Looking backwards and forwards
Mappability Estimation of Architecture and Algorithm
Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor
Microfluidic Trojan Design in Flow-based Biochips
Transistor Aging and Circuit Reliability at Cryogenic Temperatures
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach
Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators
Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs
A Synthesizable Thyristor-Like Leakage-Based True Random Number Generator
Energy efficient data flow transformation for Givens Rotation based QR Decomposition
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster
Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling
Approximation through logic isolation for the design of quality configurable circuits
Design of Many-Core Big Little µBrains for Energy-Efficient Embedded Neuromorphic Computing
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling
Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA
Model-Driven Feature Engineering for Data-Driven Battery SOH Model
Resynchronization of Cyclo-Static Dataflow graphs
Region-based Flash Caching with Joint Latency and Lifetime Optimization in Hybrid SMR Storage Systems
Model-based development of in-vehicle software
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation
Sizing Rules for Bipolar Analog Circuit Design
Modeling steep slope devices: From circuits to architectures
Big-data streaming applications scheduling with online learning and concept drift detection
Verification of networked Labs-on-Chip architectures
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV
A slack-based approach to efficiently deploy radix 8 booth multipliers
Bootstrapped full-swing CMOS driver for low supply voltage operation
XST: A Crossbar Column-wise Sparse Training for Efficient Continual Learning
Exploiting transistor-level reconfiguration to optimize combinational circuits
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules
Highly efficient reconfigurable parallel graph cuts for embedded vision
Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design
Power aware microarchitecture resource scaling
Clock-frequency assignment for multiple clock domain systems-on-a-chip
A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS
Scratchpad Memories with Ownership
A symbolic core approach to the formal verification of integrated mixed-mode applications
Design of an efficient ready queue for earliest-deadline-first (EDF) scheduler
Multi/many-core programming: where are we standing?
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level
Power-accuracy tradeoffs in human activity transition detection
Improvements to boolean resynthesis
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors
Abstraction from Counters: An Application on Real-Time Systems
Circuits for Measurement Based Quantum State Preparation
Opportunistic Communication with Latency Guarantees for Intermittently-Powered Devices
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits
Design, Implementation and Validation of NSCP: A New Secure Channel Protocol for Hardened IoT
Back to the Future: Reversible Runtime Neural Network Pruning for Safe Autonomous Systems
What lies between design intent coverage and model checking?
An area-efficient network interface for a TDM-based network-on-chip
Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition
Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors
Compositional system-level design exploration with planning of high-level synthesis
DNFA: Differential No-Fault Analysis of Bit Permutation Based Ciphers Assisted by Side-Channel
Delay management for programmable video signal processors
A Video Compression Case Study on a Reconfigurable VLIW Architecture
Hierarchical propagation of geometric constraints for full-custom physical design of ICs
Polar Code Decoder Framework
DACO: Pursuing Ultra-low Power Consumption via DNN-Adaptive CPU-GPU CO-optimization on Mobile Devices
Decoupled Access-Execute Enabled DVFS for TinyML Deployments on STM32 Microcontrollers
Fault grading of software-based self-test procedures for dependable automotive applications
Direct Conversion Pulsed UWB Transceiver Architecture
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis
DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs
SMT-Based Repairing Real-Time Task Specifications
A RDMA Interface for Ultra-Fast Ultrasound Data-Streaming over an Optical Link
Generalized Posynomial Performance Modeling
GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator
A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk
Transaction Parameterized Dataflow: A model for context-dependent streaming applications
Formal Methods for High Integrity GPU Software Development and Verification
Gated Clock Routing Minimizing the Switched Capacitance
Adaptive power allocation for many-core systems inspired from multiagent auction model
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Test cost reduction for SoC using a combined approach to test data compression and test scheduling
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC
Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion
A Lightweight CNN for Real-Time Pre-Impact Fall Detection
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective
Panel Session - The Future Car: Technology, Methods and Tools
A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems
Late Breaking Results: Dynamically Scalable Pruning for Transformer-Based Large Language Models
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
Generating and Predicting Output Perturbations in Image Segmenters
A transprecision floating-point platform for ultra-low power computing
JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
A containerized ROS-compliant verification environment for robotic systems
Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach
System integration - The bridge between More than Moore and More Moore
A new distributed event-driven gate-level HDL simulation by accurate prediction
Increasing the efficiency of syndrome coding for PUFs with helper data compression
SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture
TRJM: a high speed programmable ATM-SDH mapper
Using dynamic compilation for continuing execution under reduced memory availability
When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing
Qalitative and Quantitative Analysis of IC Designs
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy
The engineering challenges in quantum computing
Improved Approximation Bounds for the Group Steiner Problem
GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks
Control Circuit Templates for Asynchronous Bundled-Data Pipelines
Data-Aware Cache Management for Graph Analytics
Leveraging aging effect to improve SRAM-based true random number generators
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
Statistical timing analysis with path reconvergence and spatial correlations
Parallel subdivision surface rendering and animation on the Cell BE processor
Parallelization of while loops in nested loop programs for shared-memory multiprocessor systems
WCRT algebra and interfaces for esterel-style synchronous processing
Electronic system design methodology: Europe's positioning
Constructive Analysis of Cyclic Circuits
Constraints Space Management for the Layout of Analog IC's
Leveraging on-chip networks for efficient prediction on multicore coherence
Delay-Insensitive Interface Specification and Synthesis
Image analytics and machine learning for in-situ defects detection in Additive Manufacturing
Software-friendly HW/SW co-simulation: an industrial case study
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification
Priority based forced requeue to reduce worst-case latencies for bursty traffic
DeepNVM: A Framework for Modeling and Analysis of Non-Volatile Memory Technologies for Deep Learning Applications
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions
A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays
Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs
BOMP- NAS: Bayesian Optimization Mixed Precision NAS
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization
Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect
Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms
TAS: Ternarized Neural Architecture Search for Resource-Constrained Edge Devices
Task-accurate performance modeling in SystemC for real-time multi-processor architectures
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
Using guided local search for adaptive resource reservation in large-scale embedded systems
Neuron Fault Tolerance in Spiking Neural Networks
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding
Extending memory capacity of neural associative memory based on recursive synaptic bit reuse
DRAM-Locker: A General-Purpose DRAM Protection Mechanism Against Adversarial DNN Weight Attacks
Interactive presentation: Statistical simulation of high-frequency bipolar circuits
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling
Compromising FPGA SoCs using malicious hardware blocks
EDA solutions to new-defect detection in advanced process technologies
Scalable packet classification via GPU metaprogramming
PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems
Examining and Mitigating the Impact of Crossbar Non-idealities for Accurate Implementation of Sparse Deep Neural Networks
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
MegaRoute: Universal Automated Large-Scale PCB Routing Method with Adaptive Step-Size Search
Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H -Si $(100)-2\times 1$ Surface
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Hybrid source-level simulation of data caches using abstract cache models
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Physically clustered forward body biasing for variability compensation in nanometer CMOS design
Interfacing to living cells
Bias Temperature Instability analysis of FinFET based SRAM cells
Formal performance analysis and simulation of UML/SysML models for ESL design
A design for failure analysis (DFFA) technique to ensure incorruptible signatures
Leveraging Bayesian Optimization to Speed Up Automatic Precision Tuning
ERASMUS: Efficient remote attestation via self-measurement for unattended settings
MCjammer: Adaptive Verification for Multi-core Designs
An effective multi-source energy harvester for low power applications
Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator
AnalogRouter: a new approach of current-driven routing for analog circuits
Scalable fault localization for SystemC TLM designs
Measurement of IP Qualification Costs and Benefits
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system
Analog layout synthesis - Recent advances in topological approaches
Optimizing temperature guardbands
Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP
Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation
GRAMC: General-Purpose and Reconfigurable Analog Matrix Computing Architecture
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters
Synchronization Processor Synthesis for Latency Insensitive Systems
Printed Stochastic Computing Neural Networks
Register transfer level information flow tracking for provably secure hardware design
Multi-Partner Project: BIM-Powered Environmental Data Agent for More Resilient and Trustworthy Data Centers
A Binary Learning Framework for Hyperdimensional Computing
Automatic Scalable System for the Coverage-Directed Generation (CDG) Problem
Computing robustness of FlexRay schedules to uncertainties in design parameters
A Configurable Approximate Multiplier for CNNs Using Partial Product Speculation
Efficient synthesis of approximate threshold logic circuits with an error rate guarantee
INFORMER: An integrated framework for early-stage memory robustness analysis
An adaptive algorithm for low-power streaming multimedia processing
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
Trace signal selection for visibility enhancement in post-silicon validation
ARS: Reducing F2FS Fragmentation for Smartphones using Decision Trees
RON: An on-chip ring oscillator network for hardware Trojan detection
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies
Gate sizing for large cell-based designs
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models
3D FPGA using high-density interconnect Monolithic Integration
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics
A semi-canonical form for sequential AIGs
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems
Dynamic Faults based Hardware Trojan Design in STT-MRAM
FSMD Functional Partitioning for Low Power
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes
ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks
Modeling Silicon-Photonic Neural Networks under Uncertainties
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips
DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
A Hardware Accelerated Autoencoder for RF Communication Using Short-Time-Fourier- Transform Assisted Convolutional Neural Network
Built-in generation of functional broadside tests
RECORD: Reducing register traffic for checkpointing in embedded processors
A probabilistic analysis method for functional qualification under Mutation Analysis
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
A balanced multilevel decomposition method
NBTI Lifetime Evaluation and Extension in Instruction Caches
Automotive V2X on phones: Enabling next-generation mobile ITS apps
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths
A scan pattern debugger for partial scan industrial designs
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking
Quantifying Trade-Offs in Power, Performance, Area, and Total Carbon Footprint of Future Three-Dimensional Integrated Computing Systems
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling
Practical Implementation of a Network Analyzer for Analog BIST Applications
Slicing tree is a complete floorplan representation
New methods and coverage metrics for functional verification
Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture Using Spiking Neural Network
Structural Testing on Real Boards
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations
Theoretical and practical aspects of verification of quantum computers
Two approaches for developing generic components in VHDL
Memory Arbitration and Cache Management in Stream-Based Systems
DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture
Distributed reinforcement learning for power limited many-core system performance optimization
Harnessing ML Privacy by Design Through Crossbar Array Non-Idealities
ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip
Make it real: Effective floating-point reasoning via exact arithmetic
A static power estimation methodolodgy for IP-based design
Intuitive ECO synthesis for high performance circuits
Power analysis of mobile 3D graphics
Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis
A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs
Improving Address Translation in Tagless DRAM Cache by Caching PTE Pages
Program error rate-based wear leveling for NAND flash memory
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
FPGA-Based Implementation of a Serial RSA Processor
Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming
pTest: An adaptive testing tool for concurrent software on embedded multicore processors
Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs
PPS: a pipeline path-based scheduler
Integer Unit-Based Outlier-Aware LLM Accelerator Preserving Numerical Accuracy of FP-FP GEMM
SmartMap: Architecture-Agnostic CGRA Mapping Using Graph Traversal and Reinforcement Learning
Template schedule construction for global real-time scheduling on unrelated multiprocessor platforms
A compositional approach using Keras for neural networks in real-time systems
Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples
Prediction of Thermal Hazards in a Real Datacenter Room Using Temporal Convolutional Networks
A new approximate adder with low relative error and correct sign calculation
Swift-Sim: A Modular and Hybrid GPU Architecture Simulation Framework
Automatic detection of concurrency bugs through event ordering constraints
Evaluating impact of human errors on the availability of data storage systems
Using the inter- and intra-switch regularity in NoC switch testing
Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals
40Gbps de-layered silicon protocol engine for TCP record
A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator
CADE: Configurable Approximate Divider for Energy Efficiency
Fault clustering technique for 3D memory BISR
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs
A methodology for propagating design tolerances to shape tolerances for use in manufacturing
Understanding and Mitigating Memory Interference in FPGA-based HeSoCs
Playing games with scenario- and resource-aware SDF graphs through policy iteration
IIR filters using stochastic arithmetic
Built-in self test architectures for multistage interconnection networks
BlastFunction: an FPGA-as-a-Service system for Accelerated Serverless Computing
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs
Synthesis for Mixed CMOS/PTl Logic
Simulation based tuning of system specification
Exploring non-volatile main memory architectures for handheld devices
Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach