yusuke1997/dblp-id-title huggingface dataset:
Value Prediction for Speculative Multithreaded Architectures
System-Level Analysis of Network Interfaces for Hierarchical MPSoCs
MANIC: A Vector-Dataflow Architecture for Ultra-Low-Power Embedded Systems
Software tools used in the development of a VLSI VAX Microcomputer
Macro-op Scheduling: Relaxing Scheduling Loop Constraints
Better Global Scheduling Using Path Profiles
Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
ISPMET: a study in automatic emulator generation
Can Program Profiling Support Value Prediction?
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment
Improving Address Translation in Multi-GPUs via Sharing and Spilling aware TLB Design
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
Your hardware is all wired up!: attacking network-on-chips via crosstalk channel
An efficient architecture for loop based data preloading
An interactive diagnostic/debugging subsystem for bit-slice processors
Acamar: A Dynamically Reconfigurable Scientific Computing Accelerator for Robust Convergence and Minimal Resource Underutilization
Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane
Microarchitectural support for precomputation microthreads
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
Using branch handling hardware to support profile-driven optimization
Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential
Reduced code size modulo scheduling in the absence of hardware support
A customized control store design in microprogrammed control units
DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification
Co-designing accelerators and SoC interfaces using gem5-Aladdin
Rethinking Memory System Design (along with Interconnects)
Code Duplication: An Assist for Global Instruction Scheduling
ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation
HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
A patch memory system for image processing and computer vision
DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management
Genetic Algorithms and Instruction Scheduling
A non-deterministic scheduler for a software pipelining compiler
CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping
A memory management unit and cache controller for the MARS system
Virtual circuit switch based orderly delivery of packets in adaptive NoC routing
A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
Improving Branch Predictors by Correlating on Data Values
ACRE: Accelerating Random Forests for Explainability
Spill-free parallel scheduling of basic blocks
The design of an interactive compiler for optimizing microprograms
Fractal Coherence: Scalably Verifiable Cache Coherence
Capstan: A Vector RDA for Sparsity
Reconfigurable energy efficient near threshold cache architectures
The heuristic synthesis of applications-oriented microcode
ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer
The role of software tools in the development of the ECLIPSE® MV/8000 microcode
Architecture and Programming of a VLIW Style Programmable Video Signal Processor
Lessons Learned from Blockchain Applications of Trusted Execution Environments and Implications for Future Research
vTrain: A Simulation Framework for Evaluating Cost-Effective and Compute-Optimal Large Language Model Training
Software-based gate-level information flow security for IoT systems
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
AESPA: Asynchronous Execution Scheme to Exploit Bank-Level Parallelism of Processing-in-Memory
HyComp: a hybrid cache compression method for selection of data-type-specific compression methods
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
NoSQ: Store-Load Communication without a Store Queue
Fetch Directed Instruction Prefetching
Evaluating the Feasibility of Wireless Networks-on-Chip Enabled by Graphene
BOW: Breathing Operand Windows to Exploit Bypassing in GPUs
Multiple clock and voltage domains for chip multi processors
DCS: a fast and scalable device-centric server architecture
Portable compiler optimisation across embedded programs and microarchitectures using machine learning
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm
A computer aided design automation system for developing microprogrammed processors: a design approach through HDLs
MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm
Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection
Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications
Printed Machine Learning Classifiers
Control store implementation of a high performance VLSI CISC
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988
Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries
Thermal/Traffic Mutual-Coupling Co-simulation Platform for 3D Network-on-Chip (NoC) Designs
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
Very low power pipelines using significance compression
SUSHI: Ultra-High-Speed and Ultra-Low-Power Neuromorphic Chip Using Superconducting Single-Flux-Quantum Circuits
A powerful microprogram control unit - the 6700
Effective Cluster Assignment for Modulo Scheduling
Improving I/O Performance with a Conditional Store Buffer
Frequent value compression in data caches
Efficient instruction scheduling using finite state automata
Implementing the Draft RISC-V Scalar Cryptography Extensions
How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM
Distributed Page Table: Harnessing Physical Memory as an Unbounded Hashed Page Table
Performance analysis of application-specific instruction-set routers in networks-on-chip
Toward a multicore architecture for real-time ray-tracing
A Quantitative Analysis of Locality in Dataflow Programs
Power analysis of hardware implementations protected with secret sharing
Microprogramming heritage of RISC design
Universal Mechanisms for Data-Parallel Architectures
MDACache: Caching for Multi-Dimensional-Access Memories
Optimized surface code communication in superconducting quantum computers
The generation of simulator-based systems for microcode development
FORTRAN enhancement
Ristretto: An Atomized Processing Architecture for Sparsity-Condensed Stream Flow in CNN
Ternary computers: part 2: emulation of a ternary computer
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping
A limit study of local memory requirements using value reuse profiles
Efficient Path Profiling
BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads
On optimal loop parallelization
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
A Hardware-Software Platform for Intrusion Prevention
Adaptive Cache Management for Energy-Efficient GPU Computing
Accurate and Practical Profile-driven Compilation Using the Profile Buffer
Code scheduling for VLIW/superscalar processors with limited register files
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing
Racer: TSO consistency via race detection
ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata
MINT: Securely Mitigating Rowhammer with a Minimalist in-DRAM Tracker
Task mapping and communication routing model for minimizing power consumption in multi-cores
Rigorous Evaluation of Computer Processors with Statistical Model Checking
Managing GPU Concurrency in Heterogeneous Architectures
BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support
Message from the MICRO 2024 General Chairs: "Hi, How Are you?" - "Jeremiah The Innocent" Mural
Simple Vector Microprocessors for Multimedia Applications
Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference
RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction
Hierarchical and Dependency-Aware Task Mapping for NoC-based Systems
Polymorphic Error Correction
A firmware organization for minimal error evaluation in numerical computations
The FORTRAN project - a multifaceted approach to software-firmware high level language support
HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, Virtual Event, 18 October 2021
A microcoded tool to sample the software instruction address
PIFS-Rec: Process-In-Fabric-Switch for Large-Scale Recommendation System Inferences
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads
ThreadFuser: A SIMT Analysis Framework for MIMD Programs
Cache Refill/Access Decoupling for Vector Machines
CORUSCANT: Fast Efficient Processing-in-Racetrack Memories
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
MORC: a manycore-oriented compressed cache
Adaptive and Speculative Slack Simulations of CMPs on CMPs
CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices
On fundamentals of computer-aided design of firmware
PageORAM: An Efficient DRAM Page Aware ORAM Strategy
Managing Wire Delay in Large Chip-Multiprocessor Caches
Workload and Implementation Considerations for Dynamic Base Register Caching
Wormhole: Wisely Predicting Multidimensional Branches
Architecture-aware automatic computation offload for native applications
PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses
GreenDIMM: OS-assisted DRAM Power Management for DRAM with a Sub-array Granularity Power-Down State
All example of using pseudofields to eliminate version shuffling in horizontal code compaction
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation
Snake: A Variable-length Chain-based Prefetching for GPUs
Learning to Drive Software-Defined Solid-State Drives
Supporting Energy-based Learning with an Ising Machine substrate: a Case Study on RBM
DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms
A case study in signal processing microprogramming using the URPR software pipelining technique
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum)
A microprogramming teaching environment using the Macintosh computer
Hot Cold Optimization of Large Windows/NT Applications
Toward a science for future NoC design
Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
Memory cocktail therapy: a general learning-based framework to optimize dynamic tradeoffs in NVMs
Revisiting the Sequential Programming Model for Multi-Core
GPMB - software pipelining branch-intensive loops
GURPR - a method for global software pipelining
DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation
Task Selection for a Multiscalar Processor
Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed
Optimizations and Oracle Parallelism with Dynamic Translation
FeatherWeight: low-cost optical arbitration with QoS support
SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling
Two-Level Adaptive Training Branch Prediction
On multicast for dynamic and irregular on-chip networks using dynamic programming method
Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015
Grape: Practical and Efficient Graphed Execution for Dynamic Deep Neural Networks on GPUs
Cellular arrays for asynchronous control
RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance
Scalable Cache Miss Handling for High Memory-Level Parallelism
A multi-microprocessor design
NBTI tolerant microarchitecture design in the presence of process variation
DOAS: an object oriented architecture supporting secure languages
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Guaranteed Services of the NoC of a Manycore Processor
Coherence domain restriction on large scale systems
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption
Architectural Specialization for Inter-Iteration Loop Dependence Patterns
Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign
Dynamic speculative precomputation
2-in-1 Accelerator: Enabling Random Precision Switch for Winning Both Adversarial Robustness and Efficiency
NOC-Out: Microarchitecting a Scale-Out Processor
ReGraph: Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
Extending Gem5-Garnet for Efficient and Accurate Trace-driven NoC Simulation
A framework for high-speed controller design
Temporal instruction fetch streaming
An effective programmable prefetch engine for on-chip caches
Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks
Generalizing Ray Tracing Accelerators for Tree Traversals on GPUs
ESCALATE: Boosting the Efficiency of Sparse CNN Accelerator with Kernel Decomposition
Design space exploration for streaming applications on multiprocessors with guaranteed service NoC
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling
BABOL: A Software-Defined NAND Flash Controller
Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003
The M-Machine multicomputer
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory
Confluence: unified instruction supply for scale-out servers
Multi-Layer In-Memory Processing
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
Delegated persist ordering
Optimizing the Memory Hierarchy by Compositing Automatic Transformations on Computations and Data
XPGraph: XPline-Friendly Persistent Memory Graph Stores for Large-Scale Evolving Graphs
Microprogramming and its relationship to emulation and technology
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance
A microarchitecture-based framework for pre- and post-silicon power delivery analysis
Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities
A Novel Memory Management for RISC-V Enclaves
Merging Similar Patterns for Hardware Prefetching
Lazy data routing and greedy scheduling for application-specific signal processors
Tigris: Architecture and Algorithms for 3D Perception in Point Clouds
From high-level deep neural models to FPGAs
Network-On-Chip Performance Evaluation by Synchronous Circuit Simulation
Cambricon-X: An accelerator for sparse neural networks
EMMA: Hardware/Software Attestation Framework for Embedded Systems Using Electromagnetic Signals
AccelWattch: A Power Modeling Framework for Modern GPUs
Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution
Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching
A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip
Pipelining a triggered processing element
Proceedings of the 9th annual workshop on Microprogramming, MICRO 1976, New Orleans, Louisiana, USA, September 27-29, 1976
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores
Composite Cores: Pushing Heterogeneity Into a Core
Our machine, a microcoded LSI processor
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
Ares-Flash: Efficient Parallel Integer Arithmetic Operations Using NAND Flash Memory
On Error Injection for NoC Platforms: A UVM-based Practical Case Study
pTask: A smart prefetching scheme for OS intensive applications
Quality programmable vector processors for approximate computing
Automatic Domain-Specific SoC Design for Autonomous Unmanned Aerial Vehicles
Design of storage hierarchy in multithreaded architectures
Exploiting instruction-level parallelism: the multithreaded approach
Assigning Confidence to Conditional Branch Predictions
δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant Computations in the Vision Pipeline
Efficiently Enabling Block Semantics and Data Updates in DNA Storage
Highly Accurate Data Value Prediction Using Hybrid Predictors
Languages for direct execution
Teaching microprogramming(Panel Discussion)
Data dependency graph bracing
Modeling and Validation of a Mixed-Criticality NoC Router Using the IF Language
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops
Cache designs with partial address matching
Qoncord: A Multi-Device Job Scheduling Framework for Variational Quantum Algorithms
A VLSI based microprogramming evaluation system to support an instructional laboratory
More is less: improving the energy efficiency of data movement via opportunistic use of sparse codes
Hardware-based Always-On Heap Memory Safety
KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism
Mapping HLL constructs into microcode for improved execution speed
An Architectural Charge Management Interface for Energy-Harvesting Systems
Page Size Aware Cache Prefetching
Persistent Processor Architecture
Leveraging Caches to Accelerate Hash Tables and Memoization
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Approaches to design of high level languages for microprogramming
Analyzing the Working Set Characteristics of Branch Execution
IMP: indirect memory prefetcher
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture
Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
Doppelgänger: a cache for approximate computing
Message from the MICRO 2024 Program Chairs
Beyond the socket: NUMA-aware GPUs
DiVa: An Accelerator for Differentially Private Machine Learning
Blenda: Dynamically-Reconfigurable Stacked DRAM
A Front-End Execution Architecture for High Energy Efficiency
InTrust-IoT: Intelligent Ecosystem based on Power Profiling of Trusted device(s) in IoT for Hardware Trojan Detection
Memento: Architectural Support for Ephemeral Memory Management in Serverless Environments
An out-of-order superscalar processor with speculative execution and fast, precise interrupts
A microprogrammed machine architecture for efficient matrix multiplication
The store-load address table and speculative register promotion
Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency
On pipelining dynamic instruction scheduling logic
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Temporal Prefetching Without the Off-Chip Metadata
An algorithm for microcode compaction of VHDL behavioral descriptions
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer
The YAGS Branch Prediction Scheme
Cache miss heuristics and preloading techniques for general-purpose programs
Process Variation Tolerant 3T1D-Based Cache Architectures
Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM
Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory
Practical and Scalable Security Verification of Secure Architectures
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows
Register/File/Cache Microarchitecture Study Using VHDL
A new approach to schedule operations across nested-ifs and nested-loops
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The Microprogrammable Multi-Processor (MMP) system for simultaneous emulation of interoperating computer systems
Authenticache: harnessing cache ECC for system authentication
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine
CamPU: A Multi-Camera Processing Unit for Deep Learning-based 3D Spatial Computing Systems
An automatic migration scheme based on modular microcode and structured firmware sequencing
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators
Clocked and asynchronous instruction pipelines
Experience with an interactive basic machine implemented using the Burroughs B1700
Proceedings of the 14th annual workshop on Microprogramming, MICRO 1981, Chatham (Cape Cod), Massachusetts, USA
Facelift: Hiding and slowing down aging in multicores
A comparison of the code space and execution time required for FORTRAN assignment statements on six computer architectures
A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation
Software aids for microprogram development
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Improving CISC instruction decoding performance using a fill unit
The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory
A comprehensive instruction fetch mechanism for a processor supporting speculative execution
Enabling portable energy efficiency with memory accelerated library
A microprogrammable architecture with quasi time-transparent structured control
Verification of microprogrammed computer architectures in the S*-system: a case study
SAWS: synchronization aware GPGPU warp scheduling for multiple independent warp schedulers
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration
uComplexity: Estimating Processor Design Effort
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching
Using branch predictors to predict brain activity in brain-machine implants
Hardware transactional memory for GPU architectures
The Superfluous Load Queue
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics
Prefetch-Aware DRAM Controllers
Design objectives for high level microprogramming languages
Cool-cache for hot multimedia
Load Latency Tolerance in Dynamically Scheduled Processors
Enhancing loop buffering of media and telecommunications applications using low-overhead predication
Gemini: Learning to Manage CPU Power for Latency-Critical Search Engines
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware
EMI Architectural Model and Core Hopping
Instruction Scheduling for the HP PA-8000
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Flattened Butterfly Topology for On-Chip Networks
Predictive Techniques for Aggressive Load Speculation
Global methods in the flow graph approach to retargetable microcode generation