yusuke1997/dblp-id-title huggingface dataset:
Model to Improve the Efficiency in the Extrusion Area in a Manufacturing SME of the Industrial Plastic Sector Based on SMED, Autonomous Maintenance and 5S
Emotion Detection Based on Smartphone Using User Memory Tasks and Videos
Improvement of Attention Times and Efficiency of Container Movements in a Port Terminal Using a Truck Appointment System, LIFO Management and Poka Yoke
Mapping Risks and Requirements for Truck Platooning: A Human-Centred Approach
Comprehensive Management Model for Solid Waste Collection and Transportation in Peruvian Urban Municipalities
Analysis of the Mental Workload Applied to the Sorting Activity of Recyclable Materials
"I Think It's Quite Subtle, So It Doesn't Disturb Me": Employee Perceptions of Levels, Points and Badges in Corporate Training
Improvement of the Polymer Insulation Production Process Using Lean Manufacturing Tools and Plant Layout Design
Towards Visual Data Science - An Exploration
Implementing "SIREKAP" Application Based on Election for Improving the Integrity of Election Administrators and Increasing Public Trust
An AcciMap of the Edinburgh Tram Network Project Delivery Failure
Avoiding Post-Merger Corporate Downsize Restructuring: The Democratic Employee-Culture Fit Model (DeECFit)
Drilling-and-Blasting Mesh Design for Underground Mining Using the Holmberg Method
The Effects of Sound Interference on Soldiers Cognitive Performance, Workload Assessment and Emotional Responses
Human-in-the-Middle: Increasing Security of Two-Factor Authentication
Economic Recovery for Tourism Sector Based on Social Media Data Mining
Analysis of Color Control and Humanized Design in Ship Cabin Environment
Evaluation on the Comprehensibility of China's Safety Prohibition Signs Based on Ergonomic Principles
Gender Approach to Studying History of Social Work in Ukraine
Bitcoin adoption: Scams and anonymity may not matter but trust into Bitcoin security does
It's all fun and games, and some legalese: data protection implications for increasing cyber-skills of employees through games
Virtual honeypots and detection of telnet botnets
On the Feasibility of Secure Logging for Industrial Control Systems Using Blockchain
IPv6 Covert Channels in the Wild
A Secure String Class Compliant with PCI DSS
Towards unambiguous IT risk definition
What drives the motivation to self-protect on social networks?: The role of privacy concerns and perceived threats
Concept Drift Analysis for Improving Anomaly Detection Systems in Cybersecurity
A practical view on IT risk management process
Combined side-channels malware detection for NFV infrastructure
How much does a zero-permission Android app know about us?
Integrating Threat Modeling and Automated Test Case Generation into Industrialized Software Security Testing
SAT Solvers and their Limits with NFSR-based Stream Ciphers: an Example with Grain v1
From Fake News to Virtual Reality: Fake News and Digital Manipulations at the Age of Modern Technology
Privacy improvement model for biometric person recognition in ambient intelligence using perceptual hashing
Multi-Platform Authorship Verification
Case Study: Analysis and Mitigation of a Novel Sandbox-Evasion Technique
Mobile Security: Two Generations of Potential Victims
Explaining the Employment of Information Security Measures by Individuals in Organizations: The Self-protection Model
Forensic Investigations in Vehicle Data Stores
One Countermeasure, Multiple Patterns: Countermeasure Variation for Covert Channels
Improving Lawful Interception in Virtual Datacenters
Application Detection in Anonymous Communication Networks
An Ontology Capturing the Interdependence of the General Data Protection Regulation (GDPR) and Information Security
Approaching the Automation of Cyber Security Testing of Connected Vehicles
Do ut des: Disseminating online child sexual abuse material for investigative purposes?
Retrospective Tracking of Suspects in GDPR Conform Mobile Access Networks Datasets
Towards a delegation-type secure software development method
Proceedings of the Central European Cybersecurity Conference 2018, CECC 2018, Ljubljana, Slovenia, November 15-16, 2018
Information Security Management Practices: Expectations and Reality
Simulating and Detecting Attacks of Untrusted Clients in OPC UA Networks
Aligning Business Process Access Control Policies with Enterprise Architecture
Cycle Structure and Reachability Analysis for Cipher Spritz with Small N
Cipher, the Random and the Ransom: A Survey on Current and Future Ransomware
Obfuscated Android Application Development
Preparation of Response Model to Cyber-attacks at Nuclear Facilities
Accommodating Time-Triggered Authentication to FlexRay Demands
Use of Mobile Devices in Hospitals and Perceived Data Breach Consequences: An Explorative Study
Proceedings of the Third Central European Cybersecurity Conference, CECC 2019, Munich, Germany, November 14-15, 2019
A brief look at the security of DeviceNet communication in industrial control systems
A Framework for a Forensically Sound Harvesting the Dark Web
Security Analysis of Key Acquiring Strategies Used by Cryptographic Ransomware
Cybercrime victimization and seeking help: A survey of students in Slovenia
Combat Mobile Evasive Malware via Deep Learning
Coping with Access Control Requirements in the Context of Mutual Dependencies between Business and IT
Network Forensic Investigation in OpenContrail Environments
Advances in Cybersecurity - Proceedings of the 2017 Central European Cybersecurity Conference, CECC 2017, Ljubljana, Slovenia, November 16-17, 2017
The Password Literacy in North Macedonia: A Case Study
Achieving Consistency of Software Updates against Strong Attackers
Discussing the Feasibility of Acoustic Sensors for Side Channel-aided Industrial Intrusion Detection: An Essay
Determining Minimum Hash Width for Hash Chains
Digital Forensics vs. Due Process: Conflicting Standards or Complementary Approaches?
Security of IoT Cloud Services - A User-Oriented Test Approach
A Testbed for Performing Security Experiments with Software-Defined Industrial Control Systems
Why Did I End Up Living in a Cave? Risks of IoT at home
OpenSPA - An Open and Extensible Protocol for Single Packet Authorization
Security in Process: Detecting Attacks in Industrial Process Data
Hack My Company: An Empirical Assessment of Post-exploitation Behavior and Lateral Movement in Cloud Environments
Meizodon: Security Benchmarking Framework for Static Android Malware Detectors
Children Privacy Protection in Video Surveillance Based on Automatic Age Estimation
Structural Limitations of B+-Tree forensics
Proceedings of the ACM SIGPLAN SIGOA Symposium on Text Manipulation, Portland, Oregon, USA, June 8-10, 1981
Minimizing buffer requirements for throughput constrained parallel execution of synchronous dataflow graph
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems
Distributed computing in IoT: System-on-a-chip for smart cameras as an example
BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator
SecHLS: Enabling Security Awareness in High-Level Synthesis
Performance-driven global placement via adaptive network characterization
Probabilistic congestion model considering shielding for crosstalk reduction
Design of resource sharing reconfigurable ΔΣ SAR-ADC
Module Selection Using Manufacturing Information
Co-synthesis with custom ASICs
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage
SQLiteKV: An efficient LSM-tree-based SQLite-like database engine for mobile devices
Reservoir and mixer constrained scheduling for sample preparation on digital microfluidic biochips
AI-Guided Codesign for Novel Computing Paradigms
On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits
A low-latency asynchronous interconnection network with early arbitration resolution
Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithm
The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2 m ) based on Bivariate Polynomial Basis Representation
Handling stuck-at-faults in memristor crossbar arrays using matrix transformations
A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network
Tradeoff routing resource, runtime and quality in buffered routing
A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs
Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning
Early stage real-time SoC power estimation using RTL instrumentation
Re-configurable embedded core test protocol
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks
Structured Placement with Topological Regularity Evaluation
Irredundant address bus encoding techniques based on adaptive codebooks for low power
Pulsed-latch ASIC synthesis in industrial design flow
Addressing thermal and power delivery bottlenecks in 3D circuits
Dependable VLSI: device, design and architecture: how should they cooperate?
A dual-band switching digital controller for a buck converter
Design of Active Substrate Noise Canceller using Power Supply di/dt Detector
Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment
Efficient routability checking for global wires in planar layouts
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
A non-iterative model for switching window computation with crosstalk noise
DMCO: A Strategy for Design-Manufacturing Co-optimization
On the representational power of bit-level and word-level decision diagrams
An efficient IP-level power model for complex digital circuits
A Practical Randomized GMRES Algorithm for Solving Linear Equation System in Circuit Simulation
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures
Beyond von Neumann Era: Brain-Inspired Hyperdimensional Computing to the Rescue
Stress-aware P/G TSV planning in 3D-ICs
A computational model for SAT-based verification of hardware-dependent low-level embedded system software
Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography
SAT-based sequential depth computation
Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling Challenges
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench
Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010
A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures
ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices
Reducing bus delay in submicron technology using coding
Exploring the fidelity-efficiency design space using imprecise arithmetic
Towards scalable and efficient GPU-enabled slicing acceleration in continuous 3D printing
Synthesizable HDL generation method for configurable VLIW processors
Design space exploration of FPGA-based Deep Convolutional Neural Networks
Fixing Design Errors with Counterexamples and Resynthesis
Security analysis on consumer and industrial IoT devices
Low Power CMOS Off-Chip Drivers with Slew-rate Difference
ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack
An adaptive on-line CPU-GPU governor for games on mobile devices
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Optimizing FPGA-based convolutional neural networks accelerator for image super-resolution
Floorplan and placement methodology for improved energy reduction in stacked power-domain design
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs
A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"
Improving LDPC performance via asymmetric sensing level placement on flash memory
An application-centered design flow for self reconfigurable systems implementation
FSM-based transaction-level functional coverage for interface compliance verification
Lessons from the neurons themselves
Efficient and Secure Cloud-based Split Logic Synthesis
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling
Imprecise data computation for high performance asynchronous processors
Support tools for porting legacy applications to multicore
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Sleep transistor sizing using timing criticality and temporal currents
VISA: versatile impulse structure approximation for time-domain linear macromodeling
Toward large-scale access-transistor-free memristive crossbars
Constructing zero-deficiency parallel prefix adder of minimum depth
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
Modeling and detection of dynamic errors due to reflection- and crosstalk-noise
An AC powered converter-free LED driver with low flicker
Cell selection from technology libraries for minimizing power
Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools
Profile assisted online system-level performance and power estimation for dynamic reconfigurable embedded systems
Generation of Interpretive and Compiled Instruction Set Simulators
A testability metric for path delay faults and its application
Optimal TDMA time slot and cycle length allocation for hard real-time systems
Area/delay estimation for digital signal processor cores
Advanced multi-patterning and hybrid lithography techniques
A systematic security analysis of real-time cyber-physical systems
NTGAT: A Graph Attention Network Accelerator with Runtime Node Tailoring
Signal integrity analysis in the open architecture
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004
A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS
Energy-efficient optical crossbars on chip with multi-layer deposited silicon
High-level synthesis of multiple dependent CUDA kernels on FPGA
On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs
An automated method for test model generation from switch level circuits
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion
Investigation of diffusion rounding for post-lithography analysis
Load scheduling: Reducing pressure on distributed register files for free
Interconnect Delay Estimation Models for Synthesis and Design Planning
Optimizing dynamic mapping techniques for on-line NoC test
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
Relaxed Simulated Tempering for VLSI Floorplan Designs
DRiLLS: Deep Reinforcement Learning for Logic Synthesis
Self-learning and adaptive board-level functional fault diagnosis
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application
Facilitating unreachable code diagnosis and debugging
The Optimal Quantum of Temporal Decoupling
Formally analyzing fault tolerance in datapath designs using equivalence checking
Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)
Tutorial-1: Machine learning and deep learning
CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems
Comprehensive die-level assessment of design rules and layouts
STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing
Protocol Transducer Synthesis using Divide and Conquer approach
Design and application of highly integrated optical switches based on silicon photonics
A seed selection procedure for LFSR-based random pattern generators
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Systems modeling for additional development in automotive E/E architecture
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
A routability-driven flow routing algorithm for programmable microfluidic devices
Hardware implementation of an EAN-13 bar code decoder
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
Multilane Racetrack caches: Improving efficiency through compression and independent shifting
VEAP: Global optimization based efficient algorithm for VLSI placement
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation
Variational Label-Correlation Enhancement for Congestion Prediction
A dynamically reconfigurable hardware-based cipher chip
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors
Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System
A multi-task-oriented security processing architecture with powerful extensibility
PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits
Symbolic circuit-noise analysis and modeling with determinant decision diagrams
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
An interleaved dual-battery power supply for battery-operated electronics
Post-silicon bug detection for variation induced electrical bugs
A novel instruction scratchpad memory optimization method based on concomitance metric
Synthesizing multiple scan chains by cost-driven spectral ordering
An elitist distributed particle swarm algorithm for RF IC optimization
OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLM
Quantum circuit compilers using gate commutation rules
A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETC
Yield-preferred via insertion based on novel geotopological technology
PIONEER: Highly Efficient and Accurate Hyperdimensional Computing using Learned Projection
Minimization of memory size for heterogeneous MDDs
Trace-based context-sensitive timing simulation considering execution path variations
Database and Benchmark for Early-stage Malicious Activity Detection in 3D Printing
Speech encoding and encryption in VLSI
SOLSA: Neuromorphic Spatiotemporal Online Learning for Synaptic Adaptation
Deterministic test for the reproduction and detection of board-level functional failures
A novel Toffoli network synthesis algorithm for reversible logic
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules
A statistical STT-RAM retention model for fast memory subsystem designs
Performance-centric register file design for GPUs using racetrack memory
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS
An FPGA-compatible PLL-based sensor against fault injection attack
Wire synthesizable global routing for timing closure
Embedded software reliability testing by unit-level fault injection
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Fast Placement Optimization of Power Supply Pads
A VLSI implementation of the blowfish encryption/decryption algorithm
Incremental solution of power grids using random walks
Parallel fault backtracing for calculation of fault coverage
A function generator-based reconfigurable system
Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints
High speed and ultra-low power 16×16 MAC deisgn using TG techniques for web-based multimedia system
High quality IP design using high-level synthesis design flow
Design of multiple fanout clock distribution network for rapid single flux quantum technology
Variation tolerant logic mapping for crossbar array nano architectures
Floorplanning for 3-D VLSI design
An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits
Timing driven gate duplication in technology independent phase
An SPU reference model for simulation, random test generation and verification
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches
Future electron-beam lithography and implications on design and CAD tools
Emerging memories as enablers for in-memory layout transformation acceleration and virtualization
Predicting short circuit power from timing models
An automated approach for improving the inference latency and energy efficiency of pretrained CNNs by removing irrelevant pixels with focused convolutions
Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number Systems
28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver
Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing
Towards Automatic Hardware Synthesis from Formal Specification to Implementation
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction
Multi-level logic benchmarks: An exactness study
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation
A Novel Design Assistant for Analog Circuits
An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications
Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper)
Scratchpad Memory aware task scheduling with minimum number of preemptions on a single processor
PIMCH: Cooperative memory prefetching in processing-in-memory architecture
QuadraNet: Improving High-Order Neural Interaction Efficiency with Hardware-Aware Quadratic Neural Networks
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells
Analog Circuit Transfer Method Across Technology Nodes via Transistor Behavior
Negotiation-based track assignment considering local nets
Formal verification of pulse-mode asynchronous circuits
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies
Transduction method for design of logic cell structure
BEAM: bus encoding based on instruction-set-aware memories
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions
Quo vadis, BTSoC (Billion Transistor SoC)?
Device-Aware Test for Anomalous Charge Trapping in FeFETs
A new approach for ring oscillator simulation using the harmonic balance method
PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans
APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level
Fault simulation and test generation for clock delay faults
Effective Simulation for the Giga-scale Massively Parallel Supercomputer SR2201
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface
Software Performance Estimation in MPSoC Design