yusuke1997/dblp-id-title huggingface dataset:
Evolutionary composition using music theory and charts
The probe allocation problem
Contextual on-board learning and prediction of vehicle destinations
Cloud aided semi-active suspension control
Real time prediction of worst case air traffic sector collision risk using evolutionary optimization
Probabilistic modeling of navigation bridge officer's behavior
Battery-supercapacitor electric vehicles energy management using DP based predictive control algorithm
Autonomous running control system of an AGV by a tablet PC based on the wall-floor boundary line
Mining traffic accident features by evolutionary fuzzy rules
2013 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems, CIVTS 2013, Singapore, April 16-19, 2013
Fitness function for evolutionary computation applied in dynamic object simulation and positioning
Conceptual design of a driving habit recognition framework
An evolutionary approach to traffic assignment
Exploring the Mahalanobis-Taguchi approach to extract vehicle prognostics and diagnostics
A system for the traffic control in signposted junctions
Driver distraction detection by in-vehicle signal processing
Design of a toy submarine using underwater vehicle design optimization framework
A redundancy-based approach for visual navigation with collision avoidance
Data compression techniques for urban traffic data
Overview of CI research in automotive ITS
Real-time urban traffic information extraction from GPS tracking of a bus fleet
A real-time visual-based front-mounted vehicle collision warning system
Traffic information extraction from a blogging platform using knowledge-based approaches and bootstrapping
Multiobjective selection of input sensors for travel times forecasting using support vector regression
Trust-based controller for convoy string stability
Linguistic model for engine power loss
The role of data choice in data driven identification for online emission models
2011 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems, CIVTS 2011, Paris, France, April 11-15, 2011
2014 IEEE Symposium on Computational Intelligence in Vehicles and Transportation Systems, CIVTS 2014, Orlando, FL, USA, December 9-12, 2014
Grid-based visual terrain classification for outdoor robots using local features
Single intersection signal control based on Type-2 fuzzy logic
An approximate bus route planning algorithm
Fuzzy linguistic reporting in driving simulators
Improvement of the road traffic management by an ant-hierarchical fuzzy system
Dynamic ridesharing with intermediate locations
Computationally inexpensive labeling of appearance based navigable terrain for autonomous rovers
Robust obstacle segmentation based on topological persistence in outdoor traffic scenes
Batch reinforcement learning for optimizing longitudinal driving assistance strategies
Freeway ramp metering by macroscopic traffic scheduling with particle swarm optimization
Fuzzy logic based localization for vehicular ad hoc networks
Behavior characteristics of mixed traffic flow on campus
Genetic adaptive A-Star approach for ttrain trip profile optimization problems
Predicting bikeshare system usage up to one day ahead
Real time vehicle speed predition using gas-kinetic traffic modeling
Evolving intelligent vehicle control using multi-objective NEAT
An evolutionary goal-programming approach towards scenario design for air-traffic human-performance experiments
A GPU-based real-time traffic sign detection and recognition system
Car relocation for carsharing service: Comparison of CPLEX and greedy search
Context-based estimation of driver intent at road intersections
Evolving the topology of subway networks using genetic algorithms
An effective search and navigation model to an auto-recharging station of driverless vehicles
FPGA clock network architecture: flexibility vs. area and power
Power analysis and estimation tool integrated with XPOWER
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT
Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation
Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only)
Design Principles for Packet Deparsers on FPGAs
Latency Insensitivity Testing for Dataflow HLS Designs
Timing-driven placement for FPGAs
Post-route LUT output polarity selection for timing optimization
Data streaming and simd support for the microblaze architecture
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995
FPGA implementation of a high speed network interface card for optical burst switched networks
MLBlocks: FPGA Blocks for Machine Learning Applications
How to Accelerate FPGA Application in an Asynchronous Way?
Efficient FPGA implementation of qr decomposition using a systolic array architecture
Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only)
an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only)
Pipelining FPPGA-based defect detction in FPDs (abstract only)
String Natching on Nulticontext FPGAs Using Self-Reconfiguration
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Reducing the pressure on routing resources of FPGAs with generic logic chains
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010
Constraints from Hell: How to Tell Makes a Good FPGA (Panel)
Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels
A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms
An analytical model relating FPGA architecture parameters to routability
FPGA / SoC Security: Arms Race in the Cloud
Are FPGAs suffering from the innovator's dilemna?
Mapping for better than worst-case delays in LUT-based FPGA designs
AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only)
InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs
Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs
SAT-Accel: A Modern SAT Solver on a FPGA
ThunderGP: HLS-based Graph Processing Framework on FPGAs
Variation tolerant asynchronous FPGA (abstract only)
LUT-based FPGA technology mapping for reliability (abstract only)
A platform for high level synthesis of memory-intensive image processing algorithms
Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only)
The Wave Pipeline Effect on LUT-Based FPGA Architectures
Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits
Incremental physical resynthesis for timing optimization
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation
A 17ps time-to-digital converter implemented in 65nm FPGA technology
Physical Design Space Exploration
Sequence-based In-Circuit Breakpoints for Post-Silicon Debug (Abstract Only)
Measuring and modeling FPGA clock variability
Technology mapping for k/m-macrocell based FPGAs
Spatial Debug & Debug Without Re-programming in FPGAs: On-Chip debugging in FPGAs
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning
Fractal Synthesis: Invited Tutorial
A Fine-Grained Sparse Accelerator for Multi-Precision DNN
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Engaging Heterogeneous FPGAs in the Cloud
An Efficient High-Speed FFT Implementation
Reuse Kernels or Activations?: A Flexible Dataflow for Low-latency Spectral CNN Acceleration
Synthesis and Floorplanning for Large Hierarchical FPGAs
Synthesizing full-systolic arrays for matrix product on Xilinx's XC4000(E, EX) FPGAs (poster abstract)
A benchmark suite for evaluating configurable computing systems--status, reflections, and future directions
Fast and effective placement and routing directed high-level synthesis for FPGAs
A new basic logic structure for data-path computation (abstract only)
Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis
HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array
RENCO: A Reconfigurable Network Computer (Abstract)
Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene
Chameleon: A Workstation of a Different Colour
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
Design of FPGAs with Area I/O for Field Programmable MCM
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture
ReducedLUT: Table Decomposition with "Don't Care" Conditions
Global Is the New Local: FPGA Architecture at 5nm and Beyond
Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment
A Method for Implementing Fractal Image Compression on Reconfigurable Architecture
Intel nehalem processor core made FPGA synthesizable
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment
Using FPLs to Prototoype a Self-Timed Computer
OpenCL memory infrastructure for FPGAs (abstract only)
LevelST: Stream-based Accelerator for Sparse Triangular Solver
An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract)
Factoring large numbers with programmable hardware
A crosstalk-aware timing-driven router for FPGAs
JAPROC - An 8 bit Micro Controller Design and Its Test Environment
Minimization of Permuted Reed-Muller Trees for Cellular Logic
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
Understanding Performance Differences of FPGAs and GPUs: (Abtract Only)
Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only)
Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only)
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration
Combining computation and communication optimizations in system synthesis for streaming applications
Reconfigurable Acceleration of Short Read Mapping with Biological Consideration
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks
Exploration of heterogeneous reconfigurable architectures (abstract only)
LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization
Customized regular channel design in FPGAs
GraSU: A Fast Graph Update Library for FPGA-based Dynamic Graph Processing
Reducing leakage energy in FPGAs using region-constrained placement
Combining module selection and resource sharing for efficient FPGA pipeline synthesis
An execution environment for reconfigurable computing (abstract only)
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size
Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only)
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis
Superoptimized Memory Subsystems for Streaming Applications
Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR
A multilevel hierarchical interconnection structure for FPGA
Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only)
FTConv: FPGA Acceleration for Transposed Convolution Layers in Deep Neural Networks
HBM Connect: High-Performance HLS Interconnect for FPGA HBM
Design of a Three-Dimensional FPGA for Reconfigurable Computing Machines (Abstract)
A field programmable array core for image processing (abstract only)
FPGA Technology Mapping with Adaptive Gate Decomposition
CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs
Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs
Pattern-based behavior synthesis for FPGA resource reduction
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks
FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only)
A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only)
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only)
Power-aware RAM mapping for FPGA embedded memory blocks
Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only)
Fault modeling and characteristics of SRAM-based FPGAs (abstract only)
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures
CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only)
Nuclear Reactor Simulations on OpenCL FPGA Platform
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology (Abstract Only)
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
Should the academic community launch an open-source FPGA device and tools effort?: evening panel
Efficient and Effective Sparse LSTM on FPGA with Bank-Balanced Sparsity
Efficient static timing analysis and applications using edge masks
An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only)
Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only)
Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)
WireMap: FPGA technology mapping for improved routability
Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only)
Nanowire-based sublithographic programmable logic arrays
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation
Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)
ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAs
On-line sensing for healthier FPGA systems
Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract)
Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)
Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing Permutations
A configurable mapreduce accelerator for multi-core FPGAs (abstract only)
Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only)
Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only)
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
FPGAs with multidimensional mesh topology
FABulous: An Embedded FPGA Framework
Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only)
3D FPGAs: placement, routing, and architecture evaluation (abstract only)
A remote memory access infrastructure for global address space programming models in FPGAs
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing
FiT: An Automated Toolkit for Matching Processor Architecture to Applications (Abstract Only)
A Performance model for accelerating scientific applications on reconfigurable computers
Yield enhancements of design-specific FPGAs
Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling
A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only)
FPGA implementation of highly parallelized decoder logic for network coding (abstract only)
Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond
FGPU: An SIMT-Architecture for FPGAs
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Diagnosing Programmable Interconnect Systems for FPGAs
An FPGA implementation of bene permutation networks
3D configuration caching for 2D FPGAs
A SC-based novel configurable analog cell
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024
Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays
A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only)
SPFD-based global rewiring
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only)
PathFinder: A Negotiation-based Performance-driven Router for FPGAs
Performance Portable FPGA Design
Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)
Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only)
Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division
An FPGA implementation of block truncation coding for gray and color images
FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search
CUSP: a modular framework for high speed network applications on FPGAs
FPGA Based Computer Vision Camera
Fast Module Mapping and Placement for Datapaths in FPGAs
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only)
An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only)
FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022
Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only)
FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors
QTAccel: A Generic FPGA based Design for Q-Table based Reinforcement Learning Accelerators
NetTM: faster and easier synchronization for soft multicores via transactional memory
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021
wa-hls4ml and lui-gnn: A Benchmark and GNN based Surrogate Model for hls4ml Resource and Latency Estimation
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop
A magnetoelectronic macrocell employing reconfigurable threshold logic
FPGAs in Supercomputers: Opportunity or Folly?
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only)
Scalable and deterministic timing-driven parallel placement for FPGAs
A constraints programming approach to communication scheduling on SoPC architectures
MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows
Just In Time Assembly of Accelerators
Configuration Caching Vs Data Caching for Striped FPGAs
Design, layout and verification of an FPGA using automated tools
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI
Towards interconnect-adaptive packing for FPGAs
Flexibility measurement of domain-specific reconfigurable hardware
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning
NASCENT: Near-Storage Acceleration of Database Sort on SmartSSD
Scalable FPGA Median Filtering using Multiple Efficient Passes
Divide and concatenate: a scalable hardware architecture for universal MAC
High-level languages: the future or a passing fad?
Is Reconfigurable Computing Commercially Viable (panel)?
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)
Global delay optimization using structural choices
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks
Fast adders in modern FPGAs
On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only)
Wormhole Run-Time Reconfiguration
Delay-Bounded Routing for Shadow Registers
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Securing netlist-level FPGA design through exploiting process variation and degradation
Bridging Architecture and Programming for Throughput-Oriented Vision Processing (Abstract Only)
An integrated debugging environment for FPGA computing platforms
Automatic One-Hot Re-Encoding for FPLs
Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)
Extreme parallel architectures for the masses
Novel FPGA clock network with low latency and skew (abstract only)
LRoute: a delay minimal router for hierarchical CPLDs
Dynamically Programmable Cache Evaluation and Virtualization
Power-aware architectures and circuits for FPGA-based signal processing
PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs
FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals
LAWS: Large-Scale Accelerated Wave Simulations on FPGAs
VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only)
Technology Mapping into General Programmable Cells
Scalable architecture for programmable quantum gate array (abstract only)
Building a flexible and scalable DRAM interface for networking applications on FPGAs
Embedded floating-point units in FPGAs
Integrated retiming and placement for field programmable gate arrays
High-Performance 2-D FPGA DCTs Using Polynomial Transforms
Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only)
Implementing an Artificial CPG Using Fine-Grain FPGAs
From the bitstream to the netlist
Architectural enhancements in Stratix V™
FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA
Accelerating frequent item counting with FPGA
Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only)
Configuration Prefetch for Single Context Reconfigurable Coprocessors
A novel BIST approach for testing input/output buffers in FPGAs
Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only)
Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)