yusuke1997/dblp-id-title huggingface dataset:
Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS
PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers
Cryogenic Operation of Computing-In-Memory based Spiking Neural Network
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories
Low power fast and dense longest prefix match content addressable memory for IP routers
Charge migration efficiency optimization in hybrid electrical energy storage (HEES) systems
A three-port adiabatic register file suitable for embedded applications
Modeling and analysis of leakage induced damping effect in low voltage LSIs
SHIFT ECC: A Value Converting HBM ECC Approach for Refresh Energy Efficient Integer Quantized DNN Inference
Designing for dark silicon: a methodological perspective on energy efficient systems
Power reduction by aggressive synthesis design space exploration
Thread fusion
Transistor-to-GDS Reliability Analysis in Sub-3nm: Impact of Self-Heating and Aging on Timing
A simple mechanism to adapt leakage-control policies to temperature
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection
Placement mitigation techniques for power grid electromigration
Hybrid electrical energy storage systems
The design of a high performance low power microprocessor
PowerTrain: A learning-based calibration of McPAT power models
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution
ESACW: an adaptive algorithm for transmission power reduction in wireless networks
Energy harvesting photodiodes with integrated 2D diffractive storage capacitance
Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability
SmartMS: Efficient Hierarchical Database Search for Mass Spectrometry via Processing-in-Memory
Circuit styles and strategies for CMOS VLSI design on SOI
SATS: An Ultra-Low Power Time Synchronization for Solar Energy Harvesting WSNs
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation
Speeding up power estimation of embedded software
RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques
Efficient Transformer Acceleration via Reconfiguration for Encoder and Decoder Models and Sparsity-Aware Algorithm Mapping
Graphene nano-ribbon field-effect transistors as future low-power devices
Energy-efficient data scrambling on memory-processor interfaces
Low power chips: a fabless asic perspective
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications
Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation
SEPAS: a highly accurate energy-efficient branch predictor
Compact modeling of carbon nanotube transistor for early stage process-design exploration
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell
Unified embedded non-volatile memory for emerging mobile markets
Spin as state variable for computation: prospects and perspectives
8T single-ended sub-threshold SRAM with cross-point data-aware write operation
Adaptive duty cycling for energy harvesting systems
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011
A low power SRAM architecture based on segmented virtual grounding
Manufacturability of low power CMOS technology solutions
Breaking the boundary for whole-system performance optimization of big data
Memory system energy (poster session): influence of hardware-software optimizations
A CMOS analog frontend for a passive UHF RFID tag
Faster Ternary and Binary Neural Network Inference on CPU by Reducing Popcount Overhead
Design challenges for mobile communication devices
New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM
Reduction of minimum operating voltage (V DDmin ) of CMOS logic circuits with post-fabrication automatically selective charge injection
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005
OFHE: An Electro-Optical Accelerator for Discretized TFHE
Low-voltage memories for power-aware systems
Minimizing data center cooling and server power costs
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring
Challenges on designing electrostatic discharge protection solutions for low power electronics
FV encoding for low-power data I/O
LAXOR: A Bit-Accurate BNN Accelerator with Latch-XOR Logic for Local Computing
A low power high noise immunity boost DC-DC converter using the differential difference amplifiers
Techniques for fast circuit simulation applied to power estimation of CMOS circuits
Write-optimized reliable design of STT MRAM
Model to hardware matching: for nano-meter scale technologies
A 6µw, 100kbps, 3-5ghz, UWB impulse radio transmitter
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler
MemRaptor: Magnetoresistive Array as Matrix Vector Multiplication and Transcendental Function Operator for NLP Applications
HA 2 TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI
Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy
QuAKE: Speeding up Model Inference Using Quick and Approximate Kernels for Exponential Non-Linearities
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
Instruction-driven clock scheduling with glitch mitigation
Diffusion-Enhanced Graph Transformer with Reinforcement Learning for Transferable Analog Circuit Optimizer
3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files
Value-driven Synthesis for Neural Network ASICs
It is all about power analysis, exploration and trade-offs
E-Spector: Online energy inspection for Android applications
A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration
Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning
Energy-efficient motion estimation using error-tolerance
E-Flash: Energy-Efficient DNN Mapping on NAND Flash Memory with State-Switching Algorithm
Tradeoff between energy savings and privacy protection in computation offloading
A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications
Object-based local dimming for LCD systems with LED BLUs
Checkpointing alternatives for high performance, power-aware processors
A self-optimizing embedded microprocessor using a loop table for low power
Extending the Moore's law by exploring new data center architecture: Invited Paper
On Effective and Efficient Quality Management for Approximate Computing
Identifying Efficient Dataflows for Spiking Neural Networks
Tradeoffs in power-efficient issue queue design
Power reduction of multiple disks using dynamic cache resizing and speed control
Hybrid dynamic thermal management based on statistical characteristics of multimedia applications
Power signal processing: a new perspective for power analysis and optimization
Low power integrated scan-retention mechanism
Dynamic power gating with quality guarantees
EcoMicro: A Miniature Self-Powered Inertial Sensor Node Based on Bluetooth Low Energy
Conditional pre-charge techniques for power-efficient dual-edge clocking
Design benchmarking to 7nm with FinFET predictive technology models
A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receivers
Gesture-SNN: Co-optimizing accuracy, latency and energy of SNNs for neuromorphic vision sensors
Battery assignment and scheduling for drone delivery businesses
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
Design Optimization of 3D Multi-Processor System-on-Chip with Integrated Flow Cell Arrays
Fully depleted CMOS/SOI device design guidelines for low power applications
Processor caches with multi-level spin-transfer torque ram cells
Instruction fetch energy reduction using loop caches for embedded applications with small tight loops
Power-optimal pipelining in deep submicron technology
Enhancing Low-Precision Deep Learning: A Posit8 Framework for Energy Efficient DNN Training
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC
Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems
FPGA glitch power analysis and reduction
Steady state driven power gating for lightening always-on state retention storage
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses
Power delivery for high performance microprocessors
Clock skew optimization for peak current reduction
Battery management technology for an electric vehicle
A tunable bus encoder for off-chip data buses
Low power motion estimation design using adaptive pixel truncation
Dynamic indexing: concurrent leakage and aging optimization for caches
Enhancing DRAM Self-Refresh for Idle Power Reduction
Low-power dual-element memristor based memory design
DuraCap: a supercapacitor-based, power-bootstrapping, maximum power point tracking energy-harvesting system
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits
Analyzing the energy consumption of security protocols
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
CCP: common case promotion for improved timing error resilience with energy efficiency
Static low power verification at transistor level for SoC design
Thread shuffling: combining DVFS and thread migration toreduce energy consumptions for multi-core systems
2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019
Design and CAD methodologies for low power gate-level monolithic 3D ICs
Power optimal MTCMOS repeater insertion for global buses
Low-leakage asymmetric-cell SRAM
A power-aware SWDR cell for reducing cache write power
Quantifying the Overheads of Modular Multiplication
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
The whys and hows of thermal management
A biomass-based marine sediment energy harvesting system
Replication-aware leakage management in chip multiprocessors with private L2 cache
International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014
Systolic Array Acceleration of Spiking Neural Networks with Application-Independent Split-Time Temporal Coding
Energy-aware architectures for a real-valued FFT implementation
Electromigration study of power-gated grids
An adaptive on-chip voltage regulation technique for low-power applications
An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
An evaluation of code and data optimizations in the context of disk power reduction
Low voltage analog circuits using standard CMOS technology
Cooling and power consideration for semiconductors into the next century
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
A design space exploration of transmission-line links for on-chip interconnect
A High-Performance Dataflow-Based ORB Extractor Accelerator for SLAM
ILP-based optimization of sequential circuits for low power
GUMSO: Gating Unnecessary On-Chip Memory Slices for Power Optimization on GPUs
Design techniques for high performance, energy efficient control logic
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate
Low-power VLSI decoder architectures for LDPC codes
Minimizing energy consumption of banked memories using data recomputation
AC-1: a clock-powered microprocessor
vCap: Adaptive power capping for virtualized servers
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
FLASH: Content-based Power-saving Design for Scrolling Operations in Browser Applications on Mobile OLED Devices
PUFFIN: An Efficient DNN Training Accelerator for Direct Feedback Alignment in FeFET
Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits
Prediction-Guided Performance-Energy Trade-off with Continuous Run-Time Adaptation
Composable accelerator-rich microprocessor enhanced for adaptivity and longevity
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS
High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar
The parallel computing landscape: a Berkeley view
An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs
Throughput of multi-core processors under thermal constraints
HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency Capping Governor for Energy-Efficient Mobile Gaming
Multi-Pattern Active Cell Balancing Architecture and Equalization Strategy for Battery Packs
Using dynamic cache management techniques to reduce energy in a high-performance processor
Modeling and analysis of leakage power considering within-die process variations
Can Photonic Interconnects be used for High-Throughput Memory Access in FHE Accelerators?
Passive precharge and rippled power logic (PPRPL)
Power-Aware Heart Rate Monitoring using Particle Filters
Maximizing efficiency of solar-powered systems by load matching
Frequency and time domain analysis of power delivery network for monolithic 3D ICs
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks
Theory and practical implementation of harmonic resonant rail driver
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Register file caching for energy efficiency
Energy-efficient signal processing via algorithmic noise-tolerance
High density capacitance structures in submicron CMOS for low power RF application
ShiftMask: Dynamic OLED power shifting based on visual acuity for interactive mobile applications
Odd/even bus invert with two-phase transfer for buses with coupling
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results
Low power pipelining of linear systems: a common operand centric approach
A high-performance low-power nanophotonic on-chip network
A heuristic machine learning-based algorithm for power and thermal management of heterogeneous MPSoCs
On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter
Transforming set data types to power optimal data structures
Low power startup circuits for voltage and current reference with zero steady state current
The impact of data characteristics and hardware topology on hardware selection for low power DSP
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model
Automated selective multi-threshold design for ultra-low standby applications
Low-power embedded SRAM macros with current-mode read/write operations
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies
Energy-aware instruction-set customization for real-time embedded multiprocessor systems
Switching activity analysis for sequential circuits using Boolean approximation method
STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs
Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations
A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage Systems
Lightweight set buffer: low power data cache for multimedia application
Transition reduction in carry-save adder trees
When Climate Meets Machine Learning: Edge to Cloud ML Energy Efficiency
High-level power estimation
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007
Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications
PASAP: power aware structured ASIC placement
SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing
V t balancing and device sizing towards high yield of sub-threshold static logic gates
Signal strength-aware adaptive offloading for energy efficient mobile devices
Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits
Thermal Challenges and Opportunities for Off-the-shelf 3D-stacked CPUs
Energy efficient task scheduling on a multi-core platform using real-time energy measurements
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
DiReCt: Resource-Aware Dynamic Model Reconfiguration for Convolutional Neural Network in Mobile Systems
Energy-efficient scheduling on heterogeneous multi-core architectures
A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Process variation aware cache leakage management
Weight-Aware Activation Mapping for Energy-Efficient Convolution on PIM Arrays
MIN: a power efficient mechanism to mitigate the impact of process variations on nanophotonic networks
A resonant clock generator for single-phase adiabatic systems
Sparrow ECC: A Lightweight ECC Approach for HBM Refresh Reduction towards Energy-efficient DNN Inference
Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs
Examining the Robustness of Spiking Neural Networks on Non-ideal Memristive Crossbars
Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores
Entry control in network-on-chip for memory power reduction
Energy stealing - an exploration into unperceived activities on mobile systems
Integrated resynthesis for low power
Scheduling for power reduction in a real-time system
Neuromorphic Edge Computing: Challenges, Opportunities, and Current Solutions
Analytical energy dissipation models for low-power caches
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices
Microprocessor pipeline energy analysis
Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches
A Li-Ion Battery Charge Protocol with Optimal Aging-Quality of Service Trade-off
A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp
Slumber: static-power management for GPGPU register files
Low-power mapping of behavioral arrays to multiple memories
Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration
Effects of elevated temperature on tunable near-zero threshold CMOS
Battery capacity measurement and analysis using lithium coin cell battery
Energy efficient scheduling for multithreaded programs on general-purpose processors
Reducing transitions on memory buses using sector-based encoding technique
An improved clocking methodology for energy efficient low area AES architectures using register renaming
Hardware-friendly Hessian-driven Row-wise Quantization and FPGA Acceleration for Transformer-based Models
55nm CMOS Analog Circuit Implementation of LIF and STDP Functions for Low-Power SNNs
Reducing reorder buffer complexity through selective operand caching
Robust ultra-low power sub-threshold DTMOS logic
Energy minimization using multiple supply voltages
Power comparisons for barrel shifters
QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Custom feedback control: enabling truly scalable on-chip power management for MPSoCs
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
Low-power adaptive filter architectures via strength reduction
Ranking servers based on energy savings for computation offloading
Extending the lifetime of media recorders constrained by battery and flash memory size
Thermal-aware sampling in architectural simulation
Power reduction through work reuse
Understanding and minimizing ground bounce during mode transition of power gating structures
Snug set-associative caches: reducing leakage power while improving performance
A multiple clocking scheme for low power RTL design
A CMOS low power current-mode polyphase filter
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS
Reducing instruction fetch energy with backwards branch control information and buffering
A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime
Energy-efficient load and store reuse
A low-power design method using multiple supply voltages
Thermal Aware Design Methodologies for System On Chip Application Processor
An architecture for energy efficient sphere decoding
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998
Low-swing interconnect interface circuits
TruncQuant: Truncation-Ready Quantization for DNNs with Flexible Weight Bit Precision
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation
StoRM: a stochastic recognition and mining processor
Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design
Low delay-power product CMOS design using one-hot residue coding
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines
On the latency, energy and area of checkpointed, superscalar register alias tables
Do our low-power tools have enough horse power? (panel session) (title only)
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)
Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects
DeLight: Adding Energy Dimension To Deep Neural Networks
Low-energy for deep-submicron address buses
A low power SRAM using auto-backgate-controlled MT-CMOS
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors
Temporal vision-guided energy minimization for portable displays
Energy characterization of a tiled architecture processor with on-chip networks