yusuke1997/dblp-id-title huggingface dataset:
A Power-Efficient Parameter Quantization Technique for CNN Accelerators
Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip
Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays
Blind Data Adversarial Bit-flip Attack against Deep Neural Networks
Fit4MedRob: A Next-Generation Platform for Intelligent Robotic Rehabilitation
Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems
Application Analysis for Parallel Processing
Visualization of Multi-objective Design Space Exploration for Embedded Systems
Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation
An HLS Algorithm for the Direct Synthesis of Complex Control Flow Graphs Into Finite State Machines with Implicit Datapath
A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling
Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques
Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation
Optical Fault Injection Attacks against Radiation-Hard Shift Registers
Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures
Shift Invert Coding (SINV) for Low Power VLSI
High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGA
Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration
Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model
Dynamic encoding, a lightweight combined countermeasure against hardware attacks
Polynomial Formal Verification of Approximate Adders
A Novel Digital Ultrasound System for Experimental Research Activities
Deep Sub-100 nm Design Challenges
Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems
Profiling Bluetooth and Linux on the Xilinx Virtex II Pro
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
An Application of Hyper-Heuristics to Flexible Manufacturing Systems
Worst-Case Throughput Analysis of SDF-Based Parametrized Dataflow
Area-Efficient Multi-moduli Squarers for RNS
Multimodal Image Registration between SWIR and LWIR Images in an Embedded System
A RISC-V based platform supporting mixed timing-critical and high performance workloads
Nepteron Processor for Real-Time Computation of Conductance-Based Neuronal Networks
Unraveling Parallelism in Automated Workload Modeling for Distributed Cyber-Physical Systems
Lifetime Analysis in Heterogeneous Sensor Networks
Towards a Real-Time Smart Prognostics and Health Management (PHM) of Safety Critical Embedded Systems
A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption
AXIOM: A Hardware-Software Platform for Cyber Physical Systems
An Asynchronous Victim Cache
Adaptive Cache Memories for SMT Processors
Digital Twins Benefits and Challenges from Intelligent Motion Control Point of View
Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration
Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors
Improved Precision of Coarse Grained Localization in Wireless Sensor Networks
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Improving Power of Cache and Register File through Critical Path Instructions
Fault Tolerant Duplex System with High Availability for Practical Applications
Optimizing UAV location awareness telemetry data for Low Power Wide Area Network
Pre-Integrated Architectures for sustainable complex Cyber-Physical Systems
Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata
Green Computing: Power Optimisation of VFI-Based Real-Time Multiprocessor Dataflow Applications
Authenticated Encryption Schemes on Java Card
On the Validation of Multi-Level Personalised Health Condition Model
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
A High Speed FPGA Implementation of the Rijndael Algorithm
Topological BDP Fault Simulation Method
Device Context Classification for Mobile Power Consumption Reduction
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
Automation and Optimization of Coverage-driven Verification
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n)
Iteration-Based Trade-Off Analysis of Resource-Aware SDF
Flexible and Resource Efficient FPGA-Based Quad Data Rate Memory Interface Design for High-Speed Data Acquisition Systems
Efficient Parallel Rotation of Hyperspectral Images on FPGA-Accelerated Platforms
Heavy-Hitter Detection Using a Hardware Sketch with the Countmin-CU Algorithm
Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources
Design of a Faithful LNS Interpolator
Multi-objective Optimal FSM State Assignment
Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites
On the Need for Passive Monitoring in Sensor Networks
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
SAND5G - Security Assessments for Networks and Services in 5G Networks
Towards Resilient Quasi Delay Insensitive Conditional Control Elements
Single-Trace Attack on NTRU Decryption with Machine Learning and Template Profiling
An IoT-Based Framework for Elderly Remote Monitoring
SystemC-based Design Methodology for Reconfigurable System-on-Chip
Revisiting the Cache Effect on Multicore Multithreaded Network Processors
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip
FC-Min: A Fast Multi-Output Boolean Minimizer
Compiler-Directed Dynamic Memory Disambiguation for Loop Structures
Architectural Vulnerability Factor Estimation with Backwards Analysis
Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis
Partition Based Dynamic 2D HW Multitasking Management
TEST: Assessing NoC Policies Facing Aging and Leakage Power
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar
Comparison of Approximate Circuits for H.264 and HEVC Motion Estimation
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects
A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms
Efficient Implementations of Multi-pumped Multi-port Register Files in FPGAs
A Hardware Accelerator for Quantile Estimation of Network Packet Attributes
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis
Gracefully Degrading Circuit Controllers Based on Polytronics
End-to-End Real-Time Communication in Mixed-Criticality Systems Based on Networked Multicore Chips
QC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization
ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications
FPGA-based Design Approaches of Keccak Hash Function
Software Fault Tolerance: The Evaluation by Functional Verification
A Predictor-Based Power-Saving Policy for DRAM Memories
A Monitoring-Aware Network-on-Chip Design Flow
Power Management Aware Low Leakage Behavioural Synthesis
White-Box Error Effect Simulation for Assisted Safety Analysis
Framework of Key Enabling Technologies for Safe and Autonomous Drones' Applications
Error Correction Method Based on the Short-Duration Offline Test
Recursive Bi-Partitioning of Netlists for Large Number of Partitions
Voltage Glitch Attacks on Mixed-Signal Systems
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration
Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPC
Simulation-Based Analysis of Cyberphysical Systems
New Digital Control Technique for Improving Transient Response in DC - DC Converters
P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems
Challenges and Opportunities of IoT and AI in Pneumology
HTCC: Haskell to Handel-C Hardware Compiler
Energy Modeling and Architecture Exploration for Emotion Detection Systems
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications
2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013
Virtual White Cane Featuring Time-of-Flight 3D Imaging Supporting Visually Impaired Users
Dynamic Multi-Accelerator Management for Deep Learning Applications on the FPGA Edge
Comparison of Enhanced Markov Models and Discrete Event Simulation: For Evaluation of Probabilistic Faults in Safety-Critical Real-Time Task Sets
Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor
Generation of a Diagnosis Model for Hybrid-Electric Vehicles Using Machine Learning
A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks
A Novel Specification Model for IP-based Design
To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel Implementation
An Efficient List-Based Scheduling Algorithm for High-Level Synthesis
The ACROSS MPSoC - A New Generation of Multi-core Processors Designed for Safety-Critical Embedded Systems
The IoTwins Methodology and Platform to Implement and Operate Digital Twins-based I4.0 Applications in the Cloud Continuum
Functional Verification of a USB Host Controller
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Mixed Time-Criticality Process Interferences Characterization on a Multicore Linux System
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques
Structural Self-Adaptation for Decentralized Pervasive Intelligence
Design of a Two Dimensional PRSI Image Processor
Enhanced Duplication Method with TMR-Like Masking Abilities
Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks
ESAS: Exponent Series based Approximate Square Root Design
CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video
Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach
SUT-RNS Residue-to-Binary Converters Design
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates
TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs
Analysis of the Behavior of Ozone Therapy in Chemotherapy-Induced Neuropathy Using Hyperspectral Imaging Technology
Software Techniques for Soft Error Resilience: the ASTRAEUS project
Fault Models Usability Study for On-line Tested FPGA
Seto: A Framework for the Decomposition of Petri Nets and Transition Systems
Energy Efficient Versatile Video Coding Decoder Using Lightweight Regression Models
Interesting Applications of Atmel AVR Microcontrollers
Variation-tolerant Design Using Residue Number System
An Approximate Carry Disregard Multiplier with Improved Mean Relative Error Distance and Probability of Correctness
A Lightweight Operating Environment for Next Generation Cognitive Radios
Wireless Sensor Tag and Network for Improved Clinical Triage
An Embedded Video Sensor for a Smart Traffic Light
Reliability and Power Management of Integrated Systems
The TEXTAROSSA Project: Cool all the Way Down to the Hardware
Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care
An Embedded FTL for SSD RAID
Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization
An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models
ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems
Parallel Native-Simulation for Multi-processing Embedded Systems
FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories
On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks
Vital Signs Remote Management System for PDAs
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes
Pseudo-Random Pattern Generator Design for Column-Matching BIST
Test Decompressor Effectivity Improvement
Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven Binaries
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator
Automatic Controller Detection for Large Scale RTL Designs
On-chip Monitoring: A Light-Weight Interconnection Network Approach
Testability Estimation Based on Controllability and Observability Parameters
Counterfeit IC Detection By Image Texture Analysis
Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools
A Study of Performance and Power Consumption Differences Among Different ISAs
Scheduling and Assignment for Real-time Embedded Systems with Resource Contention
Instruction Precomputation for Fault Detection
Low-Cost Platform-Independent FPGA Based Real-Time Systems Tester
A Comprehensive Trade-off Analysis on the CCSDS 131.2-B-1 Extended ModCod (SCCC-X) Implementation
Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
A Concept for Logic Self Repair
Energy-Efficient Radix-4 Belief Propagation Polar Code Decoding Using an Efficient Sign-Magnitude Adder and Clock Gating
Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation
Harnessing Performance Variability: A HPC-Oriented Application Scenario
Analyzing Bus Load Data Using an FPGA and a Microcontroller
Embedded Multimodal Registration of Visible Images on Long-Wave Infrared Video in Real Time
Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude
Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI
NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories
CirKet: A Performance Efficient Hybrid Switching Mechanism for NoC Architectures
Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment
Towards optimal reconfigurable constant multipliers
JAAVR: Introducing the Next Generation of Security-Enabled RFID Tags
Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints
SAT-Hard: A Learning-Based Hardware SAT-Solver
Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality Systems
Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application Program
A Hypervisor Architecture for Low-Power Real-Time Embedded Systems
Scripting the Unpredictable: Automate Fault Injection in RTL Simulation for Vulnerability Assessment
Virtual Platform for Wireless Sensor Networks
Timing- / Power-Optimization for Digital Logic Based on Standard Cells
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher
PERMS: A Bit Permutation Instruction for Accelerating Software Cryptography
pyHybrid Analysis: A Package for Semantics Analysis of Hybrid Systems
Reachability Analysis for Formal Verification of SystemC
Master-Slave Control Structure for Massively Parallel System on Chip
Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell
Real-Time Polling Task: Design and Analysis
Energy-Aware FPGA-based Architecture for Wireless Sensor Networks
Evict+Spec+Time on RISC-V: Gem5-Based Implementation and Microarchitectural Analysis
Gigasample Time-Interleaved Delta-Sigma Modulator for FPGA-Based All-Digital Transmitters
Efficient Rapid Prototyping of Image and Video Processing Algorithms
Stochastic Logic Realization of Matrix Operations
FPGA Trojan Detection Using Length-Optimized Ring Oscillators
Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number Systems
Novel Approximate Absolute Difference Hardware
Software Modification Aided Transient Error Tolerance for Embedded Systems
True Random Number Generator Based on ROPUF Circuit
Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW
A Supervisory Control Approach for Scheduling Real-time Periodic Tasks on Dynamically Reconfigurable Platforms
Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation
Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation
Storage-Aware Value Prediction
Designing a Binary Neural Network Co-processor
Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology
Non-intrusive NoC DFS for Soft Real-Time Multimedia Applications
Evaluating Energy Consumption in Wireless Sensor Networks Applications
Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms
Compositional Dataflow Modelling for Cyclo-Static Applications
Platform Independent Software Analysis for Near Memory Computing
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis
Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
Accelerating Clifford Algebra Operations Using GPUs and an OpenCL Code Generator
Performance-Effective Compaction of Standard-Cell Libraries for Digital Design
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems
Monitoring-Aware Virtual Platform Prototype of Heterogeneous NoC-Based Multicore SoCs
28th Euromicro Conference on Digital System Design, DSD 2025, Salerno, Italy, September 10-12, 2025
AnTiQ: A Hardware-Accelerated Priority Queue Design with Constant Time Arbitrary Element Removal
OPTIMIST: Optimised Video Content Delivery Chains over Joint Multi-Access Edge Computing and 5G Radio Network Infrastructures
System-Level Power Optimization
H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials
A Constraints Programming Approach for Fabric Cell Synthesis
Software-Only Control-Flow Integrity Against Fault Injection Attacks
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance
DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design Education
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation
SoC-SLAM: FPGA-Based Hardware/Software Co-Design for Real-Time Visual SLAM Front-End and Back-End Acceleration
Multi-media Applications and Imprecise Computation
An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms
Unraveling the Mystery of NVIDIA's Unified Memory for Safety-Critical GPU Systems
Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction
Automatic Polynomial Formal Verification of a Floating-Point Multiplier
A Wireless Sensor Platform for Assistive Technology Applications
Hierarchical Constraint Conscious RT-level Test Generation
High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs
A General Framework for Average-Case Performance Analysis of Shared Resources
A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed for Evolvability
2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany
Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
A Flexible Research Testbed for C-RAN
Two's Complement: Monitoring Software Control Flow Using Both Power and Electromagnetic Side Channels
A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis
Variable-Length Instruction Set: Feature or Bug?
Efficient Fault Simulation of SystemC Designs
Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms
UML/MARTE Methodology for Automatic SystemC Code Generation of Openmax Multimedia Applications
Challenges of Return-Oriented-Programming on the Xtensa Hardware Architecture
High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process
A Hardware Accelerator for Edge Detection in High-Definition Video using Cellular Neural Networks
SAFEXPLAIN: a Complete Approach Towards Trustworthy AI-Based Safety-Critical Systems
Distributed Collaborative Design of a Mixed-Signal IP Component
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking
Towards a Safe End-to-End AI framework: MISRA C-Compliant YOLO for Object Detection
Analysis and Visualization of Product Memory Layout in IP-XACT
FPGA Based Controller for Heterogeneous Image Processing System
Logic Synthesis for Switching Lattices by Decomposition with P-Circuits
Packet Classification with Limited Memory Resources
System Design of an Open-Source Cloud-Based Framework for Internet of Drones Application
Wireless Sensor Network Implementation for Industrial Linear Position Metering
A Multi-Lingual Synthesis and Verification Environment
A Survey on Multi-unmanned Aerial Vehicle Communications for Autonomous Inspections
Adaptive MEMS Mirror Control for Reliable Automotive Driving Assistance Applications
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project
Design of a High Performance Traffic Generator on Network Processor
Dynamically Reconfigurable Architecture with Atomic Configuration Updates for Flexible Regular Expressions Matching in FPGA
Dynamic Frequency Boosting of RISC-V FPSoCs Through Monitoring Runtime Path Activations
True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits
HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic
Fundamentals of Reversible Logic and Computing
A Global Routing Technique for Wave-Steering Design Methodology
6G-TakeOff: Holistic 3D Networks for 6G Wireless Communications
Automated Design of High Performance Integer Arithmetic Cores on FPGA
Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework
On the Cascade Implementation of Multiple-Output Sparse Logic Functions
Impact of Compiler Optimization Flags on Side-Channel Information Leakage of SipHash Algorithm
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation
Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
Multi-log Processor - Towards Scalable Event-Driven Multiprocessors
SMAC: Smart Systems Co-design
Synthesis for Testability: Polynomial Test Pattern Generation for KFDD Circuits
Revisiting Explicit Enumeration for Exact Synthesis
pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems
Bit-Shift-Based Accelerator for CNNs with Selectable Accuracy and Throughput
A Hybrid Delay Model for Interconnected Multi-Input Gates
Efficient Clustering of DERs in a Virtual Association for Profit Optimization
26th Euromicro Conference on Digital System Design, DSD 2023, Golem, Albania, September 6-8, 2023
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications
Event Monitor Validation in High-Integrity Systems
Improved Task Scheduler for Dual-Core Real-Time Systems
Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning
BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory