yusuke1997/dblp-id-title huggingface dataset:
HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC
Sphere Decoder for Massive MIMO Systems
Zero-crossing detector for a piezoelectric energy harvester
A CMOS MF energy harvesting and data demodulator receiver for wide area low duty cycle applications with 230 mV start-up voltage
Practical Stimulus Design for a Multi-Tone Fit
1/f-Noise and Offset Cancellation for Rail-to-Rail Single-Slope ADCs in MEA Applications
Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
A continuous-time IR-UWB RAKE receiver for coherent symbol detection
Optimal register allocation by augmented left-edge algorithm on arbitrary control-flow structures
A fully synthesized all-digital VCO-based analog-to-digital converter
An ultra wide-band adaptive frequency divider for mm-wave PLL applications
Oscillation ring testing methodology of TSVs in 3D stacked ICs
How Diversity Affects Deep-Learning Side-Channel Attacks
IoT-based fall detection system with energy efficient sensor nodes
A measurement technique for the vibrating wire sensors
A 0.13µm CMOS ΔΣ PLL FM transmitter
Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS
On Designing PUF-Based TRNGs with Known Answer Tests
High-voltage pulse-triggered SR latch level-shifter design considerations
Time-Predictable Distributed Shared Memory for Multi-Core Processors
Contention aware scheduling for NoC-based real-time systems
On wafer X-parameter based modeling of a switching cascode power amplifier
A mixed mode design flow for multi GHz ADPLLs
Design of wideband mixer and VGA for Software Defined Radio in RFID application
Low-Power Regulator for Micro Energy Harvesting Applications
Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring
High-speed Sampling System in CMOS
A comparison of serial interfaces on energy critical systems
An analog receiver front-end for capacitive body-coupled communication
Trends in university programs in nanoelectronics and microsystems
Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL
Energy-Delay Trade-Offs in Instruction Register File Design
KL-cut based digital circuit remapping
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS
2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013
Intermediate nodes selection schemes for Network Coding in Network-on-Chips
An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage
Initial version of Matlab/Simulink based tool for VHDL code generation and FPGA implementation of Elementary Generalized Unitary rotation
Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol
A digital PLL with a multi-delay coarse-fine TDC
Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses
Stimuli generator for testing processes in VHDL
Subthreshold nano-watt front-end amplifier for wireless ECG applications
Capacitor-free, low drop-out linear regulator in a 180 nm CMOS for hearing aids
Computational and implementation complexity of polynomial evaluation schemes
On Applications of Configurable Approximation to Irregular Voltage
A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS
Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems
End-to-End Approximation for Characterizing Energy Efficiency of IoT Applications
OpenCL programmable exposed datapath high performance low-power image signal processor
A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier
Current-steering DAC linearisation by impedance transformation
Architecture-level analysis and evaluation of transient errors on NoC
Modular layout-friendly cell library design applied for subthreshold CMOS
Comparison of time-varying and non-time-varying Volterra analysis for finding distortion contributions in mixers
Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes
A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta Modulators
Evaluation of SU8 photo polymer for microwave packaging applications
A 36 nW trimless voltage reference with low sensitivity to PVT variations
A 5.3 pJ/pulse impulse-radio ultra-wideband pulse-generator for band group # 6
Linearization of RF power amplifiers using an enhanced memory polynomial predistorter
Electrical and human feedback
A CMOS High Resolution Multi-Edge Delay Generator
A power scalable and high pulse swing UWB transmitter for wirelessly-powered RFID applications
SRT radix-2 dividers with (5, 4) redundant representation of partial remainder
An analytical model for spectral peak frequency prediction of substrate noise in CMOS substrates
Electronics for characterizing and using photovoltaics
Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process
The REPLICA on-chip network
Instruction Extension of a RISC-V Processor Modeled with IP-XACT
Active charge pumping power-saving technique for SC integrators
On the Design of a CMOS-integrated Load Modulated Balanced Amplifier
Architectural trends in GHz speed DACs
A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter
An FPGA-based high-performance wireless vibration analyzer
A RF Pulse-Width and Pulse-Position Modulator IC in 28 nm FDSOI CMOS
Dependability evaluation of SISO control-theoretic power managers for processor architectures
Test-driven modeling of embedded systems
Implementation of FPGA based DSP module for CW Doppler radar: Preliminary results
Modeling and predistortion of envelope tracking power amplifiers using a memory binomial model
A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network
CMOS digital design of a trusted virtual sensor
Nex generation digital front-end for multi-standard concurrent reception
Natural logarithm and division floating-point high throughput co-processor implemented in FPGA
A 0.0186 mm 2 , 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants
Single chip wireless condition monitoring of power semiconductor modules
FPGA implementation and integration of a reconfigurable CAN-based co-processor to the coffee risc processor
Low-latency Packet Parsing in Software Defined Networks
Matrix Decomposition for Massive MIMO Detection
Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment
A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS
Carrier frequency and sampling rate offsets effect on sub 6 GHz Massive MIMO
Nanoscale CMOS impulse radar - from research to product
Area and power reduction in DFT based channel estimators for OFDM systems
A Novel on-chip ultra-low power temperature sensing scheme
An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks
Energy efficient FPGA based hardware accelerators for financial applications
DRAM row-hammer attack reduction using dummy cells
A survey on mixed operating mode/self synchronization
Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology
Customizing 6LoWPAN networks towards Internet-of-Things based ubiquitous healthcare systems
A Fault-Tolerant Time-Predictable Processor
Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors
A Hardware Inference Accelerator for Temporal Convolutional Networks
An accurate fault location method based on configuration bitstream analysis
Evaluation of the vertical magnetic field generated by a spiral planar coil
Variability-aware design of 55 nA current reference with 1.4% standard deviation and 290 nW power consumption
An improved source-follower based Sallen-Key continuous-time biquadratic cell with auxiliary path
Implementation of a performance optimized database join operation on FPGA-GPU platforms using OpenCL
Configurable RTL model for level-1 caches
An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs
Design and simulation of a quaternary memory cell based on a physical memristor
Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictions
Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders
Performance evaluation of classical differential rectifier by using forward body biasing technique
Application of spread-spectrum techniques to class-E DC/DC converters: some preliminary results
Dynamically reconfigurable real-time hardware architecture for channel utilisation analysis in industrial wireless communication
A simple all MOS voltage reference for RFID applications
Workload prediction for runtime resource management
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End
A 1V SiGe power amplifier for 81-86 GHz E-band
Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump
Design Considerations and Evaluation of a High-Speed SAR ADC
Multiphase digitally controlled oscillator for future 5G phased arrays in 90 nm CMOS
Executing secured virtual machines within a manycore architecture
Distributed systemc simulation on manycore servers
An efficient maximum power point tracking algorithm for solar PV panels
On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems
Solar panel modelling for low illuminance indoor conditions
A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS
Design of low phase noise K-band Voltage-Controlled Oscillator using 180 nm CMOS and integrated passive device technologies
Model-based rapid prototyping of multirate digital signal processing algorithms
A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet Classification
Exclusive control for compound operations on hardware transactional memory
A dependable ASIC architecture with RT-level rollback for controller soft error recovery
A 28 GHz SiGe QVCO and divider for an 81-86 GHz E-band beam steering transmitter PLL
A 97-106-GHz differential I-Q phase shifter in 28-nm CMOS
Low power Real Time Clock with high accuracy over large supply voltage range
High-efficiency peak-current-control non-inverting buck-boost converter using mode selection for single Ni-MH cell battery operation
Highly reliable and power efficient NOC interconnects
At-speed self-testing of high-performance pipe-lined processing architectures
A New Interpretation to Groszkowski's Effect
Effect of process variations in CMOS chips for radar beamforming
Ultra low power on-chip hybrid start-up for wireless sensor networks
Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches
An 85dB dynamic range transimpedance amplifier in 40nm CMOS technology
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces
A compact 0.3-10 GHz broadband stacked amplifier in 65nm standard CMOS
Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump Topology
Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture
Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades
Bivariate function approximation with encoded gradients
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems
Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory
Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology
A Design Approach for SiGe Low-Noise Amplifiers Using Wideband Input Matching
IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, Norway, October 27-28, 2020
A divide-by-three regenerative frequency divider using a subharmonic mixer
Biochips: The integrated circuit of biology
IEEE Nordic Circuits and Systems Conference, NORCAS 2016, Copenhagen, Denmark, November 1-2, 2016
A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural Amplifier
Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance
Hierarchical design of a low power standing wave oscillator based clock distribution network
A temperature sensor with 3σ inaccuracy of +0.5/-0.75 °C and energy per conversion of 0.65 μJ using a 0.18 μm CMOS technology
Polynomial modelling: Accuracy vs. shape
Validation of Pipelined Double-precision Floating Point operations in a multi-core environment implemented on FPGA using the ForSyDe/NoC system generator tool suite
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs
2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018
3.5 GHz triple cascaded current-reuse low noise amplifier
Self-formation processes in high-speed integrated circuits
Novel SRAM bias control circuits for a low power L1 data cache
Deembedding static nonlinearities of power amplifiers using least square error algorithm
A fault tolerant approach for application-specific Network-on-Chip
Designing at Millimeter-Wave: Lessons from a Triple Coil Variable Transformer
An Analogue Baseband Chain for a Magnetic Tunnel Junction Based RF Signal Detector
A GALS ASIC implementation from a CAL dataflow description
A Distributed DoS Detection Scheme for NoC-based MPSoCs
Empirical results on parity-based soft error detection with software-based retry
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology
Micro- and nano-electronics education in Vilnius Gediminas Technical University
A modified switching scheme for multiplexer based thermometer-to-binary encoders
Digital background calibration in continuous-time delta-sigma analog to digital converters
FPGA implementation of decimal processors for hardware acceleration
2011 NORCHIP, Lund, Sweden, November 14-15, 2011
An Embedded Programmable Processor for Compressive Sensing Applications
A 26 GHz UWB CMOS IR-UWB transmitter with on-chip balun
Using OpenCL to rapidly prototype FPGA designs
Sleep apnea pre-screening on neonates and children with shoe integrated sensors
Customization methodology of a Coarse Grained Reconfigurable architecture
Low power programmable frequency divider for IEEE 802.15.4a standard
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder
Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOI
A fault-aware low-energy spare core allocation in networks-on-chip
Wideband limit study of a GaN power amplifier using two-tone measurements
A noise coupled ΣΔ architecture using a Non Uniform Quantizer
Tandem Lange 3-dB 90° hybrid implemented on FR4 substrate
Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder
A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing
Hardware implementation of the exponential function using Taylor series
Design and analysis of high performance pulse ring VCO
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications
Interpolation by a prime factor other than 2 in low-voltage low-power ΣΔ DAC
Noise Considerations in Pulse-Shaping Based TIA Channel Designed for a Pulsed TOF Laser Radar Receiver
Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems
Analyzing Worst-case Delay-Buffer-Equation for wormhole networks on chip
1.8 W, 19 MHz envelope amplifier for envelope tracking and envelope elimination and restoration
FPGA implementation of elementary generalized unitary rotation with CORDIC based architecture
Systematic frequency planning for a high SFDR digital-IF RF-DAC-based transmitter
2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019
A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm
Combined RF and multilevel PWM switch mode power amplifier
2014 NORCHIP, Tampere, Finland, October 27-28, 2014
An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias
Micro rate gyroscopes based on surface acoustic waves
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
Design and evaluation of correlation accelerator in IEEE-802.11a/g receiver using a template-based Coarse-Grained Reconfigurable Array
Low power front end electronics for in-probe beamforming in ultrasound imaging
Silicon synapse designs for VLSI neuromorphic platform
Performance estimation of embedded applications on microcontrollers
Adaptive Power monitoring for self-aware embedded systems
Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS
Design of a highly linear, low noise, broad band up-converter for cognitive radio applications
A 500mV, 118nW, ∑Δ-Modulator ADC for Audio Detection in 28 nm FD-SOI
Unrolled layered architectures for non-surjective finite alphabet iterative decoders
A fault-tolerant and hierarchical routing algorithm for NoC architectures
Sensor data fusion with MPSoCSim in the context of electric vehicle charging stations
Fixed pattern noise correction for wide dynamic range CMOS image sensor with Reinhard tone mapping operator
Highly linear direct conversion receiver using customized on-chip balun
PathAware: A contention-aware selection function for application-specific Network-On-Chips
Analysis of a high-speed PCB design
Software-Defined Radio Assessment for Microwave Imaging Breast Cancer Detection
Yield modeling and yield-aware mapping for application specific networks-on-chip
Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme
Single Burst Depth-Resolving Raman Spectrometer Based on a SPAD Array with an On-Chip TDC to Analyse Heterogenous Liquid Samples
Area and power consumption trade-off for Σ-Δ decimation filter in mixed signal wearable IC
Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers
High-level synthesis for reduction of WCET in real-time systems
Origins of Intermodulation Distortion in A Pseudo-differential CMOS Beamforming Receiver
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM
A novel random approach to diagnostic test generation
Wideband RF detector design for high performance on-chip test
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud
A Low Power Front-end for Biomedical Fluorescence Sensing Applications
An AFE for Catheter-Based IEGM sensing with Inverter-based SAR ADC
Embedded low power clock generator for sensor nodes
Highly linear open-loop output driver design for high speed capacitive DACs
Limited active harmonic compensation in a grid-connected photovoltaic inverter
ESD induced EMS problems in digital IOs
A capacitance multiplier based on DBTA
Linearization of Active Transmitter Arrays in Presence of Antenna Crosstalk for 5G Systems
Challenges in IC design for hearing aids
A light-weight statically scheduled network-on-chip
A Real-Time Fast Ethernet Transceiver achieving Sub-ns Time Synchronization
Implementation of a highly-parallel soft-output MIMO detector with fast node enumeration
A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS
Phase noise improvement and noise modeling of type-I ADPLL with non-linear quantization effects
Design considerations for interface circuits to low-voltage piezoelectric energy harvesters
A 10 MHz bandwidth continuous-time delta-sigma modulator for portable ultrasound scanners
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing
Voltage multiplier arrangement for heavy load conditions in RF energy harvesting
The low delay low-pass FIR digital differentiators having flat passband and equiripple stopband
Design of a VCO-based ADC in 28 nm CMOS
Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs
Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-Propagation
Dual-Stage Phase Unwrapping
3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation
Design solutions for a low-power SoC platform using near-threshold voltages
Evaluation of digital predistortion using the USRP N200 software defined radio transceiver
Modeling and design of a dual-residue pipelined ADC in 130nm CMOS
Analysis of band-to-band mixing distortion contributions in some usual circuit topologies
Building Lumped Models for Measured Passive mm-wave Components
A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW Radar
Data type dependent energy consumption estimation
A 24GHz, 18dBm, Broadband, Three Stacked Power Amplifier in 28nm FDSOI
Self-heating and memory effects in RF power amplifiers explained through electro-thermal
Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs
Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology
Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design
Analyses of single-stage complementary self-biased CMOS differential amplifiers
Digital centric IF-DAC based heterodyne transmitter architecture
An experimental comparison between two widely adopted phase noise models
A 31.25/125MSps continuous-time ΔΣ ADC with 64/59db SNDR in 130nm CMOS
Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner
A wideband blocker-resilient RF front-end with selective input-impedance matching for direct-ΔΣ-receiver architectures
Cost effective FPGA probabilistic fault emulation
Electrical properties of CVD-graphene FETs
Fault-tolerant implementation of direct FIR filters protected using residue codes
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
Implementation of a dynamic wordlength SIMD multiplier
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS
Analysis of dead time losses in energy harvesting boost converters for implantable biosensors
A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems
Fast Fixed-point Bicubic Interpolation Algorithm on FPGA
Comparison of static and memory predistortion in envelope tracking system
A 500 mV, 4.5 mW, 16 GHz VCO with 33.3% FTR, designed for 5G applications
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters
IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP and International Symposium of System-on-Chip (SoC), Linköping, Sweden, October 23-25, 2017
Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator Startup
A integrated high voltage controller for a reconfigurable antenna array
Design of a Current Mode Multiplexed Circuit for Integrate & Fire Neuromorphic Systems
Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave Applications
Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks
Multi-Swarm based NoC Configuration and Synthesis
Process tolerant highly linear mixer output stage with feedforward linearity improvement method for a high-IF converter
Subsampling phase-locked loop behavioural modelling approach for phase noise evaluation
SynZEN: A hybrid TTA/VLIW architecture with a distributed register file
A highly compact, 16.8 dBm Pgat Ka-band power amplifier in 250 nm SiGe: C BiCMOS
10 GS/s 8-bit bipolar THA in SiGe technology
Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs