yusuke1997/dblp-id-title huggingface dataset:
Scalable FPGA Median Filtering via a Directional Median Cascade
Scientific Application Acceleration with Reconfigurable Functional Units
A Framework for Graph Machine Learning on Heterogeneous Architecture
FPGA Simulation Engine for Customized Construction of Neural Microcircuit
On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs
Architecture of a FPGA-based coprocessor: the PAR-1
FPGA Based High-Throughput Real-Time Feature Extraction for Modulation Classification
HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection
Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures
DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers
Configurable Transactional Memory
Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs
RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays
10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings
System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems
FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs
Power Visualization, Analysis, and Optimization Tools for FPGAs
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing
Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs
4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996
Improving the Accuracy of Arctan for Face Detection
Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware
Exploring the Random Network of Hodgkin and Huxley Neurons with Exponential Synaptic Conductances on OpenCL FPGA Platform
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model
Timing Fault Detection in FPGA-Based Circuits
Accelerating SpMV on FPGAs by Compressing Nonzero Values
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators
The Design of the Amalgam Reconfigurable Cluster
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Object Oriented Circuit-Generators in Java
A Scalable OpenCL-Based FPGA Accelerator for YOLOv2
A Reconfigurable Platform for Academic Purposes
Efficient Query Processing for Web Search Engine with FPGAs
Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs
Development System for FPGA-Based Digital Circuits
Programming Real-Time Autofocus on a Massively Parallel Reconfigurable Architecture Using Occam-pi
FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy
Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array
Acceleration of an FPGA router
A Stream-Based Configurable Computing Radio Testbed
Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits
Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures
31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023
An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization
Parallelization of MATLAB Applications for a Multi-FPGA System
Implementation of a Content-Scanning Module for an Internet Firewall
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
Metropolitan Road Traffic Simulation on FPGAs
GAME: Gaussian Mixture Model Mapping and Navigation Engine on Embedded FPGA
FPGA-based Acceleration for Tracking Audio Effects in Movies
Edge Accelerator for Lifelong Deep Learning using Streaming Linear Discriminant Analysis
Queue Machines: Hardware Compilation in Hardware
A Virtual Hardware Handler for RTR Systems
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware
Accelerating the Nonuniform Fast Fourier Transform Using FPGAs
Automating Production of Run-Time Reconfigurable Designs
SWiF: A Simplified Workload-Centric Framework for FPGA-Based Computing
SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGA
High Throughput Massive MIMO Signal Decoding Using Multi-Level Tree Search on FPGAs
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs
Power Side-Channel Attacks and Defenses for Neural Network Accelerators
Systematic Characterization of Programmable Packet Processing Pipelines
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware
SmartNIC-Based Distributed Shared Memory
Cost Effective Partial Scan for Hardware Emulation
An FPGA Implementation of Explicit-State Model Checking
Rotary Register File: A Micro-Architectural Primitive on FPGA
An Analysis of the Double-Precision Floating-Point FFT on FPGAs
Dual-Line-Systolic Array for High Performance CNN Accelerator
TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths
Functional Locking Modules for Design Protection of Intellectual Property Cores
Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems
An FPGA-Based BWT Accelerator for Bzip2 Data Compression
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis
Multiobjective Optimization of FPGA-Based Medical Image Registration
Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
Pattern Recognition and Reconstruction on an FPGA Coprocessor Board
PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors
UltraFormer: An Efficient Transformer for FPGAs
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders
Prototyping Architectural Support for Program Rollback Using FPGAs
RV-ESMC: Efficient Sparse Matrix Convolution Processor based on RISC-V Custom instructions for Edge Platforms
An Out-of-Order Load-Store Queue for Spatial Computing
Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs
Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing
Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware
Implementing Murf: Accelerating Large State Space Exploration on FPGAs
FCsN: A FPGA-Centric SmartNIC Framework for Neural Networks
FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks
An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware
The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer
8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings
High-Performance Parallel Radix Sort on FPGA
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube
Datapath-oriented FPGA mapping and placement for configurable computing
Cost-Effective Energy Monitoring of a Zynq-Based Real-Time System Including Dual Gigabit Ethernet
A Novel FPGA Accelerator of R(2+1)D
Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs
A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications
7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA
Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators: (Invited Paper)
Templatised Soft Floating-Point for High-Level Synthesis
Customizing Graphics Applications: Techniques and Programming Interface
Placement Optimization for NoC-Enhanced FPGAs
High-Level Synthesis of FPGA Circuits with Multiple Clock Domains
Automated target recognition on SPLASH 2
Raparo: Resource-Level Angle-Based Parallel Routing for FPGAs
A Quaternary FPGA Architecture Using Floating Gate Memories
Reconfigurable Molecular Dynamics Simulator
Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations
Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm
FPGA-Based Approximate Multiplier for FP8
Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement
Scalable Softcore Vector Processor for Biosequence Applications
A CAD Suite for High-Performance FPGA Design
GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic
Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware
An FPGA Based PCI-E Root Complex Architecture for Standalone SOPCs
A General Video Processing Framework on Edge Computing FPGAs
Hardware/Software Co-design for Machine Learning Accelerators
Power-Aware and Branch-Aware Word-Length Optimization
Terabyte Sort on FPGA-Accelerated Flash Storage
A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation
Bonded Force Computations on FPGAs
Harmonica: An FPGA-Based Data Parallel Soft Core
FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography
FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications
Corundum: An Open-Source 100-Gbps Nic
Revisiting Smalltalk-80 blocks: a logic generator for FPGAs
Run time reconfiguration of FPGA for scanning genomic databases
Rethinking Integer Divider Design for FPGA-Based Soft-Processors
Efficient Adaptable Streaming Aggregation Engine
Accelerating Big Data Analytics Using FPGAs
3D FFTs on a Single FPGA
A FCCM for dataflow (spreadsheet) programs
LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure
GraphStep: A System Architecture for Sparse-Graph Algorithms
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA
Implementation Results of Bloom Filters for String Matching
Hardware Acceleration of Short Read Mapping
Secure Configuration of a Field Programmable Gate Array
An Evaluation of High-Performance Embedded Processing on MPPAs
Defect tolerance on the Teramac custom computer
Optimizing Logarithmic Arithmetic on FPGAs
CS-Based Secured Big Data Processing on FPGA
SoftCUDA: Running CUDA on Softcore GPU
Customizable Compression Architecture for Efficient Configuration in CGRAs
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs
Ph.D. Project: Modernizing High-Level Hardware Design Workflows
Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference
Heterogeneous Platform to Accelerate Compute Intensive Applications
A Reconfigurable Hardware Interface for a Modern Computing System
A time-multiplexed FPGA
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms
Dynamically Scheduled Memory Operations in Static High-Level Synthesis
Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAs
Using Functional Programming to Generate an LDPC Forward Error Corrector
Density-Aware Parallel Hyperdimensional Genome Sequence Matching
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications
Reconfigurable Synthesizable Synchronization FIFOs
Hierarchical Clustering using Reconfigurable Devices
Massively Parallel Processors Generator for Reconfigurable System
Emulating Mammalian Vision on Reconfigurable Hardware
FUSE: Front-End User Framework for O/S Abstraction of Hardware Accelerators
Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures
FPGA-assisted Massive Packet Queueing and Traffic Shaping at the Network Edge
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor
Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
The Multiple Wordlength Paradigm
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines
From C to Fault-Tolerant FPGA-Based Systems
Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead
LGBM2VHDL: Mapping of LightGBM Models to FPGA
Design of a VLIW Compute Accelerator on the Transmogrifier-2
HLS-Compatible, Embedded-Processor Stream Links
Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications
Towards Synthesis-Free JIT Compilation to Commodity FPGAs
Reverse Engineering Neural Network Folding with Remote FPGA Power Analysis
FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP
Short-Read Mapping by a Systolic Custom FPGA Computation
Near-Storage Acceleration of Database Query Processing with SmartSSDs
A Hybrid Memory Sub-system for Video Coding Applications
A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs
A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
Totem: Custom Reconfigurable Array Generation
Automatic Offloading of Cluster Accelerators
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming
The Transmogrifier C hardware description language and compiler for FPGAs
High Performance Dynamic Communication on Reconfigurable Clusters
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs
Implementing an API for Distributed Adaptive Computing Systems
FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++
Mitrion-C Application Development on SGI Altix 350/RC100
PixelStreams-based implementation of videodetector
A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios
A LUT-Based Approximate Adder
An Effective Design System for Dynamically Reconfigurable Architectures
Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs
An Approach for Automatic Data Allocation in C to HDL Compilers
A Reconfigurable Computing Architecture for Microsensors
Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform
An FPGA-Based Fan Beam Image Reconstruction Module
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications
Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems
Reconfigurable computing in the era of post-silicon scaling [panel discussion]
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies
AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning
FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters
Scalable Network Function Virtualization for Heterogeneous Middleboxes
Hardware/Software co-design of a key point detector on FPGA
EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation
Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
One-Step Compilation of Image Processing Applications to FPGAs
RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine
Shared Memory Cache Organizations for Reconfigurable Computing Systems
Autotuning FPGA Design Parameters for Performance and Power
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems
ONT-X: An FPGA Approach to Real-time Portable Genomic Analysis
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference
Offset Pipelined Scheduling: Conditional Branching for CGRAs
Heterogeneous Floorplanner for FPGA
Reformulating the FPGA Routability Prediction Problem with Machine Learning
RIFFA: A Reusable Integration Framework for FPGA Accelerators
Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board
Fault simulation on reconfigurable hardware
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
Ph.D. Project AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration
Automatic Sliding Window Operation Optimization for FPGA-Based
AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs
An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures
ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills
Design of Networked Reconfigurable Encryption Engine
Improved Synthesis of Compressor Trees on FPGAs in High-Level Synthesis
Advanced Components in the Variable Precision Floating-Point Library
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA
Acceleration of the Pair-HMM Algorithm for DNA Variant Calling
Monobit Wideband Receiver with Integrated Dithering in FPGA
FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures
Compiling Higher Order Functional Programs to Composable Digital Hardware
A Comparative Study on the Architecture Templates for Dynamic Nested Loops
A Configurable Processor Synthesis System
A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor
Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network
A Heterogeneous FPGA Architecture for Support Vector Machine Training
NNReArch: A Tensor Program Scheduling Framework Against Neural Network Architecture Reverse Engineering
An Extensible I/O Subsystem
Ph.D. Project - IsoFPGA - A Novel CMOS Galvanic Isolation for Remote Physical Attacks in Multi-tenant Cloud FPGA
The Case for Dynamic Execution on Dynamic Hardware
Automated Least-Significant Bit Datapath Optimization for FPGAs
Analog In-Memory Computing Enhanced FPGA for High-Throughput and Energy-Efficient Acceleration
Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors
Accelerating Bit Error Rate Testing Using a System Level Design Tool
Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms
Analysis of the XC6000 Architecture for Embedded System Design
Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware
if-ZKP: Intel FPGA-Based Acceleration of Zero Knowledge Proofs
Optimizing Reconfigurable Recurrent Neural Networks
Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm
Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms
Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers
Configuration Compression for Virtex FPGAs
Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications
28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2020, Fayetteville, AR, USA, May 3-6, 2020
On Bit-Serial NoCs for FPGAs
High-Rate Machine Learning for Forecasting Time-Series Signals
Moyogi: A Memory-Centric Accelerator for Low-Latency Random Forest Inference on Embedded Devices
Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch
Configuration Relocation and Defragmentation for Reconfigurable Computing
Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance
Floating Point Unit Generation and Evaluation for FPGAs
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS
MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-Chip
24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016
Exploiting Reconfigurable Hardware for Network Security
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems
Upgrade of FPGA Range-Limited Molecular Dynamics to Handle Hundreds of Processors
AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks
A Scripting Engine for Combining Design Transformations
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing
Configuration Caching Management Techniques for Reconfigurable Computing
FPGA Acceleration of Recurrent Neural Network Based Language Model
VENICE: A Compact Vector Processor for FPGA Applications
An FPGA-Based Optical IOH Architecture for Embedded System
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
SHIP: Storage for Hybrid Interconnected Processors
An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration
A Delay-based PUF Design Using Multiplexers on FPGA
Energy Reduction through Differential Reliability and Lightweight Checking
A High Throughput No-Stall Golomb-Rice Hardware Decoder
Hot & Spicy: Improving Productivity with Python and HLS for FPGAs
Hardware Compilation from Machine Code with M2V
High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping
Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs
Mixing fixed and reconfigurable logic for array processing
Update Latency Optimization of Packet Classification for SDN Switch on FPGA
A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities
Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays
Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer
Communications Scheduling for Concurrent Processes on Reconfigurable Computers
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark
An Efficient Architecture for Floating-Point Eigenvalue Decomposition
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification
A Case for Common-Case: On FPGA Acceleration of Erasure Coding
26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, April 29 - May 1, 2018
Fast Reconfiguration Through Difference Compression
FMSA: FPGA-Accelerated ClustalW-Based Multiple Sequence Alignment through Pipelined Prefiltering
Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs
The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability
Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications
System on a FPGA Virtual Concatenation
Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms
Open-Source Bitstream Generation