yusuke1997/dblp-id-title huggingface dataset:
Applications of a microprogrammed microprocessor
Improving Code Density Using Compression Techniques
AdapTiV: Sign-Similarity Based Image-Adaptive Token Merging for Vision Transformer Acceleration
Exploiting Dead Value Information
Meet the walkers: accelerating index traversals for in-memory databases
Arbitrary Modulus Indexing
Critical issues regarding HPS, a high performance microarchitecture
Instruction tracing via microprogramming
Instruction Replication for Clustered Microarchitectures
Exploiting horizontal and vertical concurrency via the HPSm microprocessor
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
Branch merging for effective exploitation of instruction-level parallelism
DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fission
Enabling datacenter servers to scale out economically and sustainably
MIPS: A microprocessor architecture
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
The application of programming language techniques to the design and development of microprogramming languages
Mesorasi: Architecture Support for Point Cloud Analytics via Delayed-Aggregation
A microsequencer architecture with firmware support for modular microprogramming
Towards an efficient, machine-independent language for microprogramming
An analysis of dynamic scheduling techniques for symbolic applications
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems
A Compiler-Like Framework for Optimizing Cryptographic Big Integer Multiplication on GPUs
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance
A microinstruction sequencer and language package for structured microprogramming
Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
MISC: a Multiple Instruction Stream Computer
A flexible VLSI core for an adaptable architecture
Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
Coordinated Priority-aware Charging of Distributed Batteries in Oversubscribed Data Centers
A Framework for Balancing Control Flow and Predication
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor
The NoX router
LerGAN: A Zero-Free, Low Data Movement and PIM-Based GAN Architecture
FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning
SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing
On reordering instruction streams for pipelined computers
Turnpike: Lightweight Soft Error Resilience for In-Order Cores
ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip
Cost-effective design of application specific VLIW processors using the SCARCE framework
Certification of microprograms by an algebraic method
Large-reach memory management unit caches
Coordinated control of multiple prefetchers in multi-core systems
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures
Partitioned register files for VLIWs: a preliminary analysis of tradeoffs
PerpLE: Improving the Speed and Effectiveness of Memory Consistency Testing
A microprogramming language for the B-1726
ThyNVM: enabling software-transparent crash consistency in persistent memory systems
Employing finite automata for resource scheduling
A framework for designing congestion-aware deterministic routing
Optimizing shared cache behavior of chip multiprocessors
Pipestitch: An energy-minimal dataflow architecture with lightweight threads
A design space evaluation of grid processor architectures
MIMD synchronization on SIMT architectures
Optimization on instruction reorganization
A locality-aware memory hierarchy for energy-efficient GPU architectures
An evaluation system for application specific architectures
CCICheck: using µhb graphs to verify the coherence-consistency interface
Scalar Vector Runahead
Microprogrammed multiprocessor graphic controller
Cambricon-S: Addressing Irregularity in Sparse Neural Networks through A Cooperative Software/Hardware Approach
An annotated bibliography on microprogramming: late 1969 - early 1972
Fusion-3D: Integrated Acceleration for Instant 3D Reconstruction and Real-Time Rendering
Berti: an Accurate Local-Delta Data Prefetcher
In-network coherence filtering: snoopy coherence without broadcasts
MICOS: A microprogrammed hierarchical operating system nucleus and its performance comparison
Temporarily Unauthorized Stores: Write First, Ask for Permission Later
eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
Micro control hardware and high level languages interpretor: An attempt of macro supported by firmware
Three ECL designs for microprogrammable Writable Control Stores
Yield-Aware Cache Architectures
An improvement of trace scheduling for global microcode compaction
Specializing Compiler Optimizations through Programmable Composition for Dense Matrix Computations
Low Vccmin fault-tolerant cache with highly predictable performance
Efficient Selection of Vector Instructions Using Dynamic Programming
Ti-states: Processor power management in the temperature inversion region
Millimeter (mm)-wave wireless NoC as interconnection backbone for multicore chips: promises and challenges
Dynamically Controlled Resource Allocation in SMT Processors
Optimized Quantum Compilation for Near-Term Algorithms with OpenPulse
System-level integrated server architectures for scale-out datacenters
A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification
A visual microprogramming system
PointAcc: Efficient Point Cloud Accelerator
Emerging applications for the connected home
Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip
Neural Acceleration for General-Purpose Approximate Programs
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Wireframe: supporting data-dependent parallelism through dependency graph execution in GPUs
The Micro8 microcode assembler
The bi-Mode Branch Predictor
Fast, Robust and Transferable Prediction for Hardware Logic Synthesis
On storage optimization of horizontal microprograms
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators
Dynamic and scalable runtime block-based multicast routing for networks on chips
CritICs Critiquing Criticality in Mobile Apps
IceClave: A Trusted Execution Environment for In-Storage Computing
PDede: Partitioned, Deduplicated, Delta Branch Target Buffer
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically
42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA
A survey of techniques to reduce/minimize the control part/rom of a microprogrammed digital computer
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations
Microarchitectural implications of event-driven server-side web applications
Conference record of the 5th annual workshop on Microprogramming, MICRO 1972, Urbana-Champaign, Illinois, USA, September 25-26, 1972
Low-Overhead General-Purpose Near-Data Processing in CXL Memory Expanders
Adaptive Flow Control for Robust Performance and Energy
Bit-pragmatic deep neural network computing
An hybrid eDRAM/SRAM macrocell to implement first-level data caches
Improving bank-level parallelism for irregular applications
45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Workshops Proceedings, Vancouver, BC, Canada, December 1-5, 2012
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration
The Burroughs B1800 microprogrammed measurement system: A hybrid hardware/software approach
On the combination of hardware and software concurrency extraction methods
SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations
ProfileMe : Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
CacheCraft: Enhancing GPU Performance under Memory Protection through Reconstructed Caching
General microprogram width reduction using generator sets
Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms
Validation of Side-Channel Models via Observation Refinement
Testudo: Heavyweight security analysis via statistical sampling
Large pages and lightweight memory management in virtualized environments: can you have it both ways?
Memory Latency Reduction via Thread Throttling
Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization
Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012
Microprogrammed control for signal processing
ROBUST: a new self-healing fault-tolerant NoC router
Rethinking DRAM Power Modes for Energy Proportionality
Unrolling-based optimizations for modulo scheduling
Pushing Point Cloud Compression to the Edge
Compiling for instruction cache performance on a multithreaded architecture
Heuristics for Register-Constrained Software Pipelining
Procedure Placement Using Temporal Ordering Information
The Bunker Cache for spatio-value approximation
Compressing control ROM for VLSI microprogrammed microprocessors
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Zero-cycle loads: microarchitecture support for reducing load latency
Taming the instruction bandwidth of quantum computers via hardware-managed error correction
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Directed Statistical Warming through Time Traveling
PointCIM: A Computing-in-Memory Architecture for Accelerating Deep Point Cloud Analytics
TMI: thread memory isolation for false sharing repair
Pageforge: a near-memory content-aware page-merging architecture
Multiperspective reuse prediction
TACOS: Topology-Aware Collective Algorithm Synthesizer for Distributed Machine Learning
FPRaker: A Processing Element For Accelerating Neural Network Training
Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach
Hardware acceleration of logic simulation using a data flow microarchitecture
Hardware-Assisted Virtualization of Neural Processing Units for Cloud Platforms
Main memory for user microprogram residence - an analysis
Efficient checker processor design
TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining
Core Technologies in Hardware and Software
Leveraging 3D Technology for Improved Reliability
Abstract computing machines
SABRes: Atomic object reads for in-memory rack-scale computing
Efficient warp execution in presence of divergence with collaborative context collection
NVBit: A Dynamic Binary Instrumentation Framework for NVIDIA GPUs
Vulkan-Sim: A GPU Architecture Simulator for Ray Tracing
TimeTrader: exploiting latency tail to save datacenter energy for online search
Reducing memory interference in multicore systems via application-aware memory channel partitioning
A high-speed hardware unit for a subset of logic resolution
Mosaic: a GPU memory manager with application-transparent support for multiple page sizes
Partial Compilation of Variational Algorithms for Noisy Intermediate-Scale Quantum Machines
Implementation of high speed data sets with microprogrammable data processors
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
Design and specification of microprogrammed computer architectures
Sampling Dead Block Prediction for Last-Level Caches
The microarchitecture of a real-time robot motion planning accelerator
Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System
Speculative Privacy Tracking (SPT): Leaking Information From Speculative Execution Without Compromising Privacy
TorchSparse++: Efficient Training and Inference Framework for Sparse Convolution on GPUs
SOPHGO BM1684X: A Commercial High Performance Terminal AI Processor with Large Model Support
A survey on bit dimension optimization strategies of microprograms
Methodology to verify, debug and evaluate performances of NoC based interconnects
Vacuum packing: extracting hardware-detected program phases for post-link optimization
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs
The impact of VLSI on microprogramming
Active management of timing guardband to save energy in POWER7
Some experiments in global microcode compaction
The L-machine: a computer instruction set for the efficient execution of high-level language programs
Genie Cache: Non-Blocking Miss Handling and Replacement in Page-Table-Based DRAM Cache
Proceedings of the 17th annual workshop on Microprogramming, MICRO 1984, New Orleans, Louisiana, USA, October 30 - November 2, 1984
Leviathan: A Unified System for General-Purpose Near-Data Computing
A "metasimulator" for microcoded processors
Contrasting translation, verification and synthesis in software and firmware engineering
The ECLIPSE® MV/8000 Microsequencer
Proceedings of the 16th International Workshop on Network on Chip Architectures, NoCArc 2023, Toronto, ON, Canada, 28 October 2023
Improving Streaming Graph Processing Performance using Input Knowledge
Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations
Modulo schedule buffers
Improving Cache Management Policies Using Dynamic Reuse Distances
C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches
Efficient support of position independence on non-volatile memory
39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA
The effect of page allocation on caches
Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics
Scalable Store-Load Forwarding via Store Queue Index Prediction
Operation scheduling in reconfigurable, multifunction pipelines
DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search
Microprogramming: A step of a top-down design methodology
Name resolutions using a microprogrammed interpretive technique
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
TensorDash: Exploiting Sparsity to Accelerate Deep Neural Network Training
Exploiting Vector Parallelism in Software Pipelined Loops
Efficient Hardware-Assisted Logging with Asynchronous and Direct-Update for Persistent Memory
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
A direct execution architecture for Prolog?
Warped-DMR: Light-weight Error Detection for GPGPU
On the packing of micro-operations into micro-instruction words
Design verification of a VLSI VAX microcomputer
Compiler-Directed Early Load-Address Generation
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
TrainBox: An Extreme-Scale Neural Network Training Server Architecture by Systematically Balancing Operations
Efficient unicast and multicast support for CMPs
Design decisions influencing the microarchitecture for a Prolog machine
Fetching instruction streams
Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay
Global Multi-Threaded Instruction Scheduling
An approach to microprogram optimization considering resource occupancy and instruction formats
Understanding the Energy Consumption of Dynamic Random Access Memories
FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling
Microcode development tools for a capability-based processor
DiffTune: Optimizing CPU Simulator Parameters with Learned Differentiable Surrogates
Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations
ExTensor: An Accelerator for Sparse Tensor Algebra
Dynamically Trading Frequency for Complexity in a GALS Microprocessor
Codesign of energy and resource efficient contention-free Network-on Chip for real-time embedded systems
The inner most loop iteration counter: a new dimension in branch history
Network on metachip architectures
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
Select-free instruction scheduling logic
Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures
Microprogramming in the educational environment
Performance and Power Solutions for Caches Using 8T SRAM Cells
Strategies for mapping dataflow blocks to distributed hardware
Compiler managed micro-cache bypassing for high performance EPIC processors
Memory utilization for a dynamically microprogrammed computer
SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management
The role of adaptivity in two-level adaptive branch prediction
Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing
Exploiting heterogeneity for tail latency and energy efficiency
Logic programming applied to hardware design specification and verification
Neuron-Level Fuzzy Memoization in RNNs
41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy
Microprogramming of a burst structure
A Benchmarking Framework for Interactive 3D Applications in the Cloud
Dynamic Multi-Resolution Data Storage
Uncovering Hidden Instructions in Armv8-A Implementations
Evaluation of a concurrent error detection method for microprogrammed control units
User satisfaction aware routing decisions in NOC
Hardware supported persistent object address translation
Levels of representation of programs and the architecture of universal host machines
ASIC microprocessors
DelayAVF: Calculating Architectural Vulnerability Factors for Delay Faults
Evaluating the effects of cache redundancy on profit
The anatomy of the register file in a multiscalar processor
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors
CHiRP: Control-Flow History Reuse Prediction
Identifying and predicting timing-critical instructions to boost timing speculation
Selective Replication in Memory-Side GPU Caches
Reducing the complexity of the register file in dynamic superscalar processors
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997
Lazy release consistency for GPUs
Cache Sensitive Modulo Scheduling
Security verification of hardware-enabled attestation protocols
Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes
HoloAR: On-the-fly Optimization of 3D Holographic Processing for Augmented Reality
Prediction Caches for Superscalar Processors
DRISA: a DRAM-based reconfigurable in-situ accelerator
A model of a microprogrammed functional-oriented computing unit
Register sharing for equality prediction
A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network
Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs
Defect tolerant molecular electronics: algorithms, architectures, and atoms
The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU
A two level microprogram simulator
Invalid Data-Aware Coding to Enhance the Read Performance of High-Density Flash Memories
Loop-Aware Memory Prefetching Using Code Block Working Sets
Extending microcode compaction for real architectures
IDIO: Network-Driven, Inbound Network Data Orchestration on Server Processors
Complementing user-level coarse-grain parallelism with implicit speculative parallelism
The selection of optimal cache lines for microprocessor-based controllers
Ordering functions for improving memory reference locality in a shared memory multiprocessor system
Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017
Memory Protection through Dynamic Access Control
Adaptive History-Based Memory Schedulers
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment
Monte Carlo techniques in code optimization
Variability-tolerant NoC link design
A microcoded real-time executive for numeric support nodes distributed within embedded networks
Precise Register Allocation for Irregular Architectures
Design of a microcode link editor
Efficient GPU synchronization without scopes: saying no to complex consistency models
The Cascaded Predictor: Economical and Adaptive Branch Target Prediction
Performance evaluation and improvement of a dynamically microprogrammable computer with low-level parallelism
Zorua: A holistic approach to resource virtualization in GPUs
Constructing and characterizing covert channels on GPGPUs
Applying the Principle of Least Privilege to System Management Interrupt Handlers with the Intel SMI Transfer Monitor
Timely, Efficient, and Accurate Branch Precomputation
Tangram: Integrated Control of Heterogeneous Computers
Morrigan: A Composite Instruction TLB Prefetcher
A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks
A multiple floating point coprocessor architecture
A medium level compiler generating microcode
A many-core architecture for in-memory data processing
Elastic Translations: Fast Virtual Memory with Multiple Translation Sizes
Archytas: A Framework for Synthesizing and Dynamically Optimizing Accelerators for Robotic Localization
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
NeuroLPM - Scaling Longest Prefix Match Hardware with Neural Networks
Toward zero-cost branches using instruction registers
Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
CoSpec: Compiler Directed Speculative Intermittent Computation
SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices
Trace based phase prediction for tightly-coupled heterogeneous cores
Distributed Logless Atomic Durability with Persistent Memory
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
BuMP: Bulk Memory Access Prediction and Streaming
Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors