yusuke1997/dblp-id-title huggingface dataset:
Experiences in Functional Validation of a High Level Synthesis System
SYNARC: A computer - aided model for architectural design
Automatic Functional Test Program Generation for Microprocessors
NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations
CMOS scaling beyond 32nm: challenges and opportunities
ChipletEM: Physics-Based 2.5D and 3D Chiplet Heterogeneous Integration Electromigration Signoff Tool Using Coupled Stress and Thermal Simulation
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library
RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator
SAGA: SystemC acceleration on GPU architectures
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation
Improving worst-case cache performance through selective bypassing and register-indexed cache
Information Models of VHDL
A communication-theoretic design paradigm for reliable SOCs
SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity
Multi-Pads, Single Layer Power Net Routing in VLSI Circuits
Faster Region-based Hotspot Detection
Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?
Property-driven Parallel Symbolic Model Checking of LTL
Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988
Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement
Untwist your brain: efficient debugging and diagnosis of complex assertions
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits
A Unified Approach to Multilayer Over-the-Cell Routing
The Sea-of-Wires Array Aynthesis System
Mapping Quantum Circuits to IBM QX Architectures Using the Minimal Number of SWAP and H Operations
Model Checking of S3C2400X Industrial Embedded SOC Product
Statistical fault injection for impact-evaluation of timing errors on application performance
CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length
MicroNetwork-Based Integration for SOCs
Information technology a management problem
"Some things that did not happen in software DA"
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks
Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain
Arbitrarily-sized module location technique in the lop system
Minimal Shift Counters and Frequency Division
4.25 Gb/s laser driver: design challenges and EDA tool limitations
Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTs
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design
Data-Flow Assisted Behavioral Partitioning for Embedded Systems
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)
Q-PIM: A Genetic Algorithm based Flexible DNN Quantization Method and Application to Processing-In-Memory Platform
EDA for secure and dependable cybercars: challenges and opportunities
A Two-State Methodology for RTL Logic Simulation
Verifying a gigabit ethernet switch using SMV
Workshop the semi-custom revolution: How to thrive or survive
A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level
SACReD: An Attack Framework on SAC Resistant Delay-PUFs leveraging Bias and Reliability Factors
Implication algorithms for MOS switch level functional macromodeling implication and testing
R2D3: A Reliability Engine for 3D Parallel Systems
REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables
A Conceptual Framework for Designing ASIC Hardware
Brook auto: high-level certification-friendly programming for GPU-powered automotive systems
Timing and Crosstalk Driven Area Routing
The Automatic Generation of Bus-Interface Models
Incremental Circuit Simulation Using Waveform Relaxation
RL-MUL: Multiplier Design Optimization with Deep Reinforcement Learning
STAFF: online learning with stabilized adaptive forgetting factor and feature selection algorithm
Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Runtime dependency analysis for loop pipelining in high-level synthesis
The real world of design automation - part III or The user's viewpoint chairman's introduction (Panel Discussion)
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions
An Engineering Environment for Hardware/Software Co-Simulation
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design
The Performance of the Concurrent Fault Simulation Algorithms in MOZART
Modeling and simulation of real defects using fuzzy logic
Why it doesn't work for CAD (Panel Abstract)
Shielding against design flaws with field repairable control logic
Performance analysis of different arbitration algorithms of the AMBA AHB bus
An efficient incremental algorithm for min-area retiming
Optimizing Resource Utilization and Testability Using Hot Potato Techniques
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques
Reliable on-chip systems in the nano-era: lessons learnt and future trends
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach
Toward High-Accuracy, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ
OD3P: On-Demand Page Paired PCM
General river routing algorithm
Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse
Efficient SRAM failure rate prediction via Gibbs sampling
Application of a syntax driver to logic equation processing and data-control card scanning
QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization
A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC
Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs
BLESS: a simple and efficient scheme for prolonging PCM lifetime
Logic design automation of diagnosable MOS combinational logic networks
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder
Alleviating datapath conflicts and design centralization in graph analytics acceleration
A first step towards automatic application of power analysis countermeasures
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators
Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations
OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs
TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning
The good, the bad, and the ugly of silicon debug
Design techniques for sensor appliances: foundations and light compass case study
Efficient Bilevel Source Mask Optimization
Impact assessment of net metering on smart home cyberattack detection
Register binding for clock period minimization
Minimization of Memory Traffic in High-Level Synthesis
AMUSE: a minimally-unsatisfiable subformula extractor
ZoneKV: A Space-Efficient Key-Value Store for ZNS SSDs
VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals
Optimization techniques for two-dimensional placement
Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited
Reinforcement Learning-Assisted Management for Convertible SSDs
Approximate SMT Counting Beyond Discrete Domains
Variability-aware, discrete optimization for analog circuits
Deterministic approaches to analog performance space exploration (PSE)
Latency and Latch Count Minimization in Wave Steered Circuits
Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES
Modeling of Intermediate Node States in switch-Level Networks
Ensuring consistency during front-end design using an object-oriented interfacing tool called NETLISP
Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator
Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies
Verification Methodologies in a TLM-to-RTL Design Flow
Design Methods for Augmented Reality In-Vehicle Infotainment Systems
YAPI: application modeling for signal processing systems
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects
The Intel design automation system
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design
Interactive compaction router for VLSI layout
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
Dynamic Fault Diagnosis on Reconfigurable Hardware
Domain-wall memory buffer for low-energy NoCs
Systematic temperature sensor allocation and placement for microprocessors
Advanced techniques for RTL debugging
Dynamic Switching Speed Reconfiguration for Engine Performance Optimization
"Computer generated artwork - the aide system"
In-situ characterization and extraction of SRAM variability
Contention-Aware Forecasting of Energy Efficiency through Sequence-Based Models in Modern Heterogeneous Processors
A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm
A MIPS R2000 implementation
NORM: compact model order reduction of weakly nonlinear systems
Where VHDL Fits Within the CAD Environment
Legalization algorithm for multiple-row height standard cell design
Flexible architectures for engineering successful SOCs
Late Breaking Results: Reinforcement Learning for Scalable Logic Optimization with Graph Neural Networks
NOMAD: A printed wiring board layout system
Automation of design for uncommitted logic array
Computing the Maximum Power Cycles of a Sequential Circuit
Protocol Generation for Communication Channels
Worst-case execution time analysis for parallel run-time monitoring
A fast optical propagation technique for modeling micro-optical systems
Acyclic Multi-Way Partitioning of Boolean Networks
State Assignment Using Input/Output Functions
Optimal low power X OR gate decomposition
Design and implementation of the POWER5 microprocessor
LODS: locality-oriented dynamic scheduling for on-chip multiprocessors
Block placement with symmetry constraints based on the O-tree non-slicing representation
VHDL Synthesis Using Structured Modeling
CAMRAS: Computer Assisted Mapping & Records Activity Systems
Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks
ReGNN: a ReRAM-based heterogeneous architecture for general graph neural networks
An interactive graphic and process controlled system for composing and sampling loom constrained designs
On Countermeasures Against the Thermal Covert Channel Attacks Targeting Many-core Systems
Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality
The Use of Petri Nets for Modeling Pipelined Processors
SDISC: A Spike-Driven Human-Machine Interface with In-Situ Computing for Real-Time Low-Power Interaction
Towards Resilient Deployment of In-Memory Neural Networks with High Throughput
Late Breaking Results: FPGen-3D: Automated Framework for 3D-FPGA Architecture Generation and Exploration
Test generation for MOS circuits using D-algorithm
Some theoretical aspects of algorithmic routing
An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines
Exploiting die-to-die thermal coupling in 3D IC placement
A logic simulation machine
Vibration-based secure side channel for medical devices
Balancing security and utility in medical devices?
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays
An Efficient Multilayer MCM Router Based on Four-Via Routing
Internal Structure Aware RDF Data Management in SSDs
Model-based functional verification
Are Formal Methods in Design for Real? (Panel Abstract)
A-QED Verification of Hardware Accelerators
Measures of Syntactic Complexity for Modeling Behavioral VHDL
MFTI: matrix-format tangential interpolation for modeling multi-port systems
A Layout Improvement Method Based on Constraint Propagation for Analog LSI's
Dynamic voltage scaling of OLED displays
RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs
GSP: A system for computer assisted space planning
A line-expansion algorithm for the general routing problem with a guaranteed solution
Transistor abstraction for the functional verification of FPGAs
IC Analyses Including Extracted Inductance Models
InSyn: Integrated Scheduling for DSP Applications
Heterogeneous Reconfigurable Accelerators: Trends and Perspectives
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
A high quality, low cost router for MOS/LSI
On the need for statistical timing analysis
Towards State-Aware Computation in ReRAM Neural Networks
A Network Flow Approach for Hierarchical Tree Partitioning
Invited: Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities
A user interface for architectural design, a case study
Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits
Move-On-Modify: An Efficient yet Crash-Consistent Update Strategy for Interlaced Magnetic Recording
A hierarchical bit-map format for the representation of IC mask data
An Expert System Application in Semicustom VLSI Design
On the relative placement and the transportation problem for standard-cell layout
PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems
Scalable sequence-constrained retention register minimization in power gating design
ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid Workloads
Using Lower Bounds During Dynamic BDD Minimization
Parallel Circuit Simulation Using Hierarchical Relaxation
Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks Inference
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
Confidentiality preserving integer programming for global routing
Task scheduling with RT constraints
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores
The Yorktown Simulation Engine: Introduction
ALMS: Automated logic mapping system
A color graphics system for I.C. mask design and analysis
GPU friendly fast Poisson solver for structured power grid network analysis
Clock Routing for High-Performance ICs
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
A Deterministic finite automaton approach to design rule checking for VLSI
Verification strategy for integration 3G baseband SoC
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation
Experiments with simulated annealing
A RRAM-based High Energy-efficient Accelerator Supporting Multimodal Tasks for Virtual Reality Wearable Devices
Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract)
CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration
ARM2GC: Succinct Garbled Processor for Secure Computation
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology
DATAPATH: a CMOS data path silicon assembler
On switch factor based analysis of coupled RC interconnects
PREEMPT: PReempting Malware by Examining Embedded Processor Traces
MATCHA: a fast and energy-efficient accelerator for fully homomorphic encryption over the torus
TPM-SIM: a framework for performance evaluation of trusted platform modules
FIONA: Fine-grained Incoherent Optical DNN Accelerator Search for Superior Efficiency and Robustness
A design utility manager: the ADAM planning engine
Effective diagnostics through interval unloads in a BIST environment
Dnestmap: mapping deeply-nested loops on ultra-low power CGRAs
VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning
Formal Specification and Verification of Hardware: A Comparative Case Study
Capacity optimized NoC for multi-mode SoC
Simulation of urban growth as a function of accessibility
Creating and updating space occupancy and building plans using interactive graphics
Early exploration for platform architecture instantiation with multi-mode application partitioning
Developing Privacy-preserving AI Systems: The Lessons learned
Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation
How accurately can we model timing in a placement engine?
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs
Invited - Specification and modeling for systems-on-chip security verification
Automated design and manufacture of printed circuit boards
Test cost reduction for X -value elimination by scan slice correlation analysis
MetaDSE: A Few-shot Meta-learning Framework for Cross-workload CPU Design Space Exploration
Computer aided design (CAD) using logic programming
Contention-Free Configured Grant Scheduling for 5G URLLC Traffic
Variability driven gate sizing for binning yield optimization
Global Scheduling for High-Level Synthesis Applications
A hybrid NoC design for cache coherence optimization for chip multiprocessors
A linear fractional transform (LFT) based model for interconnect parametric uncertainty
Debugging strategies for mere mortals
TF-MVP: Novel Sparsity-Aware Transformer Accelerator with Mixed-Length Vector Pruning
A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System
Physics-based Electromigration Assessment for Power Grid Networks
Analysis of RC Interconnections Under Ramp Input
Geometrical Compaction in One Dimension for Channel Routing
The real world of design automation - part II or adapting to the joys of madness (Panel Session)
Selective controllability: A proposal for testing and diagnosis
FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results
Exploiting suspected redundancy without proving it
A robust envelope following method applicable to both non-autonomous and oscillatory circuits
Use of design optimization techniques at Norden
Accurate timing prediction at placement stage with look-ahead RC network
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency
Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming
A Heuristic Algorithm for the Fanout Problem
Few electron devices: towards hybrid CMOS-SET integrated circuits
The graphically accessed interactive design of industrial pipe systems
Transistor level test generation for MOS circuits
Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design
Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves
A digital system modeling philosophy and design language
Combined BEM/FEM substrate resistance modeling
SATIRE: A New Incremental Satisfiability Engine
Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning
A Structural Representation for VLSI Design
An efficient kernel transformation architecture for binary- and ternary-weight neural network inference
Checking Equivalence for Partial Implementations
An Interactive Graphics System for the design of integrated circuits
Interconnect testing in cluster-based FPGA architectures
EMS: efficient memory subsystem synthesis for spatial accelerators
Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation
Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures
Fast Min-Cost Buffer Insertion under Process Variations
RF MEMS in wireless architectures
Nanoscale digital computation through percolation
The N.mPc runtime environment
Fast algorithms for slew constrained minimum cost buffering
Solving Covering Problems Using LPR-Based Lower Bounds
WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration
Automating design-space exploration: optimal deployment of automotive SW-components in an ISO26262 context
On Computing Optimized Input Probabilities for Random Tests
Formal Verification of the Sobel Image Processing Chip
BPNet: Branch-pruned Conditional Neural Network for Systematic Time-accuracy Tradeoff
Minimizing peak current via opposite-phase clock tree
Algorithms for multiple-criterion design of microprogrammed control hardware
Parallelizable stable explicit numerical integration for efficient circuit simulation
VIPR-PCB: a machine learning based golden-free PCB assurance framework
An AWE Technique for Fast Printed Circuit Board Delays
AmgR: Algebraic Multigrid Accelerated on ReRAM
Timing Optimization By Gate Resizing And Critical Path Identification
Efficient Implementation of a BDD Package
Programmimg languages for hardware description
Multicore parallel min-cost flow algorithm for CAD applications
Toward a systematic-variation aware timing methodology
Analytical Estimation of Transition Activity From Word-Level Signal Statistics
Efficient description of the design space of analog circuits
SIDECAR: Design Support for Reliability
Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems
High-throughput Point-Cloud Accelerator with Sparsity-aware Hierarchical Neighbor Voxel Search and Skipping
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor
SCAT - a new statistical timing verifier in a silicon compiler system
LES: A Layout Expert System
Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components
DAE2FSM: automatic generation of accurate discrete-time logical abstractions for continuous-time circuit dynamics
BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement
Design automation of electronics in Sweden
Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted Behaviour
Routing tree construction under fixed buffer locations
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router
RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic: A Case Study on Post-Quantum Key Exchange Using CSIDH-512
FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization
Global convergence analysis of mixed-signal systems
Delay Analysis of the Distributed RC Line
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator
Automatic Layout of Silicon-on-Silicon Hybrid Packages
A flexible accelerator for layer 7 networking applications
Sign bit reduction encoding for low power applications
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic
Timing Verification and the Timing Analysis program
A comprehensive approach to a connectivity audit, or a fruitful comparison of apples and oranges
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors