yusuke1997/dblp-id-title huggingface dataset:
A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement
16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR
A capacitive touch controller robust to display noise for ultrathin touch screen displays
Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM
20.11 A Crystal-Less BodyID with an Asynchronous Clockless Leakage-Powered Wake-Up Receiver and Over-the-Channel Clock Recovery
F2: 3D stacking technologies for image sensors and memories
A coupled-RTWO-based subharmonic receiver front-end for 5G E-Band backhaul links in 28nm bulk CMOS
iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS
W-band CMOS amplifiers achieving +10dBm saturated output oower and 7.5dB NF
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
18.7 A remotely controlled locomotive IC driven by electrolytic bubbles and wireless powering
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS
Session 9 overview: Sensors
27.4 A 13.56MHz Wireless Power Transfer System with Hybrid Voltage-/Current-Mode Receiver and Global Digital-PWM Regulation Achieving 150% Transfer Range Extension and 72.3% End-to-End Efficiency
Session 9 overview: High-performance wireless: Wireless subcommittee
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm 2 , 1mm Package-on-Package
A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step
20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitor
A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter technique
A 32nm 3.1 billion transistor 12-wide-issue Itanium ® processor for mission-critical servers
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input
6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters
A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS
16.1 A 2.7-to-13.3μJ/boot/slot Flexible RNS-CKKS Processor in 28nm CMOS Technology for FHE-Based Privacy-Preserving Computing
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth
13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
A Bio-Impedance Readout IC With Digital-Assisted Baseline Cancellation for 2-Electrode Measurement
A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple
A CMOS Interface for a Gas-Sensor Array with a 0.5%-Linearity over 500kΧ-to-1GΧ Range and 2.5°C Temperature Control Accuracy
A Fingerprint Sensor with Impedance Sensing for Fraud Detection
A 4GS/s 4b Flash ADC in 0.18µm CMOS
A 64B CPU Pair: Dual- and Single-Processor Chips
A multistandard multiband mobile TV RF SoC in 65nm CMOS
A 10Gb/s MLSE-based Electronic-Dispersion-Compensation IC with Fast Power-Transient Management for WDM Add/Drop Networks
A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation
An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor
23.3 A Passive Crystal-Less Wi-Fi-to-BLE Tag Demonstrating Battery-Free FDD Communication with Smartphones
256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes
13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology
22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer
A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm 2 RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range
Session 8 overview: Delta-sigma converters: Data converters subcommittee
5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency counting
Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a Large Multicore Processor for Machine Learning Applications
An AC-coupled hybrid envelope modulator for HSUPA transmitters with 80% modulator efficiency
7.9 An 8b 6-12GHz 0.18mW/GHz DC Modulated Ramp-Based Phase Interpolator in 65nm CMOS Process
7.6 A High-Speed Back-Illuminated Stacked CMOS Image Sensor with Column-Parallel kT/C-Cancelling S&H and Delta-Sigma ADC
24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input
23.3 EdgeDiff: 418.4mJ/Inference Multi-Modal Few-Step Diffusion Model Accelerator with Mixed-Precision and Reordered Group Quantization
32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency
3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI
F3: Radio architectures and circuits towards 5G
A 0.8mm 3 Ultrasonic Implantable Wireless Neural Recording System With Linear AM Backscattering
A Wide 0.1-to-10 Conversion-Ratio Symmetric Hybrid Buck-Boost Converter for USB PD Bidirectional Conversion
A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging
1.1 AI Era Innovation Matrix
35.2 A Spatial-Domain Compressive-Sensing Photoacoustic Imager with Matrix-Multiplying SAR ADC
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!)
17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering
1/2-inch 7.2MPixel CMOS Image Sensor with 2.25µm Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation
16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time
24.2 A power-efficient switched-capacitor stimulating system for electrical/optical deep-brain stimulation
5.5 A 2.1e - Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology
A low noise current readout architecture for fluorescence detection in living subjects
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique
A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM
25.1 Short-Reach Silicon Photonic Interconnects with Quantum Dot Mode Locked Laser Comb Sources
5G Drives Exponential Increase in Processing Needs Across all Industries
A 20-Gb/s/pin 0.0024-mm 2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels
A Charge-Injection-Based Active-Decoupling Technique for Inductive-Supply-Noise Suppression
8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS
3D-MAPS: 3D Massively parallel processor with stacked memory
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation
A 90GHz 65nm CMOS Injection-Locked Frequency Divider
11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package
Optical PCB interconnects, Niche or mainstream?
A 28GHz Compact 3-Way Transformer-Based Parallel-Series Doherty Power Amplifier With 20.4%/14.2% PAE at 6-/12-dB Power Back-off and 25.5dBm PSAT in 55nm Bulk CMOS
14.5 A 1V W-Band Bidirectional Transceiver Front-End with <1dB T/R Switch Loss, <1°/dB Phase/Gain Resolution and 12.3% TX PAE at 15.1dBm Output Power in 65nm CMOS Technology
A 160kgate 4.5kB SKRAM H.264 video decoder for HDTV applications
ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS
A 3 to 5GHz CMOS UWB LNA with input matching using miller effect
A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC
15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS
A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOS
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)
A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS
A 2W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters
Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee
EE3: Industry showcase
Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
Session 4 overview: Imagers
A 12Gb/s non-contact interface with coupled transmission lines
A 28nm 0.6V low-power DSP for mobile applications
Session 16 overview: Switching power control techniques: Analog subcommittee
Session 28 overview: Hybrid ADCs
6.5 25.3μW at 60fps 240×160-pixel vision sensor for motion capturing with in-pixel non-volatile analog memory using crystalline oxide semiconductor FET
A 28nm Bulk-CMOS 4-to-8GHz ¡2mW Cryogenic Pulse Modulator for Scalable Quantum Computing
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver
23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4
A 0.024mm 2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS
A 1-58.125Gb/s, 5-33dB IL Multi-Protocol Ethernet-Compliant Analog PAM-4 Receiver with 16 DFE Taps in 10nm
CMOS capacitive biosensor with enhanced sensitivity for label-free DNA detection
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI
2.9 A Background calibration technique to control bandwidth in digital PLLs
Session 18 overview: Full duplex wireless front-ends
A 10b resistor-resistor-string DAC with current compensation for compact LCD driver ICs
32.7 A 25.2dBm PSAT, 35-to-43GHz VSWR-Resilient Chain-Weaver Eight-Way Balanced PA with an Embedded Impedance/Power Sensor
A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers
A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms
6.3 Imager with In-Sensor Event Detection and Morphological Transformations with 2.9pJ/pixel×frame Object Segmentation FOM for Always-On Surveillance in 40nm
A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing
40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS
20.7 A 0.45-to-3V reconfigurable charge-pump energy harvester with two-dimensional MPPT for Internet of Things
18.3 A 120mA Non-Isolated Capacitor-Drop AC/DC Power Supply
6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions
A 6.78MHz 94.2% Peak Efficiency Class-E Transmitter with Adaptive Real-Part Impedance Matching and Imaginary-Part Phase Compensation Achieving a 33W Wireless-Power-Transfer System
0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS
An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) Devices
26.8 A Trimodal Wireless Implantable Neural Interface System-on-Chip
A 342mW mobile application processor with full-HD multi-standard video codec
11.5 A time-correlated single-photon-counting sensor with 14GS/S histogramming time-to-digital converter
A 242mW 10mm 2 1080p H.264/AVC High-Profile Encoder Chip
A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging
Session 14 Overview: mm-Wave Transceivers for Communication and Radar Wireless Subcommittee
A 3MHz Low-Voltage Buck Converter with Improved Light Load Efficiency
A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×10 5 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple
2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications
A broadband THz imager in a low-cost CMOS technology
A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C
27.1 A 65nm Energy-Harvesting ULP SoC with 256kB Cortex-M0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System
23.4 A 28W -108.9dB/-102.2dB THD/THD+N Hybrid ΔΣ-PWM Class-D Audio Amplifier with 91% Peak Efficiency and Reduced EMI Emission
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor
An 8μW Heterodyning Chopper Amplifier for Direct Extraction of 2μVrms Neuronal Biomarkers
11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp
A 15mW 0.2mm 2 50MS/s ADC with wide input range
6.6 A 320×256 6.9mW 2.2mK-NETD 120.4dB-DR LW-IRFPA with Pixel-Paralleled Light-Driven 20b Current-to-Phase ADC
22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding
A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge
Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPS
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS
F3: Adaptive design techniques for energy efficiency
Trusting our Lives to Sensors
6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers
Session 3 overview: Analog techniques: Analog subcommittee
Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors
34.4 An Energy-Replenishing Ultrasound Pulser with 0.25CV 2 f Dynamic Power Consumption
NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling
A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON
A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS
A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices
A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications
Pain control on demand based on pulsed radio-frequency stimulation of the dorsal root ganglion using a batteryless implantable CMOS SoC
183GHz 13.5mW/pixel CMOS regenerative receiver for mm-wave imaging applications
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology
Challenges of image-sensor development
7.4 A 0.027mm 2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling
THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data Interface
6.4 A 400×400 3.24µm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm 2 Controller and 80ns Recovery Time
Session 34 Overview: Emerging Imaging Solutions Imagers, Medical, Mems and Displays Subcommittee
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
7.4 A 256×128 3D-Stacked (45nm) SPAD FLASH LiDAR with 7-Level Coincidence Detection and Progressive Gating for 100m Range and 10klux Background Light
17.10 A 318-to-370GHz standing-wave 2D phased array in 0.13µm BiCMOS
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer
A 0.1-to-0.2V Transformer-Based Switched-Mode Folded DCO in 22nm FDSOI With Active Step-Down Impedance Achieving 197dBc/Hz Peak FoM and 40MHz/V Frequency Pushing
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs
15.4 A 1024-element scalable optical phased array in 0.18µm SOI CMOS
An embedded DRAM technology for high-performance NAND flash memories
Session 25 overview: RF frequency generation from GHz to THz: RF subcommittee
Session 10 overview: Sensor systems: IMMD subcommittee
Millimeter-Sized 0.1pM LoD Wireless 16-Channel Organic-Electrochemical-Transistor-Based Electrochemical Sensing SoC
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques
14.4 A Class F-1/F 24-to-31GHz power amplifier with 40.7% peak PAE, 15dBm OP1dB, and 50mW Psat in 0.13μm SiGe BiCMOS
Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee
A 1V 136.6dB-DR 4kHz-BW $\Delta\Sigma$ Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm{m}$ CMOS
A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation
A mm-Wave 3-Way Linear Doherty Radiator with Multi Antenna Coupling and On-Antenna Current-Scaling Series Combiner for Deep Power Back-Off Efficiency Enhancement
A Blocker-Tolerant mm-Wave Low-Noise Amplifier Utilizing Doherty Active Load Modulation for Linearity Enhancement
7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO
A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radars
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS
An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS
15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch
27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI
A 70Mb/s -100.5dBm sensitivity 65nm LP MIMO chipset for WiMAX portable router
17.2 A 28nm 4.05µJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing
An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process
12.7 A 0.85V 600nW all-CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from -40 to 125°C
A CMOS Biosensor Array with 1024 3-Electrode Voltammetry Pixels and 93dB Dynamic Range
A 2.4GHz MEMS-Based Transceiver
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise
A Multi-Standard Analog and Digital TV Tuner for Cable and Terrestrial Applications
A 90nm CMOS 5Mb/s crystal-less RF transceiver for RF-powered WSN nodes
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS
A 6.5-to-10GHz IEEE 802.15.4/4z-Compliant 1T3R UWB Transceiver
35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS
27.5 A 30ppm <80nJ ring-down-based readout circuit for resonant sensors
A multi-path chopper-stabilized capacitively coupled operational amplifier with 20V-input-common-mode range and 3µV offset
An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS
Life Thermoscope: Integrated Microelectronics for Visualizing Hidden Life Rhythm
Multi-domain processors
23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications
SC1: Circuit design in advanced CMOS technologies: How to design with lower supply voltages
A direct digital frequency synthesizer with minimized tuning latency of 12ns
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping
A 0.18μm CMOS Dual-Band UWB Transceiver
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link