yusuke1997/dblp-id-title huggingface dataset:
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs
An Energy Measurement Front-End with Integrated In-Situ Background Full System Accuracy Monitoring Including the Current and Voltage Sensors
A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow
Session 28 overview: Wireless connectivity: Wireless subcommittee
A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise
ES1: Student research preview
11.2 3D ultrasonic fingerprint sensor-on-a-chip
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications
Near-independently regulated 5-output single-inductor DC-DC buck converter delivering 1.2W/mm 2 in 65nm CMOS
4.3 A 28GHz 4-Element MIMO Beam-Space Array in 65nm CMOS with Simultaneous Spatial Filtering and Single-Wire Frequency-Domain Multiplexing
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing
A Widely-Tunable Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect
A 3. 7V-to-1kV Chip-Cascaded Switched-Capacitor Converter with Auxiliary Boost Achieving > 96{\%}$ Reactive Power Efficiency for Electrostatic Drive Applications
26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS
9.7 A 94.3dB SNDR 184dB FoMs 4 th -Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator
A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency
Future system and memory architectures: Transformations by technology and applications
A wireless IC for time-share chemical and electrical neural recording
A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler
An 802.11a/b/g RF Transceiver in an SoC
15.9 An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS
Single-inductor dual-input dual-output buck-boost fuel-cell-li-ion charging DC-DC converter supply
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation
A 2mm 2 0.1-to-5GHz SDR receiver in 45nm digital CMOS
A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS
SSD memory subsystem innovation
A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer
A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators
3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration
A 110pJ/b multichannel FSK/GMSK/QPSK/p/4-DQPSK transmitter with phase-interpolated dual-injection DLL-based synthesizer employing hybrid FIR
18.2 A Monolithic E-Mode GaN 15W 400V Offline Self-Supplied Hysteretic Buck Converter with 95.6% Efficiency
A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations
A 45nm low-power SAW-less WCDMA transmit modulator using direct quadrature voltage modulation
50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS
A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC
A 15.2-ENOB continuous-time ΔΣ ADC for a 200mVpp-linear-input-range neural recording front-end
A 26-to-60GHz Continuous Coupler-Doherty Linear Power Amplifier for Over-An-Octave Back-Off Efficiency Enhancement
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs
30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies
A low-power 3-axis digital-output MEMS gyroscope with single drive and multiplexed angular rate readout
A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance
A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive Radar
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS
21.1 A 79pJ/b 80Mb/s full-duplex transceiver and a 42.5μW 100kb/s super-regenerative transceiver for body channel communication
A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS
25.2 A 10MHz 3-to-40V VIN tri-slope gate driving GaN DC-DC converter with 40.5dBµV spurious noise compression and 79.3% ringing suppression for automotive applications
9.11 A 98.3%-Peak-Efficiency Single-Mode Hybrid Buck-Boost Converter with 7mV Maximum Output Ripple for Li-Ion Battery Management
9.6 A 6 th -Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm
A 128-Channel 2mmx2mm Battery-Free Neural Dielet Merging Simultaneous Multi-Channel Transmission Through Multi-Carrier Orthogonal Backscatter
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing
A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode
21.7 Merging Hybrid and Multi-Phase Topologies: A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60: 1 Voltage Conversion Ratio and 868A/cm 3 Current Density
Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating
Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC
12.5 An error-based controlled single-inductor 10-output DC-DC buck converter with high efficiency at light load using adaptive pulse modulation
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI
A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems
A 4Gb/s current-mode optical transceiver in 0.18µm CMOS
36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In
22.1 A self-tuning resonant inductive link transmit driver using quadrature-symmetric phase-switched fractional capacitance
A 90μW 12MHz Relaxation Oscillator with a -162dB FOM
Image sensors for 3D capture
A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor
30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
7.4 A 413×240-pixel sub-centimeter resolution Time-of-Flight CMOS image sensor with in-pixel background canceling using lateral-electric-field charge modulators
Session 5 overview: Analog techniques: Analog subcommittee
4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient
A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC
9.1 A 13mm 2 40nm multiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver
A Scalable Quantum Magnetometer in 65nm CMOS with Vector-Field Detection Capability
A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost
29.1 A 0.42THz 9.2dBm 64-Pixel Source-Array SoC with Spatial Modulation Diversity for Computational Terahertz Imaging
27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS
A CMOS Cellular Interface Array for Digital Physiology Featuring High-Density Multi-Modal Pixels and Reconfigurable Sampling Rate
26.5 A 20µW Heartbeat Detection System-on-Chip Powered by Human Body Heat for Self-Sustaining Wearable Healthcare
A Sub-0.8pJ/b 16.3Gbps/mm 2 Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS
10.2 A digitally controlled 94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery arrays
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance
Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector
9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from -55°C to +125°C after heater-assisted voltage calibration
A -117dBc THD (-132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS
An 8b organic microprocessor on plastic foil
12.7 A power-management ASIC with Q-modulation capability for efficient inductive power transmission
19.3 A MEMS-Based Dynamic Light Focusing System for Single-Cell Precision in optogenetics
5.9 Haswell: A family of IA 22nm processors
IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023
11.1 A time-divided spread-spectrum code based 15pW-detectable multi-channel fNIRS IC for portable functional brain imaging
Unusual Data-Converter Techniques
A 0.014mm 2 9b switched-current DAC for AMOLED mobile display drivers
F4: Wireless low-power transceivers for local and wide-area networks
A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver
20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications
22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS
A mm-Wave quadrature VCO based on magnetically coupled resonators
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS
A Single-Channel 70dB-SNDR 100MHz-BW 4 th -Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping
22.5 A 0.5V 55µW 64×2-channel binaural silicon cochlea for event-driven stereo-audio sensing
Session 11 overview: Nonvolatile memory solutions
A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4 th -order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS
50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set
CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition
13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets
A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO
31.7 A 3.6W 16V-Output 180ns-Response-Time 94%-Efficiency SC Sigma Converter with Output Impedance Compensation and Ripple Mitigation for LiDAR Driver Applications
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane
A 45.8dB-SNR 120fps 100pF-Load Self-Capacitance Touch-Screen Controller with Enhanced In-Band Common Noise Immunity Using Noise Antenna Reference
A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOS
30.9 Normally-off computing with crystalline InGaZnO-based FPGA
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee
19.5 An HCI-healing 60GHz CMOS transceiver
A 1-to-5GHz All-Passive Frequency-Translational 4 th -Order N-path Filter with Low-Power Clock Boosting for High Linearity and Relaxed $\mathrm{P}_{\text{dc}}$-Frequency Trade-Off
A 480-Multiplication-Factor 13.2-to-17.3GHz Sub-Sampling PLL Achieving 6.6mW Power and -248.1 dB FoM Using a Proportionally Divided Charge Pump
2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner
24.1 A 24-to-30GHz Watt-Level Broadband Linear Doherty Power Amplifier with Multi-Primary Distributed-Active-Transformer Power-Combining Supporting 5G NR FR2 64-QAM with >19dBm Average Pout and >19% Average PAE
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS
14.6 A 76-to-81GHz 2×8 FMCW MIMO Radar Transceiver with Fast Chirp Generation and Multi-Feed Antenna-in-Package Array
28.8 Multi-Modal Peripheral Nerve Active Probe and Microstimulator with On-Chip Dual-Coil Power/Data Transmission and 64 2 nd -Order Opamp-Less ΔΣ ADCs
A low-noise active balun with IM2 cancellation for multiband portable DVB-H receivers
A fast-settling PLL frequency synthesizer with direct frequency presetting
A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor
15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW
32.5 E-band (71-to-86GHz) GaN Power Amplifier with 4.37W Output Power and 18.5% PAE for 5G Backhaul
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS
E2 Digital RF Fundamentally a New Technology or Just Marketing Hype?
17.9 A 105Gb/s 300GHz CMOS transmitter
A 150pW program-and-hold timer for ultra-low-power sensor platforms
25.3 A VCO with implicit common-mode resonance
A Single-Chip WCDMA Envelope Reconstruction LDMOS PA with 130MHz Switched-Mode Power Supply
A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces
32.4 A 0.4-to-1.2V 0.0057mm 2 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC
A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test
28.4 A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing
An 87mA·min iontophoresis controller IC with dual-mode impedance sensor for patch-type transdermal drug delivery system
23.4 Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation
Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs
A 300MHz-BW, 27-to-38dBm In-Band OIP3 sub-7GHz Receiver for 5G Local Area Base Station Applications
9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production
A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links
Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS
7.6 A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS
Session 23 overview: Short-reach links, XCVR techniques, & PLLs
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache
20.7 A multi-band inductor-less SAW-less 2G/3G-TD-SCDMA cellular receiver in 40nm CMOS
A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end
Wide Dynamic Range Imaging (Forum)
A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication
T-REX: A 68-to-567μs/Token 0.41-to-3.95μJ/Token Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization in 16nm FinFET
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution
19.6 A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit
24.2 A 14nm-FinFET 1Mb Embedded 1T1R RRAM with a 0.022µ m 2 Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference
A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm 2
Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS
6.7 A 160×120 Flash LiDAR Sensor with Fully Analog-Assisted In- Pixel Histogramming TDC Based on Self-Referenced SAR ADC
An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS
A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation
270-to-300GHz Double-Balanced Parametric Upconverter Using Asymmetric MOS Varactors and a Power-Splitting- Transformer Hybrid in 65nm CMOS
A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOS
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications
5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injection
A 21pJ/frame/pixel Imager and 34pJ/frame/pixel Image Processor for a Low-Vision Augmented-Reality Smart Contact Lens
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
Clock generation for a 32nm server processor with scalable cores
104Gb/s 2"-1 and 110Gb/s 2-1 PRBS Generator in InP HBT Technology
A 110µW 2.5kb/s -103dBm-Sensitivity Dual-Chirp Modulated ULP Receiver Achieving -41dB SIR
33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend
A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS
A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters
A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection
A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector
A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz
Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee
25.4 A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz
A 330μm×90μm opto-electronically integrated wireless system-on-chip for recording of neural activities
Forewarned is four armed: Classic Analog misteakes to avoid
A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change
Spur-reduction techniques for PLLs using sub-sampling phase detection
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
A 0.3V biofuel-cell-powered glucose/lactate biosensing system employing a 180nW 64dB SNR passive δς ADC and a 920MHz wireless transmitter
A 301.7-to-331.8GHz source with entirely on-chip feedback loop for frequency stabilization in 0.μm BiCMOS
ES3: How to achieve 1000× more wireless data capacity? 5G?
On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS
An Eye-Opening Arbiter PUF for Fingerprint Generation Using Auto-Error Detection for PVT-Robust Masking and Bit Stabilization Achieving a BER of 2e-8 in 28nm CMOS
13.4 A 6.3mW BLE transceiver embedded RX image-rejection filter and TX harmonic-suppression filter reusing on-chip matching network
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
A 1.2V 23nm 6F 2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface
A super-regenerative radio on plastic based on thin-film transistors and antennas on large flexible sheets for distributed communication links
A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry
Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers
9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands
Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit
6.7 A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273pm 2 /Channel and 1.9mV DVO for 6285-PPI OLED-on-Silicon Displays
SE4: ICs in PandemICs
An Electronically Tunable Multi-Frequency Air-Coupled CMUT Receiver Array with sub-100µPa Minimum Detectable Pressure Achieving a 28kb/s Wireless Uplink Across a Water-Air Interface
6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee
Session 13 overview: High-performance wireless
A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s
Session 30 Overview: Non-Volatile Memories Memory Subcommittee
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS
28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS
A 100W and 91% GaN-Based Class-E Wireless-Power-Transfer Transmitter with Differential-Impedance-Matching Control for Charging Multiple Devices
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems
20.6 A blocker-resilient wideband receiver with low-noise active two-point cancellation of >0dBm TX leakage and TX noise in RX band for FDD/Co-existence
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS