yusuke1997/dblp-id-title huggingface dataset:
Ultra Low-power FSM for Control Oriented Applications
Minimization of L 2 -sensitivity for a class of 2D state-space digital filters subject to L 2 -scaling constraints
Perovskite Nanocrystal Enhanced Vertically Stacked-Photodiode Image Sensor for Wavelength Resolved UV Imaging
A fast settling CMOS operational amplifier
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems
Reed-Muller weight and literal vectors for NPN classification
Design of Finite-Wordlength IIR Digital Filters in the Time/Spatial Domain
Image quality optimization using computationally efficient variable QoS multicarrier bit-allocation
Scalable low power digital filter architectures for varying input dynamic range
Design of ultra high-speed CMOS CML buffers and latches
Hardware Accelerator for Feature Matching with Binary Search Tree
A 103.9-dB SNDR 5-kHz BW Continuous-Time Dynamic Zoom ADC with Switched Resistor Technique for Reducing Thermal Noise
Design of a Readout Circuit Chip for a Cosmic Ray Muon Detector with Multi-Angular Acceptance
QContext: Context-Aware Decomposition for Quantum Gates
NBTI-aware dual threshold voltage assignment for leakage power reduction
Emerging multi-level architectures and unbalanced mismatch calibration technique for high-efficient and high-linear LINC systems
Understanding Loading Effects of RC Uniform Interconnects
26 GHz Solid State Power Amplifier in a 0.15-μm GaN on SiC technology
Modeling of switched DC-DC converters by mixed s-z description
Improved Chen-Smith image coder
Fault Detection and Location of Transmission Lines Based on Convolutional Neural Network
Parameter Extraction of HEMT Models from Multibias S-Parameters
Joint multi-CDN and LT-coding for video transport over HTTP
Constrained Sorter Design using Zero-One Principle
A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit
Multi-Bit Flip-Flop Based Timing and Power Optimization under Advanced Technology Nodes
Performance improvement of DS-SS communication systems using an adaptive IIR notch filter
Chip-scale magnetic sensing and control of nanoparticles and nanorods
FPGA-based neural probe positioning to improve spike sorting with OSort algorithm
Crosstalk driven routing resource assignment
Continuous-time Analog Computing Circuits for Solving The Electromagnetic Wave Equation
Efficient improvement of side information in GOB-based DVC system
A 1V 15-bit Audio ΔΣ ADC in 0.18µm CMOS
Feed-forward compensated high switching speed digital phase-locked loop frequency synthesizer
Finite-time-domain synthesis of recursive linear time-variant causal digital filters by separable sequences
Application of the SD to LCTI systems 2
A multi-core architecture of digital back-end for large mutual capacitance touch sensing systems
Torus Doubling and Hyperchaos in a Five Dimensional Hysteresis Circuit
A High Constancy Rail-to-rail Level Shift Generator for SEIR-based BIST circuit for ADCs
VBR video delivery using monotonic-decreasing rate scheduling
32-Channel ultra-low-noise arbitrary signal generation platform for biopotential emulation
Direct RF sampling mixer with recursive filtering in charge domain
Spectral shaping of clock jitter errors for continuous time sigma-delta modulators
A Switched Capacitor Implementation of the Generalized Linear Integrate-and-fire Neuron
Novel linear analog-adder using a-IGZO TFTs
Multi-plet two-channel perfect reconstruction filter banks
A systematic technique for optimizing multiple branch FIR filters for sampling rate conversion
Analysis of noise in higher-order translinear filters
A space-time transformation approach for adaptive clutter suppression in airborne radar
A high-performance CMOS multiphase voltage-controlled oscillator for communication systems
Scalable Mean Rate Signal Encoding Analog Neural Network
Adaptive Inter-layer Intra Prediction in Scalable Video Coding
Dynamic Reconfigurability in Embedded System Design
Structural local DCT sparse appearance model for visual tracking
An active noise control system based on simultaneous equations method without auxiliary filters
Truncated MCM using pattern modification for FIR filter implementation
Built-in current sensor with reduced voltage drop using thin-film transistors
The Role of Memories in Transprecision Computing
Analysis of a Dual N-Path Filter
A 37.37μW-Per-Cell Multifunctional Automated Nanopore Sequencing CMOS Platform with 16∗8 Biosensor Array
VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications
On Signal-Flow Graph Analysis of Multiphase SC Networks
Compensation Architecture to Alleviate Noise Effects in RRAM-based Computing-in-memory Chips with Residual Resource
Odour Localization in Neuromorphic Systems
A digital clock-less pulse stretcher with application in deep sub-nanosecond pulse detection
Challenges and recent advances in IR-UWB system design
Rail-to-rail low-power fully differential OTA utilizing adaptive biasing and partial feedback
A novel algorithm for signed-digit online multiply-accumulate operation and its purely signed-binary hardware implementation
Evaluation of microcell CDMA system in consideration of intercell correlation
A 1.2 V NPN-only log-domain integrator
Design-Oriented Analysis of CD Operating-Point Instability
Realizable reduction of RLC circuits using node elimination
KLaGen - A Generator of Static CMOS-cell Layout from Circuit Schematics
Poisson AER generator: inter-spike-intervals analysis
Long period pseudo random bit generators derived from a discretized chaotic map
MEMS automotive collision avoidence radar beamformer
A Hierarchical Approach to Clock Routing in High Performance Systems
A 16 Bit Incremental ADC with Swapping DAC for Low Power Sensor Applications
Adaptive Control of Sampling Rate Using a Local Time-Domain Sampling Theorem
Surge Current Minimization in High-level Synthesis
Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy
Embedded facial image processing with Convolutional Neural Networks
A 87 dB, 2.3 GHz, SiGe BiCMOS operational transconductance amplifier
Frequency-Domain Analysis of A/D Converter Nonlinearity
LIRSRN: A Lightweight Infrared Image Super-Resolution Network
Virtual-scan: a novel approach for software-based self-testing of microprocessors
Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes
The IMD cancellation characteristics of predistortion linearizer in microwave transistor
DPCNN: A Modular Chip for Large CNN Arrays
Development of a generalized switched-capacitor DC/DC converter with bi-directional power flow
L2-Sensitivity Analysis and Minimization for Generalized Direct-Form II Realization of 2-D Separable-Denominator Digital Filters
Post-Quantum and Blockchain-Based Attestation for Trusted FPGAs in B5G Networks
Design of bursting in two-dimensional discrete-time neuron models
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability
Content-based retrieval from nonstationary image database
Heartbeat-Based Synchronization Scheme for the Human Intranet: Modeling and Analysis
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course
Design of a high-frequency second-order Delta-Sigma modulator
Direction finding for multiuser correlated signals based on spatial signature estimation in cyclic cumulant domain
A novel unequal error protection approach for error resilient video transmission
Crosstalk Attack Resilient RNS Quantum Addition
Theoretical analysis of hysteresis neural network solving N-Queens problems
An accurate self-bias threshold voltage extractor using differential difference feedback amplifier
Dynamic power optimization of the trace-back process for the Viterbi algorithm
Dynamic compact thermal model of a package
Exploiting reconfigurability for low-power control of embedded processors
A high performance Full Adder based on Ballistic Deflection Transistor technology
Detection and compensation of sensor malfunction in time delay based direction of arrival estimation
Parallelism/regularity-driven MIMO detection algorithm design
Power-on digital calibration method for delta-Sigma ADCs
Enhancing Computer Organization Education: A Reformative Teaching Approach
Control Loop Architectures for High-Frequency Switching-Mode DC-DC Buck Converters
Addressable current reference array with 170dB dynamic range
A CMOS imager with focal plane compression
On the feasibility of application of class E RF power amplifiers in UMTS
Mixed INT4-INT8 LLM Quantization via Progressive Layerwise Assignment with Dynamic Sensitivity Estimation
Multi-Level Parallelization Scheme for Distributed HEVC Encoding on Multi-Computer Systems
Novel Reservoir Computing Approach for the Detection of Chaos
Log-Domain Time-Multiplexed Realization of Dynamical Conductance-Based Synapses
Low-power and low-latency cluster topology for local traffic NoCs
Robust strictly positive real synthesis for convex combination of the fifth-order polynomials
A VLSI architecture of cost calculation and all-zero block detection for fractional motion estimation
Financial Loan Overdue Risk Detection via Meta-path-based Graph Neural Network
An automatic three-dimensional human behavior analysis system for video surveillance applications
ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications
A 4-channel wearable wireless neural recording system
Design and evaluation of steganography for voice-over-IP
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS
On-line Learning of RVFL Neural Networks on Finite Precision Hardware
Parametric Study of Performance of Remote Photopletysmography System
A digital-to-analog converter for a cortical microelectrode stimulator
A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization
A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation
Transform-Based Feature Map Compression for CNN Inference
High Accuracy RF Modulation Recognition using Low-Dimensional Encoder-based SNN
Macrocell placement with temperature profile optimization
Accurate performance prediction of multi-GHz CML with data run-length variations
A pseudo-CCM buck converter with freewheel switching control
A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS
An Angledetector Based on Magnetic Sensing
Adaptive quantization in min-sum based irregular LDPC decoder
Architecture Generator for Type-3 Unum Posit Adder/Subtractor
Occasional Delayed Feedback Control for Switched Autonomous Systems
Using dynamic dependence analysis to improve the quality of high-level synthesis designs
Semiconductor Spin Qubits - A Scalable Platform for Quantum Computing?
A cooperative network of reconfigurable stair-climbing robots
An Area-Efficient VLSI Architecture for Parallel Jacobi-based Eigenvalue Decomposition with Inherent Eigenvalue Sorting
A modified univariate search algorithm
Frequency domain blind source separation using small and large spacing sensor pairs
A 1.5-V Low-Power Common-Gate Low Noise Amplifier for Ultrawideband Receivers
A coupled memcapacitor emulator based relaxation oscillator
Image deblocking via group sparsity optimization
FewShotEEG Learning and Classification for Brain- Computer Interface
Development of a decision support system for heart disease diagnosis using multilayer perceptron
Scheduling with multiple voltages under resource constraints
Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure
FPGA realization of RNS to binary signed conversion architecture
DehazeDiff: When Conditional Guidance Meets Diffusion Models for Image Dehazing
CTU-Level Adaptive Quantization Method Joint with GOP based Temporal Filter for Video Coding
Bipolar merged arithmetic for wavelet architectures
A novel VC routing algorithm based on chaotic neural networks in ATM networks
Improved mode selection in hybrid error concealment for multi-broadcast-reception
Investigation on dynamic channel allocation strategies suitable for PRMA schemes
Assessment of Robustness of Power Systems from the Perspective of Complex Networks
Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment
A cross-layer adaptation HCCA MAC for QoS-aware H.264 video communications over Wireless Mesh Networks
Context-based binary arithmetic coding with stochastic bit reshuffling for advanced fine granularity scalability
A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm
60 GHz meta-material wideband antenna for FPGA Giga bit data transmission
Approaches to digital compensation of excess loop delay in continuous-time Delta-Sigma modulators using a scaled quantizer
An NMOS-sided biased rectifier with enhanced dynamic range for neural stimulators
Probabilistic Modelling of Phase-tuned Disparity Energy Neuron Populations
Integration of Reconfigurable RF Manifolds with Software Defined Systems
A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors
On Chaotic Digital Encoding and Generalized Inverses
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture
Efficient DOA Estimation by a Specific SVD Algorithm
A programmable base 2D-LNS MAC with self-generated look-up tables
Design technique of an on-chip, high-voltage charge pump in SOI
Preliminary Results Towards Reinforcement Learning with Mixed-Signal Memristive Neuromorphic Circuits
Study of sub-5 nm RRAM, tunneling selector and selector less device
A multi-channel neural stimulator with resonance compensated inductive receiver and closed-loop smart power management
Frequency-response masking based filters with the even-length bandedge shaping filter
An automatic tuning scheme for high frequency bandpass filters
Easily Testable PLA-based FSMS
Activation of secure zones in many-core systems with dynamic rerouting
VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit
A background correction technique for timing errors in time-interleaved analog-to-digital converters
Off-Line Performance Maximisation in Feed-Forward Neural Networks by Applying Virtual Neurons and Covariance Transformations
Neural modelling of the large-signal drain current of the dual-gate MESFET with DC and pulsed I-V measurements
A fast adaptive quantization matrix selection method in H.264/AVC
Foreground-based depth map generation for 2D-to-3D conversion
A novel improvement technique for high-level test synthesis
A configurable divider using digit recurrence
Local independent component analysis applied to highly segmented detectors
An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method
Multithresholding of mixed-type documents
Decoupled optimization technique for design of switching regulators using genetic algorithms
An Ultra Low Power Circuits M.Sc. Course Proposal for the GreenChips-EDU Platform
Synthesis of Optimal Nonrecursive Filters
Probabilistic Fault Diagnosis in Communications Architectures
A Digital ISFET Sensor with In-Pixel ADC
A Hybrid HDSL Echo Canceler
An adaptive Viterbi algorithm based on strongly connected trellis decoding
Shortest Path Searching for the Robot Walking Using an Analog Resistive Network
OTED: Encoding Optimization Technique Targeting Energy-Efficient HEVC Decoding
High-speed and high-linearity ring oscillator based pulse width modulator
Comparison of DTC Segmentation Methods in Fractional-N Frequency Synthesizers
Digitally Intensive Mixed-Signal Approach for Self-Interference Cancellation in LTE-A/5G-Transceivers
A GaN-Based Gate Driver with Adaptive Charge Sharing Bootstrap Technique to Improve the Conduction Loss
Real-time arm movement recognition using FPGA
A CMOS monolithic implementation of a nonlinear interconnection module for a corticonic network
Live Demonstration: Human Body Communication Health Monitoring System Using Flexible Substrate
VLSI implementation issues of lattice decoders for MIMO systems
Recursive all-lag reference-code correlator and its efficient implementation
Spiking neuromorphic networks with metal-oxide memristors
A Template Matching based Extension for Merge with Motion Vector Difference
Design of Cascade and One-Shot Mixed-Mode Recursive Multipliers for GF(2 N ) Polynomials
Fingerprint recognition using CNNs: fingerprint preprocessing
SIMD architecture for job shop scheduling problem solving
Design techniques for low-power cascaded CML gates
Reconfigurable two-stage Nyquist filters utilizing the farrow structure
Design of optimal non-separable 2-D half-band filters
A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power
Feature-Embedding Triplet Networks with a Separately Constrained Loss Function
A Low-Power Multimode Eight-Channel AFE for dToF LiDAR
Fabrication of a thin film micro polarization array
Statistical analysis of the FXLMS algorithm with a nonlinearity in the secondary-path
Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison
Real time modal analysis of power system oscillations
A 4×4 Logarithmic Spike Timing Encoding Scheme for Olfactory Sensor Applications
A 630 Mbps non-binary LDPC decoder for FPGA
Automated Service Discovery for Social Internet-of-Things Systems
A locally-adaptive algorithm for measuring blocking artifacts in images and videos
Secure medical information exchange with reversible data hiding
. A new switch compensation technique for inverted R-2R ladder DACs
A quadrature UWB frequency synthesizer with dynamic settling-time calibration
An efficient processor for joint barrel distortion correction and color demosaicking
All digital time tracking loop for DVB-H and DVB-T
A high speed scalable and reconfigurable fuzzy controller
JPEG-2000 on an advanced architecture, multiple execution unit DSP
A SET quantizer circuit aiming at digital communication system
Event-Triggered Extended Kalman Filter for UAV Monitoring System
An End-to-End Deep Generative Network for Low Bitrate Image Coding
A CMOS multi-sine signal generator for multi-frequency bioimpedance measurements
DOA-matrix decoder for STBC-MC-CDMA systems over frequency-selective channel
Analysis of ultralow-power asynchronous ADCs
Improvement of Bootstrapped Switch using Track and Precharge Phase
Digital correction of circuit imperfections in cascaded Σ-Δ modulators composed of 1st-order sections
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
A Bias-Flip Interface and Dual-Input DC-DC Converter for Piezoelectric and RF Energy Harvesting
Subband adaptive filtering with critical sampling using the data selective affine projection algorithm
Highly Reliable Active Pixel Circuit Based on Dual-Gate TFTs for Dynamic X-Ray Medical Imaging
Clock jitter effect in continuous-time oversampling converters
A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection
WiiEMG: A real-time environment for control of the Wii with surface electromyography
28 GHz VCO Using Magnetically Tuning Trifilar Transformer in Cryogenic CMOS Application
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications
A rail to rail, slew-boosted pre-charge buffer
A LUT-based matrix multiplication using neural networks
Spiking Auto-Encoder Using Error Modulated Spike Timing Dependant Plasticity
A new hardware efficient design for the one dimensional discrete Fourier transform
An ion imaging ISFET array for Potassium and Sodium detection
An Integrated Environment for HW/SW Co-design based on a CAL Specification and HW/SW Code Generators
: Optimized transmultiplexers for multirate systems
Layered video over IP networks by using selective drop routers
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters
A feedforward compensated high-linearity differential transconductor for RF applications
Cascaded ΣΔ ADC with adaptive interstage coupling
A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference
An in-memory computing circuit with carry-over thermometer coding for a hippocampus-inspired model
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic
Obtaining Symbolic Network Functions of Large Circuits - An Algebraic Approach
A design methodology for logic paths tolerant to local intra-die variations
VLSI implementation of type-2 fuzzy inference processor
A pulse communication flow ready for accelerated neuromorphic experiments
Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder
A Simplified Structure for FIR Filters with an Adjustable Fractional Delay
Parallel Random Sampling with Multiprocessor System
Output impedance linearization technique for current-steering DACs
Competing and accommodating behaviors of peace SOM
Mutual transformations between Haar wavelet and arithmetic spectra
A Performance-driven Approach to the High-level Synthesis of DSP Algorithms
Live Demonstration: Neuromorphic Row-by-Row Multi-Convolution FPGA Processor-SpiNNaker Architecture for Dynamic-Vision Feature Extraction
Live Demonstration: Sea Wave Energy Harvester for Environmental Monitoring Buoys
Wireless wearable ECG sensor design based on level-crossing sampling and linear interpolation
An architecture for fractal image compression using quad-tree multiresolution
Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs
Reduce energy requirements by coupling a poly-phase pre-filter and cic filter in high-performance Sigma-Delta A/D converters
Noisy speech recognition by hierarchical recurrent neural fuzzy networks
Stream-Driven Acceleration for Embedded RISC-V SoCs
Recurrent neural network as a KWTA selector: A synthesis procedure
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms
Generalizations of adjoint networks technique for RLC interconnects model-order reductions
A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs
Traffic- and Thermal-aware Adaptive Beltway Routing for three dimensional Network-on-Chip systems
Self-repairing hardware with astrocyte-neuron networks
A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers
Quality Enhancement in H.264 Transform Domain Downsizing
MPEG-4 authoring tool for the composition of 3D audiovisual scenes
RLS-Laguerre lattice adaptive filtering: error feedback and array-based algorithms
Basis picking for matching pursuits audio compression
Analysis of imperfections in N-phase high-Q band-pass filters
An In-DRAM Neural Network Processing Engine
Design of ring oscillator structures for measuring isolated NBTI and PBTI
Fast Imaging in the Dark by using Convolutional Network
A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting
An analysis of the CCA approach for blind source separation and its adaptive realization
Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations
Frequency estimation of sinusoids in colored noise
Efficient fully-floating double-sampling integrator for DeltaSigma ADCs
Reconfigurable Leakage-based Weak PUF in 65nm CMOS with 0.63% instability
A low power 10-transistor full adder cell for embedded architectures
Two-fold singularity in nonsmooth electrical systems
A Basilar Membrane Resonator for an Active 2-D Cochlea
Pseudo-chaotic lossy compression of TRBGs
Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems
Analog VLSI Circuits for Primitive Sensory Attention
Stability analysis of multiple equilibria for recurrent neural networks with discontinuous Mexican-hat-type activation function
Digital Back-end Design Considerations of a Laser Heterodyne Radiometer