yusuke1997/dblp-id-title huggingface dataset:
A 30-110V Resonant Buck-Boost Power-Bus Charger Achieving 50-A Peak Laser-Current Pulse Generation in 2ns for MHz-Frequency Automotive LiDAR Transmitter
A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology
A Nyquist rate pixel level ADC for CMOS image sensors
X/Ku Band CMOS LNA Design Techniques
On the selection of on-chip inductors for the optimal VCO design
A monolithic vernier-based time-to-digital converter with dual PLLs for self-calibration
A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS
A Secure Digital In-Memory Compute (IMC) Macro with Protections for Side-Channel and Bus Probing Attacks
An improved architecture of the mixed mode clock/data recovery for DVD read channel
NEEDS: Moving nanoscience to nanotechnology
Fully integrated on-chip DC-DC converter with a 450x output range
A stereo 110 dB multi-rate audio ΔΣ DAC with Class-G headphone driver
A high-speed BiCMOS switched-current track-and-hold circuit
Passive & Active Control of Regenerative Standing & Soliton Waves
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion
An overview of library characterization in semi-custom design
An analysis of the design processes required for the technology conversion of SoC intellectual property
A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter
Resonant clocking using distributed parasitic capacitance
Determination of Power Gating Granularity for FPGA Fabric
A Calibration-free 80MHz CT DSM Using Dual Quantization and ISI Shuffler Achieving 106.2dB SFDR
DSP techniques for optical transceivers
Piezoresistive CMOS-MEMS pressure sensor with ring oscillator readout including Δ-Σ analog-to-digital converter on-chip
A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation
A 22-to-32 GHz 4-Beam 32-Element Polarization Reconfigurable Fully-Connected Fully-Bidirectional MIMO Transceiver for Emerging Space-Air-Ground-Sea Integrated Network
Next-Generation Domain-Specific Accelerators: From Hardware to System
AMS system simulation techniques
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS
Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS
Advanced memory topics
A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS
RF transceivers and building blocks
Thermal noise modeling of nano-scale MOSFETs for mixed-signal and RF applications
A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits
A 123μW standby power technique with EM-tolerant 1.8V I/O NMOS power switch in 28nm HKMG technology
System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface
A 2.5Gb/s Burst-Mode CDR based on a 1/8 th rate Dual Pulse Ring Oscillator
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation
A 0.92mm 2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application
Modeling of advanced devices
A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT Technology
Modeling and analysis of high-speed links
Ultra-low power circuit techniques for a new class of sub-mm 3 sensor nodes
A 1A, 20MHz/100MHz dual-inductor 4-output buck converter with fully-integrated bond-wire-based output filters for ripple reduction
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS
A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor
Analog IP migration using design knowledge extraction
A fractional-N PLL modulator with flexible direct digital phase modulation
A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data converters
WATSON: a multi-objective design space exploration tool for analog and RF IC design
A new router for reducing "antenna effect" in ASIC design
A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads
A process and temperature insensitive CMOS linear TIA for 100 Gbps/λ PAM-4 optical links
5 Gbps BPSK CMOS transmitter with on-chip antenna using Gaussian monocycle pulses
CMOS IC nanometer technology failure mechanisms
A Configurable Dual-Mode PRINCE Cipher with Security Aware Pipelining in 65nm for High Throughput Applications
Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited)
A self adaptive programming method with 5 mV accuracy for multi-level storage in FLASH
Piezoelectric power generation interface circuits
Placing substrate contacts into mixed-signal circuits controlling circuit performance
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes
Evolution of CMOS Technology at 32 nm and Beyond
A 0.010mm 2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor
An analog front-end LSI with on-chip isolator for V.90 56 kbps modems
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design
A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS
A 4 channel analog front end for central office ADSL modems
A Compact Programmable CMOS Reference With ±40μV Accuracy
An 871nW 96.2dB-SNDR Pipelined NS SAR ADC Achieving 180.8dB-FoMSNDR with a Charge-Efficient CLS-Assisted Two-Stage FIA
A low input impedance fully differential CMOS transresistance amplifier using cascode regulation
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider
Low-power technique for on-chip memory using biased partitioning and access concentration
A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver [mobile phone applications]
Analysis of spectral spreading in a phase-modulated system for 1.75-GHz GSM RF transmitter design
Device and circuit design issues in SOI technology
A Passive Crystal-Less Tag Demonstrating Battery-Free GSM-CW/5G-NR Downlink and BLE-to-BLE/BLE-to-WiFi/WiFi-to-WiFi Multi-Channel-Hopping Uplink with Smartphones
S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage
A wide-band active-RC filter with a fast tuning scheme for wireless communication receivers
A 7×7×2mm 3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS
Clock generator using factorial DLL for video applications
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability
Modeling and analysis of manufacturing variations
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip
A 450 MS/s 10-bit time-interleaved zero-crossing based ADC
Forward Error Correction Requirements for Data Center Connectivity
Low-power and high-linearity mixer design using complex transconductance equivalent circuit
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime
Smart CMOS substrates for bioelectronic interfaces: Overview and trends
RTL morphing: making IP-reuse work in system-on-a-chip designs
Application-dependent scaling tradeoffs and optimization in the SoC era
Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems
A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity
Applying placement-based synthesis for on-time system-on-a-chip design
Charge steering: A low-power design paradigm
Nucleic Acid Extraction, Amplification, and Detection on Si-based Microfluidic Platforms
Scalable behavior modeling for 3D field-programmable ESD protection structures
MIMO techniques for high data rate radio communications
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
An Efficient Wireless Power and Data Transfer System with Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Dual-Input Voltage Regulation
An energy-efficient SoC for closed-loop medical monitoring and intervention
A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS
A low-cost 0.98μW0.8V oversampled SAR ADC with pre-comparison and mismatch error shaping achieving 84.5dB SNDR and 103dB SFDR
A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os
HVM performance validation and DFM techniques used in a 32nm CMOS thermal sensor system
A Highly-Integrated 20-300V 0.5W Active-Clamp Flyback DCDC Converter with 76.7% Peak Efficiency
An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up
Advances in high-speed continuous-time delta-sigma modulators
A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35μm CMOS
A 56MΩ CMOS TIA for MEMS applications
Cryo-CMOS for Analog/Mixed-Signal Circuits and Systems
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer
A broadband low-noise front-end amplifier for ultra wideband in 0.13 μm CMOS
SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process
Data-dependant sense-amplifier flip-flop for low power applications
A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter
A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration
A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp
A 256-element CMOS imaging receiver for free-space optical communication
A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process
A 12-b 56MS/s pipelined ADC in 65nm CMOS
A supply-scalable differential amplifier with pulse-controlled common-mode feedback
Jitter injection for on-chip jitter measurement in PI-based CDRs
A 9.8-11.5 GHz quadrature ring oscillator for optical receivers
A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 μm CMOS
VCOs with very low sensitivity to noise on the power supply
Band-gap circuit design challenges in high-performance 32-nm technology
A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolution
Wireline transceivers
A Mixed-Signal Near-Sensor Convolutional Imager SoC with Charge-Based 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection
A feedback controlled coil driver for transcutaneous power transmission
Present and future applications of Silicon Carbide devices and circuits
SoC architectures for signal processing
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration
CMOS Low Noise Amplifier with Capacitive Feedback Matching
Design-space exploration of backplane receivers with high-speed ADCs and digital equalization
CCE: A 28nm Content Creation Engine with Asymmetric Computing, Semantic-Driven Instruction Generation and Collision-Free Outlier Mapper for Video Generation
An implemented of H.264 video decoder using hardware and software
A 110 MHz 350 mW 0.6μ CMOS 16-state generalized-target Viterbi detector for disk drive read channels
A highly linear CMOS buffer circuit with an adjustable output impedance
Substrate injection and crosstalk in CMOS circuits
Statistical and Corner Modeling of Interconnect Resistance and Capacitance
A 2.6Gb/s 1.56mm 2 near-optimal MIMO detector in 0.18µm CMOS
Solution to ESD Induced Pocket Isolation Failure in Multi Well CMOS
Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs
A new method for multiplying the Miller capacitance using active components [voltage regulator example]
StimDust: A 6.5mm 3 , wireless ultrasonic peripheral nerve stimulator with 82% peak chip efficiency
A Q-enhanced Transformer Coupling Dynamic Dual-Mode 5GHz Bandpass NB / Interference Rejection UWB Filter
RF-CMOS-MEMS based frequency-reconfigurable amplifiers
A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA
Energy efficient computing in large scale systems
Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiver
An In-Memory-Computing Charge-Domain Ternary CNN Classifier
A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping
A Saturation-Free 3.6V/1.8V DM/CM Input Range 46.6mV/μs Artifacts Recovery Sensor Interface using CT Track-and-Zoom
Process variability characterization and interconnect modeling
In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test
A 0.0022 mm 2 , 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping
A 0.5-V 16 GHz-20 GHz differential injection-locked divider in 0.18-μm CMOS process
A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)
A CMOS direct-conversion transceiver for IEEE 802.11a/b/g WLANs
A Fast-transient Buck Converter with One-Cycle-Balancing Control for Single and Consecutive Load Steps
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications
High performance open-loop AM modulator designed for power control of E-GPRS polar modulated power amplifier
A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation
A 54-862 MHz CMOS direct conversion transceiver for IEEE 802.22 cognitive radio applications
GPU-accelerated time-domain circuit simulation
System technology co-optimization and design challenges for 3D IC
An Integrated 90V Switch Array for Medical Ultrasound Applications
A 900-MHz T/R switch with a 0.8-dB insertion loss implemented in a 0.5-μm CMOS process
5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025mm 2
A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularity
Fully integrated capacitive converter with all digital ripple mitigation
Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application
Versatile beamforming ASIC architecture for broadband fixed wireless access
Design considerations and DFT to enable testing of digital interfaces
Including inductive effects in interconnect timing analysis
ADC-based Wireline Transceiver
Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technology
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing
Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications
A 1.0 V GHz range 0.13 μm CMOS frequency synthesizer
A 28nm 8928Kb/mm 2 -Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM
Modeling of resistance in FinFET local interconnect
Analog filter design: Current design techniques and trends
Modeling, Design, and Verification for the Analog Front-end of a MEMS-based Parallel Scanning-probe Storage Device
0.61W/mm 2 resonant inductively coupled power transfer for 3D-ICs
A 24.6-to-30.6GHz Magnetic-Isolated Sub-Sampling PLL with a Fast-Locking FLL Achieving 64.9fs Jitter, -253.3dB FoMJ, and -69.1dBc Reference Spur in 65nm CMOS
Clock verification in the presence of IR-drop in the power distribution network
A 0.37mm 2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2 nd -order Vector-Quantizer DEM
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface
Session 6 - Analog circuits using digital cells
A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications
Interferer-Tolerant RX Front-End Architectures
MIMO signal processing - the next frontier for capacity enhancement
A 1-10MHz Frequency-Aware CMOS Active Rectifier with Dual-Loop Adaptive Delay Compensation and >230 mW Output Power for Capacitively Powered Biomedical Implants
A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments
A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates
A 3D Multi-Aperture Image Sensor Architecture
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology
A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping
RRAM fabric for neuromorphic and reconfigurable compute-in-memory systems
180Vpp output voltage, 24MHz bandwidth, low power class AB current-feedback high voltage amplifier for ultrasound transmitters
Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systems
SCPA revolution: Linearization of multiphase SCPAs
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter
Millimeter-Wave CMOS Phased-Array Transceiver Supporting Dual-Polarized MIMO for 5G NR
A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
A 915-1220 TOPS/W Hybrid In-Memory Computing based Image Restoration and Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS
A 3-level PWM ADSL2+ CO line driver
A 28GHz Two-Way Current Combining Stacked-FET Power Amplifier in 22nm FD-SOI
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS
A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars
Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells
Session 21 - Analog techniques II
Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane Ethernet
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy
A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure
A CMOS 22-29GHz Receiver Front-End for UWB Automotive Pulse-Radars
Welcome from the CICC Committee!
A 16 pJ/bit 0.1-15Mbps Compressive Sensing IC with on-chip DWT Sparsifier for Audio Signals
Design and technology interaction beyond 32nm
4 Gbps high-density AC coupled interconnection
Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanisms
True Random Number Generator circuits based on single- and multi-phase beat frequency detection
110-GHz-Bandwidth InP-HBT AMUX/ADEMUX Circuits for Beyond-1-Tb/s/ch Digital Coherent Optical Transceivers
A 0.6-mm 2 Powering and Data Telemetry System Compatible with Ultrasound B-Mode Imaging for Freely Moving Biomedical Sensor Systems
A 4×4 5-6GHz CMOS Wi-Fi Transceiver Front-End for Fiber-to-the-Room with Analog Beamforming Achieving 27dBm 1024 QAM MCS11 EIRP and -45dB EVM Floor
A continuous-time delta-sigma modulator with self-ELD compensated quantizer
A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay
Modeling and optimization of inductors with patterned ground shields for a high performance fully integrated switched tuning VCO
A Compact 275 GHz Harmonic VCO with -2.6 dBm Output Power in a 130 nm SiGe Process
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC
Field configurable system-on-chip device architecture
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches
Low drain voltage S/H type PWM LED current driver for BLU in mobile LCD
An embedded stack microprocessor for SDH telecommunication applications
All Rivers Flow to the Sea: A High Power Density Wireless Power Receiver with Split-Dual-Path Rectification and Hybrid-Quad-Path Step-Down Conversion
A lumped component programmable delay element for Ultra-Wideband beamforming
On-chip temperature control circuit using common devices
CMOS biochips: Challenges and opportunities
A next generation architecture optimized for high density system level integration
FPGA fingerprinting techniques for protecting intellectual property
Multisite bio-stimulating implants magnetoelectrically powered and individually programmed by a single transmitter
Scaling of analog-to-digital converters into ultra-deep-submicron CMOS
A novel low cost, high performance and reliable silicon interposer
Finite-length signal quantization using discrete optimization
A CMOS direct conversion transmitter with integrated in-band harmonic suppression for IEEE 802.22 cognitive radio applications
A 1.5V direct digital synthesizer with tunable delta sigma modulator in 0.13 μm CMOS
Full-rate injection-locked 10.3Gb/s clock and data recovery circuit in a 45GHz-f T SiGe process
Measurements of the silicon die characteristics of packaged drivers for high-speed I/O
A new method for reuse-driven design of digital circuits
A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption
Cypress Delta39K TM . A memory-rich, high performance, scalable CPLD architecture
A fully differential ultra-compact broadband transformer based quadrature generation scheme
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL
A 24-GHz CMOS sub-harmonic mixer based zero-IF receiver with an improved active balun
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC
Analysis of Data Remanence in a 90nm FPGA
A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision
A current-mode based field programmable analog array architecture for signal processing applications
A 1.4 MHz 0.21 mW MPEG-2/4 AAC single chip decoder
A 366kS/s 400uW 0.0013mm 2 frequency-to-digital converter based CMOS temperature sensor utilizing multiphase clock
High sensitivity silicon magnetic field detector
Lithography and design integration - New paradigm for the technology architecture development
A 0.7V time-based inductor for fully integrated low bandwidth filter applications
A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels
A wide-load-range single-inductor-dual-output boost regulator with minimized cross-regulation by constant-charge-auto-hopping (CCAH) control