yusuke1997/dblp-id-title huggingface dataset:
GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids
Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor
Combinational Decompressors with Nonlinear Codes
A Formal Framework for Modeling Smart Grid Applications: Demand Response Case Study
An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip
Generating CGRA Processing Element Hardware with CGRAgen
Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron
Fast Test Cost Calculation for Hybrid BIST in Digital Systems
DNAsim: Evaluation Framework for Digital Neuromorphic Architectures
Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs
Artificial Intelligence Enables Increased Data Rate of True Random Number Generator
Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits
Reflectance Calibration with Normalization Correction in Hyperspectral Imaging
Measuring trust in automated driving using a multi-level approach to human factors *
Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks
An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty
Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol
Distributed AI Systems at Scale: Reflections from DAIS
Multi Component Digital Circuit Optimization by Solving FSM Equations
Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching
Quantum Machine Learning Based on Minimizing Kronecker-Reed-Muller Forms and Grover Search Algorithm with Hybrid Oracles
Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level
Inter-Band Movement Compensation Method for Hyperspectral Images Based on Spectral Scanning Technology
Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems
High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic
FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design
Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU Tandem
Parameterized AES-Based Crypto Processor for FPGAs
Towards Spectral Pulse Oximetry Independent of Motion Artifacts
A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields
Efficient Test Pattern Compression Method Using Hard Fault Preferring
Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture
A New Algorithm for High-Speed Projection in Point Rendering Applications
An Improved Analysis of Reliability and Entropy for Delay PUFs
System Architecture and Security Issues of Smartphone-based Point-Of-Care Devices
POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications
GPU Based Implementation for the Pre-Processing of Radar-Based Human Activity Recognition
System Level Hardening by Computing with Matrices
Design of a Low-Power Digital Core for Passive UHF RFID Transponder
ANTAREX: A DSL-Based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing
A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages
Reliable Data Transmission over Simple Wireless Channels: A Case Study
Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm
Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions
Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems
Exploiting Emerging Reconfigurable Technologies for Secure Devices
Real-Time Independent Components Analysis for Dimensional Reduction of Hyperspectral Images Using Reconfigurable Hardware
Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip
IoT Components LifeCycle Based Security Analysis
A MPSoC Prototyping Platform for Flexible Radio Applications
An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems
Measurement Based Execution Time Analysis of GPGPU Programs via SE+GA
Studying the Degradation of Propagation Delay on FPGAs at the European XFEL
Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future
Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart
A Smart Floor Device of an Exergame Platform for Elderly Fall Prevention: *Note: Sub-titles are not captured in Xplore and should not be used
A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table
Resource Management for Mixed-Criticality Systems on Multi-core Platforms with Focus on Communication
On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects
Bounded transmission latency in real-time edge computing: a scheduling analysis
Toward a Hardware Man-in-the-Middle Attack on PCIe Bus for Smart Data Replay
Digital Nuclear Magnetic Resonance Acquisition Channel
A-DECA: An Automated Design Space Exploration Approach for Computing Architectures to Develop Efficient High-Performance Many-Core Processors
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
FPGA implementation of BIKE for quantum-resistant TLS
Reducing the Overhead of Real-Time Operating System through Reconfigurable Hardware
Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl
Image Processing Algorithms on Reconfigurable Architecture using HandelC
Test Controller Synthesis Constrained by Circuit Testability Analysis
Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization
Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications
Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors
A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance
Synthesis of Multivalued Logical Networks for FPGA Implementations
Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation
An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF
Real-Time Hyperspectral and Depth Fusion Calibration Method for Improved Reflectance Measures on Arbitrary Complex Surfaces
VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services
OPERA: A Low Power Approach to the Next Generation Cloud Infrastructures
An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS)
An FPGA Implementation of the ZUC Stream Cipher
Fast and Secure Finite Field Multipliers
A Threshold Logic Synthesis Tool for RTD Circuits
Virtual Devices for Hot-Pluggable Processors
RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing
Designing Robust Asynchronous Circuits Based on FinFET Technology
The CAPSARII Approach to Cyber-Secure Wearable, Ultra-Low-Power Networked Sensors for Soldier Health Monitoring
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability
FPGA Based Design of the Railway's Interlocking Equipments
Survey of Test Data Compression Technique Emphasizing Code Based Schemes
MATISSE: A Smart Hospital Ecosystem
NET4EXA: Pioneering the Future of Interconnects for Supercomputing and AI
Efficient Compression Technique for NoC-based Deep Neural Network Accelerators
Higher-Order Abstraction in Hardware Descriptions with C?aSH
High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic
A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical Applications
DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators
BDD Circuit Optimization for Path Delay Fault Testability
MULTI-modal Imaging of FOREnsic SciEnce Evidence: MULTI-FORESEE Project
A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes
Design and Physical Implementation of a Target ASIC for SET Experiments
An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip
Inter-Patient ECG Classification Using Deep Convolutional Neural Networks
Polymorphic RTL Computational Elements
On Power-Analysis Resistant Hardware Implementations of ECC-Based Cryptosystems
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity
The SafeCOP ECSEL Project: Safe Cooperating Cyber-Physical Systems Using Wireless Communication
Design of a Fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes
Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder
Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGA
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients
OpenSSL Bellcore's Protection Helps Fault Attack
Information and Communication Technology Research Opportunities in Dynamic Charging for Electric Vehicle
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations
Automata Construct with Genetic Algorithm
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach
A Modular Peripheral to Support Self-Reconfiguration in SoCs
Towards Machine Learning Support for Embedded System Tests
Menhir: Generic High-Speed FPGA Model-Checker
MVSTT: A Multi-Value Computation-in-Memory based on Spin-Transfer Torque Memories
Combining Languages in Embedded System Design
Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning
The Influence of Implementation Technology on Dependability Parameters
SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems
MPSoC FPGA Implementation of Algorithms of Machine Learning for Clinical Applications Using High-Level Design Methodology
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
The Essence of Reliability Estimation during Operational Life for Achieving High System Dependability
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series
A Lightweight Blockchain-based Technique for Anti-Tampering in Wireless Sensor Networks
Design and Implementation of an Efficient Fingerprint Features Extractor
Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices
A Scalable Monitoring Infrastructure for Self-Organizing Many-Core Architectures
Pipelined ALU for effective external memory access in FPGA
Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse
Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing Systems
Design of Efficient 1's Complement Modified Booth Multiplier
Glioblastoma Classification in Hyperspectral Images by Nonlinear Unmixing
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
Decomposition of transition systems into sets of synchronizing state machines
A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip
Impact of 3D IC on NoC Topologies: A Wire Delay Consideration
FPGA-based real-time monitoring support for CAN applications
Formal Verification of a DSP Chip Using an Iterative Approach
Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices
AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems
Automated Power Characterization for Run-Time Power Emulation of SoC Designs
Demonstrator Development of a Next-Generation Video Instrument for Earth Observation
Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods
Logic Minimization and Testability of 2SPP-P-Circuits
PipeEdge: Pipeline Parallelism for Large-Scale Model Inference on Heterogeneous Edge Devices
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs
Morphable Compression Architecture for Efficient Configuration in CGRAs
Assessing Processing Strategies on Data from Medical Hyperspectral Acquisition Systems
A System-on-Chip Implementation of the IEEE 802.11a MAC Layer
Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations
Strengthening Post-Quantum Security for Automotive Systems
Dynamic Detection and Mitigation of DMA Races in MPSoCs
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors
Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications
Instruction Folding Compression for Java Card Runtime Environment
Hierarchical Modeling and Verification of Embedded Systems
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy
Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation Scheme
Investigating Novel 3D Modular Schemes for Large Array Topologies: Power Modeling and Prototype Feasibility
An Active Implant to Restore Dental Proprioceptivity
Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops
Energy Consumption Modeling of H.264/AVC Video Decoding for GPP and DSP
IEEE 802.11p Receiver Design for Software Defined Radio Platforms
Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors
ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs
A Faster Shift Register Alternative to Filter Generators
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs
Power Estimation of Time Variant SoCs with TAPES
Accuracy Improvement of Dataflow Analysis for Cyclic Stream Processing Applications Scheduled by Static Priority Preemptive Schedulers
A Low Latency and Energy Efficient Communication Architecture for Heterogeneous Long-Short Range Communication
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures
The Human Brain Project: High Performance Computing for Brain Cells Hw/Sw Simulation and Understanding
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates
Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation
IP-Block Based Integration of Very High Performance WLAN Modem
Practical Aspects of Logic Synthesis Based on Functional Decomposition
Adversarial Analysis and Supervisory Control of Sensor Networks
Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical Systems
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
Embedded object detection applying Deep Neural Networks in railway domain
The AFarCloud ECSEL Project
Secure Data Acquisition for Battery Management Systems
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
Hardware Acceleration of k-Mer Clustering using Locality-Sensitive Hashing
Diminished-1 Modulo 2 n + 1 Squarer Design
Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip
Embedded Real-Time Fall Detection with Deep Learning on Wearable Devices
Robustness Check for Multiple Faults Using Formal Techniques
Error-Aware Design
A Sketch-Based Algorithm for Network-Flow Entropy Estimation on Programmable Switches Using P4
Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design
Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection
DEWI - Wirelessly into the Future
Two-Phase Interarrival Time Prediction for Runtime Resource Management
UML-Based Modeling and Simulation of Environmental Effects in Networked Embedded Systems
On the Benefits of Multicores for Real-Time Systems
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement
Automatic State Space Analysis for Modeling Untrusted Embedded Device Drivers
A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines
Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded Systems
Architecture of a Public Transport Supervision System Using Hybridization Models Based on Real and Predictive Data
Temperature and Leakage Aware Power Control for Embedded Streaming Applications
Combined Compression of Multiple Correlated Data Streams for Online-Diagnosis Systems
Lightweight Software Encryption for Embedded Processors
Optimizing HQC using Frobenius Additive FFT on a RISC-V-based System-on-Chip
Message from the Program Chairs: DSD 2022
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies
FPGA-based Road Traffic Videodetector
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms
Consumer-Centric and Service-Oriented Architecture for the Envisioned Energy Internet
Attention-based Skin Cancer Classification Through Hyperspectral Imaging
FPGA-Accelerated Early-Exit Neural Decoder for Quantum Error Correction
The Case for a Balanced Decomposition Process
An Attention-Based Parallel Algorithm for Hyperspectral Skin Cancer Classification on Low-Power GPUs
An Elliptic Curve Crypto-Processor Secured by Randomized Windows
Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical Monitoring
VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers
Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System
Dependable Controller Design Using Polymorphic Counters
SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs
Utilizing Prefetch Buffers for Iterative Graph Applications
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology
Security & Trusted Devices in the Context of Internet of Things (IoT)
Secured Miniaturized System-in-Package Contactless and Passive Authentication Devices Featuring NFC
Evaluation of Fault-Tolerant Routing Methods for NoC Architectures
Formal Property Verification for Early Discovery of Functional Flaws in Digital Designs: A Designer's Guide
Execution Time and Code Size Optimization Using Multidimensional Retiming and Loop Striping
Timing Prediction for Service-Based Applications Mapped on Linux-Based Multi-core Platforms
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors
Verification of Calculations of Non-Homogeneous Markov Chains Using Monte Carlo Simulation
A Module for Packet Hijacking in NetFPGA Platform
Biconditional-BDD Ordering for Autosymmetric Functions
Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling
Multi-channel Raw-Data Acquisition for Ultrasound Research
An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip
Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores
Access Interval Prediction with Neural Networks for Tightly Coupled Memory Systems
Compiler-Directed Management of Instruction Accesses
No Principal Too Small: Memory Access Control for Fine-Grained Protection Domains
RISC-V Core with Approximate Multiplier for Error-Tolerant Applications
A Petite and Power Saving Design for the AES S-Box
Reconfigurable Randomized K-way Graph Partitioning
Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain
Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios
Evaluation of Transient Fault Susceptibility in Microprocessor Systems
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis
Exploiting Inter and Intra Application Dynamism to Save Energy
MacSim: A MAC-Enabled High-Performance Low-Power SIMD Architecture
Fault Tolerant Deadlock-Free Adaptive Routing Algorithms for Hexagonal Networks-on-Chip
Optimizing Data Compression: Enhanced Golomb-Rice Encoding with Parallel Decoding Strategies for TinyML Models
High Performance and Energy Efficient AMD and BWAD Pooling Schemes Characterised for CNN Accelerators
Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems
SecUp: Secure and Efficient Wireless Software Updates for Vehicles
A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor
Exploring ISS Abstractions for Embedded Software Design
A Flexible and Lightweight ECC-Based Authentication Solution for Resource Constrained Systems
Boolean Minimizer FC-Min: Coverage Finding Process
Enhanced Spin-Diode Synthesis Using Logic Sharing
What to Adapt in a High-Performance Microprocessor
2-SPP Approximate Synthesis for Error Tolerant Applications
A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems
Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs
Exploring Storage Organization in ASIP Synthesis
Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance
Dynamic Control Flow Checking Technique for Reliable Microprocessors
A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-Codesign
A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA
Reducing Leakage through Filter Cache
A Computation and Power Reduction Technique for H.264 Intra Prediction
Model-Based Function Mapping and Bandwidth Reservation for Mixed-Critical Adaptive Systems
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
Achieving High Throughput with a Trainable Neural-Network-Based Equalizer for Communications on FPGA
Modular Fault Injector for Multiple Fault Dependability and Security Evaluations
Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers
A resource optimized Processor Core for FPGA based SoCs
Monitoring Framework to Support Mixed-Criticality Applications on Multicore Platforms
A Novel Architecture of Implementing Error Detecting AES Using PRNS
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration
Massively Parallel Hardware Architecture for Genetic Algorithms
Implementation Study of FFT on Multi-lane Vector Processors
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels
Energy Behaviour of NUCA Caches in CMPs
VADAR: A Vision-based Anomaly Detection Algorithm for Railroads
The European H2020 project VESSEDIA (Verification Engineering of Safety and SEcurity critical Dynamic Industrial Applications)
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations
An Effective Framework for Enabling the Reuse of External Soft IP
Evaluation of Temporal Formulas Based on "Checking by Spheres"
On the Fundamental Design Gap in Terabit per Second Packet Switching