yusuke1997/dblp-id-title huggingface dataset:
Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET
Design of square generator with small look-up table
HTS DC power transmission analysis
An efficient ODT calibration scheme for improved signal integrity in memory interface
Success rate model for fully AES-128 in correlation power analysis
The VLSI Architecture Design of a Configurable and High-Throughput Singular Value Decomposition Processor
Linear array processors with multiple access modes memory for real-time image processing
Live demonstration: Signal flow platform implementation into retinal cell pathway
Fully-differential low-offset interface for capacitive sensors
A hardware-efficient color segmentation algorithm for face detection
A 7.6-nW 1-kS/s 10-bit SAR ADC for Biomedical Applications
Microsensor characterization in an integrated blood gas measurement system
Image Registration using Fractional Fourier Transform
Real-Time Image Stabilization for Digital Video Cameras
Space Vector PWM for PMSM simulation using Matlab Simulink
A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators
A new iterative reconstruction scheme for signal reconstruction
Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain Scheduling
Using ANN To Predict The Best HUB Location
Fast locking and high accurate current matching phase-locked loop
Passive RF Resonant Receiver with Voltage Gain for Wireless Power Transfer System
VoIP frame bundling for WiMAX downlink
Implementation of Gabor filter to texture analysis of radiographs in the assessment of osteoporosis
Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain Equalization
A new algorithm of adaptive IIR notch filter for the detection of sinusoids
A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction
Benchmark of RRAM based Architectures for Dot-Product Computation
Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation
A Quick Scene Search with Constructed Mapped Charts for TV Sport Programs
Design of Arbitrary FIR Digital Filters with Group Delay Constraint
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC
Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links
Spatially-modulated space-time coding in visible light communications using 2×2 LED array
Parallelisation of Digital Signal Processing in Uniform and Reconfigurable Filter Banks for Satellite Communications
HW/SW co-simulation platforms for VLSI design
40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications
Distance dependent thresholding search for fast motion estimation in real world video coding application
High-Speed Random Number Generator Design in 22nm FD-SOI Process
A New High Multiplication Factor Tunable Grounded Positive and Negative Capacitance Simulator
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
A high conversion gain, low noise figure RF-CMOS receiver front-end IC for 2.4-GHz applications
Live Demonstration: AI-Based Arrhythmia Detection with Wearable ECG and Cloud Platform for Dog Health Monitoring
Design of a Wireless Power Supply Receiver for Biomedical Applications
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs
Design of ESD protection for RF CMOS power amplifier with inductor in matching network
Noise-resistant feature extraction using 2D techniques
Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters
Digital clock data recovery circuit fot S/PDIF
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC
Bit-plane watermarking for zerotree-coded images
Development of an artificial neural network system for sulphate-reducing bacteria detection by using model-based design technique
Parallel Discovery of Transcription Factor Binding Sites
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules
A Novel Standard Cell Layout Methodology for Low Power IOT Applications
An Error Amplifier With Enhanced Slew Rate and Clamp Function Supporting Multi-Mode Control of Four-Switch-Buck-Boost Converter
A Lightweight AEAD encryption core to secure IoT applications
A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process
A Micropower CMOS Amplifier for Portable Surface EMG Recording
Low power chopper amplifier without LPF
A 2.5D mm-size Wafer-level CMOS-IPD Wireless Power Transfer Receiver Using Cross-coupled and Self-biasing Topology for Implantable Biomedical System
An integrative algorithm for predicting protein coding regions
Genetical tuning of a capacitorless current-mode bandpass biquad based on single-stage CMOS OTA
An LVQ-based technique for human motion segmentation
PCA/ICA-based SVM for fall recognition using MEMS motion sensing data
An Active-Copper-Cable with Continuous-Time-Linear-Equalizer IC for 30-AWG 7-meters Reach Interconnect of 400-Gbit/s QSFP-DD
Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aids
Embedded implementation of acoustic field enhancement for stereo headphones
Construction of short-length LDPC codes with low error floor
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process
Enhancing Physical Unclonable Function Robustness Employing Embedded Instruments
High-speed mixed-signal SoC design for basestation application
VLSI implementation of belief-propagation-based stereo matching with linear-model message update
A Display Order Oriented Scalable Video Decoder
A High Frequency Circuit Model for Current Transformer Based on the Scattering Parameter
A Novel 15T-4MTJ based Non-volatile Ternary Content-Addressable Memory Cell for High-Speed, Low-Power and High-Reliable Search Operation
Miniaturized Laser Diode Driver and Microwave Source for Transportable Quantum Sensors
Low-complexity rotators for the FFT using base-3 signed stages
An Optimization Problem on Two-Partition of Jobs for Profit Allocation
Efficient Polynomial Arithmetic and Hash Modules for ML-DSA and ML-KEM Standards
Active noise cancellation using recurrent radial basis function neural networks
The application of ultrasonic transducer in bacteria growth monitoring system
Design of Stable Error-Correction Ramp Generators Considering Process and Run-Time Variations
Video stabilization with local rotational motion model
Locating observers and controllers for severely disturbed power system using mode matrices
Fuzzy-ART based digital watermarking scheme
Performance Analysis of the Deficient Length EDS Adaptive Algorithm
Optimal power allocation for channel estimation in MIMO-OFCDM systems
In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection
A High-Speed Baugh-Wooley Multiplier Design Using Skew-Tolerant Domino Techniques
Live demonstration: A 3D die-level integration platform
Performance optimization for the CMOS voltage reference circuit based on NSGA-II
A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS
On-line Thai-English handwritten character recognition using distinctive features
Method for Measuring Silicon Quantum Dots with TMR Sensor
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory
A Fully Integrated Chopper IA for Implantable Multichannel EEG Recording Without Impedance Boosting Circuits
Sub-Volt Bulk-Driven Transconductance Amplifier and Filter Application
Low-noise amplifier path for ultrasound system applications
A cryogenic D/A converter with novel charge injection reduction technique for silicon quantum computer controller circuit
Parallel implementation of morphological processing by arbitrary kernels on Cell/BE with OpenCV interface
An implantable microsystem for studying the Parkinson's Disease
IC implementation of spike-timing-dependent synaptic plasticity model using low capacitance value
Error recovery for MPEG-4 shape and texture information
Motion estimation based on iterative color matching and structure matching
2-V 3.36-mW 2.5-GHz fourth-order inductorless CMOS RF bandpass filter
Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip
A fully digital green LDO regulator dedicated for biomedical implant using a power-aware binary switching technique
The heterogeneous sensor system on chip
RC-SCR: a novel low-voltage ESD protection circuit with new triggering mechanism
Single inductor DC-DC converter with bipolar outputs using charge pump
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology
Fast-Gaussian SIFT and its hardware architecture for keypoint detection
B*-tree based variability-aware floorplanning
Blind Subband Beamforming for Speech Enhancement of Multiple Speakers
A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology
Low power level shifter and combined with logic gates
A Hybrid Voltage-Time Dual-Slope Capacitance-to-Digital Converter With Noise Shaping for Extracellular Vesicle Sensing Systems
Comprehensive power analysis and efficiency optimum design for step-up DC-DC converters
A Novel Neural Network GA-Optimized Controller for QoS Support in Wireless MACs
Signature Verification using Velocity-based Directional Filter Bank
2020 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2020, Ha Long, Vietnam, December 8-10, 2020
An efficiency-enhanced CMOS voltage regulator module for bio-electronic implants
Low-power and Small-area Transimpedance Amplifier with Active Inductor in 65 nm CMOS
High-speed and low power unified dual-field multiplier in GF (P) and GF (2 m )
Morphological Residue Encoding and Piecewise Approximation Techniques for Lossless Binary Image Compression
Radial Basis Function Based Surrogate-Assisted Metaheuristic Approach for Variability Analysis
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing
A New Efficient Approach for Removal of Impulse Noise for Color Images
A Current-Mode Electrical Stimulator with Charge Balance for Neural Stimulation Applications
Modified Gm-Free Assisted Opamp Technique in Continuous Time Delta Sigma Modulators
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications
Hardware realization of novel pulsed neural networks based on delta-sigma modulation with GHA learning rule
Analog MOS circuit design for reconfigurable fuzzy logic controller
Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation
A 0.18µm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN Receivers
Space-time multiuser detection with alternating soft interference cancellation in highly loaded CDMA systems
Scan-based attack against DES cryptosystems using scan signatures
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning]
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016
Radiation-hardened Configuration Registers with SPI Interface Protocol in a 65nm CMOS Technology
An IDD receiver of LDPC coded modulation scheme for flash memory applications
Real-time simulation of large-scale dynamic forest with GPU
A New Linearity Enhancing Technique for Low Noise Amplifiers
Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing
A systematic network-on-chip traffic modeling and generation methodology
Quantized Optical Neural Network Based on Microring Resonators with On-Chip Modulation
Particle swarm optimization for matrix converter of switching pattern design
An Accurate and Time-Efficient Subtractor by Cross Format Coding in Stochastic Computing
Analog Implementation of Reconfigurable Convolutional Neural Network Kernels
A study on parallel transmission wireless visible light communications using color shift keying
A 4GHz direct digital frequency synthesizer utilizing a nonlinear sine-weighted DAC in 90nm CMOS
A novel versatile circuit functioning as both filter and oscillator based on CCCCTAs
DTCWT-based dynamic texture features for visual speech recognition
A 6.5-GHz LC VCO with Integrated-Transformer Tuning
Low-power ASK receiver circuit for wireless communication system
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]
Two new methods to design digital filters
An 80-GHz Phase-Locked Loop for MillimeterWave Application in 40-nm CMOS
Power system stability enhancement with an integrated offshore wind farm and marine-current farm using a STATCOM
A Background Timing Skew Calibration Technique in Time-Interleaved ADCs With Second Order Compensation
A CMOS low-dropout regulator with 3.3 μA quiescent current independent of off-chip capacitor
Design of monolithic silicon-based envelope-tracking power amplifiers for broadband wireless applications
Robust solution for synchronous communication among multi clock domains
Blocking probability of the reverse link cellular CDMA system
A 10-MS/s Binary Weight-merged SAR ADC for Real-Time Health-Monitoring System Applications
Short response Hilbert transform for edge detection
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations
An exploration of usable authentication mechanisms for virtual reality systems
A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT
Iterative Symbol-by-symbol Decision Feedback Detection for MIMO-ISI Channels
Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors
Weighted least squares design of wideband digital integrator using interlaced sampling method
De Bruijn graph-based communication modeling for fault tolerance in smart grids
A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding
The Light-Weighted Road Fault Identification for Embedded Hardware Platform Using YOLO
Adaptive partition size temporal error concealment for H.264
Li-ion battery management chip for multi-cell battery pack
Consumption of processing performance in face recognition on working memory
A low-power LDO circuit with a fast load regulation
Low-cost prototype design of a portable ECG signal recorder
Three-level AND-OR-XOR network synthesis: A GA based approach
Design of a mobile telemedicine system with wireless LAN
Voltage controlled memristor threshold logic gates
H.264/AVC hardware encoders and low-power features
Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module
A Portable Electrical Stimulation System with User Interface for Multiple tVNS Treatment
2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018
A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer
An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction Based on Repeated Utilization of Identical PRSC Sequences in Time Domain
Priority-Based Normalized Partial Distortion Search Algorithm for Fast Motion Estimation
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit
The parallel algorithm implementation of matrix multiplication based on ESCA
Optical Front-Ends for Low-Cost Laser-Based 10-Mbps Free-Space Optical Transceiver
An all-digital de-skew clock generator for arbitrary wide range delay
Low-power circuit structures for chip-scale stimulating implants
SD-PUF: An Area Efficient PUF Design with Signature Improvement for Spintronic Circuits
Oscillation-based Test Method for Continuous-time OTA-C Filters
Microelectronic channel bridge and signal regeneration of injured spinal cords
Fuzzy-based Active and Reactive Control for Brushless Doubly-fed Wind Power Generation System
Least-squares design of IIR all-pass filters using closed-form Toeplitz-plus-Hankel matrix
Reconfigurable Logic Element using a Chaotic Circuit
Transformer based front-end for a low power 2.4 GHz transceiver
Analog-to-Digital Converter with energy recovery capability using adiabatic technique
Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS
Switching synchronization states of a ring of coupled chaotic circuits with one-direction delay effects
Thermometer Code of Log Mel-Frequency Spectral Coefficient for BNN-based Keyword Spotting System
Stereo Point Cloud Refinement for 3D Object Detection
An Optimized Scheme of Energy Consumption in Wireless Sensor MAC Protocol
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding
Design Partitioning for Reducing Crosstalk Analysis Time
100-Mbps transceiver for enhanced MIL-STD-1553
Reinforcement Learning Based Prefetch-Control Mechanism
New algorithm for signed integer comparison in four-moduli superset {2 n , 2 n -1, 2 n +1, 2 n+1 -1}
A fast and precise circuit simulation method for switching power converters using a mixture of circuits and behavioral models
Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks
GF(2 m ) multiplier using Polynomial Residue Number System
A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization
A Multi-Channel 1.52 µVrms Front End with Orthogonal Frequency Chopping for Neural Recording Applications
CEERP: Cost-based Energy-Efficient Routing Protocol in wireless sensor networks
The transformer coupled mm-Wave CMOS Power Amplifier
On the approximation errors in the frequency test included in the NIST SP800-22 statistical test suite
Another Look at the Sequential Multiplier over Normal Bases
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture
Low-Noise Amplifier with Wideband Feedforward Linearisation for Mid-Band 5G Receivers
Phase-controlled system design via mixed H∞ synthesis and nonlinear method
A 0.65-V 10-bit 320-kS/s SAR-ADC with Charge Average and Skip Switching Algorithm
An Energy Operating System Adaptive for The Sustainable And Green Energy
A Tunable Ultra-Wideband Pulse Generator Using a Variable Edge-Rate Signal
Efficient implementation of real filter banks using frequency response masking techniques
A content-aware packets priority ordering and marking scheme for H.264 video over diffserv network
Missing Temperature Data Recovery Methods Based on Smoothness, Bandlimitedness and Sparseness Priors
Implementation of highly accurate NMOS Vt based clamping technique in low current comparator
Leakage Optimized DECAP Design for FPGAs
Design of Diode-Connected and Cross-Connected CMOS Rectifiers with Adaptive Tuning for RF Energy Harvesting
Design of Delta Operator Based 2-D IIR Filters Using Symmetrical Decomposition
Theory, Lattice Structure and Design of Unequal Length Linear Phase Perfect Reconstruction Filter Banks with More Flexible Length Profile
Asynchronous multi-channel ADC and DSP processor interface
Design of a Dynamic PCM Selector for Non-deterministic Environment
A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur
An Intelligent CMOS Image Sensor System Using Edge Information for Image Classification
A variable-gain single-bit ultra-wideband quantizer for baseband receiver front-end
A Real-Time Digital Baseband Channel Emulation System for OFDM Communications
Noise activity detection based on 4th order cumulant for impact noise
Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits
A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system
A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS
NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism
Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit
Testing techniques for resistive-open defects in future CMOS technologies
Optimal state-space controller for power switching converter
A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter
Current-mode analog CMOS Fuzzy Logic Controller
A compact, resource sharing on-chip soft-start technique for automotive DC-DC converters
Flattening Power Waveforms by Hamming Distance Converter for Side-channel Attacks
Scan-based side-channel attack on Camellia cipher using scan signatures
Live demonstration: FPGA based 3840×2160 video decoding and displaying system
A power-gating scheme for CAL circuits using single-phase power-clock
Design of Interconnected Bus for Low Power Based on Boolean Process
A CMOS Synthesizer using a new scheme of injection locking of VCOs
Drawing on the benefits of RFID and bluetooth technologies
V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
Signal-to-noise ratio improvement of common-gate CMOS LNA for Ultra-Wide-Band
An 8-Channel TDM Spectral Feature Extraction for Neuromodulation SoC
Analysis and Measurement of Cross Modulation Distortion in WCDMA Receivers
Characteristic analysis and tolerance analysis of nonlinear resistive circuits using integer programming
A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller
Uncertainty Management for Estimation in Dynamical Systems
High-efficiency and cost-sharing architecture design of fast algorithm based multiple 4×4 and 8×8 forward transforms for multi-standard video encoder
Chaotic Sampling of Double Scroll Chaos for Digital Random Number Generation
An EM-Based Joint Channel Estimation and Data Detection for SIMO Systems
FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic
A small die area and high linearity 10-bit capacitive three-level DAC
Improving the design of parallel-pipeline cyclic decoders towards fault-secure versions
A 32-bit Two-step Incremental-ADC with 125.6 dB Dynamic-range for Non-invasive BCI Applications
Calibration method for improving the linearity of analog-to-digital converters in CMOS image sensor
Bitwise Logical Operations in VCMA-MRAM
Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis
Redundant Adders Consume Less Energy
±1.5V high performance CMOS rail to rail voltage follower
Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic
Stepped Triangular CIC Filter for Rational Sample Rate Conversion
Non-Data Aided SBIB Receiver
Study of mobile farmland information monitoring terminal based wireless data transmission technology
A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation
Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor
Enhanced channel selection using digital low-IF in Weaver receiver architecture
Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response
A Nanopower 4 th -Order Chebyshev Lowpass Filter For ECG Detection System
$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability
Blind Determination of the Signal to Noise Ratio of Speech Signals Based on Estimation Combination of Multiple Features
Mitigation of GPS multipath error using recursive least squares adaptive filtering
Fingerprint pixel sensor array on a display
A novel coefficient automatic calculation method for sinc filter in sigma-delta ADCs
Live demonstration: An ECG-on-Chip for wearable wireless sensors
A neuromorphic microsystem on glass for monitoring fly behaviours automatically
Text information acquisition method of traffic signs for autonomous navigation
Temporal prediction improvement for parallel processing of HEVC
New parallel MDC FFT processor with efiicient scheduling scheme
Chua's Table as a Tool for Constructing Dual Networks
An efficient architecture for HWT using sparse matrix factorisation and DA principles
A Branch-and-Bound Algorithm with Reduced Search Space for Sparse Filter Design
Reversibly sharing and hiding secret using expansion strategy
A Monolithic Boost Converter with an Adaptable Current-Limited PFM Scheme
An efficient distortion model configuration for depth coding in 3D-HEVC