yusuke1997/dblp-id-title huggingface dataset:
Crossbar based design schemes for switch boxes and programmable interconnection networks
An O ( mn ) time algorithm for optimal buffer insertion of nets with m sinks
ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms
Overlapping Aware Zone Allocation for LSM Tree-Based Store on ZNS SSDs
A metric for analyzing effective on-chip inductive coupling
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling
High performance current-mode differential logic
Metacore: A Configurable and Instruction Level Extensible DSP Core
The Power of Computation-in-Memory Based on Memristive Devices
TED+: a data structure for microprocessor verification
Event Delivery using Prediction for Faster Parallel SystemC Simulation
Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction
Design and In-training Optimization of Binary Search ADC for Flexible Classifiers
BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems
Power reduction by simultaneous voltage scaling and gate sizing
Task assignment and scheduling in MPSoC under process variation: A stochastic approach
AIPlace: Analog IC Placement with Multi-Task Learning Framework
Modeling SystemC design in UML and automatic code generation
Static IR Drop Prediction with Limited Data from Real Designs
Clock network minimization methodology based on incremental placement
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design
Lamina: Low Overhead Wear Leveling for NVM with Bounded Tail
Motion Adaptive Image Sensor
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure
A Novel Technology Mapper for Complex Universal Gates
Handling dynamic frequency changes in statically scheduled cycle-accurate simulation
A nonvolatile flip-flop-enabled cryptographic wireless authentication tag with per-query key update and power-glitch attack countermeasures
Managing verification error traces with bounded model debugging
Automotive electronics: steady growth for years to come!
Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment
CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures
High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6µm TLM CMOS Technology
Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
Charge replacement in hybrid electrical energy storage systems
Robust Hyperdimensional Computing against Cyber Attacks and Hardware Errors: A Survey
Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity
A pipelined ADC macro design for multiple applications
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models
A low-cost cryptographic processor for security embedded system
Microarchitectural-level statistical timing models for near-threshold circuit design
Template-based memory access engine for accelerators in SoCs
Processor-programmable memory BIST for bus-connected embedded memories
An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor
Powering the IoT: Storage-less and converter-less energy harvesting
Architectures and algorithms for user customization of CNNs
Human++: Wireless autonomous sensor technology for body area networks
Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores
Mixed-Traffic Intersection Management Utilizing Connected and Autonomous Vehicles as Traffic Regulators
Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs
Automatic formal verification of clock domain crossing signals
AdaSens: Adaptive Environment Monitoring by Coordinating Intermittently-Powered Sensors
Large-scale fixed-outline floorplanning design using convex optimization techniques
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
Clustering of flip-flops for useful-skew clock tree synthesis
A high stability, low supply voltage and low standby power six-transistor CMOS SRAM
The world's 1st Complete-4K SoC solution with hybrid memory system
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
Facilitating the Efficiency of Secure File Data and Metadata Deletion on SMR-based Ext4 File System
A mutual auditing framework to protect IoT against hardware Trojans
Smart electrode - toward a retinal stimulator with the large number of electrodes
FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
Design and analysis for ThruChip design for manufacturing (DFM)
S 3 DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity
Register binding and port assignment for multiplexer optimization
Fast development of source-level debugging system using hardware emulation (short paper)
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection
Accelerated Capacitance Simulation of 3-D Structures with Considerable Amounts of General Floating Metals
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007
Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models
On handling arbitrary rectilinear shape constraint
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors
Data memory minimization by sharing large size buffers
Scalable frequent-pattern mining on nonvolatile memories
Dynamic reusability-based replication with network address mapping in CMPs
Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan
FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization
The road to 3D EDA tool readiness
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications
A delay-optimized universal FPGA routing architecture
Safety-Driven Interactive Planning for Neural Network-Based Lane Changing
Thermal-aware power network design for IR drop reduction in 3D ICs
Variability-driven module selection with joint design time optimization and post-silicon tuning
Efficient simulation-based optimization of power grid with on-chip voltage regulator
Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge Platforms
Static timing analysis for ring oscillators
Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators
Model checking on state transition diagram
Design of a pre-scheduled data bus for advanced encryption standard encrypted system-on-chips
Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks
Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern
Efficient reliability management in SoCs - an approximate DRAM perspective
Universal Switched-Current Integrator Blocks for SI Filter Design
An adaptively biased low-dropout regulator with transient enhancement
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness
A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators
Enhanced symbolic simulation for efficient verification of embedded array systems
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation
Issues on SOC testing in DSM area: embedded tutorial
On-chip accumulated jitter measurement for phase-locked loops
Vulnerability analysis for crypto devices against probing attack
Compression-aware capture power reduction for at-speed testing
Hardware verification using ANSI-C programs as a reference
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology
Toward mobile phone Linux
An integer programming placement approach to FPGA clock power reduction
Ultra-low voltage power management circuit and computation methodology for energy harvesting applications
Compact modeling of microbatteries using behavioral linearization and model-order reduction
Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks
Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method
HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation
On the minimization of SOPs for bi-decomposition functions
Automatic generation of bus functional models from transaction level models
Synthesis and analysis of an industrial embedded microcontroller
Micro-architectural Cache Side-Channel Attacks and Countermeasures
A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit
Modeling and analysis of integrated spiral inductors for RF system-in-package
CNN-based object detection solutions for embedded heterogeneous multicore SoCs
Streaming Accuracy: Characterizing Early Termination in Stochastic Computing
Gate-level aged timing simulation methodology for hot-carrier reliability assurance
Implicit intermittent fault detection in distributed systems
Silicon photonics technology platform for embedded and integrated optical interconnect systems
KVFTL: Optimization of storage space utilization for key-value-specific flash storage devices
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream
Full-chip thermal analysis for the early design stage via generalized integral transforms
Improved algorithms for hypergraph bipartitioning
LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space Optimization
A digital audio signal processor for cellular phone application
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting
Clock design of 300MHz 128-bit 2-way superscalar microprocessor
Physical CAD changes to incorporate design for lithography and manufacturability
An Efficient Branch-and-Bound Routing Algorithm for Optical NoCs
Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems
An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluation
Design and implementation of an SDH high-speed switch
Using C based logic synthesis to bridge the productivity gap
Post-routing redundant via insertion for yield/reliability improvement
A fast congestion estimator for routing with bounded detours
Wave-pipelined on-chip global interconnect
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation
Reevaluating the latency claims of 3D stacked memories
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs
Timing driven track routing considering coupling capacitance
Techniques for low power realization for FIR filters
High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence system
Low-Power High-Speed 180-nm CMOS Clock Drivers
Analog circuit verification by statistical model checking
Post-layout transistor sizing for power reduction in cell-based design
A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling
Robust fixed-outline floorplanning through evolutionary search
An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators
On reliability hardening in cyber-physical digital-microfluidic biochips
A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications
Design space exploration for minimizing multi-project wafer production cost
A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers
Multiplierless Design of High-Speed Very Large Constant Multiplications
Exploiting Quantum Teleportation in Quantum Circuit Mapping
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models
W-band ultra-high data-rate 65nm CMOS wireless transceiver
A gradual scheduling framework for problem size reduction and cross basic block parallelism exploitation in high-level synthesis
Embedded tutorial I: design for manufacturability
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times
Regularity-oriented analog placement with diffusion sharing and well island generation
Accelerator for LLM-Enhanced GNN with Product Quantization and Unified Indexing
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design
A figure of merit for assertions in verification
$\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal Latency
Frequency Selective Model Order Reduction via Spectral Zero Projection
PhotonGraph: High-performance Photonic Graph Processing Accelerator
Normally-off technologies for healthcare appliance
Multi-level droplet routing in active-matrix based digital-microfluidic biochips
Rethinking self-balancing binary search tree over phase change memory with write asymmetry
Energy-aware mapping for tile-based NoC architectures under performance constraints
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design
Secco: Codesign for Resource Sharing in Regular-Expression Accelerators
Java TM in electronic design automation
An entropy measure for power estimation of Boolean functions
Design and implementation of a secret key steganographic micro-architecture employing FPGA
Ordered escape routing based on Boolean satisfiability
Mixed-Type Wafer Failure Pattern Recognition
Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model
A 300-pW audio ΑΣ modulator with 100.5-dB DR using dynamic bias inverter
DISS: A Novel Data Invalidation Scheme for Swap-Data on Flash Storage Systems
Composing real-time applications from communicating black-box components
Dynamic power estimation for deep submicron circuits with process variation
APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction
1-cc computer using UWB-IR for wireless sensor network
Evaluation of runtime monitoring methods for real-time event streams
A stochastic local hot spot alerting technique
A smart imager for the vision processing front-END
Hardware Trojan detection using exhaustive testing of k-bit subspaces
TAD: time side-channel attack defense of obfuscated source code
On Designing Computing Systems for Autonomous Vehicles: a PerceptIn Case Study
A probabilistic analysis of pipelined global interconnect under process variations
Optimal redistribution of white space for wire length minimization
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment
Delta-sigma modulator based mixed-signal BIST architecture for SoC
Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning
Transistor reordering rules for power reduction in CMOS gates
Security analysis of Anti-SAT
STACCATO: disjoint support decompositions from BDDs through symbolic kernels
Polysynchronous stochastic circuits
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation
Power minimization for dynamic PLAs
embedded system design with multiple languages: embedded tutorial
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective
Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998
Automated debugging of missing assumptions
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture
Memory size computation for multimedia processing applications
Using positive equality to prove liveness for pipelined microprocessors
Sequence-pair-based placement and routing for flow-based microfluidic biochips
An accurate 1.08-GHz CMOS LC voltage-controlled oscillator
A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Embedded tutorial: subwavelength lithography
A new compilation technique for SIMD code generation across basic block boundaries
ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section
Multi-Wavelength Parallel Training and Quantization-Aware Tuning for WDM-Based Optical Convolutional Neural Networks Considering Wavelength-Relative Deviations
Compact nonlinear thermal modeling of packaged integrated systems
Hybrid Detour Refinement Strategy for Package Substrate Routing
A fast SPFD-based rewiring technique
Homogeneous integration for 3D IC with TSV
SRAF insertion via supervised dictionary learning
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
A Programmable Fully-Integrated GPS receiver in 0.18µm CMOS with Test Circuits
AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems
A low-voltage CMOS electrophoresis IC using electroless gold plating for small-form-factor biomolecule manipulation
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays
A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints
A hardware-oriented design for weighted median filters
Design of digital neural cell scheduler for intelligent IB-ATM switch
Network flow based cut redistribution and insertion for advanced 1D layout design
Reviving erroneous stability-based clock-gating using partial Max-SAT
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)
Timing analysis considering temporal supply voltage fluctuation
ScanPUF: Robust ultralow-overhead PUF using scan chain
Performance and reliability driven clock scheduling of sequential logic circuits
Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks
Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips
Fast statistical analysis of rare failure events for memory circuits in high-dimensional variation space
A new layout synthesis for leaf cell design
Biological information sensing technologies for medical, health care, and wellness applications
PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators
Synthesis of reversible circuits with minimal lines for large functions
Statistical timing verification for transparently latched circuits through structural graph traversal
Energy-aware computation duplication for improving reliability in embedded chip multiprocessors
Timing Optimization of Logic Network Using Gate Duplication
Analog circuit simulation using range arithmetics
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks
Legal protection for semiconductor Intellectual Property (IP)
An adaptive LU factorization algorithm for parallel circuit simulation
Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics
Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications
Feature extraction from design documents to enable rule learning for improving assertion coverage
Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM
LTCC spiral inductor modeling, synthesis, and optimization
On error modeling of electrical bugs for post-silicon timing validation
DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
Resiliency for many-core system on a chip
Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures
Realtime wavelet video coder based on reduced memory accessing
An approach to anchoring and placing high performance custom digital designs
Low-power domino circuits using NMOS pull-up on off-critical paths
A Timing-Driven Block Placer Based on Sequence Pair Model
Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles
A cycle accurate power estimation tool
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications
Energy-Aware Design Methodology for Myocardial Infarction Detection on Low-Power Wearable Devices
Deeper Bound in BMC by Combining Constant Propagation and Abstraction
A Wideband CMOS LC-VCO Using Variable Inductor
SOC for car navigation system with a 55.3GOPS image recognition engine
A three-layer over-cell multi-channel routing method for a new cell model
VISA synthesis: Variation-aware Instruction Set Architecture synthesis
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms
On potential design impacts of electromigration awareness
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
Body bias clustering for low test-cost post-silicon tuning
A dynamic element matching circuit for multi-bit delta-sigma modulators