yusuke1997/dblp-id-title huggingface dataset:
Fingerprinting intellectual property using constraint-addition
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Functional simulation and fault diagnosis
Performance Specification Using Attributed Grammars
Reliable communication in systems on chips
Late Breaking Results: TriSC: Low-Cost Design of Trigonometric Functions with Quasi Stochastic Computing
SRA: a secure ReRAM-based DNN accelerator
Digital Filter Synthesis Based on Minimal Signed Digit Representation
FlexiBuffer: reducing leakage power in on-chip network routers
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints
Performance bound analysis of analog circuits considering process variations
Path scheduling on digital microfluidic biochips
Occamy: Memory-efficient GPU Compiler for DNN Inference
A Convolution Neural Network Accelerator Design with Weight Mapping and Pipeline Optimization
Distributed run-time resource management for malleable applications on many-core platforms
SeIM: In-Memory Acceleration for Approximate Nearest Neighbor Search
Knowledge-based optimal IIL generator from conventional logic circuit descriptions
Hybrid Techniques for Fast Functional Simulation
PARO: Hardware-Software Co-design with Pattern-aware Reorder-based Attention Quantization in Video Generation Models
Layout Driven Technology Mapping
TSV-aware analytical placement for 3D IC designs
Partition and place finite element model on wafer-scale engine
A Scalable and Robust Compilation Framework for Emitter-Photonic Graph State
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis
Partial task assignment of task graphs under heterogeneous resource constraints
MIXS: A mixed level simulator for large digital system logic verification
Hardware/Software Co-Design: The Next Embedded System Design Challenge (Panel)
A Hardware Switch Level Simulator for Large MOS Circuits
Power-Constrained Printed Neuromorphic Hardware Training
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks
Statistical Battery Models and Variation-Aware Battery Management
A Channel/Switchbox Definition Algorithm for Building-Block Layout
Run-time instruction set selection in a transmutable embedded processor
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict
Register allocation for high-level synthesis using dual supply voltages
An effective test generation system for sequential circuits
Efficient WCRT analysis of synchronous programs using reachability
A correct network flow model for escape routing
Machine-learning-based hotspot detection using topological classification and critical feature extraction
Joint management of RAM and flash memory with access pattern considerations
Tensor Virtualization Technique to Support Efficient Data Reorganization for CNN Accelerators
Scheduling and Analysis of Parallel Real-Time Tasks with Semaphores
Design of a mask-programmable memory/multiplier array using G4-FET technology
A novel fuzzy matching model for lithography hotspot detection
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Simulation models for side-channel information leaks
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks
Automatic translation of software binaries onto FPGAs
Using machine learning to optimize graph execution on NUMA machines
A Probability-Based Approach to VLSI Circuit Partitioning
Optimizing quantum circuit synthesis for permutations using recursion
Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization
CMOS compatible nanowires for biosensing
A model-driven design environment for embedded systems
GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware
Sequential Test Generation at the Register-Transfer and Logic Levels
Any-Angle Routing for Redistribution Layers in 2.5D IC Packages
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors
MORPh: mobile OLED-friendly recording and playback system for low power video streaming
b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units
Performance Oriented Rectilinear Steiner Trees
Effective use of virtual grid compaction in macro-module generators
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs
Orchestrated multi-level information flow analysis to understand SoCs
Autodraft: A language and processor for design and drafting
Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories
Real-Time Dynamic IR-drop Prediction for IR ECO
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
Reptail: Cutting Storage Tail Latency with Inherent Redundancy
Content addressable memory based binarized neural network accelerator using time-domain signal processing
Plowing: Modifying Cells and Routing 45: 9D - Layouts
FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator
Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects
Computer designed multilayer hybrid substrate using thick film technology
LATTIS: An Iterative Speedup Heuristic for Mapped Logic
Semi-Formal Test Generation with Genevieve
Improved Selay Prediction for On-Chip Buses
Rational for and Organization of the Engineering Information System Program
Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical Systems
Automated feature localization for hardware designs using coverage metrics
Circuit and system design guidelines for ultra-low power sensor nodes
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement
Reducing channel density in standard cell layout
ReRAM-based graph attention network with node-centric edge searching and hamming similarity
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs
A Power Estimation Framework for Designing Low Power Portable Video Applications
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era
Late Breaking Results: RL-LPO: Reinforcement Learning Based Leakage Power Optimization Framework with Graph Neural Network
YAP: Yield Modeling and Simulation for Advanced Packaging
Interface Timing Verification Drives System Design
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique
SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models
Partitioning and placement technique for bus-structured PWB
LeHDC: learning-based hyperdimensional computing classifier
On tests to detect via opens in digital CMOS circuits
Computer-controlled hardware testing: A programmer's view of the test center
Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities
Hardware accelerators in the design automation environment
Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory
Robotics: The new automation tool
Interpolation-based incremental ECO synthesis for multi-error logic rectification
Hardware-efficient stochastic rounding unit design for DNN training: late breaking results
DIALED: Data Integrity Attestation for Low-end Embedded Devices
ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design
Levioso: Efficient Compiler-Informed Secure Speculation
Versatile mask generation techniques for custom microelectronic devices
Design optimization by adaptive control
CAP'NN: Class-Aware Personalized Neural Network Inference
Fault models for embedded-DRAM macros
A proven operational CAD system for P.W.B. design-based on a mini-computer and featuring fully automatic placement and routing
FIT: Fill Insertion Considering Timing
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
The Automatic Generation of Functional Test Vectors for Rambus Designs
Philosophic comments on data base context and management in design automation
ESM: A Framework for Building Effective Surrogate Models for Hardware-Aware Neural Architecture Search
Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet System
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990
SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits
HLSIM - A New Hierarchical Logic Simulator and Netlist Converter
Improved compaction by minimized length of wires
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew
Novel sizing algorithm for yield improvement under process variation in nanometer technology
OTTER: Optimal Termination of Transmission Lines Excluding Radiation
InCheck: An In-application Recovery Scheme for Soft Errors
Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications
Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory
The IPAD System: A future management/engineering/design environment
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
Model-based testing of automotive software: some challenges and solutions
Automatic generation of digital system schematic diagrams
System-level performance optimization of the data queueing memory management in high-speed network processors
Proactive channel adjustment to improve polar code capability for flash storage devices
Semi-automatic safety analysis and optimization
Over-the-Cell Channel Routing for High Performance Circuits
The "gap" between users and designers of CAD/CAM systems: Search for solutions
Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization
Towards resilient analog in-memory deep learning via data layout re-organization
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
Functional timing analysis made fast and general
Computer aided diagnostic design for electronic switching systems
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits
VLSI - a challenge for system designers (Position Statement)
KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference
LCS - A Leaf Cell Synthesizer Employing Formal Deduction Techniques
Coverage-oriented verification of banias
The Jini Architecture: Dynamic Services in a Flexible Network
PSMiner: A Pattern-Aware Accelerator for High-Performance Streaming Graph Pattern Mining
Distributed processing in manufacturing at GTE Automatic Electric
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors
System-level energy-efficient dynamic task scheduling
Module design verification system
A global routing algorithm for general cells
Microprogramming Design support System
Sting: Near-storage accelerator framework for scalable triangle counting and beyond
Design Automation for the Component Parts Industry
Using Symbolic Algebra in Algorithmic Level DSP Synthesis
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm
Vector coding techniques for high speed digital simulation
Learning-Aided Safe Controller Synthesis with Formal Guarantees via Vector Barrier Certificates
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
Design in reliability for communication designs
Multi-threaded reachability
Performance of a New Annealing Schedule
A highly scalable parallel boundary element method for capacitance extraction
Residue BDD and Its Application to the Verification of Arithmetic Circuits
OPERON: optical-electrical power-efficient route synthesis for on-chip signals
Functional Test Generation for FSMs by Fault Extraction
Fast and accurate source-level simulation of software timing considering complex code optimizations
Min/max On-Chip Inductance Models and Delay Metrics
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers
Scheduling Techniques to Enable Power Management
ICHABOD: a data base manager for design automation applications
Cost Minimization of Partitions into Multiple Devices
Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation
Design Methodology Management - a CAD Framework Initiative Perspective
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator
Logic partitioning
BitPruner: Network Pruning for Bit-serial Accelerators
Fast Exact Minimization of BDDs
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Driver Modeling and Alignment for Worst-Case Delay Noise
Formal micro-architectural analysis of on-chip ring networks
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings
Hardware/Software Partitioning and Pipelining
VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator
Go Beyond Black-box Policies: Rethinking the Design of Learning Agent for Interpretable and Verifiable HVAC Control
PAOLA: A tool for topological optimization of large PLAS
An efficient algorithm for statistical minimization of total power under timing yield constraints
mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process
INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications
Energy-Efficient On-Chip Training for Customized Home-based Rehabilitation Systems
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
Unification of Budgeting and Placement
Application of Constraint-Based Heuristics in Collaborative Design
FinerDedup: Sifting Fingerprints for Efficient Data Deduplication on Mobile Devices
IC mask layout with a single conductor layer
Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning
An 1130-based logic, layout and evaluation system
COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design
Discerning Limitations of GNN-based Attacks on Logic Locking
STL - a high level language for simulation and test
Distributed dynamic BDD reordering
An NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures
A timing-accurate modeling and simulation environment for networked embedded systems
A novel time and voltage based SAR ADC design with self-learning technique
PowerRChol: Efficient Power Grid Analysis Based on Fast Randomized Cholesky Factorization
Generalized augmented lagrangian and its applications to VLSI global placement
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips
VHSIC HDL
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system
TAPMM: A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems
A low latency router supporting adaptivity for on-chip interconnects
Statistical diagnosis of unmodeled systematic timing effects
A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs
Max-PIM: Fast and Efficient Max/Min Searching in DRAM
Acceleration of control flows on reconfigurable architecture with a composite method
A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications
Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions
Practical aspects of reliability analysis for IC designs
Formal Verification of Embedded Systems based on CFSM Networks
On metrics for comparing routability estimation methods for FPGAs
Is Redundancy Necessary to Reduce Delay
Should our power approach be current?
Delay reduction using simulated annealing
Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement
Quantum-Resistant Security: PQC Readiness and Research Challenges (Invited)
Placement of 3D ICs with Thermal and Interlayer Via Considerations
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints
Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration
An ATE assisted DFD technique for volume diagnosis of scan chains
DSPlacer: DSP Placement for FPGA-based CNN Accelerator
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography
Simultaneous flare level and flare variation minimization with dummification in EUVL
Biochemical oscillator sensitivity analysis in the presence of conservation constraints
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure
Node addition and removal in the presence of don't cares
Programmable logic circuits based on ambipolar CNFET
ESL: building the bridge between systems to silicon
Early prediction of NBTI effects using RTL source code analysis
A novel synthesis technique for communication controller hardware from declarative data communication protocol specifications
Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks
gGuard: Enabling Leakage-Resilient Memory Isolation in GPU-accelerated Autonomous Embedded Systems
Efficient simulation of oscillatory combinational loops
A unified CAD system for electronic design
Steiner network construction for timing critical nets
Automated layout synthesis in the YASC silicon compiler
Representation and Use of Design Rules within a Technology Adaptable CAD System
LENS: Layer Distribution Enabled Neural Architecture Search in Edge-Cloud Hierarchies
A High-Performance Stochastic Simulated Bifurcation Ising Machine
Exploration of associative power management with instruction governed operation for ultra-low power design
Bridge Fault simulation strategies for CMOS integrated Circuits
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
A rule-based approach to unifying functional and fault simulation and timing verification
Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration
Automating analog circuit diagrams using a list processing language
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips
Statistical Estimation of the Switching Activity in Digital Circuits
Time-shared computer aided design with the digital plotters
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs
Automatic generation of diagnostic programs for TOSBAC - 5400/150
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation
GATSPI: GPU accelerated gate-level simulation for power improvement
The conlan project: Status and future plans
Construction of reconfigurable clock trees for MCMM designs
Statistical multilayer process space coverage for at-speed test
Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training
Potential-NRG: Placement with Incomplete Data
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits
Automation of sheet metal design and manufacturing
InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design Insights
Optimum LDPC decoder: a memory architecture problem
Application of volumetric modeling to mechanical design and analysis
Making the wire frame solid
Efficient ensembles of graph neural networks
Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction
Lighting the dark silicon by exploiting heterogeneity on future processors
A Novel Covert Channel Attack Using Memory Encryption Engine Cache
Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits
InfScaler: Enabling Efficient ML Inference Serving on Multi-Accelerator Edge Devices via Asymmetric Auto-Scaling
PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical Type
An Overview of Logic Synthesis Systems
Learning to Quantize Deep Neural Networks: A Competitive-Collaborative Approach
333-eDRAM - 3T Embedded DRAM Leveraging Monolithic 3D Integration of 3 Transistor Types: IGZO, Carbon Nanotube and Silicon FETs
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications
Transformation based communication and clock domain refinement for system design
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling
Current status of AED
LightRIM: Light Runtime Integrity Measurement for Linux Kernels in Embedded Applications
Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: An Information-Theoretic Approach
Toward CAM-oriented CAD
Machine Learning-based Thermally-Safe Cache Contention Mitigation in Clustered Manycores
A Dynamically-Directed Switch Model for MOS Logic Simulation
"?": A Context-Sensitive Help System Based on Hypertext
Strategies for mainstream usage of formal verification
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs
Permissible Observability Relations in FSM Networks
Petri net modeling of gate and interconnect delays for power estimation
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
What to do when the seat of your pants wears out - the formalization of the VLSI design process
The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012
A synthesis methodology for application-specific logic-in-memory designs
Power-Grid Structure Exploration with Unified Sequence-based Learning Framework
EPOC: An Efficient Pulse Generation Framework with Advanced Synthesis for Quantum Circuits
A design by example regular structure generator
Limited Exception Modeling and Its Use in Presynthesis Optimizations
General Decomposition of Sequential Machines: Relationships to State Assignment
HEX: An instruction-driven approach to feature extraction
The analog behavior of digital integrated circuits
ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt Detector
Performance optimized floor planning by graph planarization
Crosstalk noise and bit error rate analysis for optical network-on-chip
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Web-based Algorithm Animation
A Novel Approach to Delay-Fault Diagnosis
ATV: An Abstract Timing Verifier
Synthesis of Multiple-Input Change Asynchronous Finite state Machines
Schedulability of event-driven code blocks in real-time embedded systems
Hardware description levels and test for complex circuits
Enabling File-Oriented Fast Secure Deletion on Shingled Magnetic Recording Drives
Scalable Certification Framework for Behavioral Synthesis Front-End
Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis
A SPICE model of flexible transition metal dichalcogenide field-effect transistors