yusuke1997/dblp-id-title huggingface dataset:
Application-aware prefetch prioritization in on-chip networks
MultiGraph: Efficient Graph Processing on GPUs
POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data
A GPU Multiversion B-Tree
An Evaluation of Vectorizing Compilers
Area and System Clock Effects on SMT/CMP Processors
EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions
Ordered and unordered algorithms for parallel breadth first search
Hiding Relaxed Memory Consistency with Compilers
Buffer-Safe Communication Optimization Based on Data Flow Analysis and Performance Prediction
Optimal bypass monitor for high performance last-level caches
Hardware support for spin management in overcommitted virtual machines
Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU
Implementation and Evaluation of the Complex Streamed Instruction Set
BenchPress: A Deep Active Benchmark Generator
Transactional prefetching: narrowing the window of contention in hardware transactional memory
A Scalable Low Power Store Queue for Large InstructionWindow Processors
Characterizing and Predicting Program Behavior and its Variability
POSTER: Hybrid Data Dependence Analysis for Loop Transformations
Adaptive spatiotemporal node selection in dynamic networks
Mage: online and interference-aware scheduling for multi-scale heterogeneous systems
Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models
Efficient Techniques for Advanced Data Dependence Analysis
MEDICS: ultra-portable processing for medical image reconstruction
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency
GraNNDis: Fast Distributed Graph Neural Network Training Framework for Multi-Server Clusters
Transformations for Improving Data Access Locality in Non-Perfectly Nested Loops
Dynamic Linking on a Shared-Memory Multiprocessor
Shared memory multiplexing: a novel way to improve GPGPU throughput
Data motifs: a lens towards fully understanding big data and AI workloads
General Parallel Computation can be Performed with a Cycle-Free Heap
A tuning framework for software-managed memory hierarchies
A Specialized BTB Organization for Servers
Efficacy and Performance Impact of Value Prediction
Compiling for the Impulse Memory Controller
Mappings for communication minimization using distribution and alignment
A New Heuristic for Scheduling Parallel Programs on Multiprocessor
Using the parallel complexity of programs to improve compaction
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback
A Multithreaded Runtime Environment with Thread Migration for a HPF Data-Parallel Compiler
A Thermal-Aware Data Replica Placement Strategy for Data-Intensive Data Centers
Zero-Value Caches: Cancelling Loads that Return Zero
RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions
NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs
SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs
Characterization of Silent Stores
Leakage Energy Management in Cache Hierarchies
Characterization of TCC on Chip-Multiprocessors
NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory Architectures
Improving branch prediction accuracy by reducing pattern history table interference
Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency
Scalable and Efficient Bounds Checking for Large-Scale CMP Environments
ThermOS: System support for dynamic thermal management of chip multi-processors
Memory scheduling towards high-throughput cooperative heterogeneous computing
VP Float: First Class Treatment for Variable Precision Floating Point Arithmetic
Faster and More Reliable Quantum SWAPs via Native Gates
An adaptive resource partitioning algorithm for SMT processors
Redeeming IPC as a Performance Metric for Multithreaded Programs
Partitioning streaming parallelism for multi-cores: a machine learning based approach
Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs
Pavise: Integrating Fault Tolerance Support for Persistent Memory Applications
CriticalFault: Amplifying Soft Error Effect Using Vulnerability-Driven Injection
Performance tuning scientific codes for dataflow execution
Internet of mobile things: challenges and opportunities
Predicated Static Single Assignment
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
Scalable Specialization: Architectures, Interfaces, & Applications
Redesigning Parallel Symbolic Computations Packages
Hybrid access-specific software cache techniques for the cell BE architecture
Handling Cross Interferences by Cyclic Cache Line Coloring
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, PACT 2024, Long Beach, CA, USA, October 14-16, 2024
vSPACE: Supporting Parallel Network Packet Processing in Virtualized Environments through Dynamic Core Management
Improving Compiler and Run-Time Support for Adaptive Irregular Codes
Exploiting loop-dependent stream reuse for stream processors
SM-centric transformation: circumventing hardware restrictions for flexible GPU scheduling
PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs
Towards Supporting Semiring in MLIR-Based COMET Compiler
Characterizing and Optimizing the Performance of Multithreaded Programs Under Interference
Mars: a MapReduce framework on graphics processors
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory
Exploring Memory Tiering Systems in the CXL Era via FPGA-based Emulation and Device-Side Management
A Study of a Transactional Parallel Routing Algorithm
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, PACT 2022, Chicago, Illinois, October 8-12, 2022
Compiler Assisted Load Balancing on Large Clusters
High-Performance Architecture Aware Sparse Convolutional Neural Networks for GPUs
Student Research Poster: A Scalable General Purpose System for Large-Scale Graph Processing
Transfer-Tuning: Reusing Auto-Schedules for Efficient Tensor Program Code Generation
Biomedical Computing and Visualization
MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies
Practical Near-Data Processing for In-Memory Analytics Frameworks
Quantifying Instruction Criticality
30th International Conference on Parallel Architectures and Compilation Techniques, PACT 2021, Atlanta, GA, USA, September 26-29, 2021
Neither more nor less: Optimizing thread-level parallelism for GPGPUs
TAFE: Thread Address Footprint Estimation for Capturing Data/Thread Locality in GPU Systems
Multi2Sim: a simulation framework for CPU-GPU computing
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass
Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems
Optimizing datacenter power with memory system levers for guaranteed quality-of-service
A Flexible Heterogeneous Multi-Core Architecture
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
A Matrix-Based Approach to the Global Locality Optimization Problem
Static Methods in Hybrid Branch Prediction
LaTTe: A Java VM Just-In-Time Compiler with Fast and Efficient Register Allocation
Bancroft: Genomics Acceleration Beyond On-Device Memory
Improving speculative loop parallelization via selective squash and speculation reuse
Faster FFTs via Architecture-Cognizance
Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems
KLA: a new algorithmic paradigm for parallel graph computations
POSTER: Location-Aware Computation Mapping for Manycore Processors
CoroAMU: Unleashing Memory-Driven Coroutines through Latency-Aware Decoupled Operations
Code Generation in the Polytope Model
Direct-mapped versus set-associative pipelined caches
StealthTest: Low Overhead Online Software Testing Using Transactional Memory
On-chip network design considerations for compute accelerators
Dynamic Elimination of Pointer-Expressions
Boolean Formula-Based Branch Prediction for Future Technologies
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes
Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems
Adapting to Intermittent Faults in Future Multicore Systems
Power-efficient instruction delivery through trace reuse
Exploring Last n Value Prediction
A Fast Interrupt Handling Scheme for VLIW Processors
Memory Hierarchy Design for a Multiprocessor Look-up Engine
Practical approach to single assignment code
Instruction Scheduling for Clustered VLIW DSPs
POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware
Exploring hybrid memory for GPU energy efficiency through software-hardware co-design
Architectural Support for the Stream Execution Model on General-Purpose Processors
A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions
Interprocedural Distribution Assignment Placement: More than Just Enhancing Intraprocedural Placing Techniques
Opportunistic Early Pipeline Re-steering for Data-dependent Branches
Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness
VLIW Across Multiple Superscalar Processors on a Single Chip
POSTER: Firestorm: Operating Systems for Power-Constrained Architectures
Scaling of the PARSEC benchmark inputs
MDL: A Language and Compiler for Dynamic Program Instrumentation
Compiling C for the EARTH multithreaded architecture
An empirical model for predicting cross-core performance interference on multicore processors
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls
Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management
Decoupling Schedule, Topology Layout, and Algorithm to Easily Enlarge the Tuning Space of GPU Graph Processing
UPIR: Toward the Design of Unified Parallel Intermediate Representation for Parallel Programming Models
A Silicon Photonic Multi-DNN Accelerator
Hera: A Heterogeneity-Aware Multi-Tenant Inference Server for Personalized Recommendations
Effective Usage of Vector Registers in Advanced Vector Architectures
A Flexible Approach to Autotuning Multi-Pass Machine Learning Compilers
OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access
A Compiler Framework for Recovery Code Generation in General Speculative Optimizations
ADHA: automatic data layout framework for heterogeneous architectures
Integrated Compilation and Scalability Analysis for Parallel Systems
Handling block-cyclic distributed arrays in Vienna Fortran 90
POPS: Coherence Protocol Optimization for Both Private and Shared Data
HERTI: A Reinforcement Learning-Augmented System for Efficient Real-Time Inference on Heterogeneous Embedded Systems
Parallel Execution of Radix Sort Program Using Fine-Grain Communication
Deep Program Structure Modeling Through Multi-Relational Graph-based Learning
SecSched: Flexible Scheduling in Secure Processors
APCR: an adaptive physical channel regulator for on-chip interconnects
Toast: A Heterogeneous Memory Management System
The influence of branch prediction table interference on branch prediction scheme performance
Performance impact of architectural features during binary to binary translation
Student Research Poster: Network Controller Emulation on a Sidecore for Unmodified Virtual Machines
HelperCore_DB: Exploiting Multicore Technology for Databases
Valkyrie: Leveraging Inter-TLB Locality to Enhance GPU Performance
Design of a hybrid MPI-CUDA benchmark suite for CPU-GPU clusters
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization
Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization Interface
Compiler-assisted data distribution for chip multiprocessors
Computing Three-Dimensional Constrained Delaunay Refinement Using the GPU
POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies
Comparing and Combining Read Miss Clustering and Software Prefetching
Probabilistic Models Towards Optimal Speculation of DFA Applications
Program generation for the all-pairs shortest path problem
PS-Dir: a scalable two-level directory cache
Optimizing remote data transfers in X10
Data Dependence Analysis of Assembly Code
Bit-Level Semantics: Scalable RAG Retrieval with Neurosymbolic Hyperdimensional Computing
SparseRT: Accelerating Unstructured Sparsity on GPUs for Deep Learning Inference
Fast, automatic, procedure-level performance tuning
Store-Ordered Streaming of Shared Memory
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
Power-Aware Compiler Controllable Chip Multiprocessor
Near-Memory Address Translation
Optimizing 3D Gaussian Splattering for Mobile GPUs
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture
Scalable thread scheduling and global power management for heterogeneous many-core architectures
DVFS-Aware Consolidation for Energy-Efficient Clouds
Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign
Containers on the Parallelization of General-Purpose Java Programs
On the Stability of Temporal Data Reference Profiles
Control-Flow Speculation through Value Prediction for Superscalar Processors
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
mlirSynth: Automatic, Retargetable Program Raising in Multi-Level IR Using Program Synthesis
The Impact of Resource Partitioning on SMT Processors
SparseFT: Sparsity-aware Fault Tolerance for Reliable CNN Inference on GPUs
Exploring the Design Space of Static and Incremental Graph Connectivity Algorithms on GPUs
Elastic-plastic flow simulation using the Supercomputer Toolkit
ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment
Eliminating Exception Constraints of Java Programs for IA-64
MIREncoder: Multi-modal IR-based Pretrained Embeddings for Performance Optimizations
Student Research Poster: Compiling Boolean Circuits to Non-deterministic Branching Programs to be Implemented by Light Switching Circuits
Student Research Poster: From Processing-in-Memory to Processing-in-Storage
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Automatic execution of single-GPU computations across multiple GPUs
DDCache: Decoupled and Delegable Cache Data and Metadata
Chrysalis analysis: incorporating synchronization arcs in dataflow-analysis-based parallel monitoring
Combating the Reliability Challenge of GPU Register File at Low Supply Voltage
Processor architecture: too much parallelism?
POSTER: The Liberation Day of Nondeterministic Programs
Memory Architecture for Integrating Emerging Memory Technologies
Rotating Register Allocation for Enhanced Pipeline Scheduling
XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs
Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading
INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core
Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies
Parallel and Scalable Precise Clustering
Code Generation in the Polyhedral Model Is Easier Than You Think
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
GPU evolution: will graphics morph into compute?
POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE
Resource Conscious Reuse-Driven Tiling for GPUs
Acorns: A Framework for Accelerating Deep Neural Networks with Input Sparsity
Rethinking Page Table Structure for Fast Address Translation in GPUs: A Fixed-Size Hashed Page Table
Combining analytical and empirical approaches in tuning matrix transposition
MLP-Aware Dynamic Cache Partitioning
Virtual PIM: Resource-Aware Dynamic DPU Allocation and Workload Scheduling Framework for Multi-DPU PIM Architecture
Recovery Mechanism for Latency Misprediction
VoxelCache: Accelerating Online Mapping in Robotics and 3D Reconstruction Tasks
POSTER: An Optimization of Dataflow Architectures for Scientific Applications
Using combined profiling to decide when thread level speculation is profitable
A New Framework for Integrated Global Local Scheduling
Modeling Superscalar Processors via Statistical Simulation
An empirical evaluation of the Convex SPP-1000 hierarchical shared memory system
Retargeting JIT Compilers by using C-Compiler Generated Executable Code
System-level power-performance efficiency modeling for emergent GPU architectures
Cache Automaton: Repurposing Caches for Automata Processing
Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms
POSTER: SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
Speculative Decoupled Software Pipelining
Reactive Multi-Word Synchronization for Multiprocessors
Architectural support for convolutional neural networks on modern CPUs
Separating Mechanism from Policy in STM
A programmable parallel accelerator for learning and classification
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback
Runtime optimization of vector operations on large scale SMP clusters
Unified Architectural Support for Soft-Error Protection or Software Bug Detection
PENCIL: A Platform-Neutral Compute Intermediate Language for Accelerator Programming
Optimizing Loop Performance for Clustered VLIW Architectures
SCREME: A Scalable Framework for Resilient Memory Design
Hash Map Inlining
Inference and declaration of independence: impact on deterministic task parallelism
Effective Performance Modeling and Domain-Specific Compiler Optimization of CNNs for GPUs
Load Balancing in Decoupled Look-ahead: A Do-It-Yourself (DIY) Approach
Batched Graph Community Detection on GPUs
DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing
Optimistic Register Coalescing
Coordinated power-performance optimization in manycores
Proxy Benchmarks for Emerging Big-Data Workloads
Runtime detection and optimization of collective communication patterns
EDGE: Event-Driven GPU Execution
Adaptive heterogeneous scheduling for integrated GPUs
Massively Parallel Open Modification Spectral Library Searching with Hyperdimensional Computing
Swing module scheduling: a lifetime-sensitive approach
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
The potential of using dynamic information flow analysis in data value prediction
Stratified sampling for even workload partitioning
Collaborative Caching for Unknown Cache Sizes
POSTER: GPU Based Near Data Processing for Image Processing with Pattern Aware Data Allocation and Prefetching
A portable, automatic data qantizer for deep neural networks
Challenges and Opportunities for Dataflow Processing on Exascale Computers
Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application!
Data Relation Vectors: A New Abstraction for Data Optimizations
Versatile and scalable parallel histogram construction
Q-gym: An Equality Saturation Framework for DNN Inference Exploiting Weight Repetition
SAM: Optimizing Multithreaded Cores for Speculative Parallelism
Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systems
Accelerating Sparse CNN Inference on GPUs with Performance-Aware Weight Pruning
D 2 MA: accelerating coarse-grained data transfer for GPUs
Reduction Drawing: Language Constructs and Polyhedral Compilation for Reductions on GPU
SIGARCH Conference Guidelines
Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces
Self-parallelization of sequential object codes
Interprocedural Array Remapping
Achieving Scalability in a k-NN Multi-GPU Network Service with Centaur
Identifying the capability of overlapping computation with communication
Loop induction variable canonicalization in parallelizing compilers
A Distributed Control Path Architecture for VLIW Processors
Performance Improvement via Always-Abort HTM
Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications
SQRL: hardware accelerator for collecting software data structures
Automatic Correction of Loop Transformations
Squire: A General-Purpose Accelerator to Exploit Fine-Grain Parallelism on Dependency-Bound Kernels
MLIR Loop Optimizations for High-Level Synthesis: A Case Study
Atributed consistent hashing for heterogeneous storage systems
Fusion of Parallel Array Operations
Experiences with MapReduce, an abstraction for large-scale computation
T-GCN: A Sampling Based Streaming Graph Neural Network System with Hybrid Architecture
Source Level Merging of Independent Programs
Filtering Techniques to Improve Trace-Cache Efficiency
An Optimization of Resource Arrangement for Network-on-Chip using Genetic Algorithm
ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML
Software-Pipelining on Multi-Core Architectures
Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP
Code Reordering and Speculation Support for Dynamic Optimization System
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013
On mitigating memory bandwidth contention through bandwidth-aware scheduling
Decoupled Software Pipelining with the Synchronization Array
Keynote talk: Parallel programming for mobile computing
SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores
Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design
Interprocedural strength reduction of critical sections in explicitly-parallel programs
Command Vector Memory Systems: High Performance at Low Cost
A robust compile time method for scheduling task parallelism on distributed memory machines
CAWS: criticality-aware warp scheduling for GPGPU workloads
Visualizing transactional memory
Boost.SIMD: generic programming for portable SIMDization
Challenges and opportunities in the post single-thread-processor era
Skewed redundancy
SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors
MapCG: writing parallel program portable between CPU and GPU
Recompiling QAOA Circuits on Various Rotational Directions
POSTER: Collective Dynamic Parallelism for Directive Based GPU Programming Languages and Compilers
A two-phase escape analysis for parallel java programs
Complexity-effective multicore coherence
LibraPIM: Dynamic Load Rebalancing to Maximize Utilization in PIM-Assisted LLM Inference Systems
The meeting graph: a new model for loop cyclic register allocation
Weightless Neural Networks for Efficient Edge Inference
MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors
Reducing Cache Conflicts by Partitioning and Privatizing Shared Arrays
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors
Static Locality Analysis for Cache Management
Enhancing Address Translations in Throughput Processors via Compression
Collage: Seamless Integration of Deep Learning Backends with Automatic Placement
Efficient runahead threads
Overview of HPC and AI Computing for COVID-19 in the US
An Efficient, Self-Contained, On-chip Directory: DIR1-SISD
Exploiting Parallelism on GPUs and FPGAs with OmpSs
Improving Cache Behavior of Dynamically Allocated Data Structures
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
Dynamic Fine-Grain Scheduling of Pipeline Parallelism
A Hierarchical Approach to Maximizing MapReduce Efficiency