yusuke1997/dblp-id-title huggingface dataset:
Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives
Way-predicting set-associative cache for high performance and low energy consumption
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits
The design and implementation of PowerMill
Cost-efficient Processing-in-Memory Architecture with Training-free and Universal Error Compensation
Memory modeling for system synthesis
Performance and energy-efficiency improvement through modified CPL in organic transistor integrated circuits
Maximum power transfer tracking for a photovoltaic-supercapacitor energy system
An integrated optimization framework for reducing the energy consumption of embedded real-time applications
Low power data processing by elimination of redundant computations
Demo Abstract: ECO: Low Power Context-Aware Multimodal AI on NPUs
Thermal-aware methodology for repeater insertion in low-power VLSI circuits
A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : - Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation -
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS
Heterogeneous Computing and Infrastructure for Energy Efficiency in Microsoft Data Centers: Extended Abstract
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology
Thermal-aware task scheduling at the system software level
Energy harvesting from anti-corrosion power sources
Multi-channel precision-sparsity-adapted inter-frame differential data codec for video neural network processor
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs
Fast high-level power estimation for control-flow intensive design
Power-gating-aware high-level synthesis
New stability criteria for the design of low-pass sigma-delta modulators
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection
NBTI-aware power gating for concurrent leakage and aging optimization
A dual-mode architecture for fast-switching STT-RAM
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors
DISHA: Low-Energy Sparse Transformer at Edge for Outdoor Navigation for the Visually Impaired Individuals
Architecting voltage islands in core-based system-on-a-chip designs
Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converter
Parametric timing and power macromodels for high level simulation of low-swing interconnects
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors
Low power circuit design based on heterojunction tunneling transistors (HETTs)
An on-chip autonomous thermoelectric energy management system for energy-efficient active cooling
Improving energy efficiency of write-asymmetric memories by log style write
Near optimal battery-aware energy management
Aggressive Slack Recycling via Transparent Pipelines
Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking
Electromigration and voltage drop aware power grid optimization for power gated ICs
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits
A 0.4-V UWB baseband processor
Energy Efficiency Through In-Sensor Computing: ADC-less Real-Time Sensing for Image Edge Detection
Leakage and leakage sensitivity computation for combinational circuits
Low-power current-mode transceiver for on-chip bidirectional buses
Analytical results for design space exploration of multi-core processors employing thread migration
Any-time probabilistic switching model using bayesian networks
Practical performance/power alternatives within an existing CMOS technology generation
A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations
Early power grid verification under circuit current uncertainties
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition
Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications
Energy recovery for the design of high-speed, low-power static RAMs
A Light-powered, "Always-On", Smart Camera with Compressed Domain Gesture Detection
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology
Active SSD design for energy-efficiency improvement of web-scale data analysis
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique
Low-energy embedded FPGA structures
Data-Driven Low-Cost On-Chip Memory with Adaptive Power-Quality Trade-off for Mobile Video Streaming
Error-resilient low-power Viterbi decoders
Instruction flow-based front-end throttling for power-aware high-performance processors
Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors
A semi-custom voltage-island technique and its application to high-speed serial links
An improved pass transistor synthesis method for low power, high speed CMOS circuits
Energy-optimal caches with guaranteed lifetime
A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs
EA^2: Energy Efficient Adaptive Active Learning for Smart Wearables
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs
Energy efficient implementation of parallel CMOS multipliers with improved compressors
The impact of battery capacity and memory bandwidth on CPU speed-setting: a case study
International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013
FLASH-D: FlashAttention with Hidden Softmax Division
Optimization of high-performance superscalar architectures for energy efficiency
GenSoC: A Multi-Agent-Assisted SoC Generation Methodology Leveraging Open-Source Hardware
Therma: Thermal-aware Run-time Thread Migration for Nanophotonic Interconnects
Efficient and Secure Group Key Management in IoT using Multistage Interconnected PUF
Secure Human-Internet using dynamic Human Body Communication
A process variation aware low power synthesis methodology for fixed-point FIR filters
Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition
GAVINA: flexible aggressive undervolting for bit-serial mixed-precision DNN acceleration
Recent developments in high integration multi-standard CMOS transceivers for personal communication systems
SAPP: scalable and adaptable peak power management in nocs
Design and analysis of 6-T 2-MTJ ternary Content Addressable Memory
Low power design without compromise (panel)
ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs
Pinned to the walls: impact of packaging and application properties on the memory and power walls
System-level power estimation and optimization
Processing-in-Memory Using Optically-Addressed Phase Change Memory
Maximum power transfer tracking in a solar USB charger for smartphones
A forward body-biased low-leakage SRAM cache: device and architecture considerations
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist
AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing
Dataflow analysis for energy-efficient scratch-pad memory management
Formalized methodology for data reuse exploration in hierarchical memory mappings
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster
RIMIX: RISC-V Core with MIXed-Precision SIMD Instruction Extensions Supported by Oracle-Assisted Sub-Network Search for Efficient TinyML
CMOS VCOs for frequency synthesis in wireless biotelemetry
Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar
Sky-NN: Enabling Efficient Neural Network Data Processing with Skyrmion Racetrack Memory
Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling
Energy-Efficient Single-Ended Capacitive PAM-4 Transceiver for Next-Generation HBM Interfaces
An MTCMOS design methodology and its application to mobile computing
A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces
TurboTag: lookup filtering to reduce coherence directory power
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches
HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors
RAPL: memory power estimation and capping
Stochastic modeling of a power-managed system: construction and optimization
Power-aware performance increase via core/uncore reinforcement control for chip-multiprocessors
Sustainable IT ecosystems and data centers
Efficient switching activity computation during high-level synthesis of control-dominated designs
SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization
Profile-driven code execution for low power dissipation (poster session)
A High-Performance Low-Power Barrett Modular Multiplier for Cryptosystems
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis
Reference-circuit analysis for high-bandwidth spin transfer torque random access memory
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning
A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing
Energy-efficient and performance-enhanced disks using flash-memory cache
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
Battery-Aware Electric Truck Delivery Route Planner
The microarchitecture of a low power register file
Power efficiency for variation-tolerant multicore processors
A 2 M: Approximate Algebraic Memory Using Polynomials Rings
On the rules of low-power design (and how to break them)
Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control
Low power logic for statistical inference
Slew-aware clock tree design for reliable subthreshold circuits
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control
Hardware Acceleration of Inference on Dynamic GNNs
Discharge current steering for battery lifetime optimization
ID-VS A: Independent and Dynamic Vector Symbolic Architecture for Energy-Efficient Edge Al
A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation
Load-matching adaptive task scheduling for energy efficiency in energy harvesting real-time embedded systems
Databus charge recovery: practical considerations
BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices
Making B + -tree efficient in PCM-based main memory
Drift-tolerant Coding to Enhance the Energy Efficiency of Multi-Level-Cell Phase-Change Memory
Algorithms for power-efficient QoS in application specific NoCs
Run-time power estimation in high performance microprocessors
Modeling and power optimization of cyber-physical systems with energy-workload tradeoff
DPIMA: A DRAM-Based Processing-in-Memory Accelerator for Privacy-Preserving Machine Learning
A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCs
Demo Abstract: Radar-PIM-Lite: Ultra-Low-Power PIM Processor for Real-Time UWB Radar Respiration Detection on UAVs
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations
Non redundant data cache
A low power duobinary voltage mode transmitter
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
A 28nm Scalable and Flexible Accelerator for Sparse Transformer Models
Logic synthesis using power-sensitive don't care sets
Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2025, Reykjavík, Iceland, August 6-8, 2025
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
A tunable Ultra Low Power inductorless Low Noise Amplifier exploiting body biasing of 28 nm FDSOI technology
O 2 C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors
Bit-width reduction and customized register for low cost convolutional neural network accelerator
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation
Energy-efficient and high-performance instruction fetch using a block-aware ISA
A low power video processor
Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array
Lifetime aware resource management for sensor network using distributed genetic algorithm
Characterizing and evaluating voltage noise in multi-core near-threshold processors
ComBoost: An Instruction Complexity Aware DTM Technique for Edge Devices
An energy efficient TLB design methodology
Reducing TLB power requirements
Low threshold CMOS circuits with low standby current
Conforming inverted data store for low power memory
Carbon nanotube imperfection-immune digital VLSI
A 640pW 32kHz switched-capacitor ILO analog-to-time converter for wake-up sensor applications
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency
A 1-V 1-Mb SRAM for portable equipment
An Energy-Efficient PUF Design: Computing While Racing
Low-power miniaturized information display systems
Power utility maximization for multiple-supply systems by a load-matching switch
Exploiting program hotspots and code sequentiality for instruction cache leakage management
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA
A low power 3D integrated FFT engine using hypercube memory division
UNO: Virtualizing and Unifying Nonlinear Operations for Emerging Neural Networks
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits
Breaking POps/J Barrier with Analog Multiplier Circuits Based on Nonvolatile Memories
Designing ultra-low voltage logic
Power-efficient directional wireless communication on small form-factor mobile devices
Low power current mode receiver with inductive input impedance
Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC converters
Low-Power Multi-Camera Object Re-Identification using Hierarchical Neural Networks
Challenges in low-power analog circuit design for sub-28nm CMOS technologies
A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications
Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCs
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996
RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology
Analysis of power-performance for ultra-thin-body GeOI logic circuits
Improving energy efficiency by making DRAM less randomly accessed
A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems
Automated checkpointing for enabling intensive applications on energy harvesting devices
Design issues for dynamic voltage scaling
Energy-efficient signal processing in wearable embedded systems: an optimal feature selection approach
Charge-pump assisted low-power/low-voltage CMOS opamp design
Enabling high-performance LPDDRx-compatible MRAM
Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes
MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems
HQ-DTM: A Hierarchical Q-learning Algorithm for Dynamic Thermal Management of Multi-core Processors
Low power methodology and design techniques for processor design
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
Challenges and opportunities in low-power design enablement
A power metric for mobile systems
Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks
Bridging the Gap Between Spiking Neural Networks & LSTMs for Latency & Energy Efficiency
A sequential procedure for average power analysis of sequential circuits
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
Battery management for grid-connected PV systems with a battery
Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency
Impact of technology scaling on energy aware execution cache-based microarchitectures
Low power RF IC design for wireless communication
An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal
iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product
Activity-sensitive architectural power analysis for the control path
Caching for bursts (C-Burst): let hard disks sleep well and work energetically
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023
Optimal body bias selection for leakage improvement and process compensation over different technology generations
Energy: efficient instruction dispatch buffer design for superscalar processors
Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding
Gated-V dd : a circuit technique to reduce leakage in deep-submicron cache memories
Demo Abstract: A Low-Power Real-Time Hardware Accelerator for Edge Detection Using Stochastic Computing
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters
Power reduction in on-chip interconnection network by serialization
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages
Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques
Unified Power Frequency Model Framework
Online Solar Energy Prediction for Energy-Harvesting Internet of Things Devices
Power calculation and modeling in deep submicron
TeleProbe: Zero-power Contactless Probing for Implantable Medical Devices
Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation
DynSleep: Fine-grained Power Management for a Latency-Critical Data Center Application
Multi-Source Transfer Learning for Design Technology Co-Optimization
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET
2.45 GHz power and data transmission for a low-power autonomous sensors platform
Adaptive sprinting: How to get the most out of Phase Change based passive cooling
Cryogenic CMOS as an Enabler for Low Power Dynamic Logic
HTNN: Deep Learning in Heterogeneous Transform Domains with Sparse-Orthogonal Weights
Low-power carry-select adder using adaptive supply voltage based on input vector patterns
MODEST: a model for energy estimation under spatio-temporal variability
Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors
A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks
On leakage currents: sources and reduction for transistors, gates, memories and digital systems
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors
Low power logic synthesis under a general delay model
Hardware acceleration for similarity measurement in natural language processing
Invited paper: Resilient and energy-secure power management
B#: a battery emulator and power profiling instrument
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
Scheduling of Hybrid Battery-Supercapacitor Control Instructions for Longevity in Systems with Power Gating
Effects of random MOSFET parameter fluctuations on total power consumption
Smart butterfly: reducing static power dissipation of network-on-chip with core-state-awareness
Computing in memory with FeFETs
Power management in the Intel Xeon E5 v3
Robust level converter design for sub-threshold logic
Low power and EMI, high frequency, crystal oscillator
Device optimization for ultra-low power digital sub-threshold operation
Dealing with disaggregation in ever-changing world of semiconductors
Synchronization-driven dynamic speed scaling for MPSoCs
Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture
Energy efficient data transfer and storage organization for a MAP turbo decoder module
Clock gating for power optimization in ASIC design cycle theory & practice
CoolDRAM: An Energy-Efficient and Robust DRAM
A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing
Power reduction by varying sampling rate
An open-source framework for formal specification and simulation of electrical energy systems
Aging mitigation of power supply-connected batteries
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
The energy complexity of register files
NNest: Early-Stage Design Space Exploration Tool for Neural Network Inference Accelerators
FreqLeak: A frequency step based method for efficient leakage power characterization in a system
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits
WoM-SET: Low power proactive-SET-based PCM write using WoM code
Dynamic idle core management and leakage current reuse in MPSoC platforms
Architecture strategies for energy-efficient packet forwarding in wireless sensor networks
The K computer : Japanese next-generation supercomputer development project
Input-specific dynamic power optimization for VLSI circuits
0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS
Power consumption of parallel spread spectrum correlator architectures
CompHD: Efficient Hyperdimensional Computing Using Model Compression
SparTANN: sparse training accelerator for neural networks with threshold-based sparsification
A framework for energy-scalable communication in high-density wireless networks
ESPN: A case for energy-star photonic on-chip network
The design of a low power asynchronous multiplier
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation
ECLIP: Energy-efficient and Practical Co-Location of ML Inference on Spatially Partitioned GPUs
Data manipulation techniques to reduce phase change memory write energy
Location cache: a low-power L2 cache system
Buffered clock tree synthesis considering self-heating effects
The impact of SOI MOSFETs on low power digital circuits