yusuke1997/dblp-id-title huggingface dataset:
Forecasting File Lifecycles for Intelligent Data Placement in Hierarchical Storage
A Jaccard Weights Kernel Leveraging Independent Thread Scheduling on GPUs
Parallelism and Scalability: A Solution Focused on the Cloud Computing Processing Service Billing
Reusing Traces in a Dynamic Conditional Execution Architecture
Adaptive Compressed Caching: Design and Implementation
A Generic API for Load Balancing in Structured P2P Systems
AI Gauge: Runtime Estimation for Deep Learning in the Cloud
DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability
A Parallel Implementation of Gomory-Hu's Cut Tree Algorithm
Performance Analysis and Optimization of the Vector-Kronecker Product Multiplication
TCUDA: A QoS-based GPU Sharing Framework for Autonomous Navigation Systems
A Flexible Operational Framework for Energy Profiling of Programs
Scalable and Efficient Spatial-Aware Parallelization Strategies for Multimedia Retrieval
Exploiting Compute Caches for Memory Bound Vector Operations
FGSCM: A Fine-Grained Approach to Transactional Lock Elision
A Hadoop Extension to Process Mail Folders and its Application to a Spam Dataset
Optimizing Memory Locality Using a Locality-Aware Page Table
A Speculative Trace Reuse Architecture with Reduced Hardware Requirements
Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation
Applying the zeros switch-off technique to reduce static energy in data caches
A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments
Parallel Approaches in the Heavy Ball GMRES Method
Optically Connected Memory for Disaggregated Data Centers
Comparing Performance and Portability Between CUDA and SYCL for Protein Database Search on NVIDIA, AMD, and Intel GPUs
An Evaluation of cJava System Architecture
23rd International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2011, Vitória, Espírito Santo, Brazil, October 26-29, 2011
Automated GPU Grid Geometry Selection for OPENMP Kernels
A Case Study of Hybrid Dataflow and Shared-Memory Programming Models: Dependency-Based Parallel Game Engine
FiBHA: Fixed Budget Hybrid CNN Accelerator
17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 24-27 October 2005, Rio de Janeiro, Brazil
Cluster Cache Monitor
Enabling Efficient Job Dispatching in Accelerator-Extended Heterogeneous Systems with Unified Address Space
Parallel Exact Inference on Multicore Using MapReduce
A Performance Comparison of HPC Workloads on Traditional and Cloud-Based HPC Clusters
Optimal Time and Energy-Aware Client Selection Algorithms for Federated Learning on Heterogeneous Resources
Massively Parallel Nearest Neighbor Queries for Dynamic Point Clouds on the GPU
Using Hardware Transactional Memory to Enable Speculative Trace Optimization
Evaluation Model and Performance Analysis of NIC Aggregations in Containerized Private Clouds
Distributed Shared Memory in Kernel Mode
Integrating Dataflow Abstractions into the Shared Memory Model
EASE: Energy Efficiency and Proportionality Aware Virtual Machine Scheduling
Exploiting Computational Resources in Distributed Heterogeneous Platforms
Adaptive Scheduling of Collocated Applications Using a Task-Based Runtime System
Design and Implementation of Brain Fiber Tracking for GPUs and PC Clusters
Classification and Elimination of Conflicts in Hardware Transactional Memory Systems
Towards a Federated Learning Framework on a Multi-Cloud Environment
Performance Models for Heterogeneous Systems Applied to the Dark Silicon-Aware Design Space Exploration
A Fast and Concise Parallel Implementation of the 8x8 2D IDCT using Halide
Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units
31st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2019, Campo Grande, Brazil, October 15-18, 2019
Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards
A Parallel Implementation of the LTSn Method for a Radiative Transfer Problem
Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?
26th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014, Paris, France, October 22-24, 2014
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages
Strategies for Fault-Tolerant Tightly-Coupled HPC Workloads Running on Low-Budget Spot Cloud Infrastructures
Parallel Boundary Elements Using Lapack and ScaLapack
sputniPIC: An Implicit Particle-in-Cell Code for Multi-GPU Systems
Performance Evaluation of a Prototype Distributed NFS Server
The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture
Multi-dimensional Evaluation of Haswell's Transactional Memory Performance
Exploring Self-Adaptivity Towards Performance and Energy for Time-Stepping Methods
Infrastructure, Requirements and Applications for e-Science
Memory Reclamation Methods for Lock-Free Hash Tries
An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm
Fast Parallel FFT on a Reconfigurable Computation Platform
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures
Component-Based Refactoring of Parallel Numerical Simulation Programs: A Case Study on Component-Based Parallel Programming
FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments
Reconfigurable System with Virtuoso Real-Time Kernel and TEV Environment
Accelerating Kirchhoff Migration by CPU and GPU Cooperation
Energy Efficient Last Level Caches via Last Read/Write Prediction
Conceptual and Comparative Analysis of Application Metrics in Microservices
Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches
TangramFP: Energy-Efficient, Bit-Parallel, Multiply-Accumulate for Deep Neural Networks
Balancing Load of GPU Subsystems to Accelerate Image Reconstruction in Parallel Beam Tomography
Profiling Patterns of Bit Flipping for Software Transactional Memories
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform
A Parallel IRAM Algorithm to Compute PageRank for Modeling Epidemic Spread
Runtime Management of Data Quality for Scientific Observatories Using Edge and In-Transit Resources
19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil
Selecting efficient VM types to train deep learning models on Amazon SageMaker
Towards Production Code Effective Portability among Vector Machines and Microprocessor-Based Architectures
Optimisation of a Molecular Dynamics Simulation of Chromosome Condensation
High-Quality I/O Bandwidth Prediction with Minimal Data via Transfer Learning Workflow
A New Multi-Processor Architecture for Parallel Lazy Cyclic Reference Counting
Visual Mapping of Program Components to Resources Representation: A 3D Analysis of Grid Parallel Applications
A Multi-GPU Python Solver for Low-Temperature Non-Equilibrium Plasmas
Profiling and Reducing Micro-Architecture Bottlenecks at the Hardware Level
LU Decomposition on GPUs: The Impact of Memory Access
Level-3 BLAS on the TI C6678 Multi-core DSP
Improving the Communication Network of a Cluster of PC's to Solve Implicit CFD Problems
The Performance of a Bare Machine Email Server
Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-Precision Computing
Towards a Power-Aware Application Level Scheduler for a Multithreaded Runtime Environment
A Fault-Tolerant Agent-Based Architecture for Transient Servers in Fog Computing
Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control
Self-Adaptive Fuzzy Mechanism to Load Balancing on the Web Services Provider
Quantum Virtual Machine: A Scalable Model to Optimize Energy Savings and Resource Management
Analyzing Cache Coherence Protocols for Server Consolidation
Quantifying and detecting HPC resource wastage in cloud environments
Achieving Fault Tolerance on Grids with the CPPC Framework and the GridWay Metascheduler
Exploring Federated Learning to Trace Depression in Social Media with Language Models
Improving an MPI Application-Level Migration Approach through Checkpoint File Splitting
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters
2016 International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD Workshops 2016, Los Angeles, CA, USA, October 26-28, 2016
The Network Adapter: The Missing Link between MPI Applications and Network Performance
Hardware Multiversioning for Fail-Operational Multithreaded Applications
Compression Speed Enhancements to LZO for Multi-core Systems
Efficient Scan Operator Methods on a GPU
Speeding Up Stencil Computations with Kernel Convolution
Energy Consumption Analysis of Instruction Cache Prefetching Methods
A predictive approach for dynamic replication of operators in distributed stream processing systems
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics
Efficient Strategies for Graph Pattern Mining Algorithms on GPUs
Graph Templates for Dataflow Programming
Performance Evaluation of the Dual-Core Based SGI Altix 4700
Exploring the Effects of Silent Data Corruption in Distributed Deep Learning Training
A Case Study on Optimizing Accurate Half Precision Average
kD-Tree Traversal Implementations for Ray Tracing on Massive Multiprocessors: A Comparative Study
Efficient Irregular Wavefront Propagation Algorithms on Intel(R) Xeon Phi(TM)
A Cloud-Based Batch Processing System for Loosely-Coupled Applications
A New Efficient Parallel Algorithm for Minimum Spanning Tree
Analysing Mechanisms for Virtual Channel Management in Low-Diameter Networks
An Argument in Favor of Strong Scaling for Deep Neural Networks with Small Datasets
Design Space Exploration of Memory Model for Heterogeneous Computing
Stream Oriented Modular Architecture with Polymorphic Processing Engines
Taming the Big Data Monster: Managing Petabytes of Data with Multi-Model Databases
Efficient Sorting on the Tilera Manycore Architecture
Energy Aware Dynamic Provisioning for Heterogeneous Data Centers
Tackling Permanent Faults in the Network-on-Chip Router Pipeline
Design and Evaluation of Hierarchical Rings with Deflection Routing
Exploiting Loop-Level Parallelism with the Shift Architecture
A Comparative Study of SYCL, OpenCL, and OpenMP
TASO: Time and Space Optimization for Memory-Constrained DNN Inference
Non-stationary Simulation of Computer Systems and Dynamic Performance Evaluation: A Concern-Based Approach and Case Study on Cloud Computing
Aspect-Based Patterns for Grid Programming
Parallel Adaptive Mesh Coarsening for Seismic Tomography
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation
Experimental Study of Power Consumption of Basic Parallel Programs
Efficient Tensor Slicing for Multicore NPUs using Memory Burst Modeling
Wait-Free Global Virtual Time Computation in Shared Memory TimeWarp Systems
Progressive Codesign of an Architecture and Compiler Using a Proxy Application
Structure-Constrained Microcode Compression
Ion-Molecule Collision Cross-Section Simulation using Linked-cell and Trajectory Parallelization
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs
High Performance Computing in Science and Engineering
Performance Issues for Parallel Implementations of Bootstrap Simulation Algorithm
Scalable, Efficient, and Policy-Aware Deduplication for Primary Distributed Storage Systems
21st International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2009, Sao Paolo, Brazil, October 28-31, 2009
LibBFT: A High-Performace Timed Automata Library Collection for Byzantine Fault Tolerance
MRU-Tour-based Replacement Algorithms for Last-Level Caches
Dynamic Set Stealing to Improve Cache Performance
Measuring Operating System Overhead on CMT Processors
A Study of Errant Pipeline Flushes Caused by Value Misspeculation
BEASY: Making EASY Backfilling Renewable-Only
BTL: A Framework for Measuring and Modeling Energy in Memory Hierarchies
Beyond the Fog: Bringing Cross-Platform Code Execution to Constrained IoT Devices
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems
Global Snapshot of a Distributed System Running on Virtual Machines
Effective Dynamic Scheduling on Heterogeneous Multi/Manycore Desktop Platforms
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Achieving Enhanced Performance Combining Checkpointing and Dynamic State Partitioning
Accelerating Graph Analytics on CPU-FPGA Heterogeneous Platform
Analyzing the Loop Scheduling Mechanisms on Julia Multithreading
A Reconfigurable Run-Time System for Filter-Stream Applications
Accelerating Computational Fluid Dynamics on the IBM Blue Gene/P Supercomputer
Performance Characterisation of Intra-Cluster Collective Communications
Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading
A Modeling Methodology and Pre-Run-Time Scheduling for Embedded Real-Time Software
Data Segmentation Management Infrastructure in a Database Grid
A Memory Affinity Analysis of Scientific Applications on NUMA Platforms
Computing Properties of Large Scalable and Fault-Tolerant Logical Networks
DRAM Errors and Cosmic Rays: Space Invaders or Science Fiction?
Implementing the Broadcast Operation in a Distributed Task-based Runtime
Addressing Energy Challenges in Filter Caches
MASA-StarPU: Parallel Sequence Comparison with Multiple Scheduling Policies and Pruning
On-line Scheduling of MPI-2 Programs with Hierarchical Work Stealing
Modeling the Performance of the Hadoop Online Prototype
Performance Analysis of Parallel Programs Using Prober as a Single Aid Tool
Online Detection of Spectre Attacks Using Microarchitectural Traces from Performance Counters
High-Performance Ensembles of Online Sequential Extreme Learning Machine for Regression and Time Series Forecasting
18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 17-20 October 2006, Ouro Preto, Minas Gerais, Brazil
Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures
Overcoming Memory-Capacity Constraints in the Use of ILUPACK on Graphics Processors
Predictive and Distributed Routing Balancing on High-Speed Cluster Networks
Performance-Aware Device Driver Architecture for Signal Processing
Harnessing Cloud Computing for Geophysical Exploration
A Scalability and Sensitivity Study of Parallel Geometric Algorithms for Graph Partitioning
RadFlow: An Interest-Centric Task Based Dataflow Runtime
Metrics for Packing Efficiency and Fairness of HPC Cluster Batch Job Scheduling
Exploiting Non-conventional DVFS on GPUs: Application to Deep Learning
A Run-time System for Efficient Execution of Scientific Workflows on Distributed Environments
Dataflow Virtual Machine Profiling
HPC Data Storage at a Glance: The Santos Dumont Experience
A Machine Learning Approach for Parameter Screening in Earthquake Simulation
Leveraging Task-Parallelism with OmpSs in ILUPACK's Preconditioned CG Method
International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2024 - Workshops, Hilo, HI, USA, November 13-15, 2024
Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms
Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning
A Distributed Algorithm for Identifying Strongly Connected Components on Incremental Graphs
20th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2008, October 29 - November 1, 2008, Campo Grande, MS, Brazil
Workload Balancing Methodology for Data-Intensive Applications with Divisible Load
Design Space Exploration using T&D-Bench
Energy - Efficient IaaS-PaaS Co-Design for Flexible Cloud Deployment of Scientific Applications
Lock-Free GaussSieve for Linear Speedups in Parallel High Performance SVP Calculation
Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM Performance in FPGA
22nd International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PAD 2010 Workshops, Petropolis, Brazil, October 27-30, 2010
Evaluating Computation and Data Placements in Edge Infrastructures through a Common Simulator
Automatic Generation of Custom Parallel Processors for Morphological Image Processing
Cloud Workload Analysis with SWAT
Analyzing a Five-Year Failure Record of a Leadership-Class Supercomputer
GPU-Accelerated High-Speed Eye Pupil Tracking System
Combining Source Routing and Dynamic Fault Tolerance
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
Modeling the Impact of Workload on Cloud Resource Scaling
Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures
Finite Element Nodal Approach for Parallel Processing of Non Linear Shell Analysis
Profiling General Purpose GPU Applications
ECHOFS: A Scheduler-Guided Temporary Filesystem to Leverage Node-Local NVMS
29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017, Campinas, Brazil, October 17-20, 2017
HYPPO: A Hybrid, Piecewise Polynomial Modeling Technique for Non-Smooth Surfaces
Distributed Skycube Computation with Anthill
Fast LH
High-Level Dataflow Programming for Reconfigurable Computing
A Processor Workload Distribution Algorithm for Massively Parallel Applications
Optimizing Packet Capture on Symmetric Multiprocessing Machines
Exploring Memory Hierarchy with ArchC
Hybrid MPI+openMP Implementation of eXtended Discrete Element Method
GC-CR: A Decentralized Garbage Collector Component for Checkpointing in Clouds
Disaggregated Memory with SmartNIC Offloading: a Case Study on Graph Processing
Highly Scalable Stencil-Based Matrix-Free Stochastic Estimator for the Diagonal of the Inverse
Tuning Up TVD HOPMOC Method on Intel MIC Xeon Phi Architectures with Intel Parallel Studio Tools
BatchQueue: Fast and Memory-Thrifty Core to Core Communication
Queue Register File Optimization Algorithm for QueueCore Processor
BSP/CGM Algorithm for Maximum Matching in Convex Bipartite Graphs
NUMA-Aware Dense Matrix Factorizations and Inversion with Look-Ahead on Multicore Processors
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP
Hybrid Task Scheduling: Integrating Static and Dynamic Heuristics
Energy Consumption and Scalability Evaluation for Software Transactional Memory on a Real Computing Environment
Detecting I/O Access Patterns of HPC Workloads at Runtime
Scalability of CPU and GPU Solutions of the Prime Elliptic Curve Discrete Logarithm Problem
Invasive Compute Balancing for Applications with Hybrid Parallelization
Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems
Memory Centric Computation (Mc2) for Large-Scale Graph Processing
Optimized Math Functions for a Fixed-Point DSP Architecture
PM2P: A Tool for Performance Monitoring of Message Passing Applications in COTS PC Clusters
Automatic aggregation of subtask accesses for nested OpenMP-style tasks
Three Hardware Implementations for the Binary Modular Exponentiation: Sequential, Parallel and Systolic
STOMP: Statistical Techniques for Optimizing and Modeling Performance of Blocked Sparse Matrix Vector Multiplication
Compact Hash Tables for High-Performance Traffic Classification on Multi-core Processors
Instruction Usage and the Memory Gap Problem
Global Data Re-allocation via Communication Aggregation in Chapel
Parallel Biological Sequence Comparison on Heterogeneous High Performance Computing Platforms with BSP++
Extension of a Task-Based Model to Functional Programming
Towards Seismic Wave Modeling on Heterogeneous Many-Core Architectures Using Task-Based Runtime System
HotStream: Efficient Data Streaming of Complex Patterns to Multiple Accelerating Kernels
A Dynamic Load Balance Algorithm for the S4 Parallel Stream Processing Engine
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation
Boosting Performance for I/O-Intensive Workload by Preemptive Job Migrations in a Cluster System
Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush
On the Memory Underutilization: Exploring Disaggregated Memory on HPC Systems
SPLG: A Tuned Signal Processing Library for GPU Architectures
Improved Computation of Database Operators via Vector Processing Near-Data
Function Outlining and Partial Inlining
Enabling microservices management for Deep Learning applications across the Edge-Cloud Continuum
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Exploring the Serverless First Strategy in Cloud Application Development
Parallel Strategies for the Execution of Top-k Queries with MaxScore on GPUs
Distributed Evidence Propagation in Junction Trees
FFT Optimizations and Performance Assessment Targeted towards Satellite and Airborne Radar Processing
Control Scheme for a CGRA
High Performance and Portable Convolution Operators for Multicore Processors
Performance Modeling and Estimation of a Configurable Output Stationary Neural Network Accelerator
Extending Heterogeneous Applications to Remote Co-processors with rOpenCL
Simulating Semiconductor Spectra Emissions in a PC Cluster
NeurOPar, A Neural Network-Driven EDP Optimization Strategy for Parallel Workloads
Synchronization Strategies on Many-Core SMT Systems
The Virtual Cluster: A Dynamic Environment for Exploitation of Idle Network Resources
Image Re-ranking Acceleration on GPUs
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package
Experiences with Disjoint Data Structures in a New Hardware Transactional Memory System
Revisiting a BSP/CGM Transitive Closure Algorithm
OpenCL Kernel Fusion for GPU, Xeon Phi and CPU
Easily Rendering Token-Ring Algorithms of Distributed and Parallel Applications Fault Tolerant
TMT - A TLB Tag Management Framework for Virtualized Platforms
Preliminary Experiments with XKaapi on Intel Xeon Phi Coprocessor
Applying Scheduling by Edge Reversal to Constraint Partitioning
Phase-Based Tasks Scheduling in Data Centers Powered Exclusively by Renewable Energy
An Image Processing VLIW Architecture for Real-Time Depth Detection
An Instruction-Set Extension to Support Approximate Multicore Processors
High Performance Communication System Based on Generic Programming
Sparbit: a new logarithmic-cost and data locality-aware MPI Allgather algorithm
A Task-based Execution Engine for Distributed Operating Systems Tailored to Lightweight Manycores with Limited On-Chip Memory
A Parallel Algorithm for Minimum Spanning Tree on GPU
Standalone Data-Center Sizing Combating the Over-Provisioning of the IT and Electrical Parts
27th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2015, Florianópolis, Brazil, October 17-21, 2015
Aggressive Value Prediction on a GPU
An Optimal Model for Optimizing the Placement and Parallelism of Data Stream Processing Applications on Cloud-Edge Computing
ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch
A new level-set analysis and sparse storage format for the SPTRSV in GPUs
Improving the Performance of Fog Computing Through the Use of Data Locality
Performance Tuning for GPU-Embedded Systems: Machine-Learning-Based and Analytical Model-Driven Tuning Methodologies
Exploring Novel Parallelization Technologies for 3-D Imaging Applications
A Selector of Grid Resources based on the Semantic Integration of Multiple Ontologies
15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 10-12 November 2003, Sao Paulo, Brazil
A Shared Memory SMC Sampler for Decision Trees
Generating Java Code for TINA Systems
A Novel Algorithm for Indirect Reputation-Based Grid Resource Management
Parallel Implementation of a Computational Model of the HIS Using OpenMP and MPI