yusuke1997/dblp-id-title huggingface dataset:
Property analysis and design understanding
Latency analysis of homogeneous synchronous dataflow graphs using timed automata
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
Row-shift decompositions for index generation functions
Binary Ring-LWE hardware with power side-channel countermeasures
Flow regulation for on-chip communication
MARTHA: architecture for control and emulation of power electronics and smart grid systems
CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Testable design of repeaterless low swing on-chip interconnect
Minimizing stand-by leakage power in static CMOS circuits
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors
Provably minimal energy using coordinated DVS and power gating
A Digital Test for First-Order [Sigma-Delta] Modulators
Towards a generic verification methodology for system models
Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks
Cone-based clustering heuristic for list-scheduling algorithms
Context-Aware Performance Analysis for Efficient Embedded System Design
GIS-based optimal photovoltaic panel floorplanning for residential installations
Building a better Boolean matcher and symmetry detector
Low-Latency Digital Feedback for Stochastic Quantum Calibration Using Cryogenic CMOS
An O(bn 2 ) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
Multi-output Functional Decomposition with Exploitation of Don't Cares
An overview of non-volatile memory technology and the implication for tools and architectures
Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space
Contract-based design of control protocols for safety-critical cyber-physical systems
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set
Dynamic Power Management for non-stationary service requests
Specifying and Evaluating Quality Metrics for Vision-based Perception Systems
Ultra-low energy circuit building blocks for security technologies
NBTI modeling in the framework of temperature variation
FSAF: File system aware flash translation layer for NAND Flash Memories
A framework for system reliability analysis considering both system error tolerance and component test quality
A static-placement, dynamic-issue framework for CGRA loop accelerator
A Convolutional Result Sharing Approach for Binarized Neural Network Inference
A Two-Tier Distributed Electronic Design Framework
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Advanced SIMD: Extending the reach of contemporary SIMD architectures
MoDNN: Local distributed mobile computing system for Deep Neural Network
Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme
Joint Sparsity with Mixed Granularity for Efficient GPU Implementation
Automated constraint-driven topology synthesis for analog circuits
Intermediate representations for controllers in chip generators
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology
Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses
A Novel Implementation of Tile-Based Address Mapping
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
Revisiting Persistent Hash Table Design for Commercial Non-Volatile Memory
Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's
Design with race-free hardware semantics
Process variation aware thread mapping for Chip Multiprocessors
Inductance analysis of on-chip interconnects [deep submicron CMOS]
Robust and flexible mapping for real-time distributed applications during the early design phases
State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems
An Interactive Router for Analog IC Design
Architecting high-speed command schedulers for open-row real-time SDRAM controllers
Synthesis of multilevel fault-tolerant combinational circuits
Automatic clock tree generation in ASIC designs
Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction
Multithreaded Synchronous Data Flow Simulation
Evaluating an Open-Source Hardware Approach from HDL to GDS for a Security Chip Design - a Review of the Final Stage of Project HEP
Pseudo-exhaustive word-oriented DRAM testing
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies
Expanding In-Cone Obfuscated Tree for Anti SAT Attack
Efficient Tensor Cores support in TVM for Low-Latency Deep learning
Feasibility Study and Benchmarking of Embedded MPC for Vehicle Platoons
Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems
Correlation-aware virtual machine allocation for energy-efficient datacenters
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic
Compact modeling and circuit-level simulation of silicon nanophotonic interconnects
Hardware/Software Partitioning using Integer Programming
Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs
Approximation Approach for Timing Jitter Characterization in Circuit Simulators
A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams
Neural networks for safety-critical applications - Challenges, experiments and perspectives
Formal verification of clock domain crossing using gate-level models of metastable flip-flops
Asynchronous Scheduling and Allocation
Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router Reuse
Considering Circuit Observability Don't Cares in CNF Satisfiability
Free MDD-Based Software Optimization Techniques for Embedded Systems
Automotive System Architectures (Automotive Special Day)
PP-HDC: A Privacy-Preserving Inference Framework for Hyperdimensional Computing
Modular FPGA Acceleration of Data Analytics in Heterogenous Computing
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis
Mechatronic system for energy efficiency in bus transport
Timing modeling for digital sub-threshold circuits
Reconfigurable Frequency Multipliers Based on Complementary Ferroelectric Transistors
Power reduction via near-optimal library-based cell-size selection
A synthesis-parameter tuning system for autonomous design-space exploration
An approximate voting scheme for reliable computing
Providing regulation services and managing data center peak power budgets
Towards Cross-Platform Inference on Edge Devices with Emerging Neuromorphic Architecture
Data Driven Power Optimization of Sequential Circuits
PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Multi-Partner Project: Enabling Digital Technologies for Holistic Health-Lifestyle Motivational and Assisted Supervision Supported by Artificial Intelligence Network (H2TRAIN)
Verifying UML/OCL models using Boolean satisfiability
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
Large-scale flip-chip power grid reduction with geometric templates
Real-time object detection towards high power efficiency
A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation
Moore meets maxwell
Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software
Improving the accuracy of support-set finding method for power estimation of combinational circuits
On the impact of on-chip inductance on signal nets under the influence of power grid noise
EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI
Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures
Cyclostationary feature detection on a tiled-SoC
Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT Networks
A new circuit simplification method for error tolerant applications
The programmable platform: does one size fit all?
Resource Optimization with 5G Configured Grant Scheduling for Real-Time Applications
Extended Abstract: Covert Channels and Data Exfiltration From FPGAs
Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems
LPVM: Low-Power Variation-Mitigant Adder Architecture Using Carry Expedition
Scalable stochastic processors
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms
EVX: Vector execution on low power EDGE cores
A SystemC-based Simulator for design space exploration of smart wireless systems
VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform
Feasibility exploration of NVM based I-cache through MSHR enhancements
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management
AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory
Optimized self-tuning for circuit aging
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation
On-chip network-enabled many-core architectures for computational biology applications
Reliability-Aware Quantization for Anti-Aging NPUs
Work in Progress: Linear Transformers for TinyML
IDDQ: you heard the hype, but what's really coming?
Real-time wireless communication in automotive applications
Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation
On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC
Magnetic tunnel junction enabled all-spin stochastic spiking neural network
On decomposing Boolean functions via extended cofactoring
SCFIT: A FPGA-based fault injection technique for SEU fault model
Linear programming approach for performance-driven data aggregation in networks of embedded sensors
Priority assignment for event-triggered systems using mathematical programming
Preface (Frontmatter, Table of Contents, Preface)
Programming Shared Memory Multiprocessors with Deterministic Message-Passing Concurrency: Compiling SHIM to Pthreads
Contract-Based Quality-of-Service Assurance in Dynamic Distributed Systems
Impact of resource sharing on performance and performance prediction
A Demonstration of Co-Design and Co-Verification in a Synchronous Language
Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor
EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis
An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion
Multi-sensor configurable platform for automotive applications
Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks
Structure optimizations of neuromorphic computing architectures for deep neural network
A sophisticated memory test engine for LCD display drivers
Effective post-silicon failure localization using dynamic program slicing
On effective flip-chip routing via pseudo single redistribution layer
Sub-threshold logic circuit design using feedback equalization
Autosymmetry of Incompletely Specified Functions
Practical Causality Handling for Synchronous Languages
A Complete Network-On-Chip Emulation Framework
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling
Semantic Integration Platform for Cyber-Physical System Design
Optimization of quantum computer architecture using a resource-performance simulator
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
AFRA: A low cost high performance reliable routing for 3D mesh NoCs
Redressing timing issues for speed-independent circuits in deep submicron age
Program transformations in the POLCA project
Time- and angle-triggered real-time kernel
Specification and Validation of Distributed IP-Based Designs with JavaCAD
Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation
Using Speculative Functional Units in high level synthesis
Cache aware compression for processor debug support
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs
Repartitioning and Technology-Mapping of Electronic Hybrid Systems
Eliminating speed penalty in ECC protected memories
Associative skew clock routing for difficult instances
Multi-Partner Project: Sports Performance and Health Assessment in the DistriMuse Project
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions
Approximate Random Dropout for DNN training acceleration in GPGPU
C/C++: progress or deadlock in system-level specification
Self-aware cyber-physical systems and applications in smart buildings and cities
Fast cache simulation for host-compiled simulation of embedded software
Towards a Formal Model of Recursive Self-Reflection
Global optimization of integrated transformers for high frequency microwave circuits using a Gaussian process based surrogate model
LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio
PAIS: Parallelization aware instruction scheduling for improving soft-error reliability of GPU-based systems
Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph Isomorphism
A 101 TOPS/W and 1.73 TOPS/mm 2 6T SRAM-Based Digital Compute-in-Memory Macro Featuring a Novel 2T Multiplier
Contrasting a NoC and a traditional interconnect fabric with layout awareness
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits
Data-Driven Electrostatics Analysis based on Physics-Constrained Deep learning
Multi-Partner Project: Securing Future Edge-AI Processors in Practice (CONVOLVE)
Circuit Design and Design Automation for Printed Electronics
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration
PURSE: Property Ordering Using Runtime Statistics for Efficient Multi - Property Verification
A Dynamic Model for the State Assignment Problem
Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis
A symbolic methodology for the verification of analog and mixed signal designs
Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks
Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis
PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel Environments
Adaptive approximation in arithmetic circuits: A low-power unsigned divider design
Bytecode-to-C ahead-of-time compilation for Android Dalvik virtual machine
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
Leakage aware energy minimization for real-time systems under the maximum temperature constraint
Energy-Aware Adaptive Checkpointing in Embedded Real-Time Systems
K*BMDs: A New Data Structure for Verification
Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device
Library Functions Timing Characterization for Source-Level Analysis
Design optimization of photovoltaic arrays on curved surfaces
Learning to Floorplan like Human Experts via Reinforcement Learning
A symbolic technique for automated characterization of the uniqueness and similarity of analog circuit design features
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms
Design and integration of hierarchical-placement multi-level caches for real-time systems
A New Effective And Efficient Multi-Level Partitioning Algorithm
A thermal stress-aware algorithm for power and temperature management of MPSoCs
Parametric Throughput Analysis of Synchronous Data Flow Graphs
TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators
Optimization of error detecting codes for the detection of crosstalk originated errors
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor
Designing inexact systems efficiently using elimination heuristics
AUTOSAR basic software for complex control units
A Sequential Detailed Router for Huge Grid Graphs
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing
Dimensioning heterogeneous MPSoCs via parallelism analysis
GALS synthesis and verification for xMAS models
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit
Error resilience and energy efficiency: An LDPC decoder design study
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache
Optimized out-of-order parallel discrete event simulation using predictions
Security-aware development of cyber-physical systems illustrated with automotive case study
A monolithic off-chip IDDQ monitor
A Fast Optimal Robust Path Delay Fault Testable Adder
Parallel X-fault simulation with critical path tracing technique
Time-critical computing on a single-chip massively parallel processor
RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment
Optimized integration of test compression and sharing for SOC testing
On Applying Incremental Satisfiability to Delay Fault Testing
HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms
Library mapping for memories
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters
An embedded offset and gain instrument for OpAmp IPs
Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context
Tango: An Optimizing Compiler for Just-In-Time RTL Simulation
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits
COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards
Data Reuse Exploration Techniques for Loop-Dominated Application
Architectural Rule Checking for High-level Synthesis
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory
Dataflow Optimized Reconfigurable Acceleration for FEM-Based CFD Simulations
The influence of real-time constraints on the design of FlexRay-based systems
SPPS: Secure Policy-based Publish/Subscribe System for V2C Communication
Hierarchical Adaptive Dynamic Power Management
Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCs
Energy efficient neural networks for big data analytics
Dynamic energy burst scaling for transiently powered systems
Formal Analysis of Timing Diversity for Autonomous Systems
Targeting code diversity with run-time adjustable issue-slots in a chip multiprocessor
Anomaly Detection and Classification to enable Self-Explainability of Autonomous Systems
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits
Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators
An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification
A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool
Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes *
CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection
OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring
Digital Twin Extension with Extra-Functional Properties
HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation
High-Performance Data Mapping for BNNs on PCM-Based Integrated Photonics
An Efficient Method for the Self-Consistent Electro-Thermal Simulation and its Integration into a CAD Framework
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Increasing Register File Immunity to Transient Errors
A Baseline Framework for the Qualification of LTL Specification Miners
Optimization techniques for craig interpolant compaction in unbounded model checking
Proteus : HLS-based NoC Generator and Simulator
Can Machine Learn Pipeline Leakage?
A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model
EMC-driven midway routing on PCBs
Wave Steered FSMs
Efficient test-data compression for IP cores using multilevel Huffman coding
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction
Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application
Verifying synchronous reactive systems using lazy abstraction
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring
Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches
Energy-efficient cache design in emerging mobile platforms: the implications and optimizations
Exploring pausible clocking based GALS design for 40-nm system integration
Taking one-to-one mappings for granted: Advanced logic design of encoder circuits
Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri Nets
Time-Energy Design Space Exploration for Multi-Layer Memory Architectures
ARTM: a lightweight fork-join framework for many-core embedded systems
TrueView: A LIDAR Only Perception System for Autonomous Vehicle (Interactive Presentation)
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines
Heuristic datapath allocation for multiple wordlength systems
MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting
Compatibility Checking for Autonomous Lane-Changing Assistance Systems
On the Impact of Warpage on BEOL Geometry and Path Delays in Fan-out Wafer-Level Packaging
System level clock tree synthesis for power optimization
Path-based scheduling in a hardware compiler
Gate replacement techniques for simultaneous leakage and aging optimization
Failure analysis of a network-on-chip for real-time mixed-critical systems
Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification
Instruction-set customization for real-time embedded systems