yusuke1997/dblp-id-title huggingface dataset:
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits
RASoC: A Router Soft-Core for Networks-on-Chip
TRAM: A tool for Temperature and Reliability Aware Memory Design
Opportunistic write for fast and reliable STT-MRAM
Complete and Efficient Verification for a RISC-V Processor Using Formal Verification
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application
Testable design for advanced serial-link transceivers
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
Self-suspension real-time tasks under fixed-relative-deadline fixed-priority scheduling
Detecting errors using multi-cycle invariance information
ArChiVED: Architectural checking via event digests for high performance validation
Combinational Verification based on High-Level Functional Specifications
HIT: A Hidden Instruction Trojan Model for Processors
RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature
Logical equivalence checking of asynchronous circuits using commercial tools
A BIST Scheme for On-Chip ADC and DAC Testing
coxHE: A software-hardware co-design framework for FPGA acceleration of homomorphic computation
Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems
Buffer space optimisation with communication synthesis and traffic shaping for NoCs
3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D Integration
PIMProf: An Automated Program Profiler for Processing-in-Memory Offloading Decisions
Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard
A compact model to identify delay faults due to crosstalk
Multiphysics Design and Simulation Methodology for Dense WDM Silicon Photonics
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques
Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon
Semantic driven hierarchical learning for energy-efficient image classification
RemapCom: Optimizing Compaction Performance of LSM Trees via Data Block Remapping in SSDs
Embedded tutorial: TRP: integrating embedded test and ATE
A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric
Gate Level Fault Diagnosis in Scan-Based BIST
Defect-oriented test methodology for complex mixed-signal circuits
OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy
Formal Methods in System and MpSoC Performance Analysis and Optimisation
Efficient Identification of Critical Faults in Memristor Crossbars for Deep Neural Networks
Light NUCA: A proposal for bridging the inter-cache latency gap
Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid
Efficient analysis of variability impact on interconnect lines and resistor networks
Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores
A robust authentication methodology using physically unclonable functions in DRAM arrays
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL
Efficient code density through look-up table compression
Efficient Training on Edge Devices Using Online Quantization
Test generation for combinational quantum cellular automata (QCA) circuits
BEAM: A Multi-Channel Optical Interconnect for Multi-GPU Systems
The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization
Accuracy-Adaptive Simulation of Transaction Level Models
Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator
A Novel Metric for Interconnect Architecture Performance
Exact DAG-Aware Rewriting
Comprehensive analysis of software countermeasures against fault attacks
MPSoCs run-time monitoring through Networks-on-Chip
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem
Disclosing the LDPC code decoder design space
Embedded Diagnosis IP
FPGA synthesis for minimum area, delay and power
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
System Synthesis for Networks of Programmable Blocks
Adaptive least mean square behavioral power modeling
ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects
Decentralizing IoT Data Processing: The Rise of Blockchain-Based Solutions
AURIX TC277 Multicore Contention Model Integration for Automotive Applications
Directed test generation using concolic testing on RTL models
ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization
Metastability challenges for 65nm and beyond: simulation and measurements
H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations
Time Domain Multiplexed TAM: Implementation and Comparison
OpenMP and timing predictability: a possible union?
Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC)
Towards Implementing RTL Microprocessor Agile Design Using Feature Oriented Programming
Sequential Logic Encryption Against Model Checking Attack
Path selection based acceleration of conditionals in CGRAs
VHDL Modelling and Analysis of Fault Secure Systems
A Design-for-Diagnosis Technique for SRAM Write Drivers
Code generation for embedded heterogeneous architectures on android
Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things
Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack
DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures
Adaptive Transient Leakage-Aware Linearised Model for Thermal Analysis of 3-D ICs
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction
BenQ: Benchmarking Automated Quantization on Deep Neural Network Accelerators
Modeling and Verifying Uncertainty-Aware Timing Behaviors using Parametric Logical Time Constraint
A Method of Via Variation Induced Delay Computation
A Dependability-Driven System-Level Design Approach for Embedded Systems
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices
Temperature-aware software-based self-testing for delay faults
Towards thermally-aware design of 3D MPSoCs with inter-tier cooling
Testing TSV-based three-dimensional stacked ICs
Time and memory tradeoffs in the implementation of AUTOSAR components
Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Extending the lifetime of NAND flash memory by salvaging bad blocks
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit
A practical testing framework for isolating hardware timing channels
AFEC: An analytical framework for evaluating cache performance in out-of-order processors
Joint Power Management of Memory and Disk
Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets
Minimal Length Diagnostic Tests for Analog Circuits using Test History
Online scheduling for multi-core shared reconfigurable fabric
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
Minimizing peak temperature for pipelined hard real-time systems
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture
Layout-Oriented Synthesis of High Performance Analog Circuits
Slack budgeting and slack to length converting for multi-bit flip-flop merging
LoADM: Load-Aware Directory Migration Policy in Distributed File Systems
A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems
Real-time communication analysis for Networks-on-Chip with backpressure
Energy-Aware Routing for E-Textile Applications
MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution
An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions
PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment
Fault insertion testing of a novel CPLD-based fail-safe system
Probabilistic schedulability analysis for fixed priority mixed criticality real-time systems
Distance-guided hybrid verification with GUIDO
Hardware Synthesis from C/C++ Models
Shared Cache Analysis Under Preemptive Scheduling
Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography
Enhanced design of filterless class-D audio amplifier
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate
SealPK: Sealable Protection Keys for RISC-V
Speculative reduction-based scalable redundancy identification
Power management verification experiences in Wireless SoCs
A co-design approach for embedded system modeling and code generation with UML and MARTE
AHEAD: automated framework for hardware accelerated iterative data analysis
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches
A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems
Adaptive Perception Control for Aerial Robots with Twin Delayed DDPG
Synthesis of I DDQ -testable circuits: integrating built-in current sensors
Perceptual quality preserving SRAM architecture for color motion pictures
Accelerating graph computation with racetrack memory and pointer-assisted graph representation
Recursion-driven parallel code generation for multi-core platforms
Integration, cooling and packaging issues for aerospace equipments
The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures
Combining simulation and formal methods for system-level performance analysis
Architecture driven k-way partitioning for multichip modules
Transition-Time-Relation based capture-safety checking for at-speed scan test generation
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores
Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitations
Improvement of Mixed Track - Height Standard-Cell Placement
SEERAD: A high speed yet energy-efficient rounding-based approximate divider
Verification of Embedded Memory Systems using Efficient Memory Modeling
Why design must change: Rethinking digital design
Reliability aware through silicon via planning for 3D stacked ICs
APUF Production Line Faults: Uniqueness and Testing
Decomposition of logic functions for minimum transition activity
MNSIM: Simulation platform for memristor-based neuromorphic computing system
Stimuli Generation with Late Binding of Values
Towards Scalable GPU System with Silicon Photonic Chiplet
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms
From Gates to SDCs: Understanding Fault Propagation Through the Compute Stack
Neighbor Oblivious Learning (NObLe) for Device Localization and Tracking
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors
A SystemC-Based Verification Methodology for Complex Wireless Software IP
Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study
A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications
Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems
Xray: Detecting and Exploiting Vulnerabilities in Arm AXI Interconnects
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
Exploiting CPU-load and data correlations in multi-objective VM placement for geo-distributed data centers
Warm-Boot Attack on Modern DRAMs
Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration
IOMMU Deferred Invalidation Vulnerability: Exploit and Defense
An environment for controlled experiments with in-house sensor networks
A design-space exploration for allocating security tasks in multicore real-time systems
A DRAM-Based Processing-in-Memory Accelerator for Privacy-Protecting Machine Learning
Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications
Quantitative Productivity Measurement in IC Design
Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified Dielectrics
High performance single supply CMOS inverter level up shifter for multi: supply voltages domains
Hardware Trojans in Emerging Non-Volatile Memories
Cache-aware task scheduling for maximizing control performance
REDCAP: Reconfigurable RFET-Based Circuits Against Power Side-Channel Attacks
A multi banked - Multi ported - Non blocking shared L2 cache for MPSoC platforms
All things are connected
Inductor optimization for active cell balancing using geometric programming
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs
Organizing Libraries of DFG Patterns
Securing conditional branches in the presence of fault attacks
A Variation Aware High Level Synthesis Framework
RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement
Panel: Future SoC verification methodology: UVM evolution or revolution?
Ultra low-power visual odometry for nano-scale unmanned aerial vehicles
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources
Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky Factor
Low-voltage organic transistors for flexible electronics
Modeling manufacturing process variation for design and test
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
AVF-driven parity optimization for MBU protection of in-core memory arrays
On GPU bus power reduction with 3D IC technologies
Dynamic Power Management of Laptop Hard Disk
TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-Tables
Brain-inspired computing with spin torque devices
Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations
KAST: K-associative sector translation for NAND flash memory in real-time systems
Adaptive voltage over-scaling for resilient applications
End-to-End Latency Optimization of Thread Chains Under the DDS Publish/Subscribe Middleware
ORIENT: Organized interleaved ECCs for new STT-MRAM caches
Dynamic thermal management in 3D multi-core architecture through run-time adaptation
An elastic mixed-criticality task model and its scheduling algorithm
At-Speed Testing of SOC ICs
Security in the Internet of Things: A challenge of scale
An efficient network on-chip architecture based on isolating local and non-local communications
Precise WCET calculation in highly variant real-time systems
Towards a formal semantics for the AADL behavior annex
Transient fault prediction based on anomalies in processor events
Counteract Side-Channel Analysis of Neural Networks by Shuffling
Automatic Generation of Validation Stimuli for Application-Specific Processors
EDA tools trust evaluation through security property proofs
High-level synthesis of gracefully degradable ASICs
Late Breaking Results: Energy-Efficient Printed Machine Learning Classifiers with Sequential SVMs
Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks
Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload
SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels
Pipelined data parallel task mapping/scheduling technique for MPSoC
Understanding the role of buildings in a smart microgrid
Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip
Managing a Reconfigurable Processor in a General Purpose Workstation Environment
Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit
Thermal management of manycore systems with silicon-photonic networks
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
The federated scheduling of constrained-deadline sporadic DAG task systems
Low-power embedded system for real-time correction of fish-eye automotive cameras
Design, Automation & Test in Europe Conference, DATE 2025, Lyon, France, March 31 - April 2, 2025
A reconfigurable, pipelined, conflict directed jumping search SAT solver
Simulated Annealing Algorithm with Multi-Molecule: An Approach to Analog Synthesis
Algorithm-Hardware Co-Design of a Unified Accelerator for Non-Linear Functions in Transformers
Carbon nanotube circuits: opportunities and challenges
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results
QuteSAT: a robust circuit-based SAT solver for complex circuit structure
Circuit models for the co-simulation of superconducting quantum computing systems
Bitstream- Level Interconnect Fault Characterization for SRAM-based FPGAs
Simulation-based reusable posynomial models for MOS transistor parameters
In-situ Tuning of Printed Neural Networks for Variation Tolerance
Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons
Effective resource management towards efficient computing
Communication Mechanisms for Parallel DSP Systems on a Chip
Strategies for initial sizing and operating point analysis of analog circuits
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge
TruncApp: A truncation-based approximate divider for energy efficient DSP applications
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture
Fine-grain OpenMP runtime support with explicit communication hardware primitives
ReliNoC: A reliable network for priority-based on-chip communication
Queue Based Memory Management Unit for Heterogeneous MPSoCs
Model Checking is Possible to Verify Large-scale Vehicle Distributed Application Systems
Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks
Algebraic Support for Transformational Hardware Allocation
Realistic performance-constrained pipelining in high-level synthesis
Verifying Clock Schedules in the Presence of Cross Talk
An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification
Practical Substrate Design Considering Symmetrical and Shielding Routes
Discrete Samplers for Approximate Inference in Probabilistic Machine Learning
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS
Is "Network" the next "Big Idea" in design?
Reliability-aware mapping optimization of multi-core systems with mixed-criticality
Circuit carving: A methodology for the design of approximate hardware
PANEL SESSION - Is the second wave of HLS the one industry will surf on?
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems
A logic integrated optimal pin-count design for digital microfluidic biochips
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer
Cross-layer design of reconfigurable cyber-physical systems
Poor Man's TBR: A Simple Model Reduction Scheme
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach
Increasing PCM main memory lifetime
Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor System
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
System-level scheduling of real-time streaming applications using a semi-partitioned approach
On safety assurance case for deep learning based image classification in highly automated driving
Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
Generalized reasoning scheme for redundancy addition and removal logic optimization
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges
Impact of bit-width specification on the memory hierarchy for a real-time video processing system
A System Level Performance Evaluation for Superconducting Digital Systems
A Secure Web-Based Framework for Electronic System Level Design
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits
Electrostatics-Based Analytical Global Placement for Timing Optimization
Block convolution: Towards memory-efficient inference of large-scale CNNs on FPGA
Data Type Analysis for Hardware Synthesis from Object-Oriented Models
A Design Automation Roadmap for Europe Panel discussion
On applying the set covering model to reseeding
A Crosstalk Aware Interconnect with Variable Cycle Transmission
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control
Accounting for cache-related preemption delay in dynamic priority schedulability analysis
Error rate reduction in DNA self-assembly by non-constant monomer concentrations and profiling
Simulating preemptive scheduling with timing-aware blocks in Simulink
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip
Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees
TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs
PECAN: A Product-Quantized Content Addressable Memory Network
Fast and Accurate Wire Timing Estimation Based on Graph Learning
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications
Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes
Computing-in-memory with spintronics
Integrated CMOS receiver for wearable coil arrays in MRI applications
Common Reusable Verification Environment for BCA and RTL Models
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering
Over-approximating loops to prove properties using bounded model checking
SoC in Nanoera: Challenges and Endless Possibility
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC