yusuke1997/dblp-id-title huggingface dataset:
Computer-aided Design of RF Communication Systems: Techniques and Challenges
A PMOS-diode Differential Body-driven Offset compensated 0.5V
A Design of Analog C-Matrix Circuits Used for Signal/Data Processing
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation
A C-testable modified Booth's array multiplier
Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique
Accelerating U-Net: A Patchwise Memory Optimization Approach for Image Segmentation
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs
Worst-Case Crosstalk Noise Analysis Based on Dual-Exponential Noise Metrics
Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver
Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays
Transistor Flaring in Deep Submicron-Design Considerations
I DDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests
Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits
A CAD Tool for Design of On-Chip Store & Generate Scheme
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
Energy-Efficient Compressed Address Transmission
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning
Invited Talk: Embedded Test for Systems-on-a-Chip
Efficient Verification and Synthesis using Design Commonalities
T2: HW-SW Codesign
A Modified Hill Climbing Based Watershed Algorithm and Its Real Time FPGA Implementation
Towards a Real-Time Campus-Scale Water Balance Monitoring System
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone
A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design Issues
High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors
High-level Synthesis of Multi-process Behavioral Descriptions
A Low Power Floating Point Accumulator
Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches
An Efficient Hardware Implementation of Canny Edge Detection Algorithm
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling
SoC Synthesis with Automatic Hardware Software Interface Generation
An Experimental Demonstration of Neuronal Somatic Behavior Using 2D SnS Memristive Switching Characteristics and its Equivalent Circuit for Spiking Neural Network
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
StateLock: State Transition Based Logic Locking for Sequential Circuits
Design of Reversible Finite Field Arithmetic Circuits with Error Detection
VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images
Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview
A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts
A 0.6 mW 1.6 dB Noise Figure Inductorless Shunt Feedback Wideband LNA With Gm Enhancement and Current Reuse in 65 nm CMOS
Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification
A Vision for the Broadband Network
Statistical Analysis of Controllability
TRANSPOSE: Circuit Transformations for Power Side-Channel Security at Register Transfer Level
A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis
An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation
Low-cost DC built-in self-test of linear analog circuits using checksums
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Memristor-based High Speed and Area Efficient Comparators in IMPLY Logic
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment
On Physical-Aware Synthesis of Vertically Integrated 3D Systems
Ensuring On-Die Power Supply Robustness in High-Performance Designs
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis
Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit Operation
Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations
A Galois Field Based Logic Synthesis Approach with Testability
VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009
Performance and Functional Verification of Microprocessors
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits
Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy Estimation
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
Design Planning for Uniform Thermal Distribution
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs
PODIA: Power Optimization through Differential Imbalanced Amplifier
Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology
Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing
A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability
Current DAC Based -40dB PSRR Configurable Output LDO in BCD Technology
A Robust and Reconfigurable Multi-mode Power Gating Architecture
A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors
Cellular Automata Based Test Structures with Logic Folding
Architecture Exploration for Low Power Design
Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative Technique
A Behavioral Fault Simulator For Ideal
Bipartitioning for Hybrid FPGA-Software Simulatio
Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback
A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi using a 130 nm SOI CMOS Technology
Logic Design of Asynchronous Circuits (Tutorial Abstract)
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
Synthesis & Testing for Low Power
Behavioral Modeling of an ATM Switch using SpecCharts
Apriori Formal Coverage Analysis for Protocol Properties
Creating Fastest Self timing Reference Path for High Speed Memory Designs
Application of Alpha Power Law Models to PLL Design Methodology
An Efficient Transition Detector Exploiting Charge Sharing
A Combinational Logic Mapper for Actel's SX/AX Family
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
A Partition Approach to Find the Length of the Longest Common Subsequence
ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment
Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design
Evaluation of Various Routing Architectures for Multi-FPGA Boards
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs
Accelerating Embedded System Design
Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics
Enhanced TED: A New Data Structure for RTL Verification
Non-Manhattan Routing Using a Manhattan Router
A Novel Scheme to Reset through Clock
Behavioral Synthesis of Complex Parallel Controllers
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement
On Common-Mode Skewed-Load and Broadside Tests
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
A Study of Power Supply Variation as a Source of Random Noise
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications
T4: Verification
Combination of Structural and State Analysis for Partial Scan
A Novel Approach to Design BCD Adder and Carry Skip BCD Adder
Via Minimization in Channel Routing by Layout Modification
A Time-Based Low Voltage Body Temperature Monitoring Unit
hbcLock: Encrypted RF Communication Utilizing Body-Coupled Keys for the Internet of Bodies
IEEE Market-Oriented Standards Process and the EDA Industry
Mobile Communications: Demands on VLSI Technology, Design and CAD
Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects
A New Partitioning Strategy Based on Supermodular Functions
An Improved Cost Heuristic for Transistor Sizing
Program Slicing for ATPG-Based Property Checking
Keynote Talk: Semiconductor Industry: Best of Times, Worst of Times, and Nowhere Else I Would Rather Be!
On More Efficient Combinational ATPG Using Functional Learning
Mapping and Scheduling for Architecture Exploration of Networking SoCs
Formal Verification of Digital Systems
All-SAT Using Minimal Blocking Clauses
Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICs
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm
Extraction and Analysis of Mobility in Double Gate Junctionless Transistor
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
Statistical path delay fault coverage estimation for synchronous sequential circuits
Test Techniques and Trade-offs for Embedded Cores and Systems
Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design
A New Accurate and Efficient Timing Simulator
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs
An Array Architecture for Computing KLT Basis Vectors
EvoDeb: Debugging Evolving Hardware Designs
Sequential Circuits with combinational Test Generation Complexity
CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy
Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?
Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures
nterface Synthesis: Issues and Approaches
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
GRILAPE: Graph Representation Inductive Learning-based Average Power Estimation for Frontend ASIC RTL Designs
Theory and Applications of Cellular Automata for VLSI Design and Testing
3-D Parasitic Modeling for Rotary Interconnects
Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier
A low-power resistive tail dynamic comparator with self-shut mechanism
Exploring Logic Block Granularity in Leakage Tolerant FPGA
Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core
Self-Organization and its Application to Binding
Coping with Variations through System-Level Design
Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs
Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model
A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting Systems
Encoding of Floorplans through Deterministic Perturbation
HISCOAP: a hierarchical testability analysis tool
Closed Form Expression of Input Matching of a Wideband Single-Ended to Differential LNA
Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication
A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI Robustness
Graphical Methodology Language for CAD Frameworks
Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise
Jitter Estimation Methodology for Clock Chips
Analysis of Design Methodology with Logic Cell Arrays
8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks
Demystifying Time Varying Circuits and Systems
A Novel Low Power Ternary Multiplier Design using CNFETs
A VLSI architecture for cellular automata based parallel data compression
Panel: Challenges for Future Systems on a Chip
High Speed Digital Filtering on SRAM-Based FPGAs
Low-Cost Production Testing of Wireless Transmitters
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions
High Level Synthesis Of Multi-Precision Data Flow Graphs
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath
Clocking-Based Coplanar Wire Crossing Scheme for QCA
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core
Self-Powered IoT Device for Indoor Applications
Design Verification and Functional Testing of FiniteState Machines
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging
Mixed-Signal Design for Test
Behavioral Array Mapping into Multiport Memories Targeting Low Power
IDDQ-Testability of Tree Circuits
GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes
Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors
ReConfigurable Technologies
Empirical Computation of Reject Ratio in VLSI Testing
Simulation Based Verification using Temporally Attributed Boolean Logic
Physical Design Trends and Layout-Based Fault Modeling
Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration
A Versatile BIST Technique Combining Test Registers and Accumulators
Design of t-UED/AUED Codes from Berger's AUED Code
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
Reset Careabouts in a SoC Design
Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices
Optimal algorithms for planar over-the-cell routing in the presence of obstacles
Hardware Accelerator for Dual Standard Deblocking Filter
Efficient Mitigation of DRAM Row Buffer Conflict Using Request Clustering in Manycore Systems
Design of a highly reconfigurable interconnect for array processors
A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases
Arbitrary Precision Arithmetic - SIMD Style
Bridging the Gap between Asynchronous Design and Designers
A Framework for a Parallel Architecture Dedicated to Soft Computing
Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance
Message from the Tutorial Co-Chairs
Hardware implementation of Ring-LWE lattice cryptography with BCH and Gray coding based error correction
Systolic Arithmetic Architectures
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss
Tutorial IND2B: Structured Embedded Configuration and Test
Using Tweaks to Design Fault Resistant Ciphers
Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFET
ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems
MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults
Digital Testing of ICs for Automotive Applications
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes
Image Compression Using 2D-Discrete Wavelet Transform on a Light Weight Reconfigurable Hardware
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip
19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity
Autonomous Automotives on the Edge
Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition
Processing and Scheduling Components in an Innovative Network Processor Architecture
Reducing Design Verification Cycle Time through Testbench Redundancy
Performance Considerations in Embedded DSP based System-On-a-Chip Designs
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems
Net Clustering Based Macrocell Placement
Comparison of Off-Chip Training Methods for Neuromemristive Systems
A Low-Power Wireless Camera System
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors
VLSI Implementation of Modulo Multiplication Using Carry Free Addition
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications
A VLSI Architecture of an Inverse Discrete Cosine Transform
Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis
A Library Development Framework for a Coarse Grain Reconfigurable Architecture
Decomposition Strategies and their Performance in Fpga-Based Technology Mapping
Modeling, Fabrication and Investigation of Mixing in Low-Cost Passive PDMS Micromixers
Process Disturbance Analyzer for Nuclear Reactors
A fast algorithm to test planar topological routability
Capturing the Effect of Crosstalk on Delay
Development of a Wireless Integrated Toxic and Explosive MEMS Based Gas Sensor
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology
Driving Analog Mixed Signal Verification through Verilog-AMS
On Design and Implementation of an Embedded Automatic Speech Recognition System
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits
A Process Scheduler-Based Approach to NoC Power Management
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration
(Quasi-) Linear Path Delay Fault Tests for Adders
A Method for Synthesizing Area Efficient Multilevel PTL Circuits
A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field
Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components
Dynamic Power Optimization Based on Formal Property Checking of Operations
TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface
A Methodology for Generating Application Specific Tree Multipliers
Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors
Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality
MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster Convergence
Power Side Channel Resistance of RNS Secure Logic
Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs
Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA Platform
Interpreting and Extending an Analytical Battery Model Using an Iterative Computation Method
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
A 2Kx1K Space Switch ASIC for Use in Digital Exchanges
Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management
Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems
Applying Modified Householder Transform to Kalman Filter
Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation
Design for Verification at the Register Transfer Level
FRoZN: Fault-Tolerant Routing Technique Using Reinforcement Learning for ZMesh NoC
Next Generation Network Processors
Rapid Technology Projection for High-Level Synthesis
An Amalgamated Testability Measure Derived from Machine Intelligence
A Novel Strategy to Test Core Based Designs
Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment
Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures
Call for Participation: 10th IEEE VLSI Design & Test Symposium
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
An Efficient Rule Based Fault Simulator
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs
A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications
A General Approach to High-Level Energy and Performance Estimation in SoCs
MERGERS: Multi-Access Edge Resource Governance for Real-Time SaaS Systems
Response Pipelined CAM Chips: The First Generation and Beyond
Quantifying the Efficacy of Logic Locking Methods
A Bist PLA Design for High Fault Coverage and Testing by an Interleavingly Crosspoint Counting
21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India
Path Delay Testing: Variable-Clock Versus Rated-Clock
Estimating the Complexity of Synthesized Designs from FSM Specifications
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology
A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET
Embedded Systems Design Conference History
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
On test coverage of path delay faults
Dynamic Noise Analysis with Capacitive and Inductive Coupling
High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique
Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs
Input Space Adaptive Embedded Software Synthesis
Manufacturability of Mixed Signal Systems
Recovery-Based Real-Time Static Scheduling for Battery Life Optimization
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths
10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
Rapid Embedded Hardware/Software System Generation
CACOP - A Random Pattern Testability Analyzer
RISC-V Based Secure Processor Architecture for Return Address Protection
Architecture for Blocking Detection in Wireless Video Source Authentication
A Tuturial on the Emerging Nanotechnology Devices
An ASIC Implementation of Kohonen's Map Based Color Image Compression
CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber