yusuke1997/dblp-id-title huggingface dataset:
A Sound and Complete Algorithm to Identify Independent Variables in a Reactive System Specification
Generalized Matrix Factorization Techniques for Approximate Logic Synthesis
SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators
From transistors to MEMS: Throughput-aware power gating in CMOS circuits
A Linear-Centric Simulation Framework for Parametric Fluctuations
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories
Exploring the limits of phase change memories
Genetic/bio design automation for (re-)engineering biological systems
Cost-aware capacity optimization in dynamic multi-hop WSNs
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets
FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories
A case study on the application of real phase-change RAM to main memory subsystem
Full Scan Fault Coverage With Partial Scan
Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA
Power-constrained test scheduling for multi-clock domain SoCs
Hardware-assisted Detection of Malware in Automotive-Based Systems
A landscape of the new dark silicon design regime
Dynamic code overlay of SDF-modeled programs on low-end embedded systems
On multiplexed signal tracing for post-silicon debug
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware
Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns
Next Generation Arithmetic for Edge Computing
Self-triggered controllers and hard real-time guarantees
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family
Using Machine Learning for Quality Configurable Approximate Computing
Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study
BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from Scratch
Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks
Experimentally driven verification of synthetic biological circuits
A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories
Test Planning and Design Space Exploration in a Core-Based Environment
An Effective and Efficient Cross-Link Insertion for Non-Tree Clock Network Synthesis
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
A new design-for-test technique for SRAM core-cell stability faults
What designs for coming supercomputers?
Merged Computation for Whirlpool Hashing
Spintronic memristor based temperature sensor design with CMOS current reference
Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links
An indoor localization system to detect areas causing the freezing of gait in Parkinsonians
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis
Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Top-down heterogeneous synthesis of analog and mixed-signal systems
Low power design on algorithmic and architectural level: a case study of an HSDPA baseband digital signal processing system
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing
A case for multi-channel memories in video recording
Fast Evaluation of Protocol Processor Architectures for IPv6 Routing
Silicon Debug of Systems-on-Chips
SLC: Memory Access Granularity Aware Selective Lossy Compression for GPUs
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural Network
Application of Formal Methods (SAT/SMT) to the Design of Constrained Codes
The schedulability region of two-level mixed-criticality systems based on EDF-VD
1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996
Managing Don't Cares in Boolean Satisfiability
RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 µs Collision Detection
A score-based classification method for identifying hardware-trojans at gate-level netlists
Sub-quadratic objectives in quadratic placement
CR-Spectre: Defense-Aware ROP Injected Code-Reuse Based Dynamic Spectre
A memory- and time-efficient on-chip TCAM minimizer for IP lookup
Using MaxBMC for Pareto-optimal circuit initialization
Control-quality driven design of cyber-physical systems with robustness guarantees
An automatic tool flow for the combined implementation of multi-mode circuits
Steady State Calculation of Oscillators Using Continuation Methods
Multi-Partner Project: Safe, Secure and Dependable Multi-UAV Systems for Search and Rescue Operations
FPGA Acceleration of Protein Back-Translation and Alignment
An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
Performance analysis of greedy shapers in real-time systems
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
Power consumption of logic circuits in ambipolar carbon nanotube technology
Formal probabilistic analysis of distributed dynamic thermal management
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application
Technology mapping flow for emerging reconfigurable silicon nanowire transistors
A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments
Large-scale Boolean matching
Generic Sample Preparation for Different Microfluidic Platforms
Resistive memories: Which applications?
Optimisation of mutually exclusive arithmetic sum-of-products
RTOS-aware refinement for TLM2.0-based HW/SW designs
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC
MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms
Low-g accelerometer fast prototyping for automotive applications
Towards general purpose computations on low-end mobile GPUs
Hybrid adaptive clock management for FPGA processor acceleration
Learning Circuit Placement Techniques Through Reinforcement Learning with Adaptive Rewards
Systems on Chips Design: System Manufacturer Point of View
DFPC: A dynamic frequent pattern compression scheme in NVM-based main memory
Reliable information extraction for single trace attacks
A Universal Spintronic Technology based on Multifunctional Standardized Stack
Software Thread Integration and Synthesis for Real-Time Applications
CPF: A Cross-Layer Prefetching Framework for High-Density Flash-Based Storage
PANEL SESSION - Open source hardware IP, are you serious?
Using Formal Conformance Testing to Generate Scenarios for Autonomous Vehicles
Worst case delay analysis for memory interference in multicore systems
A novel LDPC decoder for DVB-S2 IP
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
Robust design of embedded systems
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect
An embedded wide-range and high-resolution CLOCK jitter measurement circuit
UWB: Innovative architectures enable disruptive low power wireless applications
Machine learning for run-time energy optimisation in many-core systems
REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures
EVPS: An Automotive Video Acquisition and Processing Platform
Reliability Analysis of a Spiking Neural Network Hardware Accelerator
Real-time implementation and performance optimization of 3D sound localization on GPUs
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC
Object-Oriented Reuse Methodology for VHDL
Generation of the HDL-A-model of a micromembrane from its finite-element-description
HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System
SystemC and SystemVerilog: Where do They Fit? Where are They Going?
AVRNTRU: Lightweight NTRU-based Post-Quantum Cryptography for 8-bit AVR Microcontrollers
Theoretical and Practical Aspects of IDDQ Settling-Impact on Measurement Timing and Quality
An EMC-Compliant Design Method of High-Density Integrated Circuits
Extending lifetime of portable systems by battery scheduling
Priority division: A high-speed shared-memory bus arbitration with bounded latency
Analysis of ethernet-switch traffic shapers for in-vehicle networking applications
Embedded systems and software challenges in electric vehicles
Realistic Fault Extraction for Boards
Efficient Verification using Generalized Partial Order Analysis
A Skill-based library for retargetable embedded analog cores
Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory Accelerators
A Power Estimation Model for High-Speed CMOS A/D Converters
A new reversible design of BCD adder
Automated determination of top level control signals
Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction
Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology
Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications
Unsupervised power modeling of co-allocated workloads for energy efficiency in data centers
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis
A reconfigurable heterogeneous multicore with a homogeneous ISA
Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling
Verifiable Security Templates for Hardware
On Transfer Function and Power Consumption Transient Response
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
Late Breaking Results: Practical Electromagnetic Fault Injection on Intel Neural Compute Stick 2
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios
Formal Verification Techniques: Industrial Status and Perspectives
An all-digital built-in self-test technique for transfer function characterization of RF PLLs
ATLAS: a chip-multiprocessor with transactional memory support
Multidimensional Features Helping Predict Failures in Production SSD-Based Consumer Storage Systems
Memristor for computing: Myth or reality?
How Parallel Circuit Execution Can Be Useful for NISQ Computing?
Long Range Detection of Emanation from HDMI Cables Using CNN and Transfer Learning
Resource utilization and Quality-of-Control trade-off for a composable platform
WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs
Wrapper Design for Testing IP Cores with Multiple Clock Domains
UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing
Workload dependent reliability timing analysis flow
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis
The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits
Spatial Modeling with Automated Machine Learning and Gaussian Process Regression Techniques for Imputing Wafer Acceptance Test Data
A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver
TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint
The impact of loop unrolling on controller delay in high level synthesis
Identifying the Most Reliable Collaborative Workload Distribution in Heterogeneous Devices
Beyond UPF & CPF: Low-power design and verification
Security aspects in 6lowPan networks
Eliminating the Z-Buffer bottleneck
FlexiCheck: An Adaptive Checkpointing Architecture for Energy Harvesting Devices
Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023
Transparent linking of compiled software and synthesized hardware
A Heat-Recirculation-Aware VM Placement Strategy for Data Centers
FAGC: Free Space Fragmentation Aware GC Scheme based on Observations of Energy Consumption
CORN: In-Buffer Computing for Binary Neural Network
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking
Holistic simulation of FlexRay networks by using run-time model switching
Variation resilient adaptive controller for subthreshold circuits
Automated Generation of LTL Specifications For Smart Home IoT Using Natural Language
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing
Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals
Selective state retention design using symbolic simulation
Using SAT for combinational equivalence checking
A System Architecture for Reconfigurable Trusted Platforms
Static Timing Analysis Taking Crosstalk into Account
Droop mitigating last level cache architecture for STTRAM
Quantifier structure in search based procedures for QBFs
PEG, MPEG-4, and H.264 Codec IP Development
A Method of Distributed Controller Design for RTL Circuits
Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure Synthesis
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array
A novel fault tolerant cache architecture based on orthogonal latin squares theory
AttBind: Memory-Efficient Acceleration for Long-Range Attention Using Vector-Derived Symbolic Binding
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
A Software Architecture to Control Service-Oriented Manufacturing Systems
Synthesis algorithm of parallel index generation units
Improving SIMD code generation in QEMU
Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow
Impact of voltage scaling on nanoscale SRAM reliability
Aelite: A flit-synchronous Network on Chip with composable and predictable services
A testability measure for hierarchical design environments
dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding
A Framework of Stochastic Power Management Using Hidden Markov Model
A generalized scheduling approach for dynamic dataflow applications
Low cost LDPC decoder for DVB-S2
Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations
Online Performance and Power Prediction for Edge TPU via Comprehensive Characterization
Area efficient asynchronous SDM routers using 2-stage Clos switches
A scheme for multiple on-chip signature checking for embedded SRAMs
FlexRay transceiver in a 0.35 µm CMOS high-voltage technology
Scalable codeword generation for coupled buses
Diagnosis for scan-based BIST: reaching deep into the signatures
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
High-sensitivity hardware trojan detection using multimodal characterization
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design
A boolean satisfiability-based incremental rerouting approach with application to FPGAs
CE-Based Optimization for Real-time System Availability under Learned Soft Error Rate
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
Cellular neural network friendly convolutional neural networks - CNNs with CNNs
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC
The SERRANO platform: Stepping towards seamless application development & deployment in the heterogeneous edge-cloud continuum
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA
Efficient Hyperdimensional Learning with Trainable, Quantizable, and Holistic Data Representation
Access Pattern-Based Code Compression for Memory-Constrained Embedded Systems
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations
A rule-based static dataflow clustering algorithm for efficient embedded software synthesis
A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder Filling
FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations
Development of low power many-core SoC for multimedia applications
SEU-aware resource binding for modular redundancy based designs on FPGAs
Efficiency of a glitch detector against electromagnetic fault injection
Rethinking on-chip DRAM cache for simultaneous performance and energy optimization
Dancer: Dynamic Compression and Quantization Architecture for Deep Graph Convolutional Network
Design Methodology for IP Providers
Automatic Time-Frequency Analysis of MRPs for Mind-controlled Mechatronic Devices
Bright-Field AAPSM Conflict Detection and Correction
Constructing portable compiled instruction-set simulators: an ADL-driven approach
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment
(AS) 2 : accelerator synthesis using algorithmic skeletons for rapid design space exploration
Advances in variation-aware modeling, verification, and testing of analog ICs
Biologically-inspired massively-parallel architectures - Computing beyond a million processors
DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys
Balancing structural hazards and hardware cost of pipelined processors
2DCC: Cache Compression in Two Dimensions
Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs
High-Level Allocation to Minimize Internal Hardware Wastage
Orchestration of Perception Systems for Reliable Performance in Heterogeneous Platforms
Improving STT-MRAM density through multibit error correction
Programmable EM Sensor Array for Golden-Model Free Run-Time Trojan Detection and Localization
Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs
Pump-aware flow routing algorithm for programmable microfluidic devices
Joint optimization of speed, accuracy, and energy for embedded image recognition systems
Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit
Queue Management in Network Processors
Distributed cooperative shared last-level caching in tiled multiprocessor system on chip
A Brief Survey of Algorithms, Architectures, and Challenges toward Extreme-scale Graph Analytics
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise
Out-of-Step Pipeline for Gather/Scatter Instructions
Is split manufacturing secure?
Memory array protection: check on read or check on write?
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states
Architectural and technology influence on the optimal total power consumption
AMSER: Adaptive Multimodal Sensing for Energy Efficient and Resilient eHealth Systems
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
Efficient constant-time entropy decoding for H.264
Combination of Lower Bounds in Exact BDD Minimization
Polynomial Formal Verification of Sequential Circuits
Scalable Adaptive Scan (SAS)
Low supply voltage, low noise fully differential programmable gain amplifiers
Characterization of the bistable ring PUF
On the optimality of K longest path generation algorithm under memory constraints
A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
Offline Model Guard: Secure and Private ML on Mobile Devices
Power- and Deadline-Aware Dynamic Inference on Intermittent Computing Systems
Technology-Aware Logic Synthesis for Superconducting Electronics
High-level synthesis of software-customizable floating-point cores
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor
SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics
Self-awareness in remote health monitoring systems using wearable electronics
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
PFP: Parallel Floating-Point Vector Multiplication Acceleration in MAGIC ReRAM
Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints
Clock gating approaches by IOEX graphs and cluster efficiency plots
Performance-reliability tradeoff analysis for multithreaded applications
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
Pseudo circuit model for representing uncertainty in waveforms
System Synthesis for Multiprocessor Embedded Applications
An algorithm for numerical reference generation in symbolic analysis of large analog circuits
ViTA: A Highly Efficient Dataflow and Architecture for Vision Transformers
Efficient storage management for aged file systems on persistent memory
RT level timing modeling for aging prediction
Engineering Change Order for Combinational and Sequential Design Rectification
Holistic coupled field and circuit simulation
A true power detector for RF PA built-in calibration and testing
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Non-Volatile Phase Change Material based Nanophotonic Interconnect
A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations
Efficient kernel management on GPUs
HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling
GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
May-happen-in-parallel analysis based on segment graphs for safe ESL models
Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network