yusuke1997/dblp-id-title huggingface dataset:
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips
Boosting self-repair workflow with brainstorming for code generation
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
A State Machine for Detecting C/C++ Memory Faults
Test Generation for Timing-Critical Transition Faults
User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT
Industry Session II: DFT on AI Chips
An Approach to RTL Fault Extraction and Test Generation
Test and Debug Strategy for High Speed JESD204B Rx PHY
A Practical Logic BIST for ASIC Designs
Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance
RTL Agent: An Agent-Based Approach for Functionally Correct HDL Generation via LLMs
Waveform Polynomial Manipulation Using Bdds
An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing
High Quality System Level Test and Diagnosis
A SoC Test Strategy Based on a Non-Scan DFT Method
Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique
Multi-configuration Scan Structure for Various Purposes
Generator choices for delay test
SpeedGrade: An RTL Path Delay Fault Simulator
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem
A Method to Reduce Power Dissipation during Test for Sequential Circuits
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator
Test Scheduling and Test Access Architecture Optimization for System-on-Chip
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops
PowerMAX: Fast Power Analysis during Test
A Practical Implementation Of Dynamic Testing Of An Ad Converter
Core-Level Compression Technique Selection and SOC Test Architecture Design
LIFTING: A Flexible Open-Source Fault Simulator
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer
Low Power BIST with Smoother and Scan-Chain Reorder
Usable Circuits with Imperfect Scan Logic
Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems
Built-In Self-Test for Capacitive MEMS Using a Charge Control Technique
Hierarchical State Space Checks for Errors in Sensors, Actuators and Control of Nonlinear Systems: Diagnosis and Compensation
Development of practical ATPG tool with flexible interface
A Comprehensive System-on-Chip Logic Diagnosis
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security
Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction
Theoretical Analysis on Noise Performance of Modulated Wideband Converters for Analog Testing
Low Power Test-Compression for High Test-Quality and Low Test-Data Volume
On Improving Diagnostic Test Generation for Scan Chain Failures
Design and Simulation of Fault Detection Technique for NAND Based Memory Array
Dynamic Compaction in SAT-Based ATPG
Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead
Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical Software
Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits
Compaction Schemes with Minimum Test Application Time
Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits
Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage
DPSC SRAM Transparent Test Algorithm
Limitation of structural scan delay test
Build-In-Self-Test for Software
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation
Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits
Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training
Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges
Underdesigned and Opportunistic Computing
Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing
Overhead reduction techniques for hierarchical fault simulation
Generalized modular design of testable m-out-of-n code checker
Testing of Embedded Memories - The Aggregate
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction
On the testability of IEEE 1687 networks
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test
A Scan-Out Power Reduction Method for Multi-cycle BIST
Flash Memory Die Sort by a Sample Classification Method
Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique
Accurate Testing of Precision Voltage Reference by DC-AC Conversion
Compact Test Generation for Small-Delay Defects Using Testable-Path Information
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions
11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA
Logic BIST Architecture for System-Level Test and Diagnosis
Cyclic greedy generation method for limited number of IDDQ tests
TOF: a tool for test pattern generation optimization of an FPGA application oriented test
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
Evaluation of a BIST Technique for CMOS Imagers
An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters
Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test
Testing for Missing-Gate Faults in Reversible Circuits
Power supply current monitoring techniques for testing PLLs
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory
An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan
Arithmetic Test Strategy for FFT Processor
Hyperactive Faults Dictionary to Increase Diagnosis Throughput
Error Detection and Correction in VLSI Systems by Online Testing and Retrying
DC control and observation structures for analog circuits
Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language Specifications
Fourier Spectrum-Based Signature Test: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources
Customized Algorithms for High Performance Memory Test in Advanced Technology Node
On the capability of delay tests to detect bridges and opens
An FPGA-Based Emulation Platform for Functional Safety Verification in Automotive SoC Systems
SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions
XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults
A high-speed IDDQ sensor implementation
Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells
Fault Diagnosis in Memory BIST Environment with Non-march Tests
Economical Importance of the Maximum Chip Area
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
Fault Diagnosis Using Test Primitives in Random Access Memories
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
Strong self-testability for data paths high-level synthesis
Fault Testing in AI-Accelerators: A Review
32nd IEEE Asian Test Symposium, ATS 2023, Beijing, China, October 14-17, 2023
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Investigation of Ga Contamination Due to Analysis by Dual Beam FIB
Efficient SAT-Based Search for Longest Sensitisable Paths
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC
An efficient parallel transparent diagnostic BIST
Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates
Test Response Compression Based on Huffman Coding
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture
Diagnostic Test of Robust Circuits
An On-Chip Jitter Measurement Circuit for the PLL
A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications
Concurrent Test Implementations
Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations
Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests
A BIST Structure to Test Delay Faults in a Scan Environment
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
An extended march test algorithm for embedded memories
An Improved Test Case Generation Method of Pair-Wise Testing
Using Programmable On-Product Clock Generation (OPCG) for Delay Test
A perturbation based fault modeling and simulation for mixed-signal circuits
Detecting Unique Faults in Multi-port SRAMs
Testing Disturbance Faults in Various NAND Flash Memories
MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning
Design of delay-verifiable combinational logic by adding extra inputs
At-speed Test of High-Speed DUT Using Built-Off Test Interface
Power Analysis and Reduction Techniques for Transition Fault Testing
Programming a Topological Quantum Computer
A New Procedure for Measuring High-Accuracy Probability Density Functions
Between-Core Vector Overlapping for Test Cost Reduction in Core Testing
etection of SRAM cell stability by lowering array supply voltage
Advanced Analysis of Cell Stability for Reliable SRAM PUFs
Security Concerns of Machine Learning Hardware
Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs
A Ring Architecture Strategy for BIST Test Pattern Generation
Bluetooth Hopping BER Testing Methodologies on a Production Test Platform
9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan
A Test Decompression Scheme for Variable-Length Coding
Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects
Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking
Exploiting BIST Approach for Two-Pattern Testing
Hierarchical Test Generation with Built-In Fault Diagnosis
A Low-Power LFSR Architecture
The Test Ability of an Adaptive Pulse Wave for ADC Testing
A New Auto-Focus Method in Critical Dimension Measurement SEM
Test Generation for Double Stuck-at Faults
Multiple Scan Tree Design with Test Vector Modification
Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing
Charge sharing fault analysis and testing for CMOS domino logic circuits
8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China
Search Space Reduction for Low-Power Test Generation
An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE System
Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs
A Novel Multi-Scope Characterization Method for Automotive LPDDR4 Controller
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories
Detectability of the Two-Dimensional Detector for Time Resolved Emission Measurement
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs
Random Jitter Testing Using Low Tap-Count Delay Lines
An efficient BIST design using LFSR-ROM architecture
Side-Channel Attacks on Triple Modular Redundancy Schemes
Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
How the noise floor affects the production yield
Dynamic Test Compression Using Statistical Coding
Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis
ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs
Design of C-Testable Multipliers Based on the Modified Booth Algorithm
New Capabilities of OBIRCH Method for Fault Localization and Defect Detection
Mixed-Signal Fault Equivalence: Search and Evaluation
A Soft Error Resilient Low Leakage SRAM Cell Design
Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised Learning
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test
High performance advanced fault model diagnosis
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric
Probability Model for Faults in Large-Scale Multicomputer Systems
Invited Talk 1: Testing of Power Constraint Computing
Fault diagnosis of odd-even sorting networks
Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment
Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips
On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits
On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation
Seed Ordering and Selection for High Quality Delay Test
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs
A Generalized Theory for Formal Assertion Coverage
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits
Soft Error Recovery Technique for Multiprocessor SOPC
Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs
Industry Session I: On Automotive Testing
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost
Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion
An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters
Testing the Conformity of Transactional Attributes of Components by Simulation
A BIST Scheme Based on Selecting State Generation of Folding Counters
A realistic fault model for flash memories
Faults and Tests in Quantum Circuits
Sharing BIST with Multiple Cores for System-on-a-Chip
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs
Testing in the Fourth Dimension
Test Power Reduction with Multiple Capture Orders
BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search
Online Test Macro Scheduling and Assignment in MPSoC Design
Scan Diagnosis and Its Successful Industrial Applications
Comprehensive Interconnect BIST Methodology for Virtual Socket Interface
Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata
A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications
Failure Analysis and Test Solutions for Low-Power SRAMs
MD-SCAN Method for Low Power Scan Testing
Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors
MTCX: Ultra-high Throughput TRNG Based on Mesh topology of Coupled-XOR
Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic Biochips
Physically-Aware Diagnostic Resolution
A Memory Specific Notation for Fault Modeling
Core - Clustering Based SOC Test Scheduling Optimization
A Novel Approach for On-line Testable Reversible Logic Circuit Desig
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information
A Re-design Technique for Datapath Modules in Error Tolerant Applications
Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion
An Analytic Software Testability Model
D-Scale: A Scalable System-Level Dependable Method for MPSoCs
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits
High-speed generation of LFSR signatures
PointerChecker: Tag-Based and Hardware-Assisted Memory Safety against Memory Corruption
March PS(23N) Test for DRAM Pattern-Sensitive Faults
HTrans: Transformer-Based Method for Hardware Trojan Detection and Localization
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data
Thermal Safe High Level Test Synthesis for Hierarchical Testability
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator
Using FPGA configuration memory to accelerate yield learning for advanced process
A Low-Cost Jitter Measurement Technique for BIST Applications
Intelligent EB Test System for Automatic VLSI Fault Tracing
Domain Testing Based on Character String Predicate
A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability
New Microcode's Generation Technique for Programmable Memory Built-In Self Test
Module level weighted random patterns
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test
Development of a Multi-Channel PC-Based Hard Disk Drive Bode-Plot Generator
In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms
Mining Sequential Constraints for Pseudo-Functional Testing
Activation Function Manipulation for Fault Tolerant Feedforward Neural Networks
An Efficient PRPG Strategy By Utilizing Essential Faults
Variability and Soft-Error Resilience in Dependable VLSI Platform
Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing Approach
Hardware Trojan in FPGA CNN Accelerator
Monitoring Transient Errors in Sequential Circuits
Fault Diagnosis for Physical Defects of Unknown Behaviors
Diagnosis of Multiple Physical Defects Using Logic Fault Models
Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts
"Challenges in Testing"
Predicting Scan Compression IP Configurations for Better QoR
PADLOC: Physically-Aware Defect Localization and Characterization
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells
Autonomous Testing for 3D-ICs with IEEE Std. 1687
Enhanced Broadside Testing for Improved Transition Fault Coverage
Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection
Fanout-based fault diagnosis for open faults on pass/fail information
Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies
BIST TPG for SRAM cluster interconnect testing at board level
An obfuscation scheme of scan chain to protect the cryptographic chips
Multiscan-based Test Data Compression Using UBI Dictionary and Bitmask
A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation
Power Analysis of DRAMs
SAT-Based Algorithm of Verification for Port Order Fault
Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection
Optimizing Test Data Volume Using Hybrid Compression
IDDQ Sensing Technique for High Speed IDDQ Testing
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation
CausalTester: Measuring the Consistency of Replicated Services via Causality Semantics
A High-Performance and P-Type FeFET-Based Non-Volatile Latch
Verification of deadlock free property of high level robot control
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation
Test Compression with Single-Input Data Spreader and Multiple Test Sessions
Leading Edge Technology and Test Noise
On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs
LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement
Fault Set Partition for Efficient Width Compression
How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes
Automotive EEPROM Qualification and Cost Optimization
Hybrid BIST Using Partially Rotational Scan
Optimizing LBIST Run Time for a Safety Critical SoC: A Practical Approach
Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection
BISTing Switched-Current Circuits
On fault injection approaches for fault tolerance of feedforward neural networks
An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)
SAMURAI: A Framework for Safeguarding Against Malicious Usage and Resilience of AI
Deep Learning Based Diagnostics for Rowhammer Protection of DRAM Chips
On the Generation of Diagnostic Test Set for Intra-cell Defects
Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft?
A Methodology for Minimum Area Cellular Automata Generation
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment
Variation-Aware Fault Grading
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs
On-Chip Ring Oscillator Based Scheme for TSV Delay Measurement
Testability analysis of co-designed systems
An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data
A New Architecture to Cross-Fertilize On-Line and Manufacturing Testing
A Multiple Phase Partial Scan Design Method
Low Distortion Sine Waveform Generation by an AWG
An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement
Effective Runtime Fault Detection for DNN Accelerators
Not All Xs are Bad for Scan Compression
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency
Boundary Value Testing based on UML Models