yusuke1997/dblp-id-title huggingface dataset:
Vector Runahead
ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification
FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs
Sequentially Encoded Data Structures that Support Bidirectional Scanning
An embedded DRAM architecture for large-scale spatial-lattice computations
Message Repository Definitional Facility: An Architectural Model for Interprocess Communication
Micromodules: Microprogrammable Building Blocks for Hardware Development
Flexible Register Management for Sequential Programs
Hardware-Based Domain Virtualization for Intra-Process Isolation of Persistent Memory Objects
SPEAC-Special Purpose Electronic Area Correlator
TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks
An intra-chip free-space optical interconnect
Commutative Data Reordering: A New Technique to Reduce Data Movement Energy on Sparse Inference Workloads
EQC: ensembled quantum computing for variational quantum algorithms
FOLCS: A Lightweight Implementation of a Cycle-accurate NoC Simulator on FPGAs
Processor-Memory Interconnections for Multiprocessors
43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016
AI accelerator on IBM telum processor: industrial product
A Data Driven System Based on a Microprogrammed Processor Module
Crescent: taming memory irregularities for accelerating deep point cloud analytics
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
Computer Structures: What Have We Learned from the PDP-11?
A Scalable Instruction Queue Design Using Dependence Chains
The Schuss Filter: A Processor for Non-Numerical Data Processing
Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors
Proceedings of the 2nd Annual Symposium on Computer Architecture, Houston, TX, USA, December 1974
Comparing Software and Hardware Schemes For Reducing the Cost of Branches
Memory System Characterization of Commercial Workloads
SMS 101 - A Structured Multimicroprocessor System with Deadlock-Free Operation Scheme
LightML: A Photonic Accelerator for Efficient General Purpose Machine Learning
An Integrated Multiprocessing Array for Time Warp Pattern Matching
An Evaluation of Branch Architectures
Hardware Scheduler Performance on the Plural Many-Core Architecture
MANIP - A Parallel Computer System for Implementing Branch and Bound Algorithms
Adaptive insertion policies for high performance caching
Transient-Fault Recovery for Chip Multiprocessors
Retrospective: Very Long Instruction Word Architectures and the ELI-512
An integrated GPU power and performance model
On Error Correction for Nonvolatile Processing-In-Memory
S-Connect: From Networks of Workstations to Supercomputer Performance
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
A Study of Instruction Cache Organizations and Replacement Policies
QuTracer: Mitigating Quantum Gate and Measurement Errors by Tracing Subsets of Qubits
Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy
A case for FAME: FPGA architecture model execution
Hyperswitch Network for the Hypercube Computer
45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA, June 1-6, 2018
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
HyperTRIO: Hyper-Tenant Translation of I/O Addresses
Efficient code generation for horizontal architectures: Compiler techniques and architectural support
SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History
Scaling Application Performance on a Cache-Coherent Multiprocessors
Performance improvement for vector pipeline multiprocessor systems using a disordered execution model
AiF: Accelerating On-Device LLM Inference Using In-Flash Processing
Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
The Cedar System and an Initial Performance Study
Counting Dependence Predictors
Correct Memory Operation of Cache-Based Multiprocessors
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference
DRPM: Dynamic Speed Control for Power Mangagement in Server Class Disks
Computing Architectural Vulnerability Factors for Address-Based Structures
Innovative instructions and software model for isolated execution
Vantage: scalable and efficient fine-grain cache partitioning
A High Performance Factoring Machine
Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors
The Design and Implementation of a Real-Time Sound Generation System
ISA-Grid: Architecture of Fine-grained Privilege Control for Instructions and Registers
Matrix Multiplication in an Interleaved Array Processing Architecture
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing
Options for Dynamic Address Translation in COMAs
EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID Architectures
Rearrangeability of Multistage Shuffle/Exchange Networks
FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction
On Coupling Many Small Systems for Transaction Processing
Tender: Accelerating Large Language Models via Tensor Decomposition and Runtime Requantization
X-cache: a modular architecture for domain-specific caches
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
Using innovative instructions to create trustworthy software solutions
A Comparative Analysis of Schemes for Correlated Branch Prediction
DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands
The Munet: A Scalable Decentralized Architecture For Parallel Computers
EIE: Efficient Inference Engine on Compressed Deep Neural Network
Avant-Garde: Empowering GPUs with Scaled Numeric Formats
Use ECP, not ECC, for hard failures in resistive memories
A Model and an Architecture for a Relational Knowledge Base
The Impact of Communication Locality on Large-Scale Multiprocessor Performance
A VLSI Tree Machine for Relational Data Bases
Design of Cache Memories for Multi-Threaded Dataflow Architecture
Cache Hit Ratios With Geometric Task Switch Intervals
Fault-Tolerant Scheme for Multistage Interconnection Networks
Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics
Execution-based prediction using speculative slices
Software-Controlled Caches in the VMP Multiprocessor
CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems
SmartDS: Middle-Tier-centric SmartNIC Enabling Application-aware Message Split for Disaggregated Block Storage
ElasticRec: A Microservice-based Model Serving Architecture Enabling Elastic Resource Scaling for Recommendation Models
Exploring and exploiting wire-level pipelining in emerging technologies
Tarantula: A Vector Extension to the Alpha Architecture
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes
Architecture of the Corail Building Block System
Destination Tag Routing Techniques Based on a State Model for the IADM Network
Hermes: Algorithm-System Co-design for Efficient Retrieval-Augmented Generation At-Scale
Achieving Power-Efficiency in Clusters without Distributed File System Complexity
PuDHammer: Experimental Analysis of Read Disturbance Effects of Processing-using-DRAM in Real DRAM Chips
IDEA-GP: Instruction-Driven Architecture with Efficient Online Workload Allocation for Geometric Perception
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Application-aware deadlock-free oblivious routing
Stash: have your scratchpad and cache it too
Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA
Can Dataflow Subsume von Neumann Computing?
Virtualizing performance asymmetric multi-core systems
Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8
CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM
Making the fast case common and the uncommon case simple in unbounded transactional memory
Improving the energy efficiency of Big Cores
Software-Hardware Co-Optimization for Computational Chemistry on Superconducting Quantum Processors
Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer
Profile-Guided Temporal Prefetching
Designing Linear Storage Hierarchies so as to Maximize Reliability Subject to Cost and Performance Constraints
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
Architecture Validation for Processors
Adaptive Backoff Synchronization Techniques
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture
Implementation Aspects of the Symbol Hardware Compiler
A durable and energy efficient main memory using phase change memory technology
A quantum computational compiler and design tool for technology-specific targets
Speculative Dynamic Vectorization
The Architecture of the Picture System
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
On Relating Small Computer Performance to Design Parameters
Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations
Design Tradeoffs for Software-Managed TLBs
Flexible reference-counting-based hardware acceleration for garbage collection
Configurable isolation: building high availability systems with commodity multi-core processors
Power provisioning for a warehouse-sized computer
Evaluating the Memory Overhead Required for COMA Architectures
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network
Cambricon-F: machine learning computers with fractal von neumann architecture
A multiple processor system for real time control tasks
An Iteratively Structured Information Processor
Simulation Exercises for Computer Architecture Education
A Comparison of Adaptive Wormhole Routing Algorithms
38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA
Next Cache Line and Set Prediction
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors
The EM-X Parallel Computer: Architecture and Basic Performance
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches
A Character-Oriented Context-Addressed Segment Sequential Storage
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets
Side-channel indistinguishability
Architectural and implementation tradeoffs in the design of multiple-context processors
The Boolean Vector Machine [BVM]
Wire Delay is Not a Problem for SMT (In the Near Future)
An Optical Residue Arithmetic Unit
Comparing memory systems for chip multiprocessors
Snowflake: deep neural network accelerator
Toward visual intelligence
32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA
Interconnection Unit for Poly-Processor System: An Analysis and Design
Derm: SLA-aware Resource Management for Highly Dynamic Microservices
The time-constrained barrier synchronizer and its applications in parallel systems
Replay debugging: Leveraging record and replay for program debugging
Reduction Languages for Reduction Machines
ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications
Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution
Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs
Tetris: A Compilation Framework for VQA Applications in Quantum Computing
Watchdog: Hardware for safe and secure manual memory management and full memory safety
Sentry: light-weight auxiliary memory access control
Quality of Service Support for Fine-Grained Sharing on GPUs
VDL - A Definitional System for All Levels
HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping
Design and Performance of Special Purpose Hardware for Time Warp
Architectural Tradeoffs in the Design of MIPS-X
A New Formulation of Neural Data Prefetching
Efficient digital neurons for large scale cortical architectures
Microprocessor Implementation of a Parallel Processor
MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency
Retrospective: Weak Ordering - A New Definition
Graph Allocation in Static Dataflow Systems
The Status of MANIP-A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems
All Your PC Are Belong to Us: Exploiting Non-control-Transfer Instruction BTB Updates for Dynamic PC Extraction
BFS-Realization of a Fault-Tolerant Architecuture
Virtualizing the VAX Architecture
Proceedings of the 1st Annual Symposium on Computer Architecture, Gainesville, FL, USA, December 1973
Selection of Microprocessor Equipment
Genesis: A Hardware Acceleration Framework for Genomic Data Analysis
PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture
The Mondrian Data Engine
2-D SIMD Algorithms in the Perfect Shuffle Networks
Data Broadcasting in Linearly Scheduled Array Processors
Performance and security lessons learned from virtualizing the alpha processor
Database filters
Boosting Access Parallelism to PCM-Based Main Memory
To PIM or not for emerging general purpose processing in DDR memory systems
Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product
Correlation and Aliasing in Dynamic Branch Predictors
Dynamic thread block launch: a lightweight execution mechanism to support irregular applications on GPUs
Acceleration of Software Transactional Memory through Hardware Clock
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
Imprecise Store Exceptions
The Block-Based Trace Cache
Cost, Performance and Size Tradeoffs for Different Levels in a Memory Hierarchy
Criticality stacks: identifying critical threads in parallel programs using synchronization behavior
Heat to Power: Thermal Energy Harvesting and Recycling for Warm Water-Cooled Datacenters
DCPerf: An Open-Source, Battle-Tested Performance Benchmark Suite for Datacenter Workloads
On-Line Architecture Tuning Using Microcapture
Enabling preemptive multiprogramming on GPUs
Closely Coupled Asynchronous Hierarchical and Parallel Processing in an Open Architecture
EA-PLRU: Enclave-Aware Cache Replacement
AMALI: An Analytical Model for Accurately Modeling LLM Inference on Modern GPUs
Speculative Vectorisation with Selective Replay
Limits of Control Flow on Parallelism
ShiDianNao: shifting vision processing closer to the sensor
A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks
PrORAM: dynamic prefetcher for oblivious RAM
Automated design of finite state machine predictors for customized processors
Jenga: Software-Defined Cache Hierarchies
Scale-out processors
Scalable high performance main memory system using phase-change memory technology
Free atomics: hardware atomic operations without fences
A Partial-Multiple-Bus Computer Structure with Improved Cost-Effectiveness
Application and Architectural Bottlenecks in Large Scale Distributed Shared Memory Machines
Retrospective: The Turn Model for Adaptive Routing
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
Design Study of an Avionics Navigation Microcomputer
PID-Comm: A Fast and Flexible Collective Communication Framework for Commodity Processing-in-DIMM Devices
TLSync: support for multiple fast barriers using on-chip transmission lines
Completion time multiple branch prediction for enhancing trace cache performance
Can Manycores Support the Memory Requirements of Scientific Applications?
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
Understanding Application Performance on Shared Virtual Memory Systems
A partitioned translation lookaside buffer approach to reducing address bandwith
Towards a practical solution to detect code reuse attacks on ARM mobile devices
Hardware Threading Techniques for Multi-Threaded MPSoCs
Pipelining and bypassing in a VLIW processor
NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters
Low-Latency Virtual-Channel Routers for On-Chip Networks
Energy Efficient Co-Adaptive Instruction Fetch and Issue
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
RADISH: Always-on sound and complete race detection in software and hardware
SQUARE: Strategic Quantum Ancilla Reuse for Modular Quantum Programs via Cost-Effective Uncomputation
Queue Pair IP: A Hybrid Architecture for System Area Networks
Extending dataflow programs with throughput properties
Study of Multistage SIMD Interconnection Networks
A Fetch-And-Op Implementation for Parallel Computers
The Future of Virtualization Technology
Computer Modules: An Architecture for Large Digital Modules
Multithreading: A Revisionist View of Dataflow Architectures
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations
MIMD Machine Communication Using the Augmented Data Manipulator Network
A Parallel Execution Model of Logic Programs
A case for random shortcut topologies for HPC interconnects
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, MES'2014, in conjunction with the 41st International Symposium on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15, 2014
The Pringle Parallel Computer
A software-defined tensor streaming multiprocessor for large-scale machine learning
Triggered instructions: a control paradigm for spatially-programmed architectures
Memory Sharing Predictor: The Key to a Speculative Coherent DSM
Many-core acceleration for model predictive control systems
Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
High performance cache replacement using re-reference interval prediction (RRIP)
Proceedings of the 46th International Symposium on Computer Architecture, ISCA 2019, Phoenix, AZ, USA, June 22-26, 2019
A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation
Balance in Architectural Design
Implementing Optimizations at Decode Time
A Study of I/O System Organizations
Convolution engine: balancing efficiency & flexibility in specialized computing
A Research Retrospective on AMD's Exascale Computing Journey
ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014
Detecting Data Races on Weak Memory Systems
Architecture Support for System Protection
On the Feasibility of Advanced Cache Indexing for High-Performance and Energy-Efficient GPGPU Computing
Gen-NeRF: Efficient and Generalizable Neural Radiance Fields via Algorithm-Hardware Co-Design
A Unified Resource Management and Execution Control Mechanism for Data Flow Machines
FASE: finding amplitude-modulated side-channel emanations
An Associative/Parallel Processor for Partial Match Retrieval Using Superimposed Codes
Matrix scheduler reloaded
Web search using mobile cores: quantifying and mitigating the price of efficiency
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
A shared resource algorithm for distributed simulation
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs
Secure I/O device sharing among virtual machines on multiple hosts
Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays
The Case For Data Centre Hyperloops
UGPU: Dynamically Constructing Unbalanced GPUs for Enhanced Resource Efficiency
Managing reliability skew in DNA storage
Can randomized mapping secure instruction caches from side-channel attacks?
The Case for Lifetime Reliability-Aware Microprocessors
SwitchQNet: Optimizing Distributed Quantum Computing for Quantum Data Centers with Switch Networks
Concepts of the System/370 Vector Architecture
NDMiner: accelerating graph pattern mining using near data processing
Perspective: A Principled Framework for Pliable and Secure Speculation in Operating Systems
CryptoManiac: a fast flexible architecture for secure communication
Proceedings of the Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2017, Toronto, ON, Canada, June 25, 2017
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Avalanche: Optimizing Cache Utilization via Matrix Reordering for Sparse Matrix Multiplication Accelerator
Active Messages: A Mechanism for Integrated Communication and Computation
Machine learning on the edge
Page overlays: an enhanced virtual memory framework to enable fine-grained memory management
Physically Addressed Queueing (PAQ): Improving parallelism in Solid State Disks
Constructing a Weak Memory Model
Configurable fine-grain protection for multicore processor virtualization
Evaluation of the FACOM ALPHA Lisp Machine
CAWA: coordinated warp scheduling and cache prioritization for critical warp acceleration of GPGPU workloads
Atom-Aid: Detecting and Surviving Atomicity Violations
Assassyn: A Unified Abstraction for Architectural Simulation and Implementation
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
On Design of Rotary Array Communication and Wavefront-Driven Algorithms for Solving Large-Scale Band-Limited Matrix Equations
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware
The Detection and Elimination of Useless Misses in Multiprocessors
TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus Tests
Focused Value Prediction
Understanding and Mitigating Hardware Failures in Deep Learning Training Systems
A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules
Designing vertical processors in monolithic 3D
An effective hybrid transactional memory system with strong isolation guarantees
A Digital Signal Processor for Real Time Generation of Speech Waveforms
The Sparsity-Aware LazyGPU Architecture
Experimental Polyprocessor System (EPOS) - Architecture
A Combination of Field and Current Access Techniques for Effiecient and Cost-Effective Bubble Memories
Non-Speculative Load-Load Reordering in TSO
The Architecture of REPLICA-A Special-Purpose Computer System for Active Multi-Sensory Perception of 3-Dimensional Objects
Cambricon: An Instruction Set Architecture for Neural Networks
A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture
Duplication of packets and their detection in X.25 communication protocols
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache
Toward a Dataflow/von Neumann Hybrid Architecture
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA
The Dirty-Block Index
Power Awareness through Selective Dynamically Optimized Traces
UDP: Utility-Driven Fetch Directed Instruction Prefetching
Efficient Message Routing in Mega-Micro-Computer Networks
Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees
Enhancing human capabilities
The Intel 8087 Numeric Data Processor