yusuke1997/dblp-id-title huggingface dataset:
Topology and Justified True Belief: A Baseless, Evidence-Free (and Pointless) Approach
A Proof-Theoretic Analysis of the Meaning of a Formula in a Combination of Intuitionistic and Classical Propositional Logic
Cumulative Reading, QUD, and Maximal Informativeness
Formalizing Argument Structures with Combinatory Categorial Grammar
Semantic-Pragmatic Account of Syntactic Structures
An Overt Operator Associating with Covert Focus: An Even-Like Semantics for Mandarin Gèng
Events and Relative Clauses
Comparing Degree-Based and Argumentative Analyses of Even
Extending Abstract Categorial Grammars with Feature Structures: Theory and Practice
Matrix and Relative Weak Crossover on the Level of the Individual: An Experimental Investigation
Measurement Theory Meets Mereology in Multidimensionality in Resemblance Nominalism
Logic Operators and Quantifiers in Type-Theory of Algorithms
Towards a Theory of Anaphoric Binding in Event Semantics
On the Semantics of Dependencies: Relative Clauses and Open Clausal Complements
Contrafactives and Learnability: An Experiment with Propositional Constants
Actionable Program Analyses for Improving Software Performance
Ernst Denert Software Engineering Awards 2019
Same but Different: Consistently Developing and Evolving Software Architecture Models and Their Implementation
Software Developers' Work Habits and Expertise: Empirical Studies on Sketching, Code Plagiarism, and Expertise Development
Ernst Denert Award for Software Engineering 2019 - Practice Meets Foundations
Applied Artifact-Based Analysis for Architecture Consistency Checking
Applications of Synchronized Pushdown Systems
How Much Forcing Is Necessary to Let the Results of Particle Swarms Converge?
Fast Hybrid BSA-DE-SA Algorithm on GPU
Multi-level Parallelization for Hybrid ACO
Smooth Trajectory Planning for Robot Using Particle Swarm Optimization
Parallel and Distributed Implementation Models for Bio-inspired Optimization Algorithms
Classical Mechanics Optimization for Image Segmentation
An Efficient ACO-SA Hybrid Metaheuristic for the Synchronization of Single Frequency Networks in Broadcasting
Distributed Local Search for Elastic Image Matching
An Enhanced Particle Swarm Optimisation Algorithm Combined with Neural Networks to Decrease Computational Time
Total Memory Optimiser: Proof of Concept and Compromises
Data Exchange Topologies for the DISCO-HITS Algorithm to Solve the QAP
A New Parallel Memetic Algorithm to Knowledge Discovery in Data Mining
Floods Trajectories Modeling and Dynamic Relief Planning: A Bees Foraging Approach
Swarm Projects: Beyond the Metaphor
Robust Multi-agent Patrolling Strategies Using Reinforcement Learning
Using Particle Swarm Optimization Method to Invert Active Surface Waves
On the Community Identification in Weighted Time-Varying Networks
Swarm Intelligence Based Optimization - Second International Conference, ICSIBO 2016, Mulhouse, France, June 13-14, 2016, Revised Selected Papers
The Use of Ontology in Semantic Analysis of the Published Learners Messages for Adaptability
Fuzzy Logic Control Optimized by Artificial Immune System for Building Thermal Condition
Swarm Intelligence Based Optimization - First International Conference, ICSIBO 2014, Mulhouse, France, May 13-14, 2014. Revised Selected Papers
Comparison of Two Swarm Intelligence Optimization Algorithms on the Textual Color Problem for Web Accessibility
Combining PSO and FCM for Dynamic Fuzzy Clustering Problems
A Hybrid PSO Applied to the Flexible Job Shop with Transport
Metaheuristics for Solving a Hybrid Flexible Flowshop Problem with Sequence-Dependent Setup Times
Multiple Mobile Target Tracking in Wireless Sensor Networks
Inspiration by Swarms
Using Bio-inspired Algorithm to Compensate Web Page Color Contrast for Dichromat Users
BSG-Starcraft Radius Improvements of Particle Swarm Optimization Algorithm: An Application to Ceramic Matrix Composites
A Fuzzy-Controlled Comprehensive Learning Particle Swarm Optimizer
Particle Swarm Optimization for Operating Theater Scheduling Considering Medical Devices Sterilization
Efficient Testing of Time-Dependent, Asynchronous Code
A Prototype Tool for Semantic Validation of UML Class Diagrams with the Use of Domain Ontologies Expressed in OWL 2
What Is Troubling IT Analysts? A Survey Report from Poland on Requirements-Related Problems
An Association Rule Mining for Selection Requirement Elicitation and Analysis Techniques in IT Projects
Software Development for Modeling and Simulation of Computer Networks: Complex Systems Approach
Applying Use Case Logic Patterns in Practice: Lessons Learnt
A Collaborative Approach to Developing a Part-Time Ph.D. Program in IT Architecture with Industry Cooperation
Business Rule Patterns Catalog for Structural Business Rules
Mutant Generation for WSDL
Dynamic Stylometry for Defect Prediction
Sketching Use-Case Scenarios Based on Use-Case Goals and Patterns
On the Functional Specification of Queries in OCL
A Proposal for Functional Software Identification Using Risk-Based Continuous Quality Control
Software Metrics for Similarity Determination of Complex Software Systems
Enterprise Architecture Modifiability Analysis
Performance Comparison of CRM Systems Dedicated to Reporting Failures to IT Department
Exploring Relationships Between Data in Enterprise Information Systems by Analysis of Log Contents
Managing Software Complexity with Power-Generics
Automatic Processing of Dynamic Business Rules Written in a Controlled Natural Language
SIPE: A Domain-Specific Language for Specifying Interactive Programming Exercises
Software, System, and Service Engineering - S3E 2023 Topical Area, 24th Conference on Practical Aspects of and Solutions for Software Engineering, KKIO 2023, and 8th Workshop on Advances in Programming Languages, WAPL 2023, Held as Part of FedCSIS 2023, Warsaw, Poland, 17-20 September 2023, Revised Selected Papers
An Industrial Survey on Business Analysis Problems and Solutions
Beyond Software Architecture Knowledge Management Tools
Model of RUP Processes Maturity Assessment in IT Organizations
Ensuring the Strong Exception Safety
A Scrum-Centric Framework for Organizing Software Engineering Academic Courses
Assessment of the Software Defect Prediction Cost Effectiveness in an Industrial Project
Modelling and Verification of Real-Time Systems with Alvis
Domain Modeling Based on Requirements Specification and Ontology
Temporal Costs of Computing Unit Redundancy in Steady and Transient State
Hybrid Agile Method for Management of Software Creation
Software Engineering: Challenges and Solutions - Results of the XVIII KKIO 2016 Software Engineering Conference 2016 held at September 15-17 2016 in Wroclaw, Poland
Semantic Validation of UML Class Diagrams with the Use of Domain Ontologies Expressed in OWL 2
Smart City Traffic Monitoring System Based on 5G Cellular Network, RFID and Machine Learning
Engineering Software Systems: Research and Praxis [papers from KKIO 2018, Pultusk, Poland, 27-28 September 2018]
The Performance Analysis of Web Applications Based on Virtual DOM and Reactive User Interfaces
Multi-level Security System Verification Based on the Model
Monitoring and Maintenance of Telecommunication Systems: Challenges and Research Perspectives
Performance Analysis of Compiler Support for Parallel Evaluation of C++ Constant Expressions
Continuous Test-Driven Development: A Preliminary Empirical Evaluation Using Agile Experimentation in Industrial Settings
How Good Is My Project? Experiences from Projecting Software Quality Using a Reference Set
RSL-DL: Representing Domain Knowledge for the Purpose of Code Generation
A Survey Investigating the Influence of Business Analysis Techniques on Software Quality Characteristics
Control Operation Flow for Mobile Access Control with the Use of MABAC Model
Improving Measurement Certainty by Using Calibration to Find Systematic Measurement Error - A Case of Lines-of-Code Measure
Towards a Synergistic Combination of Research and Practice in Software Engineering [papers from KKIO 2017, Rzeszów, Poland, 14-16 September 2017]
Real-Time Comparable Phrases Searching Via the Levenshtein Distance with the Use of CUDA Technology
Value-Based Requirements Engineering: Challenges and Opportunities
A Reusability-Oriented Use-Case Model: Textual Specification Language
Female Leadership in Software Projects - A Preliminary Result on Leadership Style and Project Context Factors
Towards Definition of a Unified Domain Meta-model
Nexus Between Psychological Safety and Non-Technical Debt in Large-Scale Agile Enterprise Resource Planning Systems Development
Software Engineering Needs Agile Experimentation: A New Practice and Supporting Tool
Exploiting scratch-pad memory using Presburger formulas
Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOS
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
Hardware Synthesis from SPDF Representation for Multimedia Applications
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France
Catalyst: A DSIP Design Flow Development in Industry
Issues in Embedded DRAM Development and Applications
Code Generation for Compiled Bit-True Simulation of DSP Applications
Path-based Edge Activation for Dynamic Run-Time Scheduling
Size-Constrained Code Placement for Cache Miss Rate Reduction
Interface Exploration for Reduced Power in Core-Based Systems
Retargetable assembly code generation by bootstrapping
CMP on SoC: Architect's View
The Chinook hardware/software co-synthesis system
Instruction Encoding Techniques for Area Minimization of Instruction ROM
Grammar-Based Hardware Synthesis of Data Communication Protocols
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
State-of-the-art compiler optimization
Reducing the Complexity of ILP Formulations for Synthesis
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description
Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs
A Multi-Level Strategy for Software Power Estimation
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Event-Driven Power Management of Portable Systems
Real-Time Task Scheduling for a Variable Voltage Processor
Sensitivity-driven co-synthesis of distributed embedded systems
Optimal Message-Passing for Data Coherency in Distributed Architecture
Phase coupled operation assignment for VLIW processors with distributed register files
Computing lower bounds on functional units before scheduling
Pre-Fetching for Improved Core Interfacing
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
Formal Verification in a Component-Based Reuse Methodology
Code Generation for Embedded Processors
Security-Driven Exploration of Cryptography in DSP Cores
Application of Software design patterns to DSP library design
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems
On the use of VHDL-based behavioral synthesis for telecom ASIC design
Statistical Performance-Driven Module Binding in High-Level Synthesis
Memory Organization for Improved Data Cache Performance in Embedded Processors
Industrial experience using rule-driven retargetable code generation for multimedia applications
Panel Statement: System-Level Design: Designers' Wish List vs. Reality
Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications
Retargetable static timing analysis for embedded software
Derivation of Formal Representations from Process-Based Specification and Implementation Models
A specification invariant technique for operation cost minimisation in flow-graphs
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
Conditional speculation and its effects on performance and area for high-level snthesis
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters
A system level design methodology for the optimization of heterogeneous multiprocessors
System level verification of video and image processing specifications
Synchronization Detection for Multi-Process Hierarchical Synthesis
Scheduling Coarse-Grain Operations for VLIW Processors
Static resource models of instruction sets
Real-time systems specification and verification
Applications of attributed-behavior synthesis
Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines
Modeling Multicomputer Task Allocation as a Vector Packing Problem
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
Clustering for improved system-level functional partitioning
Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures
Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994
RTL semantics and methodology
System-level interconnect architecture exploration for custom memory organizations
Special Session: Security on SoC
A data scheduler for multi-context reconfigurable architectures
Array mapping in behavioral synthesis
HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
WWW based structuring of codesigns
Cache-efficient memory layout of aggregate data structures
Battery-Driven Dynamic Power Management of Portable Systems
Optimal register assignment to loops for embedded code generation
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture
Datapath Merging and Interconnection Sharing for Reconfigurable Architectures
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Energy/Power Estimation of Regular Processor Arrays
Instruction Scheduling for Clustered VLIW Architectures
Bus-Based Communication Synthesis on System-Level
Architectural Exploration and Optimization of Local Memory in Embedded Systems
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions
Modeling and simulation of steady state and transient behaviors for emergent SoCs
Requester-Aware Power Reduction
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization
Systematic Data Reuse Exploration Methodology for Irregular Access Patterns
Round-Robin Arbiter Design and Generation
A Framework for Scheduling and Context Allocation in Reconfigurable Computing
High-level automatic pipelining for sequential circuits
Intervals in Software Execution Cost Analysis
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Micro-Electromechanical Systems (MEMS): Miniaturization Beyond Microelectronics
Current consumption dynamics at instruction and program level for a VLIW DSP processor
Optimization of the Background Memory Utilization by Partitioning
Multiple-process behavioral synthesis for mixed hardware-software systems
On the Rapid Prototyping and Design of a Wireless Communication System on a Chip
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan
Conditional Scheduling for Embedded Systems using Genetic List Scheduling
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996
Code generation for a DSP processor
Data cache energy minimizations through programmable tag size matching to the applications
1995 high level synthesis design repository
Ensemble representation and techniques for exact control-dependent scheduling
Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs
Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign
Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System
Validation in a Component-Based Design Flow for Multicore SoCs
CodeSyn: a retargetable code synthesis system (abstract)
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
Is high-level synthesis marketable? (panel)
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units
Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems
Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999
Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator
Programming models for network processors (Panel)
Hardware/Software Partitioning with Iterative Improvement Heuristics
Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults
The standard SpecC language
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC design
Source code transformation based on software cost analysis
YAML: A Tool for Hardware Design Visualization and Capture
How datapath allocation affects controller delay
Embedded Java: Techniques and Applications
Embedded Java
Efficient Power Reduction Techniques for Time Multiplexed Address Buses
An Efficient Representation for Formal Synthesis
An optimal memory allocation for application-specific multiprocessor system-on-chip
An Adaptive Low-Power Transmission Scheme for On-Chip Networks
A Case Study of Hardware and Software Synthesis in ForSyDe
DSP Processor/Compiler Co-Design: A Quantitative Approach
Automatic Architectural Synthesis of VLIW and EPIC Processors
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design
Accelerating boolean satisfiability through application specific processing
Eliminating False Loops Caused by Sharing in Control Path
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis
Network processing in content inspection applications
Fast and Extensive System-Level Memory Exploration for ATM Applications
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System
System-Level Modeling of a Network Switch SoC
A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems
Incorporating Cores into System-Level Specification
Bit-alignment for retargetable code generators
System level optimization and design space exploration for low power
Lower Bound Estimation for Low Power High-Level Synthesis
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination
Breakpoints and Breakpoint Detection in Source Level Emulation
Real-time multi-tasking in software synthesis for information processing systems
Resource Constrained Modulo Scheduling with Global Resource Sharing
Architectures for One Billion of Transistors
OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors
Concurrent Error Detection at Architectural Level
Compiler Optimization on Instruction Scheduling for Low Power
IP Reuse in the System on a Chip Era
Considering power variations of DVS processing elements for energy minimisation in distributed systems
Layout-Driven RTL Binding Techniques for High-Level Synthesis
Time-constrained code compaction for DSPs
Loop Alignment for Memory Accesses Optimization
Specification of interface components for synchronous data paths
Concurrent testing in high-level synthesis
Mapping Array Communication onto FIFO Communication - Towards an Implementation
Data-Path Synthesis of VLIW Video Signal Processors
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
System-Level Design of IEEE1394 Bus Segment Bridge
A comprehensive estimation technique for high-level synthesis
Synthesis of system-level communication by an allocation-based approach
Efficient timing constraint derivation for optimal retiming high speed processing units
Low-Power Data Memory Communication for Application-Specific Embedded Processors
An Object-Oriented Design Process for System-on-Chip Using UML
Securing Wireless Data: System Architecture Challenges
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
A Visual Approach to Validating System Level Designs
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001
An algorithm for the allocation of functional units from realistic RT component libraries
Code Compression for VLIW Processors Using Variable-to-Fixed Coding
Synthesis of pipelined DSP accelerators with dynamic scheduling
On-line fault detection in a hardware/software co-design environment
A Comparison of Functional and Structural Partitioning
Efficient Simulation of Synthesis-Oriented System Level Designs
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
Proceedings of the 11th International Symposium on System Synthesis, ISSS '98, Hsinchu, Taiwan, December 2-4, 1998
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors
Modeling Assembly Instruction Timing in Superscalar Architectures
SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment
A divide-and-conquer approach for asynchronous interface synthesis
New Design Paradigms: What Needs to be Standardized?
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy
The Formal Execution Semantics of SpecC
System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Compressed Code Execution on DSP Architectures
Synthesising Controllers from Real-Time Specifications
Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design
Fine Grain Incremental Rescheduling Via Architectural Retiming
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation
Instruction set definition and instruction selection for ASIPs
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
Scheduling and resource binding for low power
Combined instruction and loop parallelism in array synthesis for FPGAs
An exact methodology for scheduling in a 3D design space
System-Level Abstraction Semantics
System Synthesis of Synchronous Multimedia Applications
APEX: Access Pattern Based Memory Architecture Exploration
SystemC: A Modeling Platform Supporting Multiple Design Abstractions
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
ASICs vs ASIPs (panel)
Interoperability as a design issue in C++ based modeling environments
Experiments with the Peripheral Virtual Component Interface
A Transformational Approach to Constraint Relaxation of a Time-driven Simulation Model
Bit-Width Selection for Data-Path Implementations
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques
System design of a telecommunication router
Memory Efficient Software Synthesis from Dataflow Graph
A methodology for simulation and synthesis of mixed hardware/software systems