yusuke1997/dblp-id-title huggingface dataset:
Adversarially-learned Image Transfer Model for Multi-content Disentanglement
Using real-time image enhancement technique to improve prostate capsula detection
News Category Classification via Multimodal Fusion Method
Optimal power reduction based on DVFS algorithm for video decoders
Design of data backup on distributed memory system based on key-value store using hot/cold data management
A reversible data hiding scheme based on histogram shifting using edge direction predictor
A study of the estimation of Stroke ASPECTS Scores based on NCCT brain scan images using deep learning
Selecting a Proper Neuromorphic Platform for the Intelligent IoT
Software similarity analysis based on dynamic stack usage patterns
A priority-based data placement method for databases using solid-state drives
Deep Learning Based End-to-End Specular Reflection Removal for Medical Endoscopic Images
An efficient visitation algorithm to improve the detection speed of high-interaction client honeypots
RTRP: right time right place kernel analysis tool
A case study of data transfer efficiency optimization for GPU- and infiniband-based clusters
Systematic monitoring of competitors' patents using 2-dimensional hybrid similarity method
Bypassing method for STT-RAM based inclusive last-level cache
Abnormal object detection and recognition in the complex construction site via cloud computing
Enhancing the security of IoT gateway based on the classification of user security-sensitive data
Viewer generated audio-visual communication system using Braille metaphor
Cross-layer design for optimal throughput of wireless networks
Optimized data transmission using cooperative devices in clustered D2D communication
Enterprise information systems: comparison of aspect-driven and MVC-like Approaches
PageRank in malware categorization
A Multi-Stream-aware DRAM Allocation Strategy inside Solid-State Drives (SSDs)
Research in Applied Computation Symposium, RACS '12, San Antonio, TX, USA, October 23-26, 2012
Memory hacking analysis in mobile devices for hybrid model of copyright protection for Android apps
Analysis of the effects of weight distribution on proportional share scheduling
More convenient more overhead: the performance evaluation of Hadoop streaming
MIPS CPU development with analogous teaching method for experimental teaching of digital logic and computer organization
A Virtual CPU Scheduling Model for I/O Performance in Paravirtualized Environments
Real-time vehicle detection using equi-height mosaicking image
Business Documentation Derivation from Aspect-driven Enterprise Information Systems
Block I/O Accelerator Technique to Improve Data Access Performance based Linux Multiple Disk
ScanMe mobile: a local and cloud hybrid service for analyzing APKs
Long Short-Term Memory Network (LSTM) based Stock Price Prediction
MetaService: an object transfer platform between Android applications
Towards in situ affect detection in mobile devices: a multimodal approach
An efficient soft decision decoding algorithm using cyclic permutations and compact genetic algorithm
A Comparison of Different Machine Learning Algorithms for Intrusion Detection
A secure QoS aware VANET
Data Oriented Blockchain: Off-Chain Storage with Data Dedicated and Prunable Transactions
Majority logic coding schemes performance over FSO channels
A game theoretic approach to multipath traffic control in Content-Centric Networking
A Framework to Secure Cluster-Header Decision in Wireless Sensor Network Using Blockchain
A secure cooperative transmission model in VANET using attribute based encryption
A reduced complexity decoder using compact genetic algorithm for linear block codes
On the Hamming and Symbol-Pair Distance of Constacyclic Codes of Length p s over $\mathbb {F}_{p^m}+ u\mathbb {F}_{p^m}$
Security in MANETs: The Blockchain Issue
Design and analysis of protecting strategies against border crossing under irregular conditions
Many-to-one matching game towards secure virtual machines migration in cloud computing
Turbo Decoder Based on DSC Codes for Multiple-Antenna Systems
A Weighted LSTM Deep Learning for Intrusion Detection
Review on using game theory in resource allocation for LTE/LTE-Advanced
Advanced Persistent Threat: New analysis driven by life cycle phases and their challenges
A novel efficient ultralightweight authentication algorithm for RFID systems
Novel method for improving performances of normalized MS decoder using WIMAX code
Information system security governance: Technology intelligence perspective
A comparative performance analysis of position estimation algorithms for GNSS localization in urban areas
A Threshold Decoding Algorithm for Non-binary OSMLD Codes
Intrusion detection system using PCA and Fuzzy PCA techniques
ICH-LEACH: An enhanced LEACH protocol for wireless sensor network
Performance analysis of random access mechanisms for machine type communications in LTE networks
Designing optimal wireless-based ICT platform for smart grid - CDMA450 proof-of-concept
Improving IoT Security with Software Defined Networking (SDN)
Improving GGH cryptosystem using generalized low density lattices
Threshold of the symmetry property of cyclic autocorrelation function detector
Sparse deconvolution of periodic random impulses based on convex relaxation
International Conference on Advanced Communication Systems and Information Security, ACOSIS 2016, Marrakesh, Morocco, October 17-19, 2016
NCBP: Network Coding Based Protocol for Recovering Lost Packets in the Internet of Things
Proposed Solution for HID Fileless Ransomware Using Machine Learning
A survey on decentralized random access MAC protocols for cognitive radio networks
Advanced Communication Systems and Information Security - Second International Conference, ACOSIS 2019, Marrakesh, Morocco, November 20-22, 2019, Revised Selected Papers
Performance analysis of dual-hop underwater communication system subject to k-μ shadowed fading channel
Field study of cybercafe usage & security in Morocco
Pilot Assignment vs Soft Pilot Reuse to Surpass the Pilot Contamination Problem: A Comparative Study in the Uplink Phase
Convolutional Neural Networks for Traffic Signs Recognition
Correction of sensing imperfections using channel coding in cognitive radio networks while keeping sensing time low
Multi-party WebRTC as a Managed Service over Multi-Operator SDN
Optical Image Encryption Process Using Triple Deterministic Spherical Phase Masks Array
Authentication protocol conforming to EPC class-1 Gen-2 standard
Design of good linear codes for a decoder based on majority voting procedure
Multi-user techniques in visible light communications: A survey
Topology-aware approach for reducing power consumption in LEO satellite constellations
A new performance results of MIMO system with orthogonal STBC over independent and identical weibull fading channels
Non-binary Euclidean Geometry codes: Majority Logic Decoding
New Channel Estimation for MC-CDMA System Under Fast Multipath Channel
Non-binary cyclic majority-logic decodable codes: An algebraic construction by using Genetic Algorithms
Vehicle Collision Avoidance
Construction and iterative threshold decoding for low rates Quasi-Cyclic One Step Majority logic decodable codes
LTE-a pro (4.5G) as pre-phase for 5G deployment: Closing the gap between technical requirements and network performance
Epigenetic algorithm for performing intrusion detection system
On the V2X Velocity Synchronization at Unsignalized Intersections: Right Hand Priority Based System
New decoder for linear block codes
Performance analysis of TAS/MRC based MIMO systems over Weibull fading channels
Energy efficient and scalable D2D architecture design for public safety network
Iterative Decoding of GSCB Codes Based on RS Codes Using Adapted Scaling Factors
An Efficient Semi-Algebraic Decoding Algorithm for Golay Code
Understanding contention-based channels and using them for defense
Origin-Based Fault-Tolerant routing in the Mesh
HoPP: Hardware-Software Co-Designed Page Prefetching for Disaggregated Memory
DVFS for NoCs in CMPs: A thread voting approach
CHOPPER: A Compiler Infrastructure for Programmable Bit-serial SIMD Processing Using Memory in DRAM
Efficient GPU hardware transactional memory through early conflict resolution
Extreme scale computing: Challenges and opportunities
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), Raleigh, North Carolina, USA, January 22-25, 1995
GPGPU performance and power estimation using machine learning
Baldur: A Power-Efficient and Scalable Network Using All-Optical Switches
Q-Zilla: A Scheduling Framework and Core Microarchitecture for Tail-Tolerant Microservices
Illusionist: Transforming lightweight cores into aggressive cores on demand
Call Graph Prefetching for Database Applications
FxHENN: FPGA-based acceleration framework for homomorphic encrypted CNN inference
Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors
16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 9-14 January 2010, Bangalore, India
Efficient synthetic traffic models for large, complex SoCs
PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator
eXtended Block Cache
PROCA: Programmable Probabilistic Processing Unit Architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference
Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE
IRIS: Unleashing ISP-Software Cooperation to Optimize the Machine Vision Pipeline
A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit
QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues
DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture
New architectures for a new biology
Checkpointed Early Load Retirement
DockerSSD: Containerized In-Storage Processing and Hardware Acceleration for Computational SSDs
High-Throughput Coherence Controllers
Quantifying sources of error in McPAT and potential impacts on architectural studies
The Impact of Data Transfer and Buffering Alternatives on Network Interface Design
The common case transactional behavior of multithreaded programs
Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking
10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain
Illustrative Design Space Studies with Microarchitectural Regression Models
The SimpleScalar tool set as an instructional tool: experiences and future directions
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores
SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator
Dragonfly+: Low Cost Topology for Scaling Datacenters
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores
Using Psychophysics to Guide Power Adaptation for Input Methods on Mobile Architectures
Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity
Maximizing Cache Performance Under Uncertainty
throttLL'eM: Predictive GPU Throttling for Energy Efficient LLM Inference Serving
Criticality-based optimizations for efficient load processing
Runahead Threads to improve SMT performance
DRAIN: Deadlock Removal for Arbitrary Irregular Networks
Improving Value Communication for Thread-Level Speculation
Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon?
How to implement effective prediction and forwarding for fusable dynamic multicore architectures
A Performance Comparison of Homeless and Home-Based Lazy Release Consistency Protocols in Software Shared Memory
BRB: Mitigating Branch Predictor Side-Channels
A Performance Comparison of Hierarchical Ring- and Mesh-Connected Multiprocessor Networks
Energy-efficient address translation
Trace Cache Redundancy: Red & Blue Traces
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
BM-Store: A Transparent and High-performance Local Storage Architecture for Bare-metal Clouds Enabling Large-scale Deployment
MP3: Minimizing performance penalty for power-gating of Clos network-on-chip
Undersubscribed threading on clustered cache architectures
FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference
Application-Level Correctness and its Impact on Fault Tolerance
Partial Sampling with Reverse State Reconstruction: A New Technique for Branch Predictor Performance Estimation
LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration
Stream Register Files with Indexed Access
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework
Rambda: RDMA-driven Acceleration Framework for Memory-intensive µs-scale Datacenter Applications
Record-Replay Architecture as a General Security Framework
Power-performance co-optimization of throughput core architecture using resistive memory
An approach for implementing efficient superscalar CISC processors
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters
Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?
Coherence Communication Prediction in Shared-Memory Multiprocessors
EDA: Energy-Efficient Inter-Layer Model Compilation for Edge DNN Inference Acceleration
User-Level DMA without Operating System Kernel Modification
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
Cottage: Coordinated Time Budget Assignment for Latency, Quality and Power Optimization in Web Search
Third Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC '99)
Out-of-Order Commit Processors
C-Oracle: Predictive thermal management for data centers
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system
Program Balance and Its Impact on High Performance RISC Architectures
Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling
High-Performance low-vcc in-order core
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems
High-Performance GPU Transactional Memory via Eager Conflict Detection
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
A Computational Stack for Cross-Domain Acceleration
Making Memristive Neural Network Accelerators Reliable
Tessel: Boosting Distributed Execution of Large DNN Models via Flexible Schedule Search
High Performance and Power Efficient Accelerator for Cloud Inference
No Rush in Executing Atomic Instructions
Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management
Inter-Cluster Communication Models for Clustered VLIW Processors
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design
Link-Time Path-Sensitive Memory Redundancy Elimination
Mascot: Predicting Memory Dependencies and Opportunities for Speculative Memory Bypassing
GPU Scale-Model Simulation
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Disintegrated control for energy-efficient and heterogeneous memory systems
Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning
Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model
HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures
Practical and secure PCM systems by online detection of malicious write streams
LIBRA: Clearing the Cloud Through Dynamic Memory Bandwidth Management
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs
An OS-based alternative to full hardware coherence on tiled CMPs
FADE: A programmable filtering accelerator for instruction-grain monitoring
Correction prediction: Reducing error correction latency for on-chip memories
Practical data value speculation for future high-end processors
Domain knowledge based energy management in handhelds
Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology
Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction
Guser: A GPGPU Power Stressmark Generator
Priority-based cache allocation in throughput processors
TSOPER: Efficient Coherence-Based Strict Persistency
SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads
Gemina: A Coordinated and High-Performance Memory Deduplication Engine
MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks
Accelerating and Adapting Precomputation Threads for Effcient Prefetching
Non-Stalling CounterFlow Architecture
Characterizing Resource Sensitivity of Database Workloads
How's the parallel computing revolution going?
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications
Faster Schrödinger-style simulation of quantum circuits
Construction and use of linear regression models for processor performance analysis
Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration
AB-ORAM: Constructing Adjustable Buckets for Space Reduction in Ring ORAM
INCA: Input-stationary Dataflow at Outside-the-box Thinking about Deep Learning Accelerators
SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters
TensorFHE: Achieving Practical Computation on Encrypted Data Using GPGPU
BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks
IEEE International Symposium on High-Performance Computer Architecture, HPCA 2024, Edinburgh, United Kingdom, March 2-6, 2024
ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism
Unlocking bandwidth for GPUs in CC-NUMA systems
ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
A Prefetching Technique for Irregular Accesses to Linked Data Structures
MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores
Interconnect-Centric Computing
NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories
Early Visibility Resolution for Removing Ineffectual Computations in the Graphics Pipeline
LAPSES: A Recipe for High Performance Adaptive Router Design
Timing channel protection for a shared memory controller
The Best of IEEE Computer Architecture Letters in 2018
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared Memory
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
Cheetah: Optimizing and Accelerating Homomorphic Encryption for Private Inference
Gables: A Roofline Model for Mobile SoCs
FlexiTaint: A programmable accelerator for dynamic taint propagation
EXCES: External caching in energy saving storage systems
Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
Domino Temporal Data Prefetcher
DigiQ: A Scalable Digital Controller for Quantum Computers Using SFQ Logic
IEEE International Symposium on High-Performance Computer Architecture, HPCA 2022, Seoul, South Korea, April 2-6, 2022
RiF: Improving Read Performance of Modern SSDs Using an On-Die Early-Retry Engine
Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers
OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing
StimulusCache: Boosting performance of chip multiprocessors with excess cache
Hercules: Heterogeneity-Aware Inference Serving for At-Scale Personalized Recommendation
Towards Efficient Microarchitectural Design for Accelerating Unsupervised GAN-Based Deep Learning
Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems
Hardware-software integrated approaches to defend against software cache-based side channel attacks
IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021
Speculative synchronization and thread management for fine granularity threads
CARE: Coordinated Augmentation for Elastic Resilience on DRAM Errors in Data Centers
Are Superpages Super-fast? Distilling Flash Blocks to Unify Flash Pages of a Superpage in an SSD
LegoZK: A Dynamically Reconfigurable Accelerator for Zero-Knowledge Proof
Scaling distributed cache hierarchies through computation and data co-scheduling
CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
Ditto: Accelerating Diffusion Model via Temporal Value Similarity
The Future of Computer Architecture Research: An Industrial Perspective
unXpec: Breaking Undo-based Safe Speculation
Thread block compaction for efficient SIMT control flow
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
RADAR: Runtime-assisted dead region management for last-level caches
PABST: Proportionally Allocated Bandwidth at the Source and Target
A scalable multi-path microarchitecture for efficient GPU control flow
Abusing Cache Line Dirty States to Leak Information in Commercial Processors
A Scalable Priority-Aware Approach to Managing Data Center Server Power
Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
Adaptive Spill-Receive for robust high-performance caching in CMPs
Intel's Tera-scale Computing Project: The first five years, the next five years
Control Flow Speculation in Multiscalar Processors
An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science Application
The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors
Hardware Support for Prescient Instruction Prefetch
Rethinking Dead Block Prediction for Intermittent Computing
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
Understanding Scheduling Replay Schemes
GADGETSPINNER: A New Transient Execution Primitive Using the Loop Stream Detector
Organizing the Last Line of Defense before Hitting the Memory Wall for CMP
SafeGuard: Reducing the Security Risk from Row-Hammer via Low-Cost Integrity Protection
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Pliant: Leveraging Approximation to Improve Datacenter Resource Efficiency
A detailed GPU cache model based on reuse distance theory
Strategies for anticipating risk in heterogeneous system design
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
AI-Enabling Workloads on Large-Scale GPU-Accelerated System: Characterization, Opportunities, and Implications
Shared last-level TLBs for chip multiprocessors
A Framework for Statistical Modeling of Superscalar Processor Performance