yusuke1997/dblp-id-title huggingface dataset:
An Object-Oriented Kernel for an Integrated Design and Process Planning System
Multiple output minimization
Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace Algorithms
A version-based strategy for reliability enhancement of flash file systems
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly Prediction
Reducing the number of lines in reversible circuits
Basejump STL: systemverilog needs a standard template library for hardware design
A layout checking system for large scale integrated circuits
Extending Moment Computation to 2-Port Circuit Representations
A minimum-impact routing algorithm
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators
Prediction of wiring space requirements for LSI
Design Management Based on Design Traces
Low power passive equalizer optimization using tritonic step response
Challenges in a future IP/ethernet-based in-car network for real-time applications
An analytical approach for dynamic range estimation
A2-ILT: GPU accelerated ILT with spatial attention mechanism
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
A Statistical Performance Simulation Methodology for VLSI Circuits
Time-Predictable Computing by Design: Looking Back, Looking Forward
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique
STREAM: Spatiotemporal Similarity-based Efficient Approximate Median with Tunable Granularity
Interconnect Estimation and Dlanning for Deep Submicron Designs
A hierarchical approach for layout versus circuit consistency check
Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E Systems
Circuit techniques for dynamic variation tolerance
Automatic Functional Test Generation Using the Extended Finite State Machine Model
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions
The IBM Engineering Verification Engine
Interactive graphics for schematic editing, a working tool
Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning
MTJ variation monitor-assisted adaptive MRAM write
System prototypes: virtual, hardware or hybrid?
A multi-contouring algorithm
Path based buffer insertion
INVITED: New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design
An O(nlogm) Algorithm for VLSI Design Rule Checking
A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems
Nanometer design: what hurts next...?
High-performance hardware monitors to protect network processors from data plane attacks
Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation
Two-dimensional compaction by "zone refining"
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs
The Use of CAD Frameworks in a CIM Environment
SNAPPIX: Efficient-Coding-Inspired In-Sensor Compression for Edge Vision
Late Breaking Results: A Neural Network that Routes ICs
The role of engineering in the evolving technology/automation interface
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I
Lessons in Language Design: Cost/Benefit analysis of VHDL Features
LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems
Automatic Verification of Floating Point Units
Leopard: Hardware Pass-Through Remote Storage Access with Queue Concurrency for Edge Intelligent Workstations
A General Method for Compiling Event-Driven Simulations
Cost effective data entry techniques for design automation
An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data
Unrolling and retiming of stream applications onto embedded multicore processors
Requirements-Based Design Evaluation
Test generation games from formal specifications
Pre-silicon security verification and validation: a formal perspective
A proper model for the partitioning of electrical circuits
Advanced timing analysis based on post-OPC extraction of critical dimensions
Dynamic river network simulation at large scale
MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach
Thousand Core ChipsA Technology Perspective
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits
Role of the verification team throughout the ASIC development life cycle
A dual-core 64b ultraSPARC microprocessor for dense server applications
The State of Simulation in Russia
Coupling graphics and circuit analysis techniques
Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits
NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era
Classifying Computations on Multi-Tenant FPGAs
Canonical computation without canonical representation
A laminate design system
Nomadic platform approach for wireless mobile multimedia
St-DRC: Stretchable DRAM Refresh Controller with No Parity-overhead Error Correction Scheme for Energy-efficient DNNs
Adaptive power management of on-chip video memory for multiview video coding
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system
Testing Strategies for the 1990's (Panel Abstract)
Memory Modeling in ESL-RTL Equivalence Checking
Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation
Chairman's introduction
Test generation systems in Japan
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List
Statistical timing analysis based on a timing yield model
Transistor-level test generation for physical failures in CMOS circuits
Patchwork: Layout from Schematic Annotations
Invited: Leveraging Machine Learning for Quantum Compilation Optimization
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search
Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR
DAG-aware logic synthesis of datapaths
Cross-layer fault-space pruning for hardware-assisted fault injection
Runtime monitoring for safety of intelligent vehicles
High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods
Performance of algorithms for initial placement
KINSYN: A minicomputer-based interactive mechanism design system
Navigator: Dynamic Multi-kernel Scheduling to Improve GPU Performance
Pin assignment on a printed circuit board
The Validity of Retiming Sequential Circuits
Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling
Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design
A Configuration Management System in a Data Management Framework
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
Workshop - industrial robotics
Smart non-default routing for clock power reduction
PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning
CAD Framework Initiative - A User Perspective
ROLoad: Securing Sensitive Operations with Pointee Integrity
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing
A minicomputerized automatic layout system for two-layer printed wiring boards
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
Automatic layout for gate arrays with one layer of metal
Exploiting "architecture for verification" to streamline the verification process
Is methodology the highway out of verification hell?
A knowledge based planning system for mechanical assembly usign robots
Operating system based software generation for systems-on-chip
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
Invited: Caching in Automated Data Centric Vehicles for Edge Computing Scenarios
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
Ternary logic in digital computers
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems
COMP: A VHDL Composition System
Hypermedia-Aided Design
Web-based frameworks to enable CAD RD (abstract)
A new circuit placement program for FET chips
A Description Language for Design Process Management
PRES: pseudo-random encoding scheme to increase the bit flip reduction in the memory
Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
A hierarchical gate array architecture and design methodology
Test strategy for microprocessers
COSY communication IP's
Proceedings of the SHARE design automation workshop, DAC '64, Cambridge, Massachusetts, USA, May 6-7, 1964
ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-Cores
Combine and top down block placement algorithm for hierarchical logic VLSI layout
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
GuardNN: secure accelerator architecture for privacy-preserving deep learning
The basis of design tools for quantum computing: arrays, decision diagrams, tensor networks, and ZX-calculus
Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors
Efficient SAT-based Boolean matching for FPGA technology mapping
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency
A hiererachical, error-tolerant compactor
Rainbow: An integrated CAD system
Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks
A measurement system for capacitive PUF-based security enclosures
A new hybrid FPGA with nanoscale clusters and CMOS routing
An effective capacitance based driver output model for on-chip RLC interconnects
Developing a Concurrent Methodology for Standard-Cell Library Generation
Find your flow: increasing flow experience by designing "human" embedded systems
An analytical method for compacting routing area in integrated circuits
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model
Simulating and controlling the effects of transmission line impedance mismatches
STM concurrency control for embedded real-time software with tighter time bounds
Future Performance Challenges in Nanometer Design
AdreamDCO: AI-Driven Robust and Efficient Design Automation for Digitally Controlled Oscillators
Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs
Transformer: a functional-driven cycle-accurate multicore simulator
SoC Integration of Reusable Baseband Bluetooth IP
Domain wall memory based digital signal processors for area and energy-efficiency
Are carbon nanotubes the future of VLSI interconnections?
Parasitic Extraction Accuracy - How Much is Enough?
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology
PARR: pin access planning and regular routing for self-aligned double patterning
Late Breaking Results: Can You Hear Me? Towards an Ultra Low-Cost Hearing Screening Device
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems
HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
TraPL: Track Planning of Local Congestion for Global Routing
Improving LUT-based optimization for ASICs
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates
Eliminating Redundant Computation in Noisy Quantum Computing Simulation
Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection
A novel layout decomposition algorithm for triple patterning lithography
PicoCube: a 1 cm 3 sensor node powered by harvested energy
CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer Systems
The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers
Word Level Model Checking - Avoiding the Pentium FDIV Error
An Improved Systematic Method for Constructing Systolic Arrays from Algorithms
Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System
On Test Set Preservation of Retimed Circuits
Automating the design of an asynchronous DLX microprocessor
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns
XPert: Peripheral Circuit & Neural Architecture Co-search for Area and Energy-efficient Xbar-based Computing
Behavioral Modeling of Transmission Gates in VHDL
GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs
ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications
Human computing for EDA
Synthesis of concurrent modular controllers from algorithmic descriptions
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs
Holistic Design towards Resource-Stringent Binary Vector Symbolic Architecture
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation
The Cell Design System
POLAR 2.0: An Effective Routability-Driven Placer
The Social Implications of Computerization: Making the Technology Humane
SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process
Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks
A low cost plotting system for generating electrical/electronic drawings
Clustering Based Simulated Annealing for Standard Cell Placement
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
Ultra Low-Power implementation of ECC on the ARM Cortex-M0+
3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNs
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits
Frequency-Domain Compatibility in Digital Filter BIST
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators
Versions and Change Notification in an Object-Oriented Database System
HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits
Functional models for VLSI design
Optimal layout of CMOS functional arrays
Serial Fault Emulation
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies
A Video Signal Processor for MIMD Multiprocessing
Design automation and the WRAP System
High-Level Synthesis: Technology Transfer to Industry
DriverJar: Lightweight Device Driver Isolation for ARM
ZION: A Practical Confidential Virtual Machine Architecture on Commodity RISC-V Processors
Estimating software development schedules and costs
Vertical Benchmarks for CAD
VIA Minimization by Layout Modification
Yield-driven iterative robust circuit optimization algorithm
Use of lithography simulation for the calibration of equation-based design rule checks
An approach to program verification
TSAcc: An Efficient \underline{T}empo-\underline{S}patial Similarity Aware \underline{Acc}elerator for Attention Acceleration
An Approach to Symbolic Timing Verification
A Compaction Method for Full Chip VLSI Layouts
The Yorktown Simulation Engine
A methodology for formal design of hardware control with application to cache coherence protocols
The incorporation of functional level element routines into an existing digital simulation system
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time
A layout verification system for analog bipolar integrated circuits
Microprocessor systems modeling with MODLAN
Application of a logic fault analyzer to the manufacture and maintenance of the CONTROL DATA 7600 computer
BREL - a Prolog Knowledge-based System Shell for VLSI CAD
Symbolic Layout Compaction Review
A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures
Optimizations for a simulator construction system supporting reusable components
An implication-based method to detect multi-cycle paths in large sequential circuits
The VHDL Validation Suite
Towards graceful aging degradation in NoCs through an adaptive routing algorithm
Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation
Signal integrity fault analysis using reduced-order modeling
BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing
PRONTO: Quick PLA product reduction
What is Design for Manufacturability (DFM)? (Panel Abstract)
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC
DeepN-JPEG: a deep neural network favorable JPEG-based image compression framework
Logic Minimization using Exclusive OR Gates
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard
Test generation for scan design circuits with tri-state modules and bidirectional terminals
An Investigation of Power Delay Trade-Offs on PowerPC Circuits
SPIDER - a Computer Aided Manufacturing Network
Design Automation for Cryogenic CMOS Circuits
A Vector Hardware Accelerator with Circuit Simulation Emphasis
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs
Area optimization of resilient designs guided by a mixed integer geometric program
Modeling the site planning of homogeneous uses
Period Optimization for Hard Real-time Distributed Automotive Systems
Fault-test analysis techniques based on logic simulation
Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulation
A generalized network flow based algorithm for power-aware FPGA memory mapping
A logic design front-end for improved engineering productivity
Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration
The design of program logic
Dynamic and deductive fault simulation
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures
Knowlege-based expert systems and their application (tutorial session
Gate assignment and pack placement: Two approaches compared
Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams
SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors
Topology synthesis of analog circuits based on adaptively generated building blocks
A Data Path Synthesis Method for Self-Testable Designs
Corolla Based Circuit Partitioning and Resynthesis
Deadlock analysis in the design of data-flow circuits
Verifying really complex systems: on earth and beyond
Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms
Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization
RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs
Massively parallel processing: it's déjà vu all over again
The wearable motherboard: a framework for personalized mobile information processing (PMIP)
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations
The design of a low power carbon nanotube chemical sensor system
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Industrial experience with test generation languages for processor verification
Behavioral Synthesis Techniques for Intellectual Property Protection
Effective Iterative Techniques for Fingerprinting Design IP
IRSIM: An Incremental MOS Switch-Level Simulator
Obfuscated Priority Assignment to CAN-FD Messages with Dependencies: A Swapping-based and Affix-Matching Approach
Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips
Symbolic Simulation - Techniques and Applications
Architecting Dynamic Power Management to be Formally Verifiable
The value of digital printer plotting in ship design
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond
TrojDRL: Evaluation of Backdoor Attacks on Deep Reinforcement Learning
Automatic ECL LSI design
Fast and precise routability analysis with conditional design rules
Formal verification: is it real enough?
Proud: A Fast Sea-of-Gates Placement Algorithm
Architectural Whispers: Robust Machine Learning Models Fingerprinting via Frequency Throttling Side-Channels
A Hierarchy-Driven FPGA Partitioning Method
Non-uniform DNN Structured Subnets Sampling for Dynamic Inference
Exploring the Heterogeneous Design Space for both Performance and Reliability
No Compromises: Secure NVM with Crash Consistency, Write-Efficiency and High-Performance
VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
Catching the flu: emerging threats from a third party power management unit
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
A layout-based approach for multiple event transient analysis
Techniques for fully integrated intra-/inter-chip optical communication
Multiply indexed data management
Electrical artificial skin using ultraflexible organic transistor
Optimal Synthesis of Multi-Controlled Qudit Gates
Reaction Time Analysis of Event-Triggered Processing Chains with Data Refreshing
Floss: An approach to automated layout for high-volume designs
A defect tolerance framework for improving yield
"An interactive system for semi-automatic artwork generation of printed circuit boards"
Neural Barrier Certificates Synthesis of NN-Controlled Continuous Systems via Counterexample-Guided Learning
Functional Verification of the Equator MAP1000 Microprocessor
High-Level Transformations for Minimizing Syntactic Variances
Routing of printed circuit boards
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow
SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks
Design of a graphic processor for computer-aided drafting
VLSI Circuit Testing Using an Adaptive Optimization Model
Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design
HDL Optimization Using Timed Decision Tables
Non-uniform multilevel analog routing with matching constraints
Algorithms and data structures for fast and good VLSI routing
Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance
A tool for describing and evaluating hierarchical real-time bus scheduling policies
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon
Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval
Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis
PIMoE: Towards Efficient MoE Transformer Deployment on NPU-PIM System through Throttle-Aware Task Offloading