yusuke1997/dblp-id-title huggingface dataset:
PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Medical cyber physical systems
A new routing algorithm and its hardware implementation
Mixed- V th (MVT) CMOS Circuit Design Methodology for Low Power Applications
Figures of Merit to Characterize the Importance of On-Chip Inductance
Temperature management in multiprocessor SoCs using online learning
Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming
MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba Models
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS
Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis
DWE: decrypting learning with errors with errors
Accelerators for biologically-inspired attention and recognition
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Generic low-cost characterization of V th and mobility variations in LTPS TFTs for non-uniformity calibration of active-matrix OLED displays
Automating the Design of Electronic Packaging (tutorial)
Using embedded FPGAs for SoC yield improvement
BlockPIM: Optimizing Memory Management for PIM-enabled Long-Context LLM Inference
The application software engineering tool
Silicon Speedpath Measurement and Feedback into EDA flows
Nanowire-aware routing considering high cut mask complexity
Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning
Can we go towards true 3-D architectures?
Tunneling and slicing: towards scalable BMC
Multi-variable Dynamic Power Management for the GPU Subsystem
Architecting DDR5 DRAM caches for non-volatile memory systems
Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction
Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age
Timing analysis for nMOS VLSI
Associative caches in formal software timing analysis
The social implications of computers and automation
Routability-driven placement for hierarchical mixed-size circuit designs
Does IC design have a future in the clouds?
Statistical Error Analysis for Low Power Approximate Adders
Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays
ReTagger: An Efficient Controller for DRAM Cache Architectures
A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications
A syntax-directed logic simulator
Multi-order Differential Neural Network for TCAD Simulation of the Semiconductor Devices
Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs
A structured approach to selecting a CAD/CAM system
HWST128: complete memory safety accelerator on RISC-V with metadata compression
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
Xplace: an extremely fast and extensible global placement framework
On the convergence of mainstream and mission-critical markets
Variation Aware Cache Partitioning for Multithreaded Programs
Optimum and Heuristic Data Path Scheduling Under Resource Constraints
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization
Systematic development of analog circuit structural macromodels through behavioral model decoupling
Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration
ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects
A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model
ICARUS: An interactive integrated circuit layout program
Logic block clustering of large designs for channel-width constrained FPGAs
Future directions for DA machine research (panel session)
Balloon-ZNS: Constructing High-Capacity and Low-Cost ZNS SSDs with Built-in Compression
Hierarchical Sequence Compaction for Power Estimation
Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems
Space efficient algorithms for VLSI artwork analysis
From milliwatts to megawatts: system level power challenge
Compositional verification of retiming and sequential optimizations
An AIG-Based QBF-solver using SAT for preprocessing
Compaction of a Routed Channel on the Connection Machine
Silicon compilation-a hierarchical use of PLAs
Current problems related to LSI functional testing
Energy Characterization based on Clustering
Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networks
Don't-Care-Based Node Minimization for Threshold Logic Networks
Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory
Temperature-aware resource allocation and binding in high-level synthesis
SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre Attacks
Automatic abstraction and verification of verilog models
Leveraging FDSOI through body bias domain partitioning and bias search
Hierarchical decoding of double error correcting codes for high speed reliable memories
From myth to methodology: cross-layer design for energy-efficient wireless communication
Logic Design System
The Design Automation Standards Environment
Property-driven Automatic Generation of Reduced-ISA Hardware
The semi-automatic generation of processing element control paths for highly parallel machines
A combined force and cut algorithm for hierarchical VLSI layout
RADAR : a case for retention-aware DRAM assembly and repair in future FGR DRAM memory
Design Automation - a perspective (Position Paper)
A novel synthesis approach for active leakage power reduction using dynamic supply gating
Multiple-detect ATPG based on physical neighborhoods
Choosing flows and methodologies for SoC design
NobLSM: an LSM-tree with non-blocking writes for SSDs
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer
RAMP: resource-aware mapping for CGRAs
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Efficient Continuous Logic Optimization with Diffusion Model
Verbal and graphical language for the AED system: A progress report
A design rule database system to support technology-adaptable applications
Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead
Battery lifetime-aware automotive climate control for electric vehicles
SAPO: Improving the Scalability and Accuracy of Quantum Linear Solver for Portfolio Optimization
Planaria: Pattern Directed Cross-page Composite Prefetcher
Enabling union page cache to boost file access performance of NVRAM-based storage device
Design and Synthesis of Array Structured Telecommunication Processing Applications
Optimal jumper insertion for antenna avoidance under ratio upper-bound
PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors
FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness
Sequential Synthesis for Table Look Up Programmable Gate Arrays
Hardware acceleration of gate array layout
FPGA-TrustZone: Security Extension of TrustZone to FPGA for SoC-FPGA Heterogeneous Architecture
Intermittent Inference with Nonuniformly Compressed Multi-Exit Neural Network for Energy Harvesting Powered Devices
Efficient placement and routing techniques for master slice LSI
Transient Simulation of Lossy Interconnect
Towards variation-aware system-level power estimation of DRAMs: an empirical approach
Graphic display techniques in the automated interconnection process
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder
TLM: Crossing Over From Buzz To Adoption
Introduction to stochastic computing and its challenges
A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification
Pauli Frames for Quantum Computer Architectures
Exploiting finite precision information to guide data-flow mapping
Distributed Application Development with Inferno
PDS: pseudo-differential sensing scheme for STT-MRAM
TATOO: A Flexible Hardware Platform for Binary-Only Fuzzing
DimNoC: a dim silicon approach towards power-efficient on-chip network
Robust Design of Large Area Flexible Electronics via Compressed Sensing
Sustainable data centers: enabled by supply and demand side management
Cryogenic In-Memory Matrix-Vector Multiplication using Ferroelectric Superconducting Quantum Interference Device (FE-SQUID)
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory
A New Approach to the Pin Assignment Problem
CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Hybrid Embedding Framework for Memory-Efficient Recommendation Systems
Relays do not leak: CMOS does
FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events
Efficiency attacks on spiking neural networks
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability
An Algorithm for Bi-Decomposition of Logic Functions
Variational delay metrics for interconnect timing analysis
System Design Methodology of UltraSPARC-I
TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs
An approach to gate assignment and module placement for printed wiring boards
FPGA technology mapping: a study of optimality
Solving traveling salesman problems via a parallel fully connected ising machine
Guaranteed passive balancing transformations for model order reduction
OLLS: The On-Line Logical Simulation System
Automated design of self-adjusting pipelines
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient Processor
Transaction level statistical analysis for efficient micro-architectural power and performance studies
Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip
Maximizing Performance by Retiming and Clock Skew Scheduling
Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits
Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks
A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
A current driven routing and verification methodology for analog applications
Holistic verification: myth or magic bullet?
Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference
Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis
mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices
Practical results with CADSYS
Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications
GRASP: A Grammar-based Schematic Parser
SMApproxlib : library of FPGA-based approximate multipliers
Simultaneous analog placement and routing with current flow and current density considerations
Global Critical Path: A Tool for System-Level Timing Analysis
MAP: A user-controlled automated Mask Analysis Program
Design for Verification in System-level Models and RTL
Low Power CMOS Design Strategies
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs
Implementing asynchronous circuits using a conventional EDA tool-flow
A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration
Rapid estimation of control delay from high-level specifications
Hardware Compilation for FPGA-Based Configurable Computing Machines
GreenBus: a generic interconnect fabric for transaction level modelling
LAWN: boosting the performance of NVMM file system through reducing write amplification
Lower power by voltage stacking: a fine-grained system design approach
Automatic trace analysis for logic of constraints
Incremental exploration of the combined physical and behavioral design space
Enabling efficient deep convolutional neural network-based sensor fusion for autonomous driving
Lightning Talk: Private and Secure Edge AI with Hyperdimensional Computing
An electronic design interchange format
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity
An Interactive Graphics System for custom design
PIPF-DRAM: processing in precharge-free DRAM
An architecture for application of artificial intelligence to design
Fault Simulation under the Multiple Observation Time Approach using Backward Implications
The Attributed-Behavior Abstraction and Synthesis Tools
A concurrent pattern operation algorithm for VLSI mask data
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only)
FlashGPU: Placing New Flash Next to GPU Cores
A semantics-aware design for mounting remote sensors on mobile systems
CMOST: a system-level FPGA compilation framework
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY
3D-Adv: Black-Box Adversarial Attacks against Deep Learning Models through 3D Sensors
Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space Exploration
Power grid physics and implications for CAD
Relational and entity-relationship model databases and specialized design files in VLSI design
Parameterized Macromodeling for Analog System-Level Design Exploration
IP Protection in TinyML
Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning
Improving compute in-memory ECC reliability with successive correction
Improved indexing for cache miss reduction in embedded systems
Mitigating the impact of faults in unreliable memories for error-resilient applications
Optimal order of the VLSI IC testing sequence
Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing
What happened to ASIC?: Go (recon)figure?
Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems
Fast Performance Estimation and Design Space Exploration of Manycore-based Neural Processors
A rule-based logic circuit synthesis system for CMOS gate arrays
Computer Aided Software Engineering (CASE)
X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks
Synthesis of Instruction Sets for Pipelined Microprocessors
Bandwidth-efficient deep learning
Control theory-based DVS for interactive 3D games
Sizing Synchronization Queues: A Case Study in Higher Level Synthesis
Late Breaking Results: COPPER: Computation Obfuscation by Producing Permutations for Encoding Randomly
Deep Reinforcement Learning for Building HVAC Control
Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design Methodologies
VVDS: A Verification/Diagnosis System for VHDL
Improving testability and soft-error resilience through retiming
Solving the latch mapping problem in an industrial setting
Functional ECO Using Metal-Configurable Gate-Array Spare Cells
Flow engineering for physical implementation: theory and practice
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment
Contrasts in physical design between LSI and VLSI
EST: The New Frontier in Automatic Test-Pattern Generation
ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization
Application design within the system for business automation (SBA)
Data Path Allocation Based on Bipartite Weighted Matching
ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference
An Adaptive Timing-Driven Layout for High Speed VLSI
Interconnect and noise immunity design for the Pentium 4 processor
Leakage-and crosstalk-aware bus encoding for total power reduction
Full-Chip Verification Methods for DSM Power Distribution Systems
A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification
A data architecture for an uncertain design and manufacturing environment
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism
Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search
Digital simulation for control system design
Global Scheduling Independent of Control Dependencies Based on Condition Vectors
The VIVID system approach to technology independence: the matster technology file system
Router system for printed wiring boards of very high-speed, very large-scale computers
Quantum logic synthesis by symbolic reachability analysis
Memory Exploration for Low Power, Embedded Systems
Physical design and manufacturing information aspects aspects of the AT & T bell laboratories CAD system
Automated hardware-independent scenario identification
R-TOSS: A Framework for Real-Time Object Detection using Semi-Structured Pruning
Incremental CTL Model Checking Using BDD Subsetting
CrossCheck: A Cell Based VLSI Testability Solution
Laplace transform computer program
Rule-based VLSI Verification System Constrained by Layout Parasitics
Late Breaking Results: Machine Learning Based Reference Ripple Error Suppression in Successive Approximation Register Analog-to-Digital Converters
Extraction of Statistical Timing Profiles Using Test Data
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs
STAC: statistical timing analysis with correlation
Death, taxes and failing chips
Linking the behavioral and structural dominis of representation in a synthesis system
DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications
Via Minimization for Gridless Layouts
On Optimal Board-Level Routing for FPGA-Based Logic Emulation
STEM: An IC Design Environment Based on the Smalltalk Model-View-Controller Construct
A design automation system for printed circuit board assemblies
Uniform support for information handling and problem solving required by the VLSI design process
IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications
Electronics: The New Differential in the Automotive Industry
Noise-aware DVFS transition sequence optimization for battery-powered IoT devices
Aging-constrained performance optimization for multi cores
Deterministic systems design from functional specifications
Optimal Circuits for Parallel Bit Reversal
On EDA-Driven Learning for SAT Solving
Accelerator-Rich Architectures: Opportunities and Progresses
CIM-BLAS: Computing-in-Memory Accelerator for BLAS
Design Methodology for Pipelined Heterogeneous Multiprocessor System
ISDL: An Instruction Set Description Language for Retargetability
A scenario-based run-time task mapping algorithm for MPSoCs
Retiming and recycling for elastic systems with early evaluation
Phoenix architecture
MISER: An Integrated Three Layer Gridless Channel Router and Compactor
ASTA: LSI Design Management System
Generalized cofactoring for logic function evaluation
Change control in automated design
Pythia: Intellectual Property Verification in Zero-Knowledge
A tool to support design automation in batch manufacturing
libcrpm: improving the checkpoint performance of NVM
Battery Management and Application for Energy-Efficient Buildings
CANN: Curable Approximations for High-Performance Deep Neural Network Accelerators
On the Complexity Reduction of Dense Layers from O(N2) to O(NlogN) with Cyclic Sparsely Connected Layers
Top down design and testability of VLSI circuits
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
Quantum Spectral Clustering of Mixed Graphs
Timing Driven Placement for Large Standard Cell Circuits
NetBooster: Empowering Tiny Deep Learning By Standing on the Shoulders of Deep Giants
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication
Algorithms for Timing Requirement Analysis and Generation
MOSSIM: A switch-level simulator for MOS LSI
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Performance optimization of error detection based on speculative reconfiguration
COSA:Co-Operative Systolic Arrays for Multi-head Attention Mechanism in Neural Network using Hybrid Data Reuse and Fusion Methodologies
A statistical methodology for noise sensor placement and full-chip voltage map generation
Special Purpose Architecture for Accelerating Bitmap DRC
CoARX: a coprocessor for ARX-based cryptographic algorithms
Scan Test Planning for Power Reduction
Age-aware Logic and Memory Co-Placement for RRAM-FPGAs
Automation of manufacturing planning, shop loading and work measurement in an engineering job shop environment
Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis
Extensibility in Automotive Security: Current Practice and Challenges: Invited
Coding-based energy minimization for phase change memory
Technology Mapping for Lower Power
Static noise analysis with noise windows
Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution
State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory
PLEST: a program for area estimation of VLSI integrated circuits
Evaluating Hardware Models in DIGITAL's System Simulation Environment
Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm
Escape Routing For Dense Pin Clusters In Integrated Circuits
Chip assemblers: Concepts and capabilities
Digital logic simulation at the gate and functional level
An experiment in architectural instruction
On test generation for transition faults with minimized peak power dissipation
Automatic batch processing in multilayer ceramic metallization
A Novel GPU Overdrive Fault Attack
Reconciling remote attestation and safety-critical operation on simple IoT devices
A Case Study in Embedded System Design: An Engine Control Unit
Static Scheduling of Multiple Asynchronous Domains For Functional Verification
Correlated Bayesian Model Fusion: efficient performance modeling of large-scale tunable analog/RF integrated circuits
A new IP lookup cache for high performance IP routers
Multiple chip planning for chip-interposer codesign
EmMark: Robust Watermarks for IP Protection of Embedded Quantized Large Language Models
Estimation of Speed, Area, and Power of Parameterizable, Soft IP
Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM
Design Methodology Management Using Graph Grammars
Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory