yusuke1997/dblp-id-title huggingface dataset:
The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
A Novel High-Throughput Acceleration Engine for Read Alignment
IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing
Hardware-in-the-Loop Evolution of a 3-bit Multiplier
Safe Task Interruption for FPGAs
Changing Output Quality for Thermal Management
CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures
High-Throughput Fixed-Point Object Detection on FPGAs
Memory Access Scheduling on the Convey HC-1
Time-Domain FPGA Power Delivery Network Characterization Methodology
MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources
Reconsideration of Computing Paradigms and a Novel Reconfigurable Architecture
Efficient Reconfigurable On-Chip Buses for FPGAs
Adaptive Fault Recovery for Networked Reconfigurable Systems
General Architecture for Hardware Implementation of Genetic Algorithm
Sparse Matrix-Vector Multiplication Design on FPGAs
Software defined optical time-domain reflectometer
A declarative approach to incremental custom computing
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
An Empirical Analysis of the Fidelity of VPR Area Models
Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA Modules
Précis: A Design-Time Precision Analysis Tool
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials
K-Mer Counting Using Bloom Filters with an FPGA-Attached HMC
Image Segmentation Using Hardware Forest Classifiers
PhD Project: Reconfigurable Network on Chip Architecture Through Topology Obfuscation For Protecting SoC Against Reverse Engineering
An Architecture for Video Compression Based on the SCAN Algorithm
Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs
Large-Scale and High-Throughput QR Decomposition on an FPGA
Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications
Kernel Formation in Garpcc
Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices
Compact FPGA-based True and Pseudo Random Number Generators
RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA
Configuration Compression for the Xilinx XC6200 FPGA
Terrestrial-Based Radiation Upsets: A Cautionary Tale
Improving Performance of Partial Reconfiguration Using Strategy of Virtual Deletion
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardware
Standardizing the Performance Assessment of Reconfigurable Processor Architectures
FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)
NeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference
Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection
Implementing a Simple Continuous Speech Recognition System on an FPGA
Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work
Cloud FPGA Cartography using PCIe Contention
Accelerating Quadrature Methods for Option Valuation
Multilevel Granularity Parallelism Synthesis on FPGAs
A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer
Scheduling divisible loads on partially reconfigurable hardware
Application Specific Customization and Scalability of Soft Multiprocessors
Benchmarking Reconfigurable Architectures in the Mobile Domain
Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays
IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011
Fast Multivariate Signature Generation in Hardware: The Case of Rainbow
A dynamic reconfiguration run-time system
A High-Throughput Implementation of the MUSIC Algorithm Using AMD Versal AI Engine
In-situ FPGA Debug Driven by On-Board Microcontroller
SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction
Improving the Availability of Secure Space Links through the Partial Reconfiguration of FPGAs
A C++ compiler for FPGA custom execution units synthesis
13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings
Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes
Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver
The PowerPC 405 Memory Sentinel and Injection System
Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures
Building Optimized Packet Filters with COFFi
A Co-Verification Tool for a High Level Language Compiler for FPGAs
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array
Accelerating Run-Time Reconfiguration on FCCMs
High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two
Hardware Factorization Based on Elliptic Curve Method
Instrumenting Bitstreams for Debugging FPGA Circuits
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)
Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive
A Structured System Methodology for FPGA Based System-on-A-Chip Design
Go Ahead: A Partial Reconfiguration Framework
From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis
Systems performance measurement on PCI Pamette
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
Shuhai: Benchmarking High Bandwidth Memory On FPGAS
Migrating Functionality from ROMS to Embedded Multipliers
Active Stereo Vision with High Resolution on an FPGA
Clustering Classification on FPGAs for Neuromorphic Feature Extraction
A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators
An FPGA-Based Data Flow Engine for Gaussian Copula Model
FPGA Implementation of Post-Quantum DME Cryptosystem
Hybrid XML Parser Based on Software and Hardware Co-design
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction
Particle Mesh Ewald for Molecular Dynamics in OpenCL on an FPGA Cluster
Heterogeneous Implementation of ECG Encryption and Identification on the Zynq SoC
BCIM: A Bit-Serial Approach for Block-Cipher-in-Memory
A Reliable LZ Data Compressor on Reconfigurable Coprocessors
High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex
Efficient Calculation of Pairwise Nonbonded Forces
An ACS Robotic Control Algorithm with Fault Tolerant Capabilities
PCQ: Parallel Compact Quantum Circuit Simulation
Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation
An Adaptive Cryptographic Engine for IPSec Architectures
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device
Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis
Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines
A Fully Pipelined and Dynamically Composable Architecture of CGRA
An Arithmetic Library and Its Application to the N-body Problem
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy
Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform
Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip
More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control
Fast Regular Expression Matching Using FPGAs
FPGA Accelerator for Homomorphic Encrypted Sparse Convolutional Neural Network Inference
Trusted Configuration in Cloud FPGAs
DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators
Improved Techniques for Sensing Intra-Device Side Channel Leakage
The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators
iSEW: in-Sensor Embedded Watermarking for Secure Imaging
An Open TCP/IP Core for Reconfigurable Logic
Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs
27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019, San Diego, CA, USA, April 28 - May 1, 2019
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method
Exploring architectures for volume visualization on the Teramac custom computer
HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance
Hardware-Assisted Fast Routing
An Approach to a Fully Automated Partial Reconfiguration Design Flow
22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014
Power Management Strategies for Serial RapidIO Endpoints in FPGAs
Compilation tools for run-time reconfigurable designs
FPGA-Based Template Matching Using Distance Transforms
Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
Hardware Acceleration of Approximate Tandem Repeat Detection
Efficient Implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA
A BIST Approach for Testing FPGAs Using JBITS
Scheduling Considerations for Voter Checking in TMR-MER Systems
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
Post Synthesis Level Power Modeling of FPGAs
A C to HDL Compiler for Pipeline Processing on FPGAs
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
Laser defect correction applications to FPGA based custom computers
An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform
Using Runahead Execution to Hide Memory Latency in High Level Synthesis
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Scalable Pattern Matching for High Speed Networks
Designing Modular Hardware Accelerators in C with ROCCC 2.0
Cycle-Accurate Replay and Debugging of Running FPGA Systems
Accelerating Boolean Satisfiability with Configurable Hardware
A Near-Memory Radix Sort Accelerator with Parallel 1-bit Sorter
Automating the Layout of Reconfigurable Subsystems Via Template Reduction
Scalable Key/Value Search in Datacenters
Ph.D. Project: ManAge: A Tool for Timing Characterization of FPGAs
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices
Generic Software Framework for Adaptive Applications on FPGAs
HighWave: Large-Scale High-Bandwidth Wave Simulations on FPGAs
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking
A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System
Coarse-Grain Pipelining on Multiple FPGA Architectures
Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
Energy Efficient Loop Unrolling for Low-Cost FPGAs
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip
A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages
A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation
Circlets: Circuitry over the Internet
Sonar: Writing Testbenches through Python
Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA
BigSky-An On-Line Arithmetic Design Tool for FPGAs
An Efficient Piecewise Linear Approximation of Non-linear Operations for Transformer Inference
Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration
FPGA-Based Vector Processing for Solving Sparse Sets of Equations
Remote Execution in Distributed Memory MPSoC
Evaluation of Reconfigurable Cache Module Architecture
Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing
Abstract: Shared L2 Cache Management in Multicore Real-Time System
IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA
CoMeFa: Compute-in-Memory Blocks for FPGAs
A Type Architecture for Hybrid Micro-Parallel Computers
Computing and Compressing Electron Repulsion Integrals on FPGAs
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001
Customizing Neural Networks for Efficient FPGA Implementation
High-Throughput DNN Inference with LogicNets
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro
Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment
K-means Clustering for Multispectral Images Using Floating-Point Divide
Reconfigurable Designs for Ray Tracing
b8c: SpMV accelerator implementation leveraging high memory bandwidth
Acceleration of a DWT-Based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform
Compiling Policy Descriptions into Reconfigurable Firewall Processors
Modular SRAM-Based Binary Content-Addressable Memories
Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems
IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS
ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling
RVC - A Reconfigurable Coprocessor for Vector Processing Applications
ATHEENA: A Toolflow for Hardware Early-Exit Network Automation
Enable ++: A Second Generation FPGA Processor
Discrete-Time Cellular Neural Networks in FPGA
Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA
Explore Efficient LUT-based Architecture for Quantized Convolutional Neural Networks on FPGA
An FPGA Implementation of GENET for Solving Graph Coloring Problems
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
Initiation Interval Aware Resource Sharing for FPGA DSP Blocks
The NAPA Adaptive Processing Architecture
Blocking LU Decomposition for FPGAs
An FPGA Implementation of Triangle Mesh Decompression
Using the Power Side Channel of FPGAs for Communication
An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing
Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance
Multiple Precision for Resource Minimization
Jumble: A Hardware-in-the-Loop Simulation System for JHDL
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
AccDNN: An IP-Based DNN Generator for FPGAs
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
Design of a Distributed Compressor for Astronomy SSD
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
VLSI architectures for field programmable gate arrays: a case study
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine
EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGA
Parallel Hardware Merge Sorter
Scaling Soft Processor Systems
FASE: FPGA Acceleration of Secure Function Evaluation
ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits -1 Data Acquisition System for 6G Prototyping
FPGA-accelerated Automatic Alignment for Three-dimensional Tomography
A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine
6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA
An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic
Accelerating Adobe Photoshop with the Reconfigurable Logic
Hardware Implementation of Generalized Profile Search on the GENSTORM Machine
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions
Exploiting Irregular Memory Parallelism in Quasi-Stencils through Nonlinear Transformation
OS4C: An Open-Source SR-IOV System for SmartNIC-based Cloud Platforms
Accuracy-Performance Tradeoffs on an FPGA through Overclocking
An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars
A Virtual Machine for Merit-Based Runtime Reconfiguration
Efficient Hardware Generation of Random Variates with Arbitrary Distributions
Supporting FPGA microprocessors through retargetable software tools
Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations
Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware
High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves
Scalable Hardware Architecture for Real-Time Dynamic Programming Applications
Switch Box Architectures for Three-Dimensional FPGAs
Enabling High Throughput and Virtualization for Traffic Classification on FPGA
Sectors: Divide & Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA
Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Low-Latency Modular Exponentiation for FPGAs
Efficient Large Integer Squarers on FPGA
TwinDNN: A Tale of Two Deep Neural Networks
Rethinking Secure FPGAs: Towards a Cryptography-Friendly Configurable Cell Architecture and Its Automated Design Flow
Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors
Runtime Detection of Probing/Tampering on Interconnecting Buses
Speech recognition HMM training on reconfigurable parallel processor
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA
Fast Voltage Transients on FPGAs: Impact and Mitigation Strategies
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design
An Efficient FPGA Implementation of k-Nearest Neighbors via Online Arithmetic
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW
Common processor element packaging for CHAMP
Exploring Optimal Cost-Performance Designs for Raw Microprocessors
KPynq: A Work-Efficient Triangle-Inequality Based K-Means on FPGA
Word-Length Optimization of Folded Polynomial Evaluation
A Massively Parallel RC4 Key Search Engine
EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device
High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors
On Distributed Reconfigurable Systems: Open Problems and Some Initial Solutions
Bandwidth Efficient Homomorphic Encrypted Discrete Fourier Transform Acceleration on FPGA
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments
TCP-Stream Reassembly and State Tracking in Hardware
Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators
Column-Based Precompiled Configuration Techniques for FPGA
Online Bandwidth Reduction Using Dynamic Partial Reconfiguration
Mixed-Resource Parallel Processing on FPGAs
Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs
Latte: Locality Aware Transformation for High-Level Synthesis
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping
A Run-Time Reconfigurable Engine for Image Interpolation
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs
A Configurable Hardware/Software Approach to SAT Solving
FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation
Mapping a real-time video algorithm to a context-switched FPGA
Global Atmospheric Simulation on a Reconfigurable Platform
FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection
Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore Processors
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding
Formal Verification of Reconfigurable Cores
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
Design of a Reconfigurable Hybrid Database System
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing
Proposing a Fast and Scalable Systolic Array for Matrix Multiplication
On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs
GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA
Reconfigurable High Resolution Network Camera
Reconfigurable Pipelines in VLIW Execution Units
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor
Assessing document relevance with run-time reconfigurable machines
Accelerating Cosmological Data Analysis with FPGAs
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs
Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption
Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis
A Low-Latency, Low-Area Hardware Oblivious RAM Controller
Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout
A Custom Precision Based Architecture for Accelerating Parallel Tempering MCMC on FPGAs without Introducing Sampling Error
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems
Software/Hardware Co-Scheduling for Reconfigurable Computing Systems
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration
HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks
Latency-Optimized Networks for Clustering FPGAs
VHDL Placement Directives for Parametric IP Blocks
Synthesis of Platform Architectures from OpenCL Programs
A Packet Generator on the NetFPGA Platform
Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data
Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph
High Speed Video Processing Using Fine-Grained Processing on FPGA Platform
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing
VPN Acceleration Using Reconfigurable System-On-Chip Technology
Module Generators Driving the Compilation for Adaptive Computing Systems
TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs
A Hardware Gaussian Noise Generator for Channel Code Evaluation