yusuke1997/dblp-id-title huggingface dataset:
A package of computer subprograms for control system analysis
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
RAIN: a tool for reliability assessment of interconnect networks - physics to software
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model
ACIM-QMM: Efficient Analog Computing-in-Memory Accelerator for QC-MDPC McEliece Cryptosystem
VirTEE: a full backward-compatible TEE with native live migration and secure I/O
A 1.5GHz third generation itanium® 2 processor
System verification of concurrent RTL modules by compositional path predicate abstraction
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors
Quadratic Placement Revisited
Architecting energy-efficient STT-RAM based register file on GPGPUs via delta compression
Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis
SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model Training
Pin assignment in automated printed circuit board design
Code Coverage of Assertions Using RTL Source Code Analysis
A heathkit approach for computer-aided comparison of building alternatives
Constraint synthesis for environment modeling in functional verification
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells
Computer aided logic design
FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development
Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload Balance
Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost Benchmarks
Making Manufacturing Work For You
ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum Devices
How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising
NTPT: on the end-to-end traffic prediction in the on-chip networks
Towards Training Robustness Against Dynamic Errors in Quantum Machine Learning
Hardware-Software Co-design for Distributed Quantum Computing
Constraint Management for Collaborative Electronic Design
SecPaging: Secure Enclave Paging with Hardware-Enforced Protection against Controlled-Channel Attacks
Top-k Aggressors Sets in Delay Noise Analysis
Real time diagnosis of logic assemblies
An Object-Oriented VHDL Design Environment
Tutorial: Design of a Logic Synthesis System
A simulator to replace wire rules for high speed computer design
A logic and signal flow diagram subsystem
RF front end application and technology trends
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems
Thermal monitoring of real processors: techniques for sensor allocation and full characterization
Fast Incremental Circuit Analysis Using Extracted Hierarchy
FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUT
Hynify: A High-throughput and Unified Accelerator for Multi-Mode Nonparametric Statistics
Verification of gate-level arithmetic circuits by function extraction
A New Efficient Approach to Multilayer Channel Routing Problem
Analysis of placement procedures for VLSI standard cell layout
Fault Characterizations and Design-for-Testability Technique for Detecting I DDQ Faults in CMOS/BiCMOS Circuits
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference
A static pattern-independent technique for power grid voltage integrity verification
Will Cell Generation Displace Standard Cells?
DRG-cache: a data retention gated-ground cache for low power
Looking for Mr. "Turnkey"
A Transformation-Based Approach for Storage Optimization
PHIGURE: A Parallel Hierarchical Global Router
In-process Memory Isolation Using Hardware Watchpoint
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms
Computer generation of streaming sorting networks
Data compression for improving SPM behavior
The HELIX project: overview and directions
Joint DAC/IWBDA special session design and synthesis of biological circuits
A switchbox router with obstacle avoidance
Reduction Operator for Wide-SIMDs Reconsidered
The Implementation of a State Machine Compiler
A new algorithm for third generation circuit simulators: the one-step relaxation method
Design without Borders - A Tribute to the Legacy of A. Richard Newton
Efficient Analog Test Methodology Based on Adaptive Algorithms
Performance Analysis Based on Timing Simulation
VEEP A VEctor Editor and Preparer
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
RADAR: a 3D-reRAM based DNA alignment accelerator architecture
Fair Will Go On: A Collaboration-Aware Fairness Scheme for NVMe SSD in Cloud Storage System
Compiler-directed scratch pad memory hierarchy design and management
Extending the relational database data model for design applications
A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation
Modular system-level architecture for concurrent cell balancing
A Practical Methodology for Early Buffer and Wire Resource Allocation
FPGA-based accelerator for the verification of leading-edge wireless systems
An affordable approach to an architectural computer system
High-Level Graphical User Interface Management in the FACE Synthesis Environment
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification
Evaluating the Security of Logic Locking on Deep Neural Networks
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips
Spare-cell-aware multilevel analytical placement
Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order Prediction
Automated failure population creation for validating integrated circuit diagnosis methods
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment
SAS - A Framework for Symmetry-based Approximate Synthesis
Component library for an integratel DA system
Simulation of large communications networks using SPIN
HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing
Minimal Delay Interconnect Design Using Alphabetic Trees
An automated data path synthesizer for a canonic structure, implementable in VLSI
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits
Keeping hot chips cool
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
Proceedings of the SHARE design automation project, DAC '65, Atlantic City, NJ, USA, June 23-25, 1965
DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on Edge
Functional testing of LSI gate arrays
Enabling adaptability through elastic clocks
Conforming the runtime inputs for hard real-time embedded systems
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications
Smart diagnostics for configurable processor verification
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment
Glimpse: mathematical embedding of hardware specification for neural compilation
Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems
"Implementation of a space planning system in a small scale architecture office"
Characterizing chip-multiprocessor variability-tolerance
Multiprocessor performance estimation using hybrid simulation
QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference
Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper
Optimal voltage allocation techniques for dynamically variable voltage processors
RDE-based transistor-level gate simulation for statistical static timing analysis
A heterogeneous multiple network-on-chip design: an application-aware approach
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology
PATEGE: an automatic DC parametric test generation system for series gated ECL circuits
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology
RC Interconnect Optimization Under the Elmore Delay Model
Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud
Implicit pseudo boolean enumeration algorithms for input vector control
Ensuring functional safety compliance for ISO 26262
A Resource Binding Approach to Logic Obfuscation
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor
A high-density multilayer PCB router based on necessary and sufficient conditions for single row routing
AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
The CMU design automation system: An example of automated data path design
TAIM: ternary activation in-memory computing hardware with 6T SRAM array
Graph-Morphing: Exploiting Hidden Parallelism of Non-Stencil Computation in High-Level Synthesis
Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool
DPCP-p: A Distributed Locking Protocol for Parallel Real-Time Tasks
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor
Density-aware Detailed Placement with Instant Legalization
Layout Synthesis of MOS Digital Cells
ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning
Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007
A time and space efficient net extractor
BLAST: efficient computation of nonlinear delay sensitivities in electronic and biological networks using barycentric Lagrange enabled transient adjoint analysis
Optimizing data placement for reducing shift operations on domain wall memories
Lattice-based computation of Boolean functions
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks
G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural Networks
Domain knowledge and the design process
netShip: a networked virtual platform for large-scale heterogeneous distributed embedded systems
An integrated system for interactive editing of schematics, logic simulation and PCB layout design
Scalable Community Detection Using Quantum Hamiltonian Descent and QUBO Formulation
Scalable-effort classifiers for energy-efficient machine learning
An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering
Architecture Synthesis of High-Performance Application-Specific Processors
Virtualizing real-time embedded systems with Java
A Defect-Tolerant and Fully Testable PLA
A high level synthesis tool for MOS chip design
Modelling multicore contention on the AURIX TM TC27x
A programmable printed-wiring router
Software controlled cell bit-density to improve NAND flash lifetime
Management Issues in Eda
Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001
Instruction-Level Data Isolation for the Kernel on ARM
LLMs: A Driving Force in Next Generation Digital Design Automation
A new synthesis for the MIMOLA software system
A proof engine approach to solving combinational design automation problems
AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM
New spare cell design for IR drop minimization in Engineering Change Order
TFix: Exploiting the Natural Redundancy of Ternary Neural Networks for Fault Tolerant In-Memory Vector Matrix Multiplication
SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAs
FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems
Experience with ADAM Synthesis System
Condense: A Framework for Device and Frequency Adaptive Neural Network Models on the Edge
BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language Models
Importance of standards (tutorial session)
INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended Abstract
AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits
Bundling (cable signal assignment)
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems
A switch level fault simulation environment
Advanced Verification Techniques Based on Learning
G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning
Semantics of a Hardware Design Language for Japanese Standardization
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization
Relative Scheduling Under Timing Constraints
An Energy-Efficient Network-on-Chip Design using Reinforcement Learning
Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM
Trusted Hardware: Can It Be Trustworthy?
Design transaction management
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
Locating Functional Errors in Logic Circuits
Guiding sensitization searches using problem reduction graphs
A CAD System for the Design of Field Programmable Gate Arrays
The management of engineering changes using the PRIMUS system
Routability-Driven Fanout Optimization
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems
Abstraction refinement by controllability and cooperativeness analysis
Use of C/C++ models for architecture exploration and verification of DSPs
Validating Discrete Event Simulations Using Event Pattern Mappings
Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks
Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics
Reliability-aware Register Binding for Control-Flow Intensive Designs
Placement initialization via a projected eigenvector algorithm: late breaking results
DARIS: An Oversubscribed Spatio-Temporal Scheduler for Real-Time DNN Inference on GPUs
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design
On-chip interconnection network for accelerator-rich architectures
Java Driven Codesign and Prototyping of Networked Embedded Systems
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology
Hybrid Obfuscation of Chiplet-Based Systems
Challenges in using system-level models for RTL verification
Constraint Driven Code Selection for Fixed-Point DSPs
A hybrid scheduling technique for hierarchical logic simulators or "Close Encounters of the Simulated Kind"
Latency-Driven Design of Multi-Purpose Systems-On-Chip
CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing
Register Allocation and Binding for Low Power
A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI's
A new statistical model for gate array routing
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation
An arbitrary twoqubit computation In 23 elementary gates or less
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA
A language for describing rectilinear Steiner tree configurations
Simulated annealing and combinatorial optimization
Multithreaded simulation for synchronous dataflow graphs
HAL: A block level HArdware Logic simulator
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning
Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling
A Data Path Layout Assembler for High Performance DSP Circuits
Clock Skew Minimization During FPGA Placement
Automatic routing algorithm for VLSI
Life is CMOS: why chase the life after?
A Rule-Based Circuit Representation for Automated CMOS Design and Verification
On the layering problem of multilayer PWB wiring
SystemClick: a domain-specific framework for early exploration using functional performance models
Minimum test patterns for residue networks
The use of graphics processors for circuit design simulation at GTE AE Labs
STASH: security architecture for smart hybrid memories
Nautilus: fast automated IP design space search using guided genetic algorithms
RADAR: RET-aware detailed routing using fast lithography simulations
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
Using error latch trace to obtain diagnostic information
Circuit optimization using statistical static timing analysis
ePlace: Electrostatics Based Placement Using Nesterov's Method
Design verification system for large-scale LSI designs
Can recursive bisection alone produce routable placements?
Optimal Graph Constraint Reduction for Symbolic Layout Compaction
Facet: A procedure for the automated synthesis of digital systems
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction
ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited
DeMOR: decentralized model order reduction of linear networks with massive ports
Multicore Environment State Representation for Agent-Directed Test Generation
Hierarchical design verification for large digital systems
Design Automation Tools for FPGA Design (Panel)
A CAD Tool for Optical MEMS
On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking
Evolution of a spatial allocation system: Allocate
LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors
Metasynthesis for Designing Automotive SoCs
Sequential Circuit Delay optimization Using Global Path Delays
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning
ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAM
How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances
A Circuit Comparison System with Rule-Based Functional Isomorphism Checking
OpenMem: Hardware/Software Cooperative Management for Mobile Memory System
DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip
Desisn automation and VLSI in the 80's (Position Statement)
RESP: a robust physical unclonable function retrofitted into embedded SRAM array
Fault injection acceleration by simultaneous injection of non-interacting faults
Towards Secure Data Management using Multi-Cryptographic Solutions (Invited)
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design
Partition Based Differential Testing for Finding Embedded Code Generation Bugs in Simulink
Timing influenced layout design
Hardware Trojan horse benchmark via optimal creation and placement of malicious circuitry
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
On the Bounded-Skew Clock and Steiner Routing Problems
System-level data format exploration for dynamically allocated data structures
A Highly Flexible Ring Oscillator PUF
Measuring designer performance to verify design automation systems
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis
A Fault Analysis Method for Synchronous Sequential Circuits
Xquasher: a tool for efficient computation of multiple linear expressions
HPEX: A Hierarchical Parasitic Circuit Extractor
Is Technology-Independent Design Really Practical? (Panel Abstract)
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling
Panel: Your Core - My Problem? Integration and Verification of IP
Timing-aware control software design for automotive systems
EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis
Embedded software-based self-testing for SoC design
A wire routing scheme for double-layer cell arrays
Address Code Generation for Digital Signal Processors
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
Synthesizing Barrier Certificates of Neural Network Controlled Continuous Systems via Approximations
CGALA-a multi technology Gate Array Layout system
Dynamic thermal management for multimedia applications using machine learning
A Path-Oriented Approach for Reducing Hazards in Asynchronous Designs
Exploring serial vertical interconnects for 3D ICs
Measurement-based cache representativeness on multipath programs
Thermal-Aware Design and Management for Search-based In-Memory Acceleration
An Intelligent Video Processing Architecture for Edge-cloud Video Streaming
Functional Synthesis Using Area and Delay Optimization
New trends in dark silicon
Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration
Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures
Geometric constraint satisfaction for a computer/display system
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams
DARPT: defense against remote physical attack based on TDC in multi-tenant scenario
The generation of Technical Data Drawing Packages by the integration of Design Automation Graphics
Finite State Machine Synthesis with Fault Tolerant Test Function
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs
High-Level Synthesis: Current Status and Future Directions
HCG: optimizing embedded code generation of simulink with SIMD instruction synthesis
Novel power grid reduction method based on L1 regularization
Energy-aware design techniques for differential power analysis protection
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
Design Strategy of On-Chip Inductors for Highly Integrated RF Systems
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
Synchronous sequential computation with molecular reactions
Data-Path Synthesis Using Path Analysis
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
An experimental system for power/timing optimization of LSI chips
Leakage aware dynamic voltage scaling for real-time embedded systems
DC-DC converter-aware power management for battery-operated embedded systems
A Clustering-Based Optimization Algorithm in Zero-Skew Routings
An Analytical Approach to Floorplan Design and Optimization
An efficient phase detector connection structure for the skew synchronization system
Magic's circuit extractor
Thermal-driven analog placement considering device matching
Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking
On-chip logic minimization
Analysis of timing failures due to random AC defects in VLSI modules
Late Breaking Results: On-the-Fly Hadamard Hypervector Processing for Efficient Hyperdimensional Computing
Rectification of Multiple Logic Design Errors in Multiple Output Circuits
Oracle - a simulator for Bipolar and MOS IC design
Generating parametric models from tabulated data
A novel optimal single constant multiplication algorithm
ABLE: AMD Backplane for Layout Engines
Reliability challenges for electric vehicles: from devices to architecture and systems software
Designing Stealthy Trojans with Sequential Logic: A Stream Cipher Case Study
Raven: a novel kernel debugging tool on RISC-V
Tools or users: which is the bigger bottleneck?
DISPLAYTRAN a graphic oriented conversational system
Quantifying Rowhammer Vulnerability for DRAM Security