yusuke1997/dblp-id-title huggingface dataset:
Aliasing Probability in Multiple Input Linear Signature Automata for Q-ary Symmetric Errors
IBM second-generation RISC machine organization
Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems
A Partial Scan Cost Estimation Method at the System Level
SMRTS: A Performance and Cost-Effectiveness Optimized SSD-SMR Tiered File System with Data Deduplication
CostFM: A High Cost-Performance Fingerprint Management Mechanism for Shared SSDs
Re-Thinking Mixed-Criticality Architecture for Automotive Industry
Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems
A CRegs Implementation Study Based on the MIPS-X RISC Processor
Conceptual Modeling and Simulation
SLIDER: Smart Late Injection DEflection Router for mesh NoCs
Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache
DDPSL: An easy way of defining properties
An improved micro-architecture for function approximation using piecewise quadratic interpolation
Power gating with block migration in chip-multiprocessor last-level caches
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits
Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2
APT: Efficient Side-Channel Analysis Framework against Inner Product Masking Scheme
HASDH: A Hotspot-Aware and Scalable Dynamic Hashing for Hybrid DRAM-NVM Memory
Aggressive Test Power Reduction Through Test Stimuli Transformation
Future Needs for Automotive Electronics
Near-Sensor Inference Architecture with Region Aware Processing
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
Error behaviors testing with temperature and magnetism dependency for MRAM
ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural Networks
Distributed EDA Tool Integration: The PPP Paradigm
Tutorial on Embedded System Design
An Effective Analog Approach to Steiner Routing
Suitable cache organizations for a novel biomedical implant processor
A module-sliced approach for high yield VLSI/WSI processors
20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings
Hardware Verification Using Symbolic State Transition Graphs
PCCL: Energy-Efficient LLM Training with Power-Aware Collective Communication
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
Opportunities and pitfalls in HDL-based system design
Accurate estimation of vector dependent leakage power in the presence of process variations
Path aware event scheduler in HoldAdvisor for fixing min timing violations
Peephole Optimization of Asynchronous Macromodule Networks
Pursuing the Performance Potential of Dynamic Cache Line Sizes
Voltage drop reduction for on-chip power delivery considering leakage current variations
Stealth assessment of hardware Trojans in a microcontroller
Robust optimization of a Chip Multiprocessor's performance under power and thermal constraints
Reinforcement learning based dynamic power management with a hybrid power supply
Chip level thermal profile estimation using on-chip temperature sensors
LCKV: Learner-Cleaner Optimized Adaptive Key-Value Separated LSM-Tree Store
AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction
Llm4mcu-Onto: Leveraging Llms for Automated Ontology Generation From Microcontroller Reference Manual
Fast and compact binary-to-BCD conversion circuits for decimal multiplication
1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings
MMPacking: A Load and Storage Balancing Algorithm for Distributed Multimedia Servers
An Open-Source Scalable Thermal and Power Controller for HPC Processors
Challenges and prospects of SDR for mobile phones
Adaptive Prefetching for Accelerating Read and Write in NVM-Based File Systems
Automatic signal net-matching for VLSI layout design
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing
Floating-Point Fused Multiply-Add with Reduced Latency
Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications
Reactive clocks with variability-tracking jitter
MOTPE/D: Hardware and Algorithm Co-design for Reconfigurable Neuromorphic Processor
ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
VLSI programming and silicon compilation; a novel approach from Philips research
Customizable Fault Tolerant Caches for Embedded Processors
An optimized diagnostic procedure for pre-bond TSV defects
A Layout Compaction Algorithm with Multiple Grid Constraints
Exploring DRAM cache architectures for CMP server platforms
Recent additions to the ARMv7-A architecture
Analysis and minimization of short-circuit current in mesh clock network
Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme
A Study of Channeled DRAM Memory Architectures
Thena: Torus Fully Homomorphic Encryption on Energy-Efficient Heterogeneous Architecture
Efficient Fixpoint Computation for Invariant Checking
FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation
Algorithms for Interface Timing Verification
Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous components
STAG: Enabling Low Latency and Low Staleness of GNN-based Services with Dynamic Graphs
Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration
A VLSI Chip for Template Matching
Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits
Experiments with an efficient heuristic algorithm for local microcode generation
Memory based computation using embedded cache for processor yield and reliability improvement
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines
A framework for evaluating test pattern generation strategies
On the Road to a Mobile Information Society
YEPHCAD and FLORA: Logic Synthesis for Control and Datapath
Designing the M·CORE TM M3 CPU Architecture
CheriRTOS: A Capability Model for Embedded Devices
A Semi Black-Box Adversarial Bit- Flip Attack with Limited DNN Model Information
Static Transition Probability Analysis Under Uncertainty
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
The observability don't-care set and its approximations
Model checking of a real ATM switch
On the Construction of Universal Series-Parallel Functions for Logic Module Design
Latch Redundancy Removal Without Global Reset
A High-Frequency Decimal Multiplier
A methodology for power characterization of associative memories
OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read Performance
A Reliability Study on CNNs for Critical Embedded Systems
Pollution control caching
The Monsoon Interconnection Network
Placement-Based Partitioning for Lookup-Table-Based FPGAs
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability
41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus
A Black-Box Sensitization Attack on SAT-Hard Instances in Logic Obfuscation
A Quantum Method to Match Vector Boolean Functions using Simon's Solver
Hardware thread reordering to boost OpenCL throughput on FPGAs
CCAS: Contention and congestion aware switch allocation for network-on-chips
A Timing-Driven Macro-Cell Placement Algorithm
Practical Advances in Asynchronous Design
DRAM-Page Based Prediction and Prefetching
ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator
Thermal Aware Lifetime Reliability Optimization for Automotive Distributed Computing Applications
Efficient State Space Pruning in Symbolic Backward Traversal
Early: An Importance-Aware Early Firing and Exit for SNN Acceleration
Increasing GPU throughput using kernel interleaved thread block scheduling
Improving Performance of TLC RRAM with Compression-Ratio-Aware Data Encoding
A tag-based cache replacement
Multiterminal-net routing by grid stretching
SOI Implementation of a 64-Bit Adder
Log-ROC: Log Structured RAID on Open-Channel SSD
Efficient Synthesis of Networks On Chip
A Learning-Based Framework for Automatic Parameterized Verification
Special Session: XTA: Open Source eXtensible, Scalable and Adaptable Tensor Architecture for AI Acceleration
Simulated annealing on a multiprocessor
Welcome to ICCD 2010!
Hierarchical Simulation of a Multiprocessor Architecture
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
A lightweight and open-source framework for the lifetime estimation of multicore systems
Hermes: Memory-Efficient Pipeline Inference for Large Models on Edge Devices
InvArch: A hardware eficient architecture for Matrix Inversion
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective
Efficient Delay-Insensitive RSFQ Circuits
A Methodology for Fast and Efficient ML-Based Power Modeling
DualSpar: A Dual-Granularity Memory Framework with Adaptive Sparsity for Efficient LLM Inference
Yoda: Judge Me by My Size, Do You?
AGQFL: Communication-efficient Federated Learning via Automatic Gradient Quantization in Edge Heterogeneous Systems
Tuning Stencil codes in OpenCL for FPGAs
A Dependence Driven Efficient Dispatch Scheme
NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores
HAP: Hybrid-memory-Aware Partition in shared Last-Level Cache
From theory to practice of private circuit: A cautionary note
Fuzzy Logic: Why the U.S. Falls Behind?
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach
Long-term Performance Bottleneck Analysis and Prediction
Requirements for Automotive System Engineering Tools
Synthesis of parallel prefix adders considering switching activities
Computer-aided simulation of optical interconnects for high-speed digital systems
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Multiplier-less and table-less linear approximation for square and square-root
On-the-fly circuit to measure the average working set size
A Distributed In-Situ CNN Inference System for IoT Applications
Exploiting microarchitectural redundancy for defect tolerance
A novel VLSI architecture for the real-time implementation of 2-D signal processing systems
Placement algorithms for CMOS cell synthesis
Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines
Ultra-low energy security circuits for IoT applications
A Brief History of the Future of Semiconductor Electronic Design Automation
Parallelizing Latent Semantic Indexing using an FPGA-based architecture
IPC Driven Dynamic Associative Cache Architecture for Low Energy
Towards a timing attack aware high-level synthesis of integrated circuits
Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems
Dynamic File Cache Optimization for Hybrid SSDs with High-Density and Low-Cost Flash Memory
McMAP: a fast technology mapping procedure for multi-level logic synthesis
Static thread mapping for NoCs via binary instrumentation traces
Special Session: Physics- Informed Neural Networks for Securing Water Distribution Systems
A modular scan-based testability system
Breaking the Oblivious-RAM Bandwidth Wall
Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine
Trojan Resilience in Implantable and Wearable Medical Devices with Virtual Biosensing
SecNPU: Securing LLM Inference on NPU
A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme
Timing variation-aware high-level synthesis considering accurate yield computation
MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing
Dynamic Thread Resizing for Speculative Multithreaded Processors
Fault Localization for Hardware Design Code with Time-Aware Program Spectrum
Fast error aware model for arithmetic and logic circuits
An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors
High-Level Synthesis of Self-Recovering MicroArchitectures
Increasing cache capacity via critical-words-only cache
Energy aware task mapping algorithm for heterogeneous MPSoC based architectures
Influence of Error Correlations on the Signature Analysis Aliasing
Low Energy, Highly-Associative Cache Design for Embedded Processors
Assessment of cloud-based health monitoring using Homomorphic Encryption
Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits
HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Design Methodology for a MIPS Compatible Embedded Control Processor
Multi-Column Implementations for Cache Associativity
FaRAccel: FPGA-Accelerated Defense Architecture for Efficient Bit-Flip Attack Resilience in Transformer Models
A channelless layout for multilevel synthesis with compiled cells
SMAC: A Scene Matching Chip
UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000
Design Exploration for Multiple Level Cell Based Non-Volatile FPGAs
AutoSparse: A Source-to-Source Format and Schedule Auto- Tuning Framework for Sparse Tensor Program
Statistics on concurrent fault and design error simulation
Synchronization of Wave-Pipelined Circuits
LLM - TG: Towards Automated Test Case Generation for Processors Using Large Language Models
DPPC: Dynamic power partitioning and capping in chip multiprocessors
A New Processor Architecture for Digital Signal Transport Systems
Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing
Speculative tag access for reduced energy dissipation in set-associative L1 data caches
Cyber-physical integration in programmable microfluidic biochips
An edge based netlist extractor for IC layouts
DLL-Assisted Clock Synchronization Method for Multi-Die ICs
Deployment of Better Than Worst-Case Design: Solutions and Needs
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches
Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory
Diagnosis of Hold Time Defects
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
Power Efficient Data Cache Designs
Efficient calibration of thermal models based on application behavior
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case
The capability mechanism of a VLSI processor
WOLT: Transparent Deployment of ML Workloads on Lightweight Many-Accelerator Architectures
Guiding RTL Test Generation Using Relevant Potential Invariants
Selective Compression Scheme for Read Performance Improvement on Flash Devices
Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993
Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses
Parametric throughput analysis of scenario-aware dataflow graphs
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy
CNN Inference Accelerators with Adjustable Feature Map Compression Ratios
Snapshot: Fast, Userspace Crash Consistency for CXL and PM Using msync
On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs
High speed, low power CMOS transmitter-receiver system
A hardware-based multi-objective thread mapper for tiled manycore architectures
Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999
Compression of Embedded System Programs
Testing of embedded A/D converters in mixed-signal circuit
Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs
Analyzing the optimal ratio of SRAM banks in hybrid caches
Dynamic register file partitioning in superscalar microprocessors for energy efficiency
Impact and optimization of lithography-aware regular layout in digital circuit design
Low power, high throughput network-on-chip fabric for 3D multicore processors
A Highly Non-Volatile Memory Scalable and Efficient File System
Quantifying the difference in resource demand among classic and modern NoC workloads
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.
A hierarchical constraint graph generation and compaction system for symbolic layout
Power variations of multi-port routers in an application-specific NoC design : A case study
A matched-delay CMOS TDM multiplexer cell
Realization of Multiple-Output Functions by Reconfigurable Cascades
Architectural Considerations for SF-core Based Microprocessor
OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization
Parameterized free space redistribution for engineering change in placement of integrated circuits
Potential Slack Budgeting with Clock Skew Optimization
Negative-skewed shadow registers for at-speed delay variation characterization
Reducing data access penalty using intelligent opcode-driven cache prefetching
Electromagnetic Modeling and Simulation of Electronic Packages
Chopin: Composing Cost-Effective Custom Chips with Algorithmic Chiplets
Sequential Circuit Design Using Synthesis and Optimization
The J-Machine Network
Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration
Timing-test scheduling for constraint-graph based post-silicon skew tuning
Enabling Encrypted Delta Compression for Outsourced Storage Systems via Preserving Similarity
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection
Special Session: Potentially Leaky Controller: Examining Cache Side-Channel Attacks in Programmable Logic Controllers
WaveSync: A low-latency source synchronous bypass network-on-chip architecture
Temporal Decomposition for Logic Optimization
Design and Evaluation of a Selective Compressed Memory System
Mind: a module binder for high level synthesis
A fine-grain, current mode scheme for VLSI proximity search engine
Real-time, unobtrusive, and efficient program execution tracing with stream caches and last stream predictors
The Future of Embedded System Design
Special Session: When Dataflows Converge: Reconfigurable and Approximate Computing for Emerging Neural Networks
WSSR: Weight Set Segmentation and Recovery for Fault Resilient Transformers
Special Session: An Adiabatic Logic Based Silicon Physical Unclonable Function
Turn Waste Into Wealth: Alleviating Read/Write Interference in ZNS SSDs
SYLON-REDUCE: an MOS network optimization algorithms using permissible functions
Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation
A simple latency tolerant processor
Effective Signal Restoration in Post-Silicon Validation
A Direct Mapping FPGA Architecture for Industrial Process Control Applications
Stop criteria in simulated annealing
SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution
Energy-Efficient MAC Units for Fused Posit Arithmetic
Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques
An Efficient and Flexible Metadata Management Layer for Local File Systems
PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine
Analytical Model for Sensor Placement on Microprocessors
An efficient parallel algorithm for channel routing
Low power multi-level-cell resistive memory design with incomplete data mapping
Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter
IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-Memory
Issues on the architecture and the design of distributed shared memory systems
Logic Obfuscation against IC Reverse Engineering Attacks Using PLGs
Towards a tool for implementing delay-free ECC in embedded memories
Microarchitecture of the 80960 high-integration processors
Application specific microprocessor [NS3200/EP family]
HAp-FT: A Hybrid Approximate Fault Tolerance Framework for DNN Accelerator
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy
Energy-efficient implementations of GF (p) and GF(2m) elliptic curve cryptography
Dynamic associative caches: Reducing dynamic energy of first level caches
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits
Improving the reliability of on-chip L2 cache using redundancy
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992
One-Chip System Integration for GSM with the DSP KISS-16V2
A voting-based working set assessment scheme for dynamic cache resizing mechanisms
Techniques for increasing effective data bandwidth
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Intertwined Development and Formal Verification of a 60x Bus Model
Clock mesh synthesis method using the Earth Mover's Distance under transformations
Integrating thermocouple sensors into 3D ICs
On short circuit power estimation of CMOS inverters
Hierarchical Image Computation with Dynamic Conjunction Scheduling
TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective
Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions
Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area
Time-Stamped Transition Density for the Estimation of Delay Dependent Switching Activities
Dynamic Branch Decoupled Architecture
Dynamic Flip-Flop with Improved Power
From ASIC to ASIP: The Next Design Discontinuity
A New Architecture for Signed Radix-2m Pure Array Multipliers
TAXI: Trace Analysis for X86 Interpretation
On Detecting Bridges Causing Timing Failures