yusuke1997/dblp-id-title huggingface dataset:
Emulating and diagnosing IR-drop by using dynamic SDF
Optimal topology exploration for application-specific 3D architectures
Architecture-level thermal behavioral characterization for multi-core microprocessors
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow
Short-Circuit Compiler Transformation: Optimizing Conditional Blocks
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design
NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults
A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC
Multi-parametric improvements for embedded systems using code-placement and address bus coding
Logic rectification and synthesis for engineering change
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture
18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013
A fractional delay-locked loop for on chip clock generation applications
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
Delay estimation for technology independent synthesis
Adiabatic CMOS gate and adiabatic circuit design for low-power applications
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs
Run-time energy estimation in system-on-a-chip designs
Hardware Trojan Detection by Fine-grained Power Domain Partitioning
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling
Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
A local optimal method on DSA guiding template assignment with redundant/dummy via insertion
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors
A method for debugging of pipelined processors in formal verification by correspondence checking
A fast digit-serial systolic multiplier for finite field GF (2 m )
A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver
A fast logic simulator using a look up table cascade emulator
Diagnosing Single Faults for Interconnects in SRAM Based FPGAs
Formal Verification Method for Combinatorial Circuits at High Level Design
MCSSim: A memory channel storage simulator
L-shape based layout fracturing for e-beam lithography
Low energy level converter design for sub-V th logics
Retiming for Synchronous Data Flow Graphs
A low-power video segmentation LSI with boundary-active-only architecture
AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs
A power driven two-level logic optimizer
Feasible two-way circuit partitioning with complex resource constraints
Cascaded time difference amplifier using differential logic delay cell
Verification of timed circuits with symbolic delays
An optimum fitting algorithm for generation of reduced-order models
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
Layer assignment for reliable system-on-package
Circuit design using stripe-shaped PMELA TFTs on glass
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture
System-wide profiling and optimization with virtual machines
DLPS: Dynamic laser power scaling for optical Network-on-Chip
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters
MPIM: Multi-purpose in-memory processing using configurable resistive memory
PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion
Localized random access scan: Towards low area and routing overhead
Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate Formulation
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique
Partitioned and overhead-aware scheduling of mixed-criticality real-time systems
22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors
A staircase structure for scalable and efficient synthesis of memristor-aided logic
Efficient DDD-based term generation algorithm for analog circuit behavioral modeling
TreeNet: Deep Point Cloud Embedding for Routing Tree Construction
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach
FPGA-based Heterogeneous Solver for Three-Dimensional Routing
Multi-project chip service for university and industry in Taiwan
d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Nonvolatile memory allocation and hierarchy optimization for high-level synthesis
A 3-step approach for performance-driven whole-chip routing
K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided Attacks
Machine learning and structural characteristics for reverse engineering
PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool
Crosstalk analysis using reconvergence correlation
An artificial neural network approach for screening test escapes
A real-time permutation entropy computation for EEG signals
Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
Effective platform-based development for large-scale systems design
High performance of short-channel MOSFETs due to an elevated central-channel doping
Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning
A high performance bus communication architecture through bus splitting
Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment Wires
Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-V
Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper)
Hardware security strategies exploiting nanoelectronic circuits
A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge
Three parameters to find functional decompositions
SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating
Post-routing redundant via insertion with wire spreading capability
Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology
Slack redistribution for graceful degradation under voltage overscaling
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory
Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing
MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation
A frequency separation macromodel for system-level simulation of RF circuits
A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compression
Efficient Sublogic-Cone-Based Switching Activity Estimation using Correlation Factor
Exploiting Reversible Computing for Verification: Potential, Possible Paths, and Consequences
A robust pixel-based RET optimization algorithm independent of initial conditions
Efficient sparsification of dense circuit matrices in model order reduction
Electromigration recovery modeling and analysis under time-dependent current and temperature stressing
Optimizing embedded applications using programmer-inserted hints
Thermal-aware post compilation for VLIW architectures
Embedded software generation from system level design languages
Efficient synthesis of AND/XOR networks
Towards Automated Testing of Multiplexers in Fully Programmable Valve Array Biochips
A General Equivalence Checking Framework for Multivalued Logic
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation
Formal verification based on assume and guarantee approach - a case study (short paper)
A current-integration-based CMOS amperometric sensor with 1.2 μm × 2.05 μm electroless-plated microelectrode array for high-sensitivity bacteria counting
Gravity: An Artificial Neural Network Compiler for Embedded Applications
Implementation of H.264/AVC decoder for mobile video applications
A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel
Design of Nonlinear Switched-Current Circuits Using Building Block Approach
Hard Error Correction in STT-MRAM
Logic and Layout Aware Voltage Island Generation for Low Power Design
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage
BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems
CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support
Effect of aging on linear and nonlinear MUX PUFs by statistical modeling
Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics
Strategic circuits for neuromodulation of the visual system
Graph Partitioning Approach for Fast Quantum Circuit Simulation
PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement
A Graph Neural Network Method for Fast ECO Leakage Power Optimization
Integer Programming Models for Optimization Problems in Test Generation
Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits
Block-level 3D IC design with through-silicon-via planning
Instruction set and functional unit synthesis for SIMD processor cores
An image sensor/processor 3D stacked module featuring ThruChip interfaces
Leakage control in FPGA routing fabric
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
A high-speed and low-complexity lens distortion correction processor for wide-angle cameras
Exploring emerging CNFET for efficient last level cache design
The design and implementation of a low-latency on-chip network
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier
Signal-to-Memory Mapping Analysis for Multimedia Signal Processing
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products
A new K-way partitioning approach for multiple types of FPGAs
A new approach for an AHDL based on system semantics
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction
Soft Error and Its Countermeasures in Terrestrial Environment
Efficient BMC for Multi-Clock Systems with Clocked Specifications
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs
Test circuits for substrate noise evaluation in CMOS digital ICs
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial)
Delay modeling and static timing analysis for MTCMOS circuits
Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators
ASAX: Automatic security assertion extraction for detecting Hardware Trojans
Deep learning-based framework for comprehensive mask optimization
An evaluation of an energy efficient many-core SoC with parallelized face detection
Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model
Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells
An image-sensor-based optical receiver fabricated in a standard 0.35-µm CMOS technology for free-space optical communications
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs
Coupling-aware Dummy Metal Insertion for Lithography
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators
Fast simulation of large networks of nanotechnological and biochemical oscillators for investigating self-organization phenomena
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
Statistical modeling of cross-coupling effects in VLSI interconnects
FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy Optimization
Robust sample preparation on digital microfluidic biochips
Iterative disparity voting based stereo matching algorithm and its hardware implementation
An FPGA based Network Interface Card with Query Filter for Storage Nodes of Big Data Systems
Time-domain performance bound analysis for analog and interconnect circuits considering process variations
Predictive models and CAD methodology for pattern dependent variability
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Runtime Software Selection for Adaptive Automotive Systems
Exploring adjacency in floorplanning
Duo-binary circular turbo decoder based on border metric encoding for WiMAX
A design of high speed double precision floating point adder using macro modules
A reconfigurable platform for the design and verification of domain-specific accelerators
Optimizing Temporal Decoupling using Event Relevance
ML for Computational Lithography: Practical Recipes
Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL
High-level specification and efficient implementation of pipelined circuits
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
Finding the best system design flow for a high-speed JPEG encoder
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture
Accelerate pattern recognition for cyber security analysis
Speeding up single pass simulation of PLRUt caches
Timing Analysis beyond Complementary CMOS Logic Styles
Ensuring system security through proximity based authentication
A system-level perspective to understand the vulnerability of deep learning systems
Yield driven gate sizing for coupling-noise reduction under uncertainty
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs
Adaptive power management for real-time event streams
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency
Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer
A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis
A high-level synthesis flow for custom instruction set extensions for application-specific processors
Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition
Minimization of Free BDDs
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing
Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models
Evaluating cost-performance tradeoffs for system level applications
A versatile recognition processor for sensor network applications
An integrated temperature-cycling acceleration and test technique for 3D stacked ICs
Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters
Technique for controlling power-mode transition noise in distributed sleep transistor network
Memory-aware mapping and scheduling of tasks and communications on many-core SoC
NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Energy and performance driven circuit design for emerging phase-change memory
Speed binning with high-quality structural patterns from functional timing analysis (FTA)
Proceedings of the 30th Asia and South Pacific Design Automation Conference, ASPDAC 2025, Tokyo, Japan, January 20-23, 2025
An efficient and globally convergent homotopy method for finding DC operating points of nonlinear circuits
Thermal-driven multilevel routing for 3-D ICs
ICD 2 S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method
A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System
Predictable design of low power systems by pre-implementation estimation and optimization
Buffer minimization in pipelined SDF scheduling on multi-core platforms
Modern FPGA constrained placement
The impact of hot carriers on timing in large circuits
BufFormer: A Generative ML Framework for Scalable Buffering
Parallel discrete event simulation of Transaction Level Models
A buffer planning algorithm based on dead space redistribution
MESGA: An MPSoC based embedded system solution for short read genome alignment
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level
Boosting Graph Spectral Sparsification via Parallel Sparse Approximate Inverse of Cholesky Factor
Minimization of fractional wordlength on fixed-point conversion for high-level synthesis
A full 4-channel 60 GHz direct-conversion transceiver
Routing perturbation for enhanced security in split manufacturing
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
EA-HRT: An Energy-Aware scheduler for Heterogeneous Real-Time systems
Combinatorial group testing methods for the BIST diagnosis problem
A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips
Bound-based identification of timing-violating paths under variability
A High Speed and Low Power Phase-Frequency Detector and Charge - pump
A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
Functional extension of structural logic optimization techniques
The design of a USB device controller IYOYOYO
Causality based generation of directed test cases
Don't cares in logic minimization of extended finite state machines
Design of A 2.4-GHz integrated frequency synthesizer
Fast data-cache modeling for native co-simulation
Efficient techniques for 3-D impedance extraction using mixed boundary element method
Design of networks on chips for 3D ICs
A mixed-signal simulator for VHDL-AMS
Machine learning and systems for building the next generation of EDA tools
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Improving Efficiency in Neural Network Accelerator using Operands Hamming Distance Optimization
Minimum-energy driving speed profiles for low-speed electric vehicles
Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement
Analytical placement for rectilinear blocks
Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication
Speed binning aware design methodology to improve profit under parameter variations
The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial Defenders
Detection and Classification of Malicious Bitstreams for FPGAs in Cloud Computing
Workload-aware static aging monitoring of timing-critical flip-flops
Design for manufacturability: a path from system level to high yielding chips: embedded tutorial
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS
Power distribution network modeling for 3-D ICs with TSV arrays
Automatic timing granularity adjustment for host-compiled software simulation
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs
Automatic formal verification of reconfigurable DSPs
Detecting support-reducing bound sets using two-cofactor symmetries
Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems
The impact of inverse narrow width effect on sub-threshold device sizing
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis
Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Design methodology of low-power CMOS RF-ICs
High-speed stochastic circuits using synchronous analog pulses
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Incremental high-level synthesis
Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip
GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver
REIN: a robust training method for enhancing generalization ability of neural networks in autonomous driving systems
Efficient throughput-guarantees for latency-sensitive networks-on-chip
Studying interactions between prefetching and cache line turnoff
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
Electronic data book: current status of standard representation and future perspective
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach
Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems
Virtual prototyping of Cyber-Physical Systems
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper)
SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs
Accelerate Non-unit Stride Convolutions with Winograd Algorithms
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Discovering the input assumptions in specification refinement coverage
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Non-binary cyclic ADC with correlated level shifting technique
From restrictive to prescriptive design
The Shining embedded system design methodology based on self dynamic reconfigurable architectures
Calculating the effective capacitance for the RC interconnect in VDSM technologies
Reduced-Order Modelling of Time-Varying Systems
Abridged addressing: a low power memory addressing strategy