yusuke1997/dblp-id-title huggingface dataset:
Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture
Determining Cost-Effective Multiple Issue Processor Designs
Architectural Synthesis of Timed Asynchronous Systems
Dependency-Aware Parallel Routing for Large-Scale FPGAs
Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors
Heuristic Minimization of Synchronous Relations
Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules
Bandwidth optimization in asynchronous NoCs by customizing link wire length
Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs
HBM-Aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed
On thin Boolean functions and related optimum OBDD ordering
Adaptive Pipeline Depth Control for Processor Power-Management
QRAM-Quick access memory system
Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System
Trail: A Track-Based Logging Disk Architecture for Zero-Overhead Writes
Trace driven modelling and performance evaluation of tightly coupled multiprocessor systems
A 75 MHz CMOS digital convolver
BADGR: A practical GHR implementation for TAGE branch predictors
Channel Segmentation Design for Symmentrical FPGAs
DAGAR: an automatic pipelined microarchitecture synthesis system
Pixel-DNA: Increasing Robustness of Approximate DNA Storage for Images by Using Hierarchical Deduplication
FPGA Emulation of Quantum Circuits
Message from the General Chair ICCD 2020
Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAs
Initialization Isuues in the Synthesis of Asynchronous Circuits
Exploiting spare resources of in-order SMT processors executing hard real-time threads
Test generation for multiple state-table faults in finite-state machines
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
Neural Trojans
Optimization of Mutant Space for RTL Test Generation
A flexible structure of standard cell and its optimization method for near-threshold voltage operation
TriMedia CPU64 Application Development Environment
3D Crosspoint Memory as a Parallel Architecture for Computing Network Reachability
A C-Testable Carry-Free Divider
Collate: Collaborative Neural Network Learning for Latency-Critical Edge Systems
Hybrid system level power consumption estimation for FPGA-based MPSoC
Systolic implementation of neural networks
Understanding variance propagation in stochastic computing systems
EQUIPE: Parallel equivalence checking with GP-GPUs
Verification Techniques for a MIPS Compatibvle Embedded Control Processor
CNFET-based high throughput register file architecture
Energy-efficient execution of data-parallel applications on heterogeneous mobile platforms
Area, Performance, and Yield Implications of Redundancy in On-Chip Caches
DSP for the Third Generation Wireless Communications
A Decompression Architecture for Low Power Embedded Systems
Test generation of C-testable array dividers
Fast Minimum and Maximum Selection
CoolBudget: Data center power budgeting with workload and cooling asymmetry awareness
A parallel algorithm for fault simulation based on PROOFS
Decomposition of Finite State Machines for Area, Delay Minimization
Overview of the Monsoon Project
CG-Resync: Conversion-guided resynchronization for a SSD-based RAID array
Red team: Design of intelligent hardware trojans with known defense schemes
Iron-Dome: Securing IoT Networked Systems at Runtime by Network and Device Characteristics to Confine Malware Epidemics
A Fast Division Algorithm for VLSI
On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions
Using checksum to reduce power consumption of display systems for low-motion content
An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations
A scan chain optimization method for diagnosis
Back-End Layout Reflection for Test Chip Design
The role of synthesis in an ASIC design environment
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors
On Reducing Register Pressure and Energy in Multiple-Banked Register Files
Low power SRAM design using hierarchical divided bit-line approach
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
A novel profiled side-channel attack in presence of high Algorithmic Noise
Special Session: Harness the Power of DERs for Secure Communications in Electric Energy Systems
ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator
Design and Test-The Two Sides of a Coin
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings
Early Quantification and Partitioned Transition Relations
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors
I/O Pad Assignment Based on the Circuit Structure
Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor
Multiple Fault Detection in CMOS Logic Circuits
Continuations in Hardware-Software Codesign
Three-Dimensional Cache Design Exploration Using 3DCacti
Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures
A 690 ps read-access latency register file for a GHz integer microprocessor
Enabling technologies for memory compression: Metadata, mapping, and prediction
Design Flow Enhancements for DNA Arrays
Smart-pixel array processors based on optimal cellular neural networks for space sensor applications
Capturing Synchronization Specifications for Sequential Compositions
Concurrent timing optimization of latch-based digital systems
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Floating point CORDIC for matrix computations
Re-synthesis in technology mapping for heterogeneous FPGAs
Timing-Abstract Circuit Design in Transaction-Level Verilog
Improving multilevel PCM reliability through age-aware reading and writing strategies
A study on performance benefits of core morphing in an asymmetric multicore processor
Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links
Towards Efficient Microarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality Era
Fast Hierarchical Floorplanning with Congestion and Timing Control
Memristor-based IMPLY logic design procedure
Opportunistic Migration for Hybrid Memories While Mitigating Aging Effects
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction
Making register file resistant to power analysis attacks
Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997
Embedded System Design Issues (The Rest of the Story)
CMOS Processor Circuit Design in Hewlett-Packard's Series 700 Workstations
Cerasure: Fast Acceleration Strategies For XOR-Based Erasure Codes
RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance
A methodology for the control and custom VLSI implementation of large-scale Clos networks
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches
Modular BIST concept for microprocessors
Hermes: Accelerating Packet Processing in DPU with Neural Network
String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation
SID: synthesis of integral design
Directions in Futrue High End Processors
A strategy for avoiding pipeline interlock delays in a microprocessor
Hierarchical Simulation of MOS Circuits Using Extracted Functional Models
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor
Data parallel fault simulation
SAT-Based Algorithms for Logic Minimization
Transitive Closure and Graph Component Labeling on Realistic Processor Arrays Based on Reconfigurable Mesh Network
Is Wireless Data Dead?
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms
OK, If These CAD Tools Are So Great, Why Isn't My Chip Design On Schedule?
Timing error masking by exploiting operand value locality in SIMD architecture
DFM is dead - Long live DFM
A Survey of Techniques for Formal Verification of Combinational Circuits
Low-Power, High-Speed CMOS VLSI Design
Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation
The Message Driven Processor: An Integrated Multicomputer Processing Element
Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack
ScalaHDL: Express and test hardware designs in a Scala DSL
PID controlled thermal management in photonic network-on-chip
Optimizing Structural Modification Operation for B+-Tree on Byte-Addressable Devices
ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits
The channel intersection problem in the building block style layout
A Vector Memory System Based on Wafer-Scale Integrated Memory Arrays
Dynamic AC-scheduling for hardware cores with unknown and uncertain information
Ring oscillator physical unclonable function with multi level supply voltages
Aliasing errors in signature analysis testing of integrated circuits
New Challenges for Video Servers: Performance of Non-Linear Applications under User Choice
A Low Power Pseudo-Random BIST Technique
The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost
High-Performance VLSI Processor for Robot Inverse Dynamics Computation
TileMap: Mapping Multi-Head Attention on Spatial Accelerators with Tile-based Analysis
HS-BAS: A hybrid storage system based on band awareness of Shingled Write Disk
Physical synthesis of DNA circuits with spatially localized gates
Fast, Ring-Based Design of 3D Stacked DRAM
An Approach to Network Caching for Multimedia Objects
Is there always performance overhead for regular fabric?
Lowering the latency of interfaces for rationally-related frequencies
Reconfigurable Dataflow Optimization for Spatiotemporal Spiking Neural Computation on Systolic Array Accelerators
OpenCGRA: An Open-Source Unified Framework for Modeling, Testing, and Evaluating CGRAs
Trends and Future Directions in Nano Structure Based Computing and Fabrication
2017 IEEE International Conference on Computer Design, ICCD 2017, Boston, MA, USA, November 5-8, 2017
Fixed-Width Multiplier for DSP Application
Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration
Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier
Fault Dictionary Size Reduction through Test Response Superposition
On design vulnerability analysis and trust benchmarks development
Special purpose FPGA for high-speed digital telecommunication systems
Testing-what's missing? An incomplete list of challenges
Desgin for Testability of Asynchronous Sequential Circuits
Integration and packaging plateaus of processor performance
Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space exploration
A Tool for Automatic Generation of BISTed and Transparent BISTed Rams
Design of Instruction Stream Buffer with Trace Support for X86 Processors
Technology Mapping via Transformations of Function Graphs
Efficent Boolean Matching Algorithm for Cell Libraries
Latency Lags Bandwidth
IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
RepKV: A Replicated Key-Value Store to Boost Multiple Indices for Key-Value Separation
HosNa: A DPC++ Benchmark Suite for Heterogeneous Architectures
QD-Compressor: a Quantization-based Delta Compression Framework for Deep Neural Networks
When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices
To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
Frame-based and thread-based power management for mobile games on HMP platforms
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme
Design and Evaluation of an N-Trace Compliant Hardware Tracer for RISC-V Processors
Improving cache efficiency via resizing + remapping
Reinforcement Learning-Driven Co-Scheduling and Diverse Resource Assignments on NUMA Systems
Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique
SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations
Is single-scheme Trojan prevention sufficient?
An Evaluation of Move-Based Multi-Way Partitioning Algorithms
Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems
LPScan: An algorithm for supply scaling and switching activity minimization during test
PARET: an integrated visual tool for the study of parallel systems
A Fine Grain Architecture for Parallel Fault Simulation
Design and application trade-offs between high-density and high-speed ASICs
A rule based logic reorganization system LORES/EX
Wearable Computers: Merging Information Space with the Workspace
Assertion Checking of Behavioral Descriptions with Non-linear Solver
A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter
Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells
Interconnect Considerations For High Performance Network on Chip Designs
HL-DNA: A Hybrid Lossy/Lossless Encoding Scheme to Enhance DNA Storage Density and Robustness for Images
Towards the Formal Verification of Lower System Layers in Automotive Systems
Advanced EDA Tools for High-Performance Design
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
A Reconfiguration-Based Yield Enhancement System
An effective datapath design methodology for high-frequency design
Power efficient register file update approach for embedded processors
Physical Design Challenges for Billion Transistor Chips
Smart-DNN: Efficiently Reducing the Memory Requirements of Running Deep Neural Networks on Resource-constrained Platforms
Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project
Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis
Auto-tuning of AI/ML Graphs for Optimal Performance in a Heterogenous Processor System
High accuracy approximate multiplier with error correction
Designing Self-Testable Cellular Arrays
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition
Timing Characterization of Dual-edge Triggered Flip-flops
Synthesis of Timed Asynchronous Circuits
Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification
Application of symbolic computer algebra to arithmetic circuit verification
VOSCH: Voltage scaled cache hierarchies
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning
Motion-Control: The Power Side of Disk Drives
VLSI support for copyback caching protocols on Futurebus
Benchmarks and performance analysis of decimal floating-point applications
A TSC Evaluation Function for Combinational Circuits
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints
VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication
A Cost-Efficient NVM-Based Journaling Scheme for File Systems
WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders
Schematic specification of datapath layout
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory
Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension
A programmable routing controller for flexible communications in point-to-point networks
Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation Environments
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation
Supporting Dynamic Translation Granularity for Hybrid Memory Systems
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield
Dichotomy-based Model for FSM Power Minimization
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
A low-jitter phase-locked resonant clock generation and distribution scheme
An efficient reliability simulation flow for evaluating the hot carrier injection effect in CMOS VLSI circuits
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions
An Algorithm for Dynamically Reconfigurable FPGA Placement
Representation Learning for Digital Integrated Circuit Design Automation
A Built-In Self-Testing Approach for Minimizing Hardware Overhead
4-output Programmable Spin Wave Logic Gate
Logical Verification of the NVAX CPU Chip Design
Concolic Testing for Quantum Compilers
CMOS Comparators for High-Speed and Low-Power Applications
Estimating aliasing in CA and LFSR based signature registers
Non-arithmetic carry chains for reconfigurable fabrics
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits
Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment
Post-silicon verification for cache coherence
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node
High-Level vs. RTL Combinational Equivalence: An Introduction
Sparkle: A High Efficient Sparse Matrix Multiplication Accelerator for Deep Learning
Fast arbiters for on-chip network switches
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip
Test and Validation for Monsoon Processing Elements
On dynamic polymorphing of a superscalar core for improving energy efficiency
Internal ECL-BiCMOS translator circuits in half micron technology
NATSA: A Near-Data Processing Accelerator for Time Series Analysis
Ternary cache: Three-valued MLC STT-RAM caches
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Real-time computing of optical flow using adaptive VLSI neuroprocessors
Accelerating Garbage Collection of 3D Flash Memory via Exploiting Inter-Channel Parallelism
Test points selection process and diagnosability analysis of analog integrated circuits
Computational models for the age of multicore processing
Resilient mobile cognition: Algorithms, innovations, and architectures
A microprogrammable VLSI routing controller for HARTS
Exploiting cache coherence for effective on-the-fly data tracing in multicores
MemSort: In-Memory Sorting Architecture
Reduction of Crosstalk Pessimism using Tendency Graph Approach
Extending the Applicability of Parallel-Serial Scan Designs
csRNA: Connection-Scalable RDMA NIC Architecture in Datacenter Environment
AMBIANT: Automatic Generation of Behavioral Modifications for Testability
Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients
Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations
Finding the longest simple path in cyclic combinational circuits
Guided lightweight Software test qualification for IP integration using Virtual Prototypes
Energy Efficient Asymmetrically Ported Register Files
Efficient RISC-V-on-x64 Floating Point Simulation
Power-aware soft error hardening via selective voltage scaling
Using Application-Level Thread Progress Information to Manage Power and Performance
A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic
Gate array technology
Equivalence Checking Using Abstract BDDs
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
Coping with The Variability of Combinational Logic Delays
Optimal Clock Period Clustering for Sequential Circuits with Retiming
Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores
A Tag Coprocessor Architecture for Symbolic Languages
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
DEQ: Dynamic Element-wise Quantization for Efficient Attention Architecture
Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions
Vision Transformer Inference on a CNN Accelerator
Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system
Requirements and Concepts for Transaction Level Assertions
A machine learning approach to modeling power and performance of chip multiprocessors
Scattered superpage: A case for bridging the gap between superpage and page coloring
Design automation of multiple-demand mixture preparation using a K-array rotary mixer on digital microfluidic biochips
Area-oriented synthesis for pass-transistor logic
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture
Placement and routing of RF embedded passive designs in LCP substrate
Conversion driven design of binary to mixed radix circuits
ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers
Routing Architectures for Hierarchical Field Programmable Gate Arrays
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit
RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing
Low Power Test Data Compression Based on LFSR Reseeding
Scaling Manufacturability Software to Thousands of Processors
A Design-for-Test Solution for Monolithic 3D Integrated Circuits
Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays
TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers
Early Zero Detection
A class of close-to-optimum adder trees allowing regular and compact layout
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW
A Flexible Data Structure for Efficient Buffer Insertion
FIMSIM: A fault injection infrastructure for microarchitectural simulators
Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988
Implicit Verification of Structurally Dissimilar Arithmetic Circuits
A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance
Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function
FPGA Energy Efficiency by Leveraging Thermal Margin
A simple adaptive wormhole routing algorithm for MIMD systems
SoftFusion: A Low-Cost Approach to Enhance Reliability of Object Detection Applications
Scalable memory architecture for soft-core processors
AICAWS: Arithmetic Intensity Based Cache-Conscious Adaptive Warp Scheduler
ISVDA: An in Storage Processing Accelerator for Visual Data Analysis
NRHI: A Concurrent Non-Rehashing Hash Index for Persistent Memory
Accurate prediction of detailed routing congestion using supervised data learning
A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication
RepEC-Duet: Ensure High Reliability and Performance for Deduplicated and Delta-Compressed Storage Systems
Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAM
Floorplan optimization on multiprocessors
Built-in self-test for interposer-based 2.5D ICs
Performance-Driven Global Routing for Cell Based ICs
Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-Chip
A logic network synthesis system, SYLON