yusuke1997/dblp-id-title huggingface dataset:
3D integration technology for set-top box application
Plasma Hydrophilic Treatment for Improved Wafer Bonding Strength via Polysilazane
Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications
Development of 3D-IC Embedded Flexible Hybrid System
Additive interconnect fabrication by picosecond Laser Induced Forward Transfer
Design of 60 GHz contactless probe system for RDL in passive silicon interposer
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration
Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits
6 Tbps/W, 1 Tbps/mm 2 , 3D interconnect using adaptive timing control and low capacitance TSV
A study on wafer level TSV build-up integration method
Impact of 3D design choices on manufacturing cost
Cost-Effective Low-Temperature Hybrid Bonding Using Layer Transfer Technology
3D stacking using Cu-Cu direct bonding
Physical design of a 3D-stacked heterogeneous multi-core processor
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology
Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications
Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration
Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield
Non-contact wafer-level TSV connectivity test methodology using magnetic coupling
3D TSV based high frequency components for RF IC and RF MEMS applications
2016 IEEE International 3D Systems Integration Conference, 3DIC 2016, San Francisco, CA, USA, November 8-11, 2016
Characterization of particle beds in percolating thermal underfills based on centrifugation
Wet cleaning process for high-yield via-last TSV formation
A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicing
Mechanical characterization of residual stress around TSV through instrumented indentation algorithm
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges
Chip to wafer copper direct bonding electrical characterization and thermal cycling
3D memory stacking for fast checkpointing/restore applications
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
Path to 3D heterogeneous integration
Multi-step approach for thermal optimization of 3D-IC and package
Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structures
A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC
Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing
From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose
Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI
Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs
Variation of thermal stress in TSV structures caused by crystallinity of electroplated copper interconnections
Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC
Reliability aspects of 3D-oriented heterogeneous device design related to stress sensitivity of MOS transistors
A 3D SoC design for H.264 application with on-chip DRAM stacking
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories
Hydrolysis-Tolerant Hybrid Bonding in Ambient Atmosphere for 3D Integration
TSV development for miniaturized MEMS acceleration switch
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects
Evaluation of energy-recovering interconnects for low-power 3D stacked ICs
A novel concept for ultra-low capacitance via-last TSV
Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects
Thermotropic liquid crystalline polyimides toward high heat conducting materials for 3D chip stack
Invited talk: Progress in 3D integrated circuits
Integration of multi physics modeling of 3D stacks into modern 3D data structures
High-speed via hole filling using electrophoresis of Ag nanoparticles
Fault localisation of defects using Electro Optical Terahertz Pulse Reflectometry and 3D EM modelling with Virtual Known Good Device
Pathfinder 3D: A flow for system-level design space exploration
2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012
Development of high accuracy wafer thinning and pickup technology for thin wafer
Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional Devices
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration
Development of wafer thinning and dicing technology for thin wafer
Developing digital test sequences for through-silicon vias within 3D structures
Development of Laser-Assisted Bonding with Compression (LABC) Process for 3D IC Integration
High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture
Chiplet Set For Artificial Intelligence
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs
Design rule check and layout versus schematic for 3D integration and advanced packaging
3D-Scalable Adaptive Scan (3D-SAS)
Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC
Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration
Measurement Point Selection Algorithms for Testing Power TSVs
3DIC multi-project-wafer program: A collaboration to provide fabrication access
2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, October 8-10, 2019
Fabrication and bonding process of fine pitch Cu pillar bump on thin Si chip for 3D stacking IC
2014 International 3D Systems Integration Conference, 3DIC 2014, Kinsdale, Ireland, December 1-3, 2014
Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package
RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits
Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer
TSV metrology and inspection challenges
Ultra-High Density Deep Trench Capacitor (DTC) for 3DIC Integration
Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology
High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer
Influence of wafer thinning process on backside damage in 3D integration
Face-Down and Heterogeneous Chip Bonding Technology on Waffle-Wafer for Bumpless Chip-an-Wafer (COW) Package
Using NEM relay to improve 3DIC cost efficiency
Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development
Modeling and analysis of defects in through silicon via channel for non-invasive fault isolation
Nano-Function materials for TSV technologies
Electroless metal deposition for IC and TSV applications
Study of MacEtch using Additives for Preparation of TSV
A Study on a Tether-Less Approach Towards Micro-Transfer-Printing of Large-Footprint Power Micro-Inductor Chiplets
A Temporary Bonding De-Bonding Tape with High Thermal Resistance, Easy peeling and Excellent TTV for 3DIC
Die to Wafer Direct Hybid Bonding Demonstration with High Alignment Accuracy and Electrical Yields
TSV capacitance aware 3-D floorplanning
3D-IC dynamic thermal analysis with hierarchical and configurable chip thermal model
An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling
Pre-bond testing of die logic and TSVs in high performance 3D-SICs
3D heterogeneous integration for novel functionality
Miniature wireless activity monitor using 3D system integration
Recent advances and new trends in nanotechnology and 3D integration for semiconductor industry
3D cache hierarchy optimization
Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assemblies
Comparative analysis of two 3D integration implementations of a SAR processor
A built-in test circuit for open defects at interconnects between dies in 3D ICs
3D integrated circuits for lab-on-chip applications
Vertical Optical and Electrical Interconnection for Chip-Scale-Packaged Si Photonic Transceivers
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems
Characterization of Nitride Passivated Cu Surface for Low-Temperature Cu-Cu Bonding
Interposer based integration to achieve high speed interfaces for ADC application
Room-temperature bonding mechanism of compliant bump with ultrasonic assist
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered
A low stress bond pad design optimization of low temperature solder interconnections on TSVs for MEMS applications
Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications
Thermal Analysis of Reflow Process for PIC-Embedded Package Substrate with 2.3D RDL Interposer for Co-Packaged Optics
Thermo-mechanical evaluation of 3D packages
High speed I/O and thermal effect characterization of 3D stacked ICs
Design of a 3-D stacked floating-point Goldschmidt divider
3D multiprocessor with 3D NoC architecture based on Tezzaron technology
Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route
Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages
A study of IR-drop noise issues in 3D ICs with through-silicon-vias
Effects of 3-D stacked vector cache on energy consumption
Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes
Dedicated MEMS-based test structure for 3D SiP interconnects reliability investigation
Test-TSV estimation during 3D-IC partitioning
3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron
A 3D heterogeneous integration method using LTCC wafer for RF applications
Through-substrate via (TSV) with embedded capacitor as an on-chip energy storage element
A 3D multi-layer CMOS-RRAM accelerator for neural network
Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler
Cost modeling and analysis for the design, manufacturing and test of 3D-ICs
3D-enabled customizable embedded computer (3DECC)
Impact of 2-Dimensional Materials for 3D Power IC
Enabling power distribution network analysis flows for 3D ICs
Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing
Characterization of stress distribution in ultra-thinned DRAM wafer
Enabling automatic system design optimization through Assembly Design Kits
Fault isolation of short defect in through silicon via (TSV) based 3D-IC
Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package
Vertically integrated processor and memory module design for vector supercomputers
Power-Performance Advantages of InFO Technology for Advanced System Integration
In-tier diagnosis of power domains in 3D TSV ICs
Silicon Etch with integrated metrology for through silicon via (TSV) reveal
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs
A novel reconfigurable logic device base on 3D stack technology
Surface Modification for Ultrasonic Cu-to-Cu Direct Bonding
Pre bonding metrology solutions for 3D integration
System level evaluation of Silicon imager based see-through Silicon application
3D Integration Technologies for the Stacked CMOS Image Sensors
16-Layer 3D Stacking Based on Self-Assembly Technology for HBM Application
Recent progress in thin wafer processing
Creep Behavior of Low-Temperature Sn-In Solder Using Nanoindentation Test
IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009
Multi-Die to Wafer Bonding Through Plasma-Activated Cu-Cu Direct Bonding in Ambient Conditions
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers
3D integration: Applications and market trends
3D system integration research at IMEC
Manufacturing and test assistance for 3D-Integrated heterogeneous systems
Design tools for the 3D roadmap
X-ray Photon-Counting Imager with CdTe/Si-LSI Stacking
High-bandwidth data transmission of new transceiver module through optical interconnection
High sensitivity fully digital photodetector
The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study
TSV noise coupling in 3D IC using guard ring
3D integration - A server perspective
Temporary bonding strength control for self-assembly-based 3D integration
Silicon-interposer with high density Cu-filled TSVs
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers
Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions
Neuromorphic semiconductor memory
Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications
Evolution of bond technology to hybridized process flows
Performance and process characteristic of glass interposer with through-glass-via(TGV)
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory
Wafer thinning for 3D integration
3D integration technology for 3D stacked retinal chip
Fine-pitch bump-less Cu-Cu bonding for wafer-on-wafer stacking and its quality enhancement
Superconducting Titanium Nitride in Through-Silicon Vias for 3D Integration of Qubits
SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration
Analysis of microbump induced stress effects in 3D stacked IC technologies
Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation
Yield analysis of a novel wafer manipulation method in 3D stacking
A tileable switch module architecture for homogeneous 3D FPGAs
Numerical analysis of bonding process-induced deformation for 3D package
Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration
A study on the edge traces technique for 3D stack chip
Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D Integration
Heterogeneous integration technology for MEMS-LSI multi-chip module
Advances of 3M™ wafer support system
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs
Improved noise coupling performance using optimized Teflon liner with different TSV structures for 3D IC integration
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI
Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC
A high-performance multiported L2 memory IP for scalable three-dimensional integration
Study of Optimizing Stress-Strain Curve of Adhesive for High Expansion Tape
Scalable direct bond technology and applications driving adoption
Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing
Thermal requirements in future 3D processors
PDN impedance and SSO noise simulation of 3D system-in-package with a widebus structure
3D ICs and pixel sensors: The Italian VIPIX project and the European AIDA WP3 project
Fine-grained 3-D integrated circuit fabric using vertical nanowires
Room-Temperature and Compressive Force-Free Metal-Metal Direct Bonding for Heterogeneous Integration of Micro-LED Array on 3D-IC
Review of Hybrid Integration Techniques for Integrating III-V Onta Silicon
Leveraging 3D-IC for on-chip timing uncertainty measurements
A parallel ADC for high-speed CMOS image processing system with 3D structure
Innovative SiC over Si photodiode based dual-band, 3D integrated detector
TSV reveal etch for 3D integration
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration
Fraunhofer's Initial and Ongoing Contributions in 3D IC Integration
Highly conformal and adhesive electroless barrier and Cu seed formation using nanoparticle catalyst for realizing a high aspect ratio cu-filled TSV
The NCSU Tezzaron design kit
Collective and Gang Bonding for Three-Dimensional Integrated Circuits in Chip-on-Wafer Process
Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks
Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuits
Device physics aware 3D electromagnetic simulation of Through-Silicon-Vias in system modeling
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core
Analysis and optimization of a power distribution network in 2.5D IC with glass interposer
Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology
Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges
Design considerations for 2.5-D and 3-D integration accounting for thermal constraints
Implementing wireless communication links in 3-D ICs utilizing wide-band on-chip meandering microbump antenna
Use of optical metrology for wafer level packaging of CMOS image sensor
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs
Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies
A holistic view of chip-level thermal architecture from heterogeneous stacked dice to system level in telecoms applications
Robust verification of 3D-ICs: Pros, cons and recommendations
TSV Formation Using a Direct CU Electroplating on Electroless Plated Barrier Layer with a Low Resistivity
ESD protection networks for 3D integrated circuits
Thermal performance of 3D ICs: Analysis and alternatives
Metal coated polymer spheres for compliant fine pitch ball grid arrays
Thermal Estimation for 3D-ICs Through Generative Networks
Thermal implications of mobile 3D-ICs
Chip-level TSV integration for rapid prototyping of 3D system LSIs
3D system on chip memory interface based on modeled capacitive coupling interconnections
Supression of TSV-Induced Stress by Using Negative Thermal Expansion Material
Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuits
Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics
Advanced wafer bonding solutions for TSV integration with thin wafers
Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bonding
3D floorplan representations: Corner links and partial order
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
Invited talk: Technology and overview of Sony's 3D stacked CMOS image sensor
Study on high performance and productivity of TSV's with new filling method and alloy for advanced 3D-SiP
The issues of automated driving vehicle and the expectations for 3D integration technology
Warpage analysis of organic substrates for 2.1D packaging
Detailed electrical and reliability study of tapered TSVs
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC
Machine Learning-Based Diagnosis of Defects in Chiplet Interconnects
Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging
Mechanical reliability of Cu/low-k interconnects and underfill
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology
Gate Driver IC for GaN Power Device Suitable for 3D Power IC
The dependency of TSV keep-out zone (KOZ) on Si crystal direction and liner material
Monolithic 3D-ICs with single crystal silicon layers
2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015
High productivity thermal compression bonding for 3D-IC
Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system
Predicted thermal stresses in a TSV design
Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking
In-line metrology and inspection for process control during 3D stacking of IC's
Electrical modeling of Through Silicon and Package Vias
Reduction of TSV Pumping
Arithmetic unit design using 180nm TSV-based 3D stacking technology
System-level comparison of power delivery design for 2D and 3D ICs
Low temperature through-Si via fabrication using electroless deposition
3-D thin chip integration technology - from technology development to application
Development of a CAD tool for 3D-FPGAs
Low-Temperature Adhesive Hybrid Bonding Technology with Novel Area-Selective Passivation Layer
Fabrication cost analysis for 2D, 2.5D, and 3D IC designs
Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal
Impacts of though-DRAM vias in 3D processor-DRAM integrated systems
Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation
Layout dependent synthesis for manufacturing costs optimized 3D integrated systems
Copper micro and nano particles mixture for 3D interconnections application
Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design
Clean Dicing: An Alternative Blade Dicing Technique for Minimising Particles in 3D Heterogeneous Integration
Chip-to-chip communication based on capacitive coupling
Interconnect design and analysis for Through Silicon Interposers (TSIs)
Developments of novel vertically integrated pixel sensors in the high energy physics community
Stacked Pixel Sensor/Detector Technology using Au Micro-Bump Junction
Cu-based bonding technology for 3D integration applications
Study of MOSFET thermal stability with TSV in operation temperature using novel 3D-LSI stress analysis
Solution space investigation and comparison of modern data structures for heterogeneous 3D designs
3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bonds
Process Complexity and Cost Considerations of Multi-Layer Die Stacks
Ultra-compact micro-coil realized via multilevel dense TSV coil for MEMs application
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding