yusuke1997/dblp-id-title huggingface dataset:
10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Error under a 2.3GHz Chirp Bandwidth, 2.3GHz/μs Slope, and 50ns Idle Time in 65nm CMOS
An 800MS/s dual-residue pipeline ADC in 40nm CMOS
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage
Integrated capacitive power-management circuit for thermal harvesters with output power 10 to 1000µW
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
26.2 A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS
A 110µW 10Mb/s etextiles transceiver for body area networks with remote battery power
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter
8.7 A 92.7% Peak Efficiency 12V-to-60V Input to 1.2V Output Hybrid DC-DC Converter Based on a Series-Parallel-Connected Switched Capacitor
Free-Running Ring Frequency Synthesizer
Side-Channel Attack Counteraction via Machine Learning-Targeted Power Compensation for Post-Silicon HW Security Patching
15.5 Cryo-CMOS circuits and systems for scalable quantum computing
26.5 A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM
A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication
A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern Wireless Systems
A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems
A 1.8dB NF 112mW Single-Chip Diversity Tuner for 2.6GHz S-DMB Applications
A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM
24.5 A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET
20.1 A 28µW IoT Tag That Can Communicate with Commodity WiFi Transceivers via a Single-Side-Band QPSK Backscatter Communication Technique
19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
Highlights of IEDM 2008
Reconfigurable processor for energy-scalable computational photography
A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD
Session 26 overview: Processor-power management and clocking
Integration of a SiP for GSM/EDGE in CMOS Technology
A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC
Thyristor-Based Volatile Memory in Nano-Scale CMOS
Session 21 overview: Innovative personalized biomédical systems: Technology directions subcommittee
An 8Gb/s Transformer-Boosted Transmitter with >V 00 swing
A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM
1.4 Quantum computing - the next challenge in circuit and system design
21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels
34.5 An 18.5-to-23.6GHz Quad-Core Class-F23 Oscillator Without 2nd/3rd Harmonic Tuning Achieving 193dBc/Hz Peak FoM and 140-to-250kHz 1/f 3 PN Corner in 65nm CMOS
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
A fully integrated multi-CPU, GPU and memory controller 32nm processor
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture
A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvesting
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS
A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS
Session 2 overview: Ultra-high-speed transceivers and equalizers
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM
A 42.2Gb/s 4.3pJ/b 60GHz Digital Transmitter with 12b/Symbol Polarization MIMO
A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
Session 10 overview: Analog techniques
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2 nd -Order Mismatch Error Shaping
Toward Automotive Surround-View Radars
Design of "green" high-performance processor circuits
A calibration-free 800MHz fractional-N digital PLL with embedded TDC
A 60GHz-band 2×2 phased-array transmitter in 65nm CMOS
25.1 A 50.7% peak efficiency subharmonic resonant isolated capacitive power transfer system with 62mW output power for low-power industrial sensor interfaces
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS
A 220-to-275GHz traveling-wave frequency doubler with -6.6dBm Power at 244GHz in 65nm CMOS
An Auto-Selectable-Frequency Pulse-Width Modulator for Buck Converters with Improved Light-Load Efficiency
User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects
A soft self-commutating method using minimum control circuitry for multiple-string LED drivers
8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1
A 10b column driver with variable-current-control interpolation for mobile active-matrix LCDs
12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control
23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices
9.7 An LTE SAW-less transmitter using 33% duty-cycle LO signals for harmonic suppression
Westmere: A family of 32nm IA processors
A 1.1nJ/b 802.15.4a-compliant fully integrated UWB transceiver in 0.13µm CMOS
A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm
13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process
33.8 A Decentralized Daisy-Chain-Controlled Switched-Capacitor Driver for Microrobotic Actuators with 10× Power-Reduction Factor and Over 300V Drive Voltage
An 18Gb/s duobinary receiver with a CDR-assisted DFE
19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOM
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics
23.3 A 0-to-60V-Input VCM Coulomb Counter with Signal-Dependent Supply Current and ±0.5% Gain Inaccuracy from -50°C to 125°C
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
16.3 A 16×16 pixels SPAD-based 128-Mb/s quantum random number generator with -74dB light rejection ratio and -6.7ppm/°C bias sensitivity on temperature
26.1 A 600ch 10b Source-Driver IC with a Charge-Modulation DAC Achieving 1-Horizontal Time of 1.5μs Suitable for 240Hz-Frame-Rate Mobile Displays
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS
13.4 A microwave injection-locking outphasing modulator with 30dB dynamic range and 22% system efficiency in 45nm CMOS SOI
Multiple-output step-up/down switching DC-DC converter with vestigial current control
A CMOS temperature sensor with an energy-efficient zoom ADC and an Inaccuracy of ±0.25°C (3s) from -40°C to 125°C
"Smart life solutions" from home to city
A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor
A pulsed UWB receiver SoC for insect motion control
Session 26 overview: RF techniques for communication and sensing: RF subcommittee
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier
A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS
7.3 A 40nm low-power transceiver for LTE-A Carrier Aggregation
45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR
A 108nW 0.8mm 2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS
A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS
1.4 The Future of Computing: Bits + Neurons + Qubits
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion
24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm
A Low-Power 2.4GHz CMOS Receiver Front-End Using BAW Resonators
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
A 6 th -Order 100μA 280MHz Source-Follower-Based Single-loop Continuous-Time Filter
17.1 A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation
A 145GHz FMCW-Radar Transceiver in 28nm CMOS
15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices
12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels
A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC
26.4 A Cell-Capacitance-Insensitive CMOS Sample-and-Hold Chronoamperometric Sensor for Real-Time Measurement of Small Molecule Drugs in Whole Blood
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory
2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applications
ICs for mobile multimedia communications
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip
An implantable 5mW/channel dual-wavelength optogenetic stimulator for therapeutic neuromodulation research
2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage
33.7 An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface with On-Chip Application Tunable Time-Domain Feature Extraction
Session 18 Overview: Biomedical Devices, Circuits, and Systems Technology Directions Subcommittee
A 12b 22.5/45MS/s 3.0mW 0.059mm 2 CMOS SAR ADC achieving over 90dB SFDR
A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique
15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization
A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
A batteryless thermoelectric energy-harvesting interface circuit with 35mV startup voltage
6.33mW MPEG audio decoding on a multimedia processor
9.9 A 0.6nm resolution 19.8mW eddy-current displacement sensor interface with 126MHz excitation
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition
A Reconfigurable Sub-Array Multiplexing Microelectrode Array System With 24, 320 Electrodes and 380 Readout Channels for Investigating Neural Communication
Deterministic Frequency Boost and Voltage Enhancements on the POWER10 TM Processor
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications
Multiple-Phase Accelerated Current Control in Bidirectional Energy Transfer of Automotive High-Voltage and Low-Voltage Batteries
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm 2 1.89μVrms noise 12b biasing DAC
8.3 A 3GHz ARM Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications
An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver
A 0.55-to-0.9GHz 2.7dB NF full-duplex hybrid-coupler circulator with 56MHz 40dB TX SI suppression
A 0.021mm 2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS
20.1 A 40nm CMOS receiver for 60GHz discrete-carrier indoor localization achieving mm-precision at 4m range
1.4 The road ahead for securely-connected cars
2.3 Granite Rapids-D: Intel Xeon 6 SoC for vRAN, Edge, Networking, and Storage
Foreword: Silicon systems for the Internet of Everything
Session 26 Overview: RF Power-Amplifier and Front-End Techniques Rf Subcommittee
A 3.2Gb/s Semi-Blind-Oversampling CDR
Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee
A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement
Session 29 overview: Advanced biomedical systems: IMMD subcommittee
SkyLake-SP: A 14nm 28-Core xeon® processor
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOS
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS
Session 12 overview: SRAM
A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS
Session 7 overview: Wireless transceivers
31.2 A 0.9V 28MHz Dual-RC Frequency Reference with 5pJ/Cycle and ±200 ppm Inaccuracy from -40°C to 85°C
A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend
Session 7 overview: Optical transceivers and silicon photonics
A 45nm CMOS near-field communication radio with 0.15A/m RX sensitivity and 4mA current consumption in card emulation mode
A 121.4dB DR, -109.8dB THD+N Capacitively-Coupled Chopper Class-D Audio Amplifier
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link
A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time
A sub-electron readout noise CMOS image sensor with pixel-level open-loop voltage amplification
A 606μW mm-Scale Bluetooth Low-Energy Transmitter Using Co-Designed 3.5×3.5mm 2 Loop Antenna and Transformer-Boost Power Oscillator
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor
9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS
A quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with <0.15dB crosstalk penalty
A 2.2μW 94nV/√Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic Implants
22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme
A IMax | max , Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS
A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver
A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
A 70W and 90% GaN-based class-E wireless-power-transfer system with automatic-matching-point-search control for zero-voltage switching and zero-voltage-derivative switching
A wireless and batteryless 130mg 300µW 10b implantable blood-pressure-sensing microsystem for real-time genetically engineered mice monitoring
16.5 A NEMS-array control IC for sub-attogram gravimetric sensing applications in 28nm CMOS technology
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration
An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access
8.7 Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor
A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
EE4: Eureka! The best moments of solid-state circuit design in the 2000s
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs
32.9 An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer Output Combiner
8.8 Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Voltage Micron-Scale Thermal Sensors
Session 6 overview: Ultra-high-speed wireline
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W
A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration
A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f 3 PN Corner Without Harmonic Tuning
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS
A fully integrated power-management solution for a 65nm CMOS cellular handset chip
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
A mm-sized free-floating wirelessly powered implantable optical stimulating system-on-a-chip
F1: Designing secure systems: Manufacturing, circuits and architectures
31.1 An Inductor-Less Capacitor-Less Synchronous Piezoelectric-Electromagnetic Hybrid Energy Harvesting Platform with Coil-Sharing Scheme
23.2 A 1mm 2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s
Ultra-low voltage VLSIs for energy efficient systems
12.4 A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver
29.8 THzID: A 1.6mm2 Package-Less Cryptographic Identification Tag with Backscattering and Beam-Steering at 260GHz
A 13-ENOB 2 nd -order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure
7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
A multipath technique for canceling harmonics and sidebands in a wideband power upconverter
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee
A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS
A 50mW CMOS wind sensor with ±4% speed and ±2° direction error
A 6.7MHz-to-1.24GHz 0.0318mm 2 fast-locking all-digital DLL in 90nm CMOS
6.3 A 45.5μW 15fps always-on CMOS image sensor for mobile and wearable devices
F6: Optical and Electrical Transceivers for 400GbE and Beyond
23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction
3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS
A Low-Power WCDMA Transmitter with an Integrated Notch Filter
11.5 A 2-Phase Soft-Charging Hybrid Boost Converter with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5% Efficiency at a Conversion Ratio of 4.5
Leaner and greener: Adapting to a changing climate of innovation
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time
32.3 A Load-Variation-Tolerant Doherty Power Amplifier with Dual-Adaptive-Bias Scheme for 5G Handsets
A W-band 65nm CMOS transmitter front-end with 8GHz IF bandwidth and 20dB IR-ratio
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management
18.2 A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and energy-efficient stimulation in 0.18μm HVCMOS
Session 13 overview: High-performance transmitters
Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiography
Frequency Compensation of an SOI Bipolar-CMOSDMOS Car Audio PA
A 5.5mW IEEE-802.15.6 wireless body-area-network standard transceiver for multichannel electro-acupuncture application
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs
A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS
21.2 A 0.81mA, -105.2dB THD+N Class-D Audio Amplifier with Capacitive Feedforward and PWM-Aliasing Reduction for Wide-Band-Effective Linearity Improvement
Compact voltage and current stimulation buffer for high-density microelectrode arrays
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data
A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias
Micro Short-Circuit Detector Including S/H Circuit for 1hr Retention and 52dB Comparator Composed of C-Axis Aligned Crystalline IGZO FETs for Li-Ion Battery Protection IC
A 1.5μW 1V 2 nd -Order ΔΣ Sensor Front-End with Signal Boosting and Offset Compensation for a Capacitive 3-Axis Micro-Accelerometer
Session 14 overview: High-resolution ADCs: Data converter subcommittee
15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy
A fully integrated dual-mode CMOS power amplifier for WCDMA applications
A 4-Channel UWB Beam-Former in 0.13μm CMOS using a Path-Sharing True-Time-Delay Architecture
A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control
9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS
28.1 A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving -28dB Worst-Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance
An Integrated Magnetic Sensor with Two Continuous-Time ΔΣ-Converters and Stress Compensation Capability