yusuke1997/dblp-id-title huggingface dataset:
AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning
Adaptive Set-Granular Cooperative Caching
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks
Improving Multiple-CMP Systems Using Token Coherence
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture
Coset coding to extend the lifetime of memory
μDPM: Dynamic Power Management for the Microsecond Era
DMA-aware memory energy management
14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor
Software Directed Issue Queue Power Reduction
Tensor Movement Orchestration in Multi-GPU Training Systems
An Analog Preconditioner for Solving Linear Systems
Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor
Towards scalable, energy-efficient, bus-based on-chip networks
Scatter-Add in Data Parallel Architectures
Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST
Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices
Performance of Hardware Compressed Main Memory
Supporting efficient collective communication in NoCs
CATalyst: Defeating last-level cache side channel attacks in cloud computing
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997
Analysis and Improvement of Valiant Routing in Low-Diameter Networks
G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs
String Figure: A Scalable and Elastic Memory Network Architecture
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions
Dynamic Thermal Management for High-Performance Microprocessors
Interleaved Logical Qubits in Atom Arrays
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
Speculative instruction validation for performance-reliability trade-off
Evaluating MPI Collective Communication on the SP2, T3D, and Paragon Multicomputers
Charge-Aware DRAM Refresh Reduction with Value Transformation
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery
A 3 : Accelerating Attention Mechanisms in Neural Networks with Approximation
Slipstream Execution Mode for CMP-Based Multiprocessors
Detecting Qubit-coupling Faults in Ion-trap Quantum Computers
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
P-OPT: Practical Optimal Cache Replacement for Graph Analytics
GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design
2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors
Improving the Data Cache Performance of Multiprocessor Operating Systems
CARS: A New Code Generation Framework for Clustered ILP Processors
Paying to save: Reducing cost of colocation data center via rewards
Mini-Threads: Increasing TLP on Small-Scale SMT Processors
Veritas - Demystifying Silent Data Corruptions: μArch-Level Modeling and Fleet Data of Modern x86 CPUs
DRAM-Less: Hardware Acceleration of Data Processing with New Memory
Beyond Performance: Some (Other) Challenges for Systems Design
Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings
Crash Consistency in Encrypted Non-volatile Main Memory Systems
Reliability-Aware Data Placement for Heterogeneous Memory Architecture
Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather
FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks
Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance
Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors
Reducing the Scheduling Critical Cycle Using Wakeup Prediction
Efficiently Adapting to Sharing Patterns in Software DSMs
Designing a Cost-Effective Cache Replacement Policy using Machine Learning
WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs
Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors
Elastic-buffer flow control for on-chip networks
Precise Runahead Execution
ScalaGraph: A Scalable Accelerator for Massively Parallel Graph Processing
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
BBB: Simplifying Persistent Programming using Battery-Backed Buffers
Challenging Applications on Fast Networks
The Importance of Generalizability in Machine Learning for Systems
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
Investigating QoS Support for Traffic Mixes with the MediaWorm Router
Evaluating Energy-Saving Strategies on Torus, K-Ary N-Tree, and Dragonfly
Decoupled Value Prediction on Trace Processors
Fg-STP: Fine-Grain Single Thread Partitioning on Multicores
MOPED: Orchestrating interprocess message data on CMPs
Improving DRAM performance by parallelizing refreshes with accesses
Global Context-Based Value Prediction
iPatch: Intelligent fault patching to improve energy efficiency
Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory
MLPerf Power: Benchmarking the Energy Efficiency of Machine Learning Systems from μWatts to MWatts for Sustainable AI
The Effectiveness of SRAM Network Caches in Clustered DSMs
The Synergy of Multithreading and Access/Execute Decoupling
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors
IADVS: On-demand performance for interactive applications
Thread-safe dynamic binary translation using transactional memory
Understanding the Future of Energy Efficiency in Multi-Module GPUs
Architectural Implications of a Family of Irregular Applications
DWT: Decoupled Workload Tracing for Data Centers
New Link Arrangements for Dragonfly Networks
Perceptron-Based Branch Confidence Estimation
Securator: A Fast and Secure Neural Processing Unit
Providing Differentiated Services, Congestion Management, and Deadlock Freedom in Dragonfly Networks
A Topology-Independent Generic Methodology for Deadlock-Free Wormhole Routing
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation
SIPT: Speculatively Indexed, Physically Tagged Caches
Controlled Kernel Launch for Dynamic Parallelism in GPUs
GPU Subwarp Interleaving
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
Exploiting compressed block size as an indicator of future reuse
NUAT: A non-uniform access time memory controller
Efficient Optimization with Encoded Ising Models
Explaining cache SER anomaly using DUE AVF measurement
Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems
Towards high performance paged memory for GPUs
PaCo: Probability-based path confidence prediction
2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era HiPINEB@HPCA 2016, Barcelona, Spain, March 12, 2016
Towards Virtually-Addressed Memory Hierarchies
Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors
Software transparent dynamic binary translation for coarse-grain reconfigurable architectures
ASAP: A Speculative Approach to Persistence
Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings
Co-Designed Architectures for Modular Superconducting Quantum Computers
Lazy Batching: An SLA-aware Batching System for Cloud Machine Learning Inference
Increasing TLB reach by exploiting clustering in page translations
SpArch: Efficient Architecture for Sparse Matrix Multiplication
Cache restoration for highly partitioned virtualized systems
Salus: Efficient Security Support for CXL-Expanded GPU Memory
Reconciling specialization and flexibility through compound circuits
FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads
CARE: A Concurrency-Aware Enhanced Lightweight Cache Management Framework
R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory
The Specialized High-Performance Network on Anton 3
BigDataBench: A big data benchmark suite from internet services
Enabling Efficient Large-Scale Deep Learning Training with Cache Coherent Disaggregated Memory Systems
Anaheim: Architecture and Algorithms for Processing Fully Homomorphic Encryption in Memory
Domain-Specialized Cache Management for Graph Analytics
Efficient data streaming with on-chip accelerators: Opportunities and challenges
Multitasking and Multithreading on a Multiprocessor with Virtual Shared Memory
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing
Hardware/software techniques for DRAM thermal management
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
Checked Load: Architectural support for JavaScript type-checking on mobile processors
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Regional congestion awareness for load balance in networks-on-chip
HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness
Blueshift: Designing processors for timing speculation from the ground up
QuickIA: Exploring heterogeneous architectures on real prototypes
Supporting superpages in non-contiguous physical memory
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control
Dynamic management of TurboMode in modern multi-core chips
Analyzing the Energy (Dis-) Proportionality of Scalable Interconnection Networks
NvWa: Enhancing Sequence Alignment Accelerator Throughput via Hardware Scheduling
HATT: Hamiltonian Adaptive Ternary Tree for Optimizing Fermion-to-Qubit Mapping
Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures
ScalCore: Designing a core for voltage scalability
Exploiting thermal energy storage to reduce data center capital and operating expenses
Cooperative Warp Execution in Tensor Core for RISC-V GPGPU
Implications of high energy proportional servers on cluster-wide energy proportionality
Concurrent and consistent virtual machine introspection with hardware transactional memory
Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices
RECAP: A region-based cure for the common cold (cache)
Dynamic Data Dependence Tracking and its Application to Branch Prediction
Ascend: a Scalable and Unified Architecture for Ubiquitous Deep Neural Network Computing : Industry Track Paper
Co-Scheduling Hardware and Software Pipelines
Limits to the Performance of Software Shared Memory: A Layered Approach
The Architectural Implications of Facebook's DNN-Based Personalized Recommendation
MORSE: Multi-objective reconfigurable self-optimizing memory scheduler
Accelerating write by exploiting PCM asymmetries
Sprinkler: Maximizing resource utilization in many-chip solid state disks
Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs
Bit-slice Architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation
Tuning Garbage Collection in an Embedded Java Environment
Worm-Bubble Flow Control
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters
Mitigating Write Disturbance in Non-Volatile Memory via Coupling Machine Learning with Out-of-Place Updates
Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System
Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory Encryption
PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM
Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies
Reliability Evaluation of Mixed-Precision Architectures
Network within a network approach to create a scalable high-radix router microarchitecture
On the Limits of Leakage Power Reduction in Caches
Chip-multiprocessing and beyond
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Logical/Physical Topology-Aware Collective Communication in Deep Learning Training
Ant architecture: an architecture for CS1
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks
Distributed Path Reservation Algorithms for Multiplexed All-Optical Interconnection Networks
Thoth: Bridging the Gap Between Persistently Secure Memories and Memory Interfaces of Emerging NVMs
21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015
E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping
Towards a Communication Characterization Methodology for Parallel Applications
Improving the Efficiency of Future Exascale Systems with rCUDA
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches
A Storage-Effective BTB Organization for Servers
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration
The Minimax Cache: An Energy-Efficient Framework for Media Processors
LightPool: A NVMe-oF-based High-performance and Lightweight Storage Pool Architecture for Cloud-Native Distributed Database
Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors
Boomerang: A Metadata-Free Architecture for Control Flow Delivery
QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds
VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Fundamental performance constraints in horizontal fusion of in-order cores
Treegion Scheduling for Wide Issue Processors
Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures
Runtime validation of memory ordering using constraint graph checking
LiveSim: Going live with microarchitecture simulation
Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems
Instruction Pre-Processing in Trace Processors
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003
LiteTM: Reducing transactional state overhead
Application-to-core mapping policies to reduce memory system interference in multi-core systems
The State of State
TNPU: Supporting Trusted Execution with Tree-less Integrity Protection for Neural Processing Unit
Reevaluating Online Superpage Promotion with Hardware Support
BeBoP: A cost effective predictor infrastructure for superscalar value prediction
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading
Resilient Low Voltage Accelerators for High Energy Efficiency
Layout-conscious random topologies for HPC off-chip interconnects
HyQSAT: A Hybrid Approach for 3-SAT Problems by Integrating Quantum Annealer with CDCL
Not All SWAPs Have the Same Cost: A Case for Optimization-Aware Qubit Routing
Design and implementation of a mobile storage leveraging the DRAM interface
The Imitation Game: Leveraging CopyCats for Robust Native Gate Selection in NISQ Programs
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis
DeACT: Architecture-Aware Virtual Memory Support for Fabric Attached Memory Systems
SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
Modeling Virtual Channel Flow Control in Hypercubes
SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support
Concurrent Direct Network Access for Virtual Machine Monitors
Parallel Time Batching: Systolic-Array Acceleration of Sparse Spiking Neural Computation
RELIEF: Relieving Memory Pressure In SoCs Via Data Movement-Aware Accelerator Scheduling
Locality-aware data replication in the Last-Level Cache
Non-Consistent Dual Register Files to Reduce Register Pressure
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator
LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding
uSystolic: Byte-Crawling Unary Systolic Array
Silo: Speculative Hardware Logging for Atomic Durability in Persistent Memory
Cost effective data center servers
Reducing Code Size with Run-Time Decompression
McVerSi: A test generation framework for fast memory consistency verification in simulation
Plutus: Bandwidth-Efficient Memory Security for GPUs
FREE-p: Protecting non-volatile memory against both hard and soft errors
Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks
Stash directory: A scalable directory for many-core coherence
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency
QEI: Query Acceleration Can be Generic and Efficient in the Cloud
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures
Scalably verifiable dynamic power management
Operating system support for overlapping-ISA heterogeneous multi-core architectures
Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells
Ultra-Elastic CGRAs for Irregular Loop Specialization
Power and Energy Characterization of an Open Source 25-Core Manycore Processor
Lincoln: Real-Time 50~100B LLM Inference on Consumer Devices with LPDDR-Interfaced, Compute-Enabled Flash Memory
U-Cache: A Cost-Effective Solution to the Synonym Problem
Architecting Waferscale Processors - A GPU Case Study
BRIM: Bistable Resistively-Coupled Ising Machine
Fast Decentralized Power Capping for Server Clusters
Lightening-Transformer: A Dynamically-Operated Optically-Interconnected Photonic Transformer Accelerator
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols
A Quantum Computer Trusted Execution Environment
Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators
Scalable architectural support for trusted software
Enabling Effective Module-Oblivious Power Gating for Embedded Processors
A decoupled KILO-instruction processor
EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors
Cuckoo directory: A scalable directory for many-core systems
A New Fault-Tolerant Routing Methodology for KNS Topologies
Data Motion Acceleration: Chaining Cross-Domain Multi Accelerators
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
Representative Traces for Processor Models with Infinite Cache
SnackNoC: Processing in the Communication Layer
Improving CC-NUMA Performance Using Instruction-Based Prediction
Power Efficient Processor Architecture and The Cell Processor
Prediction-based superpage-friendly TLB designs
BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap
MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs
Enhancing Large-Scale AI Training Efficiency: The C4 Solution for Real-Time Anomaly Detection and Communication Optimization
Power shifting in Thrifty Interconnection Network
Industrial Perspectives: System IO Network Evolution - Closing Requirement Gaps
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
An Evaluation of Fine-Grain Producer-Initiated Communication in Cache-Coherent Multiprocessors
Efficient Load Value Prediction Using Multiple Predictors and Filters
LUTein: Dense-Sparse Bit-Slice Architecture With Radix-4 LUT-Based Slice-Tensor Processing Units
Network congestion avoidance through Speculative Reservation
Streamline Ring ORAM Accesses through Spatial and Temporal Optimization
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches
Post0-VR: Enabling Universal Realistic Rendering for Modern VR via Exploiting Architectural Similarity and Data Sharing
Exploring high-performance and energy proportional interface for phase change memory systems
Analyzing and Leveraging Decoupled L1 Caches in GPUs
Register Organization for Media Processing
HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
Balancing reliability, cost, and performance tradeoffs with FreeFault
Speculative Data-Driven Multithreading
Creating a Wider Bus Using Caching Techniques
Modeling and Managing Thermal Profiles of Rack-mounted Servers with ThermoStat
SecNDP: Secure Near-Data Processing with Untrusted Memory
Advances of the Counterflow Pipeline Microarchitecture
TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
Cambricon-DG: An Accelerator for Redundant-Free Dynamic Graph Neural Networks Based on Nonlinear Isolation
Adaptive Security Support for Heterogeneous Memory on GPUs
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches
Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth
ASADI: Accelerating Sparse Attention Using Diagonal-based In-Situ Computing
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
Evaluating MapReduce for Multi-core and Multiprocessor Systems
Bandwidth Adaptive Snooping
AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing
CMP design space exploration subject to physical constraints
A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets
A Novel Register Renaming Technique for Out-of-Order Processors
Simulation Study of Cached RAID5 Designs
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation
CDTT: Compiler-generated data-triggered threads
Systematic Approaches for Precise and Approximate Quantum State Runtime Assertion
HIRAC: A Hierarchical Accelerator with Sorting-based Packing for SpGEMMs in DNN Applications
Common Counters: Compressed Encryption Counters for Secure GPU Memory
Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores
LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
START: Scalable Tracking for any Rowhammer Threshold
Data Cache Prefetching Using a Global History Buffer
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
Bloom Filter Guided Transaction Scheduling
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications