yusuke1997/dblp-id-title huggingface dataset:
Incremental Circuit Simulation Analysis for Design Modification and Verification
Field driven STT-MRAM cell for reduced switching latency and energy
Increasing the power efficiency of Bloom filters for network string matching
Current-sensing completion detection method for standard cell based digital system design
A Fast Charging System based on Charging Current Dynamic Adjustment Method
Cost efficient mains powered supply concepts for wireless sensor nodes
Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC
Floating-gate EEPROM cell model based on MOS model 9
Synthesis based introduction to opamps and phase locked loops
Fully-distributed finite-time consensus of second-order multi-agent systems on a directed network
CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis
A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver
Early detection of all-zero block in H.264 with new rate-quantization models
Unequal authenticity protection (UAP) for rate-distortion-optimized secure streaming of multimedia over wireless networks
Dynamically-Wiresized Elmore-Based Routing Constructions
EDLICS: A New Relaxation-Based Electrical Circuit Simulation Technique
Heuristic algorithms for the marking construction problem of Petri nets
Suppression of overflow limit cycles in LDI allpass/lattice filters
A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC
Simulation of TaOx-based complementary resistive switches by a physics-based memristive model
TV energy management by camera-based viewer monitoring
Development of protein chips based on self-assembled monolayer and protein A
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
A 4.1 kb/s hybrid speech coder
A linearized 2-GHz SiGe low noise amplifier for direct conversion receiver
VLSI architecture exploration for sliding-window Log-MAP decoders
A simple and accurate method to predict offset voltage in dynamic comparators
On Fully Differential Incremental ΔΣ ADC with Initial Feedback Zeroing and 1.5-Bit Feedback
A New Compressed Sensing Based Terminal-to-Cloud Video Transmission System
Signed power-of-two allocation scheme for the design of lattice orthogonal filter banks
Vector delta-sigma modulation with integral shaping of hardware-mismatch errors
Viewpoint switching in multiview video streaming
A Hybrid Adaptive Scheme based on Selective Gaussian Modeling for Real-time Object Detection
Design of a reduced KII set and network in analog VLSI
An ECG-on-chip with joint QRS detection & data compression for wearable sensors
Novel high performance single amplifier biquads [voltage mode filters]
Reconfigurable Intelligent Surfaces: Field Trial Campaign for Performance Evaluation from Near-to Far-Field Regions
A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor
The Italian proposal for a new Divertor Test Tokamak (DTT)
Machine Learning and Genetic Programming-based behavioral modeling approaches of Li-ion Batteries
Energy circulation quadrature LC-VCO
Energy-efficient power trimming for reliable nanophotonic NoC microring resonators
Low voltage-drop bypass switch for photovoltaic applications
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis
Area-sharing cyclic structure MRF cirucits design in ultra-low supply voltage
Parasitic and mismatch modeling for optimal stack generation [in CMOS]
Analytic modeling of memristor variability for robust memristor systems designs
On randomization of digital delta-sigma modulators with DC inputs
Extending the CNN paradigm to approximate chaotic systems with multivariable nonlinearities
Exploring reusable frame buffer data for MPEG-4 video decoding
A non-invasive material sensing system and its integrated interface circuits
Efficient and accurate modeling of power supply noise on distributed on-chip power networks
Wire-speed traffic management in Ethernet switches
VLSI implementation of a shift-enabled reconfigurable array
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device
Improved Stability and Performance from Sigma-Delta Modulators Using 1-bit Vector Quantization
A novel synapses circuit and its application to a neural-based A/D converter
Parameter space depiction of stability limits in the presence of singularities
Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters
Scheduling design for distributed video-on-demand servers
Compensation for clock skew in voice over packet networks by speech interpolation
Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS
A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications
A Mismatch Calibrated Bipolar Spatial Contrast AER Retina with Adjustable Contrast Threshold
A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS
Sensorless variable structure speed control of an induction motor
Unipolar ECG circuits: Towards more precise cardiac event identification
Power line communication front-ends based on ADSL technology
A novel pilot structure for the downlink transmission of cyclic prefix assisted single carrier CDMA system with frequency domain equalisation
Sigma delta ADC with a dynamic reference for accurate temperature and voltage sensing
A retiming-based test pattern generator design for built-in self test of data path architectures
Comparison of Haar wavelet-based and Poisson-based numerical integration techniques
Design methodology for global resonant H-tree clock distribution networks
SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)
A tunable, robust pseudo-resistor with enhanced linearity for scanning ion-conductance microscopy
Realization of processing blocks of CNN based CASA system on CPU and FPGA
A Square Root Merit Function for Canonical Correlation Analysis
A first lab in filter design: Power line hum suppression in an ECG signal
A 650-uW 30-Mbps Galvanic Coupling Communication Receiver for Bionic Arms
Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design
A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations
Hard Thresholding based Stochastic Robust Algorithm for Multiple Measurement Vectors
Automatic video annotation based on co-adaptation and label correction
Live Demonstration: 4K100p HEVC Intra Encoder
A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$
Evaluation of a distributed fault handler method for MPSoC
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter
Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter
A calibration technique for SAR analog-to-digital converter based on INL testing with quantization bits and redundant bit
A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter
A new edge detection algorithm: Fast and localizing to a single pixel
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations
Fast Packet Classification using RISC-V and HyperSplit Acceleration on FPGA
Quantization error calculation of various realizations of 2-D separable-in-denominator recursive filters
A new motor-neuron circuit implementation
An adjustable CMOS floating resistor
Motion compensation for block-based lossless video coding using lattice-based binning
MMSE-QR factorization systolic array design for applications in MIMO signal detections
Realization of variable band-pass/band-stop IIR digital filters using Gramian-preserving frequency transformation
Time Precision Comparison of Digitally Controlled Delay Elements
Twin-Chaos - Simultaneous Asynchronous Oscillations of Chaos
Dual Task Learning: A Semi-Supervised Approach to Medical Image Joint Segmentation and Registration
Recursive independent component analysis for online blind source separation
FPGA implementation of the MIMO-OFDM physical layer using single FFT multiplexing
Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder
Routing algorithms on wireless multihop networks and their modifications
A framework for real time gesture recognition for interactive mobile robots
Design and Application of a Novel Readout ASIC for SiPM Array
Design automation of single-ended LNAs using symbolic analysis
Power-aware design with various low-power algorithms for an H.264/AVC encoder
Tone Supression in General Double-Loop Sigma-Delta Modulators using Chaos
An FPGA Implementation of Convolutional Spiking Neural Networks for Radioisotope Identification
Sampling clock jitter estimation and compensation in ADC circuits
Spin Wave Based Full Adder
Error-resilient transcoding using adaptive intra refresh for video streaming
A Subthreshold Voltage Reference with Coarse- Fine Voltage Trimming
Design target exploration for meeting time-to-market using pareto analysis
Multi-stage 20 Gbaud driver in 130 nm CMOS for segmented Mach-Zehnder optical modulators
A Photo-Luminescence Modulator with Improved Linearity for Solar Cell-Based Optical Communications
Estimation of Channel Delay in Analog-to-Information Converters
Edge of Chaos Induces a Hopf Bifurcation in a Bio-Inspired Thermally-Activated Memristor Oscillator
A switched delay line based optical switch architecture with a bypass line
Analog Test Bus Structure for Wide-Bandwidth High-Frequency Measurements
A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing
A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter
Placement and routing optimization for circuits derived from BDDs
A bandwidth-efficient embedded compression algorithm using two-level rate control scheme for video coding system
A Novel Loop Gain Adaptation Method for Digital CDRs Based on the Cross-Correlation Function
A Fully Integrated Inductorless Low Noise Amplifier with 1dB-Step Programmable Gain for FM Radio Receiver Front-End
Noise Decomposition Based on VGG and LSTM Networks
Efficient design of sparse FIR filters in WLS sense
Process variations aware robust on-chip bus architecture synthesis for MPSoCs
High-Throughput Polynomial Multiplier Architecture for Lattice-Based Cryptography
Constrained Image Representation Using Multi-Transforms
A highly efficient method for extracting FSMs from flattened gate-level netlist
Gain enhanced high frequency OTA with on-chip tuned negative conductance load
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
A Miniaturized Flexible Functional Near-infrared Spectroscopy System for Obstructive Sleep Apnea Detection
Optimizing a Multispectral-Images-Based DL Model, Through Feature Selection, Pruning and Quantization
BiFeO3 memristor-based encryption of medical data
Interactive interface of realtime 3D sound movement for embedded applications
Operational Amplifier Sharing Based High-Pass Sigma-Delta Modulator with Programmable Feedforward Coefficients for ECG Signal Acquisition
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem
Asymmetric Neural Image Compression with High-Preserving Information
Hopf-Type Intermediate-Scale Bifurcation in Single-Stage Power-Factor-Correction Power Supplies
Design of class E backlight module incorporating piezoelectric transformer
A Unitary ESPRIT algorithm for carrier frequency offset estimation
Bounds on Noise in Integrated Active-RC and MOSFET-C Filters
Low-Complexity Parallel Cyclic Redundancy Check
An adaptive mesh refinement strategy of substrate modeling for smart power ICs
Efficient Kernels for Real-Time Position Decoding from In Vivo Calcium Images
A Spectral Approach for Studying Spatio-Temporal Chaos
On deployment of overlay network for live video streaming
A 7-MHz process, temperature and supply compensated clock oscillator in 0.25µm CMOS
Some properties of generalized 2-D mirror image and anti mirror image polynomials
A 336fsrms 0.89mW 200MS/s 5MHz Bandwidth 2-2 MASH ΔΣ Time-to-Digital Converter with Differential Time-Mode Arithmetic Units
Design of MUX, XOR and D-latch SCL gates
Non-smooth continuation of periodic orbits in a chaotic buck converter
High-quality view synthesis algorithm and architecture for 2D to 3D conversion
Minimum Power Point Design of Inverter Based Continuous Time Linear Equalizer (CTLE)
A 32×32 ISFET Array with In-Pixel Digitisation and Column-Wise TDC for Ultra-Fast Chemical Sensing
Distributed filter design on silicon CMOS
Chopping in continuous-time sigma-delta modulators
Characterization of 1/f noise vs. number of gate stripes in MOS transistors
Parametric compact models by directional moment matching
Background stabilization and debris flagging in launch pad videos
Versatile smart hip implant technology using 3D metal printing
A neural network model for nonlinear predicitve coding in Fock space
A mixed-signal behavioral level implementation of 1000BASE-X physical layer for gigabit Ethernet
A heuristic algorithm for reducing system-level test vectors with high branch coverage
ISECAD: an iterative simulation-equation-based opamp-design CAD tool
A compensation-based optimization methodology for gain-boosted opamp
A gain-enhancing technique for very low-voltage amplifiers
Design of Optimal Linear-Phase Transmitter and Receiver Filters for Digital Systems
A New Class-based Early Termination Method for Fast Motion Estimation in Video Coding
Space-time block coding for wireless ad hoc networks
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells
A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range
Compensation of Excess Loop Delay in Continuous-Time Incremental ∆Σ ADCs
Dynamic sawtooth compensation (DSC) technique with self-tuning mode selection (SMS) for current-mode Buck-Boost converter
Towards detection and control of Hopf bifurcation in electric power system
A high performance floating-point special function unit using constrained piecewise quadratic approximation
Color Image Enhancement Based on Single-Scale Retinex With a JND-Based Nonlinear Filter
Hybrid incremental-ΣΔ-ADC for ambient light sensing applications
Efficient approaches to improving performance of VLSI SOVA-based turbo decoders
Smart RFID Label for Monitoring the Preservation Conditions of Food
On control of networks of dynamical systems
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB
A Chopper Interface Circuit for Thermopile-Based Thermal Sensors
Motion estimation using on-line arithmetic
A 1.8V-0.18µm CMOS lock-in amplifier for portable applications
Silicon neurons that phase-lock
MAGNet: A Convolutional Neural Network with Multi-Scale and Global Attention Modules for Medical Image Segmentation
Modified Joint Channel-and-Data Estimation for One-Bit Massive MIMO
Audio Sigma-Delta-Modulator Implementaion using Class AB Compact Switched Current Memory Cells
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors
VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition
Enhancing pinning controllability of complex networks of coupled maps
Low-Complexity Encryption Using Redundant Bits and Adaptive Frequency Rates in RFID
A current-mode chaotic oscillator
Automatic generation of functional coverage models
A 1.57mW 99dBΩ CMOS transimpedance amplifier for VHF micromechanical reference oscillators
A new window for the design of cosine-modulated multirate systems
Sub-Sampling Framework of Distributed Video Coding
An embedded probabilistic extraction unit for on-chip jitter measurements
A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage
The Application of Redundant Number Systems to Digital Sigma-Delta Modulators
A new robust handshake for asymmetric asynchronous micro-pipelines
A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier
A near-lossless data hiding method with an improved quantizer
Power-Up Delay for Retiming Digital Circuits
Design and performance considerations for an on-chip jitter analysis system
Macromodel Simplification Using Dimensional Analysis
A novel CMOS logic style with data independent power consumption
Mitigation of Camouflaged Adversarial Attacks in Autonomous Vehicles-A Case Study Using CARLA Simulator
Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters
Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders
JPEG-compliant image coding with adaptive pre-/post-filtering
Chaos in Josephson junction circuits with voltage-dependent supercurrent
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis
Dynamic Gradient Sparse Update for Edge Training
A novel DC-offset cancelling circuit for DCR
Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologies
A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch
A memory addressing and access design for real time volume rendering
Error resilient scalability for video bit-stream over heterogeneous packet loss networks
A low-leakage parallel CRC generator for ultra-low power applications
Integrate and fire circuit as an ADC replacement
An interconnect-driven design of a DFT processor
Beyond Arduino: A Guide for the Perplexed
An Event-Based Line Sensor with Configurable Antagonistic Center Surround
Signal detection based on pattern classification for use in wireless CPFSK receivers
Full calibration digital techniques for pipeline ADCs
A spiking-neuron collective analog adder with scalable precision
Efficient Hardware Implementation of the Hyperbolic Tangent Sigmoid Function
Adaptive exposure control and real-time image fusion for surveillance systems
Power minimization of a 433-MHz LC VCO for an implantable neural recording system
Practical Static Output Feedback Control Methods for Constrained Piecewise Affine Systems: An Application in Vehicle Suspension Control
CMOS luminescence lifetime sensor for white LED multi-spectral characterization
Saturation RRAM Leveraging Bit-Level Sparsity Resulting from Term Quantization
Unified Accelerator for Attention and Convolution in Inference Based on FPGA
GPU-enabled parallel processing for image halftoning applications
Band-selective estimation for IQ-imbalance and carrier frequency offset in OFDM systems
Efficient all-zero block detection algorithm for H.264 integer transform
Ultra-low-power high sensitivity spike detectors based on modified nonlinear energy operator
A Background DAC Error Estimation in Sigma-Delta ADCs using a Pseudo Random Noise based Correlation Technique
Limit Cycles and Asymptotic Stability of Delta-Operator Formulated Discrete-Time Systems in Fixed-Point Arithmetic
On the utilization of strength-reduced architectures for adaptive equalizers
Latency and Cost-aware Resource Provisioning in Fog Computing: An Auction Theory-based Approach
CMOS Compatible Color Photodiode for LOC Applications
Common mode control loop for current mode logic-based circuits in FD-SOI technology
Quality perception in 3D interactive environments
A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications
Circuit Partitioning for Multi-Core Quantum Architectures with Deep Reinforcement Learning
Graph-Based Descriptor Learning for Non-Rigid 3D Shapes
Low-Cost 2-D Map Generation System for a Mobile Robot
Dynamically coupled multi-layer mixed-mode CNN
An Inference Hardware Accelerator for EEG-Based Emotion Detection
High bandwidth transimpedance amplifier design using active transmission lines
Visual cryptography for print and scan applications
Memory-efficient scalable video encoder architecture for multi-source digital home environment
Continuous time delta sigma modulators with reduced clock jitter sensitivity
New results in multidimensional linear phase filter bank design
A low-power high driving ability voltage control oscillator used in PLL
Wearable Device for Real-time Assessment of Facing Time in Small Group Social Interactions
Bandwidth and Local Memory Reduction of Video Encoders using Bit Plane Partitioning Memory Management
On the Performance of Augmented Signature Testing
A 30fJ/b Current-Biased Inverter Based RO TRNG with High Temperature and Supply Voltage Stabilities
Implementation of the MFCC front-end for low-cost speech recognition systems
Generalized Shifting-Based PAPR Reduction Architecture for Discrete Multitone Systems
Advancing Image Classification with Phase-coded Ultra-Efficient Spiking Neural Networks
An interleaver implementation for the serially concatenated pulse-position modulation decoder
Analyzing and Enhancing the Reliability of Vision Transformer Models Against Soft Errors
Exploiting memristance for low-energy neuromorphic computing hardware
A current-mode Σ△ modulator with FIR feedback and DC servo loop for an improved dynamic range
Complexity scalable MPEG-2 to WMV transcoder with adaptive error compensation
Deep Learning for Logic Optimization Algorithms
Fast H.264/AVC to HEVC transcoder based on data mining and decision trees
Rigorous study of short periodic orbits for the Lorenz system
Transparency-based hierarchical test generation for modular RTL designs
Event-Based Resilient Consensus of Second-Order Multi-Agent Systems Under Dos Attacks
Live demonstration: Characterization of RRAM crossbar arrays at a click of a button
Asympototic stability of two-dimensional digital filters with overflow nonlinearities
Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators
CMOS operational amplifiers with continuous-time capacitive common mode feedback
SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs
Robust image watermarking on the DCT domain
Neuron architecture based on jamming avoidance response of an electric fish
An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS
A Novel Deep-Learning Method for Obstructive Sleep Apnea Detection from Single Channel Photoplethysmography
A High Throughput H-QC LDPC Decoder
CompoundEye: A 0.24-4.17 TOPS Scalable Multi-Node DNN Processor for Image Recognition
New IIR Digital Filter Realizations Using Residue-Feedback
Low-power state assignment techniques for finite state machines
A High Efficiency, Low EMI Non-inverting Buck-Boost Converter in Wireless Power and Data Transfer System for Brain Computer Interface
Programmable switched-current floating-gate cells
Low noise, high linearity double-balanced active mixers using lossless feedback
Bifurcation analysis of a second-order impact model for forest fire prediction through a 1D-map
High-order cascade multibit ΣΔ modulators for xDSL applications
An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors
Fast Host Service Interface Design for Embedded Java Application Processor
VPU-CIM: A 130nm, 33.98 TOPS/W RRAM based Compute-In-Memory Vector Co-Processor
Solution of vector partial differential equations by transfer function models
A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications
ADCs, Chaos and TRNGs: a Generalized View Exploiting Markov Chain Lumpability Properties
Short-circuit Power Dissipation Formulae for CMOS Gates
Modeling of self-adaptive systems with SCADE
A low-voltage CMOS low-dropout regulator with enhanced loop response
A Method for Selecting the Wiring Direction from Terminals using a Planar Graph Drawing Method
A predictive updating scheme to improve the NLMS algorithm for acoustic echo cancellation
Solar energy harvesting with light emitting diodes
Independent component analysis of digital image watermarking
A 6T-4C shadow memory using plate line and word line boosting
A parallel architecture for estimating 4th-order cumulants
On equalization of channels with ZP precoders
Self-learning-based rain streak removal for image/video