yusuke1997/dblp-id-title huggingface dataset:
A closed form solution to L 2 -sensitivity minimization of second-order state-space digital filters
Stochastic delay differential equation and its application on communications
A CAD environment for fuzzy systems HW/SW mapping
Ultrasound energy harvesting system for deep implanted-medical-devices (IMDs)
A flexible design of a decision feedback equalizer and a novel CCK technique for wireless LAN systems
Design of a dB-Linear 21.5-to-36 GHz 6-bit RF-VGA with Accurate Gain Control in 0.13-μm SiGe BiCMOS Technology
AFT-CIM: An Energy Efficient ADC-Free Transpose Computing-in-Memory Macro for MAC Operations
Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock
Document image binarization via optimized hybrid thresholding
Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers
A low-power dynamic comparator with time-domain bulk-driven offset cancellation
A nearest neighbor graph based watershed algorithm
An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models
An efficient texture cache for programmable vertex shaders
Deep Sparse Depth Completion Using Joint Depth and Normal Estimation
MuBiNN: Multi-Level Binarized Recurrent Neural Network for EEG Signal Classification
Grouped Transform for Ultra-Low-Complexity Learned Image Compression
A digital dynamic power monitor based adaptive clocking system for voltage droop mitigation in 5nm mobile application processor
Real-time streaming for the animation of talking faces in multiuser environments
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications
Fast Transient Simulation of Lossy Transmission Lines
Radix-based digital correction technique for two-capacitor DACs
38 GHz low-power static frequency divider in SiGe bipolar technology
Low-complexity turbo product code for high-speed fiber-optic systems based on expurgated BCH codes
ReRAM-Based Process-In-Memory Accelerator for Iterative Solvers: A Systematic Survey
A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks
A calibration-free low-power supply-pushing reduction circuit (SPRC) for LC VCOs
Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs
Spatio-temporal distribution of brain electrical activity patterns in epilepsy: inputs for cellular neural networks
A CNN approach to computing arbitrary Boolean functions
Pulsed OFDM modulation for ultra wideband communications
Spiking Neurons: A New Entropy Source for Physically Unclonable Functions
An HMM-based eye movement detection system using EEG brain-computer interface
iSPAZ: An Improved Switched-Capacitor Ping-Pong Voltage Generator with Auto-Zero for Ultra-Low-Power Internet of Everything Systems
A Fully Memristive Spiking Neural Network with Unsupervised Learning
Power Harvesting With PZT Ceramics
High speed VLSI architecture design for block turbo decoder
3-D direction aligned wavelet transform for scalable video coding
VHF Highly Linear Fully-balanced CMOS OTA
Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction
Extending 2D Saliency Models for Head Movement Prediction in 360-Degree Images using CNN-Based Fusion
Bifurcation analysis of a circuit-related piecewise-affine map
High CMRR power efficient neural recording amplifier architecture
Dark current and noise of 100nm thick silicon on sapphire CMOS lateral PIN photodiodes
A 1.8 V 10-bit 80 MS/s low power track-and-hold circuit in a 0.18µm CMOS process
Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs
A Highly Precise Analog Subtractor with Background Calibration Technique
Fast-settling CMOS operational amplifiers with negative conductance voltage gain enhancement
An efficient method to compute phase-noise in injection-locked frequency dividers
Lossless image compression based on a fuzzy-clustered prediction
New improved CMOS class AB buffers based on differential flipped voltage followers
Hierarchical Coding for Talking-Head Video
An overview of directional transforms in image coding
A crosscorrelation predistorter using memory polynomials
A Ka- to W-Band Tightly Coupled Array Antenna-in-Package Using Glass IPD for Ultrawideband mmWave Wireless Communication
Distributing Deep Neural Networks for Maximising Computing Capabilities and Power Efficiency in Swarm
Spatially supervised recurrent convolutional neural networks for visual object tracking
A MD FFT Algorithm for Symmetric Signals
A new level sensitive D Latch using Ballistic nanodevices
Vector median-rational hybrid filters for multichannel image processing
Class-Specific Neural Network for Video Compressed Sensing
An improved multiple access scheme for chaos-based digital communications using adaptive receivers
CC/CV ZVS WPT system without any feedback from receiver to transmitter
Two-Layer MPEG Video Coding Algorithm for ATM Networks
Photon counting and direct ToF camera prototype based on CMOS SPADs
Adaptive envelope-constrained filter design
Minty's coloured branch theorem versus Tellegen's theorem
Scheduling tests for low power built-in self-test
Real-time sepsis prediction using fusion of on-chip analog classifier and electronic medical record
Design and integration of a remotely programmable dental monitoring device
Extinction and intermittency of the chaotic attractor in phase-locked loop equation with periodic external forcing term
Ultra-low voltage VLSI: are we there yet?
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's
Reservoir Computing with VCO-Based Spiking Neurons for Regression and Classification
Self-adaptive quasi-Gaussian circuits for analog on-chip-trainable multi-class classifiers
A low power scheduling scheme with resources operating at multiple voltages
Functionalized ImmunoFET for Detection of Phosphatidyl-L-serine
A 1.8 μW 32 nV/√Hz current-reuse capacitively-coupled instrumentation amplifier for EEG detection
Random error analysis and reduction for stochastic computation based on autocorrelation sequence
Cost-Effectiveness Analysis of Structural Robustness in Complex Networks
Sequential Detection Using a New Recursive-Averaging Cumulant Estimation Method
A reconfigurable inverse transform architecture design for HEVC decoder
Layout Optimization Using Arbitrarily High Degree Posynomial Models
Increase in delay uncertainty by performance optimization
Efficient error detection architectures for CORDIC through recomputing with encoded operands
Algorithmic optimization of H.264/AVC encoder
A gate-level strategy to design Carry Select Adders
An information-theoretic approach to study activity driven networks
Photovoltaic inverters with Perturb&Observe MPPT technique and one-cycle control
Edge Computing-based Adaptive Machine Learning Model for Dynamic IoT Environment
Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier
Scaled Lifting Scheme and Generalized Reversible Integer Transform
Continuous and Discrete Time Low Voltage Analog Circuits in 16 nm CMOS Technology
MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion
Live demonstration: Prosthesis grip force modulation using neuromorphic tactile sensing
Power optimized LC VCO and mixer co-design
A low power multi-mode CMOS image sensor with integrated on-chip motion detection
A low-power bioamplifier with a new active DC rejection scheme
"Green" micro-architecture and circuit co-design for ternary content addressable memory
An extended generalized sidelobe canceller in time and frequency domain
Fundamental Aspects of Large Switched-Capacitor Networks
Extracting underlying trend and predicting power usage via joint SSA and sparse binary programming
Integrating Ultra-thin SiGe BiCMOS Power Amplifier Chip in Combination with Flexible Antenna in the Polymer Foil
A Hardware-Software Co-Design Platform to Evaluate SNN Workloads for ReRAM-based IMC
The best basis problem, compaction problem and PCFB design problems [filter banks]
Combined linear-decision feedback sequence estimation: an improved system design
Drive voltage optimization controller to improve efficiency
A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS
H.264-to-AV1 Video Transcoding Acceleration Based on Lightweight Machine Learning
Ali266: an optimized VVC Software Encoder Implementation Towards Real-time Applications
On the Double Biliniear Transformation and Nonessential Singularities of the Second Kind at Infinity
A High-Precision Sub-10 nV/√Hz Variable Gain Chopper Amplifier for Phase Current Sensing in Adaptive High-Efficiency DC/DC Converters
Frequency and Q tuning techniques for continuous-time bandpass sigma-delta modulator
A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator
A Hybrid Coding Method for Digital HDTV Signals
Enabling Mycelium-Inspired Reservoir Computing with Memristive Oscillating Cellular Automata
Face hallucination based on independent component analysis
A pipelined A/D converter for high-speed and high-resolution application
Interval Finite-Difference Methods for Digital MOS Circuits Simulation
An efficient pulse mode multilayer neural network
Live Demonstration: A Wearable Device for Optogenetic Vision Restoration
A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL
FPGA-based transmitter-receiver architecture of an overlapped FFH-CDMA system: design and simulation
Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies
An artificial immune system for visual applications with CNN-UM
Design of an inter-plane circuit for clocked PLAs
An Adiabatic Regenerative Capacitive Artificial Neuron
A programmable rail-to-rail constant-g m input structure for LV amplifier
A low-power reduced swing single clock flip-flop
RFID-based positioning for building management systems
A single-FPGA multipath MIMO fading channel simulator
A Fully Differential CMOS Potentiostat
A Respiratory Monitoring System in Surgical Environment Based on Fiducial Markers Tracking
A novel CMOS Bandgap reference circuit with improved high-order temperature compensation
Lossless data hiding: fundamentals, algorithms and applications
Digital Compensated Methodology of a 2-1-1 Cascaded Continuous Time Delta-sigma Modulator
Circuit Implementation of a Nonmonotone Activation Function
Reactive rejuvenation of CMOS logic paths using self-activating voltage domains
A new method of an IF I/Q demodulator for narrowband signals
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis
VLSI Implementation of an Associative Memory Using Temporal Relations
Experimental Testbed for Ultrasonic Wireless Power Transfer and Backscattering Based Localization for Future Implantable Devices
Distortion Compensation of Multi-Mesfet Circuits
A MEMS socket system for high density SoC interconnection
Extensions of ACC Technology Toward Ad Hoc Platooning with Guaranteed String Stability and Improved Tracking Performance
Stability analysis of nonlinear systems via piecewise linear Lyapunov functions
A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array
Stacked Ring Oscillators with Fractional Injection Lock
Linearization of subthreshold low-noise amplifiers
Structural compression and reconstruction of static image by ideal diode retina network
Multiplier-less discrete sinusoidal and lapped transforms using sum-of-powers-of-two (sopot) coefficients
Use of adaptive integer-to-integer wavelet transforms in lossless image coding
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs
Simplified Reed-Muller expressions for residue threshold functions
A low-voltage wide-swing FGMOS current amplifier
Optimally weighted local discriminant bases [signal feature extraction/classification]
The Design of the CMOS Current-Mode General-Purpose Analog Processor
A programmable vision chip with pixel-neighborhood level parallel processing
An Approach to Compensate for Capacitor Mismatches in SAR ADC using Multiple Comparisons
NS-Engine: Near-Sensor Neural Network Engine with SRAM-Based Compute-in-Memory Macro
Simulation of an Analogue Circuit Solving NP-Hard Optimization Problems
Co-scheduling of flexible energy loads in building clusters
A second order hyperstable adaptive filter with no post-error filtering
Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs
A High Speed, Low Energy Comparator Based on Current Recycling Approach
Simulation and modeling of power and ground planes in high speed printed circuit boards
Phase shift keying demodulator with decision feedback phase-locked loop
Fast Peak Detector with Improved Accuracy and Linearity for High-Frequency Waveform Processing
A 4.8dB NF, 3-to-119GHz Distributed LNA With Three-Turn Transformer and Multiple Magnetic Coupling Feedback Network in 28nm CMOS
Multibit incremental data converters with reduced sensitivity to mismatch
A result on global convergence in finite time for nonsmooth neural networks
Effect of Recompression on Attacking JPEG Steganographic Schemes An Experimental Study
Vascular compliance probe with integrated ECG for image-free evaluation of arterial stiffness
Second Order Cone Programming (SOCP) Relaxations for Large Margin HMMs in Speech Recognition
New proportionate affine projection sign algorithms
A multiplier-less 1-D and 2-D fast Fourier transform-like transformation using sum-of-powers-of-two (SOPOT) coefficients
Low-Complexity Wideband Hybrid Precoding for mmWave MIMO-OFDM
Simultaneous deblocking and error concealment for decoded visual signal
Modem floorplanning with abutment and fixed-outline constraints
An efficient denoising chip for the removal of impulse noise
Automated Detection of Diabetic Retinopathy using a Binocular Siamese-Like Convolutional Network
An improved bang-bang phase detector for clock and data recovery applications
Architecture for Multiple Reference Frame Variable Block Size Motion Estimation
A 55-fJ/Comparison Dynamic Current Comparator with Parasitic Charge Recycling Technique
Cycle slipping in nonlinear circuits under periodic nonlinearities and time delays
Live Demo: Affine arithmetic concept based Symbolic Circuit Analyser
A high step-up DC-DC converter using transformer with intrinsic voltage-doubler
A novel equaliser architecture with dynamic length optimisation
Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle
A 0.4V ultra low-power UWB CMOS LNA employing noise cancellation
A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS
An antialiasing filter using complementary MOS transconductors biased in the triode region
Ionoacoustic Dosimetry for FLASH Electron Beams: Design of Sensor Arrays and Reconstruction Algorithms through Computational Simulations
A class of approximate FIR low-pass filters
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology
Performance analysis of transform in uncoded wireless visual communication
Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators
Simulating phase noise induced from cyclostationary noise sources
High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology
Improved design of C 2 PL 3-2 compressors with less transistor count
Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing
A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter
A Gm-C bump equalizer for low-voltage low-power applications
A low power and area efficient FIR filter chip for PRML read channels
Concise representation and cellular structure for universal maximally flat FIR filters
On the Design of Vertical-Turn Solenoids for Magnetically Isolated Densely Integrated LC Oscillators
An accurate phase shift detector using bulk voltage boosting technique for sensing applications
Parallel DSP implementation of wavelet transform in image compression
Enhanced Tower Field Mask Scheme with Affine Transformation-based Dynamic S-box
Design and Characterization of New Content Addressable Memory Cells
Programmable logic gate based on resonant tunnelling devices
Enhancing Compression Rate by Just-noticeable Distortion Model for H.264/AVC
Mutual inductance between intentional inductors: closed form expressions
VLSI design of Reed-Solomon decoder architectures
Fault Tolerance Circuit for AM-OLED
Capabilities and Limitations of Feedforward Neural Networks with Multilevel Neurons
SHeFU: Secure Hardware-Enabled Protocol for Firmware Updates
The application of lattice-reduction to the K-Best algorithm for near-optimal MIMO detection
TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications
Hardware Security Vulnerability in Analog Signal Chain Filters
A novel approach to the design of higher-order Bode-type variable-amplitude wave-digital equalizers
Design of two-channel PR FIR filter banks with low system delay
An Efficient Jacobian Updating Technique for Analog Circuit Optimization
Neural tissue and brain interfacing CMOS devices - An introduction to state-of-the-art, current and future challenges
Self-latching operation limits for MOBILE circuits
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case
A new recursive formulation for 2-D WHT
Efficient differential fault analysis attacks to AES decryption for low cost sensors in IoTs
An output tracking delay-recycled clock skew-compensation and/or duty-cycle-correction circuit
Perfect-Reconstruction Cosine-Modulated Filter Banks via Improved Constraint Linearization
An efficient algorithm for blind separation of multiple independent sources
Wavelet-Based Interpolation Point Selection for Multi-Shifted Arnoldi
Linear Phase Cosine Modulated Maximally Decimated Filter Banks with Perfect Reconstruction
A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages
An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting
CMOS Current-Mode Outstar Neural Networks with Long-Period Analog Ratio Memory
On the energy concentration property for zero-phase sequences
A multi-agent based system for run-time distributed resource management
Blind separation with Gaussian mixture model for convolutively mixed sources
Neural network based on-chip thermal simulator
Weather-based road condition estimation in the era of Internet-of-Vehicles (IoV)
Use of time variant digital sigma-delta for fractional frequency synthesizers
A 670 ps, 64 bit dynamic low-power adder design
Exploiting bit-depth scaling for quality-scalable energy efficient display processing
Robust blind dereverberation of speech signals based on characteristics of short-time speech segments
A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips
Gain bandwidth considerations in fully integrated distributed amplifiers implemented in silicon
On-line IDDQ fault testing for CMOS/BiCMOS logic families
Rate distortion modeling and adaptive rate control scheme for high efficiency video coding (HEVC)
A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications
On the use of the describing function in fuzzy controller design for switching dc-dc regulators
Low-Power Low-Noise Neural Amplifier in 0.18µm FD-SOI Technology
State Equations of Memristor Circuits with Nonlinear Lossless Elements in the Flux-Charge Domain
Blind identification of brain mechanism in MEG
A 442.1 nVpp, 13.07 ppm/°C Ultra-Low Noise Bandgap Reference Circuit in 180 nm BCD Process
A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers
Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility
Cascading failures in scale-free coupled map lattices
Smart Dysphagia Detection System with Adaptive Boosting Analysis of Throat Signals
A low-power current-mode front-end acquisition system for biopotential signal recording
s-Expanded Transfer Function using UaL Decomposition with Convolution & Deconvolution
A resistorless low current reference circuit for implantable devices
A frequency synthesizer using two different delay feedbacks
A limitation on active filter dynamic range
A 15-bit two-step pixel-level ADC for 17μm-pitch low-power and high-dynamic-range IRFPA
On-chip fluorescence detection system with high-density microchamber array based on CMOS image sensor
Digital VLSI OFDM transceiver architecture for wireless SoC design
Application of ACM model to the design of CMOS OTA through a graphical approach
Mirror N PUF: Harvesting Multiple Independent Bits From Each PUF Cell in 65nm
Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem
Logically reversible arithmetic circuit using pass-transistor
A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture
Power Grids in the Midst of Rapidly Increasing Penetration of Power Electronics
A concept inventory for an Electric Circuits course : Rationale and fundamental topics
Record fT, fmax, and GHz amplification in 2dimensional CVD MoS2 embedded gate fets
XVPE-Net: A Novel Methodology for Interpretable Vital Parameter and Cuffless Blood Pressure Estimation from PPG Signal
Multidimensional Similarity Fusion for Speech Quality Assessment
A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder
The use of NNs in MRAC to control nonlinear magnetic levitation system
Adaptive RBF Neural Network in Signal Detection
A wide dynamic range integrating pixel with an improved low light sensitivity
A Dual-Ring Switched-Capacitor DC-DC Converter With Systematic Fractional Conversion Ratios
Learning with prior information
Model Reduction of Linear Interval Systems Using Padé Approximation
High-performance CMOS pseudo-differential amplifier
Hybrid Supervised Deep Learning for Ethnicity Classification using Face Images
Design and implementation of channel equalizers for block transmission systems
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability
Power-Efficient and Small-Area Approximate Multiplier Design with FPGA-Based Compressors
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation
A start-up calibration method for generic current-steering D/A converters with optimal area solution
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming
A new parallel architecture for low power linear feedback shift registers
Lifting based integer wavelet transform with binary coefficients
Optimum Number of Transistors in Stacked CMOS Millimeter-Wave Power Amplifiers
A wideband analog multi-resolution spectrum sensing (MRSS) technique for cognitive radio (CR) systems
Polynomial transform algorithms for multidimensional discrete Hartley transform
Differential nuclear magnetic resonance receiver: Design, implementation and experimental results
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
Partially coherent signal combination for impulse radio synchronisation
Forward error correction codes to reduce intercarrier interference in OFDM
An ultra-low voltage, VCO-based ADC with digital background calibration
Depth-powered Moving-obstacle Segmentation Under Bird-eye-view for Autonomous Driving
A Current-Source Sinusoidal Gate Driver for High-Frequency Applications
A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems
Analog CMOS Implementation of Neural Network for Adaptive Signal Processing
A vMOS Soft-Maximum Current Mirror
Isolation Electromagnetically coupled DC and AC current sensor and detector
A charge based computation system and control strategy for energy harvesting applications
Minimax design of 2-D IIR digital filters using sequential semidefinite programming
Real-Time EEG-Based Affective Computing Using On-Chip Learning Long-Term Recurrent Convolutional Network