yusuke1997/dblp-id-title huggingface dataset:
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below
43rd IEEE VLSI Test Symposium, VTS 2025, Tempe, AZ, USA, April 28-30, 2025
Design of Wireless Sub-Micron Characterization System
An approach to dynamic power consumption current testing of CMOS ICs
A distance reduction approach to design for testability
Reducing test application time in scan design schemes
Circuit-level classification and testability analysis for CMOS faults
Online Millimeter Wave Phased Array Calibration Based on Channel Estimation
Design and analysis of ring oscillator based Design-for-Trust technique
Hot topic session 12A: Split manufacturing - IARPA's TIC program
Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integration
STDF Memory Fail Datalog Standard
Functional verification and simulation of FSM networks
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor
Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations
A Novel Self-referencing Approach Using Memory Power-up States for Detecting COTS SRAMs
A neural inverse function for automatic test pattern generation using strictly digital neural networks
Special Session: Security Verification & Testing for SR-Latch TRNGs
CMOS bridging fault modeling
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices
Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment
Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies
Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation
Post fabrication tuning of GaN based RF power amplifiers for pico-cell applications
Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure
20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA
Faults in data prefetchers: Performance degradation and variability
A Novel Test Methodology for MEMS Magnetic Micromotors
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing
SPIRIT: A Highly Robust Combinational Test Generation Algorithm
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis
Customizing ATPG User-Defined Stresses and Tests To Target Cell-Neighborhood-Bridging Defects
Analyzing the design-for-test techniques in a multiple substrate MCM
Design for Self-Checking and Self-Timed Datapath
ATPG-based cost-effective, secure logic locking
Debating the Future of Burn-In
A portable ATPG tool for parallel and distributed systems
14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA
Effective and Efficient Test Pattern Generation for Small Delay Defect
Introduction to approximate computing
Designing a Testable System on a Chip
On minimizing the number of test points needed to achieve complete robust path delay fault testability
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
Test Metrics for Analog Parametric Faults
Design for diagnosable multiple-output digital systems
Defect Screening Using Independent Component Analysis on I_DDQ
Cache- and register-aware system reliability evaluation based on data lifetime analysis
Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems
An oscillation-based test structure for timing information extraction
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive
Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips
Test time reduction using parallel RF test techniques
Density estimation for analog/RF test problem solving
Jump Scan: A DFT Technique for Low Power Testing
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level
Simulation-Based Test Algorithm Generation for Random Access Memories
Diagnosis Outcome Preview through Learning
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects
Innovative practices session 5C automotive test solutions
Multifault testability of delay-testable circuits
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?
Test Data Compression Using Dictionaries with Fixed-Length Indices
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction
Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
41st IEEE VLSI Test Symposium, VTS 2023, San Diego, CA, USA, April 24-26, 2023
Error Detecting Refreshment for Embedded DRAMs
Cyclic stress tests for full scan circuits
Maximal Diagnosis of Interconnects of Random Access Memories
Weighted random robust path delay testing of synthesized multilevel circuits
A framework for low overhead hardware based runtime control flow error detection and recovery
Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Yield Analysis of Logic Circuits
Test Generation for Ground Bounce in Internal Logic Circuitry
A shared memory based parallel diagnosis system
Testability metrics for synthesis of self-testable designs and effective test plans
Iddt testing of continuous-time filters
Testing of VLSI CMOS System/390 processor at card and system level
A Metric for Assessing the Error Tolerance of Tile Sets for Punctured DNA Self-Assemblies
Partial scan testing with single clock control
A high-level synthesis approach to design of fault-tolerant systems
Test Enabled Process Tuning for Adaptive Baseband OFDM Processor
An organization of the test bus for analog and mixed-signal systems
Extracting effective functional tests from commercial programs
FIFO Topology Aware Stalling for Accelerating Coverage Convergence of Stalling Regressions
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications
Signature analysis and aliasing for sequential circuits
Accelerating capture of infrequent errors on ATE for silicon TV tuners
An Analysis Framework for Transient-Error Tolerance
Path clustering for adaptive test
Innovative practices session 2C: "How is industry simplifying analog test"
Synchronization of large sequential circuits by partial reset
Sequential test generation with reduced test clocks for partial scan designs
An Industrial Case Study of Sticky Path-Delay Faults
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling
A tool for automatic generation of self-checking data paths
Transistor Self-Heating: The Rising Challenge for Semiconductor Testing
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor
Breaking Correlation to Improve Testability
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs
On the (non-)resetability of synchronous sequential circuits
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
Testing combinational iterative logic arrays for realistic faults
A diagnosability metric for parametric path delay faults
SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection
Horizontal-FPN fault coverage improvement in production test of CMOS imagers
Structured scan patterns retargeting for dynamic instruments access
3D self testing with Spidergon STNoC
Innovative practices on challenges, opportunities, and solutions to hardware security
Fault modeling and test algorithm creation strategy for FinFET-based memories
Hardware Trojan attacks in embedded memory
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?
Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions
Measuring the coverage of node shorts by internal access methods
Test method and scheme for low-power validation in modern SOC integrated circuits
RTL Test Point Insertion to Reduce Delay Test Volume
18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada
Implicit test pattern generation constrained to cellular automata embedding
Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory
Generating Complete and Optimal March Tests for Linked Faults in Memories
SLIDER: A fast and accurate defect simulation framework
Current Measurement for Dynamic Idd Test
Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits
Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures
An IEEE 1149.1 based voltmeter/oscilloscope in a chip
RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning
Special session 8C: E.J. McCluskey doctoral thesis award semi-final
11th IEEE VLSI Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993, Atlantic City, NJ, USA
Polynomial Formal Verification of Multipliers
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits
17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories
Recent advances in sequential test generation
Disturb Neighborhood Pattern Sensitive Fault
Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution
Degrading fault model for WSI interconnection lines
Compact testing with intermediate signature analysis
Mixed Signal DFT at GHz Frequencies
Test of phase interpolators in high speed I/Os using a sliding window search
ML-based Adaptive Wafer Sort to Preserve Diagnostic Information
Panel: When will the cost of dependability end innovation in computer design?
Dominance Based Analysis for Large Volume Production Fail Diagnosis
Iterative OPDD Based Signal Probability Calculation
Delay Fault Testing: How Robust are Our Models?
A programmable method for low-power scan shift in SoC integrated circuits
Applying two-pattern tests using scan-mapping
Pulse shrinkage based pre-bond through silicon vias test in 3D IC
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories
NOIDA: Noise-resistant Intra-cell Diagnosis
Thermal issues in test: An overview of the significant aspects and industrial practice
Low Cost Scheme for On-Line Clock Skew Compensation
Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects
Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUs
Outlier Detection for Analog Tests Using Deep Learning Techniques
Self-testing and self-checking combinational circuits with weakly independent outputs
Fault Models and Tests for Two-Port Memories
Effective TARO Pattern Generation
Resynthesis for sequential circuits designed with a specified initial state
Generalization of independent faults for transition faults
Controlling Peak Power During Scan Testing
Structural Software-Based Self-Test of Network-on-Chip
High Speed Ring Generators and Compactors of Test Data
DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain
Scenario-based Test Content Optimization: Scan Test vs. System-Level Test
FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security
New topic session 2B: Why (Re-)Designing Biology is ∗Slightly∗ more challenging than designing electronics
Identification of structured automata for test evaluation
Combining checkpointing and scrubbing in FPGA-based real-time systems
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
Trading off area, yield and performance via hybrid redundancy in multi-core architectures
On Test Data Volume Reduction for Multiple Scan Chain Designs
Concurrent autonomous self-test for uncore components in system-on-chips
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages
Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
Panel: Analog/RF BIST: Are we there yet?
A low cost jitter separation and characterization method
Disturbance-free BIST for loop characterization of DC-DC buck converters
SRAM yield-per-area optimization under spatially-correlated process variation
Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits
Multiple weighted cellular automata
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS
Synthesis of combinational circuits with special fault-handling capabilitie
High-Level Synthesis for Orthogonal Sca
10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA
Non-RF to RF Test Correlation Using Learning Machines: A Case Study
High Quality Robust Tests for Path Delay Faults
A new tool for random testability evaluation using simulation and formal proof
Non-Masking Non-Robust Tests for Path Delay Faults
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation
Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits
TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test
Generalized Sensitization using Fault Tuples
Special session 11B: Hot topic on-chip clocking - Industrial trends
Flip-flop clustering based trace signal selection for post-silicon debug
Alternative "safe" test of hysteretic power converters
A General Failure Candidate Ranking Framework for Silicon Debug
Analysis of Failures in Deep Submicron SRAM Cells
Leakage power profiling and leakage power reduction using DFT hardware
Test cost optimization technique for the pre-bond test of 3D ICs
Switch-level modeling of transistor-level stuck-at faults
Reducing Scan Shift Power at RTL
Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF
Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation
Automating the verification of memory tests
Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check
Verification of transient response of linear analog circuits
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs
Differential Sensing Strategy for Dynamic Thermal Testing of ICs
The bang for the buck with resiliency: Yield or field?
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
A Bayesian-based process parameter estimation using IDDQ current signature
Apprentice - VTS edition: Season 4
Testing High-Speed SoCs Using Low-Speed ATEs
Delay-fault testability preservation of the concurrent decomposition and factorization transformations
Special Session: A Quality and Reliability Driven DFT and DFR Strategy for Automotive and Industrial Markets
Robust counterfeit PCB detection exploiting intrinsic trace impedance variations
Lifetime reliability modeling and estimation in multi-core systems
A Current Integrator for BIST of Mixed-Signal ICs
Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?
A built-in gain calibration technique for RF low-noise amplifiers
Innovation Practices Track: Industry RAS/SDC Innovative Practices - from Silicon to Mega Fleets
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms
Test Scheduling for Minimal Energy Consumption under Power Constraints
Simulation and generation of I DDQ tests for bridging faults in combinational circuits
Special Session: Reliability Assessment Recipes for DNN Accelerators
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming
Detection, diagnosis, and repair of faults in memristor-based memories
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
Power Virus Generation Using Behavioral Models of Circuits
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results
A functional BIST approach for FIR digital filters
Analyzing and Mitigating Circuit Aging Effects in Deep Learning Accelerators
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage
Electrically Induced Stimuli For MEMS Self-Test
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education
Test Reuse at System Level
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
A New Post-Silicon Debug Approach Based on Suspect Window
A Deterministic-Statistical Multiple-Defect Diagnosis Methodology
Multifrequency testability analysis for analog circuits
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits
Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems
Synthesis of Low Power CED Circuits Based on Parity Codes
Challenge Selection for Salvaging Faulty APUFs
Reduced code linearity testing of pipeline adcs in the presence of noise
AI for Test : (Innovation Practices Track)
Threshold Voltage Mismatch (DeltaVT) Fault Modeling
On Test Set Generation for Efficient Path Delay Fault Diagnosis
A new methodology for realistic open defect detection probability evaluation under process variations
Systems On Silicon: Design and Test Challenges
Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing
How Effective are Compression Codes for Reducing Test Data Volume?
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
Pin-count-aware online testing of digital microfluidic biochips
Innovative practices session 7C: Verification and testing challenges in high-level synthesis
Memory BIST Using ESP
Functional design verification for the PowerPC 601 microprocessor
Shielding Logic Locking from Redundancy Attacks
Special session: Hot topic: Smart silicon
Oscillation-test strategy for analog and mixed-signal integrated circuits
A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors
X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data
Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal
VTS 2004 Best Innovative Practices Session Award
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation
Reliability analysis and mitigation for analog computation-in-memory: from technology to application
Evaluating yield and testing impact of sub-wavelength lithography
Improving the efficiency of error identification via signature analysis
An algebraic method for delay fault testing
Innovative practices session 1C: Post-silicon validation
Innovative Practices on Automotive Test
Testing SoC Interconnects for Signal Integrity Using Boundary Scan
Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle
Innovative practices session 9B innovative practices in Asia-1: From quality perspective
Periodic Non-Destructive Memory BIST for Automotive Applications
Parallelism in Structural Fault Testing of Embedded Cores
A new high level testability measure: description and evaluation
Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC
A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq
Real-time DC motor error detection and control compensation using linear checksums
Ultra Low Cost Analog BIST Using Spectral Analysis
Dynamic scan clock control for test time reduction maintaining peak power limit
Efficient RTL Coverage Metric for Functional Test Selection
The advantages of boundary-scan testing
RT level testability-driven partitioning
Detecting NBTI induced failures in SRAM core-cells
BSM2: Next Generation Boundary-Scan Master
Test-time optimization in NOC-based manycore SOCs using multicast routing
Hot topic session 4A: Reliability analysis of complex digital systems
Synthesis of Zero-Aliasing Elementary-Tree Space Compactors
Test Power Reduction through Minimization of Scan Chain Transitions
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits
Full fault dictionary storage based on labeled tree encoding
Bounded Adjacent Fill for Low Capture Power Scan Testing
Proof carrying-based information flow tracking for data secrecy protection and hardware trust
A simulation-based approach to test pattern generation for synchronous sequential circuits
Lateral coupling faults in multi-ported register files and methods for their testing
Testability analysis based on structural and behavioral information
Exploiting Unused Spare Columns to Improve Memory ECC
Test Generation for Maximizing Ground Bounce Considering Circuit Delay
Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors
An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling
Cold Delay Defect Screening
Testable Design and Testing of Micro-Electro-Fluidic Arrays
Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award
Special Session - Test for AI Chips: from DFT to On-line Testing
Soft Error Mitigation for SRAM-Based FPGAs
Retiming sequential circuits to enhance testability
Robust switch-level test generation
Generating At-Speed Array Fail Maps with Low-Speed ATE
On-line monitoring and error correction in sensor interface circuits using digital calibration techniques
Innovative Test Practices in Asia
Fault coverage analysis of RAM test algorithms
Novel Single and Double Output TSC Berger Code Checkers
Advanced methods for leveraging new test standards
Input pattern classification for transistor level testing of BiCMOS circuits
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
Self-dual parity checking-A new method for on-line testing
Low Cost Partial Scan Design: A High Level Synthesis Approach
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Simulation of physical faults in VLSI circuits
Experimental Results for IDDQ and VLV Testing
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements
Broadcast-based minimization of the overall access time for the IEEE 1687 network
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors
Optimization of analog IC test structures
Self-Testable Pipelined ADC with Low Hardware Overhead
Innovative Practices Track: High Speed Test Fabric
Rapid online fault recovery for cyber-physical digital microfluidic biochips
RF Front-end System Gain and Linearity Built-in Test
Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation
LFSR based deterministic hardware for at-speed BIST