yusuke1997/dblp-id-title huggingface dataset:
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
Fault injection attacks on emerging non-volatile memory and countermeasures
SMARTS: secure memory assurance of RISC-V trusted SoC
Transactional Memory: Architectural Support for Lock-Free Data Structures
LUT Tensor Core: A Software-Hardware Co-Design for LUT-Based Low-Bit LLM Inference
Instant-3D: Instant Neural Radiance Field Training Towards On-Device AR/VR 3D Reconstruction
Evaluating Stream Buffers as a Secondary Cache Replacement
INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities
51st ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2024, Buenos Aires, Argentina, June 29 - July 3, 2024
Computing Size-Independent Matrix Problems on Systolic Array Processors
Effects of cache coherency in multiprocessors
Orchestrated scheduling and prefetching for GPGPUs
Retrospective: The MIT Alewife Machine: Architecture and Performance
SmartSAGE: training large-scale graph neural networks using in-storage processing architectures
CloudMonatt: an architecture for security health monitoring and attestation of virtual machines in cloud computing
Language-level persistency
A Hierarchical Microcomputer System for Hardware and Software Development
Architectural Requirements of Parallel Scientific Applications with Explicit Communication
An Analysis of Loop Latency in Dataflow Execution
Proceedings of the 6th Annual Symposium on Computer Architecture, Philadelphia, PA, USA, April 1979
DACAPO: Accelerating Continuous Learning in Autonomous Systems for Video Analytics
GraphSSD: graph semantics aware SSD
RAGO: Systematic Performance Optimization for Retrieval-Augmented Generation Serving
Corona: System Implications of Emerging Nanophotonic Technology
Performance optimizations of integrity checking based on Merkle trees
BlueDBM: an appliance for big data analytics
Contiguitas: The Pursuit of Physical Memory Contiguity in Datacenters
TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Towards energy proportionality for large-scale latency-critical workloads
ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
Understanding sources of inefficiency in general-purpose chips
Mitigating Amdahl's Law through EPI Throttling
An Architecture for Extended Abstract Data Flow
InvisiPage: oblivious demand paging for secure enclaves
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently
Synchronizing Large VLSI Processor Arrays
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
Hiding Intermittent Information Leakage with Architectural Support for Blinking
Lazy Release Consistency for Software Distributed Shared Memory
Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters
Intel® Software Guard Extensions (Intel® SGX) Architecture for Oversubscription of Secure Memory in a Virtualized Environment
48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Virtual Event / Valencia, Spain, June 14-18, 2021
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Retrospective: Tempest and Typhoon: User-Level Shared Memory
Basil Architecture - An HLL Minicomputer
The Influence of Parallel Decomposition Strategies on the Performance of Multiprocessor Systems
Retrospective on High-Level Language Computer Architecture
Software-Controlled Priority Characterization of POWER5 Processor
Output Devices Sharing by Minicomputers
Energy-efficient mechanisms for managing thread context in throughput processors
Very Long Instruction Word Architectures and the ELI-512
Rescue: A Microarchitecture for Testability and Defect Tolerance
Adaptive Compute-phase Prediction and Thread Prioritization to Mitigate Memory Access Latency
Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction
Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies
Production-Run Software Failure Diagnosis via Adaptive Communication Tracking
The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization
CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing
Use-Based Register Caching with Decoupled Indexing
The Use of Static Column RAM as a Memory Hierarchy
Analysis of Vector Access Performance on Skewed Interleaved Memory
An Architecture Framework for Application-Specific and Scalable Architectures
HardHarvest: Hardware-Supported Core Harvesting for Microservices
NASA: Accelerating Neural Network Design with a NAS Processor
Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing
Running a Quantum Circuit at the Speed of Data
Rethinking DRAM design and organization for energy-constrained multi-cores
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior
ALISA: Accelerating Large Language Model Inference via Sparsity-Aware KV Caching
Design space exploration and optimization of path oblivious RAM in secure processors
Increasing Processor Performance by Implementing Deeper Pipelines
Optimal Processor Interconnection Topologies
Compressionless Routing: A Framework for Adaptive and Fault-Tolerant Routing
Retrospective: Active Messages: A Mechanism for Integrating Computation and Communication
Performance of Cached DRAM Organizations in Vector Supercomputers
Mirage: An RNS-Based Photonic Accelerator for DNN Training
Removing architectural bottlenecks to the scalability of speculative parallelization
Design of a Fully Variable - Length Structured Minicomputer
An In-Cache Address Translation Mechanism
Multi-execution: multicore caching for data-similar executions
A dynamically configurable coprocessor for convolutional neural networks
Field-testing IMPACT EPIC research results in Itanium 2
Footprint: Regulating Routing Adaptiveness in Networks-on-Chip
A Characterization of Processor Performance in the VAX-11/780
The Anytime Automaton
A Varistructured Fail-Soft Cellular Computer
Energy-Efficient Neural Network Accelerator Based on Outlier-Aware Low-Precision Computation
GoSPA: An Energy-efficient High-performance Globally Optimized SParse Convolutional Neural Network Accelerator
Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability
Performance Characteristics of Explicit Superpage Support
Data Prefetching in Multiprocessor Vector Cache Memories
Warped-compression: enabling power efficient GPUs through register compression
Multiple Instruction Issue in the NonStop Cyclone Processor
RTSpMSpM: Harnessing Ray Tracing for Efficient Sparse Matrix Computations
A Hardware Unification Unit: Design and Analysis
Fair-CO2: Fair Attribution for Cloud Carbon Emissions
F4T: A Fast and Flexible FPGA-based Full-stack TCP Acceleration Framework
Duality cache for data parallel acceleration
Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators
A High Performance Prolog Processor with Multiple Function Units
The role of the fault model in DFA against AES
The Optimum Pipeline Depth for a Microprocessor
MD-pipe: A Strong Scaling Enhanced Pipeline Architecture for Ab Initio Accuracy Molecular Dynamics
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems
Inspection resistant memory: Architectural support for security from physical examination
A Relational Data Base Machine: First Step to Knowledge Base Machine
Hardware Alorithms for Nonnumeric Computation
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Rebound: scalable checkpointing for coherent shared memory
Flattened butterfly: a cost-efficient topology for high-radix networks
A Content Aware Integer Register File Organization
Cache Replacement with Dynamic Exclusion
LIPP-A SIMD Multiprocessor Architecture for Image Processing
Tagged Architecture and the Semantics of Programming Languages: Extensible Types
Multi-Dimensional Systolic Networks for Discrete Fourier Transform
ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design
AxMemo: hardware-compiler co-design for approximate code memoization
Characteristics of Workloads Using the Pipeline Programming Model
High Performance Communications in Processor Networks
CaliQEC: In-situ Qubit Calibration for Surface Code Quantum Error Correction
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History
Memory persistency
MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State
Selective Eager Execution on the PolyPath Architecture
ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators
An end to end IR stack for deep learning systems
The Yin and Yang of power and performance for asymmetric hardware and managed software
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer
Pipelines wth Internal Buffers
Streamlining Data Cache Access with Fast Address Calculation
Retrospective: A Personal Retrospective on the NYU Ultracomputer
Energy-efficient video processing for virtual reality
Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks
An Expanded Multiprocessor Architecture for Video Graphics
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine
The Design of a Mass Memory for a Database Computer
The impact of memory subsystem resource sharing on datacenter applications
Towards User Transparent Parallel Multimedia Computing on GPU-Clusters
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
JPEG-ACT: Accelerating Deep Learning via Transform-based Lossy Compression
Caddie - An Interactive Design Environment
Rethinking Belady's Algorithm to Accommodate Prefetching
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
OliVe: Accelerating Large Language Models via Hardware-friendly Outlier-Victim Pair Quantization
PUMP: a programmable unit for metadata processing
An IPC Protocol and Its Hardware Realization for a High-Speed Distributed Multicomputer System
Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA
A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar Switches
Software-hardware co-design for fast and scalable training of deep learning recommendation models
XPro: A Cross-End Processing Architecture for Data Analytics in Wearables
Software Versus Hardware Shared-Memory Implementation: A Case Study
Reducing Memory Contention in Shared Memory Multiprocessors
Target Prediction for Indirect Jumps
Translation caching: skip, don't walk (the page table)
Characterization of Alpha AXP Performance Using TP and SPEC Workloads
Adaptive Cache Bypass and Insertion for Many-core Accelerators
Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory
Doubly Twisted Torus Networks for VLSI Processing Arrays
Memory access scheduling
Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor
All I want for Christmas... is a CUDA ASIC
Accelerating attention through gradient-based learned runtime pruning
QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms
A Performance Analysis of Automatically Managed Top of Stack Buffers
A GALS Router for Asynchronous Network-on-Chip
Energy-Efficient Realtime Motion Planning
Selective, accurate, and timely self-invalidation using last-touch prediction
MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation
A Cellular General Purpose Computer
FloatPIM: in-memory acceleration of deep neural network training with high precision
DCD - Disk Caching Disk: A New Approach for Boosting I/O Performance
Performance Comparison of Load/Store and Symmetric Instruction Set Architectures
A Specialized Architecture for Object Serialization with Applications to Big Data Analytics
A Virtual Memory for Microprocessors
Planar-Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors
Adjustable Block Size Coherent Caches
Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations
Improving NAND Flash Based Disk Caches
Lx: a technology platform for customizable VLIW embedded processing
On the Working Set Concept for Data-Flow Machines
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences
An Efficient VLSI Dictionary Machine
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work
Power Attack Defense: Securing Battery-Backed Data Centers
ZSim: fast and accurate microarchitectural simulation of thousand-core systems
CORD: Low-Latency, Bandwidth-Efficient and Scalable Release Consistency via Directory Ordering
Lockup-Free Instruction Fetch/Prefetch Cache Organization
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions
Circuits for wide-window superscalar processors
SHRINK: reducing the ISA complexity via instruction recycling
Trace Execution Automata in Dynamic Binary Translation
BioHD: an efficient genome sequence search platform using HyperDimensional memorization
Decoupling Loads for Nano-Instruction Set Computers
End-to-end sequential consistency
A Low-resource and Scalable Strategy for Segment Partitioning of Many-core Nano Networks
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation
Division of Labor: A More Effective Approach to Prefetching
Hardware-Software Co-Design for Brain-Computer Interfaces
On Refuting the Creation Theory of Computer Architecture
NanoFabrics: spatial computing using molecular electronics
Efficient execution of memory access phases using dataflow specialization
A case for exposing extra-architectural state in the ISA: position paper
RoboShape: Using Topology Patterns to Scalably and Flexibly Deploy Accelerators Across Robots
Efficient virtual memory for big memory servers
Flexible software profiling of GPU architectures
PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures
Exploiting Page Table Locality for Agile TLB Prefetching
Thin servers with smart pipes: designing SoC accelerators for memcached
Thermal modeling and management of DRAM memory systems
Tri-level-cell phase change memory: toward an efficient and reliable memory system
An Evaluation of Directory Schemes for Cache Coherence
Comparative Evaluation of Latency Reducing and Tolerating Techniques
Retrospective: A Retrospective on High-Level Language Computer Architecture
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures
Supporting Systolic and Memory Communciation in iWarp
PF-DRAM: A Precharge-Free DRAM Structure
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers
AQB8: Energy-Efficient Ray Tracing Accelerator through Multi-Level Quantization
A Fast Display-Oriented Processor
Storage Concepts in a Software-Reliabiltiy
Review of the Workshop on Computer Architecture Education
Data Flow Languages and Architecture
Architectural implications of brick and mortar silicon manufacturing
Kensur: An Architecture Oriented Towards Programming Languages Translation
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware
IXM2: A Parallel Associative Processor
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
Rethinking programmable wearable processors
Variational Quantum Algorithms in the era of Early Fault Tolerance
LaZy superscalar
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
Prefetch unit for vector operations on scalar computers
BabelFish: Fusing Address Translations for Containers
Switcherland: A QoS Communication Architecture for Workstation Clusters
A Two-Level Load/Store Queue Based on Execution Locality
Some Implementations of Segment Sequential Functions
A fully associative, tagless DRAM cache
A Microprocessor-Controlled Asynchronous Circuit Switching Network
Decentralized Computation
Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators
Combining Speed with Alpha-Particle Induced Memory Error Tolerance in a Large Boolean Vector Machine (Extended Abstract)
The Hughes Data Flow Multiprocessor: Architecture for Efficient Signal and Data Processing
HOOP: Efficient Hardware-Assisted Out-of-Place Update for Non-Volatile Memory
Towards a family of languages for the design and implementation of machine architectures
Impact of Hardware Interconnection Structures on the Performance of Decentralized Software
Automatic abstraction and fault tolerance in cortical microachitectures
Seasoning effect based side channel attacks to AES implementation with phase change memory
Rotating Combined Queueing (RCQ): Bandwidth and Latency Guarantees in Low-Cost, High-Performance Networks
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Improving writeback efficiency with decoupled last-write prediction
Deconfigurable microprocessor architectures for silicon debug acceleration
QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction
Telos: A Dataflow Accelerator for Sparse Triangular Solver of Partial Differential Equations
MemGuard: A low cost and energy efficient design to support and enhance memory system reliability
Memory mapped ECC: low-cost error protection for last level caches
Anticipating and eliminating redundant computations in accelerated sparse training
HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy
I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches
Memory-System Design Considerations for Dynamically-Scheduled Processors
MLPerf Inference Benchmark
Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs
Towards a Parallel SIMULA Machine
Internet-scale service infrastructure efficiency
Performance of the SCI Ring
Multi-Level Texture Caching for 3D Graphics Hardware
The V-Way Cache: Demand Based Associativity via Global Replacement
Energy proportional datacenter networks
MiSAR: minimalistic synchronization accelerator with resource overflow management
Multiprocessor Cache Synchronization: Issues, Innovations, Evolution
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime
Cache Design of a Sub-Micron CMOS System/370
A Closed Loop Control based Power Manager for WiNoC Architectures
Fault Diagnosis of Bit-Slice Processor
MeshSlice: Efficient 2D Tensor Parallelism for Distributed DNN Training
RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision
Design Choices in the SHRIMP System: An Empirical Study
A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus
Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices
Weak Ordering - A New Definition
A Cache Consistency Protocol for Multiprocessors with Multistage Networks
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Rapid profiling via stratified sampling
Morpheus: benchmarking computational diversity in mobile malware
A new perspective for efficient virtual-cache coherence
Performance Evaluation of a Communication System for Transputer-Networks Based on Monitored Event Traces
ShortCut: Architectural Support for Fast Object Access in Scripting Languages
Inference Machine: From Sequential to Paralle
Bulk Disambiguation of Speculative Threads in Multiprocessors
Soter: Analytical Tensor-Architecture Modeling and Automatic Tensor Program Tuning for Spatial Accelerators
Decoupled Hardware Support for Distributed Shared Memory
Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors
A Case for MLP-Aware Cache Replacement
Polling Watchdog: Combining Polling and Interrupts for Efficient Message Handling
Execution Characteristics of Desktop Applications on Windows NT
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives
Adaptive Cache Coherency for Detecting Migratory Shared Data
Seamless - a latency-tolerant RISC-based multiprocessor architecture
Using Feedback to Control Tree Saturation in Multistage Interconnection Networks
Retrospective: The DASH Prototype: Implementation and Performance
LReplay: a pending period based deterministic replay scheme
ATUM: A New Technique for Capturing Address Traces Using Microcode
RegMutex: Inter-Warp GPU Register Time-Sharing
On Data Synchronization for Multiprocessors
Instruction Cache Fetch Policies for Speculative Execution
Slipstream Processors Revisited: Exploiting Branch Sets
On the Comparison Between Single and Multiple Processor Systems
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors
Data Prefetching on the HP PA-8000
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction
Thread motion: fine-grained power management for multi-core systems
NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs
A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology
Cost-Efficient Overclocking in Immersion-Cooled Datacenters
Exploiting Fine-Grained Parallelism Through a Combination of Hardware and Software Techniques
Scaling Llama 3 Training with Efficient Parallelism Strategies
VAX Vector Architecture
General-purpose code acceleration with limited-precision analog computation
A High-Level Multi-Lingual Multiprocessor KMP
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability
A Large, Fast Instruction Window for Tolerating Cache Misses
Forwardflow: a scalable core for power-constrained CMPs
Performance Evaluation of the PowerPC 620 Microarchitecture
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs
HeterRAG: Heterogeneous Processing-in-Memory Acceleration for Retrieval-augmented Generation
Scheduling Pipelined Communication in Distributed Memory Multiprocessors for Real-Time Applications
XQsim: modeling cross-technology control processors for 10+K qubit quantum computers
Decoupled Affine Computation for SIMT GPUs
HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs
A Technique for the Architectural Implementation of Software Subsystems
A Structured Language for CAD of Digital Systems
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
An Instruction Fetch Unit for a Graph Reduction Machine
Retrospective: Lockup-Free Instruction Fetch/Prefetch Cache Organization