yusuke1997/dblp-id-title huggingface dataset:
Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules
Hierarchical analysis of process variation for mixed-signal systems
Side-channel Collision Attacks on Hyper-Dimensional Computing based on Emerging Resistive Memories
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design
Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity
Physical Synthesis for Advanced Neural Network Processors
An image retrieval system using FPGAs
ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA
SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks
Raads: Rapidus's AI/ML based assisted design flow to reduce design period halved
DFT timing design methodology for at-speed BIST
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Constrained global scheduling of streaming applications on MPSoCs
Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems
Frequent value compression in packet-based NoC architectures
A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem
PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing
A benchmark suite for substrate analysis
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration
Time and energy efficient mapping of embedded applications onto NoCs
Enhancement of parallelism for tearing-based circuit simulation
Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications
Efficient Global Optimization for Large Scaled Ordered Escape Routing
VOLtA: Voltage over-scaling based lightweight authentication for IoT applications
Loop Pipelining in Hardware-Software Partitioning
Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, January 16-19, 2023
A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits
Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness
A fast and accurate method for interconnect current calculation
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process
Geometry variations analysis of TiO2 thin-film and spintronic memristors
Efficient sensitivity-based capacitance modeling for systematic and random geometric variations
Data transmission over a bus with peak-limited transition activity
A Design of Sound Synthesis IC
Robust high-performance low-power carry select adder
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement
Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs
A thread partitioning algorithm in low power high-level synthesis
Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface
Return path selection for loop RL extraction
Parasitics extraction involving 3-D conductors based on multi-layered Green's function
Fast, quasi-optimal, and pipelined instruction-set extensions
Predicting circuit aging using ring oscillators
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 n )
A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead
Exploiting 2.5D/3D Heterogeneous Integration for AI Computing
EUV lithography: Prospects and challenges
Scheduler implementation in MP SoC design
A dynamic test compaction procedure for high-quality path delay testing
A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios
Optimized address assignment for DSPs with SIMD memory accesses
The role of photons in cryptanalysis
Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradation
Layer minimization in escape routing for staggered-pin-array PCBs
Detection and diagnosis of faulty quantum circuits
Self-reforming routing for stochastic search in VLSI interconnection layout
Self-timed 1-D ICT processor
Random Stimuli Generation for the Verification of Quantum Circuits
A Technology-Independent Methodology of Placement Generation for Analog Circuit
POSIX modeling in SystemC
Design and design automation of rectification logic for engineering change
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
Engineering complex systems for health, security and the environment
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices
An Effcient 2-D Convolver Chip for Real Time Image Processing
Parallel verilog simulation: architecture and circuit partition
Locality-aware bank partitioning for shared DRAM MPSoCs
High-level synthesis scheduling and allocation using genetic algorithms
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization
A time domain behavioral model for oscillators considering flicker noise
Sequential equivalence checking using cuts
A prototype chip of multicontext FPGA with DRAM for virtual hardware
Application specific sensor node architecture optimization - Experiences from field deployments
Handling partial correlations in yield prediction
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
A digital SC converter with high efficiency and low voltage ripple
In-memory batch-normalization for resistive memory based binary neural network hardware
Limiting the Search Space in Optimal Quantum Circuit Mapping
Design space exploration for a coarse grain accelerator
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Functionality directed clustering for low power MTCMOS design
Exploitation signal flow and logic dependency in standard cell placement
Taiwan foundry for system-in-package (SIP)
A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate
A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain
HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner
Analysis and optimization of gate leakage current of power gating circuits
ASIP approach for implementation of H.264/AVC
Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS: Towards Distributed and Scalable Environmental Sensing with a Myriad of Nodes
Floorplan management: incremental placement for gate sizing and buffer insertion
Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction
Optimization of overdrive signoff
Statistical noise margin estimation for sub-threshold combinational circuits
Scheduling and shaping of complex task activations for mixed-criticality systems
Reconfigurable Systems: A Survey (Embedded Tutorial)
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
Optimal reconfiguration sequence management
Towards Efficient Kyber on FPGAs: A Processor for Vector of Polynomials
DefectTrackNet: Efficient Root Cause Analysis of Wafer Defects in Semiconductor Manufacturing Using a Lightweight CNN-Transformer Architecture
Automated throughput-driven synthesis of bus-based communication architectures
HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs
Linear time algorithm to find all relocation positions for EUV defect mitigation
A Low-Power VCO based ADC with asynchronous sigma-delta modulator in 65nm CMOS
Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset
Performance sensitivity analysis using statistical method and its applications to delay
K-disjointness paradigm with application to symmetry detection for incompletely specified functions
300MHz design methodology of VU for emotion synthesis
Decision Diagrams for Discrete Functions: Classification and Unified Interpretation
Built-in chaining: introducing complex components into architectural synthesis
Analysis of buffered hybrid structured clock networks
RF-analog circuit design in scaled SoC
Design time body bias selection for parametric yield improvement
Unified Redistribution Layer Routing for 2.5D IC Packages
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
Recent developments in ESD protection for RF ICs
Instruction scheduling of VLIW architectures for balanced power consumption
Current-driven wire planning for electromigration avoidance in analog circuits
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron
Fast circuit simulation on graphics processing units
Toward better wireload models in the presence of obstacles
Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters
Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits
Guiding fault-driven adaption in multicore systems through a reliability-aware static task schedule
A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique
Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers
Co-synthesis of a configurable SoC platform based on a network on chip architecture
Reliable Memristive Neural Network Accelerators Based on Early Denoising and Sparsity Induction
Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation
Redeeming chip-level power efficiency by collaborative management of the computation and communication
A Multi-Commodity Network Flow Based Routing Algorithm for Paper-Based Digital Microfluidic Biochips
A reconfigurable, power-scalable rake receiver IP for W-CDMA
A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor
An HDL-synthesized gated-edge-injection PLL with a current output DAC
Buffer allocation algorithm with consideration of routing congestion
Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation
Optimization of circuit trajectories: an auxiliary network approach
A C-based synthesis system, Bach, and its application (invited talk)
Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
An implementation of a CMOS down-conversion mixer for GSM1900 receiver
Interconnect modeling for improved system-level design optimization
Achieving continuous V T performance in a dual V T process
ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory
Trace-based performance analysis framework for heterogeneous multicore systems
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs
Routing-aware scan chain ordering
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration
Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns
Maximizing power state cross coverage in firmware-based power management
Dynamic thermal management for multi-core microprocessors considering transient thermal effects
Logic optimization using rule-based randomized search
WEID: Worst-case Error Improvement in Approximate Dividers
A Look Up Table design with 3D bipolar RRAMs
Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars
BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms
Scan-based attack against elliptic curve cryptosystems
A neural network approach to the placement problem
Rethinking B-epsilon tree Indexing Structure over NVM with the Support of Multi-write Modes
An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation
Optimizing Decision Diagrams for Measurements of Quantum Circuits
Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC
An adaptive filtering mechanism for energy efficient data prefetching
Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability
Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
Timing influenced generell-cell genetic floorplanner
A new register file access architecture for software pipelining in VLIW processors
Architectural aspects in design and analysis of SOT-based memories
Communication Architecture Synthesis of Cascaded Bus Matrix
Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators
A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization
PIMutation: Exploring the Potential of Real PIM Architecture for Quantum Circuit Simulation
Low-power neuromorphic speech recognition engine with coarse-grain sparsity
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects
Slicing Floorplans with Boundary Constraint
A practical cut-based physical retiming algorithm for field programmable gate arrays
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification
A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms
Structural rewriting in XOR-majority graphs
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
HitME: low power Hit MEmory buffer for embedded systems
Applying VLSI EDA to energy distribution system design
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor
Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis
Fast Electromigration Stress Analysis Considering Spatial Joule Heating Effects
Virtual prototyping of smart systems through automatic abstraction and mixed-signal scheduling
Performance estimation of embedded software with confidence levels
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999
Security Threats and Countermeasures for Approximate Arithmetic Computing
A high performance LDPC decoder for IEEE802.11n standard
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults
Data-Driven Approaches for Process Simulation and Optical Proximity Correction
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing
E-QUARTIC: Energy Efficient Edge Ensemble of Convolutional Neural Networks for Resource-Optimized Learning
A variation-aware low-power coding methodology for tightly coupled buses
ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches
Embedded tutorial: IC design technology for building system-on-a-chip
MUP: a minimal unsatisfiability prover
Optimizing translation information management in NAND flash memory storage systems
Quantum key distribution with integrated optics
Implication of assertion graphs in GSTE
Highly scalable algorithms for rectilinear and octilinear Steiner trees
Fast hybrid simulation for accurate decoded video quality assessment on MPSoC platforms with resource constraints
EPROF: An energy/performance/reliability optimization framework for streaming applications
MPSoC programming using the MAPS compiler
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Efficient identification of multi-cycle false path
Superlog, a unified design language for system-on-chip
Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning
Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit Optimization
ASP-DAC 2017 keynote speech I-2: Electronics for the human body
Optimizing thread-to-core mapping on manycore platforms with distributed Tag Directories
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration
Multi-clock path analysis using propositional satisfiability
Mapping and configuration methods for multi-use-case networks on chips
EO-Shield: A Multi-Function Protection Scheme against Side Channel and Focused Ion Beam Attacks
Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC
Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units
Highly sensitive fingerprint readout IC for glass-covered mutual capacitive fingerprint sensor
A statistical static timing analysis considering correlations between delays
Efficient Routing in Coarse-Grained Reconfigurable Arrays Using Multi-Pole NEM Relays
Thermal-Aware Layout Optimization and Mapping Methods for Resistive Neuromorphic Engines
Partitioning and placement for buildable QCA circuits
CycSAT-unresolvable cyclic logic encryption using unreachable states
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Exploiting program execution phases to trade power and performance for media workload
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation
A higher level system communication model for object-oriented specification and design of embedded systems
A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit Deobfuscation
GRAM: graph processing in a ReRAM-based computational memory
Constraint-free analog placement with topological symmetry structure
Memory subsystem simulation in software TLM/T models
Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU
Run-time adaptive performance compensation using on-chip sensors
Energy Harvesting Aware Multi-Hop Routing Policy in Distributed IoT System Based on Multi-Agent Reinforcement Learning
On using SAT to ordered escape problems
AutoFlex: Unified Evaluation and Design Framework for Flexible Hybrid Electronics
Power control of CDMA systems with successive interference cancellation using the knowledge of battery power capacity
Linear decomposition of index generation functions
NESTA: Hamming Weight Compression-Based Neural Proc. EngineAli Mirzaeian
Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization
Realization of Regular Ternary Logic Functions
Structural approach for performance driven ECC circuit synthesis
A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR
MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention Recognition
Piecewise-polynomial associated transform macromodeling algorithm for fast nonlinear circuit simulation
Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip
Design at the end of the silicon roadmap
SonicFFT: A system architecture for ultrasonic-based FFT acceleration
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles
A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology
Mixed-clock issue queue design for energy aware, high-performance cores
A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators
Improved alternative wiring scheme applying dominator relationship
Energy efficient joint scheduling and multi-core interconnect design
FastRoute 2.0: A High-quality and Efficient Global Router
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
A wide conversion ratio, 92.8% efficiency, 3-level buck converter with adaptive on/off-time control and shared charge pump intermediate voltage regulator
Genetic algorithm accelerator GAA-II
Pearl: Towards Optimization of DNN-accelerators Via Closed-Form Analytical Representation
High-Dimensional Yield Estimation Using Shrinkage Deep Features and Maximization of Integral Entropy Reduction
Performance test of Viterbi decoder for wideband CDMA system
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM
-Possibility of ESL-: a software centric system design for multicore SoC in the upstream phase
NETA: when IP fails, secrets leak
Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes
A 2.2µW 15b incremental delta-sigma ADC with output-driven input segmentation
CMP aware shuttle mask floorplanning
A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component Analysis
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
Design and chip implementation of the ubiquitous processor HCgorilla
ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions
An Edge AI and Adaptive Embedded System Design for Agricultural Robotics Applications
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Tightly integrate dynamic verification with formal verification: a GSTE based approach
An Efficient near-Bank Processing Architecture for Personalized Recommendation System
Learning Boolean Circuits from Examples for Approximate Logic Synthesis
ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration
VFGR: A very fast parallel global router with accurate congestion modeling
Cache size selection for performance, energy and reliability of time-constrained systems
A Performance-Driven I/O Pin Routing Algorithm
CAD challenges for 3D ICs
Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration
In Medio Stat Virtus*: Combining Boolean and Pattern Matching
A new partitioning scheme for improvement of image computation
Timing driven co-design of networked embedded systems
An 8-b nRERL microprocessor for ultra-low-energy applications
MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation