yusuke1997/dblp-id-title huggingface dataset:
Forward-looking objective functions: concept & applications in high level synthesis
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking
DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks
Increasing confidence on measurement-based contention bounds for real-time round-robin buses
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators
Partitioning by Regularity Extraction
Physics-aware Roughness Optimization for Diffractive Optical Neural Networks
Principles of design automatioon system for very large scale computer design
On-die power grids: the missing link
Predicting future technology performance
A graphics aided drafting system (GRAD)
Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice
Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration Optimization
Reliable verification using symbolic simulation with scalar values
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
Improving the Concurrency Performance of Persistent Memory Transactions on Multicores
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
RoboRun: A Robot Runtime to Exploit Spatial Heterogeneity
The channel expansion problem in layout design
Generalized translation in a data base system
ASCE Avionic System Configuration Evaluation
Process variation in near-threshold wide SIMD architectures
Construction of DAG Models for Autonomous Systems
A learning digital computer
Enhancing timing-driven FPGA placement for pipelined netlists
An Interactive Tool for Register-level Structure Optimization
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs
CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs
Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM
Adversarial Machine Learning Beyond the Image Domain
Topographic simulation as an aid to printed circuit board design
Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition
REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning
MAT: Processing In-Memory Acceleration for Long-Sequence Attention
Performance analysis and optimization of latency insensitive systems
Circuit Extraction on a Message-Based Multiprocessor
High-Level Test Generation for Design Verification of Pipelined Microprocessors
Hierarchical Reversible Logic Synthesis Using LUTs
KATO: Knowledge Alignment And Transfer for Transistor Sizing Of Different Design and Technology
Test response compactor with programmable selector
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers
Circuit diagram generation via functional logic
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture
Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR
Integrated CPU-GPU Power Management for 3D Mobile Games
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization
Concurrent topology and routing optimization in automotive network integration
GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer
An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM)
On the Over-Specification Problem in Sequential ATPG Algorithms
An energy saving strategy based on adaptive loop parallelization
Invited - A box of dots: using scan-based path delay test for timing verification
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling
An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling
Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulation
A distributed algorithm for layout geometry operations
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
Directed-simulation assisted formal verification of serial protocol and bridge
A hardware engine for analogue mode simulation of MOS digital circuits
Analysis of security of split manufacturing using machine learning
Achieving 550Mhz in an ASIC Methodology
Noise characterization of static CMOS gates
Software Development in a Hardware Simulation Environment
Context-aware dataflow adaptation technique for low-power multi-core embedded systems
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications
ISA Modeling with Trace Notation for Context Free Property Generation
Variability analysis under layout pattern-dependent rapid-thermal annealing process
Diagnosing scan clock delay faults through statistical timing pruning
An Object-Oriented Datamodel for the VLSI Design System PLAYOUT
Blade and razor: cell and interconnect delay analysis using current-based models
Hierarchial global wiring for custom chip design
Neural computation for robust and holographic face detection
Interactive graphics package for human engineering and layout of vehicle workspace
Special purpose vs. general purpose hardware for da
Optimizing Systems for Effective Block-Processing: The k -Delay Problem
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration
Regression verification
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs
Waveform Moment Methods for Improved Interconnection Analysis
Rephasing: A Transformation Technique for the Manipulation of Timing Constraints
Approximate bitcoin mining
Pathfinding Model and Lagrangian-Based Global Routing
A timing graph based approach to mode merging
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers
Differential Fault Simulation - a Fast Method Using Minimal Memory
Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance
TACO: timing analysis with coupling
Information dispersion for trojan defense through high-level synthesis
RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers
Equivalence Checking Using Cuts and Heaps
A procedure for checking the topological consistency of a 2-D or 3-D finite element mesh
Efficient and accurate gate sizing with piecewise convex delay models
System-Level Security for Network Processors with Hardware Monitors
iMARS: an in-memory-computing architecture for recommendation systems
Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
GENAC: An Automatic Cell Synthesis Tool
A hardware description language for processor based digital systems
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
A Scheme for Overlaying Concurrent Testing of VLSI Circuits
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies
DrAcc: a DRAM based accelerator for accurate CNN inference
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
Combinatorial aspects of automated designs
Essential Building Blocks for Creating an Open-source EDA Project
A simulation system for implementation and evaluation of diagnostic programs of a special-purpose telecommunication switching processor
A simulation model for evaluating the effectiveness of various stock market strategies
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology
Generative Model Based Standard Cell Timing Library Characterization
Designing systems-on-chip using cores
Lazy symbolic model checking
Automatic checking of logic design structures For compliance with testability ground rules
Test data verification - not just the final step for test data before release for production testing
Balancing Scalability and Uniformity in SAT Witness Generator
A Nuffer Distribution Algorithm for High-Speed Clock Routing
Simulation techniques for microprocessors
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools
CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search
Predictable sharing of last-level cache partitions for multi-core safety-critical systems
PHRAN-SPAN: A Natural Language Interface for System Specifications
An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor
Automation of test specifications for N/C printed circuit boards
Proceedings of the 20th System Level Interconnect Prediction Workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018
Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time Hypervisor
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits
A New Optimizer for Performance Optimization of Analog Integrated Circuits
An experimental MOS fault simulation program CSASIM
A partial solution to fitting large parametric surfaces in computer-aided design systems
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
Area and search space control for technology mapping
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference
On Using Implied Values in EDT-based Test Compression
NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing System
Accelerating DNN Inference with Heterogeneous Multi-DPU Engines
CREST-CiM: Cross-Coupling-Enhanced Differential STT-MRAM for Robust Computing-in-Memory in Binary Neural Networks
SAT-based unbounded symbolic model checking
Clock Event Suppression Algorithm of VELVET and Its Application to S-820 Development
Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture
Engineering design aspects
Scheduling-based test-case generation for verification of multimedia SoCs
EcoFusion: energy-aware adaptive sensor fusion for efficient autonomous vehicle perception
Case studies: Chip design on the bleeding edge (panel session abstract)
Over-the-Cell Routers for New Cell Model
The Clinton/Gore Technology Policies
A router for multilayer printed wiring backplanes
MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns
CORAL II: Linking Behavior and Structure in an IC Design System
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Using introspective software-based testing for post-silicon debug and repair
Efficient state representation for symbolic simulation
Integrating Formal Verification Methods with A Conventional Project Design Flow
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers
HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration
Chiplets: How Small is too Small?
Application-Driven Design Automation for Microprocessor Design
Fast Adversarial Training with Dynamic Batch-level Attack Control
Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *
SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine Learning
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems
The Best of Both Worlds: On Exploiting Bit-Alterable NAND Flash for Lifetime and Read Performance Optimization
CADTOOLS: a CAD algorithm development system
A branch and bound algorithm for optimal pla folding
Computer-aided prediction of delays in LSI logic systems
Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration
Circuit Compilers don't have to be Slow
MOSS: Multi-Modal Representation Learning on Sequential Circuits
Exploring sub-20nm FinFET design with predictive technology models
A database approach for managing VLSI design data
Dynamic hardware/software partitioning: a first approach
Reducing Power in High-Performance Microprocessors
Lightning Talk: Bridging Neuro-Dynamics and Cognition
BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal Layers
Compiler-based side channel vulnerability analysis and optimized countermeasures application
Automatic Layout Synthesis of Leaf Cells
ClariNet: a noise analysis tool for deep submicron design
Guiding simulation with increasingly refined abstract traces
Hybrid Verification Using Saturated Simulation
Fault Tolerance in Time-Sensitive Networking with Mixed-Critical Traffic
Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip
Utilizing Memory Bandwidth in DSP Embedded Processors
Design Process Management for CAD Frameworks
What don't we know about CPS architectures?
A successful automated IC design system
The Metric Matters: The Art of Measuring Trust in Electronics
Behavioral level transformation in the CMU-DA system
Optimized Design of a Human Intranet Network
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning
Design Productivity: How To Measure It, How To Improve It (Panel)
Combining graphics and a layout language in a single interactive system
How to Boost Deep Neural Networks for Computer Vision
An Optimal Algorithm for Floorplan Area Optimization
DRPTM: A Decoupled Read-efficient High-scalable Persistent Transactional Memory
Design challenges for next-generation multimedia, game and entertainment platforms
Architecture-level performance evaluation of component-based embedded systems
General Chair's Message
Formal verification methods: getting around the brick wall
Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation
A novel 3D DRAM memory cube architecture for space applications
A technology independent MOS multiplier generator
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification
Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory Computing
Compaction with Incremental Over-Constraint Resolution
Design and CAD for 3D integrated circuits
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
Interactive graphics for volume modeling
The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve
Invited - Context-aware energy-efficient communication for IoT sensor nodes
Matlab as a development environment for FPGA design
A Unified Approach for the Synthesis of Self-Testable Finite State Machines
Superpipelined Control and Data Path Synthesis
Design of a SPDIF Receiver Using Protocol Compiler
Low-power repeater insertion with both delay and slew rate constraints
A Model Checking-based Analysis Framework for Systems Biology Models
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis
Virtual grid symbolic layout
An analytical algorithm for placement of arbitrarily sized rectangular blocks
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
Active Documentation: A New Interface for VLSI Design
A machine learning framework to identify detailed routing short violations from a placed netlist
Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized Multicores
GENERIC: highly efficient learning engine on edge using hyperdimensional computing
Sidekick: Near Data Processing for Clustering Enhanced by Automatic Memory Disaggregation
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
Ultra-thin Skin Electronics for High Quality and Continuous Skin-Sensor-Silicon Interfacing
RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops
Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing
A remote design station for customer Uncommitted Logic Array designs
Buffer memory optimization for video codec application modeled in Simulink
An ECL Logic Synthesis System
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Analyze - Compose - Display computer aided space planning
Crosstalk noise estimation for noise management
Test Generation in the Presence of Timing Exceptions and Constraints
Predictive design space exploration using genetically programmed response surfaces
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference
To collect or not to collect: just-in-time garbage collection for high-performance SSDs with long lifetimes
All-in-Memory Stochastic Computing using ReRAM
Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time
On routing for custom integrated circuits
VLSI Design and System Level Verification for the Mini-Disc
Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor
QURE: Qubit Re-allocation in Noisy Intermediate-Scale Quantum Computers
PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis
Real-Time Scheduling and Analysis of Synchronous OpenMP Task Systems with Tied Tasks
Synergistic timing speculation for multi-threaded programs
Routing for Manufacturability
On Improving Fault Diagnosis for Synchronous Sequential Circuits
A topology for semicustom array-structured LSI devices, and their automatic customisation
Hierarchical hybrid power supply networks
An interactive drafting system based on two dimensional primitives
Engineering workstation applications to systems design (panel session): life above the IC
Symbolic Modeling and Evaluation of Data Paths
Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories
Logic Simulation System Using Simulation Processor (SP)
A Hardware/Software Co-design Flow and IP Library Based of Simulink TM
Navigating registers in placement for clock network minimization
Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems
Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency Estimation
A method to decompose multiple-output logic functions
An Approach to Incremental Design of Distributed Embedded Systems
MetaZip: a high-throughput and efficient accelerator for DEFLATE
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA
Control and integration of a CAD data base
SMERT: energy-efficient design of a multimedia messaging system for mobile devices
Enhanced leakage reduction Technique by gate replacement
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning
Nona: Accurate Power Prediction Model Using Neural Networks
A pattern generator system - hardward/software
Riot - a simple graphical chip assembly tool
Automotive Software Integration
Global wiring on a wire routing machine
Accelerating Regular Path Queries over Graph Database with Processing-in-Memory
X-DeepSCA: Cross-Device Deep Learning Side Channel Attack
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads
Design Automation Standards Need Integration
Bounds for BEM Capacitance Extraction
Model design using hierarchical web-based libraries
STAFAN: An alternative to fault simulation
A new look at logic synthesis
Compiling Esterel into sequential code
Proceedings of the 18th Design Automation Conference, DAC '81, Nashville, Tennessee, USA, June 29 - July 1, 1981
Analog Placement Based on Novel Symmetry-Island Formulation
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths
VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash Memory
TAO: techniques for algorithm-level obfuscation during high-level synthesis
FFD: A Framework for Fake Flash Detection
Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource Management
Reasoning about safety of learning-enabled components in autonomous cyber-physical systems
Fast and flexible buffer trees that navigate the physical layout environment
Bandwidth-efficient on-chip interconnect designs for GPGPUs
Compiled HW/SW Co-Simulation
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS
Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration
Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment
Characterization and Parameterized Random Generation of Digital Circuits
RJOP: a customized Java processor for reactive embedded systems
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
A new state assignment technique for testing and low power
Reinventing EDA with manycore processors
Recovery-based design for variation-tolerant SoCs
Efficient Boolean operations on IC masks
Spectral graph sparsification in nearly-linear time leveraging efficient spectral perturbation analysis
Lightning Talk: Power and Performance Reconciliation - from Tradeoff to Win-Win
I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
A realizable driving point model for on-chip interconnect with inductance
Automatic generation of cells for recurrence structures
Hierarchical Pitchmatching Compaction Using Minimum Design
Reversible statistical max/min operation: concept and applications to timing
Layout Decomposition via Boolean Satisfiability
Optimizations for configuring and mapping software pipelines in many core systems
Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements
Don't Care-Based BDD Minimization for Embedded Software
Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines
FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display
Conversion of engineering drawings to digital form
Control Variate Approximation for DNN Accelerators
Speedpath analysis under parametric timing models
Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications
DeepGate: learning neural representations of logic gates
Programs for verifying circuit connectivity of mos/lsi mask artwork
TyTAN: tiny trust anchor for tiny devices
A framework for block-based timing sensitivity analysis
LO-FAT: Low-Overhead Control Flow ATtestation in Hardware
Design Flow Management in the NELSIS CAD Framework
New Time-Domain Preconditioners for HB Jacobian of RF Circuits
Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers
Estimating Architectural Resources and Performance for High-Level Synthesis Applications
Curvilinear Optical Proximity Correction via Cardinal Spline
A case for NEMS-based functional-unit power gating of low-power embedded microprocessors
Power minimization derived from architectural-usage of VLIW processors
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation
Improved tangent space based distance metric for accurate lithographic hotspot classification
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness
An automated database design tool using the ELKA conceptual model
CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator