yusuke1997/dblp-id-title huggingface dataset:
2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, USA, April 30 - May 4, 2018
FitBit: Ensuring Robust and Secure Execution Through Runtime-Generated Stressmarks
EvoWeight: Sponge Poisoning of FPGA-Based DNN Accelerators in Differential Private Secure Federated Learning
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks
Verifying the Authenticity of Chip Designs with the DesignTag System
Mathematical Model of Strong Physically Unclonable Functions Based on Hybrid Boolean Networks
Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow
RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning
Charlie, Charlie, Charlie on Industrial Control Systems: PLC Control Logic Attacks by Design, Not by Chance
Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks
AppSAT: Approximately deobfuscating integrated circuits
Security of SoC firmware load protocols
Layout-level Vulnerability Ranking from Electromagnetic Fault Injection
Structural transformation for best-possible obfuscation of sequential circuits
R2D2: Runtime reassurance and detection of A2 Trojan
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers
HTOutlier: Hardware Trojan detection with side-channel signature outlier identification
One Flip Away from Chaos: Unraveling Single Points of Failure in Quantized DNN s
HOST 2011, Proceedings of the 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 5-6 June 2011, San Diego, California, USA
Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits
Efficient 2nd-order power analysis on masked devices utilizing multiple leakage
On designing optimal camouflaged layouts
In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs
Granularity and detection capability of an adaptive embedded Hardware Trojan detection system
TripletPower: Deep-Learning Side-Channel Attacks over Few Traces
Optimality and beyond: The case of 4×4 S-boxes
Challenging on-chip SRAM security with boot-state statistics
Hardware virtualization for protection against power analysis attack
Novel strong PUF based on nonlinearity of MOSFET subthreshold operation
DOMREP II
VITAMIN: Voltage Inversion Technique to Ascertain Malicious Insertions in ICs
Advanced Covert-Channels in Modern SoCs
Correlation power analysis attack against STT-MRAM based cyptosystems
A Thorough Study of State Leakage Mitigation in Quantum Computing with One-Time Pad
Connecting the dots: Privacy leakage via write-access patterns to the main memory
ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, McLean, VA, USA, May 5-10, 2019
Time Series-Based Malware Detection Using Hardware Performance Counters
CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution
2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014, Arlington, VA, USA, May 6-7, 2014
Termite Attacks: Gnawing on Logs to Extract Secret Information
2016 IEEE Asian Hardware-Oriented Security and Trust, AsianHOST 2016, Yilan, Taiwan, December 19-20, 2016
Diagonal fault analysis of Gr⊘stl in dedicated MAC mode
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Reward-Based Blockchain Infrastructure for 3D Ic Supply Chain Provenance
SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers
TrustGeM: Dynamic trusted environment generation for chip-multiprocessors
A zero-cost approach to detect recycled SoC chips using embedded SRAM
SynCirc: Efficient Synthesis of Depth-Optimized Circuits for Secure Computation
Dynamic Pulse Switching for Protection of Quantum Computation on Untrusted Clouds
Hardware Implementations of Hash Function Luffa
FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets
An enhanced classification-based golden chips-free hardware Trojan detection technique
True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF
Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience
TRRScope: Understanding Target Row Refresh Mechanism for Modern DDR Protection
How secure is split manufacturing in preventing hardware trojan?
A Privacy-Preserving Protocol Level Approach to Prevent Machine Learning Modelling Attacks on PUFs in the Presence of Semi-Honest Verifiers
A novel physiological features-assisted architecture for rapidly distinguishing health problems from hardware Trojan attacks and errors in medical devices
FPGA based trustworthy authentication technique using Physically Unclonable Functions and artificial intelligence
CHESS: Compiling Homomorphic Encryption with Scheme Switching
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL
LightFAt: Mitigating Control-Flow Explosion via Lightweight PMU-Based Control-Flow Attestation
Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results
A Region Based Approach for the Identification of Hardware Trojans
Multiplexing Methods for Power Watermarking
Reconfigurable Physical Unclonable Functions -- Enabling Technology for Tamper-Resistant Storage
Metrics for Assessing Security of System-on-Chip
Inner collisions in ECC: Vulnerabilities of complete addition formulas for NIST curves
3D Bioprinter Firmware Attacks: Categorization, Implementation, and Impacts
SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits
A compact energy-efficient pseudo-static camouflaged logic family
Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs
Value prediction for security (VPsec): Countering fault attacks in modern microprocessors
Encoding Power Traces as Images for Efficient Side-Channel Analysis
Independent detection of recycled flash memory: Challenges and solutions
SecWalk: Protecting Page Table Walks Against Fault Attacks
Micropower: Micro Neural Networks for Side-Channel Attacks
The Butterfly PUF: Protecting IP on every FPGA
A novel method for watermarking sequential circuits
A flexible leakage trace collection setup for arbitrary cryptographic IP cores
Practical Performance of Analog Attack Techniques
Robust keys from physical unclonable functions
Calibratable Polymorphic Temperature Sensor for Detecting Fault Injection and Side-Channel Attacks
An Input Recovery Side-Channel Attack on Dnn Accelerator with Three-Dimensional Power Surface
Evaluating Security Specification Mining for a CISC Architecture
Trained to Leak: Hiding Trojan Side-Channels in Neural Network Weights
A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF
Amplifying Electromagnetic Leakage by Hardware Trojans Through Cable Geometry Manipulation
Hardware implementations of the WG-5 cipher for passive RFID tags
STIQ: Safeguarding Training and Inferencing of Quantum Neural Networks from Untrusted Cloud
LAHEL: Lightweight Attestation Hardening Embedded Devices using Macrocells
Uprooting Trust: Learnings from an Unpatchable Hardware Root-of-Trust Vulnerability in Siemens S7-1500 PLCs
The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes
RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders
Frontside laser fault injection on cryptosystems - Application to the AES' last round -
JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis
Security Checkers: Detecting processor malicious inclusions at runtime
Functional integrated circuit analysis
Dynamic Key Updates for LUT Locked Design
A Post-Quantum Secure Discrete Gaussian Noise Sampler
Fresh re-keying with strong PUFs: A new approach to side-channel security
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family
Eyehearyou: Probing Location Identification Via Occluded Smartphone Cameras and Ultrasound
Local Heating Attacks on Flash Memory Devices
IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2009, San Francisco, CA, USA, July 27, 2009. Proceedings
A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature
RS-Mask: Random Space Masking as an Integrated Countermeasure against Power and Fault Analysis
FHE-Booster: Accelerating Fully Homomorphic Execution with Fine-tuned Bootstrapping Scheduling
Comparison of cost of protection against differential power analysis of selected authenticated ciphers
Complementary IBS: Application specific error correction for PUFs
DOSCrack: Deobfuscation Using Oracle-Guided Symbolic Execution and Clustering of Binary Security Keys
Syndrome: Spectral analysis for anomaly detection on medical IoT and embedded devices
SoCureLLM: An LLM-Driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation
A hierarchical formal approach to verifying side-channel resistant cryptographic processors
Stateless leakage resiliency from NLFSRs
Protecting Indirect Branches Against Fault Attacks Using ARM Pointer Authentication
Traffic Analysis Attacks on Wireless NoC-Based SoCs
An efficient algorithm for identifying security relevant logic and vulnerabilities in RTL designs
Robust Stable Radiometric Fingerprinting for Frequency Reconfigurable Devices
t-Private logic synthesis on FPGAs
Hardware security risk assessment: A case study
Hardware intrinsic security based on SRAM PUFs: Tales from the industry
Preventing fault attack on stream cipher using randomization
Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON
Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments
Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA
On the Impossibility of Approximation-Resilient Circuit Locking
Dynamic Evaluation of Hardware Trust
Security analysis of index-based syndrome coding for PUF-based key generation
At-Speed Delay Characterization for IC Authentication and Trojan Horse Detection
Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing
Functional block identification in circuit design recovery
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS
Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks
Large laser spots and fault sensitivity analysis
Placement of trust anchors in embedded computer systems
Accelerating early design phase differential power analysis using power emulation techniques
Influence of the temperature on true random number generators
Silent Simon: A threshold implementation under 100 slices
A security-aware design scheme for better hardware Trojan detection sensitivity
Safeguarding the Intelligence of Neural Networks with Built-in Light-weight Integrity MArks (LIMA)
Towards the Avoidance of Counterfeit Memory: Identifying the DRAM Origin
A bulk built-in sensor for detection of fault attacks
Temperature-Aware Cooperative Ring Oscillator PUF
Trustworthy System Security through 3-D Integrated Hardware
Wattshield: A Power Side-Channel Framework for Detecting Malicious Firmware in Fused Filament Fabrication
Hardening Hardware Accelerartor Based CNN Inference Phase Against Adversarial Noises
Abstract: Characterizing EEPROM for usage as a ubiquitous PUF source
Side-channel based Watermarks for Integrated Circuits
Place-and-Route Impact on the Security of DPL Designs in FPGAs
Towards Secure Classical-Quantum Systems
A Chaotic Ring oscillator based Random Number Generator
IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings
Experimental evaluation of two software countermeasures against fault attacks
IC Activation and User Authentication for Security-Sensitive Systems
Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions
Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database
Zero-permission acoustic cross-device tracking
Delay model and machine learning exploration of a hardware-embedded delay PUF
Side-channel leakage on silicon substrate of CMOS cryptographic chip
DeepEM: Deep Neural Networks Model Recovery through EM Side-Channel Information Leakage
2017 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2017, McLean, VA, USA, May 1-5, 2017
ReFID: A System-Aware Remote Fault-Injection Attack Detection & Mitigation for Secure Heterogeneous System
Identification and Classification of Corrupted PUF Responses via Machine Learning
Glitch-free implementation of masking in modern FPGAs
Provably Secure Obfuscation of Diverse Watermarks for Sequential Circuits
Low-Entropy Packed Binary Detection via Accurate Hardware Events Profiling
Unified Digit-Serial Multiplier and Inverter in Finite Field GF(2 m )
Masked Memory Primitive for Key Insulated Schemes
Side-Channel Analysis of MAC-Keccak
A Comparison of Neural Networks for PCB Component Segmentation
IP-level implementation of a resistance-based physical unclonable function
Safeguarding Unmanned Aerial Vehicles Against Side Channel Analysis Via Motor Noise Injection
Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller
Hermes: Secure heterogeneous multicore architecture design
CTCG: Charge-trap based camouflaged gates for reverse engineering prevention
STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis
Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption
Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation
MaskedNet: The First Hardware Inference Engine Aiming Power Side-Channel Protection
Abnormal vehicle behavior induced using only fabricated informative CAN messages
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation
iTimed: Cache Attacks on the Apple A10 Fusion SoC
Entropy Extraction in Metastability-based TRNG
Blinded random corruption attacks
Efficient and secure split manufacturing via obfuscated built-in self-authentication
Bits to BNNs: Reconstructing FPGA ML-IP with Joint Bitstream and Side-Channel Analysis
A new approach for root-causing attacks on digital microfluidic devices
PUF-based Secure Test Wrapper Design for Network-on-Chip
Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification
SNOW-SCA: ML-Assisted Side-Channel Attack on SNOW-V
Breaking SCA-Protected CRYSTALS-Kyber with a Single Trace
On charge sensors for FIB attack detection
An adaptable, modular, and autonomous side-channel vulnerability evaluator
Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs
Robust, low-cost, and accurate detection of recycled ICs using digital signatures
A new approach for rowhammer attacks
SCALE: Secure and Scalable Cache Partitioning
Machine Learning Attacks on Challenge-Response Obfuscations in Strong PUFs
Characterising a CPU fault attack model via run-time data analysis
Single-Trace Side-Channel Attacks on ω-Small Polynomial Sampling: With Applications to NTRU, NTRU Prime, and CRYSTALS-DILITHIUM
Pre-processing power traces with a phase-sensitive detector
IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2015, Washington, DC, USA, 5-7 May, 2015
A frequency leakage model for SCA
WiP: Applicability of ISO Standard Side-Channel Leakage Tests to NIST Post-Quantum Cryptography
Current Flattening Circuit for DPA Countermeasure
Low-cost and area-efficient FPGA implementations of lattice-based cryptography
Chosen-Plaintext Attack on Energy-Efficient Hardware Implementation of GIFT-COFB
Cryptographically secure shields
Efficient One-pass Entity Authentication based on ECC for Constrained Devices
A Lightweight Non-Oscillatory Delay-Sensor for Remote Power Analysis
Side-channel Attack Resistant ROM-based AES S-Box
Efficient configurations for block ciphers with unified ENC/DEC paths
On improving reliability of delay based Physically Unclonable Functions under temperature variations
State-of-the-art of Secure ECC Implementations: A Survey on Known Side-channel Attacks and Countermeasures
A new event-driven Dynamic Vision Sensor based Physical Unclonable Function for camera authentication in reactive monitoring system
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs
Countering the effects of silicon aging on SRAM PUFs
Time-Aware Re-Synthesis for Secure Quantum Systems
FPGA-oriented moving target defense against security threats from malicious FPGA tools
Formal Evaluation and Construction of Glitch-resistant Masked Functions
Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs
Sourcing Trust From Peers with Physical Unclonable Functions
Betrayed by Light: How Photon Emission Microscopy Empowers Register Bit-Level Laser Attacks on Microcontrollers
Robust hardware true random number generators using DRAM remanence effects
Hardware/Software Obfuscation against Timing Side-channel Attack on a GPU
Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs
A practical DPA on Grain v1 using LS-SVM
Security challenges and opportunities in adaptive and reconfigurable hardware
Cache Wars: A Comparative Study of UMWAIT, UMONITOR, and Prime-Probe Attacks
On secure implementations of quantum-resistant supersingular isogeny Diffie-Hellman
Low-cost recovery for the code integrity protection in secure embedded processors
Latch-Based Logic Locking
Practical evaluation of DPA countermeasures on reconfigurable hardware
LEDA: Locking Enabled Differential Analysis of Cryptographic Circuits
Resurrection Attack: Defeating Xilinx MPU's Memory Protection
Security Properties Driven Pre-Silicon Laser Fault Injection Assessment
Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors
Statistical Ineffective Fault Analysis of GIMLI
WordRev: Finding word-level structures in a sea of bit-level gates
Structural Analysis Attack on Sequential Circuit Logic Locking
HSDL: A Security Development Lifecycle for hardware technologies
Using Undervolting as an on-Device Defense Against Adversarial Machine Learning Attacks
GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units
Improved algebraic side-channel attack on AES
Chaos computing for mitigating side channel attack
Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters
Design of Quantum Computer Antivirus
Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals
A separation and protection scheme for on-chip memory blocks in FPGAs
Detecting Continuous Jamming Attack using Ultra-low Power RSSI Circuit
A Hardware-Assisted Data Hiding Based Approach in Building High-Performance Trusted Computing Systems
Systematic security evaluation method against C safe-error attacks
Bit selection algorithm suitable for high-volume production of SRAM-PUF
The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions
High efficiency power side-channel attack immunity using noise injection in attenuated signature domain
An ultra-low overhead LUT-based PUF for FPGA
Power analysis of the t-private logic style for FPGAs
A Low-Randomness First-Order Masked Xoodyak
High Precision Laser Fault Injection using Low-cost Components
Sneak path enabled authentication for memristive crossbar memories
Reviving instruction set randomization
2012 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2012, San Francisco, CA, USA, June 3-4, 2012
Echeloned IJTAG data protection
Dual-Leak: Deep Unsupervised Active Learning for Cross-Device Profiled Side-Channel Leakage Analysis
Aging attacks for key extraction on permutation-based obfuscation
ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
Low-Latency Masking with Arbitrary Protection Order Based on Click Elements
Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells
Template Attacks against ECC: practical implementation against Curve25519
BISA: Built-in self-authentication for preventing hardware Trojan insertion
A secure camouflaged threshold voltage defined logic family
Ag conductive bridge RAMs for physical unclonable functions
A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style
Resilient hardware Trojans detection based on path delay measurements
Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure
Robust privacy-preserving fingerprint authentication
VPP: Privacy Preserving Machine Learning via Undervolting
Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology
Fast Fingerprinting of Cloud-based NISQ Quantum Computers
Code Encryption for Confidentiality and Execution Integrity Down to Control Signals
Towards a Semantic Representation for Functional Software Requirements
An Extended Knowledge Representation Learning Approach for Context-Based Traceability Link Recovery: Extended Abstract
TT-RecS: The Taxonomic Trace Recommender System
Towards Improved Network Security Requirements and Policy: Domain-Specific Completeness Analysis via Topic Modeling
SENET: A Semantic Web for Supporting Automation of Software Engineering Tasks
Towards Requirements Specification for Machine-learned Perception Based on Human Performance
7th IEEE International Workshop on Artificial Intelligence for Requirements Engineering, AIRE@RE 2020, Zurich, Switzerland, September 1, 2020
Traceability Network Analysis: A Case Study of Links in Issue Tracking Systems
Message from the Organizers
Faulty Requirements Made Valuable: On the Role of Data Quality in Deep Learning
Towards an Extended Requirements Problem Formulation for Superintelligence Safety
Analysis of Compatibility in Open Source Android Mobile Apps
Identification and Classification of Architecturally Significant Functional Requirements
Topic Modeling on User Stories using Word Mover's Distance
CEREC: Causality Extraction from Requirements Artifacts
Does Link Prediction Help Find Feature Interactions in Software Product Lines?
A Novel Elbow Pneumatic Muscle Actuator for Exoskeleton Arm in Post-Stroke Rehabilitation
Fabrication and Characterization of I-cord Knitted SMA Actuators
Hybrid Soft-Rigid Continuum Robot Inspired by Spider Monkey Tail
Nonlinearity Compensation in A Multi-DoF Shoulder Sensing Exosuit For Real-Time Teleoperation
RISO: Combining Rigid Grippers with Soft Switchable Adhesives
Variable stiffness and shape prosthetic socket based on layer jamming technology
Hierarchical Performance-Based Design Optimization Framework for Soft Grippers
Design of Pneumatic Origami Muscle Actuators (POMAs) for A Soft Robotic Hand Orthosis for Grasping Assistance
Resistance-based self-sensing system of active self-melting bolt towards autonomous healing structure
Automated Fiber Embedding for Tailoring Mechanical and Functional Properties of Soft Robot Components
Kinematic Modeling and Self-Sensing of a Shape Memory Alloy Wire-Driven Continuum Robot
Dimension Optimization of Pneumatically Actuated Soft Continuum Manipulators
VBAMS: Vision-Based Sensing for Estimating and Controlling Shrinkage Ratios in McKibben Artificial Muscles
Soft Robotics for Space Applications: Towards a Family of Locomotion Platforms
Towards vision-based robotic skins: a data-driven, multi-camera tactile sensor