yusuke1997/dblp-id-title huggingface dataset:
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms
PFCG: Improving the Restore Performance of Package Datasets in Deduplication Systems
A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLS
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Optimal Logic Blocks for FPGAs, using Factorial Design Techniques
Implementing Caches in a 3D Technology for High Performance Processors
A Focused Garbage Collection Approach for Primary Deduplicated Storage with Low Memory Overhead
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor
NSC's Digital Answering Machine Solution
Transforming Natural Language Specifications to Logical Forms for Hardware Verification
Architectural Performance Verification: PowerPC TM Processors
A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
Cyclic Beneš Network Based Logic Encryption for Mitigating SAT-Based Attacks
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns
Fast Differential Fault Simulation by Dynamic Fault Ordering
RCTP: Region Correlated Temporal Prefetcher
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
ActiveOS: Virtualizing Intelligent Memory
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits
Transition Recovery Attack on Embedded State Machines Using Power Analysis
A spectral transform approach to stochastic circuits
Pseudo-Sim: An Accurate Analytical Modeling Framework for Systolic Array Architectures
Compiler-directed leakage reduction in embedded microprocessors
Reducing dTLB Energy Through Dynamic Resizing
PS4: A Low Power SNN Accelerator with Spike Speculative Scheme
The bus interface and paging units of the i860TM microprocessor
Improving inclusive cache performance with two-level eviction priority
AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System
Pattern-restricted design at 10nm and beyond
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
A novel software-based defect-tolerance approach for application-specific embedded systems
EdgeNAS: Discovering Efficient Neural Architectures for Edge Systems
Emulation verification of the Motorola 68060
Low Power Design Methodologies for Mobile Communication
Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems
An IBM second generation RISC processor architecture
Dynamic phase-based tuning for embedded systems using phase distance mapping
Reconfigurable CAM Architecture for Network Search Engines
A global floorplanning technique for VLSI layout
CacheTrimmer: Adaptive Cache File Trimming for Optimized Performance and Lifetime on Mobile Devices
Exploring early and late ALUs for single-issue in-order pipelines
Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications
Quality Transition Fault Tests Suitable for Small Delay Defects
FSM Anomaly Detection Using Formal Analysis
Selected inversion for vectorless power grid verification by exploiting locality
Power and performance characterization, analysis and tuning for energy-efficient edge detection on atom and ARM based platforms
Issue system protection mechanisms
Prioritizing verification via value-based correctness criticality
A comparison of two digit serial VLSI adders
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
BDR: A Balanced Data Redistribution scheme to accelerate the scaling process of XOR-based Triple Disk Failure Tolerant arrays
Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning
Selecting critical implications with set-covering formulation for SAT-based Bounded Model Checking
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
Modeling the Difficulty of Sequential Automatic Test Pattern Generation
An Efficient Twin-Precision Multiplier
ES4D: Accelerating Exact Similarity Search for High-Dimensional Vectors via Vector Slicing and In-SSD Computation
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction
Statistical Analysis Driven Synthesis of Asynchronous Systems
Issues in the test of artificial neural networks
A Standard-Cell Placement Tool for Designs with High Row Utilization
Exploring static and dynamic flash-based FPGA design topologies
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits
A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface
Synthesis of 3D Asynchronous State Machines
Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level Cache
A Data-Driven Architecture for Distributed Parallel Processing
Design of TSC checkers for implementation in CMOS technology
A Split Data Cache for Superscalar Processors
Compiler-based approach to reducing leakage energy of instruction scratch-pad memories
Mitigating NBTI in the physical register file through stress prediction
Circuit technologies for BiCMOS VLSI's as computer elements
Tradeoffs in Canonical Sequential Function Representations
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels
Energy aware routing of multi-level Network-on-Chip traffic
A High-Performance Hardware-Efficient Memory Allocation Technique and Design
The Role of Prime Compatibles in the Minimization of Finite State Machines
TermiNETor: Early Convolution Termination for Efficient Deep Neural Networks
Architectural Adaptation for Application-Specific Locality Optimization
PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks
Testability driven synthesis of interacting finite state machines
A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-III
SST: Symbolic Subordinate Threading
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk
PIM-SUM: Fast and Reliable In-Memory Summation for Recommendation Systems
Variable reduction in MOS timing models
Read Error Resilient MLC STT-MRAM Based Last Level Cache
Simultaneous continual flow pipeline architecture
Transmission Line Clock Driver
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction
Structured ASICs: Opportunities and Challenges
Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits
An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures
Efficient Methods for SoC Trust Validation Using Information Flow Verification
Agile Design Flow for Cryptographic Hardware Accelerators
Design of the Intel Pentium TM Processor
Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths
An Intelligent I-Cache Prefetch Mechanism
Speculative path power estimation using trace-driven simulations during high-level design phase
WHOLE: A low energy I-Cache with separate way history
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset
Hardware Efficient Multiplier Design Using an Optimal Mix of Approximate Booth Encodings
Design Verfication and Reachability Analysis Using Algebraic Manipulation
A parallel algorithm for constructing binary decision diagrams
Multiple Fault Diagnosis Using n-Detection Tests
Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects
Memory Bank Predictors
A Compressed and Accurate Sparse Deep Learning-based Workload-Aware Timing Error Model
Noise-based algorithms for functional equivalence and tautology checking
An Efficient Logic Emulation System
A modular VLSI architecture for coincidence detection in positron emission tomography
ProactiveDRAM: A DRAM-initiated retention management scheme
Extension of a transistor level digital timing simulator to include first order analog behavior
Practical use of transition mode delay to solve the problems of floating mode delay under highly correlated input streams
Resilient, UAV-embedded real-time computing
Runtime multi-optimizations for energy efficient on-chip interconnections1
Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel
On mismatch number distribution of nanocrossbar logic mapping
The Architecture of the LR33020 GraphX Processor: A MIPS-RISC Based X-Terminal Controller
Verification of a subtractive radix-2 square root algorithm and implementation
The design of a reduced ambient temperature, air cooled supercomputer
Reinforce Memory Error Protection by Breaking DRAM Disturbance Correlation Within ECC Words
Performance-driven board-level routing for FPGA-based logic emulation
Efficient Function Approximation for Embedded and ASIC Applications
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
Accelerating search and recognition with a TCAM functional unit
Towards finding path delay fault tests with high test efficiency using ZBDDs
Thermal Design of an Advanced Multichip Module for a RISC Processor
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells
Hamming count-a compaction testing technique
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization
Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
Computing-in-Memory Dataflow for Minimal Buffer Traffic
A Scalable High-Performance DMA Architecture for DSP Applications
Using M/G/l queueing models with vacations to analyze virtualized logic computations
A co-processor with supercomputer capabilities for personal computers
Hard Disk Controller: The Disk Drive's Brain and Body
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan
Integration of correct-by-construction BIP models into the MetroII design space exploration flow
DCR: Decomposition-Aware Column Re-Mapping for Stuck-At-Fault Tolerance in ReRAM Arrays
On State Assignment of Finite State Machines Using Hypercube Embedding Approach
A Memory Controller with an Integrated Graphics Processor
Can Trace-Driven Simulators Accurately Predict Superscalar Performance?
Performance monitoring on the PowerPC 604 microprocessor
Effective Optimization of Branch Predictors through Lightweight Simulation
Logic Optimization with Multi-Output Gates
Rapid early-stage microarchitecture design using predictive models
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine
A Systolic Architecture for High Speed Pipelined Memories
Fast Specification of Cycle-accurate Processor Models
An Architectural Power Estimator for Analog-to-Digital Converters
Hardware/software co-verification, an IP vendors viewpoint
A robust pulsed flip-flop and its use in enhanced scan design
AS/400 PowerPC TM Compatible Semi-Custom Technology
AirGun: Adaptive Granularity Quantization for Accelerating Large Language Models
High throughput reconstruction of Huffman-coded images
Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem
Design of an Online Surface Code Decoder Using Union-Find Algorithm
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications
Exploiting SIMD extensions for linear image processing with OpenCL
PLA based finite state machines using Johnson counters as state memories
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
Automatic VHDL restructuring for RTL synthesis optimization and testability improvement
How logic masking can improve path delay analysis for Hardware Trojan detection
Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash Memory
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits
Special Session: Approximate TinyML Systems: Full System Approximations for Extreme Energy-Efficiency in Intelligent Edge Devices
Prototyping a hybrid main memory using a virtual machine monitor
An efficient gate delay model for VLSI design
Using variable clocking to reduce leakage in synchronous circuits
FM-P2L: An Algorithm Hardware Co-design of Fixed-Point MSBs with Power-of-2 LSBs in CNN Accelerators
RTOS-aware modeling of embedded hardware/software systems
Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching
A theory of Error-Rate Testing
Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory Machines
Generation of high speed CMOS multiplier-accumulators
Minimization of multioutput TANT networks for unlimited fan-in network model
Distributed Binary Decision Diagrams for Verification of Large Circuit
Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency
Equivalence checking for compiler transformations in behavioral synthesis
Processor design using path programmable logic
A Multi-Schedule Approach to High-Level Synthesis
Performance estimation for real-time distributed embedded systems
Identification of Viable Paths Using Binary Decision Diagrams
Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems
Comparison of chip crossing delay in various packaging environments
Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification
Logic simplification by minterm complement for error tolerant application
Versioning and Concurrency Control in a Distributed Design Environment
A Buffer and Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm
Analysis of Row Hammer Attack on STTRAM
Formal verification of state-machines using higher-order logic
Optimization for automatic cell assembly
Oblivious routing design for mesh networks to achieve a new worst-case throughput bound
Multi-core data streaming architecture for ray tracing
Two-level ata prefetching
42nd IEEE International Conference on Computer Design, ICCD 2024, Milan, Italy, November 18-20, 2024
Optimal power/performance pipelining for error resilient processors
ColSpace: Towards algorithm/implementation co-optimization
Identification of Single Gate Delay Fault Redundancies
New ideas on symbolic manipulations of finite state machines
Digital magnetic recording systems
A high performance CMOS chipset for FFT processors
A design environment for high performance VLSI signal processing
Algorithms for CPU and DRAM DVFS under inefficiency constraints
Exploring multiple sleep modes in on/off based energy efficient HPC networks
Chip clustering with mutual information on multiple clock tests and its application to yield tuning
Architectural Impact of Secure Socket Layer on Internet Servers
How Multi-Threshold Designs Can Protect Analog IPs
AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based Cache Attacks on ARM-FPGA Embedded SoC
FPGA global routing based on a new congestion metric
Hybridizing and Coalescing Load Value Predictors
Testability Analysis for Test Generation in Synchronous Sequential Circuits
Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor
PEAS-III: An ASIP Design Environment
Multimodal query support in database servers
Test cost minimization through adaptive test development
High-radix SRT division with speculation of quotient digits
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations
TDM: Time and Distance Metric for Quantifying Information Leakage Vulnerabilities in SoCs
Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams
Blue team red team approach to hardware trust assessment
Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads
Enhancing Key-Recovery Chosen-Ciphertext Side-Channel Attacks on NTRU Using LDPC
Read-Optimized Persistent Hash Index for Query Acceleration through Fingerprint Filtering and Lock-Free Prefetching
Optimal variable ordering in ZBDD-based path representations for directed acyclic graphs
On-Chip Voltage and Temperature Digital Sensor for Security, Reliability, and Portability
A Framework for Energy Estimation of VLIW Architecture
In-depth Testing of x86 Instruction Disassemblers with Feedback Controlled DFS Algorithm
A Low Power Highly Associative Cache for Embedded Systems
IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022
Scalable memory fabric for silicon interposer-based multi-core systems
A Synthesis Algorithm for Two-Level XOR Based Circuits
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals
Design of a high-speed arithmetic datapath
A self-timed real-time sorting network
Architectural impact of secure socket layer on Internet servers: A retrospect
A Shingle-Aware Persistent Cache Management Scheme for DM-SMR Disks
A control-theoretic energy management for fault-tolerant hard real-time systems
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation
Power-capped DVFS and thread allocation with ANN models on modern NUMA systems
FastMatch: Enhancing Data Pipeline Efficiency for Accelerated Distributed Training
A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design
39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021
FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Covert Data Exfiltration Using Light and Power Channels
Hierarchical modeling of Phase Change memory for reliable design
Synthesis of Pseudo Kronecker Lattice Diagrams
SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache
Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment
Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on?
Tracing the Logic: Evaluating LLM Reasoning Paths in RTL Generation
Precise exception support for decoupled run-time monitoring architectures
Oak: A Fault-Tolerant Shared-Memory System Atop Memory-Semantic Fabrics
A general-purpose video signal processor: architecture and programming
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits
GPU acceleration for PCA-based statistical static timing analysis
An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems
Frigg: a simulation environment for multiple-processor DSP system development
Special Session: Impact of Noise on Quantum Algorithms in Noisy Intermediate-Scale Quantum Systems
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach
Flipping Bits to Share Crossbars in ReRAM-Based DNN Accelerator
A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor
MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces
Dynamic Optimization of Battery Health in IoT Networks
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs
Exploring the energy efficiency of Multispeculative Adders
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core
SmartNetSSD: Exploiting Path Resources for Read Performance Improvement in Network-Based SSDs
Runtime adaptable concurrent error detection for linear digital systems
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug
Cluster-level simultaneous multithreading for VLIW processors
Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence
Design and test strategies for microarchitectural post-fabrication tuning
32-Bit Architectures for Embedded Systems
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy
Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance
Static race verification for networks with reconvergent clocks
APE-FV: Concolic Testing for RTL Functional Verification Using Adaptive Path Exploration
A novel hardware hash unit design for modern microprocessors
Data compression for thermal mitigation in the Hybrid Memory Cube
Ebird: Elastic Batch for Improving Responsiveness and Throughput of Deep Learning Services
Analysis of conditional resource sharing using a guard-based control representation
State Set Management for SAT-based Unbounded Model Checking
Write-aware random page initialization for non-volatile memory systems
Correctness verification of VLSI modules supported by a very efficient Boolean prover
Intra-vector SIMD instructions for core specialization
Testability of digital circuits via the spectral domain
In-field NoC-based SoC testing with distributed test vector storage
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
Best of Both Latency and Throughput
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures
Alleviating Transfer Latency in DataFlow Accelerator for DSP Applications
Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL Environment
Configurable rectilinear Steiner tree construction for SoC and nano technologies
Custom rotary clock router
Incremental Synthesis for Engineering Changes
Very Low Voltage (VLV) Design
Adaptive online testing for efficient hard fault detection
The Structured Logic CAD Suite Used on the DPS7000 System
A Distributed Computation Platform for Wireless Embedded Sensing
Modeling and simulation of coupled lossy lines for VLSI interconnections
New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead
File System Interfaces for Embedded Software Development
Reducing leakage power in peripheral circuits of L2 caches
A proposed standard test bus and boundary scan architecture
DIPLOMA: Consistent and coherent shared memory over mobile phones
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications
SATL: A Spatial Architecture Rapid Prototyping Framework for Irregular Applications Acceleration
Accurate interconnect modeling for high frequency LSI/VLSI circuits and systems
Reducing Compilation Time Overhead in Compiled Simulators
Wavefront array processor for video applications
System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software Decomposition
Improving Processor Performance by Simplifying and Bypassing Trivial Computations
Software pipelining of dataflow programs with dynamic constructs on multi-core processor
Hardware Trojans: The defense and attack of integrated circuits
A parallel Steiner tree heuristic for macro cell routing
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture
DART: delay and routability driven technology mapping for LUT based FPGAs