yusuke1997/dblp-id-title huggingface dataset:
Local Search for Boolean Relations on the Basis of Unit Propagation
An On-board Algorithm Implementation on an Embedded GPU: A Space Case Study
A 50 Mbit/s Iterative Turbo-Decoder
A methodology for designing continuous-time sigma-delta modulators
CMOS Combinational Circuit Sizing by Stage-wise Tapering
High-Level Synthesis of Benevolent Trojans
MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers
Scaling up Network Centrality Computations *
Interconnect Tuning Strategies for High-Performance Ics
Search Space Reduction for E/E-Architecture Partitioning
Interactive presentation: A coefficient optimization and architecture selection tool for SigmaDelta modulators in MATLAB
Memory centric thread synchronization on platform FPGAs
A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits
Sensor-wise methodology to face NBTI stress of NoC buffers
A Read Latency Variation Aware Independent Read Scheme for QLC SSDs
mDTM: Multi-objective dynamic thermal management for on-chip systems
ChipVQA: Benchmarking Visual Language Models for Chip Design
MINIME-validator: Validating hardware with synthetic parallel testcases
Self-Secured Control with Anomaly Detection and Recovery in Automotive Cyber-Physical Systems
Eliminating data invalidation in debugging multiple-clock chips
A Low-Complexity Framework for Distributed Energy Market Targeting Smart-Grid
Hidden Cost of Circuit Design with RFETs
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication
Remote Sensing with UAV and Mobile Recharging Vehicle Rendezvous
Alleviating Barren Plateaus in Parameterized Quantum Machine Learning Circuits: Investigating Advanced Parameter Initialization Strategies
A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks
Efficient SAT-Based Bounded Model Checking of Evolving Systems
Topology identification for smart cells in modular batteries
Phalanx: Failure-Resilient Truck Platooning System
ATPG Tools for Delay Faults at the Functional Level
12 mJ Per Class On-Device Online Few-Shot Class-Incremental Learning
Design of safety critical systems by refinement
Describing instruction set processors using nML
MeSAP: A fast analytic power model for DRAM memories
Completeness in SMT-based BMC for Software Programs
ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification
Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks
Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks
Architecture and optimal configuration of a real-time multi-channel memory controller
Design of low energy, high performance synchronous and asynchronous 64-point FFT
Future of GPGPU micro-architectural parameters
From algorithm to first 3.5G call in record time: a novel system design approach based on virtual prototyping and its consequences for interdisciplinary system design teams
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
A two-tone test method for continuous-time adaptive equalizers
Adaptive Vehicle Detection for Real-time Autonomous Driving System
From UML/SysML to Matlab/Simulink: current state and future perspectives
Practical ILP-based routing of standard cells
An ILP formulation for task mapping and scheduling on multi-core architectures
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
Simulation platform for UHF RFID
EF-IMR: Embedded Flash with Interlaced Magnetic Recording Technology
Statistical thermal modeling and optimization considering leakage power variations
Software Components for Reliable Automotive Systems
A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems
Efficient verification of multi-property designs (The benefit of wrong assumptions)
Tuning dynamic data flow analysis to support design understanding
Monte-Carlo approach for power estimation in sequential circuits
3DFAR: A three-dimensional fabric for reliable multi-core processors
ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM
Scheduling Reusable Instructions for Power Reduction
A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications
Global Optimization Applied to the Oscillator Problem
Sigma-delta testability for pipeline A/D converters
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits
Transmitting TLM transactions over analogue wire models
A unified scheduling model for high-level synthesis and code generation
Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCs
Random Jitter Extraction Technique in a Multi-Gigahertz Signal
Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC
Deep Reinforcement Learning for Analog Circuit Structure Synthesis
Aspects of Formal and Graphical Design of a Bus System
SigNet: Network-on-chip filtering for coarse vector directories
Generalized Recognition of Gates: A VLSI Abstraction Tool
Reducing the energy cost of computing through efficient co-scheduling of parallel workloads
Analyzing timing uncertainty in mesh-based clock architectures
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits
Efficiency-driven Hardware Optimization for Adversarially Robust Neural Networks
Robust Human Activity Recognition Using Generative Adversarial Imputation Networks
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip
X-PIM: Fast Modeling and Validation Framework for Mixed-Signal Processing-in-Memory Using Compressed Equivalent Model in System Verilog
HPAZ: A high-throughput pipeline architecture of ZUC in hardware
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators
Generation of minimal size code for scheduling graphs
On passivity of the super node algorithm for EM modeling of interconnect systems
URECA: Unified register file for CGRAs
Multi-core fixed-priority scheduling of real-time tasks with statistical deadline guarantee
Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks
Hardware-Assisted Control-Flow Integrity Enhancement for IoT Devices
Extending the lifetime of NVMs with compression
Tutorial Statement
Co-Design of Topology, Scheduling, and Path Planning in Automated Warehouses
Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic
An Application-Specific Design Methodology for STbus Crossbar Generation
Electrothermal simulation of bonding wire degradation under uncertain geometries
Adaptive reduction of the frequency search space for multi-vdd digital circuits
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A Framework for Battery-Aware Sensor Management
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
An efficient framework for passive compact dynamical modeling of multiport linear systems
Real-time Private Membership Test using Homomorphic Encryption
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits
AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips
Improving performance by monitoring while maintaining worst-case guarantees
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern
Mixed wire and surface-wave communication fabrics for decentralized on-chip multicasting
Compact modeling of carbon nanotube thin film transistors for flexible circuit design
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis
How to speed-up your NLFSR-based stream cipher
Rate-adaptive tasks: Model, analysis, and design issues
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models
Effective Low Power BIST for Datapaths
Automatic microarchitectural pipelining
Optimizing sequential cycles through Shannon decomposition and retiming
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Parallel transistor level full-chip circuit simulation
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors
A Compaction Method for STLs for GPU in-field test
Lazy Pipelines: Enhancing quality in approximate computing
On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models
Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms
Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence
Decomposition of Extended Finite State Machine for Low Power Design
Coherence based message prediction for optically interconnected chip multiprocessors
Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception
Uniformly-Switching Logic for Cryptographic Hardware
Solving DQBF through quantifier elimination
An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping
A Circuit SAT Solver With Signal Correlation Guided Learning
An active vision system for fall detection and posture recognition in elderly healthcare
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
VM-aware Flush Mechanism for Mitigating Inter-VM I/O Interference
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies
Modeling and design exploration of FBDRAM as on-chip memory
GPU-accelerated small delay fault simulation
Nanoelectronics challenges for the 21 st century
Timing-Predictable Vision Processing for Autonomous Systems
Accelerating Oblivious Transfer with a Pipelined Architecture
Scalable Scan-Chain-Based Extraction of Neural Network Models
Design space exploration of partially re-configurable embedded processors
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
Collapsing the Transistor Chain to an Effective Single Equivalent Transistor
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
Reliable Interval Prediction of Minimum Operating Voltage Based on On-Chip Monitors via Conformalized Quantile Regression
Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions
An integrated open framework for heterogeneous MPSoC design space exploration
Verification-guided voter minimization in triple-modular redundant circuits
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic
Understanding the impact of precision quantization on the accuracy and energy of neural networks
Defect Aware Test Patterns
Optimal regulation of traffic flows in networks-on-chip
On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
Locality-Aware Data Placement for NUMA Architectures: Data Decoupling and Asynchronous Replication
High Throughput Hardware Accelerated CoreSight Trace Decoding
Embedded System Design Based On Webservices
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
An Efficient Heuristic Approach to Solve the Unate Covering Problem
Annotated data types for addressed token passing networks
The METASAT Model-Based Engineering Workflow and Digital Twin Concept
Continuous GNN-Based Anomaly Detection on Edge Using Efficient Adaptive Knowledge Graph Learning
On improving genetic optimization based test generation
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance
Automatic generation of hardware checkers from formal micro-architectural specifications
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems
System Verilog for VHDL Users
Data Center Demand Response for Sustainable Computing: Myth or Opportunity?
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Fast Machine Learning Based Prediction for Temperature Simulation Using Compact Models
Wireless innovations for smartphones
A method for the estimation of defect detection probability of analog/RF defect-oriented tests
Model-based energy optimization of automotive control systems
Motivating the Use of Machine-Learning for Improving Timing Behaviour of Embedded Mixed-Criticality Systems
Static power side-channel analysis of a threshold implementation prototype chip
Low power synthesis of dynamic logic circuits using fine-grained clock gating
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
Low-voltage low-power switched-current circuits and systems
Concurrent core test for SOC using shared test set and scan chain disable
PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks
Embedded Robustness Ips
Fast and efficient lagrangian relaxation-based discrete gate sizing
Behavioural Bitwise Scheduling Based on Computational Effort Balancing
Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis
A new quality estimation methodology for mixed-signal and analogue ICs
Automotive Electronics - A Challenge For Systems Engineering
Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications
Compiling Permutations for Superconducting QPUs
Power Aware Interface Synthesis for Bus-Based SoC Design
Extracting useful computation from error-prone processors for streaming applications
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Exploiting narrow-width values for thermal-aware register file designs
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines
Physical Architectures of Automotive Systems
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
Priority-Preserving Optimization of Status Quo ID-Assignments in Controller Area Network
Pseudo-CMOS: A novel design style for flexible electronics
Improving the accuracy of the leakage power estimation of embedded CPUs
Post-deployment trust evaluation in wireless cryptographic ICs
HFL: Hardware Fuzzing Loop with Reinforcement Learning
A fast, source-synchronous ring-based network-on-chip design
RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems
Search-Based SAT Using Zero-Suppressed BDDs
Automatic generation of custom SIMD instructions for Superword Level Parallelism
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission
A design flow for configurable embedded processors based on optimized instruction set extension synthesis
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks
Behavioral synthesis with systemC
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems
Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN
Hardware virtualization support for shared resources in mixed-criticality multicore systems
PM-COSYN: PE and memory co-synthesis for MPSoCs
A clock-gating based capture power droop reduction methodology for at-speed scan testing
Heterogeneous behavioral hierarchy for system level designs
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
An Isotropic Shift-Pointwise Network for Crossbar-Efficient Neural Network Design
EVOLVE: Towards Converging Big-Data, High-Performance and Cloud-Computing Worlds
Analytical model for TDDB-based performance degradation in combinational logic
AMSA: Adaptive Merkle Signature Architecture
Cognitive Sensing for Energy-Efficient Edge Intelligence
Timing analysis of cyber-physical applications for hybrid communication protocols
A general method to make multi-clock system deterministic
A new sampling technique for Monte Carlo-based statistical circuit analysis
On reset based functional broadside tests
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design
Unsupervised Test-Time Adaptation of Deep Neural Networks at the Edge: A Case Study
A methodology for improving software design lifecycle in embedded control systems
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training
A Synthesis Procedure for Flexible Logic Functions
IPSIM: SystemC 3.0 Enhancements for Communication Refinement
Interactive presentation: A middleware-centric design flow for networked embedded systems
Monolithically stackable hybrid FPGA
Gradient Approximation of Approximate Multipliers for High-Accuracy Deep Neural Network Retraining
Memristor technology in future electronic system design
LAC: Learned Approximate Computing
C2C: A Framework for Critical Token Classification in Transformer-Based Inference Systems
Berger code-based concurrent error detection in asynchronous burst-mode machines
NeuronFlow: a neuromorphic processor architecture for Live AI applications
Rebooting Our Computing Models
Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache
Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components
Post Silicon Validation of the MMU
Coherent crosstalk noise analyses in ring-based optical interconnects
A reconfiguration approach for fault-tolerant FlexRay networks
A high performance reconfigurable Motion Estimation hardware architecture
Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation
Automated Synthesis of Assertion Monitors using Visual Specifications
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits
A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations
Two-way partitioning based on direction vector [layout design]
Cross entropy minimization for efficient estimation of SRAM failure rate
BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0
A low complexity heuristic for design of custom network-on-chip architectures
Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit
Reducing Multi-Valued Algebraic Operations to Binary
Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image Recognition
Systolic like soft-detection architecture for 4×4 64-QAM MIMO system
Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform
Time-decoupled parallel SystemC simulation
Layout-aware gate duplication and buffer insertion
Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping"
Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips
Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation
A resilient architecture for low latency communication in shared-L1 processor clusters
Thermal Sensing Using Micro-ring Resonators in Optical Network-on-Chip
A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis
ChiselFV: A Formal Verification Framework for Chisel
Performance Considerations for an Embedded Implementation of OMA DRM 2
Testing RF circuits with true non-intrusive built-in sensors
Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators
Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network Encoding
Optimized selection of reliable and cost-effective cyber-physical system architectures
Physically-Aware N-Detect Test Pattern Selection
SLIF: a specification-level intermediate format for system design
Improving Software Reliability with Rust: Implementation for Enhanced Control Flow Checking Methods
Optimal energy management and recovery for FEV
Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
Concurrent and Selective Logic Extraction with Timing Consideration
An open reconfigurable research platform as stepping stone to exascale high-performance computing
Online Learning for Dynamic Structural Characterization in Electron Energy Loss Spectroscopy
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms
CycPUF: Cyclic Physical Unclonable Function
Thermal- and Cache-Aware Resource Management based on ML- Driven Cache Contention Prediction
Timing-Driven Detailed Placement with Unsupervised Graph Learning
Fast and accurate cache modeling in source-level simulation of embedded software
RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation
Towards Non-intrusive Malware Detection for Industrial Control Systems
Uncertainty-aware reliability analysis and optimization
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment
Efficient link capacity and QoS design for network-on-chip
Nonlinear model order reduction using remainder functions
Duetto: Latency Guarantees at Minimal Performance Cost
Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs
Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors
Automatic operating point distillation for hybrid mapping methodologies
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
A Novel Neuromorphic Processors Realization of Spiking Deep Reinforcement Learning for Portfolio Management
Boosting: Min-Cut Placement with Improved Signal Delay
Energy-efficient branch prediction with Compiler-guided History Stack
Modular code generation for emulating the electrical conduction system of the human heart
Enabling concurrent clock and power gating in an industrial design flow
Design Automation for Organs-on-Chip
Symbiotic Safety: Safe and Efficient Human-Machine Collaboration by utilizing Rules
Introducing new verification methods into a company's design flow: an industrial user's point of view
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures
PCFI: Program Counter Guided Fault Injection for Accelerating GPU Reliability Assessment