yusuke1997/dblp-id-title huggingface dataset:
Towards the least complex time-multiplexed constant multiplication
Low Power Network-on-Chip Architecture Design Technique
The multi-channel small signal readout system for THz spectroscopy and imaging applications
Formal Analysis of Physically Unclonable Functions
Circuit performance optimization for local intra-die process variations using a gate selection metric
A real-time 720p feature extraction core based on Semantic Kernels Binarized
High-Throughput Montgomery Modular Multiplication
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File
A novel non-minimal turn model for highly adaptive routing in 2D NoCs
Graph based fault model definition for bus testing
OCAPI: A Prototype for High Precision Arithmetic
A micropipelined ARM
Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture
Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs
Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy
Run Time Power and Accuracy Management with Approximate Circuits
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory
A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid
Rate-based scheduling policy for QoS flows in networks on chip
Low cost FPGA design and implementation of a stereo matching system for 3D-TV applications
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)
Network-on-Chip multicasting with low latency path setup
Architectural synthesis of DSP circuits under simultaneous error and time constraints
ZaLoBI: Zero avoiding Load Balanced Inference accelerator
Trace Buffer Attack: Security versus observability study in post-silicon debug
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips
A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging
Energy Efficient and Reliable System Design
Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies
Variation-Aware, Library Compatible Delay Modeling Strategy
Memory and Energy Efficient Method Toward Sparse Neural Network Using LFSR Indexing
Self-test method and recovery mechanism for high frequency TSV array
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers
In-Place Storage of Path Metrics in Viterbi Decoders
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST
A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Exploring area and total wirelength using a cell merging technique
Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints
An Over-the-Cell Channel Router
PA-PUF: A Novel Priority Arbiter PUF
∑-Δ based force-feedback capacitive micro-machined sensors: Extending the input signal range
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device
Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing
VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion
Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication
A general statistical estimation for application mapping in Network-on-Chip
Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits
VLSI-SoC: Forward-Looking Trends in IC and Systems Design - 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010, Madrid, Spain, September 27-29, 2010, Revised Selected Papers
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology
A time-window based approach for dynamic assertions mining on control signals
Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers
Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interface
Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques
A Hardware-based Framework for Secure Firmware Updates on Embedded Systems
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors
Debugging Methods Through Identification of Appropriate Functions for Internal Gates
Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication
Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories
Two Combinatorial Problems on the Layout of Switching Lattices
Memristive devices for computing: Beyond CMOS and beyond von Neumann
A Digital Event-Based Strategy for ASK demodulation
Defragmentation Algorithms for Partially Reconfigurable Hardware
A framework to accelerate sequential programs on homogeneous multicores
On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system
IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011
Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4
Keynotes: Robustness challenges in the internet of things
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems
FLUTE-EM: Electromigration-Optimized Net Considering Topology Currents and Mechanical Stress
A 128dB dynamic range 1kHz bandwidth stereo ADC with 114dB THD
Modeling and Evaluation of Application-Aware Dynamic Thermal Control in HPC Nodes
ARM6: Processor design for high performance at low power
Tradeoffs in the Design Space Exploration of Application-Specific Processors
Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processors
CMOS implementation of static threshold gates with hysteresis: A new approach
3D rendering using FPGAs
Improvements to satisfiability-based boolean function bi-decomposition
An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census with Aggregation and Belief Propagation
A low power 720p motion estimation processor with 3D stacked memory
A debugging method for gate level circuit designs by introducing programmability
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing
Evolution of logic locking
Temperature- and bus traffic- aware data placement in 3D-stacked cache
Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis
VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers
Communication and Timing Constraints Analysis for IP Design and Integration
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012
Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applications
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory
Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions
Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis
New design of analog and mixed-signal cells using back-gate cross-coupled structure
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs
A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI
Quantum Search Algorithm for Automated Test Pattern Generation in VLSI Testing
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture
Self-dependent Equivalent Circuit Modeling of Electrostatic Comb Transducers for Integrated MEMS
FeFET based Logic-in-Memory design methodologies, tools and open challenges
Post-Quantum Cryptography in MPSoC Environments
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole
A Power Reduction Technique Based on Linear Transformations for Block Ciphers
A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stage
Processor Architecture Optimization for Spatially Dynamic Neural Networks
An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design
Redesigning software and systems for non-volatile processors on self-powered devices
A Hardware File System for Database Storage
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors
VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers
Multiple reset domains verification using assertion based verification
A single-VDD ultra-low energy sub-threshold FPGA
RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support
Preserving Don't Care Conditions During Retiming
Semi- and Fully-Random Access LUTs for Smooth Functions
Qualification of behavioral level design validation for AMS & RF SoCs
Microsystem and SoC Design with UMIPS
Engineering of an Effective Automatic Dynamic Assertion Mining Platform
Combinational logic synthesis for material implication
Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM
VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers
Online Reward-Based Training of Spiking Central Pattern Generator for Hexapod Locomotion
Data re-allocation enabled cache locking for embedded systems
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors
Process Variability Impact on the SET Response of FinFET Multi-level Design
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs
A Simple Circuit to Reduce the Search Range for Large Prime Numbers
A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model
High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card
A Reconfigurable Nanophotonic Architecture based on Phase Change Material
On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
Harmonic resonant clocking
On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits
Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion
Detecting DNA by field effect transistor arrays
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs
Reprogrammable Algorithm Accelerator IP Block
Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verification
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications
On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture
An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector
VLSI Engineering: Beyond Software Engineering
On-Line Test Vector Generation from Temporal Constraints Written in PSL
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications
Contactless transmission of intellectual property data to protect FPGA designs
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications
Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability
A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated Circuits
Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling
Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communications
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory
Adaptive Block-Scaled GeMMs on Vector Processors for DNN Training at the Edge
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load
A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays
Fine-grained post placement voltage assignment considering level shifter overhead
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology
On-Chip Property Verification Using Assertion Processors
GR-PA: A cost pre-allocation model for global routing
2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015
Conclusively verifying clock-domain crossings in very large hardware designs
A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs
Parallelized radix-2 scalable Montgomery multiplier
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method
Towards safer cars - Microeletronics in Automotive
Delay and Short Circuit Power Estimation for a Submicron CMOS Inverter driving a CRC-PI Interconnect Load
SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique
An FPGA-based testing platform for the validation of automotive powertrain ECU
FPGA implementation of high sampling rate in-car non-stationary noise cancellation based on adaptive Wiener filter
Static ultra-low-voltage high-speed CMOS logic and latches
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders
Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge
Timing and interface communication analysis of H.264/AVC encoder using SystemC model
A low-offset dynamic comparator with area-efficient and low-power offset cancellation
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
An FPGA implementation of the VESA Display Stream Compression decoder
Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS
Validating a DFT Strategy's Detection Capability regarding Emerging Faults in RRAMs
Test of single fault tolerant controllers in VLSI circuits
System Design for Computation-in-Memory: From Primitive to Complex Functions
Optimizing an Architecture with Software Pipelining Strategies
Restoration protocol: Lightweight and secur devices authentication based on PUF
Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures
Detailed placement accounting for technology constraints
Resources Restricted Global Scheduling
AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets
FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism
Energy-Effcient Scheduling for Autonomous Mobile Robots
End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays
A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries
Towards future VLSI interconnects using aligned carbon nanotubes
Effects of the positive feedback loop in self biased bandgap reference circuits
SoC oriented real-time high-quality stereo vision system
On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks
Assessing IMD of a Direct-to-RF Platform
Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers
A low-power CAM using a 12-transistor design cell
On-Chip CMOS Sensors for VLSI Imaging Systems
Performance and Energy Evaluation of Memory Organizations in NoC-Based MPSoCs under Latency and Task Migration
Logic synthesis and verification on fixed topology
Evaluation of SET under Process Variability on FinFET Multi-level Design
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache
Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework
Efficient signature-based sub-circuit matching
Radar for assisted living in the context of Internet of Things for Health and beyond
A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS
FPGA Implementation of a VVI Temporary Pacemaker Digital Control
System-level bug explanation through program slicing and instruction clusterization
Crosstalk Fault Tolerant NoC: Design and Evaluation
Improvements to Satisfiability-Based Boolean Function Bi-Decomposition
An accurate power estimation model for low-power hierarchical-architecture SRAMs
PT controlled buck converter with adaptive PCCM using charge monitoring and NMOS current sensing
A Leap of Confidence: A Write-Intensity Aware Prudent Page Migration for Hybrid Memories
On the design of modulo 2 n ±1 residue generators
Circuit and Device Technologies for CMOS functional Image Sensors
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources
Decentralized self-balancing systems
Transistor level automatic layout generator for non-complementary CMOS cells
Phase Coincidence Technique for Frequency Difference Measurement
System-level Dynamic Power Management Techniques for Communication Intensive Devices
Adaptive priority toggle asynchronous tree arbiter for AER-based image sensor
Reversible circuit rewriting with simulated annealing
Ambient Intelligence - Key Technologies in the Communication Age
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms
Multimodal proton and fluorescence image sensor for bio applications
A Unified and Energy-Efficient Depthwise Separable Convolution Accelerator
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations
Netlist Optimization by Gate Merging
Sparsity Controllable Hyperdimensional Computing for Genome Sequence Matching Acceleration
Static energy minimization of 3D stacked L2 cache with selective cache compression
Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecom
Timing Error Detection and Correction by Time Dilation
Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
A software-supported methodology for designing high-performance 3D FPGA architectures
Agent-based on-chip network using efficient selection method
Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis
A Reconfigurable Switch for a DSP Array
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI
Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors
Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths
Level Shifter Circuit Having Dual Outputs for FPD Gate Driver
Power and area efficient clock stretching and critical path reshaping for error resilience
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors
An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them
An analysis of test solutions for COTS-based systems in space applications
A study on the performance of fast initial placement algorithms
Planar Spiral Inductor Modeling for RFIC Design
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography
Solving the partial differential equations of transmission lines with wave digital filters
Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems
A multimode decision-directed channel estimation ASIC for MIMO-OFDM
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems
Has CAD for VLSI Reached a Dead End?
A Low Cost CMOS Polarimetric Ophthalmoscope Scheme for Cerebral Malaria Diagnostics
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias
A sub-μW bio-potential front end in 65nm CMOS
Software-programmable digital pre-distortion on the Zynq SoC
Ultra-Compact, Scalable, Energy-Efficient $VO_{2}$ Insulator-Metal-Transition Oxide Based Spiking Neurons for Liquid State Machines
A 2×VDD-enabled fully-integrated low-dropout regulator with fast transient response
A high efficiency rectifier for inductively power transfer application
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis
A new performance-driven global routing algorithm for gate array
Design Understanding: From Logic to Specification *
Frequency-domain transient analysis of multitime partial differential equation systems
Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates
An efficient H.264 intra frame coder system design
A Genetic Approach To Bus Encoding
Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation
A highly linear wide dynamic range detector for cell recording with microelectrode arrays
Super Freedom Simulator PAX
A voltage mode power converter with the function of digitally duty cycle tuning
Robustness and Minimum Energy-Oriented FinFET Design
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture
Cost-effective smart memory implementation for parallel backprojection in computed tomography
Methodologies for layout decomposition and mask optimization: A systematic review
On Protecting IJTAG using an Inherently Secure SIB
Mining Hyperproperties from Behavioral Traces
Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems
Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures
Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property Verification