yusuke1997/dblp-id-title huggingface dataset:
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter
A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS
A compact low-power 3D I/O in 45nm CMOS
Circuits for portable medical electronic systems
130dB-DR Transimpedance Amplifier with Monotonic Logarithmic Compression and High-Current Monitor
A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element
18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO
13.1 A 227pJ/b -83dBm 2.4GHz multi-channel OOK receiver adopting receiver-based FLL
A 2.6μW Monolithic CMOS Photoplethysmographic Sensor Operating with 2μW LED Power
Dielectrically Transduced Single-Ended to Differential MEMS Filter
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS
4.8 A 0.44e - rms read-noise 32fps 0.5Mpixel high-sensitivity RG-less-pixel CMOS image sensor using bootstrapping reset
A 20 Gb/s/pin 1.18pJ/b 1149µm 2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS
A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios
An LTE-A Multimode Multiband RF Transceiver with 4RX/2TX Inter-Band Carrier Aggregation, 2-Carrier 4×4 MIMO with 256QAM and HPUE Capability in 28nm CMOS
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise
9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications
A Sub-40μW 5Mb/s Magnetic Human Body Communication Transceiver Demonstrating Trans-Body Delivery of High-Fidelity Audio to a Wearable In-Ear Headphone
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance
22.2: An 850µW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces
28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays
A 1.041-Mb/mm 2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS
28.3 CMOS biosensor IC focusing on dielectric relaxations of biological water with 120GHz and 60GHz oscillator arrays
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology
20.3 An RFID-Inspired One-Step Packaged Multimode Bio-Analyzer with Vacuum Microfluidics for Point-of-Care Diagnostics
9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS
5.4 A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavg for 5G FR2 Applications
23.3 A 3nW fully integrated energy harvester based on self-oscillating switched-capacitor DC-DC converter
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration
6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications
21.2 A 4µW-to-1mW parallel-SSHI rectifier for piezoelectric energy harvesting of periodic and shock excitations with inductor sharing, cold start-up and up to 681% power extraction improvement
11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS
20.9 An Autonomous and Lightweight Microactuator Driving System Using Flying Solid-State Batteries
33.2 A 600V GaN Active Gate Driver with Dynamic Feedback Delay Compensation Technique Achieving 22.5% Turn-On Energy Saving
9.6 A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficiency and 131mW Output Power
15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node
Printable electronics for polymer RFID applications
14.7 An Adaptive Analog Temperature-Healing Low-Power 17.7-to-19.2GHz RX Front-End with ±0.005dB/°C Gain Variation, <1.6dB NF Variation, and <2.2dB IP1dB Variation across -15 to 85°C for Phased-Array Receiver
All-digital hybrid temperature sensor network for dense thermal monitoring
CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmission
A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR
A Fully Integrated 62-to-69GHz Crystal-Less Transceiver with 12 Channels Tuned by a Transmission-Line- Referenced FLL in 0.13µm BiCMOS
31.11 A Capacitor-Based Bias-Flip Rectifier with Electrostatic Charge Boosting for Triboelectric Energy Harvesting Achieving Auto-MPPT at Breakdown Voltage and 14× Power Extraction Improvement
A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D
11.7 A load-aware pre-emphasis column driver with 27% settling-time reduction in ±18% panel-load RC delay variation for 240Hz UHD flat-panel displays
A 2.2GHz sub-harmonic mixer for directconversion receivers in 0.13µm CMOS
A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking
Next generation energy scavenging systems
A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor
A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/ps Slew Rate for 8K Displays and Beyond
A Fully Integrated 14-Band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF Transceiver
A 562F 2 Physically Unclonable Function with a Zero-Overhead Stabilization Scheme
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS
A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $\mathsf{i}$
11.4 A 67, 392-SPAD PVTB-compensated multi-channel digital SiPM with 432 column-parallel 48ps 17b TDCs for endoscopic time-of-flight PET
A 32-Site 4-Channel Cochlear Electrode Array
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology
25.5 A 320GHz phase-locked transmitter with 3.3mW radiated power and 22.5dBm EIRP for heterodyne THz imaging systems
19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS
Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process
A 128×128 Single-Photon Imager with on-Chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices
Session 20 Overview: High-Performance VCOs Rf Subcommittee
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-Κ Metal Gate CMOS
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
10.3 A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO
A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface
29.4 A Cryo-CMOS Quantum Computing Unit Interface Chipset in 28nm Bulk CMOS with Phase-Detection Based Readout and Phase-Shifter Based Pulse Generation
A 75-GHz PLL in 90-nm CMOS Technology
A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY
A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface
23.6 A 2pA/√Hz Transimpedance Amplifier for Miniature Ultrasound Probes with 36dB Continuous-Time Gain Compensation
5.7 A 132dB Single-Exposure-Dynamic-Range CMOS Image Sensor with High Temperature Tolerance
A 1V 357Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90nm CMOS
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology
A 60GHz CMOS Receiver Using a 30GHz LO
A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS
A 3mW 2.7GS/s 8b Subranging ADC with Multiple-Reference-Reference-Embedded Comparators
17.8 0.4V 988nW Time-Domain Audio Feature Extraction for Keyword Spotting Using Injection-Locked Oscillators
27.6 A 0.7pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge
Session 27 overview: Physical sensors: Imagers, MEMS, medical and displays subcommittee
A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS
A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB
14.10 34.7A/mm 2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS
EP2: You're hired! The top 25 interview questions for circuit designers
F3: Cutting the last wire - Advances in wireless power
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing
A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator
The next-generation 64b SPARC core in a T4 SoC processor
A 192-Virtual-Receiver 77/79GHz GMSK Code-Domain MIMO Radar System-on-Chip
2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems
16.7 A fully-integrated half-duplex data/power transfer system with up to 40Mb/s data rate, 23mW output power and on-chip 5kV galvanic isolation
A 2MHz 4-to-60VIN Buck-Boost Converter for Automotive Use Achieving 95% Efficiency and CISPR 25 Class 5 Standard
Non-Magnetic 60GHz SOI CMOS Circulator Based on Loss/Dispersion-Engineered Switched Bandpass Filters
A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency
10.3 An analog front-end for 100BASE-T1 automotive Ethernet in 28nm CMOS
A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS
7.2 A 224Gb/s sub pJ/b PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET
A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology
7.9 A 60Gb/s NRZ Burst-Mode CDR with Cross-Injection Locking and Flash Phase Detector Achieving 0.13ns Reconfiguration Time in 28nm CMOS
24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel
Remembrances of Dave Pricer
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors
F1: Digitally assisted analog and analog-assisted digital in high-performance scaled CMOS process
A maximally-digital radio receiver front-end
28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizer
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor
A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory
Session 1 Overview Plenary Session - Invited Papers
A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS
A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS
17.4 A sub-mW antenna-impedance detection using electrical balance for single-step on-chip tunable matching in wearable/implantable applications
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
17.3 A 0.9V 6.3μW multistage amplifier driving 500pF capacitive load with 1.34MHz GBW
23.3 A 605GHz 0.84mW Harmonic Injection-Locked Receiver Achieving 2.3pW/√Hz NEP in 28nm CMOS
Bidirectional OLED microdisplay: Combining display and image sensor functionality into a monolithic CMOS chip
A 0.5V <4µW CMOS photoplethysmographic heart-rate sensor IC based on a non-uniform quantizer
A 12mW 70-to-100GHz mixer-first receiver front-end for mm-wave massive-MIMO arrays in 28nm CMOS
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture
A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reduction
10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications
Session 26 overview: High-speed data converters
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control
A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2
14.8 A 135mW fully integrated data processor for next-generation sequencing
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS
An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications
24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS
A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications
8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line
A 0.9V 0.35 μm Adaptively Biased CMOS LDO Regulator with Fast Transient Response
A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC
Innovation For the Next Decade of Compute Efficiency
A release-on-demand wireless CMOS drug delivery SoC based on electrothermal activation technique
A 5.4mW 0.0035mm 2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
1.1 Silicon technologies and solutions for the data-driven world
An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver
A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle
6.6 A 240Hz-reporting-rate mutual-capacitance touch-sensing analog front-end enabling multiple active/passive styluses with 41dB/32dB SNR for 0.5mm diameter
A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Adaptive circuits for the 0.5-V nanoscale CMOS era
21.5 A portable micro gas chromatography system for volatile compounds detection with 15ppb of sensitivity
A 900MHz direct ΔΣ receiver in 65nm CMOS
15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation
8.5 A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability
A low-power wideband polar transmitter for 3G applications
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs
A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz
29.7 A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL
A 1600-pixel Subretinal Chip with DC-free Terminals and ±2V Supply Optimized for Long Lifetime and High Stimulation Efficiency
A BJT-Based Temperature Sensor with $\pm 0.1^{\circ}\mathrm{C}(3\sigma)$ Inaccuracy from -55°C to 125°C and a 0.85pJ.K 2 Resolution FoM Using Continuous-Time Readout
27.5: A 4, 100µm 2 Wire-Metal-Based Temperature Sensor with a Fractional-Discharge FLL and a Time-Domain Amplifier with ±0.2°C Inaccuracy (3σ) from -40 to 125°C and 45fJ·K 2 Resolution FoM in 28nm CMOS
A Gain-Boosted Discrete-Time Charge-Domain FIR LPF with Double-Complementary MOS Parametric Amplifiers
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS
A 40GOPS 250mW massively parallel processor based on matrix architecture
A CMOS temperature sensor with a voltage-calibrated inaccuracy of ±0.15°C (3σ) from -55 to 125°C
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
A 1.7mW 0.22mm 2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS
Ring amplifiers for switched-capacitor circuits
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
A 160μW 8-channel active electrode system for EEG monitoring
A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS
A 10GS/s 8b 25fJ/c-s 2850um 2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface
A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS
8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing
20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models
A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC
A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging
27.3 A 13.8-ENOB 0.4pF-CIN 3 rd -Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching
A scalable massively parallel processor for real-time image processing
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension
26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage
A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS
Design issues and considerations for low-cost 3D TSV IC technology
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference
35.8 DustNet: A Network of Time-Division Multiplexed Ultrasonic Implants with 16-Level ASK Backscatter Modulation
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS
17.4 Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing
A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18µ SiGe process
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking
12.1 Monolithically Integrated Sub-63 fJ/b 8-Channel 256Gb/s Optical Transmitter with Autonomous Wavelength Locking in 45nm CMOS SOI
A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS
27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing
16.4 A flexible EEG acquisition and biomarker extraction system based on thin-film electronics
A 2Gb/s network processor with a 24mW IPsec offload for residential gateways
8.3 A 553F 2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability
Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset
A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices
16.3 3nm Physical Unclonable Function with Multi-Mode Self-Destruction and 3.48×10 -5 Bit Error Rate
A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card
A Power-Efficient High-Throughput 32-Thread SPARC Processor
19.2 A self-interference-cancelling receiver for in-band full-duplex wireless with low distortion under cancellation of strong TX leakage
25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators
Session 12 overview: Efficient Power Conversion
5μW-to-10mW input power range inductive boost converter for indoor photovoltaic energy harvesting with integrated maximum power point tracking algorithm
A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
2.5 A complementary VCO for IoE that achieves a 195dBc/Hz FOM and flicker noise corner of 200kHz
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting
A Fully Digital Time-Mode CMOS Image Sensor with 22.9pJ/frame.pixel and 92dB Dynamic Range
An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput