yusuke1997/dblp-id-title huggingface dataset:
Using Formal Methods to Support the Development of STLs for GPUs
Defect Detection Rate through IDDQ for Production Testing
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model
Concurrent Error Detection and Fault Location in a Fast ATM Switch
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores
An SBus Multi-Tracer and its applications
Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation
Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication Protocols
In-Field Testing of NAND Flash Storage: Why and How?
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor
Testing the Logic Cells and Interconnect Resources for FPGAs
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
A New Test Paradigm for Semiconductor Memories in the Nano-Era
Efficient Identification of Crosstalk Induced Slowdown Targets
An adjacency-based test pattern generator for low power BIST design
Improving Test Pattern Compactness in SAT-based ATPG
Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips
An Enhanced SRAM BISR Design with Reduced Timing Penalty
A Test Pattern Generation Algorithm Exploiting Behavioral Information
BIST testability enhancement using high level test synthesis for behavioral and structural designs
On Chip Weighted Random Patterns
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test
Automotive Microcontroller Characterization Hardware - Challenges and Solutions
Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing
Temperature Dependent Test Scheduling for Multi-core System-on-Chip
Benefits of Phase Interference Detection to IC Waveform Probing
Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
New Fault Detection Algorithm for Multi-level Cell Flash Memroies
Reliability: A Cross-Disciplinary and Cross-Layer Approach
Testing Embedded Memories: Is BIST the Ultimate Solution?
Critical-Area-Aware Test Pattern Generation and Reordering
Rough-Hierarchical Testing for Safety Critical Software
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation
An HDL-Based Platform for High Level NoC Switch Testing
Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells
Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking
EB-Testing-Pad Method and Its Evaluation by Actual Devices
Post Silicon Debugging of Electrical Bugs Using Trace Buffers
Testing domino circuits in SOI technology
Software transformations for sequential test generation
Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs
Accelerating Test Data Processin
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal
Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage
SSTKR: Secure and Testable Scan Design through Test Key Randomization
Syndrome Simulation And Syndrome Test For Unscanned Interconnects
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way
Error-Tolerability Evaluation and Test for Images in Face Detection Applications
7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore
Efficient Embedding of Deterministic Test Data
A Comparison Study of the Compatibility Approaches for SGX Enclaves
A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing
Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry
Identification of Faulty TSV with a Built-In Self-Test Mechanism
Security Vulnerabilities in AI Hardware: Threats and Countermeasures
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits
On the Generation of Functional Test Programs for the Cache Replacement Logic
A method for determining whether asynchronous circuits are self-checking
Generating Test Cases for Real-Time Software by Time Petri Nets Model
Pair Balance-Based Test Scheduling for SOCs
Testable design of non-scan sequential circuits using extra logic
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs
Automated Post-Silicon Debugging of Failing Speedpaths
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits
Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation
Test Efficiency Analysis and Improvement of SOC Test Platforms
A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE
Effective parallel processing techniques for the generation of test data for a logic built-in self test system
Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture
Test generation for crosstalk-induced faults: framework and computational result
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling
A Delay Measurement Technique Using Signature Registers
Self-Checking Residue Number System for Low-Power Reliable Neural Network
An Effective Test Pattern Generation for Testing Signal Integrity
Hybrid BIST Test Scheduling Based on Defect Probabilities
Low-cost generation of RF test stimuli from baseband digital signals
Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay
High Level Verification and Its Use at Pos-Silicon Debugging and Patching
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks
IDDQ Defect Detection in Deep Submicron CMOS ICs
Simulation and Development of Short Transparent Tests for RAM
A Heuristically Mechanical Model for Accurate and Fast Soft Error Analysis
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)
A Robust Solution for Embedded Memory Test and Repair
Thermal Monitoring Of Safety-Critical Integrated Systems
Testing for Parasitic Memory Effect in SRAMs
TEA: A Test Generation Algorithm for Designs with Timing Exceptions
Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution
Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes
MMFuzz: Towards Enhancing RTL Fuzz Testing Using Metric Feedbacks Based on Markov Chain
An ASIC Designer's Point of View
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs
Identification of Feedback Bridging Faults with Oscillation
Peak Power Estimation: A Case Study on CPU Cores
Protocol Aware Test Methodologies Using Today
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing
Built-In Self-Test for Multi-Port RAMs
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach
Easily Testable Data Path Allocation Using Input/Output Registers
Enabling Inter-Product Transfer Learning on MCU Performance Screening
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding
Single-control testability of RTL data paths for BIST
An approach to hierarchy model checking via evaluating CTL hierarchically
An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing
A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure
Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods
Keynote Speech 1: New Paths for Test
NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs ∗
Experimental Results of Transition Fault Simulation with DC Scan Tests
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults
Software-Based Self-Testing of Processors Using Expanded Instructions
SMASh: A State Encoding Methodology Against Attacks on Finite State Machines
Delay Test Pattern Generation Considering Crosstalk-Induced Effects
Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis
Test Time Analysis for IEEE P1687
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit
A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
A Complete Logic BIST Technology with No Storage Requirement
Automation of 3D-DfT Insertion
A High-Level Synthesis Method for Weakly Testable Data Paths
Design for Diagnosability of CMOS Circuits
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems
On the development of power supply voltage control testing technique for analogue circuits
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test
A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits
Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits
Tailoring Tests for Functional Binning of Integrated Circuits
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies
Test Generation for State Retention Logic
Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems
Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms
Test Roles in Diagnosis and Silicon Debug
High speed IDDQ test and its testability for process variation
Reducing Scan Shifts Using Folding Scan Trees
FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis
Microsystem Testing: Challenge or Common Knowledge?
A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores
Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project
Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan
Predicting IC Defect Level Using Diagnosis
Power Aware test methodology for Test Power hungry complex SoCs
SHAKTI-F: A Fault Tolerant Microprocessor Architecture
On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter
Trojan Horse Detection for RISC-V Cores Using Cross-Auditing
A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-sampling
Achieving High Test Quality with Reduced Pin Count Testing
An RT-Level ATPG Based on Clustering of Circuit States
A Novel Testing Approach for Safety-Critical Software
Lifetime Reliability Trojan Based on Exploring Malicious Aging
New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency
Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability
Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency
Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption
Low Power Decompressor and PRPG with Constant Value Broadcast
Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs
AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators
High Performance Compaction for Test Responses with Many Unknowns
SeGa: A Trojan Detection Method Combined With Gate Semantics
Special Session: Analog Production Test
Testing of Configurable 8T SRAMs for In-Memory Computing
A RTL Testability Analyzer Based on Logical Virtual Prototyping
Spectral RTL Test Generation for Gate-Level Stuck-at Faults
USB2.0 Logic Built In Self Test Methodology
Built-in current sensor designs based on the bulk-driven technique
Pseudo-Parity Testing with Testable Design
Faster processing for microprocessor functional ATPG
Deterministic Path Delay Measurement Using Short Cycle Test Pattern
A fault location technique and alternate routing in Benes network
Testable Design and Testing of MCMs Based on Multifrequency Scan
High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST
High Level Test Generation / SW based Embedded Test
Fault-Tolerant Analysis of Feedback Neural Networks with Threshold Neurons
An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains
A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints
Panel: New Research Problems in the Emerging Test Technology
Fast functional testing of delay-insensitive circuits
Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets
DFT of the Cell Processor and its Impact on EDA Test Softwar
Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN Design
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format
Evaluation of Intra-Word Faults in Word-Oriented RAMs
On Determining the Real Output Xs by SAT-Based Reasoning
Online Periodic Test of Reconfigurable Scan Networks
Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test
A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
Embedded Test and Measurement Critical for Deep Submicron Technology
A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training
Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
F-matrix (ABCD-matrix) Circuit Simulation Built in IC Test Program
Briefing a New Approach to Improve the EMI Immunity of DSP Systems
A Methodology for Identifying High Timing Variability Paths in Complex Designs
Improving Logic Test Quality of Microprocessors
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency
15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006
Measurement-Based Modeling with Adaptive Sampling
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level
Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits
A BIST Scheme for Asynchronous Logic
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST
Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection
Fail Pattern Identification for Memory Built-In Self-Repair
Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs
Lowering Cost of Test: Parallel Test or Low-Cost ATE?
A New LFSR Reseeding Scheme via Internal Response Feedback
An ISA-level Accurate Fault Simulator for System-level Fault Analysis
Overview of On-Chip Performance Monitors for Clock Signals
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices
Test Generation Of Analog Switched-Current Circuits
DFT for fast testing of self-timed control circuits
At-Speed Scan Test Method for the Timing Optimization and Calibration
Structure-Oriented Test of Reconfigurable Scan Networks
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects
A Power Reduction Method for Scan Testing in Ultra-Low Power Designs
LLM-aided Front-End Design Framework For Early Development of Verified RTLs
A Test Integration Methodology for 3D Integrated Circuits
Static compaction for two-pattern test sets
Towards Formal Verification for MAC-based In-Memory Computing
Synthesis of Testable Finite State Machine Through Decomposition
Fault Diagnosis under Transparent-Scan
An Approach to Testing the Nonexistence of Initial State in Z Specifications
T1: Design for Manufacturability
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor
DFT + DFD: An Integrated Method for Design for Testability and Diagnosability
An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits
Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults
Quality Aware Error Detection in 2-D Separable Linear Transformation
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification
Self-Calibrating Embedded RF Down-Conversion Mixers
Improve Volume Physical-Aware Diagnosis via Active Pattern Sampling
IC Reliability Simulator ARET and Its Application in Design-for-Reliability
Device Aware Diagnosis for Unique Defects in STT-MRAMs
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs
Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus
A new framework for static timing analysis, incremental timing refinement, and timing simulation
17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008
iDEN Phone System Test: An Automation Approach
Non-Intrusive Design of Concurrently Self-Testable FSMs
A Soft Error Tolerant LUT Cascade Emulator
On-chip Analog Response Extraction with 1-Bit ? - Modulators
EHSAT Modeling from Algorithm Description for RTL Model Checking
Fault Diagnosis for Static CMOS Circuits
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation
Non-robust Test Generation for Crosstalk-Induced Delay Faults
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders
Low Power BIST for Scan-Shift and Capture Power
Enhancing Transition Fault Model for Delay Defect Diagnosis
6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan
On Pass/Fail Dictionaries for Scan Circuits
Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design
PLL Based High Speed Functional Testing
A New Algorithm for Retiming-Based Partial Scan
Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors
On-Line Error Detection in Digital Microfluidic Biochips
Control-Flow Checking via Regular Expressions
rosTest: Universal Test Framework for Real-Time Operating System
A Fault-Tolerant Architecture for Symmetric Block Ciphers
An efficient comparative concurrent Built-In Self-Test technique
Code-Disjoint Circuits for Parity Circuits
Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem
Block-based Schema-driven Assertion Generation for Functional Verification
A Robust Automated Scan Pattern Mismatch Debugger
Efficient Pattern-Based Verification of Connections to IP Cores
Test Compression Based on Lossy Image Encoding
Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits
Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning
26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017
Test sequence compaction by reduced scan shift and retiming
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits
Analysis of Resistive Bridging Defects in a Synchronizer
ECSAS: Exploring Critical Scenarios from Action Sequence in Autonomous Driving
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM
Characterization and Test of Intermittent Over RESET in RRAMs
A Low-Cost Diagnosis Methodology for Pipelined A/D Converters
A Complete Security Protocol To Safeguard IJTAG Architecture
Test Generation for Designs with On-Chip Clock Generators
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation
A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself
Enhanced untestable path analysis using edge graphs
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage
Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
Testing for Floating Gates Defects in CMOS Circuits
An FPGA-based re-configurable functional tester for memory chips
Collaboration between Industry and Academia in Test Research
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test
On Bias in Transition Coverage of Test Sets for Path Delay Faults
An Efficient 2-Phase Strategy to Achieve High Branch Coverage
March Tests for Word-Oriented Two-Port Memories
Chip Identification using the Characteristic Dispersion of Transistor
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs
Test Scheduling of BISTed Memory Cores for SOC
CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply
Synthesis of Sequential Circuits with Clock Control to Improve Testability
Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test
Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence
Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs
An Approach to the On-Line Testing of Operational Amplifiers
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits
Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns
Programmable Logic BIST for At-speed Test
Multiple-Core under Test Architecture for HOY Wireless Testing Platform
Digital Compensation for Timing Mismatches in Interleaved ADCs
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis
Fault diagnosis for linear analog circuits
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation
A Flexible Logic BIST Scheme and Its Application to SoC Designs
An Examination of PRPG Selection Approaches for Large, Industrial Designs
Vector-Based Functional Fault Models for Delay Faults
Finite element analysis (FEA) based design optimization of ultrastable, high finesse optical cavities for portable optical atomic clock applications
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure