yusuke1997/dblp-id-title huggingface dataset:
Coverage directed test generation for functional verification using bayesian networks
Route Packets, Not Wires: On-Chip Interconnection Networks
Language extensibility and program design
Test-data volume optimization for diagnosis
Automatic pipe routing and material take-off system for chemical plant
A Methodology for Concurrent Fabrication Process/Cell Library Optimization
ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits
Lightning Talk 6: Bringing Together Foundation Models and Edge Devices
Life Expectancy of Standards (Panel Abstract)
A technique for distributed execution of design automation tools
Obstacle-avoiding free-assignment routing for flip-chip designs
A CAD user's perspective what gets done right wrong and not at all (Position Paper)
Probabilistic Error Propagation through Approximated Boolean Networks
BirdMoE: Reducing Communication Costs for Mixture-of-Experts Training Using Load-Aware Bi-random Quantization
Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver
LSI layout checking using bipolar device recognition technique
Experiments with a Performance Driven Module Generator
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes
DDOT: Data Driven Online Tuning for energy efficient acceleration
Studying the mouse for CAD systems
A Data Structure for Circuit Net Lists
Precise timing analysis for direct-mapped caches
StitchUp: automatic control flow protection for high level synthesis circuits
Energy efficient MapReduce with VFI-enabled multicore platforms
Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform
Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?"
Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation
Design of an one-cycle decompression hardware for performance increase in embedded systems
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs
Distributed Computing Environment for Design Automation in the 90's (Panel Abstract)
Constraint abstraction for vectorless power grid verification
A low cost, transportable, data management system for LSI/VLSI design
A General Purpose Multiple Way Partitioning Algorithm
Transmission line models for transient analysis
United We Stand: A Threshold Signature Scheme for Identifying Outliers in PLCs
On the role of timing masking in reliable logic circuit design
A Robust Exponential Integrator Method for Generic Nonlinear Circuit Simulation
A survey of current microprogrammed computers
A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators
A reconfigurable design-for-debug infrastructure for SoCs
Traffic-aware power optimization for network applications on multicore servers
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers
A placement algorithm for polycell LSI and ITS evaluation
Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation
An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits
Compact State Machines for High Performance Pattern Matching
Robustly Executing DNNs in IoT Systems Using Coded Distributed Computing
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points
qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology
Total stuct-at-fault testing by circuit transformation
Trace-driven optimization of networks-on-chip configurations
INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded Robots
Efficient SAT solving: beyond supercubes
PUMICE: Processing-using-Memory Integration with a Scalar Pipeline for Symbiotic Execution
The EDA Start-up Experience: The First Product (Panel)
Invited: SambaNova SN40L: Unleashing Agentic AI with Dataflow
Operating-system controlled network on chip
Multiple constant multiplication by time-multiplexed mapping of addition chains
Automating the generation of interactive interfaces
Design automation and VLSI in the 80's (Panel Discussion)
MetaCore: An Application Specific DSP Development System
Assigning wires to layers of a printed circuit board
Compiler directed automatic stack trimming for efficient non-volatile processors
LocusRoute: A Parallel Global Router for Standard Cells
Silicon compilers and expert systems for VLSI
Data Security for Web-based CAD
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis
TetrisLock: Quantum Circuit Split Compilation with Interlocking Patterns
Placement of irregular circuit elements on non-uniform gate arrays
A Fast State Assignment Procedure for Large FSMs
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
Taking into account asynchronous signals in functional test of complex circuits
Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval
VQT-CiM: Accelerating Vector Quantization Enhanced Transformer with Ferroelectric Compute-in-Memory
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction
LPCA: learned MRC profiling based cache allocation for file storage systems
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264
Mapping a domain specific language to a platform FPGA
Piecewise polynomial nonlinear model reduction
Memory heat map: anomaly detection in real-time embedded systems using memory behavior
Design tools for reliability analysis
Improving Bus Test Via I DDT and Boundary Scan
New Spectral Linear Placement and Clustering Approach
A rectangle-probe router for multilayer P.C. boards
Process oriented logic simulation
Bitwise Adaptive Early Termination in Hyperdimensional Computing Inference
Flashmark: Watermarking of NOR Flash Memories for Counterfeit Detection
Clock tree synthesis with methodology of re-use in 3D IC
The Interactive Computer Graphics System for Machined Part Design and NC Tape Generation
Synthesizing interconnect-efficient low density parity check codes
Remote attestation for low-end embedded devices: the prover's perspective
Rate Optimal VLSI Design from Data Flow Graph
Estimation of Average Switching Activity in Combinational and Sequential Circuits
A subjective review of compaction (tutorial session)
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management
SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST
State encoding of large asynchronous controllers
On the status of design automation in canada
ChipSecure: A Reconfigurable Analog eFlash-Based PUF with Machine Learning Attack Resiliency in 55nm CMOS
Register Minimization beyond Sharing among Variables
Fast timing-driven partitioning-based placement for island style FPGAs
Creating and Exploiting Flexibility in Steiner Trees
An application of branch and bound method to automatic printed circuit board routing
TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of Multipliers
Architectural selection of A/D converters
SAT-Sweeping Enhanced for Logic Synthesis
Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers
Identifying Sequential Redundancies Without Search
Automatic design rule correction in presence of multiple grids and track patterns
Exploration with upgradeable models using statistical methods for physical model emulation
Behavioral-level test development
An approach to the testing of microprocessors
A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Invited - Can IoT be secured: emerging challenges in connecting the unconnected
Serial reconfigurable mismatch-tolerant clock distribution
Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves
N.mPc: A retrospective
MixPipe: Efficient Bidirectional Pipeline Parallelism for Training Large-Scale Models
Low-overhead Aging-aware Resource Management on Embedded GPUs
Hardware Reuse at the Behavioral Level
Correctness and security at odds: post-silicon validation of modern SoC designs
Computation and Refinement of Statistical Bounds on Circuit Delay
Secure Information Flow Verification with Mutable Dependent Types
ADVISOR: Approximate Computing-frienDly High-LeVel Synthesis DesIgn Space ExplORer
A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation
A CAD system for logic design based on frames and demons
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
Predictive runtime verification of multi-processor SoCs in SystemC
CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge Distillation
Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization
A hybrid approach to cyber-physical systems verification
Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation
Designing a 2048-Chiplet, 14336-Core Waferscale Processor
Hardware-Assisted Intellectual Property Protection of Deep Learning Models
Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011
The evolution of design automation to meet the challanges of VLSI
Analysis and minimization techniques for total leakage considering gate oxide leakage
Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM Systems
Algorithmic Aspects of Three Dimensional MCM Routing
Translation Validation for Stateflow to C
ST 2 GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders
The State of VHDL in Russia
Using SAT-based Craig interpolation to enlarge clock gating functions
Segmented Angular Pre-Processing for Accurate and Efficient In-Memory Vector Similarity Search
SRAM parametric failure analysis
Predicting performance potential of modern DSPs
Robust Rational Function Approximation Algorithm for Model Generation
Contract-based system-level composition of analog circuits
New game, new goal posts: a recent history of timing closure
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement
VStore: in-storage graph based vector search accelerator
Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters
Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
HDPG: hyperdimensional policy-based reinforcement learning for continuous control
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs
Split Circuit Model for Test Generation
Enabling a new era of brain-inspired computing: energy-efficient spiking neural network with ring topology
Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing
A Framework for Collaborative and Distributed Web-Based Design
A linear-time heuristic for improving network partitions
Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCC
What's the next EDA driver?
ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script Customization
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology
Pipette: efficient fine-grained reads for SSDs
A network-variational basis for generalized computer representation of multifreedom, constrained, mechanical systems
An efficient dynamically reconfigurable on-chip network architecture
Debugging from high level down to gate level
Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture
A SAT-based algorithm for reparameterization in symbolic simulation
Mapping on multi/many-core systems: survey of current and emerging trends
Convex delay models for transistor sizing
Design automation in norway
GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving
Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors
Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing
Fast algorithms for IR voltage drop analysis exploiting locality
In-situ self-powered intelligent vision system with inference-adaptive energy scheduling for BNN-based always-on perception
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005
Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories
Generalized Moment-Matching Methods for Transient Analysis of Interconnect Networks
NAX: neural architecture and memristive xbar based accelerator co-design
A new algebraic procedure for the simulation of large digital networks
Invited: Conformal Inference meets Evidential Learning: Distribution-Free Uncertainty Quantification with Epistemic and Aleatoric Separability
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK
Automatic communication refinement for system level design
Transmission line models, a unified physical network approach
BIMOS, an MOS oriented multi-level logic simulator
Quadratic Boolean Programming for Performance-Driven System Partitioning
CirSTAG: Circuit Stability Analysis on Graph-based Manifolds
QuickYield: an efficient global-search based parametric yield estimation with performance constraints
Modeling Litho-Constrained Design Layout
Dynamic Power Management Based on Continuous-Time Markov Decision Processes
Formal hardware/software co-verification by interval property checking with abstraction
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
QMS: Evaluating the Side-Channel Resistance of Masked Software from Source Code
Abstract Data Types and High-Level Synthesis
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
Observations of a CAD user (Position Paper)
DRAFTS: Discretized Analog Circuit Fault Simulator
Topological routing to maximize routability for package substrate
Algebraic analysis of nondeterministic behavior
Time-domain segmentation based massively parallel simulation for ADCs
Handling non-unitaries in quantum circuit equivalence checking
System facilities for CAD databases
A Reordering Technique for Efficient Code Motion
Optimum positioning of interleaved repeaters In bidirectional buses
Holistic WCRT Analysis for Global Fixed-Priority Preemptive Multiprocessor Scheduling
PESDA and Design Abstraction: How High is Up? (Panel)
Computer system design description
Asynchronous Interface Specification, Analysis and Synthesis
Recursive Channel Router
Cache-aware Task Decomposition for Efficient Intermittent Computing Systems
Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN Accelerators
Software Synthesis of Process-Based Concurrent Programs
A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability
PRIMO: Probability Interpretation of Moments for Delay Calculation
The semi-custom revolution: How to thrive or survive
Layered Switching for Networks on Chip
FORMPLOT - a forms design system
It's hammer time: how to attack (rowhammer-based) DRAM-PUFs
MOCA: an Inter/Intra-Chip Optical Network for Memory
Invited: Algorithm and Hardware Co-Design for Energy-Efficient Neural SLAM
Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs
Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction
On the Security of Strong Memristor-based Physically Unclonable Functions
Automatic formal verification of DSP software
Architecture 2.0: Challenges and Opportunities
Share-design automation workshop
Structured Design of Microelectromechanical Systems
MDELTA - a digital program for control system analysis
Automatic test generation for stuck-open faults in CMOS VLSI
Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum Circuits
Thermal-aware optical-electrical routing codesign for on-chip signal communications
Design tools for oscillator-based computing systems
Generation of High Quality Non-Robust Tests for Path Delay Faults
Co-design of deep neural nets and neural net accelerators for embedded vision applications
Enabling Practical Processing in and near Memory for Data-Intensive Computing
The Future of Custom Cell Generation in Physical Synthesis
Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks
ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs
Knowledge Based Control in Micro-Architecture Design
High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
An efficient method for multi-level approximate logic synthesis under error rate constraint
AxoNN: energy-aware execution of neural network inference on multi-accelerator heterogeneous SoCs
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Hold time validation on silicon and the relevance of hazards in timing analysis
SimPhony: A Device-Circuit-Architecture Cross-Layer Modeling and Simulation Framework for Heterogeneous Electronic-Photonic AI System
Proceedings of the 10th Design Automation Workshop, DAC '73, Portland, Oregon, USA, June 25-27, 1973
Efficient Simulation of Lossy and Dispersive Transmission Lines
A framework for optimizing thermoelectric active cooling systems
VITAL: Vision Transformer Neural Networks for Accurate Smartphone Heterogeneity Resilient Indoor Localization
GERMINAL: Towards a general and integrated system for computer aided design
Terminator on SkyNet: a practical DVFS attack on DNN hardware IP for UAV object detection
Exact Coloring of Real-Life Graphs is Easy
Path Hashing to Accelerate Delay Fault Simulation
Improving charging efficiency with workload scheduling in energy harvesting embedded systems
Application of design patterns for hardware design
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams
Improving high-level synthesis with decoupled data structure optimization
Minimizing Labeling, Maximizing Performance: A Novel Approach to Nanoscale Scanning Electron Microscope (SEM) Defect Segmentation
PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon era
Beyond ECDSA and RSA: Lattice-based Digital Signatures on Constrained Devices
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits
Unifying behavioral synthesis and physical design
Towards Uncertainty-aware Robotic Perception via Mixed-signal BNN Engine Leveraging Probabilistic Quantum Tunneling
EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Unified Compression and Adaptive Layer Voting
Circuit frequency response analysis program with worst-case capabilities (FRWC)
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis
Functional simulation in the lamp system
Complementary communication path for energy efficient on-chip optical interconnects
State Reduction Using Reversible Rules
System design of active basestations based on dynamically reconfigurable hardware
A practical reconfigurable hardware accelerator for Boolean satisfiability solvers
Watermarking Techniques for Intellectual Property Protection
Control Optimization in High-Level Synthesis Using Behavioral Don't Cares
SIGMA-CAD: Some new concepts in design of general purpose CAD systems
On the potential of 3D integration of inductive DC-DC converter for high-performance power delivery
Exact Evaluation of Diagnostic Test Resolution
Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL
Massively Parallel Approximate Simulation of Hard Quantum Circuits
Practical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing Systems
Picture generation for Interactive Graphics
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software
UTMC's LSI CAD system - highland
Alternate hammering test for application-specific DRAMs and an industrial case study
Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction
Reticle Enhancement Technology: Implications and Challenges for Physical Design
Automatic generation and characterization of CMOS polycells
Automated fixed-point data-type optimization tool for signal processing and communication systems
Externally Hazard-Free Implementations of Asynchronous Circuits
The standard transistor array (STAR): Part I A two-layer metal semicustom design system
Reducing Memory Requirements of Nested Loops for Embedded Systems
Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution
Future Computing Environments for DA (panel)
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers
PriMax: maximizing DSL application performance with selective primitive acceleration
A Bridge-based Compression Algorithm for Topological Quantum Circuits
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification
PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator
Algorithms for Accuracy Enhancement in a Hardware Logic Simulator
Vicis: a reliable network for unreliable silicon
Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design
In Hardware We Trust: Gains and Pains of Hardware-assisted Security
On Computing the Transitive Closure of a State Transition Relation
What is the Next Big Productivity Boost for Designers? (Panel Abstract)
HyperAttack: An Efficient Attack Framework for HyperDimensional Computing
Heuristic enhancement of an algorithmic test generator
FCM: A Fusion-aware Wire Cutting Approach for Measurement-based Quantum Computing
Information leakage chaff: feeding red herrings to side channel attackers
CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing
Asynchronous circuits transient faults sensitivity evaluation
Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Synthesis of synchronous elastic architectures
Aiming at a general routing strategy
Plant design management system (PDMS) in action
MobileSwap: Cross-Device Memory Swapping for Mobile Devices
Delay Fault Coverage and Performance Tradeoffs