yusuke1997/dblp-id-title huggingface dataset:
New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric Materials
Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs
Characterization of sequential cells for constraint sensitivities
DT2HDL: A Binary Decision Tree to HDL Generation Tool
Precision Unwound: Fine-Tuning Loop Unrolling for Energy-Efficient FPGA-Based PQC Using HLS
Input-aware statistical timing analysis-based delay test pattern generation
Stopping Criteria Comparison: Towards High Quality Behavioral Verification
A novel and efficient method for power pad placement optimization
Merits of Time-Domain Computing for VMM - A Quantitative Comparison
Power Supply Noise Suppression via Clock Skew Scheduling
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment
Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions
Irregularly shaped voltage islands generation with hazard and heal strategy
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits
A novel fine-grain track routing approach for routability and crosstalk optimization
Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling
GlYFF: A framework for global yield and floorplan aware design optimization
Energy Consumption and Runtime Performance Optimizations Applied to Hyperspectral Imaging Cancer Detection
Adding Context to LLM-Guided Verilog Repair
Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing
Design Success: Foundry Perspective
Evening Panel Discussion: IP Industry: Nordstrom or K-Mart? The Trend Toward Tighter Relationships between Suppliers and Users
Organization of a Microprocessor Design Process Using Internet-Based Interoperable Workflows
Application and OS unconscious power manager for SoC systems
Dynamic Power Management by Combination of Dual Static Supply Voltages
Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs
Test Structures for Circuit Yield Assessment and Modeling
Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution
Variability resilient low-power 7T-SRAM design for nano-scaled technologies
Optimizing Post-Quantum Crypto Algorithms in Embedded IoT Systems
Coverage of compositional property sets under reactive constraints
A New Foe in GPUs: Power Side-Channel Attacks on Neural Network
Robust importance sampling for efficient SRAM yield analysis
Power Macromodeling for a High Quality RT-Level Power Estimation
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
What is Design Quality? How can Quality in Electronic Design be Quantified?
Scalable Low-Cost Sorting Network with Weighted Bit-Streams
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits
Supplemental Test Methods (Tutorial Abstract)
Scratch-pad memory banking by dynamic programming for embedded data-intensive applications
Hybrid-comp: A criticality-aware compressed last-level cache
Complex Reliability Evaluation of Voters for Fault Tolerant Designs
An ultra-fast and low-power design of analog circuit network for DoG pyramid construction of SIFT algorithm
Analysis of Short and Aging Faults in TSVs at the Physical Level with Parametric Variation
Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs
Comparison between power gating and DVFS from the viewpoint of energy efficiency
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory
Reseeding-Based Test Set Embedding with Reduced Test Sequences
Technology Mapping for Reliability Enhancement in Logic Synthesis
Directed test generation for hybrid systems
A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications
A router for via configurable structured ASIC with standard cells and relocatable IPs
An efficient statistical chip-level total power estimation method considering process variations with spatial correlation
XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration
A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices
A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications
Wire Planning with Bounded Over-the-Block Wires
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
Sandbox Detection Using Hardware Side Channels
Incremental ATPG methods for multiple faults under multiple fault models
A Versatile High Speed Bit Error Rate Testing Scheme
Virtual Hellfire Hypervisor: Extending Hellfire Framework for embedded virtualization support
Self-Learning Analog Comparator with Adaptive Sampling Rate Scheme for Energy Optimization in Continuous Input Monitoring Applications
Electrical Characterization of Signal Routability and Performance
Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs
Impact of FinFET technology for power gating in nano-scale design
A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic
Revisiting the linear programming framework for leakage power vs. performance optimization
Power-supply-network design in 3D integrated systems
Design Space Exploration of Modular Multipliers for ASIC FHE accelerators
Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing
Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack
Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology
Impact Analysis of Process Variability on Clock Skew
Processing High Volume Scan Test Results for Yield Learning
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits
Leveraging Deep CNN and Transfer Learning for Side-Channel Attack
Circuit design perspectives for Ge FinFET at 10nm and beyond
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences
PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems
Temperature aware thread migration in 3D architecture with stacked DRAM
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis
Digitally Named World: Challenges for New Social Infrastructures
A low-power field-programmable analog array for wireless sensing
A Resistor-less, Nano-Watt CMOS Voltage Reference with High PSRR
Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping
ESD: Design For IC Chip Quality and Reliability
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Critical area driven dummy fill insertion to improve manufacturing yield
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance
ML-Based Real-Time URL Inspection with Hardware Acceleration for Enhanced Web Security
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs
Spice Model Quality: Process Development Viewpoint
Crosstalk Aware Static Timing Analysis: A Two Step Approach
Design of an efficient NoC architecture using millimeter-wave wireless links
Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis
Robust gate sizing by Uncertainty Second Order Cone
Signal probability control for relieving NBTI in SRAM cells
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators
REDACTOR: eFPGA Redaction for DNN Accelerator Security
Reliable Laser Programmable Gate Array Technology
Optimal Sequencing Energy Allocation for CMOS Integrated Systems
A low noise CMOS interface circuit for capacitive liquid crystal chemical and biological sensor
Dynamic Timing Analysis Considering Power Supply Noise Effects
Accelerating trace computation in post-silicon debug
Strategies for Quality CAD PDKs
On pattern generation for maximizing IR drop
DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis
Simulation Based Assessment of SRAM Data Retention Voltage
Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs
A Divide-and-Conquer Algorithm for 3D Capacitance Extraction
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation
Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits
Resource constrained cellular neural networks for real-time obstacle detection using FPGAs
Towards Energy Efficient non-von Neumann Architectures for Deep Learning
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design
A negotiated congestion based router for simultaneous escape routing
Electromigration Reliability Comparison of Cu and Al Interconnects
Low redundancy matrix-based codes for adjacent error correction with parity sharing
Constructing small-signal equivalent impedances using ellipsoidal norms
Resistance Matrix in Crosstalk Modeling for Muliconductor Systems
Focusing on the Key Suspicious Trojan Nets with a Collaborative Approach
High-Level Synthesis for Microfluidic Biochips Considering Actual Volume Management and Channel Storage
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Challenges of Securing Low-Power LoRaWAN Devices Deployed in Advanced Manufacturing
AutoFlows: Inferring Message Flows from System Communication Traces
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations
Memory Bus Encoding for Low Power: A Tutorial
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates
HISPE: High-Speed Configurable Floating-Point Multi-Precision Processing Element
Compact Dictionaries for Fault Diagnosis in BIST
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors
Self-aligned double patterning (SADP) layout decomposition
Ultra low-voltage, rail-to-rail input/output stage Operational Transconductance Amplifier (OTA) with high linearity and its application in a Gm-C filter
An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization
On-line reliability-aware dynamic power management for real-time systems
Simulation Using Code-Perturbation: Black- and White-Box Approach
Statistical Timing Analysis Considering Spatial Correlations
Full-Chip Analysis Method of ESD Protection Network
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning
Maximizing the performance of NoC-based MPSoCs under total power and power density constraints
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design
A Reliable Clock Tree Design Methodology for ASIC Designs
Low-leakage and process-variation-tolerant write-read disturb-free 9T SRA cell using CMOS and FinFETs
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
Photomasks and the enablement of circuit design complexity
A new ECO technology for functional changes and removing timing violations
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
An effective approach to detect logic soft errors in digital circuits based on GRAAL
Switch level optimization of digital CMOS gate networks
Procedural Analog Design (PAD) Tool
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design
Exploring Parallel Implementation of SPHINCS + Using Advanced Vector Extensions (AVX) Sets
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract)
Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations
Rewiring for Watermarking Digital Circuits
Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application
A Hybrid BIST Architecture and Its Optimization for SoC Testing
IP Quality: A New Model that Faces Methodology and Management Challenges
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations
Realization of efficient RF energy harvesting circuits employing different matching technique
Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise
Performance evaluation of copper and graphene nanoribbons in 2-D NoC structures
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator
Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM
Efficient Delay Calculation in Presence of Crosstalk
A low cost approach to calibrate on-chip thermal sensors
Platform Leadership in the Ambient Intelligence Era
Calibration of on-chip thermal sensors using process monitoring circuits
SolicitudeSavvy: An IoT-based Edge Intelligent Framework for Monitoring Anxiety in Real-time
A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator
When "things" get older: Exploring circuit aging in IoT applications
Towards Automatic and Portable Data Loading Template Attacks on Microcontrollers
Thermal-Aware Placement for FPGAs Using Electrostatic Charge Model
Battery State of Health Estimation Using LLM Framework
Obstacle-Aware Synthesis of the Bus Topology Considering Wire Length Minimization
Efficient nanoscale VLSI standard cell library characterization using a novel delay model
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects
Multi-programming environment for structure under pads (SUP) and via arrays pattern recognition automated classification system
Tipping Point for New Design Technologies: DFM, Low Power and ESL
A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation
Plenary Speech 1P1: Shrinking time-to-market through global value chain integration
LibApprox: A Comprehensive Library for Performance Efficient Approximate Circuits
On testing physically unclonable functions for uniqueness
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor
Performance evaluation considering mask misalignment in multiple patterning decomposition
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation
Reliability-aware and energy-efficient synthesis of NoC based MPSoCs
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation
A dual-level adaptive supply voltage system for variation resilience
Physically-Based Simulation of Electromigration Induced Failures in Copper Dual-Damascene Interconnect
Tabu search based cells placement in nanofabric architectures with restricted connectivity
Timing yield estimation of digital circuits using a control variate technique
Bit error rate estimation in SRAM considering temperature fluctuation
TSV-aware topology generation for 3D Clock Tree Synthesis
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously
Unleashing Energy-Efficiency: Neural Architecture Search without Training for Spiking Neural Networks on Loihi Chip
Active decap design considerations for optimal supply noise reduction
Accelerated Machine Learning for On-Device Hardware-Assisted Cybersecurity in Edge Platforms
Single-Electronics - How It Works. How It's Used. How It's Simulated (invited)
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
Speed-path analysis for multi-path failed latches with random variation
Model analysis of multi-finger MOSFET layout in ring oscillator design
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
On Securing Scan Obfuscation Strategies Against ScanSAT Attack
Quality of Electronic Design: From Architectural Level to Test Coverage
Question: DRC or DfM ? Answer: FMEA and ROI
Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive Survey
Low capture power dictionary-based test data compression
A More Effective C EFF
Infineon Platform for SoC IO Ring and Package Design
FPGA implementation of modeling attack resistant arbiter PUF with enhanced reliability
Passive Modeling of Interconnects by Waveform Shaping
Metrics for characterizing machine learning-based hotspot detection methods
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow
An Effective Current Source Cell Model for VDSM Delay Calculation
Welcome to ISQED 2010
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects
Recent Progress and Remaining Challenges in Pattern Transfer Technologies for Advanced Chip Designs
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron
The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron
Tutorial 4: Robust System Design in Scaled CMOS
Unreachable code identification for improved line coverage
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012
Optimal microarchitectural design configuration selection for processor hard-error reliability
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications
Preemptive built-in self-test for in-field structural testing
Digital IP protection using threshold voltage control
Does Q=MC2? (On the Relationship between Quality in Electronic Design and the Model of Colloidal Computing, invited)
Lagrangian relaxation based register placement for high-performance circuits
Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria
A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS
Performance Driven OPC for Mask Cost Reduction
Variability aware modeling of SoCs: From device variations to manufactured system yield
Constraint analysis and debugging for multi-million instance SoC designs
A High Performance, Scalable Multiplexed Keeper Technique
Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology
FastMem: A Fast Architecture-aware Memory Layout Design
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference
IR Drop Reduction via a Flip-Flop Resynthesis Technique
Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations
Power aware placement for FPGAs with dual supply voltages
Vertical Slit Field Effect Transistor in ultra-low power applications
A New Method of Implementing Hierarchical OPC
Optimization of Individual Well Adaptive Body Biasing (IWABB) Using a Multiple Objective Evolutionary Algorithm
Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique
Power-aware IoT based Smart Health Monitoring using Wireless Body Area Network
Min-cut based leakage power aware scheduling in high-level synthesis
Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology
Binary adder circuit design using emerging MIGFET devices
Trojan detection in digital systems using current sensing of pulse propagation in logic gates
Peephole Optimization for Quantum Approximate Synthesis
RECminThrash: Recency and Eviction Count Based Cache Replacement Policy to Minimize Thrashing at the Last Level Caches
False-Noise Analysis Using Resolution Method
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware
Chaogate Parameter Optimization using Bayesian Optimization and Genetic Algorithm
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme
A delay variation and floorplan aware high-level synthesis algorithm with body biasing
Enhancement of incremental design for FPGAs using circuit similarity
Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Combining System Level Modeling with Assertion Based Verification
A High-Speed CNN Hardware Accelerator with Regular Pruning
Promising Directions in Hardware Design Verification (invited)
A method to determine the sensitization probability of a non-robustly testable path
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization
Antenna Violation Avoidance/Fixing for X-clock routing
Parameter-Variation-Aware Analysis for Noise Robustness
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS
Design-for-Manufacture for Multi Gate Oxide CMOS Process
Semiconductors for the next wave in Automotive
System Level Estimation of Interconnect Length in the Presence of IP Blocks
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks
A multi band flexible N-path filter suited for non-contiguous channel aggregation
ATPG for Path Delay Faults without Path Enumeration
Agents and Peer-to-Peer Computing: A Promising Combination of Paradigms
Emergent Structures of Social Exchange in Socio-cognitive Grids
Agents and Peer-to-Peer Computing, Third International Workshop, AP2PC 2004, New York, NY, USA, July 19, 2004, Revised and Invited Papers
What Agents and Peers Have to Offer Each Other: A Partial History of the AP2PC Workshop
Group Formation Among Peer-to-Peer Agents: Learning Group Characteristics
Distributed Multi-layered Network Management for NEC Using Multi-Agent Systems
Information Sharing among Autonomous Agents in Referral Networks
PROSA: P2P Resource Organisation by Social Acquaintances
Multi-agent Interaction Technology for Peer-to-Peer Computing in Electronic Trading Environments
Performance Prediction in Peer-to-Peer MultiAgent Networks
Bayesian Network Trust Model in Peer-to-Peer Networks
Market Models for P2P Content Distribution
A Robust and Scalable Peer-to-Peer Gossiping Protocol
Trustworthy Agent-Based Recommender System in a Mobile P2P Environment
Fuzzy Cost Modeling for Peer-to-Peer Systems
Studying Viable Free Markets in Peer-to-Peer File Exchange Applications without Altruistic Agents
An Agent-Based Approach for Trustworthy Service Location
An O-Telos Provider Peer for the RDF-Based Edutella P2P-Network
Photo Agent: An Agent-Based P2P Sharing System
On Exploiting Agent Technology in the Design of Peer-to-Peer Applications
A Trust Management Scheme in Structured P2P Systems
Modeling and Evaluating Cooperation Strategies in P2P Agent Systems