yusuke1997/dblp-id-title huggingface dataset:
Hardware-Aware Feature Extraction Quantisation for Real-Time Visual Odometry on FPGA Platforms
Advanced Switching Mechanisms for Forthcoming On-Chip Networks
Co-Optimizing Sensing and Deep Machine Learning in Automotive Cyber-Physical Systems
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system
A 3D Time-of-Flight Mixed-Criticality System for Environment Perception
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors
VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption
Building a Better Random Number Generator for Stochastic Computing
Occupancy Grid Fusion of Low-Level Radar and Time-of-Flight Sensor Data
DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS
Consideration of Security Attacks in the Design Space Exploration of Embedded Systems
Area-Time Efficient Self-Checking ALU Based on Scalable Error Detection Coding
Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion
High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic
Analyzing the Impact of Secure CAN Networks on Braking Dynamics of Cooperative Driving
RTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-Based Architectures
27th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, August 28-30, 2024
Hardware Acceleration of Capsule Networks for Real-Time Applications
General Digit-Serial Normal Basis Multiplier with Distributed Overlap
Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical Devices
A Realistic Approach to a Network-on-Chip Cross-Domain Pattern
Flexible Baseband Architectures for Future Wireless Systems
FP-SLIC: A Fully-Pipelined FPGA Implementation of Superpixel Image Segmentation
Run-Time Reconfigurable Array Using Magnetic RAM
A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments
Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links
A high-level tool for the design of custom image processing systems
HDCRAM Proof-of-Concept for Opportunistic Spectrum Access
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits
Modeling a Network Processor Using Object Oriented Techniques
Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems
Specification and Simulation of Microprocessor Operations and Parallel Instructions
Estimating the Utilization of Embedded FPGA Co-Processor
Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software
Digital Forensics, Video Forgery Recognition, for Cybersecurity Systems
A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator
Memory Generation and Power Distribution In SOC
EventIRQ: An Event Based and Priority Aware IRQ Handling for Multi-tasking Environments
VHDL Code Generation from Formal Event-B Models
Hardware Platforms Benchmark For Real-Time Polyp Detection
Measurement, Analysis and Modeling of RTOS System Calls Timing
25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022
Reliable Railway Station System Based on Regular Structure Implemented in FPGA
Evaluating the Model Accuracy in Automated Design Space Exploration
Experimental Evaluation of CPU Performance Features
A Hardware IP-Core for Information Retrieval
Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings
Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture
Model-Driven Design Approach for Building Smart Grid Applications
Toward an OFDM-Based Technique for Electrochemical Impedance Spectroscopy
Reconfigurable Parallel Approximate String Matching on FPGAs
On the Packet-Switched Implementation of a Discrete-Time CNN
Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks
Virtualization of Hardware Accelerators in a Network-on-Chip
24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021
Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches
Distributed Grid Storage by Ordinary House Heating Variations: A Swiss Case Study
Pulse Generation for On-chip Data Transmission
Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAs
A Constraints Programming Approach to Communication Scheduling on SoPC Architectures
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures
Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems
A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains
Investigation on AUTOSAR-Compliant Solutions for Many-Core Architectures
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA
Automatic Hard Block Inference on FPGAs
Digital Late-Transition Metastability Simulation Model
RED-SEA: Network Solution for Exascale Architectures
Pipelining Considerations for an FPGA Case
A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication
Video SIMDBench: Benchmarking the Compiler Vectorization for Multimedia Applications
Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements
Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures
FPGA-based SPHINCS + Implementations: Mind the Glitch
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration
Open-People: Open Power and Energy Optimization PLatform and Estimator
MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC
Merge Logic for Clustered Multithreaded VLIW Processors
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
Fast Reconfigurable Hardware for the M-ary Modular Exponentiation
Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning
RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion
UP2DATE software updating framework compliance with safety and security regulations and standards
Short Distance Wireless, Dense Networks, and Their Opportunities
Minimization of OPKFDDs Using Genetic Algorithms
MPC-Based Speed Tracking for Automated Urban Buses Performing V2I Communications with Traffic Lights *
Reliability Estimation Process
DCP: A New Data Collection Protocol for Bluetooth-Based Sensor Networks
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level
H.264 Color Components Video Decoding Parallelization on Multi-core Processors
Implicit vs. Explicit Resource Allocation in SMT Processors
An Open-Source High-Throughput, Reduced Memory Footprint, Face Detection, Pose Estimation and Landmark Localization System
Towards a Smart Multi-Sensor Ionizing Radiation Monitoring System
Execution Platform Contracts
In vitro Testbed Platform for Evaluating Small Volume Contrast Agents via Magnetic Resonance Imaging
Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs
Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent
An FPGA-Based Embedded System for a Sailing Robot
Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard
Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine
Predictive Resource Management in Energy-constrained Embedded Systems
PRIV-DRIVE: Privacy-Ensured Federated Learning using Homomorphic Encryption for Driver Fatigue Detection
Zenoh: Unifying Communication, Storage and Computation from the Cloud to the Microcontroller
Braking in Close Following Platoons: The Law of the Weakest
Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4
Adaptive Field Strength ScalingL: A Power Optimization Technique for Contactless Reader / Smart Card Systems
Rapid Estimation of Power-Management Unit Overhead from System-Level Specification
Controlling Hardware Synthesis with Aspects
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach
Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM
A Hardware Accelerator for Real Time Simulation of Complex Neuronal Models
Exploiting Quantum Gates in Secure Computation
Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project
Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-Chip
Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks
DevOps for Cyber-Physical Systems: Objectives, Results and Lessons Learned from the Adeptness H2020 Project
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
An Effective Replacement Strategy of Cache Memory for an SMT Processor
Semiconductor and EDA Challenges: Still Lots To Solve!
Memory Requirement Optimization with Loop Fusion and Loop Shifting
Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit Microcontroller
Design of Radiation Hardened RADFET Readout System for Space Applications
Impact of Contention-Aware Placement in Heterogeneous Edge Devices
A Technique for Accelerating Injection of Transient Faults in Complex SoCs
Header Compression in Handel-C - An Internet Application and a New Design Language
Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative
Design and Application of a Scalable Embedded Systems' Architecture with an FPGA Based Operating Infrastucture
Modular Development and Certification of Dependable Mixed-Criticality Systems
Optimization of Equational Specifications Using Genetic Techniques
FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar
Regular Realization of Symmetric Functions Using Reversible Logic
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Path-Based Dynamic Voltage and Frequency Scaling Algorithms for Multiprocessor Embedded Applications with Soft Delay Deadlines
Reversible Logic Synthesis for Minimization of Full-Adder Circuit
Data Footprint Reduction in DNN Inference by Sensitivity-Controlled Approximations with Online Arithmetic
Heterogeneous Communication Virtualization for Distributed Embedded Applications
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification
The Future of Data-Parallel Embedded Systems (Abstract)
Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-Decoders
Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor
Remote Path Delay Fault Simulation
A Novel Memristive-Based Data Reordering Scheme
State Assignment for PAL-based CPLDs
Skeptical Dynamic Dependability Management for Automated Systems
Modeling Battery SoC Predictions for Smart Connected Glasses Simulations
Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions
Adapting EPIC Architecture's Register Stack for Virtual Stack Machines
A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications
Managing a Massively-Parallel Resource-Constrained Computing Architecture
Federated Learning for Obstacle Detection to Assist the Visually-Impaired Using Augmented Reality
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits
Drones for Inspection of Overhead Power Lines with Recharge Function
{2 n +1, s n+k , s n -1}: A New RNS Moduli Set Extension
Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology
Attack Surface Modeling and Assessment for Penetration Testing of IoT System Designs
mcQEMU: Time-Accurate Simulation of Multi-core platforms using QEMU
Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot Navigation
Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware
Simplifying Instruction Issue Logic in Superscalar Processors
VLSI Implementation of a Cryptography-Oriented Reconfigurable Array
Lightweight Security Data Streaming, Based on Reconfigurable Logic, for FPGA Platform
Testability of Switching Lattices in the Cellular Fault Model
Digital Systems Architectures Based on On-line Checkers
Playful Supervised Smart Spaces (P3S) - A Framework for Designing, Implementing and Deploying Multisensory Play Experiences for Children with Special Needs
Information Trans-Coders in Information-Driven Circuit Synthesis
Calibration Method for a CMOS 0.06mm 2 150MS/s 8-bit ADC
Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis
A New Framework for Design and Simulation of Complex Hardware/Software Systems
Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems
Change of Plans: Optimizing for Power, Reliability and Timeliness for Cost-Conscious Real-Time Systems
Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities
A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation
Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA
A 130 nm Event-Driven Voltage and Temperature Insensitive Capacitive ROC
NoC Topologies Exploration based on Mapping and Simulation Models
Evolutionary Algorithm for State Assignment of Finite State Machines
The importance of At-Speed Scan Testing: an industrial experience
Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections
Component-Based Hardware/Software Co-Simulation
PositIV: A Configurable Posit Processor Architecture for Image and Video Processing
Implementation and Verification of the Argo Network-on-Chip in Chisel
Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures
Development of Cyber-Physical Speech-Controlled Wheelchair for Disabled Persons
SEEK: SIP-Based Emergency Embedded Framework Supports Elderly and Disabled to Perform Emergency Calls
HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework
Development of Functional Delay Tests
An Agile and Wideband All-Digital SDR Receiver for 5G Wireless Communications
A Three-Dimensional Integrated Accelerator
Binary-to-RNS Conversion Units for moduli {2^n ± 3}
Low-Power Differential Logic Gates for DPA Resistant Circuits
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents
Side-Channel Leakage Models for RISC Instruction Set Architectures from Empirical Data
Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices
Two-Criterial Constraint-Driven FSM State Encoding for Low Power
Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's
On Lookup Table Cascade-Based Realizations of Arbiters
MPU-based incremental checkpointing for transiently-powered systems
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video
Model-Based Evaluation of System Scalability: Bandwidth Analysis for Smartphone-Based Biosensing Applications
Mixed-Criticality Embedded Systems - A Balance Ensuring Partitioning and Performance
Throughput of Streaming Applications Running on a Multiprocessor Architecture
On the Development of a Runtime Reconfigurable Multicore System-on-Chip
LLM4CVE: Enabling Iterative Automated Vulnerability Repair with Large Language Models
Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip Multiprocessor
Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers
Memory Aware HLS and the Implementation of Ageing Vectors
Systematic Reverse Engineering of Cache Slice Selection in Intel Processors
The AQUAS ECSEL Project
Fault-Tolerant Lightweight High Level Architecture
CPU-GPU Layer-Switched Low Latency CNN Inference
Challenges in Deeply Heterogeneous High Performance Systems
Memristor-Based Lightweight Encryption
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism
A holistic hardware-software approach for fault-aware embedded systems
Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks
Dependability Prediction Involving Temporal Redundancy and the Effect of Transient Faults
A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography
Compilation Technique for Loop Overhead Minimization
Easy SoC Design with VCI SystemC Adapters
Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems
Studying OpenCL-based Number Theoretic Transform for heterogeneous platforms
RailCheck: A WSN-Based System for Condition Monitoring of Railway Infrastructure
Reconfigurable Computing: A New Business Model and its Impact on SoC Design
Distributing SoC Simulations over a Network of Computers
EMC2 a Platform Project on Embedded Microcontrollers in Applications of Mobility, Industry and the Internet of Things
How are Industry 4.0 Reference Architectures Used in CPPS Development?
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications
Description-Level Optimisation of Synthesisable Asynchronous Circuits
Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGA
A Flexible Architecture for H.263 Video Coding
Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network
The Accuracy and Efficacy of Real-Time Compressed ECG Signal Reconstruction on a Heterogeneous Multicore Edge-Device
Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias
Exploring Fault Injection Attacks on CVA6 PMP Configuration Flow
Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors
Adaptive Reliability for Fault Tolerant Multicore Systems
On the Feasibility of using FPGA's for Efficient Topology Optimization
EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off
An FPGA Architecture for Authentication and Key Agreement Protocol for 5G Networks
Performance Targeted Minimization of Incompletely Specified Finite State Machines for Implementation in FPGA Devices
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks
Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan Attacks
Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture
Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms
Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel Attacks
Techniques for Formal Verification of Digital Systems: A System Approach
On Precise Fault Localization and Identification in NoC Architectures
A Reconfigurable Fractional Interpolation Hardware for VVC Motion Compensation
Side Channel Evaluation of PUF-Based Pseudorandom Permutation
An Implementation of an Address Generator Using Hash Memories
Function Call Optimization in Behavioral Synthesis
Characterizing Intrusion Detection Systems On Heterogeneous Embedded Platforms
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures
An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation
A Versatile Emulator for the Aging Effect of Non-volatile Memories: The Case of NAND Flash
An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles
NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes
Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis
Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic
Deductive Fault Simulation for Asynchronous Sequential Circuits
Adjustable self-healing methodology for accelerated functions in heterogeneous systems
Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment
PREEMPT-K8S: Pod Prioritization for Mixed-Criticality Edge-Cloud Services
SOC Power Management Strategy Based on Global Hardware Functional State Analysis
Lightweight Performance Monitoring of Real-Time Applications in RISC-V Platforms
A Markovian Decision Process Analysis of Experienced Agents Joining Ad-Hoc Teams
Cross-Layer Early Reliability Evaluation for the Computing cOntinuum
Verification of Robotic Surgery Tasks by Reachability Analysis: A Comparison of Tools
The M2DC Project: Modular Microserver DataCentre
Energy Characterization and Classification of Embedded Operating System Services
PET-to-MLIR: A polyhedral front-end for MLIR
Mapping of High-Level SDL Models to Efficient Implementations for TinyOS
A Subplatooning Strategy for Safe Braking Maneuvers
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
How Microprobing Can Attack Encrypted Memory
Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support
Message from the General Chair DSD 2023
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels
Hardware Trojan Protection for Third Party IPs
PRUS - Processor Network for Digital Circuit Implementation
Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing
On the Bright Side of Darkness: Side-Channel Based Authentication Protocol Against Relay Attacks
Digital Implementation of a BIST Method based on Binary Observations
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures
Optimization of Electronic Power Consumption in Wireless Sensor Nodes
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow
A Glimpse of SmartHG Project Test-bed and Communication Infrastructure
Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers
On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs
Assertion-Based Verification for SoC Models and Identification of Key Events
Synthesis of ASM-based Self-Checking Controllers
Virtual Switch Supporting Time-Space Partitioning and Dynamic Configuration for Integrated Train Control and Management Systems
Clock-Gating in FPGAs: A Novel and Comparative Evaluation
Functional Verification of RTL Designs driven by Mutation Testing metrics
In-channel Flow Control Scheme for Network-on-Chip
A Low-Area Reference-Free Power Supply Sensor
UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems
Testable Design Verification Using Petri Nets
Scalable FPGA Accelerator of the NRM Algorithm for Efficient Stochastic Simulation of Large-Scale Biochemical Reaction Networks
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices
Maximizing Resource Utilization by Slicing of Superscalar Architecture