yusuke1997/dblp-id-title huggingface dataset:
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist
An Evolutionary Scheme for Cosynthesis of Real-Time Systems
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
A New Approach to Analyze a Sub-micron CMOS Inverter
Designing Leakage Aware Multipliers
A graph approach to DFT hardware placement for robust delay fault BIST
A Fully Autonomous 1.2A Auxiliary Buck DC-DC Converter for Fast Transient Load-on-Demand
Using Level Restoring Method for Dual Supply Voltage
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits
On the Effect of Aging on Digital Sensors
Towards a Fully Autonomous UAV Controller for Moving Platform Detection and Landing
Dual-Edge Triggered Static Pulsed Flip-Flops
OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application
LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications
Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits
Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices
Reasoning about the Trends and Challenges of Engineering Design Automation
System Aspects of Analog to Digital Converter Designs
Accelerating Fluid Loading in Sample Preparation with Fully Programmable Valve Arrays
Incremental Autojogging using Range Spaces
Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
Novel Variability Aware Path Selection for Self-Referencing Based Hardware Trojan Detection
Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions
Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline
Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters
A low power video encoder with power, memory and bandwidth scalability
Constraint Driven Pin Mapping for Concurrent SOC Testing
Self-Awareness in Cyber-Physical Systems
On Optimum Cell Models for Over-the-Cell Routing
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator
Improving Concurrency for Cosine-modulated Filterbank Windowing
Tutorial T7B: Network on Chips - The Journey Overview
An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs
High Gain Capacitance Sensor Interface for the Monitoring of Cell Volume Growth
Carry Circuitry for LUT-Based FPGA
Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip
Optimization of Global Interconnects in High Performance VLSI Circuits
Use of CMOS Technology in Wave Pipelining
NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks
An Efficient VLSI Architecture for Discrete Hadamard Transform
An efficient automatic test generation system for path delay faults in combinational circuits
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges
A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology
A Verification System for Transient Response of Analog Circuits Using Model Checking
Tutorial T8A: Automated Application Engine Synthesis from C Algorithms
Improvements to Negative-C Compensation Based Amplifiers for Broadband Applications
FPGA Implementation of Power Management Algorithm for Wind Energy Storage System with Kalman Filter MPPT Technique
Interface Design Techniques for Single-Chip Systems
Post-Silicon Validation and Diagnosis
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing
Gigachip Technology and the Signal Processing Revolution
The Dawn of 22nm Era: Design and CAD Challenges
Supply Noise and Peak Current Reduction in High-Speed Output Drivers
Modeling RTOS for Reactive Embedded Systems
Automatic Component Matching Using Forced Simulation
Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing
A Visual Approach for Asynchronous Circuit Synthesis
Exclusive Test and its Applications to Fault Diagnosis
A Framework for Low Power Audio Design
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs
Embedded Support Vector Machine : Architectural Enhancements and Evaluation
A Multiply Accumulator for Stochastic Numbers Without Scaling Errors
Trustworthy Cyber Physical Systems
Interconnect Optimization Techniques in Data Path Synthesis
A CMOS Low Voltage Charge Pump
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage
Low Power Configurable Readout Integrated Circuit for Infrared Detector
Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs
VaWiRAM: a variable width random access memory module
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks
An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors
Functional Broadside Tests with Different Levels of Reachability
Coverage of Bridging Faults by Random Testing in I DDQ Test Environment
Application of GF(2p) CA in Burst Error Correcting Codes
A Noise Aware CML Latch Modelling for Large System Simulation
Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown System
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI
A Digitally Assisted Radiation Hardened Current Steering DAC
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip
Moore's Law is Unconstitutional
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor
Optimizing Bandwidth Utilization Through Word Based Compression in Main Memories
Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier
Power-Efficient Asynchronous Design
Lossy Compression of Images Using Logic Minimization
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
A Novel Encoding Scheme for Low Power in Network on Chip Links
Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects
Enhancing Hardware Trojan Security through Reference-Free Clustering using Representatives
Transition Activity Estimation for General Correlated Data Distributions
Path Based Approach for Crosstalk Delay Analysis
Design Challenges in Sub-100nm High Performance Microprocessors
Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies
A Power Minimization Technique for Arithmetic Circuits by Cell Selection
Heuristic Technology Mapper For Lut Based Fpgas
EDA Made-in-India: Fact or Fiction?
Mathematical Methods in VLSI (Tutorial Abstract)
An Integrated CMOS RF Energy Harvester with Differential Microstrip Antenna and On-Chip Charger
Simultaneous Circuit Transformation and Routing
On Minimization of Test Application Time for RAS
Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications
Thermal Load-aware Adaptive Scheduling for Heterogeneous Platforms
A Hardware Scheduler for Real Time Multiprocessor System on Chip
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation
A Novel Scheme for Designing Error Correcting Codes Using Cellular Automata
Design Considerations of a Sub-50 Mu-W Receiver Front-end for Implantable Devices in MedRadio Band
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation
Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis
Simulation and Synthesis of VLSI Communication Systems
Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning
Translation of Array Expressions for in-Memory Computation on Memristive Crossbar
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs
A Pipeline Architecture for Encompression (Encryption + Compression) Technology
Finite State Machines: A Deeper Look into Synthesis Optimization for VHDL
Synthesis of Dual-VT Dynamic CMOS Circuits
SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement
Optimal Retiming for Initial State Computation
Hybrid Testing Schemes Based on Mutual and Signature Testing
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture
Low power realization of FIR filters using multirate architectures
Graph Transformations for Improved Tree Height Reduction
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm
Wave pipelined architecture folding: a method to achieve low power and low area
An Efficient Scan Tree Design for Compact Test Pattern Set
A Simulation Methodology for Software Energy Evaluation
Impact of Device Aging on Early Mode Failures in Pulsed Latches
Battery Model for Embedded Systems
Smart Port Allocation for Adaptive NoC Routers
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment
A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment
H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors
Embedded tutorial - Can silicon machines match the efficiency of the human brain?
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract)
A Novel Approach for Assisting Blind People Using a Smart Wearable Device
A Soft RISC-V Vector Processor for Edge-AI
Robust Circuit Design: Challenges and Solutions
Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders
MAGIC-Based High-Speed Adders for in-Memory Computing Using Memristors
A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET
All-Printed RFID Tags: Materials, Devices, and Circuit Implications
X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology
Exceptional ASIC: Through Automatic Timing Exception Generation (ATEG)
A Wide-Band Receiver Front-End with Programmable Frequency Selective Input Matching
Evolution of Oscillation in a Quadrature Oscillator
Analog IC Design in Nanometer CMOS Technologies
An Asynchronous Interconnect Architecture for Device Security Enhancement
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V
Low Shift and Capture Power Scan Tests
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs
An event driven approximate bio-electrical model generating surface electromyography RMS features
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs
A First-Principles-Based Comparative Study Between Pristine and Au-Modified Graphene Nanosheet Towards Acetaldehyde Sensing Performance
Variability-Aware Thermal Simulation using CNNs
Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet Architectures
Design of Dedicated Reversible Quantum Circuitry for Square Computation
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array
Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown
Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders
Design, Testing, and Applications of Digital Microfluidics-Based Biochips
Identifying the Bottlenecks to the RF Performance of FinFETs
A High Efficiency Body Injected Differential Power Amplifier at 2.4GHz for Low Power Applications
An Attack Resilient PUF-based Authentication Mechanism for Distributed Systems
A Power Efficient Video Encoder Using Reconfigurable Approximate Arithmetic Units
Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter
Vlsi Architectures For High-Speed Map Decoders
A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture
A Hierarchical Cost Tree Mutation Approach to Optimization of Analog Circuits
CAD Tools Pathway in Hardware Security
Transformations for functional verification of synthesized designs
RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICs
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
System Level Testability Issues of Core Based System-on-a-Chip
Fault-Tolerant Arbitration in Multichip Crossbar Switches
Simulated Annealing Based Parallel State Assignment of Finite State Machines
0.36 nJ/bit MedRadio Band OOK Transmitter for Wearable Healthcare Applications
Game Theory-Based Parameter-Tuning for Path Planning of UAVs
Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces
A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX Applications
A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications
Automated Debugger for Optimum Physical Clock Structure Targeting Minimal Latency
Weight-Based Bus-Invert Coding for Low-Power Applications
Tutorial: Delay Fault Models and Coverage
Dynamic Keeper for 1R1W 8T-SRAM to Enable Read Operation at 150c till 0.5v in 5nm FinFET
23.97GHz CMOS Distributed Voltage Controlled Oscillators with Inverter Gain Cells and Frequency Tuning by Body Bias and MOS Varactors Concurrently
A Statistical Model for Hybrid Wireless Network on Chip
A 6V to 42V High Voltage CMOS Bandgap Reference Robust to RF Interference for Automotive Applications
LO-SC: Local-Only Split Computing for Accurate Deep Learning on Edge Devices
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits
Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences
DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs
Optical Lithography Simulation with Focus Variation using Wavelet Transform
Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs
An Effective Timing-Driven Placement Algorithm For Macro Cells
Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling Model
An Optical Reconfiguration System with Four Contexts
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters
Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
The Pentium processor-90/100, microarchitecture and low power circuit design
Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver
A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis
In-memory realization of SHA-2 using ReVAMP architecture
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence
Oversampling Analog-to-Digital Converter Design
A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions
Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins
A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems
Low Power Realization of Residue Number System Based FIR Filters
FPGA based convolution and memory architecture for Convolutional Neural Network
LATCHECK: A Latchup Checker for VLSI Layouts
A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture
Practical Test and DFT for Next Generation VLSI
Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs
A New algorithm for combined PLA folding
Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST
SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects
Convergence Issues in Resonant Tunneling Diode Circuit Simulation
Unified Challenges in Nano-CMOS High-Level Synthesis
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
Hardware Software Co-Design of Embedded Systems
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Keynote Address: The Networked Society - Enabled by DSP Solutions
Efficient Grouping of Fail Chips for Volume Yield Diagnostics
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
Topological Analysis for Leakage Prediction of Digital Circuits
Design of a VLSI parallel processor for fuzzy computing
LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era
33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020
KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA
Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs
Test Time Minimisation in Scan Compression Designs Using Dynamic Channel Allocation
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell
Nexperia Computing Architecture for Connected Consumer Applications
HARVEST: Towards Efficient Sparse DNN Accelerators using Programmable Thresholds
Fast Algorithms for Computer IDDQ Tests for Combination Circuits
High Performance MCM Routing: A New Approach
Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature
Application of DC Analyzer to Combinatorial Optimization Problems
Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC
A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems
A Run-Time Reconfigurable System for Gene-Sequence Searching
Synthesizability of 3 Party Formal Specifications-Does My Controller See Enough?
Instruction Controlled In-memory Sorting on Memristor Crossbars
Prospects of Near-Threshold Voltage Design for Green Computing
MEMS: Technology, Design, CAD and Applications (Tutorial Abstract)
PositGen-A Verification Suite for Posit Arithmetic
Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
Synchronous Methodology for Designing Hardware, Software and Mixed Embedded Systems
Hybrid OPC Technique for Fast and Accurate Lithography Simulation
Synthesis of Initializable Asynchronous Circuits
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
Top-Down Approach to Technology Migration for Full-Custom Mask Layouts
A 800 MHz System-on-Chip for Wireless Infrastructure Applications
DFM / DFT / SiliconDebug / Diagnosis
FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio Input
Design of a 1 V Low Power 900 MHz QVCO
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
Specification and Design of Multi-Million Gate SOCs
Design, Analysis, and Implementation of Analog Complex Filter for Low-IF Wireless LAN Application
Dynamic Power Management for Microprocessors: A Case Study
29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
Power-Aware, Reliable Microprocessor Design
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
Test Solution for OTA Based Analog Circuits
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
Modeling VHDL in Multiclock ESTEREL
Open Computation Tree Logic for Formal Verification of Modules
A Novel Low Power 16X16 Content Addressable Memory Using PA
Defect-Aware Synthesis of Droplet-Based Microfluidic Biochips
Computer Aided Test (CAT) Tool for Mixed Signal SOCs
High-Speed Interconnect Technology: On-Chip and Off-Chip
The Future of NoCs: New Technologies and Architectures
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read
A Low Power Multi-channel Input Delta-Sigma ADC without Reset
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model
Optimal Respiratory Rate Estimation with mmWave Sensing Using PYNQ System-on-Chip Platform
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and Biosensors
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms
KANSYS: a CAD tool for analog circuit synthesis
Handling Constraints in Multi-Objective GA for Embedded System Design
Functional Test Generation for Sequential Circuits
Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by Mode
Analysis of the Effects of Crosstalk Errors on Various Quantum Circuits
Safe-ERfair
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing
Trends in Communication Technology and its Impact on Semiconductor
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications
Tutorial T7A: New Modeling Methodologies for Thermal Analysis of 3D ICs and Advanced Cooling Technologies of the Future
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures
Optimization of Test Accesses with a Combined BIST and External Test Scheme
Automated Architectural Optimization of Digital FIR Filters
MS 3 : Micro-Rollback and Self-Recovery System Synthesis
Improving Android Performance and Energy Efficiency
A Practical Approach to Layout Optimization
Reversible Logic Synthesis with Output Permutation
A Path Sensitization Technique for Testing of Switched Capacitor Circuits
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects