yusuke1997/dblp-id-title huggingface dataset:
A 10 $\mu \mathrm{W}-74.6\mathrm{dB}$ THD Arterial Pulse Waveform Sensing System with Automatic Bridge-Offset Calibration and Super Class-AB Output Stage
Architecture Challenges for Heterogeneous Processors in Embedded SoCs
A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications
Flexible global carbon pricing study: A new method to establish the international cooperation on reducing carbon emission
A 5.92-Mb/mm 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry
A 95% accurate EEG-connectome processor for a mental health monitoring system
EV bus system control strategy design with consideration of battery lifetime model
An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC
Implementation an adaptive fuzzy NARX controller for MPPT PV supplied DC pump motor
An Energy-Efficient Composite Phase Shift 16-QAM Frequency Multiplying TX Achieving a 3.4% EVM in 65nm CMOS
A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet
2-20-V Wide Input Range Active Rectifier with Single-Multiplexing Adaptive Delay Compensation and Low-Voltage Enhancement for Wireless Power Transmission
A Neural Stimulation IC Based on a Reconfigurable Current DAC with In-Situ Neural Recording Function for Cochlear Implant Systems
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability
A continuous-time ΣΔ modulator with a Gm-C input stage, 120-dB CMRR and -87 dB THD
Parameters determination for a.c. voltage and current waveforms: IEC 61083-4 TDG Waveform analyses
A 2-Electrode ECG Amplifier with 0.5% Nominal Gain Shift and 0.13% THD in a 530mVpp Input Common-Mode Range
A 28.2 μC Neuromorphic Sensing System Featuring SNN-based Near-sensor Computation and Event-Driven Body-Channel Communication for Insertable Cardiac Monitoring
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS
A 2pA/√Hz Current-Conveyor-Assisted Ultrasound Receiver with 25pF CMUT Parasitic Capacitance
A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER -6
An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training
A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM
EQSCALE: Energy-quality scalable feature extraction engine for Sub-mW real-time video processing with 0.55 mm 2 area in 40nm CMOS
A D-Band ASK Transmitter with 50GHz RF Bandwidth and Multi-Mode Interface Implemented in 28nm CMOS
A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM
A Programmable 6T SRAM-Based PUF with Dynamic Stability Data Masking
Power split of fuel cell/ultracapacitor hybrid power system by backstepping sliding mode control
A Millimeter-Scale Computing System with Adaptive Dynamic Load Power Tracking
The design of switched reluctance motor variable-speed system based on digital signal controller
A Low-Noise Sub-Bandgap Reference with a ±0.64% Untrimmed Precision in 16nm FinFET
Application of soft start in charging storage battery of PV system
DPe-CIM: A 4T1C Dual-Port eDRAM Compute-in-Memory for Simultaneous Computing and Refresh with Adaptive Refresh and Data Conversion Reduction Scheme
A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm
A 10kHz-BW 93.7dB-SNR chopped ΔΣ ADC with 30V input CM range and 115dB CMRR at 10kHz
An area effective forward/reverse body bias generator for within-die variability compensation
Automatic extraction method suitable for deriving load model parameters
A 24-to-32GHz series-Doherty PA with two-step impedance inverting power combiner achieving 20.4dBm Psat and 38%/34% PAE at Psat/6dB PBO for 5G applications
A 2D Beam-Steerable 252-285-GHz 25.8-Gbit/s CMOS Receiver Module
Auto-Calibration Technique for Current-Based Bandgap Voltage Reference
AC voltage sensorless control of battery charger system in electric vehicle applications
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs
A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS
A 1.1mW hybrid OFDM ground effect-resilient body coupled communication transceiver for head and body area network
A 0.012 mm2, $1.5 \mathrm{G}\Omega$ ZIN Intrinsic Feedback Capacitor Instrumentation Amplifier for Bio-Potential Recording and Respiratory Monitoring
A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT
Energy efficient computing in nanoscale CMOS: Challenges and opportunities
Shunt capacitor renewal planning through cost leveling strategy using condition age model
An 8-bit 20.2fJ/conv-step FoM CI-C Asynchronous SAR ADC with Common-mode Level Shifting
A 95pJ/label Wide-Range Depth-Estimation Processor for Full-HD Light-Field Applications on FPGA
Fully-integrated AMLED micro display system with a hybrid voltage regulator
A 2.85mm 2 RF Transceiver in 40nm CMOS for IoT Micro-Hub Applications
An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier
220GHz wide-band MEMS switch in standard BiCMOS technology
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F 2 and K-means Clustering for Power Reduction
An 8.5ps Resolution, $2000\mu\mathrm{m}^{2}$ Phase-Domain Delta-Sigma TDC for Lidar Applications
A 2.4GHz low-power SAW-less receiver for SoC coexistence
A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces
A reconfigurable dual-band WiFi/BT combo transceiver with integrated 2G/BT SP3T, LNA/PA achieving concurrent receiving and wide dynamic range transmitting in 40nm CMOS
A 173-200 GHz quadrature voltage-controlled oscillator in 130 nm SiGe BiCMOS
99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system
A 3-to-40 GHz 64QAM/256QAM/4096QAM Zero-IF CMOS Transceiver Chipset for Millimeter-wave Software-defined Radios
A Multi-phase Series-Parallel with Bond Wire Auxiliary Fully-Integrated 250pF Switched-Capacitor with 13.6mV output ripple for Supplying Temperature Sensor with 0.1°C Accuracy to Early Detect COVID-19
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse
Simplified loop-type fuzzy feeder models for distribution system calculations
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter
Ouput power smoothening of variable-speed wind turbine systems by pitch angle control
A K-band pulse radar transceiver with highly digital closed-loop time-of-flight measurement
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm
Compact Hybrid Strong SOIPUF Exploiting Secret Key Generation and Dual-Edge Response Extraction for Enhanced Modeling Attack Resistance
Co-optimization targeting future interconnection
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS
A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs
A 5-GHz 0.15-mm 2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process
Triangular approximate distribution model of wind electric generators
A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonators
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit
A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation
A 16nm 231mW Channel MLP Optimized Neural Processing Unit for 80.3% Top-1 ImageNet Classification Accuracy at 102fps
Transmission lines operating reliability evaluation based on real-time power flow
A nMOS-Only Pulse-Width Modulation CMOS Imager with Body Effect Mitigation Using Differential Comparison Technique
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm
A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX
A wide load and voltage range switched-capacitor DC-DC converter with load-dependent configurability for DVS implementation in miniature sensors
A Digital Multiphase Converter with Sensor-less Current and Thermal Balance Mechanism
A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control
A process scalable voltage-reference-free temperature sensor utilizing MOSFET threshold voltage variation
RF transconductor linearization technique robust to process, voltage and temperature variations
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS
Fully Integrated Reconfigurable Solar Energy Harvester for $100\mu\mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm 2
An energy-efficient super-regenerative ASK receiver with a ΔΣ-based pulse-width demodulator
A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector
Investigation on solar PV and battery system penetration in Singapore distribution power networks
A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network
0.6 V 8.1/0.2µW Ultra-Low-Power Logarithmic Power Detectors Employing Subthreshold MOS Transistors
An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier
A High-Performance Low Complexity All-Digital Fractional Clock Multiplier
A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier
CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays
A 639.38GOPS Hybrid-Domain Logic-Compatible Multi-Level Embedded Flash Computing-in-Memory Macro with Spike-Edge Computation
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators
Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping
A research for time-varying power in power electric power system
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability
A 5.5GHz 0.84TOPS/mm 2 neural network engine with stream architecture and resonant clock mesh
A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell
A Fully Integrated 400MHz Band Transceiver with a 96Mbps 16QAM Transmitter and a Phase Tracking Receiver in 40-nm CMOS
Assessment of the impact that individual voltage source has on a generator's stability
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach
Efficient trust node aware routing in ZigBee communication network of smart grid
A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix
Autonomous appliance scheduling based on time of use probabilities and load clustering
OPF computer program for reactive power dispatch
Control of a 3-phase 4 wire grid connected converter with active power filter and var compensation functionality for nonlinear loads
A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique
A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS
245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining
A 87.2%-Efficiency 27.12MHz Current-Mode Wireless Power Receiver with Ramp-Assisted Energy Delivery Controller for Implantable Devices
FlashMAC: An Energy-Efficient Analog-Digital Hybrid MAC with Variable Latency-Aware Scheduling
A power efficient frequency shaping neural recorder with automatic bandwidth adjustment
A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOS
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems
A 0.13-μm HBT divide-by-6 injection-locked frequency divider
A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology
A 1V fractional-N PLL with nonlinearity-insensitive modulator
Fast memory and storage architectures for the big data era
A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor
A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology
A DCM ZVS Class-D Power Amplifier for Wireless Power Transfer Applications
The Second Generation Intel® Core™: A highly integrated high performance multi IA-core and processor graphics chip
Hardware Architecture for Fast General Object Detection using Aggregated Channel Features
124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking
A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller
A 23-mW 60-GHz Differential Sub-Sampling PLL with an NMOS-Only Differential-Inductively-Tuned VCO
Direct-Conversion Receiver Front-End for 180 GHz with 80 GHz Bandwidth in 130nm SiGe
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage
Assessment of effects of capacitor banks on harmonic distortion by a direct Z-bus power flow method
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode
31.3 μs/Signature-Generation 256-bit 픽p ECDSA Cryptoprocessor
An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery
A Ka-Band CMOS Phase-Inverting Amplifier with 0.6 dB Gain Error and 2.5° Phase Error
A Real-Time Event Vision Sensor based Object Detection and Tracking System for Edge Applications
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring
A 0.0006-mm 2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS
Dynamic study of a battery change-over scheme of a windfarm containing dual BESS
A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shaping
A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure
Medical electronics - A challenging research and industry frontier
A battery-less 31 µW HBC receiver with RF energy harvester for implantable devices
An isolated PoR based pulse generator for TEG energy harvesting with minimum startup of 150 mV and maximum series resistance of 600 Ω
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
Maximum allowable distributed generation considering fault ride through requirement and reach reduction of utility relay
A 16.6μW 32.8MHz monolithic CMOS relaxation oscillator
A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas
A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy
A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics
Open the New World of 5G
A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency
A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers
A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface
A 1kHz-to-62MHz 2.06zFrms Resolution Lock-in Amplifier with SAR-assisted Parasitic and Baseline Capacitance Compensation
A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS
A 200Gb/s, 3.5pJ/bit Monolithically Integrated WDM SiPhotonic Transceiver for Chiplet Optical I/O
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology
0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications
Where do Innovations stem from?: Further Innovations Beyond Silicon Technology
A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop
A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator
A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS
A Physically Unclonable Function with 0% BER Using Soft Oxide Breakdown in 40nm CMOS
A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications
A 132dB DR readout IC with pulse width modulation for IR focal plane arrays
A 26.5-to-29.5GHz Transformer-Based Doherty Phased-Array Transceiver Front-End With 7-Bit Phase Shifter and 16% Back-Off Drain Efficiency
A Jitter-Tolerant Referenceless Digital-CDR for Cellular Transceivers
A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS
A 0.57°/h bias instability 0.067°/√h angle random walk MEMS gyroscope with CMOS readout circuit
A 1.2 V 2.3 µW 94.7 dB DR Delta-Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC
Maintaining New Zealand's electrical reserve management tool
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation
A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback
Main-steam temperature control for ultra-supercritical unit using Multi-Model Predictive strategy
A 1448-Mpixel/s, 84-pJ/Pixel Display Stream Compression Encoder in 28 nm for 4K Video Resolution
An Area and Power Efficient Fully Nonlinear 10-bit Column Driver with Time-Shared Multi-Gamma-Slope DAC and Time-Interleaved Sampling Buffer for Mobile AMOLEDs
A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation
MSN: Battery-Less Multiple Subcarrier Multiple Access Sensor Node with Full-Duplex Backscatter Concurrent Data Streaming
IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017
A 226 GHz Coupled Harmonic VCO with 9.34% Tuning Range Utilizing Three-Coil Transformer with Switched Inductor in 65nm CMOS
A 0.9V CMOS Voltage Reference with 0.41% Untrimmed Accuracy and 44.7 ppm/°C TC from -35°C to 130°C
A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS
A 918MHz Wide-Range CMOS Rectifier with Diode-Feeding and Switch-Capacitor-Based Load Modulation Technique
22-nm Data Backup SRAM Using 3.3V IO MOSs with Ultralow-Voltage-Drop Erasure Technique for Secure IoT Applications
A 0.6 V-2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags
A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications
An ultra-low phase noise all-digital multi-frequency generator using injection-locked DCOs and time-interleaved calibration
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS
A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices
Finite control on wind power ramping event
A 5.37-TSOPS/W Reconfigurable Neuron Array with Dual-mode Neurons and Asynchronous Synapses for Energy-Efficient Inference and Biological Neural Network Simulation
Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash Memory
A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation
Simulation of lightning-transient responses of grounding systems using the RBF-FDTD method
A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range
A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS
A 280.580 μm 2 /Grid, 30.7pJ TMRA-PIM (Time-Multiplexed Random-Access Processing-in-Memory) Programmable Accelerator for Partial Differential Equations Solving and Edge Processing
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction
PWM AC chopper control schemes for energy saving of single-phase induction motors
A 16.1-b ENOB 0.064mm 2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS
A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase Detector
System frequency control using multi-step smart charging of electric vehicles
A 0.6-V 200-kbps 429-MHz ultra-low-power FSK transceiver in 90-nm CMOS
CMOS THz transmissive imaging system
A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications
A Wireless Battery-Free Cerebral-Oxygen-Monitoring Micro-System Featuring 0.028% Sensing Resolution
A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration
A 0.011 mm 2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI
On-chip spur and phase noise cancellation techniques