yusuke1997/dblp-id-title huggingface dataset:
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
Disjoint eager execution: an optimal form of speculative execution
A variable-pipeline on-chip router optimized to traffic pattern
JetStream: Graph Analytics on Streaming Data with Event-Driven Hardware Accelerator
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling
Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture
The Performance Potential of Data Dependence Speculation & Collapsing
Parallel application memory scheduling
Low-power, high-performance analog neural branch prediction
AutoFL: Enabling Heterogeneity-Aware Energy Efficient Federated Learning
Applications of pipelining to firmware
CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs
TIP: Time-Proportional Instruction Profiling
Memory Prefetching Using Adaptive Stream Detection
Performance analysis and design methodology for a scalable superscalar architecture
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor
TransCom: transforming stream communication for load balance and efficiency in networks-on-chip
Preventing PCM banks from seizing too much power
The derivation of microcode by symbolic execution
Continuous, Low Overhead, Run-Time Validation of Program Executions
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs
Efficient kernel synthesis for performance portable programming
In Memory of Bob Rau
ALPS: An Algorithm for Pipeline Data Path Synthesis
The PRIM system: An alternative architecture for emulator development and use
Exceeding the Dataflow Limit via Value Prediction
Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach
Algorithm implementation on specific microprogrammed structure
SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions
Understanding the Differences Between Value Prediction and Instruction Reuse
TRINE: A Tree-Based Silicon Photonic Interposer Network for Energy-Efficient 2.5D Machine Learning Acceleration
Chainsaw: Von-neumann accelerators to leverage fused instruction chains
Cambricon-R: A Fully Fused Accelerator for Real-Time Learning of Neural Scene Representation
An algorithm for selection of migration candidates
A study of pointer aliasing for software pipelining using run-time disambiguation
Locality-Centric Data and Threadblock Management for Massive GPUs
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures
Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem
Self-regulation of workload in the Manchester Data-Flow computer
A microprogrammed interpreter for concurrent Euclid
An interactive debugger for software and firmware
Wire-Aware Architecture and Dataflow for CNN Accelerators
Ordering decoupled metadata accesses in multiprocessors
The use of a meta-assembler to design an M code interpreter on AMD2900 chips
Microprogramming with statements of higher-level languages
Hybrid analog-digital solution of nonlinear partial differential equations
Architecting a chunk-based memory race recorder in modern CMPs
Spatiotemporal Coherence Tracking
A Bandwidth-efficient Architecture for Media Processing
Surface wave communication system for on-chip and off-chip interconnects
A Control Word Model for detecting conflicts between microprograms
Path-Based Next Trace Prediction
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 12th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2019, Columbus, OH, USA, October 13, 2019
An axiomatization of low-level parallelism in microarchitectures
Jump over ASLR: Attacking branch predictors to bypass ASLR
Improving the Utilization of Micro-operation Caches in x86 Processors
B2RAC: a physical express link addition methodology for network on chip
A survey of high level microprogramming languages
Dynamic instruction set evaluation
LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems
Mint: An Accelerator For Mining Temporal Motifs
A framework for dynamic energy efficiency and temperature management
A register-file approach for row buffer caches in die-stacked DRAMs
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All
Control-Flow Decoupling
Improving the effectiveness of searching for isomorphic chains in superword level parallelism
Dynamic error mitigation in NoCs using intelligent prediction techniques
CABLE: A CAche-Based Link Encoder for Bandwidth-Starved Manycores
How to Fake 1000 Registers
PCCS: Processor-Centric Contention-aware Slowdown Model for Heterogeneous System-on-Chips
A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors
Beyond the Memory Wall: A Case for Memory-Centric HPC System for Deep Learning
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011
Exploiting emerging technologies for nanoscale photonic networks-on-chip
Skipper: Enabling efficient SNN training through activation-checkpointing and time-skipping
Border control: sandboxing accelerators
Hardware support for large atomic units in dynamically scheduled machines
Microprogramming in multiprocessor data acquisition system
Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems
Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support
Characterizing the impact of predicated execution on branch prediction
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
Transparent Hardware Management of Stacked DRAM as Part of Memory
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain
Control flow prediction for dynamic ILP processors
ADAPT: Mitigating Idling Errors in Qubits via Adaptive Dynamical Decoupling
Microinstruction sequencing and structured microprogramming
Custom-fit Processors: Letting Applications Define Architectures
IBM 4341 hardware/microcode trade-off decisions
A case study in using two-level control stores
Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution
A high-performance microarchitecture with hardware-programmable functional units
PUSh: Data Race Detection Based on Hardware-Supported Prevention of Unintended Sharing
A Superscalar 3D Graphics Engine
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
MIDAS - microprogram description and analysis system
Keynote address - the processor instruction set
Conference record of the 6th annual workshop on Microprogramming, MICRO 1973, College Park, Maryland, USA, September 24-25, 1973
Application of microprogramming to medium scale computer design
Warming Up a Cold Front-End with Ignite
Patching up Network Data Leaks with Sweeper
Architectural Implications of Function-as-a-Service Computing
Fast Path-Based Neural Branch Prediction
Cryptographic Capability Computing
Netrace: dependency-driven trace-based network-on-chip simulation
LEF: long edge first routing for two-dimensional mesh network on chip
RDIP: return-address-stack directed instruction prefetching
Using modern graphics architectures for general-purpose computing: a framework and analysis
The implementation of a user-extensible system on a dynamically microprogrammable computer
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications
BVF: enabling significant on-chip power savings via bit-value-favor for throughput processors
A high-efficiency low-cost heterogeneous 3D network-on-chip design
Automatic synthesis of a dual-PLA controller with a counter
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor
A quantitative framework for automated pre-execution thread selection
Locking down insecure indirection with hardware-based control-data isolation
Cambricon-M: A Fibonacci-Coded Charge-Domain SRAM-Based CIM Accelerator for DNN Inference
Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks
The StageNet fabric for constructing resilient multicore systems
Crank it up or dial it down: coordinated multiprocessor frequency and folding control
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures
iDO: Compiler-Directed Failure Atomicity for Nonvolatile Memory
RHMD: evasion-resilient hardware malware detectors
Heterogeneous system coherence for integrated CPU-GPU systems
Customizing Cache Indexing Through Entropy Estimation
Performance Evaluation of Mesh-based 3D NoCs
The Cell Processor Architecture
Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads
Store Memory-Level Parallelism Optimizations for Commercial Applications
HARE: Hardware accelerator for regular expressions
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference
CSALT: context switch aware large TLB
Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Linearly compressed pages: a low-complexity, low-latency main memory compression framework
Predicting Indirect Branches via Data Compression
Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism
HetArch: Heterogeneous Microarchitectures for Superconducting Quantum Systems
NN-Noxim: High-Level Cycle-Accurate NoC-based Neural Networks Simulator
Realizing a virtual machine
LUCIE: A Universal Chiplet-Interposer Design Framework for Plug-and-Play Integration
A performance-correctness explicitly-decoupled architecture
Functional languages in microcode compilers
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research
PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems
The performance impact of incomplete bypassing in processor pipelines
Issues of the design of a low level microprogramming language for global microcode compaction
High-level microprogramming with APL syntax
Design of a microprogrammed alphanumeric terminal
Strategies for Branch Target Buffers
A microprogrammed keyword transformation unit for a database computer
NetDIMM: Low-Latency Near-Memory Network Interface Architecture
Hierarchical Scheduling Windows
CHERIoT: Complete Memory Safety for Embedded Devices
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance
AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
Flag-Proxy Networks: Overcoming the Architectural, Scheduling and Decoding Obstacles of Quantum LDPC Codes
A bit slice architecture for microprogrammable machines
Optimal versus Heuristic Global Code Scheduling
Research problems and opportunities in NoC-based side channel attacks and defenses: lessons learned from cache-based side channels
Compiler Support for Optimizing Memory Bank-Level Parallelism
Design methodology and microdiagnostics development for a self-checking microprocessor
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating
Light speed arbitration and flow control for nanophotonic interconnects
Microprogrammed spectrum analysis
Control schemes for VLSI microprocessors
Optimum Power/Performance Pipeline Depth
A micro controlled peripheral processor
47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014
Tree-Mesh Heterogeneous Topology for Low-Latency NoC
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
An architecture interface and offload model for low-overhead, near-data, distributed accelerators
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems
Packet chaining: efficient single-cycle allocation for on-chip networks
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy
COMPAQT: Compressed Waveform Memory Architecture for Scalable Qubit Control
A whole new ballgame - supercomputing on two AA batteries (keynote session)
Address compression through base register caching
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
UFC: A Unified Accelerator for Fully Homomorphic Encryption
NMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads
The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs
MIES: a microarchitecture design tool
How secure is your cache against side-channel attacks?
AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants
Tuning architecture at run-time
Dependence-aware transactional memory for increased concurrency
CPElide: Efficient Multi-Chiplet GPU Implicit Synchronization
Microprogramming as a technique to minimize card types in high performance machine design
QuCT: A Framework for Analyzing Quantum Circuit by Extracting Contextual and Topological Features
Stage scheduling: a technique to reduce the register requirements of a modulo schedule
Automatic synthesis of microcontrollers
Regless: just-in-time operand staging for GPUs
Trace selection for compiling large C application programs to microcode
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions
HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator
Fast support for unstructured data processing: the unified automata processor
Unroll-and-Jam Using Uniformly Generated Sets
AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing
Peephole optimization as a targeting and coupling tool
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk
Reducing data movement energy via online data clustering and encoding
Hardware Support for Control Transfers in Code Caches
In-Network Cache Coherence
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems
Direct load: dependence-linked dataflow resolution of load address and cache coordinate
An Efficient Self-Routing and Non-Blocking Interconnection Network on Chip
Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning
Improving the Performance and Endurance of Encrypted Non-Volatile Main Memory through Deduplicating Writes
GPUpd: a fast and scalable multi-GPU architecture using cooperative projection and distribution
TLC: Transmission Line Caches
Exploiting instruction-level parallelism with the conjugate register file scheme
PORPLE: An Extensible Optimizer for Portable Data Placement on GPU
An integrated approach to accelerate data and predicate computations in hyperblocks
Weeding out Front-End Stalls with Uneven Block Size Instruction Cache
4th International Workshop on Network on Chip Architectures, NoCArc '11, Porto Alegre, Brazil, December 4-5, 2011
Uncore Encore: Covert Channels Exploiting Uncore Frequency Scaling
Power-driven Design of Router Microarchitectures in On-chip Networks
Speculative Enforcement of Store Atomicity
SIMR: Single Instruction Multiple Request Processing for Energy-Efficient Data Center Microservices
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
Dynamic clustering for distinct parallel programming models on NoC-based MPSoCs
Ternary computers: part I: motivation for ternary computers
Microprogramming concepts - a step towards structured hardware design
A Case for Multi-Programming Quantum Computers
Implementing a Prolog machine with multiple functional units
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors
EMMY/360: An emulation of System/360 for the Stanford EMMY
Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture
CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores
Code Compression Based on Operand Factorization
Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001
CPR: Composable performance regression for scalable multiprocessor models
Minimizing register requirements under resource-constrained rate-optimal software pipelining
MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
Flexible hardware acceleration for multimedia oriented microprocessors
GPU register file virtualization
The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor
Tuning Compiler Optimizations for Simultaneous Multithreading
Design problems in emulating the MIX computer on the Microdata 1600
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design
Improving energy efficiency of DRAM by exploiting half page row access
A model for microarchitecture structure evaluation
Graphene: Strong yet Lightweight Row Hammer Protection
A Dynamic Multithreading Processor
An APL microprogramming structure
Jumanji: The Case for Dynamic NUCA in the Datacenter
Toward user sharing of the microprogramming level under UNIX on the Perkin-Elmer 3220
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
I-GCN: A Graph Convolutional Network Accelerator with Runtime Locality Enhancement through Islandization
An introduction to the verification oriented microprogramming language "MIDDLE"
Considerations for local compaction of nanocode for the nanodata QM-1
Register integration: a simple and efficient implementation of squash reuse
UDSYS a microcode development system
SCRATCH: an end-to-end application-aware soft-GPGPU architecture and trimming tool
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study
A virtual memory system for the Hewlett-Packard 2100A
Swordfish: A Framework for Evaluating Deep Neural Network-based Basecalling using Computation-In-Memory with Non-Ideal Memristors
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching
Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow
Proactive transaction scheduling for contention management
Microcode compaction with timing constraints
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security
Characterizing flash memory: anomalies, observations, and applications
PRISM architecture: parallel and pipeline features
CANDY: Enabling coherent DRAM caches for multi-node systems
The reuse cache: downsizing the shared last-level cache
Microarchitectural denial of service: insuring microarchitectural fairness
Trinity: A General Purpose FHE Accelerator
Composable Building Blocks to Open up Processor Design
Run-time generation of HPS microinstructions from a VAX instruction stream
The Predictability of Data Values
MIDL - a microinstruction description language
Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
Architecting hierarchical coherence protocols for push-button parametric verification
Intra-chip Wireless Interconnect: The Road Ahead
Microarchitecture support for dynamic scheduling of acyclic task graphs
Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments
RpStacks-MT: A High-Throughput Design Evaluation Methodology for Multi-Core Processors
Dead flit attack on NoC by hardware trojan and its impact analysis
Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design
Advances in microcode support software
Coherence Ordering for Ring-based Chip Multiprocessors
Manna: An Accelerator for Memory-Augmented Neural Networks
SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators
End-to-End Automated Exploit Generation for Validating the Security of Processor Designs
Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm
A microprogrammed implementation of a block structured architecture
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
Extending GPU Ray-Tracing Units for Hierarchical Search Acceleration
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
Prediction-guided performance-energy trade-off for interactive applications
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
The big three - today's 16-bit microprocessor
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998
Beating in-order stalls with "flea-flicker" two-pass pipelining
A loop optimization technique based on scheduling table
Interconnection synthesis with geometric constraints
Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue
Using a lookahead window in a compaction-based parallelizing compiler
Implementing high availability memory with a duplication cache
Tree register allocation
The architecture and operational characteristics of the VMX host machine
Register allocation for predicated code
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture
LightWSP: Whole-System Persistence on the Cheap
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
Performance characterization of a hardware mechanism for dynamic optimization
A barrel shift microsystem for parallel processing
A fill-unit approach to multiple instruction issue
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
Microprogrammed implementation of a scheduler
Three extensions to register integration
SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts
Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture
Skipper: a microarchitecture for exploiting control-flow independence
Dodec: Random-Link, Low-Radix On-Chip Networks