yusuke1997/dblp-id-title huggingface dataset:
2017 IEEE Custom Integrated Circuits Conference, CICC 2017, Austin, TX, USA, April 30 - May 3, 2017
A frequency-domain, Volterra series-based behavioral simulation tool for RF systems
Low-Power Design of Pipeline A/D Converters
A fully integrated CMOS UHF RFID reader transceiver for handheld applications
Modeling well edge proximity effect on highly-scaled MOSFETs
5GHz SRAM for High-Performance Compute Platform in 5nm CMOS
A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR
A 20 µW contact impedance sensor for wireless body-area-network transceiver
SP-SOI: a third generation surface potential based compact SOI MOSFET Model
High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS
Matching the power density and potentials of biological systems: A 3.1-nW, 130-mV, 0.023-mm 3 pulsed 33-GHz radio transmitter in 32-nm SOI CMOS
A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT
A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis
Robust design and experimental demonstrations of carbon nanotube digital circuits
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems
Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts
An integrated environment for configurable designs
Energy efficient designs with wide dynamic range
60GHz low-loss compact phase shifters using a transformer-based hybrid in 65nm CMOS
An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS
A methodology for yield-specific leakage estimation in memory
A Noise Circulating Cross-Coupled VCO with a 195.6dBc/Hz FoM and 50kHz 1/f 3 Noise Corner
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications
Clocking circuits for a 16Gb/s memory interface
A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage
A Tripolar Stimulator with Return-Electrode-Based Charge-Pack Injection Technique for Charge Imbalance Correction in Spatiotemporal Stimulation
A 34.7-mW quad-core MIQP solver processor for robot control
Power supply noise in future IC's: a crystal ball reading
Configurable incremental sigma-delta ADC for DC measure and audio conversion
Substrate network modeling for CMOS RF circuit simulation
A 150nW, 5ppm/ o C, 100kHz On-Chip clock source for ultra low power SoCs
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs
Poster session
A 80 Mb/s low-power scalable turbo codec core
Grid selection strategies for time-mapped harmonic balance simulation of circuits with rapid transitions
Loosely coupled memory-based decoding architecture for low density parity check codes
Automated extraction of nonlinear circuit macromodels
A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier
A fully programmable CMOS block matrix transform imager architecture
A novel high precision adjustment method for the transconductance of a MOSFET
Implementing logic in FPGA embedded memory arrays: architectural implications
Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage
A single-chip x-band chirp radar MMIC with stretch processing
A 4.6-6GHz Self-Injection LC Oscillator Exploiting 2 nd Harmonic Extraction and Self-Mixing to Achieve 5-35kHz 1/f 3 Phase Noise Corner and 201dB FoMT
An efficiency-enhanced 2.4GHz stacked CMOS power amplifier with mode switching scheme for WLAN applications
Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors
A spurious-free delta-sigma DAC using rotated data weighted averaging
Design and development of 130-nanometer ICs for a multi-Gigabit switching network system
A 15.5b-ENOB 335mVpp-Linear-Input-Range 4.7GΩ-Input-Impedance Direct-ADC Based Analog Front-End
Future Microprocessor Interfaces: Analysis, Design and Optimization
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator
Digital link pre-emphasis with dynamic driver impedance modulation
A full-duplex wireless integrated transceiver for implant-to-air data communications
A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface
Low power transceivers and oscillators
Effect of RTL coding style on testability
A 46μW, 8.2MHz self-threshold-tracking differential relaxation oscillator with 7.66psrms period jitter and 1.56ppm allan deviation floor
A low-power system-on-chip for the documentation of road accidents
A 0.1-5.0GHz self-calibrated SDR transmitter with -62.6dBc CIM3 in 65nm CMOS
Session 7 - High resolution converters
A 20 dBm Q-band SiGe Class-E power amplifier with 31% peak PAE
A low power capacitive coupled bus interface based on pulsed signaling
Wire planning for performance and yield enhancement
7V tristate-capable output buffer implemented in standard 2.5 V CMOS process
Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall
Microelectronics for the real world: "Moore" versus "More than Moore"
Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices
In-Ear EEG Auditory Neurofeedback Towards Unobtrusive Sleep Enhancement
A 180nm CMOS image sensor with on-chip optoelectronic image compression
Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise
Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications]
Compact modeling and simulation of accelerated circuit aging
Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling
An interference robust 0.18μm CMOS 3.1-8GHz receiver front-end for UWB radio
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration
A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS
Variability in 3-D integrated circuits
A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10
Time to digital converter based on a 2-dimensions Vernier architecture
A substrate noise analysis methodology for large-scale mixed-signal ICs
A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding
Spatial Temperature Sensor with Distributed MASH Modulators
Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder
180nm Sn-doped Ge 2 Sb 2 Te 5 chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications
High Voltage Devices, Topologies and Gate Drivers
Circuits and systems for high-speed links
Design of low-power wake-up radios for IoT applications
Experimental study on MOSFET's flicker noise under switching conditions and modelling in RF applications
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation
A 3V, 4.25Gb/s laser driver with 0.4V output voltage compliance
A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications
A 13.56MHz Fully Integrated 91.8% Efficiency Single-Stage Dual-Output Regulating Voltage Doubler for Biomedical Wireless Power Transfer
CMOS RF transmitter with integrated power amplifier utilizing digital equalization
A 0.9V 2MHz 6.4x-Slope-Boosted Quadrature-Phase Relaxation Oscillator with 164.2dBc/Hz FoM and 62.5ppm Period Jitter in 0.18μm CMOS
Cross talk countermeasures in inductive inter-chip wireless superconnect
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement
A Wideband 180-GHz Phase-Lacked-Loop Based MSK Receiver
An interpolating sense circuit for molecular memory
A 1V 10b 30MSPS Switched-RC Pipelined ADC
CMOS technology characterization for analog and RF design
192-channel CMOS neurochemical microarray
Dynamic current mode logic (DyCML), a new low-power high-performance logic family
A CMOS inductorless MedRadio OOK transceiver with a 42 μW event-driven supply-modulated RX and a 14% efficiency TX for medical implants
A continuous-time programmable digital FIR filter
Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors
200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme
A 0.49W 120.230VRMS to 8.12VDC Power Converter with Switched-Capacitor Regulation and Rectifier Short Flipping Achieving Maximized Bridge Conduction Time
A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor
Novel VLIW code compaction method for a 3D geometry processor
Improving SRAM Vmin and yield by using variation-aware BTI stress
A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling
A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications
Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS
Oversampled ADC's
An isolated DC-DC converter with fully integrated magnetic core transformer
A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks
Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS
Nanoliter-Scale Autonomous Electronics: Advances, Challenges, and Opportunities
A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS
Active On-Die Suppression of Power Supply Noise
Wirelessly powered and bidirectional data exchanged in smart medical microsystems
Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS
A Sub-i V Low-Noise Bandgap Voltage Reference
VSIA technical challenges
28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
A wireless, low-drift, implantable intraocular pressure sensor with parylene-on-oil encapsulation
A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization
Electronic design automation (EDA) solutions for ESD-robust design and verification
Fast Automatic Tuning of Channel Selection Filters Based on Phase Delay Calibration
A unified framework for capacitive series-parallel DC-DC converter design
A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording
A 10.24GSPS photonic sampled bandpass ΔΣ modulator direct-sampling at 12GHz
Challenge: variability characterization and modeling for 65- to 90-nm processes
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS
A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS
A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB
Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAs
A 430MHz-2.15GHz fractional-N frequency synthesizer for DVB and ABS-S applications
Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions
A Direct Digitizing, 1MHz Bandwidth, 28fA/√Hz Current Sensing Front-End Based on a Mixed-Signal Integrator-Differentiator TIA in 28nm CMOS
A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold
Embedded anti-aliasing in switched-capacitor ladder filters
Passive closed-form time-domain macromodels for on-chip distributed RC interconnects
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems
A shared built-in self-repair analysis for multiple embedded memories
A 2.5-Gb/s one-chip receiver module for gigabit-to-the-home (GTTH) system
A 400MHz RF Transceiver for Implantable Biomedical Micro-Stimulators
A single-chip narrowband frequency domain excisor for a Global Positioning System (GPS) receiver
Simplifying in-system programming: evolving standards for ISP
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit
A 0.5 mm 2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor
An X/Ku-band frequency synthesizer using a 9-Bit quadrature DDS
A compact 2.4GHz polar/quadrature reconfigurable digital power amplifier in 28nm logic LP CMOS
An 80 MHz noise optimized continuous-time bandpass filter in 0.25 μm BiCMOS
A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques
Low power direct digital frequency synthesizers in 0.18 μm CMOS
Embedded Test Features for High-Speed Serial I/O
Resistance ratio read (R 3 ) architecture for a burst operated 1.5V MRAM macro
Cellular handset integration - SIP vs. SOC
Nyquist rate ADCs
Low-power sequential access memory design
An open-loop class-D audio amplifier with increased low-distortion output power and PVT-insensitive EMI reduction
A class-D amplifier using a spectrum shaping technique [audio power amplifier]
A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends
A -80dBm BLE-compliant, FSK wake-up receiver with system and within-bit dutycycling for scalable power and latency
A CMOS 2D Transmit Beamformer With Integrated PZT Ultrasound Transducers For Neuromodulation
A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology
A 120dB dynamic range 400mW class-D speaker driver with 4 th -order PWM modulator
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM
Low power analog circuit techniques in the 5 th generation intel core TM microprocessor (broadwell)
A low power 20 GHz 1.5 Gb/s CMOS injection-pulling FSK modulator and frequency discriminator for 60GHz links
An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions
TD-dAJC: A 2pJ/Pixel Time-Domain Weight and Integrating-MAC Based Direct-Analog-to-MJPEG Compression for Video Sensor Nodes
Envelope-Tracking Supply Modulator with Trellis Search-Based Switching and 160MHz Capability
A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID
Improved circuits for microchip identification using SRAM mismatch
Low noise μWatt interface circuits for wireless implantable real-time digital blood pressure monitoring
A 0.055pJ/bit/dB 42Gb/s PAM-4 Wireline Transceiver with Consecutive Symbol to Center (CSC) Encoding and Classification for 26dB Loss in 16nm FinFET
Digital wireline and PLL techniques
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme
A low TC, supply independent and process compensated current reference
High-speed wireline timing recovery & PLLs
A 100-120GHz 20Gbps Bits-to-RF 16QAM Transmitter Using 1-bit Digital-to-Analog Interface
An extended bipolar transistor model for substrate crosstalk analysis
High-Entropy Analog-Based Strong PUF Reaching 166 F2/Bit Area-to-Entropy-Ratio
An ESD protection circuit for mixed-signal ICs
Nyquist rate A/D converters
Low Cost Test of High Bandwidth Embedded Memories
Trimless second order curvature compensated bandgap reference using diffusion resistor
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS
A 60 GHz CMOS combined mm-wave VCO/divider with 10-GHz tuning range
Timing yield enhancement through soft edge flip-flop based design
Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control
Digital RF Processor Techniques for Single-Chip Radios
A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems
An embedded FeRAM macro cell for a smart card microcontroller
An all-digital universal RF transmitter [CMOS RF modulator and PA]
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer
A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications
A 52-dB Self-Interference Rejection Receiver using RF Code-Domain Signal Processing
Interface circuit for metal-oxide gas sensor
A 209TOPS/W Reinforcement Learning Processor with Full Speculation Exploitation and Inference-Training Parallel Processing
Design Techniques of Integrated Power Management Circuits for Low Power Edge Devices
A low-power multi-band ECoG/EEG interface IC
An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and -98 dB THD
Event-driven data acquisition and continuous-time digital signal processing
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling
A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers
ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor
High-speed direct digital frequency synthesizers in 0.25-μm CMOS
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation
A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage
An image recognition processor using dynamically reconfigurable ALU
Highly energy-efficient and quality-tunable inexact FFT accelerators
A 32-to-38GHz Variable-Gain Phase Shifter with Impedance-Invariant Vector Modulation Achieving RMS Phase/Amplitude Errors of 0.33 ○ /0.10dB in PS mode and 0.23 ○ /0.08dB in VGA mode
Energy efficient system architecture for wireless wearable biomedical sensors
A wideband ultra-low-current on-chip ammeter
Single-Chip UHF RFID reader in 0.18- μm CMOS
A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays
Symmetry breaking in the drain current of multi-finger transistors
Characterization of random decision errors in clocked comparators
A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier
A BiCMOS 1× to 5× combined analog frontend IC for DVD-ROM and movie players
Linear current-controlled oscillator for analog to digital conversion
A fully integrated battery-connected switched-capacitor 4: 1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling
Modelling multistability and hysteresis in ESD clamps, memristors and other devices
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation
A 3.6dB NF, 23-39GHz Reflectionless RX with Absorptive Amplifier and Dual-Path Noise Cancelling LNA Supporting 64-QAM/256-QAM/1024-QAM for 5G NR
A ±5V, ±10V, ±15V, 4-channel class-G biphasic constant-current stimulator
A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification
Behavioral modeling and simulation
Performance limitation of on-chip global interconnects for high-speed signaling
A novel wideband 1-π model with accurate substrate modeling for on-chip spiral inductors
From 2D-planar to 3D-non-planar device architecture: A scalable path forward?
A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifier
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates
Noise analysis of a VCO with automatic amplitude control
More than Moore
Crosstalk-induced jitter equalization
A 40nm 0.05-1.4uJ/inference Sample-Wise-Adaptive Spiking Neural Network Processor with Dynamic Neuron-Pruning and Unstructured-Model-Aware Architecture
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC
23mm 2 single-chip 0.18μm CMOS GPS receiver with 28mW-4.1 mm 2 radio and CPU/DSP/RAM/ROM
AI Processor with Sparsity-adaptive Real-time Dynamic Frequency Modulation for Convolutional Neural Networks and Transformers
A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques
10 Gb/s CMOS laser driver with 3.3 V pp output swing
Trends and challenges for wireless embedded DSPs
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference
An Efficiency-Enhanced Integrated CMOS Rectifier with Comparator-Controlled Switches for Transcutaneous Powered Implants
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology
Rigorous Analytical/Graphical Injection Locking Analysis of Two-Port Negative Resistance Oscillators
A 100-MSPS 8-b CMOS subranging ADC with parametric operation from 3.8 V down to 2.2 V
Design considerations for distributed microsensor systems
Clocking circuits for wireline communications
A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter
A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data
A Digitally-Reconfigurable RC Frequency Generator using Impedance IQ-Balanced Frequency-Locked-Loop with Selectable Phase Mixing
On-Chip Circuit for Measuring Period Jitter and Skew of Clock Distribution Networks
A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS
A Fully-Integrated Wireless Ingestible Drug Delivery Chip with Electrochemical Energy Harvesting and pH-Based MPPT
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor
Impact of high resolution lithography on IC mask design
A 0.6V 3.8μW ECG/bio-impedance monitoring IC for disposable health patch in 40nm CMOS
A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing
A 22.0-to-28.4GHz 192.2dBc/Hz FoM and 206.2dBc/Hz FoMA Dual-Core VCO Using Circular-Inverse-Class-F Topology Under Standard Supply Voltage in 65nm CMOS Process
Implementation of the 65nm Cell Broadband Engine
CMOS-year 2010 and beyond; from technological side
Intel 22nm Low-Power FinFET (22FFL) Process Technology for 5G and Beyond
A millimeter-wave tunable transformer-based dual-antenna duplexer with 50 dB isolation
A digital phase-locked loop with calibrated coarse and stochastic fine TDC
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
A surface-mounted RF IC technology demonstrated with a 10 GHz LC oscillator with copper coils
Design validation of .18 μm 1 GHz cache and register arrays
Lookup-table-based background linearization for VCO-based ADCs
45pW ESD clamp circuit for ultra-low power applications
Optimization of phase-locked loop circuits via geometric programming
An 83mA 96.8% Peak Efficiency 3-Level Boost Converter with Full-Range Auto-Capacitor-Calibrating Pulse Frequency Modulation
A 3-7GHz 4-element digital modulated polar phased-array transmitter with 0.35° phase resolution and 38.2% peak system efficiency
Body wellness without wires
A -90 dBm sensitivity 0.13 μm CMOS bluetooth transceiver operating in wide temperature range
Fast transient technique (FTT) in buck current-mode DC-DC converters for low-voltage SoC systems
7T SRAM enabling low-energy simultaneous block copy
A 29 dBm CMOS class-E power amplifier with 63% PAE using negative capacitance
RFCMOS technology from 0.25μm to 65nm: the state of the art
A 0.8V/0.6V 2.2μW Time-Domain Analog Front-End with $540\text{mV}_{\text{pp}}$ Input Range, 81.6dB SNDR and $80\mathrm{M}\Omega$ Input Impedance
A single chip terminal solution for high-end telephone applications
TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption
A baseband technique for automated LO leakage suppression achieving > -80dBm in wideband passive mixer-first receivers
Key, Value, Compress: A Systematic Exploration of KV Cache Compression Techniques