yusuke1997/dblp-id-title huggingface dataset:
Neural network integral representations with the ReLU activation function
Momentum Transformer: Closing the Performance Gap Between Self-attention and Its Linearization
Sharp threshold for alignment of graph databases with Gaussian weights
Dynamic Algorithms for Online Multiple Testing
SHRIMP: Sparser Random Feature Models via Iterative Magnitude Pruning
Some observations on high-dimensional partial differential equations with Barron data
A Qualitative Study of the Dynamic Behavior for Adaptive Gradient Algorithms
The Slow Deterioration of the Generalization Error of the Random Feature Model
A deep learning method for solving Fokker-Planck equations
Proceedings of Mathematical and Scientific Machine Learning, MSML 2020, 20-24 July 2020, Virtual Conference / Princeton, NJ, USA
Deep learning Markov and Koopman models with physical constraints
Construction of optimal spectral methods in phase retrieval
Non-Gaussian processes and neural networks at finite widths
Large deviations for the perceptron model and consequences for active learning
Active Importance Sampling for Variational Objectives Dominated by Rare Events: Consequences for Optimization and Generalization
Multilevel Stein variational gradient descent with applications to Bayesian inverse problems
Deep Generative Learning via Euler Particle Transport
Analyzing Finite Neural Networks: Can We Trust Neural Tangent Kernel Theory?
Online Weak-form Sparse Identification of Partial Differential Equations
Exact asymptotics for phase retrieval and compressed sensing with random generative priors
On the stable recovery of deep structured linear networks under sparsity constraints
Deep Fictitious Play for Finding Markovian Nash Equilibrium in Multi-Agent Games
On the Nash equilibrium of moment-matching GANs for stationary Gaussian processes
Deep Autoencoders: From Understanding to Generalization Guarantees
Geometric Wavelet Scattering Networks on Compact Riemannian Manifolds
New Potential-Based Bounds for the Geometric-Stopping Version of Prediction with Expert Advice
Practical and Fast Momentum-Based Power Methods
Learning Green’s Functions of Linear Reaction-Diffusion Equations with Application to Fast Numerical Solver
Deep learning interpretation: Flip points and homotopy methods
Average-Case Integrality Gap for Non-Negative Principal Component Analysis
Deep Domain Decomposition Method: Elliptic Problems
Generalization and Memorization: The Bias Potential Model
A type of generalization error induced by initialization in deep neural networks
Solvable Model for Inheriting the Regularization through Knowledge Distillation
Policy Gradient based Quantum Approximate Optimization Algorithm
Butterfly-Net2: Simplified Butterfly-Net and Fourier Transform Initialization
Temporal-difference learning with nonlinear function approximation: lazy training and mean field regimes
Monte Carlo Tree Search based Hybrid Optimization of Variational Quantum Circuits
The Gaussian equivalence of generative models for learning with shallow neural networks
Implicit Form Neural Network for Learning Scalar Hyperbolic Conservation Laws
Decentralized Multi-Agents by Imitation of a Centralized Controller
SchrödingerRNN: Generative modeling of raw audio as a continuously observed quantum state
Structure-preserving Sparse Identification of Nonlinear Dynamics for Data-driven Modeling
Ground States of Quantum Many Body Lattice Models via Reinforcement Learning
Optimal denoising of rotationally invariant rectangular matrices
SpecNet2: Orthogonalization-free Spectral Embedding by Neural Networks
Noise-Robust End-to-End Quantum Control using Deep Autoregressive Policy Networks
Hessian-Aided Random Perturbation (HARP) Using Noisy Zeroth-Order Queries
Reduced Order Modeling using Shallow ReLU Networks with Grassmann Layers
On the emergence of simplex symmetry in the final and penultimate layers of neural network classifiers
MURANA: A Generic Framework for Stochastic Variance-Reduced Optimization
Optimal Policies for a Pandemic: A Stochastic Game Approach and a Deep Learning Algorithm
Natural Compression for Distributed Deep Learning
Interpretable and Learnable Super-Resolution Time-Frequency Representation
SelectNet: Learning to Sample from the Wild for Imbalanced Data Training
Numerical Calabi-Yau metrics from holomorphic networks
A semigroup method for high dimensional committor functions based on neural network
4th International Workshop on High-Level Concurrent Languages, HLCL 2000, Satellite to PLI 2000, Montreal, Canada, September 20, 2000
3rd International Workshop on High-Level Concurrent Languages, HLCL 1998, Satellite Workshop of CONCUR 1998, Nice, France, September 12, 1998
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware
Enhanced reliability-aware power management through shared recovery technique
The associative-skew clock routing problem
Measurement and modeling of MOS transistor current mismatch in analog IC's
DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators
C-GOOD: C-code generation framework for optimized on-device deep learning
Novel proximal group ADMM for placement considering fogging and proximity effects
Hardware/software co-synthesis with memory hierarchies
On Uniformly Sampling Traces of a Transition System
Arithmetic and galois checksums
Transistor-Level Timing Analysis Using Embedded Simulation
Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees
Guiding global placement with wire density
Switching activity analysis using Boolean approximation method
Pairwise Proximity-Based Features for Test Escape Screening
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation
On undetectable faults in partial scan circuits
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic
Graph algorithms for clock schedule optimization
ProperSYN: a portable parallel algorithm for logic synthesis
Model-based hardware design
Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Modeling oscillator arrays for video analytic applications
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique
Efficient orthonormality testing for synthesis with pass-transistor selectors
SEM-CLIP: Precise Few-Shot Learning for Nanoscale Defect Detection in Scanning Electron Microscope Image
Congestion analysis for global routing via integer programming
Variation-aware layout-driven scheduling for performance yield optimization
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995
Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Multi-objective design optimization for flexible hybrid electronics
C3DSTAR: a 3D wiring capacitance calculator
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits
Microarchitecture parameter selection to optimize system performance under process variation
Transmission line design of clock trees
CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Network
MORE 2 : Morphable Encryption and Encoding for Secure NVM
Bayesian Accuracy Analysis of Stochastic Circuits
FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGA
Tetris: re-architecting convolutional neural network computation for machine learning accelerators
PACE2: an improved parallel VLSI extractor with parameter extraction
Towards completely automatic decoder synthesis
Keynote addresses: Quantum computing: Revolutionizing computation through quantum mechanics
Accuate simplification of large symbolic formulae
Don't cares and global flow analysis of Boolean networks
AWE macromodels of VLSI interconnect for circuit simulation
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits
Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm
Automatic Synthesis of Locally-Clocked Asynchronous State Machines
Min-max linear programming and the timing analysis of digital circuits
An accurate grid local truncation error for device simulation
2010 International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, November 7-11, 2010
Kernel Shape Control for Row-Efficient Convolution on Processing-In-Memory Arrays
ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings
Circuit Optimization Driven by Worst-Case Distances
Exact and heuristic approaches to input vector control for leakage power reduction
Memory bank and register allocation in software synthesis for ASIPs
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators
Dynamic resource management for heterogeneous many-cores
Fast timing simulation of transient faults in digital circuits
DALTA: A Decomposition-based Approximate Lookup Table Architecture
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)
New algorithms for min-cut replication in partitioned circuits
A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling
Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach
HANNIBAL: an efficient tool for logic verification based on recursive learning
A graph-partitioning-based approach for multi-layer constrained via minimization
ETA: electrical-level timing analysis
Design strategies for high-dimensional electromagnetic systems
LRR-DPUF: learning resilient and reliable digital physical unclonable function
DtCraft: A distributed execution engine for compute-intensive applications
Automatic netlist extraction for measurement-based characterization of off-chip interconnect
A new statistical max operation for propagating skewness in statistical timing analysis
Hardware/software partitioning for multi-function systems
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems
The analysis of cyclic circuits with Boolean satisfiability
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
Global Routing with Inherent Static Timing Constraints
FGILP: an integer linear program solver based on function graphs
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
Extension of the asymptotic waveform evaluation technique with the method of characteristics
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques
Re-engineering of timing constrained placements for regular architectures
A hybrid scheme for compacting test responses with unknown values
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs
CADICS - Cyclic Analog-to-Digital Converter Synthesis
Advanced Packaging Warpage Modeling with DeepONet-Based Operator Learning
On Minimizing the Read Latency of Flash Memory to Preserve Inter-Tree Locality in Random Forest
A general approach for identifying hierarchical symmetry constraints for analog circuit layout
A revisit to floorplan optimization by Lagrangian relaxation
Efficient and effective placement for very large circuits
FANHAT: fanout oriented hierarchical automatic test generation system
Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
A self-evolving design methodology for power efficient multi-core systems
Spin torque devices in embedded memory: model studies and design space exploration
AdaPI: Facilitating DNN Model Adaptivity for Efficient Private Inference in Edge Computing
Achieving Simultaneous Buffering and Steiner Tree Synthesis via Harmonic Based Reinforcement Learning
Architecture and details of a high quality, large-scale analytical placer
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
Exact route matching algorithms for analog and mixed signal integrated circuits
An Algebra for Switch-Level Simulation
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures
2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004
Mitigating Resource Contention for Responsive On-device Machine Learning Inferences
Proof logging for computer algebra based SMT solving
A provably good algorithm for high performance bus routing
FabThink: A Wafer Analysis Multimodal LLM via Chain-of-Thought-Driven Retrieval Augmentation
Statistical gate sizing for timing yield optimization
Directional bias and non-uniformity in FPGA global routing architectures
A silicon-validated methodology for power delivery modeling and simulation
Architecture and routability analysis for row-based FPGAs
Synthesis for multiple input wires replacement of a gate for wiring consideration
Dynamic range estimation for nonlinear systems
Improving Timing & Power Trade-off in Post-place Optimization Using Multi-agent Reinforcement Learning
Application specific processor design: Architectures, design methods and tools
Diagnosis and repair of memory with coupling faults
Predictive subset testing for IC performance
Neurally-Inspired Hyperdimensional Classification for Efficient and Robust Biosignal Processing
Towards Floating Point-Based Attention-Free LLM: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression
Learning from biological neurons to compute with electronic noise special
A High-Packing Density Module Generator for Bipolar Analog LSIs
Vectorized fault simulation on the Cray X-MP supercomputer
Design of sequential machines for efficient test generation
A Neural-Ordinary-Differential-Equations Based Generic Approach for Process Modeling in DTCO: A Case Study in Chemical-Mechanical Planarization and Copper Plating
Approximation knob: power capping meets energy efficiency
PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures
The STeTSiMS STT-RAM simulation and modeling system
MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error Bound
Comparison of Random Test Vector Generation Strategies
Design exploration for high-performance pipelines
Minimizing area and power of sequential CMOS circuits using threshold decomposition
Trajectory-Directed discrete state space modeling for formal verification of nonlinear analog circuits
A Unified Framework for Layout Pattern Analysis with Deep Causal Estimation
Clock power minimization using structured latch templates and decision tree induction
Decomposition and technology mapping of speed-independent circuits using Boolean relations
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols
Invited Paper: Instruction Set Extensions for Post-Quantum Cryptography
Embedded program timing analysis based on path clustering and architecture classification
Modeling and design automation of biological circuits and systems
Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation
Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths
The Design and Optimization of SOC Test Solutions
ICCAD-2016 CAD contest in large-scale identical fault search
Fast Switch-Level Fault Simulation Using Functional Fault Modeling
Asymptotically efficient retiming under setup and hold constraints
Depth controlled symmetric function fanin tree restructure
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper
High-level area and power estimation for VLSI circuits
Invited Paper: Accelerating Next-G Wireless Communications with FPGA-Based AI Accelerators
On Advancing Physical Design Using Graph Neural Networks
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits
Fast methods for simulation of biomolecule electrostatics
Cellular automata based synthesis of easily and fully testable FSMs
Timing Driven Gate Duplication: Complexity Issues and Algorithms
A Customized Graph Neural Network Model for Guiding Analog IC Placement
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design
Transition-aware decoupling-capacitor allocation in power noise reduction
Novel heterogeneous computing platforms and 5G communications for IoT applications
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
Physical models for electron transport in graphene nanoribbons and their junctions
Multi-Domain Clock Skew Scheduling
RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems
Laser Attack Benchmark Suite
Multi-level network optimization for low power
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing
Optimal Layout Synthesis for Quantum Computing
Logic Synthesis for Digital In-Memory Computing
ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC
A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach
MOSAIC: a tile-based datapath layout generator
Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths
SiSMA: a statistical simulator for mismatch analysis of MOS ICs
A symbolic algorithm for maximum flow in 0-1 networks
Clustering for processing rate optimization
Fast decap allocation based on algebraic multigrid
A novel reconfiguration scheme for 2-D processor arrays
An efficient and effective detailed placement algorithm
HDXpose: Harnessing Hyperdimensional Computing's Explainability for Adversarial Attacks
Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process
Computing Parametric Yield Accurately and Efficiently
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
Noise in genetic circuits: hindrance or chance?
Invited paper - Connecting the D.O.T.S.: Design of fluidic circuit boards for multi-OoC platforms using CAD Tools for Standardization
Remote inter-chip power analysis side-channel attacks at board-level
Placement Driven Retiming with a Coupled Edge Timing Model
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs
On Compacting Test Response Data Containing Unknown Values
Buffer assignment for data driven architectures
New methods of improving parallel fault simulation in synchronous sequential circuits
Partitioning issues in circuit simulation on multiprocessors
Deterministic methods for stochastic computing using low-discrepancy sequences
Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits
Compositional Verification Using a Formal Component and Interface Specification
MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers
Computational geometry based placement migration
Checking consistency of C and Verilog using predicate abstraction and induction
Interface co-synthesis techniques for embedded systems
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization
A robust functional ECO engine by SAT proof minimization and interpolation techniques
Machine Learning for Testing Machine-Learning Hardware: A Virtuous Cycle
A cocktail approach on random access scan toward low power and high efficiency test
Verification of Relations Between Synchronous Machines
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
Power-Aware Training for Energy-Efficient Printed Neuromorphic Circuits
EDA and the network
Scalable N-worst algorithms for dynamic timing and activity analysis
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems
A precorrected-FFT method for capacitance extraction of complicated 3-D structures
GSTE through a case study
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Property-Directed Synthesis of Reactive Systems from Safety Specifications
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis
Fast test generation for sequential circuits
A multi-harmonic probe technique for computing oscillator steady states
An O(m+n)-Space Spatiotemporal Denoising Filter with Cache-Like Memories for Dynamic Vision Sensors
Metrology for analog module testing using analog testability bus
SIMCURRENT: An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits
LaserEscape: Detecting and Mitigating Optical Probing Attacks
Heterogeneous built-in resiliency of application specific programmable processors
Quantifying Timing-Based Information Flow in Cryptographic Hardware
Online task-scheduling for fault-tolerant low-energy real-time systems
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication
The effect of process variation on device temperature in FinFET circuits
Switch cell optimization of power-gated modern system-on-chips
Fast and Efficient 2-bit LLM Inference on GPU: 2/4/16-bit in a Weight Matrix with Asynchronous Dequantization
3POr - Parallel projection based parameterized order reduction for multi-dimensional linear models
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications
Using precomputation in architecture and logic resynthesis
Towards provably-secure analog and mixed-signal locking against overproduction
Symbolic hazard-free minimization and encoding of asynchronous finite state machines
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing
Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Formal verification of pipeline control using controlled token nets and abstract interpretation
Overall consideration of scan design and test generation
A technology-independent CAD tool for ESD protection device extraction: ESDExtractor
Electromagnetic equalizer: an active countermeasure against EM side-channel attack
JSA-CIM: A Joint-Sparse AdderNet Compute-In-Memory Accelerator for Energy-Efficient Edge AI Applications
A resource sharing and control synthesis method for conditional branches
A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Timing variation-aware high-level synthesis
ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories