yusuke1997/dblp-id-title huggingface dataset:
CSER: BISER-based concurrent soft-error resilience
Unstructured text: Test analysis techniques applied to non-test problems
Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors
Recursive Path Selection for Delay Fault Testing
A UML Based System Level Failure Rate Assessment Technique for SoC Designs
Unified Functional Safety Framework for advance multi-domain SoCs combining ISO 26262 & IEC61508
Using piecewise-functional broadside tests for functional broadside test compaction
SMV methodology enhancements for high speed I/O links of SoCs
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests
Test algorithms for ECC-based memory repair in nanotechnologies
Recent advances in logic synthesis with testability
Understanding customer returns from a test perspective
At-Product-Test Dedicated Adaptive supply-resonance suppression
A scan cell architecture for inter-clock at-speed delay testing
High level fault modeling of asynchronous circuits
Test-cost optimization and test-flow selection for 3D-stacked ICs
Innovative practices session 7C: Reduced pin-count testing - How low can we go?
Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study
On test generation for path delay faults in ASICs
False Path Aware Timing Yield Estimation under Variability
Test-set reordering for improving diagnosability
SAT-ATPG using preferences for improved detection of complex defect mechanisms
On the effectiveness of simultaneous self-test techniques
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O
Improving test generation by use of majority gates
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries
Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests
Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies
A Design for Testability Study on a High Performance Automatic Gain Control Circuit
The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation
Revival of partial scan: Test cube analysis driven conversion of flip-flops
Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests
Simulation of non-classical faults on the gate level-fault modeling
Tester-based optical and electrical diagnostic system and techniques
Bridging fault coverage improvement by power supply control
An optimised SDD ATPG and SDQL computation method across different pattern sets
Design Technology Research and Education for Deep-Submicron Systems of the Next Century
Static Compaction of Delay Tests Considering Power Supply Noise
Soft Errors and Tolerance for Soft Errors
On the effects of test compaction on defect coverage
Special session 4B: Elevator talks
WeSPer: A flexible small delay defect quality metric
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Fault probabilities in routing channels of VLSI standard cell designs
A Time-Domain Method for Pseudo-Spectral Characterization
Transformed pseudo-random patterns for BIST
Limitations in predicting defect level based on stuck-at fault coverage
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
Using target faults to achieve a minimized partial scan path
On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers
On evaluating competing bridge fault models for CMOS ICs
A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits
Innovative Practices on DFT for AI Chips
Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processing
A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique
Controllable self-checking checkers for conditional concurrent checking
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments
Synthesis-for-scan and scan chain ordering
On clustering of undetectable transition faults in standard-scan circuits
High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification
On-Chip Spectrum Analyzer for Analog Built-In Self Test
A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitter
Reducing Power Dissipation during Test Using Scan Chain Disable
Programmable extended SEC-DED codes for memory errors
Cost-Driven Selection of Parity Trees
Partner SRLs for improved shift register diagnostics
Special session: Multifaceted approaches for field reliability
Test Generation for Accurate Prediction of Analog Specifications
Defect-Oriented Test Scheduling
On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observers
Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation
Instruction Randomization Self Test For Processor Cores
Theoretical analysis for low-power test decompression using test-slice duplication
Circuit-level dictionaries of CMOS bridging faults
Special Session: Bringing Symbolic Execution to the Security Verification of Hardware Designs
The Impacts of Untestable Defects on Transition Fault Testing
Active defense against counterfeiting attacks through robust antifuse-based on-chip locks
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance
Ultra-Wideband Modulation Signal Measurement Using Local Sweep Digitizing Method
Tools for the Characterization of Bipolar CML Testability
A coherent subsampling test system arrangement suitable for phase domain measurements
Automatic test generation using genetically-engineered distinguishing sequences
Analyzing the Impact of Scheduling Policies on the Reliability of GPUs Running CNN Operations
Innovative practices session 7C: Self-calibration & trimming
Random pattern generation for post-silicon validation of DDR3 SDRAM
Exploiting Dominance and Equivalence using Fault Tuples
A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications
Innovative Practices on In-System Test and Reliability of Memories
Innovative practices session 4C: Disruptive solutions in the non-digital world
Fast fault coverage estimation of sequential tests using entropy measurements
Analog/RF test ordering in the early stages of production testing
A power supply ramping and current measurement based technique for analog fault diagnosis
An inter-layer interconnect BIST solution for monolithic 3D ICs
A BIST Scheme for FPGA Interconnect Delay Faults
Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays
Do I Need this Tool for My Chips to Work?
Innovative practices on machine learning for emerging applications
Design of Parameterizable Error-Propagating Space Compactors for Response Observation
Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation
On Performance Testing with Path Delay Patterns
Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality?
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities
Test Generation for Defect-Based Faults of Scan Flip-Flops
Asynchronous multiple scan chain
Diagnosis of Sequence-Dependent Chips
RT-Level Deviation-Based Grading of Functional Test Sequences
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces
Coset error detection in BIST design
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates
Automated Design For Yield Through Defect Tolerance
Test generation and three-state elements, buses, and bidirectionals
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements
Vmin Prediction Using Nondestructive Stress Test
A Method for Simulating Mixed-Signal ATE Tests
Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies
Automated Design and Insertion of Optimal One-Hot Bus Encoders
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER)
Robust Sequential Fault Testing of Iterative Logic Arrays
Accelerating Diagnosis via Dominance Relations between Sets of Faults
Test Vector Modification for Power Reduction during Scan Testing
A Scalable On-Chip Jitter Extraction Technique
Finitely self-checking circuits and their application on current sensors
Special session 11C: Young professionals in test - Elevator talks
Auto-identification of positive feedback loops in multi-state vulnerable circuits
Special Session: A Call to Standardize Chip-let Interconnect Testing
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets
Innovative practices session 3C: Advances in silicon debug & diagnosis
Automatic Configuration Generation for FPGA Interconnect Testing
Hardware Resource Minimization for Histogram-Based ADC BIST
Innovative Practices Track: Session 2 Silent Data Corruption
Innovative practices session 1C: Existing/emerging low power techniques
Revealing SRAM memory content using spontaneous photon emission
An analytical method for estimating SET propagation
Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators
Detection of gate-oxide defects with timing tests at reduced power supply
Low Power/Energy BIST Scheme for Datapaths
Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages
Analysis of redundant structures in combinational circuits
A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture
On the Evaluation of Arbitrary Defect Coverage of Test Sets
Innovative practices on silicon photonics
Timing Critical Path Validation for Intel ATOM Cores Using Structural Test
Special panel session IIB: "System validation and silicon debug - Is standardization possible?"
Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors
iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages
Initialization of sequential circuits and its application to ATPG
Experiments and analysis to characterize logic state retention limitations in 28nm process node
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
On the Relaxation of n-detect Test Sets
Adaptive Techniques for Improving Delay Fault Diagnosis
Compact test generation for bridging faults under I DDQ testing
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage
A Multi-Step Algorithm to Increase Measurement Accuracy of mm-Wave BIST Using Periodic Structures
MicroFI: TensorFlow Lite based Fault Injection Framework for Microcontrollers
NN-ECC: Embedding Error Correction Codes in Neural Network Weight Memories using Multi-task Learning
Panel: Analog Characterization and Test: The Long Road to Realization
Optimal voltage testing for physically-based faults
Enhancing testability by structured partial scan
CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme
Test vector omission with minimal sets of simulated faults
Quality impacts of non-uniform fault coverage
Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits
ECC design of a custom DRAM storage unit
An approach for testing programmable/configurable field programmable gate arrays
Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering
On Diagnosing Path Delay Faults in an At-Speed Environment
Fault Models for Speed Failures Caused by Bridges and Opens
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays
Functional Memory Faults: A Formal Notation and a Taxonomy
On multiple bridging faults
Write-through method for embedded memory with compression Scan-based testing
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs
On Synchronizing Sequences and Test Sequence Partitioning
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories
Energy-Efficient Logic BIST Based on State Correlation Analysis
A concurrent checking scheme for single and multibit errors in logic circuits
Restrict Encoding for Mixed-Mode BIST
Innovative practices session 6C: Latest practices in test compression
Selective Checksum based On-line Error Correction for RRAM based Matrix Operations
TSV aware timing analysis and diagnosis in paths with multiple TSVs
RSAK: Random stream attack for phase change memory in video applications
Using hardware testing approaches to improve software testing: Undetectable mutant identification
Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking
Testing Static and Dynamic Faults in Random Access Memories
On the complexity of terminal stuck-at fault detection tests for monotone Boolean functions
12th IEEE VLSI Test Symposium (VTS'94), April 25-28, 1994, Cherry Hill, New Jersey, USA
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints
Physically-Aware N-Detect Test Relaxation
In-field Functional Test of CAN Bus Controllers
Overview of flexible electronics from ITRI's viewpoint
Functional test pattern generation for CMOS operational amplifier
Gate Leakage Current Integration-Based Dielectric Breakdown Monitor in a 12nm FinFET Process
Reliable Board-Level Degradation Prediction with Monotonic Segmented Regression under Noisy Measurement
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links
Low-Cost On-Line Test for Digital Filters
Innovative practices session 10C: Delay test
Impact of high level functional constraints on testability
Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits
Realization of fully path-delay-fault testable non-scan sequential circuits
Fast evaluation of test vector sets using a simulation-based statistical metric
Novel estimation method of EVM with channel correction for linear impairments in multi-standard RF transceivers
Automated Debug of Speed Path Failures Using Functional Tests
A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters
Diagnostic of path and gate delay faults in non-scan sequential circuits
SOC Test Scheduling Using Simulated Annealing
Is High Frequency Analog DFT Possible?
Checksum-based concurrent error detection in linear analog systems with second and higher order stages
Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms
At-speed scan test with low switching activity
On the Comparison of IDDQ and IDDQ Testing
Test and Debug of Networking SoCs: A Case Study
Distributed Generation of Weighted Random Patterns
Innovative Practices on IEEE 1687.xyz
A SMT-based diagnostic test generation method for combinational circuits
Testability of Sequential Circuits with Multi-Cycle False Path
Rule Generation for Classifying SLT Failed Parts
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Issues of integrating the IEEE Std 1149.1 into a gate array
Fully Deterministic Storage Based Logic Built-In Self-Test
31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013
Special session 5B: Panel How much toggle activity should we be testing with?
Identification of critical variables using an FPGA-based fault injection framework
Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing
A study on the effectiveness of Trojan detection techniques using a red team blue team approach
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
Power-aware test generation with guaranteed launch safety for at-speed scan testing
Single-Measurement Diagnostic Test Method for Parametric Faults of I/Q Modulating RF Transceivers
Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
Power/ground supply voltage variation-aware delay test pattern generation
Dynamic diagnosis of sequential circuits based on stuck-at faults
Gate-Oxide Early Life Failure Prediction
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance
Test and characterization of high-speed circuits
ChipMnd: LLMs for Agile Chip Design
High-level test generation using physically-induced faults
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test
PROBE: A PPSFP Simulator for Resistive Bridging Faults
Special Session (New Topic): Emerging Computing and Testing Techniques
Silent Data Errors: Sources, Detection, and Modeling
Design Optimization for Robustness to Single Event Upsets
How Should Fault Coverage Be Defined?
Open faults in BiCMOS gates
Test embedding with discrete logarithms
Can Defect-Tolerant Chips Better Meet the Quality Challenge?
Design, analysis, and test of low-power and reliable flexible electronics
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation
Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering Buffer
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test
Comprehensive investigation of gate oxide short in FinFETs
Silicon evaluation of faster than at-speed transition delay tests
PPB: Partially-working processors binning for maximizing wafer utilization
Performance-aware reliability assessment of heterogeneous chips
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis
Improved Test Monitor Circuit in Power Pin DfT
Panel: Apprentice - VTS Edition: Season 2
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits
An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits
FACTS: fault coverage estimation by test vector sampling
CCSTG: an efficient test pattern generator for sequential circuits
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
Scan-Path with Directly Duplicated and Inverted Duplicated Registers
Are advanced DfT structures sufficient for preventing scan-attacks?
Methods to reduce test application time for accumulator-based self-test
The roadblocks to broad adoption of high level synthesis
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware
Special session 12B: Panel post-silicon validation & test in huge variance era
Time and space correlated errors in signature analysis
Impact of the application activity on intermittent faults in embedded systems
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects
Automated diagnosis of VLSI failures
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems
Pattern Generation and Estimation for Power Supply Noise Analysis
An On-Chip Transfer Function Characterization System for Analog Built-in Testing
A Test Pattern Generation Methodology for Low-Power Consumption
IDDq benefits [digital CMOS testing]
Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs
Accurate and efficient method of jitter and noise separation and its application to ADC testing
Predicting the Silent Data Error Prone Devices Using Machine Learning
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications
On-die learning-based self-calibration of analog/RF ICs
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification
CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking
Aliasing-free error detection (ALFRED)
On shrinking wide compressors
A Discovery Platform to Characterize Emerging Nonvolatile Memories for Computing
Partial Scan Using Multi-Hop State Reachability Analysis
QBIST: Quantum Built-in Self-Test for any Boolean Circuit
Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS
An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction
HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing
Techniques to Encode and Compress Fault Dictionaries
HLDTL: High-performance, low-cost, and double node upset tolerant latch design
Improving Gate-Level ATPG by Traversing Concurrent EFSMs
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs
Multi-Cycle Sensitizable Transition Delay Faults
IP session on ISO26262 EDA
Test generation for subtractive specification errors
Fault tolerant approximate computing using emerging non-volatile spintronic memories
Built in self test (BIST) for RSFQ circuits
The use of IDDQ testing in low stuck-at coverage situations
Efficient trace data compression using statically selected dictionary
Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs
Analysis of the die test optimization algorithm for negative binomial yield statistics
Calibration and Source Localization Using an Array of Resistive Metal Oxide Gas Sensors
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction
Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors
Innovative practices session 5C: Machine learning and data analysis in test
Security-aware SoC test access mechanisms
Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework
Design for testability of on-line multipliers
Innovative practices session 3C: Solving today's test challenges
Minimizing the Impact of Scan Compression
Volume Manufacturing - ICs and Boards: DFT to the Rescue?
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I DDQ monitoring
A New Secure Scan Design with PUF-based Key for Authentication
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements
DSP-Based Statistical Self Test of On-Chip Converters
Resistive Opens in a Class of CMOS Latches: Analysis and DFT
Analog and Mixed Signal BIST: Too Much, Too Little, Too Late?
Test Technology Educational Program (TTEP) Tutorials
Defective Pixel Analysis for Image Sensor Online Diagnostic and Self-Healing
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
Innovative practices session 4C data analytics in test
RT-level Fault Simulation Based on Symbolic Propagation
Fault Escapes in Duplex Systems