yusuke1997/dblp-id-title huggingface dataset:
A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantization
Energy-delay minimization in nanoscale domino logic
Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs
Shielding effect of on-chip interconnect inductance
A Bounding Box-based Net Partitioning Method for Double-sided Routing
Accelerating multi-party scheduling for transaction-level modeling
An asymmetric adaptive-precision energy-efficient 3DIC multiplier
Implementation of MOSFET based capacitors for digital applications
A qualitative simulation approach for verifying PLL locking property
Flexible blocks for high throughput serially concatenated convolutional codes
Trade-off between energy and quality of service through dynamic operand truncation and fusion
IoT-enabled Soft Robotics for Electrical Engineers
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks
Security Challenges of Processing-In-Memory Systems
More Efficient Accuracy-Ensured Waveform Compression for Circuit Simulation Supporting Asynchronous Waveforms
Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers
A low stand-by power start-up circuit for SMPS PWM controller
AttenPU: An Area Efficient Attention Processor with Reconfigurable FP8 Precision and Dataflow
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation
An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning
Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition
A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder
In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges
Implications of the Use of Magnetic Tunnel Junctions as Synapses in Neuromorphic Systems
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow
Enabling Approximate Storage through Lossy Media Data Compression
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection
Real-Time Analysis for Wormhole NoC: Revisited and Revised
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches
A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functions
TPNoC: An Efficient Topology Reconfigurable NoC Generator
LDL-SCA: Linearized Deep Learning Side-Channel Attack Targeting Multi-tenant FPGAs✱
Resource-Aware Saliency-Guided Differentiable Pruning for Deep Neural Networks
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip
Fault simulation and random test generation for speed-independent circuits
Tracking Data Flow at Gate-Level through Structural Checking
An efficient tabu search algorithm for graph bisectioning
An Analytical-based Hybrid Algorithm for FPGA Placement
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015
Efficient and Trusted Detection of Rootkit in IoT Devices via Offline Profiling and Online Monitoring
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation
GALSY, an automatic layout generator of symbolic layouts from MOS circuit schematics
Thumbnail rectilinear Steiner trees
Branch prediction techniques for low-power VLIW processors
Recent Advances in Brain-controlled Prosthetics for Paralysis: Friday Keynote
EATS: Energy-Aware Adaptive Topology Switching for NoCs
Experimental Validation of a Faithful Binary Circuit Model
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop
A Novel Fault-Tolerant Last-Level Cache to Improve Reliability at Near-Threshold Voltage
Dynamic Physically Unclonable Functions
Δ-trees of a graph: introduction and formal definition
An energy-efficient temporal encoding circuit technique for on-chip high performance buses
Low-Energy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and Multi-Level Classification
SOI for asynchronous dynamic circuits
Modular Placement for Interposer based Multi-FPGA Systems
Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms
A formula of STI cmp design rule
Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models
NeuroDSP Accelerator for Face Detection Application
Optimal technology mapping for single output cells
A VLSI Architecture for ATM Algorithm-Agile Encryption
An approach for multilevel logic cell optimization in module generators
Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations
Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging
Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003
XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators
Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series
A VLSI implementation of a state variable filter algorithm
An Energy Combiner Design for Multiple Microbial Energy Harvesting Sources
A Full-Swing Bootstrapped BiCMOS Buffer
Binarized Depthwise Separable Neural Network for Object Tracking in FPGA
Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach
Circuit-level NBTI macro-models for collaborative reliability monitoring
Energy Efficient Multi-Modal Stress Detection System with Dynamic Adaptive Spiking Neurons
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance
VLSI CAD tool protection by birthmarking design solutions
EPQUIC: Efficient Post-Quantum Cryptography for QUIC-Enabled Secure Communication
A Machine Learning Attack Resistant Dual-mode PUF
Transformation synthesis for data intensive applications to FPGAs
Asynchronous Neuromorphic Optimization in Lava
High frequency analog circuit design using QuickChip
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
Modell Evaluation Using Genetic Manipulation Techniques
Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level Synthesis
A Parametrical Architecture for Reed-Solomon Decoders
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries
MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering Architecture
Voltage island-driven power optimization for application specific network-on-chip design
An efficient cost-based canonical form for Boolean matching
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver
The Development of Analog SPICE Behavioral Model Based on IBIS Model
AFeCAM: An Energy Efficient Analog 1FeFET Content Addressable Memory
AQuRate: MRAM-based Stochastic Oscillator for Adaptive Quantization Rate Sampling of Sparse Signals
On-chip point-of-load voltage regulator for distributed power supplies
Scheduling with Confidence for Probabilistic Data-flow Graphs
Energy optimal sizing of FinFET standard cells operating in multiple voltage regimes using adaptive independent gate control
RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security
A scalable shared buffer ATM switch architecture
Two-dimensional multirate systolic array design for artificial neural networks
Performance-Driven Interconnect Global Routing
Medical Device Security: The First 165 Years
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation
Design of embedded MRAM macros for memory-in-logic applications
Unaligned Access Optimization with Request-based Mapping Scheme for Solid-state Drives
Causal probabilistic input dependency learning for switching model in VLSI circuits
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
H.264 8x8 inverse transform architecture optimization
Low-Power Design of Finite Field Multipliers for Wireless Applications
Approximate Memory with Approximate DCT
Red-Shield: Shielding Read Disturbance for STT-RAM Based Register Files on GPUs
Quantum-dot cellular automata SPICE macro model
A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing
Techniques for improved placement-coupled logic replication
Reducing BDD Size by Exploiting Structural Connectivity
CarbonSet: A Dataset to Analyze Trends and Benchmark the Sustainability of CPUs and GPUs
Delay fault testability evaluation through timing simulation
A design methodology for temperature variation insensitive low power circuits
An arbiter based on-chip droop detector system
8T1R: A Novel Low-power High-speed RRAM-based Non-volatile SRAM Design
Iterative decoding in analog CMOS
On-line detection of the deadlocks caused by permanently faulty links in quasi-delay insensitive networks on chip
Selective code/data migration for reducing communication energy in embedded MpSoC architectures
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates
Time-mode reconstruction iir filters for ΣΔ phase modulation applications
Enhancing SAT-based sequential depth computation by pruning search space
Formal Checking of Properties in Complex Systems Using Abstractions
Efficient modulo 2 n +1 multiplication for the idea block cipher
A novel parallel adaptation of an implicit path delay grading method
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing
Minimizing channel density with movable terminals
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
IVcache: Defending Cache Side Channel Attacks via Invisible Accesses
What to Lock?: Functional and Parametric Locking
Leakage current reduction by new technique in standby mode
A new systolic architecture for pipeline prime factor DFT-algorithm
SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction
Digital Arithmetic Using Analog Arrays
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis
BiNMAC: Binarized neural Network Manycore ACcelerator
Combined architecture and hardening techniques exploration for reliable embedded system design
Robust signaling techniques for through silicon via bundles
Design Automation of MEMS Systems Using Behavioral Modeling
Efficient realization of RTD-CMOS logic gates
Fpga-based hardware/software co-design for chirplet signal decomposition
Accommodating Transformer onto FPGA: Coupling the Balanced Model Compression and FPGA-Implementation Optimization
Exploiting frequent opcode locality for power efficient instruction cache
Extracting Designs of Secure IPs Using FPGA CAD Tools
StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features
ESFO: Equality Saturation for FIRRTL Optimization
Reinforcement Learning based Module Placement for Enhancing Reliability of MEDA Digital Microfluidic Biochips
Extended layered decoding of LDPC codes
Current Sensor on the Base of Permanent Pre-chargeable Amplifier
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs
Oxho-3D: An Analytical Die-to-Die 3D Placement Engine
Rapid-prototyping of high-assurance systems
The oct-touched tile: a new architecture for shape-based routing
Software adaptation in quality sensitive applications to deal with hardware variability
An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid Lithography
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit Applications
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input
Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers
VisNAV: An Autonomous, Unified, Focus-assisted Navigation in UAVs for Agricultural Field Operations
A high performance RNS multiply-accumulate unit
Fault Recovery from Multi-Tenant FPGA Voltage Attacks
Safe clocking for the setup and hold timing constraints in datapath synthesis
Energy-Efficient Machine Learning Accelerator for Binary Neural Networks
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors
Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications
Event-Driven Sensing and Embedded Neuromorphic Platforms for Gamma Radiation Monitoring
A universal formalization of the effects of threshold voltages for discrete switch-level circuit models
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
Maximizing Sub-Array Resource Utilization in Digital Processing-in-Memory: A Versatile Hardware-Aware Approach
An energy-aware co-simulation framework for the design of wireless sensor networks
SAT-Lancer: A Hardware SAT-Solver for Self-Verification
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures
AI-Driven Microelectronics Education Using Digital Twins and Extended Reality
Exploiting PSL standard assertions in a theorem-proving-based verification environment
An Order Sampling Processing-in-Memory Architecture for Approximate Graph Pattern Mining
Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Comparative Analysis of Hardware Obfuscation for IP Protection
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm
Towards formal probabilistic power-performance design space exploration
ILAFD: Accuracy-Configurable Floating-Point Divider Using an Approximate Reciprocal and an Iterative Logarithmic Multiplier
A VLSI wrapped wave front arbiter for crossbar switches
Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth
IRET: Incremental Resolution Enhancing Transformer
Concurrency-Aware Cache Miss Cost Prediction with Perceptron Learning
FPGA implementation of binary edwards curve usingternary representation
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning
Discrete Fourier transform processors using CORDIC
Physical aware clock skew rescheduling
Symbolic execution of data paths
Transistor sizing for reliable domino logic design in dual threshold voltage technologies
Innovating at Cloud Speed for IoT, AI, and Semiconductor Design
Yield-aware Performance-Cost Characterization for Multi-Core SIMT
Evolving Trust for High Consequence Microelectronics
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths
Active bank switching for temperature control of the register file in a microprocessor
On the generalized channel definition problem
Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects
Session details: Session 4A: Testing, Reliability and Fault Tolerance
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism
Session details: Session 2A: Hardware Security
Bridging the Gap between Hardware Fuzzing and Industrial Verification
A low-offset high-speed double-tail dual-rail dynamic latched comparator
Improving self-timed pipeline ring performance through the addition of buffer loops
Low-power weighted pseudo-random BIST using special scan cells
A first look at the interplay of code reordering and configurable caches
A keyword match processor architecture using content addressable memory
Linearized CMOS active resistor independent on the bulk effect
A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks
Dynamic instruction schedulers in a 3-dimensional integration technology
A high-performance online assay interpreter for digital microfluidic biochips
Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load
Characterizing the VCO jitter due to the digital simultaneous switching noise
Utilizing don't care states in SAT-based bounded sequential problems
FPGAs in the Datacenter: Combining the Worlds of Hardware and Software Development
A novel intermittent fault Markov model for deep sub-micron processors
Accurate Resource Estimation Algorithms for Behavioral Synthesis
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis
Blockchain-Enabled Whitelisting Mechanisms for Enhancing Security in 3D ICs
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power
Logic synthesis for low power using clock gating and rewiring
Automated Analysis of Virtual Prototypes at Electronic System Level
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
ApproxMA: Approximate Memory Access for Dynamic Precision Scaling
A high-speed radix-4 multiplexer-based array multiplier
AOP-based high-level power estimation in SystemC
Improving Lifetime of Multicore Soft Real-Time Systems through Global Utilization Control
A Reprogrammable FPGA-Based ATM Traffic Generator
Repeater insertion in power-managed VLSI systems
Evolutionary Large Language Models for Hardware Security: A Comparative Survey
The Curious Case of Trusted IC Provisioning in Untrusted Testing Facilities
Accelerating Homomorphic Comparison Operations for Thresholding Using an Asymmetric Input Range and Input Scaling
An interconnect-aware delay model for dynamic voltage scaling in NM technologies
Using dynamic domino circuits in self-timed systems
Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells
Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance
Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs
Power estimation for a submicron CMOS inverter driving a CRC interconnect load
Performance assessment of analog circuits with carbon nanotube FET (CNFET)
Software Fault Tolerance Using Dynamically Reconfigurable FPGAs
Energy-efficient bus encoding for LCD displays
The design of the fixed point unit for the z990 microprocessor
On-chip inductance modeling
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
Efficient pipelining for modular multiplication architectures in prime fields
Bioinspired Programming of Resistive Memory Devices for Implementing Spiking Neural Networks
TACPlace: Ultrafast Thermal-Aware Chiplet Placement with Feasibility Seeking
MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications
Local improvement in Steiner trees
Merged Arithmetic for Computing Wavelet Transforms
Graph theoretic approach for scan cell reordering to minimize peak shift power
An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories
Design of mixed gates for leakage reduction
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks
Mutually Disjoint Signals and Probability Calculation in Digital Circuits
Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs
A Scalable and Process Variation Aware NVM-FPGA Placement Algorithm
MI2D: Accelerating Matrix Inversion with 2-Dimensional Tile Manipulations
On efficient generation of instruction sequences to test for delay defects in a processor
A New Low-Voltage Full Adder Circuit
Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing
AB-Aware: Application Behavior Aware Management of Shared Last Level Caches
WRIP: logic restructuring techniques for wirelength-driven incremental placement
A practical approach to modeling skin effect in on-chip interconnects
An Approach for Testing Safety-Critical Software
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization
Thermal-aware voltage droop compensation for multi-core architectures
Evaluating Data Resilience in CNNs from an Approximate Memory Perspective
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits
DFM issues for 65nm and beyond
Performance driven placement with global routing for macro cells
Advanced Continuous-Time Convolution Framework for Security Assurance in Wireless Sensor Networks
Analysis of data dependence of leakage current in CMOS cryptographic hardware
A Clockless Sequential PUF with Autonomous Majority Voting
Circuits with light at the nanoscale: meta-nanocircuits and metactronics
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Thermal aware cell-based full-chip electromigration reliability analysis
Partitioning transition relations efficiently and automatically
Green computing: reducing energy cost and carbon footprint of information processing systems
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation
Tabu Search Based Circuit Optimization
A novel technique for sea of gates global routing
A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM)
AltGraph: Redesigning Quantum Circuits Using Generative Graph Models for Efficient Optimization
HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors
Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga
Threats on Logic Locking: A Decade Later
Squash: a scalable quantum mapper considering ancilla sharing
Global objectives for standard cell placement
Enhanced AI for Science using Diffusion-based Generative AI - A Case Study on Ultrasound Computing Tomography
A Remote FPGA-based Experimental Teaching System Design Supporting Single-board Multi-user and Multi-board Single-user Operations in MOOCs
Integrating Generative AI into Microelectronics Education: Implications for Learning and Pedagogical Practice
Soft Error Resilience Analysis of LSTM Networks
Lazy suspect-set computation: fault diagnosis for deep electrical bugs
Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012
Prove that a faulty multiplier is faulty!?
Convergence analyses of simulated evolution algorithms
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design
Moment-driven coupling-aware routing methodology
Incremental SAT-based Exact Synthesis
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs
Design tools for emerging technologies
First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991
A performance driven logic synthesis system using delay estimator
A 7T SRAM bit-cell for low-power embedded memories
A 5 GHz wide band input and output matched low noise amplifier
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits
Overview of Ferroelectric Memory Devices and Reliability Aware Design Optimization
ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG Signal
Uniform area timing-driven circuit implementation