yusuke1997/dblp-id-title huggingface dataset:
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing
Session 11 overview: Emerging memory and wireless technology
A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices
8.4 A Fast-Transient 3-Fine-Level Buck-Boost Hybrid DC-DC Converter with Half-Voltage-Stress on All Switches and 98.2% Peak Efficiency
1024 3D-Stacked Monolithic NEMS Array with 375μm 2 0.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing
14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR
A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor units
A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitry
A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b-Resolution Capacitance-to-Digital Converter from 1 to 100nF
A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural Implants
A mm-sized wirelessly powered and remotely controlled locomotive implantable device
From Silicon Aether and Back
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique
WLAN/Bluetooth
An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS
A compact dual-band digital doherty power amplifier using parallel-combining transformer for cellular NB-IoT applications
A Spur Suppression Technique for Phase-Locked Frequency Synthesizers
A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation
1.1 A smart design paradigm for smart chips
324GHz CMOS Frequency Generator Using Linear Superposition Technique
13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction
26.8 A 236nW -56.5dBm-sensitivity bluetooth low-energy wakeup receiver with energy harvesting in 65nm CMOS
F2: High-performance frequency generation for wireless and wireline systems
20-22nm technology options and design implications
Session 35 Overview: Adaptive Digital Techniques for Variation Tolerant Systems Digital Circuits Subcommittee
A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed
Improving CDR Performance via Estimation
Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint
Session 25 overview: Energy-efficient wireless
A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core
20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity
Through-silicon-via-based double-side integrated microsystem for neural sensing applications
35.3 Thread-Level Power Management for a Current- and Temperature-Limiting System in a 7nm Hexagon™ Processor
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface
An optimized driver for SiC JFET-based switches delivering more than 99% efficiency
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS
A 0.004mm 2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
23.2 A 436-to-467GHz Lens-Integrated Reconfigurable Radiating Source with Continuous 2D Steering and Multi-Beam Operations in 65nm CMOS
A fully integrated 24GHz UWB radar sensor for automotive applications
Analog Techniques and PLLs
Session 12 overview: Inductor-based power conversion: Analog subcommittee
18.3: A 93.3dB SNDR, 180.4dB FoMs Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-Error-Shaping Technique and Negative-R-Assisted Residue Integrator
Beyond-Classical Computing Using Superconducting Quantum Processors
Catalyzing the Impossible: Silicon, Software, and Smarts for the SysMoore Era
A -31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers
A 10Gb/s photonic modulator and WDM MUX/DEMUX integrated with electronics in 0.13µm SOI CMOS
A 200mV 32b subthreshold processor with adaptive supply voltage control
9.1 A resistor-based temperature sensor with a 0.13pJ·K 2 resolution FOM
A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
A Compact DC-to-108GHz Stacked-SOI Distributed PA/Driver Using Multi-Drive Inter-Stack Coupling, Achieving 1.525THz GBW, 20.8dBm Peak P1dB, and Over 100Gb/s in 64-QAM and PAM-4 Modulation
A 13.56MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systems
A dual-conversion-gain video sensor with dewarping and overlay on a single chip
Session 12 overview: DRAM: Memory subcommittee
CMOS-Driven Pneumatic-Free Scalable Microfluidics and Fluid Processing with Label-Free Cellular and Bio-Molecular Sensing Capability for an End-to-End Point-of-Care System
F2: VLSI power-management techniques: Principles and applications
6.5 A 64×64-pixel digital silicon photomultiplier direct ToF sensor with 100Mphotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6km for spacecraft navigation and landing
A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation
An ultra-low-power 9.8GHz crystal-less UWB transceiver with digital baseband integrated in 0.18µm BiCMOS
5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability
Session 27 overview: Hybrid and nyquist data converters
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs
17.7 A 0.03mV/mA Low Crosstalk and 185nA Ultra-Low-Quiescent Single-Inductor Multiple-Output Converter Assisted by 5-Input Operational Amplifier for 94.3% Peak Efficiency and 3.0W Driving Capability
An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain
15.8 A 22.3b 1kHz 12.7mW switched-capacitor ΔΣ modulator with stacked split-steering amplifiers
A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converter
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices
A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18μm CMOS
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS
A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise
F1: Integrated voltage regulators for SoC and emerging IoT systems
Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee
22.1 THz Prism: One-Shot Simultaneous Multi-Node Angular Localization Using Spectrum-to-Space Mapping with 360-to-400GHz Broadband Transceiver and Dual-Port Integrated Leaky-Wave Antennas
A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders
27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET
SC1: Biomedical and sensor interface circuits
A 256x256 CMOS Microelectrode Array for Extracellular Neural Stimulation of Acute Brain Slices
7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networks
A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend
Ultra-low-voltage circuits for sensor applications powered by free-space optics
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link
7.5 A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact Suppression
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee
A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture
A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier
15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation
6.9 A 0.35V 0.367TOPS/W Image Sensor with 3-Layer Optical-Electronic Hybrid Convolutional Neural Network
60 and 77GHz Power Amplifiers in Standard 90nm CMOS
A 19.7-to-43.8GHz Power Amplifier with Broadband Linearization Technique in 28nm Bulk CMOS
A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor
A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
A 0.0056mm 2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM
A 95fJ/b current-mode transceiver for 10mm on-chip interconnect
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup
A 2-to-16GHz 204mW 3mm-resolution stepped-frequency radar for breast-cancer diagnostic imaging in 65nm CMOS
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm
Session 11 overview: Sensors and MEMS: Imagers, MEMS, medical and displays subcommittee
A 5, th -order CT/DT Multi-Mode ΔΣ Modulator
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control
A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications
A timing controlled AC-DC converter for biomedical implants
A ±0.4°C (3σ) -70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2
16.2 A 28nm 69.4kOPS 4.4μJ/Op Versatile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS
Session 22 overview: Gigahertz data converters: Data converter subcommittee
A Dual-Band CMOS Transceiver for 3G TD-SCDMA
A 0.55V 16Mb/s 1.6mW non-coherent IR-UWB digital baseband with ±1ns synchronization accuracy
8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
8.2 A 96.9%-Peak-Efficiency Bilaterally-Symmetrical Hybrid Buck-Boost Converter Featuring Seamless Single-Mode Operation, Always-Reduced Inductor Current, and the Use of All CMOS Switches
A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO
Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommittee
A 40nm wideband direct-conversion transmitter with sub-sampling-based output power, LO feedthrough and I/Q imbalance calibration
A multiband multimode transmitter without driver amplifier
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning
Harnessing technology to advance the next-generation mobile user-experience
15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts
3D clock distribution using vertically/horizontally-coupled resonators
F6: Mixed-signal/RF design and modeling in next-generation CMOS
Session 14 overview: Digital PLLs and building blocks
A self-biased 5-to-60V input voltage and 25-to-1600µW integrated DC-DC buck converter with fully analog MPPT algorithm reaching up to 88% end-to-end efficiency
26.4 A Reflection-Coefficient Sensor for 28GHz Beamforming Transmitters in 22nm FD-SOI CMOS
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies
25.2 A 210-to-305GHz CMOS receiver for rotational spectroscopy
A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB
37.2 A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm 2 SoC and bySPI Chiplets
An 8×16-pixel 92kSPAD time-resolved sensor with on-pixel 64ps 12b TDC and 100MS/s real-time energy histogramming in 0.13µm CIS technology for PET/MRI applications
A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment
A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications
A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF Modulator
A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency control
A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range
A 28Gb/s transceiver with chirp-managed EDC for DML systems
21.3 A 5.69mm 2 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications
IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019
28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output
5.3 A 2×70W monolithic five-level Class-D audio power amplifier
90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization
A 1V 2.3µW Biomedical Signal Acquisition IC
7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE
A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS
A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS
14.1 A 0.048mm 2 3mW synthesizable fractional-N PLL with a soft injection-locking technique
24-channel dual-band wireless neural recorder with activity-dependent power consumption
A Single-Chip CMOS Radio SoC for v2.1 Bluetooth Applications
An Integrated LDI with Readout Function for Touch-Sensor-Embedded Display Panels
32.5 A Scalable and PCB-Friendly Daisy-Chain Approach to Parallelize LDO Regulators with 2.613% Current-Sharing Accuracy Using Dynamic Element Matching for Integrated Current Sensing
A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors
19.1 A fundamental-frequency 114GHz circular-polarized radiating element with 14dBm EIRP, -99.3dBc/Hz phase-noise at 1MHz offset and 3.7% peak efficiency
An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS
A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully State-based Phase Selection Achieving Simultaneous High-Speed $\mathbf{V}_{\text{CF}}$ Balancing and Smooth Transition
A phase-noise and spur filtering technique using reciprocal-mixing cancellation
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS
The role of semiconductors in the energy landscape
A Blocker Filtering Technique for Wireless Receivers
2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014
1.2V 1.6Gb/s 56nm 6F 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology
A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8 TM microprocessor
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications
A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band
7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology
2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET
A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS
A 400-to-1000nm 24μ W Monolithic PPG Sensor with 0.3A/W Spectral Responsivity for Miniature Wearables
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration
An 18.5nF-Input-Range PM-SAR-Hybrid Capacitance-to-Digital Converter Achieving 6.1μs Conversion Time at 18.1pF Input Capacitance
A 65nm low-power embedded DRAM with extended data-retention sleep mode
Session 10 overview: DC-DC converters
A multimode 76-to-81GHz automotive radar transceiver with autonomous monitoring
F1: Advanced RF transceiver design techniques
11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET Technology
A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS
12.9 A fully integrated 6W wireless power receiver operating at 6.78MHz with magnetic resonance coupling
Semiconductor innovation: Is the party over, or just getting started?
A 1.23W/mm 2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns
Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee
27.4 A sub-1dB NF dual-channel on-coil CMOS receiver for Magnetic Resonance Imaging
5.10 A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOS
A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissions
A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter with 100µg/h/√Hz Noise i Floor and Zero Stability of ±0.35mg/h
A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from -40°C to 125°C
32.6 A Dynamic-RON-Diminished Bidirectional GaN Load Switch with Inrush Current Protection and Spike Attenuation
10.8 A 281GHz, -1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter D-Band Cascaded Subharmonically Injection-Locked Sub-Sampling PLL with a 274MHz Reference
6.2 High-capacity scalable optical communication for future Optical Transport Network
21.1 A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS Transceiver
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×
2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers
A digitally modulated mm-Wave cartesian beamforming transmitter with quadrature spatial combining
An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications
8.7 A 0.0047mm 2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz
Session 6 Overview: High-Performance Receivers and Transmitters for Sub-6GHz Radios Wireless Subcommittee
29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
25.3 A 40-to-330GHz synthesizer-free THz spectroscope-on-chip exploiting electromagnetic scattering
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee
14.5 A 0.53THz reconfigurable source array with up to 1mW radiated power for terahertz imaging applications in 0.13μm SiGe BiCMOS
12.3 A Scalable and Instantaneously Wideband 5GS/s RF Correlator Based on Charge Thresholding Achieving 8-bit ENOB and 152 TOPS/W Compute Efficiency
A 3D vision 2.1Mpixel image sensor for single-lens camera systems
A 0.53pJK 2 7000μm 2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS
An 8b Source Driver for 2.0 inch Full-Color Active-Matrix OLEDs Made with LTPS TFTs
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications
26.2 Power supply noise in a 22nm z13™ microprocessor
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs
A UMTS-complaint fully digitally controlled oscillator with 100Mhz fine-tuning range in 0.13µm CMOS
A 28GHz 41%-PAE linear CMOS power amplifier using a transformer-based AM-PM distortion-correction technique for 5G phased arrays
21.5 A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light-Load-Efficiency Peak of 86%, Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS
20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor
10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
6.11 A 320x240 CMOS LiDAR Sensor with 6-Transistor nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogram Memory
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications
An 86% efficiency SIMO DC-DC converter with one boost, one buck, and a floating output voltage for car-radio
Session 2 Overview: Highlighted Chip Releases: 5G and Radar Systems Invited Papers
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB
Robust VLSI circuit design & systems for sustainable society
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting
Things all RFIC designers should know (But are afraid to ask)
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation
ES2: Data centers to support tomorrow's cloud
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications
A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement
A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput