yusuke1997/dblp-id-title huggingface dataset:
Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing
Evaluation of Attitude Estimation Algorithm under Soft Error Effects
On Comparing and Complementing two MBT approaches
Functional verification of logic modules for a Gigabit Ethernet switch
Parametric model calibration and measurement extraction for LFN using virtual instrumentation
Protecting analog circuits with parameter biasing obfuscation
Low cost signal reconstruction based testing of RF components using incoherent undersampling
A case study for Formal Verification of a timing co-processor
An improved OBT strategy for untuned continuous-time analog filters
Double Column Error Correction in RRAM Matrix Multiplication Using Weighted Checksums
Generalized Distributed Comparison-Based System-Level Diagnosis
Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches
Testing for faults, looking for defects
Optimized hybrid verification of embedded software
Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC
An Overview Covering the Different Solutions: from radiation testing to Software Fault Injection
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects
A Revised Isolation Forest procedure for Anomaly Detection with High Number of Data Points
Specific Tests of Thin Film Devices for Large Area Electronics
Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis
Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations
Assessing the Reliability of Different Split Computing Neural Network Applications
Space Radiation Flux Driven Fault Injection for Evaluating Dynamic Mitigation Strategies
Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategy
Harmonic distortion correction for 8-bit delay line ADC using gray code
Testing Heatsink Faults in Power Transistors by means of Thermal Model
Improved Fault Detection Using a Charge Monitor
Enhancing Logic Diagnosis of Field Returns Through Logic BIST in Automotive SoCs
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications
Low-cost DC BIST for analog circuits: A case study
A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking
Merging BIST and Configurable Computing Technology to Improve Availability in Space Applications
Challenges and emerging solutions in testing HBM IO & systems
TMR technique for mutex kernel data structures
On the functional test of the BTB logic in pipelined and superscalar processors
A Flexible UVM-Based Verification Framework Reusable with Avalon, AHB, AXI and Wishbone Bus Interfaces for an AES Encryption Module
On the reuse of RTL assertions in SystemC TLM verification
A Test Calculation Principle for Logic and Timing Faults
On the SCA Resistance of Crypto IP Cores
Improving logic obfuscation via logic cone analysis
Experimental dependability assessment using a faultload specification tool
SEU fault-injection at system level: Method, tools and preliminary results
Formally verifying an RTOS scheduling monitor IP core in embedded systems
Dependability validation of a cryptoprocessor to SEU effects
Using Reconfigurability Features to Break Down Test Costs: a Case Study
Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits
MiFIT: A Fault Injection Tool to Validate the Reliability of Microprocessors
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme
Upset-like fault injection in VHDL descriptions: A Method and Preliminary Results
Impact of Thermal Effects on Cryptographic Resilience: A Study of an ASIC Implementation of the Montgomery Ladder
Exemplar-based failure triage for regression design debugging
Variability-aware physical design techniques
Handling manufacturing and aging faults with software-based techniques in tiny embedded systems
Superimposed in-circuit debugging for self-healing FPGA overlays
Total Ionizing Dose Effects on Floating Gate Structures. Preliminary Results
Towards Vehicle-Level Simulator Aided Failure Mode, Effect, and Diagnostic Analysis of Automotive Power Electronics Items
Test compression for circuits with multiple scan chains
25th IEEE Latin American Test Symposium, LATS 2024, Maceio, Brazil, April 9-12, 2024
Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential Amplifier
Single event effect: Simulations and analysis on 3N163 PMOS transistor
A DMA and CACHE-based stress schema for burn-in of automotive microcontroller
DOC: Detection of On-Line Failures in CNNs
Attacking the smart grid using public information
MoDiVHA: A hierarchical strategy for distributed test assignment
NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time
23rd IEEE Latin American Test Symposium, LATS 2022, Montevideo, Uruguay, September 5-8, 2022
Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis
Fault injection methodology for single event effects on clock-gated ASICs
Considerations on application of selective hardening based on software fault tolerance techniques
SPICE level analysis of Single Event Effects in an OxRRAM cell
Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs
22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021
Using mixed-mode test bus architecture to RF-based fault injection analysis and EMC fault debug
An algorithm for diagnostic fault simulation
Fast worst-case peak temperature evaluation for real-time applications on multi-core systems
Adopting multi-valued logic for reduced pin-count testing
On the detection of board delay faults through the execution of functional programs
Analyzing Side-Channel Attack Vulnerabilities at RTL
Testing Fault Tolerance Mechanisms in DBMS Through Fault Injection
Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications
Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks
Preserving and Improving Verifiability of Circuits Based on Local Transformations
Investigating the effects of transient faults in Programmable Capacitor Arrays
Retiming scan circuit to eliminate timing penalty
Processor core profiling for SEU effect analysis
Improving the robustness of a switch box in a mesh of clusters FPGA
Improving approximate-TMR using multi-objective optimization genetic algorithm
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters
Comparing Exhaustive and Random Fault Injection Methods for Configuration Memory on SRAM-based FPGAs
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect
Evaluating Approaches of Information Capturing from Applications Information
Software-based self-test generation for microprocessors with high-level decision diagrams
A Software Tool for Simulating Single Event Upsets in a Digital Signal Processor
Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GA
Impact of Soft Errors on High Performance Autoencoders for Cyberattack Detection
Evaluating the effectiveness of D-chains in SAT-based ATPG
Dependability evaluation of COTS microprocessors via on-chip debugging facilities
A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects
Investigation of Single Event Effects in a Resistive RAM memory array by SPICE level simulation
An effective strategy for selective hardening of software
Low latency reconfiguration mechanism for fine-grained processor internal functional units
Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios
Hard-to-Detect Faults by Dinamic Current Sensor in Analogue Circuits
Comparing different solutions for testing resistive defects in low-power SRAMs
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements
Fast fault injection techniques using FPGAs
PSL assertion checkers synthesis with ASM based HLS tool ABELITE
On BTI Aging Rejuvenation in Memory Address Decoders
Non-stationary Communication Dalays in Failure Detectors
Analysis of short defects in FinFET based logic cells
A Combined Strategy for Testing RRAMs After Manufacturing and During Lifetime
A New Approach to Software-Implemented Fault Tolerance
Improvement of a VCO concept for low energy particule detection and recognition
Seamless Testing of Embedded Control Systems
A review of approximate computing techniques towards fault mitigation in HW/SW systems
A Token-Based Testing Strategy for Non-Broadcast Network Diagnosis
Implementing indirect test of RF circuits without compromising test quality: a practical case study
SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core
Real-time validation of mixed-criticality applications
As Aspect-Oriented Fault Injection Tool to Test Fault Tolerant Mechanisms of Dependable Java-based Network Applications
Memristor-based filtering applications
Applying FIRMAMENT to test the SCTP communication protocol under network faults
Efficient and Exact Diagnosis of Multiple Stuck-At Faults
Test mode method and strategy for RF-based fault injection analysis for on-chip relaxation oscillators under EMC standard tests or RFI susceptibility characterization
Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital Domain
Modeling the effect of process variations on the timing response of nanometer digital circuits
SoC Memory Test Optimization using NXP MTR Solutions
Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs
Co-optimization of security and accessibility to on-chip instruments
Case Study: AI-Driven Log Extraction and Trace Outlier Detection for Efficient Post-Silicon Validation
Fault model qualification by assertion mining
Soft error analysis in embedded software developed with & without operating system
A Brief Review of Logarithmic Multiplier Designs
Cube Subtraction in SAT Solvers
MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips
On-line test and monitoring of multi-processor SoCs: A software-based approach
Implementing a Self-Checking PROFIBUS Slave
Hybrid soft error mitigation techniques for COTS processor-based systems
On improving real-time observability for in-system post-silicon debug
Electromagnetic Immunity Test of Analog-to-Digital Interfaces of a Mixed-Signal Programmable SoC
Microservices-based architecture for fault diagnosis in tele-rehabilitation equipment operated via Internet
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area
FPGA redundancy recovery based on partial bitstreams for multiple partitions
An Analog-based Approach for MEMS Testing
Probabilistic High-Level Estimation of Vulnerability and Fault Mitigation of Critical Systems Using Fault-Mitigation Trees (FMTs)
Estimating the Impact of Soft Errors on AI-Based Perception in Automotive
Adaptive approach to tolerate multiple faulty links in Network-on-Chip
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor
Development and evaluation of a flexible instrumentation layer for system-level testing of radiation effects
A Fault Injection Environment for SoPC's Embedded Microprocessors
A Test Architecture and VIE to Characterize Dielectric Absorption in Small Capacitors
Validation and Verification of Complex Digital Systems: A Practical Perspective
Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs
Blockchain Applied In Decentralization of Ground Stations To Educational Nanosatellites
Alternative functional verification methodology for low and medium level designs (Applied to an AES encryption module)
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG
Fast and Exact is Doable: Polynomial Algorithms in Test and Verification
Implementation and experimental evaluation of a CUDA core under single event effects
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination
On Line IC Test Course With Distance Access to Test Equipment
Test set generation almost for free using a run-time FPGA reconfiguration technique
A Synchronous Testing Strategy for Hierarchical Adaptive Distributed System-Level Diagnosis
Impact of RF-based fault injection in Pierce-type crystal oscillators under EMC standard tests in microcontrollers
Radiation effects in low power and ultra low power voltage references
Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometry
Using software invariants for dynamic detection of transient errors
Harmonic Response of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks
A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors
Concurrent test of Network-on-Chip interconnects and routers
Software Testing in Client-Server Environments: a Strategy and its Application
Assessment of diagnostic test for automated bug localization
Design Considerations Towards Zero-Variability Resistive RAMs in HRS State
Low voltage testing for interconnect opens under process variations
14th Latin American Test Workshop, LATW 2013, Cordoba, Argentina, 3-5 April, 2013
Simulation framework for multilevel power estimation and timing analysis of digital systems allowing the consideration of thermal effects
Fault conditions of a simple chaotic circuit under capacitor nonlinear effects
Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus Standard
Generation of Simulated Neutrino Signals for the Digitization Subsystem in the DAPHNE Test Bench of the DUNE Experiment
Zero Overhead Error-Tolerant Communication
Analyzing graph-based algorithms employed to generate test cases from finite state machines
SET susceptibility estimation of clock tree networks from layout extraction
Risk Assessment and Prediction in Human-Robot Interaction Through Assertion Mining and Pose Estimation
An Integrated Environment for the Reliability Assessment of CNNs Accelerators Implemented in FPGAs
Defect-Location Identification for Cell-Aware Test
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing
Leveraging ATE to Optimize System-Level-Test for Multicore Automotive SoCs
Dynamic Fault Injection in Integrated Circuits with a Pulsed Laser
On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs
A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests
Testability of Circuits Derived from Lattice Diagrams
A modern look at the CMOS stuck-open fault
Parametric faults detection and concealment on imager with FPGA implementation
A new Built-In Current Sensor scheme to detect dynamic faults in Nano-Scale SRAMs
A RTN variation tolerant guard band design for a deeper nanometer scaled SRAM screening test: Based on EM Gaussians mixtures approximations model of long-tail distributions
A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage
Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied
Resistive Open Defect Classification of Embedded Cells under Variations
Towards a transmission power self-optimization in reliable Wireless Sensor Networks
Using FPGA self-produced transients to emulate SETs for SER estimation
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking
Analyzing the Reliability of Stream Sparse Matrix-Vector Multiplication Accelerators: A High-Level Approach
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture
Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method
Local data fusion algorithm for fire detection through mobile robot
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test
Power distribution network analysis using semi irregular plane shape approach and via modeling
LFSR characteristic polynomial and phase shifter computation for two-dimensional test set generation
Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Bridging Faults and n-Detect Test
Mutation operators for concurrent programs in MPI
26th IEEE Latin American Test Symposium, LATS 2025, San Andres Islas, Colombia, March 11-14, 2025
28 nm FD-SOI 4 K RF LNA Design Using DC Transistor Characterization Measurements
A fault-tolerant service discovery protocol for emergency search and rescue missions
3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002
Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs
Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis
Aging and Soft Error Resilience in Reconfigurable CNN Accelerators Employing a Multi-Purpose On-Chip Sensor
Evaluating the Code Encryption Effects on Memory Fault Resilience
Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation
Physical-aware pattern selection for stuck-at faults
Detectability Dependency on Test Generation Process for Interconnection Opens
Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs
Determination of Silicon Film Thickness in SOI Capacitors
The Sigma-Delta-Bist Method Applied to Linear Analog Circuits
Heterogeneous integration: Beyond CMOS - coping with variability at the end of the CMOS roadmap
SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA
24th IEEE Latin American Test Symposium, LATS 2023, Veracruz, Mexico, March 21-24, 2023
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard
ISA configurability of an FPGA test-processor used for board-level interconnection testing
Study of radiation effects on PIN photodiodes with deep-trap levels using computer modeling
Fault prediction in electrical valves using temporal Kohonen maps
Fault Tolerant Architecture Design of a CubeSat Command and Data Handling System
Improved Methods for Fault Diagnosis in Scan-Based BIST
Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs
Software-Based Mitigation for Memory Address Decoder Aging
A deep analysis of SEU consequences in the internal memory of LEON3 processor
Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects
Methodology and platform for fault co-emulation
Laser Utilization for Various Testing Purposes
Architecture of an industrial analog input designed to meet safety requirements
On the Evaluation of Heartbeat-like Detectors
Towards an automatic generation of diagnostic in-field SBST for processor components
Reliability Assessment Methodologies for ANN-based Systems
SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System
Analysis of SEU parameters for the study of SRAM cells reliability under radiation
Evaluating a New RRAM Manufacturing Test Strategy
OBT applied to a 2nd order continuous time Feedforward Sigma Delta modulator
Silent Error Corruption: The New Reliability and Test Challenge
Reliability and safety of medical equipment by use of calibration and certification instruments
Topological Considerations for the Diagnosability Conditions of Analogue CircuitsUsing a Pair of Conjugate Trees
On the derivation of a minimum test set in high quality transition testing
Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors
Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning
Analysis of the effects of single event transients on an SAR-ADC based on charge redistribution
1st Latin American Test Workshop, LATW 2000, Rio de Janeiro, RJ, Brazil, March 13-15, 2000
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment
On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design
Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test
Specification test minimization for given defect level
On-Chip Aging Sensor Core for Silicon Lifecycle Management
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell
Automatic generation of a parameter-domain-based functional input coverage model
Evaluating the effects of single event upsets in soft-core GPGPUs
Orienting Redundancy and HW/SW Codesign Techniques Towards Speech Recognition Systems
The hype, myths, and realities of testing 2.5D/3D integrated circuits
Multi-Level Testing Strategy for Radiation Hardened SOI/SOS ICs
An approach to LFSR-based X-masking for built-in self-test
Test Challenges in a Nanometric World
IoT-Based Digital Twin for Vehicle Battery Testing and Emissions Analysis
Studying the influence of chip temperatures on timing integrity
SW-based transparent in-field memory testing
Invited Talk: Pros and Cons of Assertion Mining
Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors
Reliability analysis of small delay defects in vias located in signal paths
Path Selection Strategies in the Context of Software Testing Criteria
Post-silicon validation based on synthetic test patterns for early detection of timing anomalies
The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles
Scan chain configuration method for broadcast decompressor architecture
Fault tolerance assessment of PIC microcontroller based on fault injection
Single event effects in an analog SOI transconductor: a case study
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors
Detecting hard synapses faults in artificial neural networks
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery
Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing
Automated test-bed for analog to digital converters
Study of regression methodologies on analog circuit design
Impact of SEU configurations on a SRAM cell response at circuit level
Analyzing and quantifying fault tolerance properties
A Test Method for a Broad Class of DSP Circuits
A New Efficient Coordinated Checkpointing
Evaluation of a mixed-signal design diversity system under radiation effects
Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment
Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller
A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults
Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization
Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic
Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip