yusuke1997/dblp-id-title huggingface dataset:
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
Granidt: Towards Gigabit Rate Network Intrusion Detection Technology
System Design with Genetic Algorithms
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching
Efficiently Generating FPGA Configurations through a Stack Machine
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
Design Space Exploration of the European Option Benchmark Using HyperStreams
FPGA Implementation of 64-bit Exponential Function for HPC
UniStream: A unified stream architecture combining configuration and data processing
The Rising Wave of Field Programmability
FPGA support for satellite computations of hyper spectral images
Network processors
A Load/Store Unit for a Memcpy Hardware Accelerator
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators
Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs
Software Radio Reconfigurable Hardware System (SHaRe)
Modeling post-techmapping and post-clustering FPGA circuit depth
Reducing interconnection cost in coarse-grained dynamic computing through multistage network
Secure FPGA configuration architecture preventing system downgrade
29th International Conference on Field Programmable Logic and Applications, FPL 2019, Barcelona, Spain, September 8-12, 2019
The Trianus System and Its Application to Custom Computing
Application-specific soft-core vector processor for advanced driver assistance systems
Predictive Load Balancing for Interconnected FPGAs
Towards a Reconfigurable Tracking System
Controller architecture for low-latency access to phase-change memory in OpenPOWER systems
Designing a virtual runtime for FPGA accelerators in the cloud
Chip-Based Reconfigurable Task Management
FPL Demo: Kyokko - An Aurora 64b66b compatible 100 Gbps Communication Controller
Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives
24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2-4 September, 2014
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules
Optimal Finite Field Multipliers for FPGAs
Building Run-Time Reconfigurable Systems from Tiles
A scalable architecture for multi-class visual object detection
Early performance estimation of image compression methods on soft processors
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses
Providing Multi-tenant Services with FPGAs: Case Study on a Key-Value Store
Dynamic Reconfiguration Optimisation with Streaming Data Decompression
Partial Reconfiguration for Design Optimization
Demo: A Closer Look at Malicious Bitstreams
Concurrent Design of Hardware/Software Dedicated Systems
Multithreading in a Hyper-programmable Platform for Networked Systems
Case for Fast FPGA Compilation Using Partial Reconfiguration
Implementing On Line Arithmetic on PAM
Maia: Matrix Inversion Acceleration Near Memory
A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN
On-the-fly attestation of reconfigurable hardware
Early Prediction of Hardware Complexity in HLL-to-HDL Translation
A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck
Hardware Accelerated Novel Protein Identification
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS
Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles
Quantitative Analysis of Run-Time Reconfigurable Database Search
Generation of multi-core systems from multithreaded software
Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures
Using 3D integration technology to realize multi-context FPGAs
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers
Correctly rounded floating-point division for DSP-enabled FPGAs
An automatic FPGA design and implementation framework
An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic
A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs
Some Notes on Power Management on FPGA-Based Systems
Optimization Techniques for Hestenes-Jacobi SVD on FPGAs
Towards dark silicon era in FPGAs using complementary hard logic design
Hybrid FPGA-accelerated SQL query processing
Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation
Analysis and Optimization of 3-D FPGA Design Parameters
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects
Solving Boolean Satisfiability with Dynamic Hardware Configurations
A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test
Implementing Photoshop Filters in Virtex
Automating the Layout of Reconfigurable Subsystems via Template Reduction
Efficient particle-pair filtering for acceleration of molecular dynamics simulation
General Digit Width Normal Basis Multipliers with Circular and Linear Structure
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems
A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits
A partial reconfiguration based microphone array network emulator
A partial reconfiguration controller for Altera Stratix V FPGAs
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers
Hierarchical reconfiguration of FPGAs
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms
A security library for FPGA interlays
Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks
Very High Speed 17 Gbps SHACAL Encryption Architecture
Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs
An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor
Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit
A New Switch Block for Segmented FPGAs
Second Order Function Approximation Using a Single Multiplication on FPGAs
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs
An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
FPGA Acceleration of Rigid Molecule Interactions
Scalable high performance computing on FPGA clusters using message passing
Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs
Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack
Stress-Resiliency of AI Implementations on FPGAs
The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays
Formal CAD Techniques for Safety-Critical FPGA Design and Deployment in Embedded Subsystems
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems
Demonstration of a context-switch method for heterogeneous reconfigurable systems
Global Routing Models
Simultaneous Timing Driven Clustering and Placement for FPGAs
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model
Accelerating Molecular Dynamics Simulations With Configurable Circuits
Stream synthesis for a wormhole run-time reconfigurable platform
Power Consumption Reduction Through Dynamic Reconfiguration
An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization
FPL Demo: Hot Reconfiguration - Partial Reconfiguration without Bounds
FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007
Networks on Chip as Hardware Components of an OS for Reconfigurable Systems
Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V
FPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligence
Altering LUT configuration for wear-out mitigation of FPGA-mapped designs
Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs
Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings
Token Packing for Transformers with Variable-Length Inputs
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
Multithreading for Logic-Centric Systems
Multi-terminal BDD synthesis and applications
High-Performance and Parameterized Matrix Factorization on FPGAs
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration
HW-Driven Emulation with Automatic Interface Generation
A Field-Programmable Gate-Array System for Evolutionary Computation
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
Statistical Power Estimation for FPGA
A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs
rrBox: A remote dynamically reconfigurable network processing middlebox
Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA
FACT: Co-evaluation Environment for FPGA Architecture and CAD System
Laura: Leiden Architecture Research and Exploration Tool
GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips
FPGA Implementation of a Prototype WDM On-Line Scheduler
An Implementation of the Mean Shift Filter on FPGA
On accelerating pair-HMM computations in programmable hardware
The >S<puter: Introducing a Novel Concept for Dispatching Instructions Using Reconfigurable Hardware
Accelerating Local Laplacian Filters on FPGAs
Caching memcached at reconfigurable network interface
Irregular Reconfigurable CAM Structures for Firewall Applications
A Test Methodology Applied to Cellular Logic Programmable Gate Arrays
Modified Fuzzy C-Means Clustering Algorithm for Real-Time Applications
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs
FSSD: FPGA-Based Emulator for SSDs
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
Maximizing the reuse of routing resources in a reconfiguration-aware connection router
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems
Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign
Flexible FPGA design for FDTD using OpenCL
DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems
Ultra low latency dataflow renderer
An FPGA-based Hybrid Memory Emulation System
A 800 Mpixel/sec reconfigurable image correlator on XC6216
Improved resource sharing for FPGA DSP blocks
Multiple-Wordlength Resource Binding
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques
A Configurable Logic Processor for Machine Vision
BIT-Serial FIR Filters with CSD Coefficients for FPGAs
Quantised Siamese Tracker for 4K/UltraHD Video Stream - a demo
A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms
A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations
Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications
Fast FPGA system for microarchitecture optimization on synthesizable modern processor design
Virtualization of Embedded Reconfigurable Systems
Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions
Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine
Towards the Efficient Multi-Platform Execution of Deep Neural Networks
An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware
NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations
FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes
Robust FPGA Design under Variations
Introducing ReConfigME: An Operating System for Reconfigurable Computing
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management
TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features
FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach
Resource Elastic Virtualization for FPGAs Using OpenCL
A scalable FPGA architecture for nonnegative least squares problems
Bil: A tool-chain for bitstream reverse-engineering
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
viciLogic2.0 Online Learning and Prototyping Using PYNQ
Synthesis of the SR programming language for complex FPGAs
Energy-Aware Synchronization of Hardware Tasks in Virtualized Embedded Systems
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs
On Feasibility of FPGA Bitstream Compression During Placement and Routing
Run-time optimization of a dynamically reconfigurable embedded system through performance prediction
Performance comparison of FPGA, GPU and CPU in image processing
Customizable domain-specific computing
Parallelizing Simulated Annealing-Based Placement Using GPGPU
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision
Latency-driven design for FPGA-based convolutional neural networks
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms
A CMOS Field Programmable Analog Array for intelligent sensory application
Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC
FPGA-based design and implementation of a multi-GBPS LDPC decoder
High Performance Quadrature Digital Mixers for FPGAs
SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures
Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings
WebScope: A Circuit Debug Tool
Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core
Run-Time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration
Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment
Incremental Fault Emulation
An analytical model relating FPGA architecture and place and route runtime
FPGA Implementation of the Wavelet Packet Transform for High Speed Communications
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
A System Level Resource Estimation Tool for FPGAs
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions
Project of IPv6 Router with FPGA Hardware Accelerator
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules
High-performance video content recognition with long-term recurrent convolutional network for FPGA
Defect Tolerance in Multiple-FPGA Systems
A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability
Virtual radix array processors (V-RaAP)
Non-Uniform Random Number Generation Through Piecewise Linear Approximations
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation
A Novel Toolset for the Development of FPGA-like Reconfigurable Logic
Magnitude modulation on reconfigurable computing devices
MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
Reconfigurable Systems: New Activities in Asia
A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs
Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor
Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking
Towards heterogeneous solvers for large-scale linear systems
Run-time compaction of FPGA designs
A System on Chip for Power Line Communications According to European Home Systems Specifications
A High-performance Open-channel Open-way NAND Flash Controller Architecture
DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification
Performance analysis of fully-adaptable CRC accelerators on an FPGA
VIZARD II: An FPGA-based Interactive Volume Rendering System
Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play?
System Level Tools for DSP in FPGAs
SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration
A Library of Parameterized Floating-Point Modules and Their Use
Placement and Timing for FPGAs Considering Variations
FPGA acceleration in EVOLVE's Converged Cloud-HPC Infrastructure
Acceleration of distance-to-default with hardware-software co-design
On Applying Software Development Best Practice to FPFAs in Safety Critical Systems
Power-efficient range-match-based packet classification on FPGA
FPGA-Based Parallel Comparison of Run-Length-Encoded Strings
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach
An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding
System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework
An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation
Analysis of matrix multiplication on high density Virtex-7 FPGA
Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation
Soft errors in Flash-based FPGAs: Analysis methodologies and first results
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration
Automation Framework for Large-Scale Regular Expression Matching on FPGA
Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization
A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA
UniGuard: A Unified Hardware-oriented Threat Detector for FPGA-based AI Accelerators
A Virtual Hardware Operating System for the Xilinx XC6200
Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture
Variable-latency signed addition on FPGAs
An FPGA based verification platform for HyperTransport 3.x
Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs
FPGA implementation of real-time digital controllers using on-line arithmetic
Reconfigurable Router Modules Using Network Protocol Wrappers
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems
An FPGA Solver for WSAT Algorithms
High Frequency Trading Acceleration Using FPGAs
A packet classifier using LUT cascades based on EVMDDS (k)
FPGAs for trusted cloud computing
The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams
A Power Estimation Model for an FPGA-based Softcore Processor
High Bandwidth Memory on FPGAs: A Data Analytics Perspective
Beyond the Limits: SHA-3 in Just 49 Slices
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs
A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture
ASIC Design and FPGA Design: A Unified Design Methodology Applied to Different Technologies
A Reconfigurable Processor Architecture
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors
A Self-Reconfiguration Framework for Multiprocessor CSoPCs
NOC architecture design for multi-cluster chips
A Transmutable Telecom System
DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model
Fault Modeling and Test Generation for FPGAs
FPGA Implementation of a GF(2 4M ) Multiplier for use in Pairing Based Cryptosystems
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip
A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs
FPGA implementation of a flexible decoder for long LDPC codes
FPGA Vendor Agnostic True Random Number Generator
AES Implementation on FPGA: Time - Flexibility Tradeoff
DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators
Accelerating solvers for global atmospheric equations through mixed-precision data flow engine
A Wildcarding Mechanism for Acceleration of Partial Configurations
An FPGA Prototype for a Multiplierless FIR Filter Built Using the Logarithmic Number System
Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures
Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications
FPGA Processor for Real-Time Optical Flow Computation
Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments
Secure Logic Synthesis
A Prolog-Based Hardware Development Environment
In-switch approximate processing: Delayed tasks management for MapReduce applications
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
A Benign Hardware Trojan on FPGA-based embedded systems
Lightweight Secure Processor Prototype on FPGA
Real-Time Waveform Matching with a Digitizer at 10 GS/s
Sea Cucumber: A Synthesizing Compiler for FPGAs
Accelerating Boolean Implications with FPGAs
Remote FPGA design through eDiViDe - European Digital Virtual Design Lab
A digital architecture for real-time nonuniformity correction of infrared focal-plane arrays
Test Compression for Dynamically Reconfigurable Processors
A Reconfigurable Engine for Real-Time Video Processing
Communication Costs Driven Design Space Exploration for Reconfigurable Architectures
Liquid: Fast placement prototyping through steepest gradient descent movement