yusuke1997/dblp-id-title huggingface dataset:
A fast process variation and pattern fidelity aware mask optimization algorithm
Parallel multi-level analytical global placement on graphics processing units
A fast algorithm for VLSI net extraction
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs
A comprehensive fault macromodel for opamps
Using test data to improve IC quality and yield
ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
Multi-level cell STT-RAM: Is it realistic or just a dream?
Voltage binning under process variation
Logic simulation on vector processors
Post-silicon bug diagnosis with inconsistent executions
An efficient method for parametric yield optimization of MOS integrated circuits
Control generation for embedded systems based on composition of modal processes
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks
Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for boolean encoding of cardinality
IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA
NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory
Design and optimization of LC oscillators
Evaluation and Synthesis of Self-Monitoring State Machines
Path toward future CAD environments for MEMS (tutorial abstract)
Lower Voltage for Higher Security: Using Voltage Overscaling to Secure Deep Neural Networks
High-performance gate sizing with a signoff timer
Design automation for analog: the next generation of tool challenges
CRISP: Congestion reduction by iterated spreading during placement
Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded Hardware
In-place decomposition for robustness in FPGA
Efficient Boolean function matching
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
A geometric approach for early power grid verification using current constraints
ToMamba: Towards Token-Efficient Mamba Architecture on FPGA
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions
TonyChopper: a desynchronization package
Data path optimisation and delay matching for asynchronous bundled-data balsa circuits
Hercules: Hardware accElerator foR stoChastic schedULing in hEterogeneous Systems
VLSI timing simulation with selective dynamic regionization
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
Formal Methods for Dynamic Power Management
Reconfigurable in-memory computing with resistive memory crossbar
System Level Design and Verification Using a Synchronous Language
Attractor-repeller approach for global placement
System software techniques for low-power operation in wireless sensor networks
Subthreshold leakage modeling and reduction techniques
On the decreasing significance of large standard cells in technology mapping
Strengthening PUFs using Composition
Address generation for memories containing multiple arrays
Re-LSM: A ReRAM-Based Processing-in-Memory Framework for LSM-Based Key-Value Store
Memory binding for performance optimization of control-flow intensive behaviors
ICCAD-2017 CAD contest in net open location finder with obstacles: Invited paper
Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement
Making split-fabrication more secure
Copy detection for intellectual property protection of VLSI designs
A scalable substrate noise coupling model for mixed-signal ICs
Sensorless estimation of global device-parameters based on F max testing
A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis
Overlapping-aware throughput-driven stencil planning for E-beam lithography
Routability-Driven Orientation-Aware Analytical Placement for System in Package
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
TReCiM: Lower Power and Temperature-Resilient Multibit 2FeFET-1T Compute-in-Memory Design
Analog placement with symmetry and other placement constraints
A new algorithm for CMOS gate matrix layout
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Interconnect-aware device targeting from PPA perspective
A lower bound computation method for evaluation of statistical design techniques
RTL SAT simplification by Boolean and interval arithmetic reasoning
Verification by approximate forward and backward reachability
Know the Unknowns: Addressing Disturbances and Uncertainties in Autonomous Systems : Invited Paper
Twill: Scheduling Compound AI Systems on Heterogeneous Mobile Edge Platforms
PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation
Conflict driven techniques for improving deterministic test pattern generation
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance
Virtual persistent cache: Remedy the long latency behavior of host-aware shingled magnetic recording drives
Representation of process mode correlation for scheduling
SMT( CLU ): a step toward scalability in system verification
A metal and via maskset programmable VLSI design methodology using PLAs
Wireplanning in logic synthesis
The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013
Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices
HAPIC: A Scalable, Lightweight and Reactive Cache for Persistent-Memory-Based Index
A power aware system level interconnect design methodology for latency-insensitive systems
Combined loop transformation and hierarchy allocation for data reuse optimization
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Efficient harmonic balance simulation using multi-level frequency decomposition
Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-Service
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects
Transistor technologies and pixel circuit design for efficient active-matrix organic light-emitting diode displays
SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator
RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization
Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems
Methods for true power minimization
AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPU
Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits
ECC Cache: A Lightweight Error Detection for Phase-Change Memory Stuck-At Faults
Design of large area electronics with organic transistors
Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architectures
1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers
Efficient and accurate eye diagram prediction for high speed signaling
Stratified random sampling for power estimation
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Algorithmic tuning of clock trees and derived non-tree structures
Hybrid decision diagrams
Exploration and Exploitation of Hidden PMU Events
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Optimal wire sizing and buffer insertion for low power and a generalized delay model
Local Search for Final Placement in VLSI Design
OpenRAM: an open-source memory compiler
Utilizing random noise in cryptography: Where is the Tofu?
Debugging sequential circuits using Boolean satisfiability
GPU Overdrive Fault Attacks on Neural Networks
Customized locking of IP blocks on a multi-million-gate SoC
A Global Optimization Approach for Architectural Synthesis
An automated technique for topology and route generation of application specific on-chip interconnection networks
Shaping a VLSI wire to minimize delay using transmission line model
Escape routing for staggered-pin-array PCBs
DaS: Implementing Dense Ising Machines Using Sparse Resistive Networks
A hierarchical modeling framework for on-chip communication architectures
Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing
Boolean matching for full-custom ECL gates
ThermoPhoton: Fast 3D Thermal Simulation of Photonic Integrated Circuits via Operator Learning
$\mathcal{P}\text{ARseL}$: Towards a Verified Root-of-Trust Over seL4
DeepFense: online accelerated defense against adversarial deep learning
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification
A Convex Programming Approach to Positive Real Rational Approximation
Exploiting randomness in sketching for efficient hardware implementation of machine learning applications
Graph Learning-Based Arithmetic Block Identification
Overview of 2021 CAD Contest at ICCAD
Computer-aided design for quantum computation
K-PACT: Kernel Planning for Adaptive Context Switching - A Framework for Clustering, Placement, and Prefetching in Spectrum Sensing
Pin assignment with global routing
Augmented Co-Simulation for Fast Functional and System-Level Verification of HLS Accelerators
Decomposing image computation for symbolic reachability analysis using control flow information
Fast Overlapped Scattered Array Storage Schemes for Sparse Matrices
Retarded Models for PC Board Interconnects - Or How the Speed of Light Affects your SPICE Circuit Simulation
Online and incremental machine learning approaches for IC yield improvement
RRAM-based reconfigurable in-memory computing architecture with hybrid routing
FLUTE: fast lookup table based wirelength estimation technique
Exploiting off-chip memory access modes in high-level synthesis
Functional debugging of systems-on-chip
The Chebyshev expansion based passive model for distributed interconnect networks
Circuit power estimation using pattern recognition techniques
Parallel multi-delay simulation
Application-aware deadlock-free oblivious routing based on extended turn-model
FPGA device and architecture evaluation considering process variations
Augmented partial reset
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks
A test synthesis technique using redundant register transfers
Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management
HidFix: Efficient Mitigation of Cache-Based Spectre Attacks Through Hidden Rollbacks
Test generation for primitive path delay faults in combinational circuits
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks
Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method
HyperTune: Dynamic Hyperparameter Tuning for Efficient Distribution of DNN Training Over Heterogeneous Systems
Code restructuring for improving cache performance of MPSoCs
SAT and ATPG: Boolean engines for formal hardware verification
ICCAD-2020 CAD contest in Routing with Cell Movement : Invited Talk
Template-mask design methodology for double patterning technology
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs
MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs
Online human activity recognition using low-power wearable devices
Security trends and advances in manufacturing systems in the era of industry 4.0
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines
Optimal statistical chip disposition
Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
MIST: An Algorithm for Memory Miss Traffic Management
Clock tree synthesis for multi-chip modules
Enforcing hard constraints in physics-informed learning for transient TSV electromigration analysis
Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators
Clustering based pruning for statistical criticality computation under process variations
Area-time model for synthesis of non-pipelined designs
Mobile devices user - The subscriber and also the publisher of real-time OLED display power management plan
Mathematical Models and Control Algorithms for Dynamic Optimization of Multicore Platforms: A Complex Dynamics Approach
Free space management for cut-based placement
Simultaneous layout migration and decomposition for double patterning technology
Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics
CMOS inverter delay and other formulas using alpha -power law MOS model
Efficient computation of current flow in signal wires for reliability analysis
Performance-driven analog placement considering monotonic current paths
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML
On the design of robust multiple fault testable CMOS combinational logic circuits
DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence Workloads
Edge segmentation: Empowering mobile telemedicine with compressed cellular neural networks
Race analysis for SystemC using model checking
Thermal simulation techniques for nanoscale transistors
Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding
Threshold Logic Synthesis Based on Cut Pruning
SPARTA: Spike-Aware Token Skipping Co-Optimization with Heterogeneous ReRAM-CIM Architecture for Spiking Transformer Acceleration
Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic
Perception-Aware Power Management for Mobile Games via Dynamic Resolution Scaling
System-level impact of chip-level failure mechanisms and screens
An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems
ProtoCellLayout: Prototype-Guided Graph Learning for Accurate and Generalizable Standard Cell Layout PPA Estimation
A synthesis flow for digital signal processing with biomolecular reactions
Scheduling and binding bounds for RT-level symbolic execution
Design and CAD Challenges in sub-90nm CMOS Technologies
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os
Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper)
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization
Clock period constrained minimal buffer insertion in clock trees
Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems
State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results
Adjustment-based modeling for statistical static timing analysis with high dimension of variability
Rapid prototyping of microprocessor-based systems
A Complete Modeling Methodology for Full-chip Parasitic Extraction
SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture
From single core to multi-core: preparing for a new exponential
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Routing-Free Crosstalk Prediction
Near-term industrial perspective of analog CAD
Aesthetic routing for transistor schematics
Performance boosting under reliability and power constraints
Mapping model with inter-array memory sharing for multidimensional signal processing
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper)
Efficient time-domain simulation of frequency-dependent elements
A general framework for vertex orderings, with applications to netlist clustering
On the difference between two widely publicized methods for analyzing oscillator phase behavior
Toward safe interoperations in network connected medical cyber-physical systems using open-loop safe protocols
Module locking in biochemical synthesis
The formal verification of a pipelined double-precision IEEE floating-point multiplier
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation
Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime Configurability
A generalized state assignment theory for transformation on signal transition graphs
Robust optimization based backtrace method for analog circuits
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
A User-Centric CPU-GPU Governing Framework for 3D Games on Mobile Devices
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages
On Determining Scan Flip-Flops in Partial-Scan Designs
H3D-LLM: Heterogeneous 3D Chiplet Design for LLM Inference with Dynamic Task Scheduling and Memory-Aware Orchestration
A non-volatile memory based physically unclonable function without helper data
Security-aware mapping for CAN-based real-time distributed automotive systems
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
Split Compilation for Security of Quantum Circuits
Piecewise linear models for Rsim
TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips
QuickFlow: An Efficient Local Search Method to Map Convolutions on Spatial Architectures
Efficient process-hotspot detection using range pattern matching
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper
Efficient verification of determinate speed-independent circuits
CRACKER: a general area router based on stepwise reshaping
Runtime integrity checking for inter-object connections
Schedulability analysis of multiprocessor real-time applications with stochastic task execution times
Differentiable Timing-Driven FPGA Placement with Smooth Optimization and ML-Based Delay Calibration
Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node
Formal approaches to design of active cell balancing architectures in battery management systems
Efficient High-Fidelity Two-Dimensional Warpage Modeling for Advanced Packaging Analysis
PATHE: A Privacy-Preserving Database Pattern Search Platform with Homomorphic Encryption
DecoRTL: A Run-Time Decoding Framework for RTL Code Generation with LLMs
Channel routing order for building-block layout with rectilinear modules
Lazy man's logic synthesis
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction
Countering Variations and Thermal Effects for Accurate Optical Neural Networks
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework
Fast timing closure by interconnect criticality driven delay relaxation
Floorplan design for multi-million gate FPGAs
KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics
Hotspot Detection via Multi-task Learning and Transformer Encoder
No Redundancy, No Stall: Lightweight Streaming 3D Gaussian Splatting for Real-time Rendering
A unified framework for statistical timing analysis with coupling and multiple input switching
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Accuracy-Preserving Reduction of Sparsified Reduced Power Grids with A Multilevel Node Aggregation Scheme
Temporal floorplanning using the T-tree formulation
Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms
Solution of Parallel Language Equations for Logic Synthesis
Current estimation in MOS IC logic circuits
Triple patterning aware detailed placement with constrained pattern assignment
Invited Paper: LLM4HWDesign Contest: Constructing a Comprehensive Dataset for LLM-Assisted Hardware Code Generation with Community Efforts
Inferring assertion for complementary synthesis
Efficient manipulation algorithms for linearly transformed BDDs
TKtimer: fast & accurate clock network pessimism removal
Resilient circuits - Enabling energy-efficient performance and reliability
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
Machine learning for performance and power modeling of heterogeneous systems
A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping
ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures
Accelerating Electro-Thermal Co-Analysis via Coarse-to-Fine Physics-Informed Neural Networks
HW/SW co-design of parallel systems
Lazy transition systems: application to timing optimization of asynchronous circuits
Fast performance evaluation of fixed-point systems with un-smooth operators
Advancing supercomputer performance through interconnection topology synthesis
Implication graph based domino logic synthesis
Holistic Power Side-Channel Leakage Assessment: Towards a Robust Multidimensional Metric
TETRIS: On-Device Trainable Energy-Efficient FPGA Accelerator for Trustworthy and Real-Time Instance Segmentation
Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Symbolic functional and timing verification of transistor-level circuits
Power scheduling with active power grids
Rectification method for lookup-table type FPGA's
Construction of rectilinear Steiner minimum trees with slew constraints over obstacles
IEEE/ACM International Conference On Computer Aided Design, ICCAD 2025, Munich, Germany, October 26-30, 2025
Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout
Thermal via planning for 3-D ICs
Parallel logic and fault simulation algorithms for shared memory vector machines
TinySPICE plus: scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniques
A nonlinear cell macromodel for digital applications
A study of Through-Silicon-Via impact on the 3D stacked IC layout
GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks
Prompt, Fab, Flex: Agentic LLMs for Flexible Electronics Design
A new algorithm for standard cell global routing
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications
NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources