yusuke1997/dblp-id-title huggingface dataset:
A comparator energy model considering shallow trench isolation stress by geometric programming
Formal verification of safety of polymorphic heterogeneous multi-core architectures
Cell Swapping Based Migration Methodology for Analog and Custom Layouts
Synthesis and formal verification of on-chip protocol transducers through decomposed specification
Highest Wireless Power: Inductively Coupled Or RF?
Yield-constrained digital circuit sizing via sequential geometric programming
HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD
A scan shifting method based on clock gating of multiple groups for low power scan testing
BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit
Exploiting static and dynamic locality of timing errors in robust L1 cache design
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology
Impact of Low-K on Crosstalk
Power/Ground Integrity Issues for Sub-130nm IC Designs (Tutorial Abstract)
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models
Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM
Clock buffer polarity assignment considering the effect of delay variations
Investigation on Realistic Stuck-on/off Defects to Complement IEEE P2427 Draft Standard
Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs
Concolic testing of SystemC designs
A Bit-Parallel Deterministic Stochastic Multiplier
Optimizing power and throughput for m-out-of-n encoded asynchronous circuits
An innovative method to automate the waiver of IP-level DRC violations
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction
Asynchronous Circuits: An Increasingly Practical Design Solution (invited)
A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array
CMOS diodes operating beyond avalanche frequency
Hybrid Learning for Orchestrating Deep Learning Inference in Multi-user Edge-cloud Networks
An Automatic and Efficient BERT Pruning for Edge AI Systems
Topology optimization of a passive thermal actuator
A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule
On predicting NBTI-induced circuit aging by isolating leakage change
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method
Yield in flash memory: Methodology, modeling and design issues
SRAM Local Bit Line Access Failure Analyses
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit
A SPICE-based Emulator Framework for Quantum Error Correction Circuits using LC Resonators
Redundant Via Insertion in Restricted Topology Layouts
Statistical static performance analysis of asynchronous circuits considering process variation
A systematic approach to modeling and analysis of transient faults in logic circuits
Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode
Behavioral Modeling of Tunable I/O Drivers with Pre-emphasis Using Neural Networks
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection
New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm
Wearout-aware compiler-directed register assignment for embedded systems
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS
A low overhead fault tolerant routing scheme for 3D Networks-on-Chip
Leveraging DDR5 RCDs for High-Speed DDR5 Protocol Analysis: A Novel Approach to RDIMM Testing
Reducing the Complexity of VLSI Performance Variation Modeling Via Parameter Dimension Reduction
International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013
Project Management for System-on-Chip Using Multi-Chip Modules
Fast and Accurate Library Generation Leveraging Deep Learning for OCV Modelling
Methodology for analysis of TSV stress induced transistor variation and circuit performance
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization
Dot-product engine as computing memory to accelerate machine learning algorithms
Temperature effects on energy optimization in sub-threshold circuit design
CMOS Based Low Cost Temperature Sensor
Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs
Leveraging Generative AI for Platform Hardware Design Automation - Learnings and Recommendations
A Lightweight Error-Resiliency Mechanism for Deep Neural Networks
Fixed outline multi-bend bus driven floorplanning
Testing of Analogue Circuits via (Standard) Digital Gates
Timing-Aware Multiple-Delay-Fault Diagnosis
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application
ISQED 2010 fellow award recipient
Two-Dimensional Layout Migration by Soft Constraint Satisfaction
Leakage Increase of Narrow and Short BCPMOS
Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits
Small Memory Footprint Neural Network Accelerators
Hot carrier effects on CMOS phase-locked loop frequency synthesizers
Weighted Vertex Cover Using Disjoint Set Data Structures for the Memory Reconfiguration Problem
Signal Selection Heuristics for Post-Silicon Validation
Implementation of power managed hyper transport system for transmission of HD video
Polymorphic Sensor to Detect Laser Logic State Imaging Attack
Accelerating physical level sub-component power simulation by online power partitioning
Partial Selective Encryption: An Improved System for Protecting VLSI Design Data in the OASIS format
Post Silicon Power/Performance Optimization in the Presence of ProcessVariations Using Individual Well Adaptive Body Biasing (IWABB)
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs
A novel approach to IC, package and board co-optimization
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis
Test set identification for improved delay defect coverage in the presence of statistical delays
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology
Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes
A Variable Reduction Technique for the Analysis of Ultra Large-Scale Power Distribution Networks
Design for Quality and Manufacturing
An Integrated Tool for Analog Test Generation and Fault Simulation
Graph Neural Network-Based Detailed Placement Optimization Framework
Hardware-aware 3D Model Workload Selection and Characterization for Graphics and ML Applications
Efficient Multiphase Test Set Embedding for Scan-based Testing
Data interface buffer compensation scheme for fast calibration
Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1
Energy-Aware DNN Task Scheduling with Dynamic Batching and Frequency Adjustment
Designing and Validating Process-Variation-Aware Cell Libraries
Evening Panel Discussion: Process Variation: Is It Too Much to Handle?
Modeling and analyzing NBTI in the presence of Process Variation
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices
Function Approximation Using Analog Building Blocks in Flexible Electronics
Energy-Efficient Edge Detection using Approximate Ramanujan Sums
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits
Quality of SoC Designs through Quality of the Design Flow: Status and Needs
Routing Intent Aware Pin Access Point Selection for Standard Cell Designs
Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure
Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts
Device and circuit implications of double-patterning - A designer's perspective
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis
Self-timed Sensors for Detecting Static Optical Side Channel Attacks
Delay and power optimization with TSV-aware 3D floorplanning
The Role of ICs in the Creation of a Connected World and the Importance of Product Quality
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques
Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits
Quality of a Bit (QoB): A New Concept in Dependable SRAM
MReC: A Multilayer Photonic Reservoir Computing Architecture
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model
Density Aware Cell Library Design for Design-Technology Co-Optimization
Efficient analog circuit optimization using sparse regression and error margining
A multilevel multilayer partitioning algorithm for three dimensional integrated circuits
Statistical yield analysis of silicon-on-insulator embedded DRAM
Terahertz travelling wave amplifier design using Ballistic Deflection Transistor
Portable biosensor for chronic malaria detection
Mining Message Flows from System-on-Chip Execution Traces
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
EFSM Manipulation to Increase High-Level ATPG Effectiveness
An Approach for a Comprehensive QA Methodology for the PDKs
A 0.2nJ/sample 0.01mm 2 ring oscillator based temperature sensor for on-chip thermal management
High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC
MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis
Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient Applications
Noise Analysis for 0.13um and Beyond
TDTB error detecting latches: Timing violation sensitivity analysis and optimization
Wire delay variability in nanoscale technology and its impact on physical design
On lithography aware metal-fill insertion
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique
A deep learning based approach for analog hardware implementation of delayed feedback reservoir computing system
Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches
Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications
Evaluation of Collapsing Methods for Fault Diagnosis
RF passive device modeling and characterization in 65nm CMOS technology
Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling
Reliability - A highly important product attribute for the world's poorest consumers
Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC
i-lete: An IoT-based physical stress monitoring framework for athletes
AGRAS: Aging and memory request rate aware scheduler for PCM memories
Protection of Muller-Pipelines from transient faults
A fully pipelined implementation of Monte Carlo based SSTA on FPGAs
Noise in Radio Frequency Circuits: Analysis and Design Implications
An analytical approach to efficient circuit variability analysis in scaled CMOS design
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement
Recognition of regular layout structures
Hot Carrier Reliability and Design Considerations (Tutorial Abstract)
Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting
Early Detection of Design Sensitivities that Cause Yield Loss for New Products
SeqL: Secure Scan-Locking for IP Protection
On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network
ACLA: An Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
Design, Integration and Validation of Heterogeneous Systems
Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques
A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects
Novel adaptive power gating strategy of TSV-based multi-layer 3D IC
Impact of interconnect variability on circuit performance in advanced technology nodes
Learning Client Selection Strategy for Federated Learning across Heterogeneous Mobile Devices
EM Fault Injection on ARM and RISC-V
Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop
Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
An extended-range incremental CT ∑Δ ADC with optimized digital filter
An efficient timing analysis model for 6T FinFET SRAM using current-based method
Efficient reduction techniques for statistical model generation of standard cells
Toward effective utilization of timing exceptions in design optimization
Architecture design exploration of three-dimensional (3D) integrated DRAM
Moving Towards Game-Changing Technology: Fabrication and Application of HfO2 RRAM for In-Memory Computing
Configurable redundant via-aware standard cell design considering multi-via mechanism
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design
26th International Symposium on Quality Electronic Design, ISQED 2025, San Francisco, CA, USA, April 23-25, 2025
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design
A Comprehensive Approach to Characterizing $V_{T}$ Miscorrelation Derates for Physical Design and Timing Signoff
DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM
Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts
Delay optimization considering power saving in dynamic CMOS circuits
Dynamic Reconfiguration of CNNs for Input-Dependent Approximation
50GB/s signaling on organic substrates using PMTL technology
Hybrid CMOS-TFET based register files for energy-efficient GPGPUs
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation
Solving the SoC Test Scheduling Problem Using Network Flow and Reconfigurable Wrappers
Error Diluted Approximate Multipliers Using Positive And Negative Compressors
Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy
Accurate multi-specification DPPM estimation using layered sampling based simulation
New SRAM design using body bias technique for ultra low power applications
An Audio Frequency Unfolding Framework for Ultra-Low Sampling Rate Sensors
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs
Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
A framework for MPSoC generation and distributed applications evaluation
Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model
Instruction cache aging mitigation through Instruction Set Encoding
On Chip Jitter Measurement through a High Accuracy TDC
3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores
Quality Challenges of the Nanometer Design Realm
On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks
System-level process variability compensation on memory organizations of dynamic applications: a case study
Post-Route Gate Sizing for Crosstalk Noise Reduction
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems
Adaptive HCI-aware power gating structure
Modeling and verification of industrial flash memories
Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs
Online Training from Streaming Data with Concept Drift on FPGAs
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs
Deep Submicron USLI Design Paradigm: Who is Writing the Future?
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing
Foundry's Perspective of System Integration: Quality Design and Time-to-Volume
Automated Assertion Checker Generator and Information Flow Tracking for Security Verification
Standby power reduction and SRAM cell optimization for 65nm technology
Test Generation and Fault Modeling for Stress Testing (invited)
Design of an incoherent IR-UWB receiver front-end in 180-nm CMOS technology
A Survey on Neural Trojans
Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detection
IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design
Global Multi-voltage Interface Unit for Diverse Digital Logic
Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography
Exploiting abstraction, learning from random simulation, and SVM classification for efficient dynamic prediction of software health problems
Advancing Customer-Perceived Quality in the EDA Industry
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
A New Method for Design of Robust Digital Circuits
On-chip transistor characterization arrays with digital interfaces for variability characterization
Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA
Knowledge Distillation between DNN and SNN for Intelligent Sensing Systems on Loihi Chip
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
Low cost and power CNN/deep learning solution for automated driving
Power-Performance Yield optimization for MPSoCs using MILP
Robust differential asynchronous nanoelectronic circuits
Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning
Recovery of faulty TSVs in 3D ICs
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology
Process Window and Device Variations Evaluation using Array-Based Characterization Circuits
5nm: Has the time for a device change come?
Adaptive tracking channel control for GNSS receivers under renewable energy
Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer
Reliable memory PUF design for low-power applications
Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates
Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework
Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage
High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA
A software pipelining algorithm in high-level synthesis for FPGA architectures
A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAs
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology
Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing
DFM Based Detailed Routing Algorithm for ECP and CMP
A True Random Number Generator for Probabilistic Computing using Stochastic Magnetic Actuated Random Transducer Devices
An ILP Formulation for Reliability-Oriented High-Level Synthesis
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs
Verification of Embedded Phase-Locked Loops
Chosen-input side-channel analysis on unrolled light-weight cryptographic hardware
24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023
Design Considerations for Low-Power Ultra Wideband Receivers
3DICE: 3D IC cost evaluation based on fast tier number estimation
Comparative analysis and study of metastability on high-performance flip-flops
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature
A revisit to the primal-dual based clock skew scheduling algorithm
Low-Cost and Real-Time Super-Resolution over a Video Encoder IP
Predictive synchronization for DVFS-enabled multi-processor systems
A Basis for Formal Robustness Checking
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access
Limits of bias based assist methods in nano-scale 6T SRAM
Quality Driven Manufacturing and SOC Designs
Methodology to ensure circuit robustness and exceptional silicon quality while proliferating designs across process revisions with high productivity
Variability- and correlation-aware logical effort for near-threshold circuit design
Performance-energy tradeoffs in reliable NoCs
Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices
Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?
A framework for logic-aware layout analysis
Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm
DAPP: Delay Aware Power Prediction
Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric
Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis
Proactive management of X's in scan chains for compression
Mixed non-rectangular block packing for non-Manhattan layout architectures
X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach
Easy-to-build Arbiter Physical Unclonable Function with enhanced challenge/response set
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process
Process variation aware D-Flip-Flop design using regression analysis
A Hardware and Software Monitor for High-Level System-on-Chip Verification
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
A sensitivity-aware methodology to improve cell layouts for DFM guidelines
Adaptive power gating for function units in a microprocessor
Why Nano Technology? Why Now? And What Might Its Impact on Electronics
Future Prediction of Self-Heating in Short Intra-Block Wires
Ramping New IC Products in the Deep Submicron Age
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations
Lightweight Neural Network Architectures for Resource-Limited Devices
Rapid heterogeneous prototyping from Simulink
A Reconfigurable Low-Power High-Performance Matrix Multiplier Design
On the selection of adder unit in energy efficient vector processing
Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems