yusuke1997/dblp-id-title huggingface dataset:
Innovative Charging Solutions for Li-Ion Batteries in UPS Systems: A Microcontroller-Based Design
On the Representation of Mappings to Multicores
Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array
Evaluation of Memory Optimization in a Large-Scale Structural Finite Element Pre-processor
Enhancing Pega Robotics Process Automation with Machine Learning: A Novel Integration for Optimized Performance
A Network Simulator for the Estimation of Bandwidth Load and Latency Created by Heterogeneous Spiking Neural Networks on Neuromorphic Computing Communication Networks
17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024, Kuala Lumpur, Malaysia, December 16-19, 2024
A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization
Multiport Register File Design for High-Performance Embedded Cores
Combining Decision Tree and Convolutional Neural Network for Energy Efficient On-Device Activity Recognition
Power Management Controller for Online Power Saving in Network-on-Chips
GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation
Enhancing Anonymity in NoC Communication to Counter Traffic Profiling by Hardware Trojans
15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model
14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2021, Singapore, Singapore, December 20-23, 2021
Accelerating Graph-Based SLAM through Data Parallelism and Mixed Precision on FPGAs
Recognition of CAPTCHAs Utilizing The Middle Part of The Convolutional Feature Map
EnsembleSTDP: Distributed in-situ Spike Timing Dependent Plasticity Learning in Spiking Neural Networks
A Code Selection Mechanism Using Deep Learning
UI Method to Support Knowledge Creation in Hybrid Museum Experience
Performance of precision auto-tuned neural networks
Performance Comparision of TPU, GPU, CPU on Google Colaboratory Over Distributed Deep Learning
A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator
High-Performance Asynchronous CNN Accelerator with Early Termination
Approximated Triple Modular Redundancy of Convolutional Neural Networks Based on Residual Quantization
An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem
Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems
Reentrancy Vulnerability Detection Based on Graph Convolutional Networks and Expert Patterns
Unifying Wire and Time Scheduling for Highlevel Synthesis
A Study on Number Theoretic Transform Acceleration on AMD AI Engine
An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA Systems
VLC-UNIT: Unsupervised Image-to-Image Translation with Vision-Language Classification
A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings
Making Software Based on Human-Driven Design Case Study: SQL for non-experts
Performance Evaluation of Tsunami Simulation Using OpenCL on GPU and FPGA
Improved Decimal Rounding Module based on Compound Adder
A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology
Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUF
Efficient Service Discovery Using Social Service Network Based on Big Data Infrastructure
Real-Time Implementation of Time-Space Continuous Dynamic Programming for Air-Drawn Character Recognition Using GPUs
Road Surface Extraction and Object Elimination for Autonomous Driving Simulators Based on Neural Radiance Field
A Quantum Q-Learning Model for the Capacitated Vehicle Routing Problem
Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control
Evaluation of Recursive Feature Elimination and LASSO Regularization-based optimized feature selection approaches for cervical cancer prediction
Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems
Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor
Implementation of Physics Informed Neural Networks on Edge Device
SAMNoC: A Novel Optical Network-on-Chip for Energy-Efficient Memory Access
A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs
Cluster Based Smart Random Walk for Data Aggregation in Wireless Sensor Network
Enhancement of Incremental Performance Parameter Estimation on ppOpen-AT
NoC Based Virtualized Accelerators for Cloud Computing
Model-Based Platform Composition for Embedded System Design
Convolutional Neural Network for Classification of Source Codes
Programming Models and Methods for Heterogeneous Parallel Embedded Systems
Incremental Training of SVM-Based Human Detector
Theoretical Analysis of the Memory-Efficient Matrix Storage Method for Quantum Emulation Accelerators with Gate Fusion on FPGAs
Cloud-Based Service for eBooks Using EPUB under the Aspect of Learning Analytics
Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar Array
SSG-AT: An Auto-tuning Method of Sparse Matrix-vector Multiplicataion for Semi-structured Grids - An Adaptation to OpenFOAM
MLDPBS: A Machine Learning based Dynamic Partitioning Buddy System for Efficient Memory Allocation in Embedded Systems
Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor
Emerging Frontiers and Limitations of Logic Locking for Secure IC Design
FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT
Key Frame Extraction from Video Based on Determinant-Type of Sparse Measure and DC Programming
Optimization Strategies for Thermal Management in Electric Drivetrains: Enhancing Performance and Longevity
Transputer-like Multicore Digital Signal Processing on the Array of ARM Cortex-M0 Microprocessors
Dynamic Ring-Based Multicast with Wavelength Reuse for Optical Network on Chips
Accurate Coverage of Complex Targets in Three-Dimensional Mobile Sensor Networks
Analyzable Publish-Subcribe Communication Through a Wait-Free FIFO Channel for MPSoC Real-Time Applications
Network on Chip and Parallel Computing in Embedded Systems
Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming
Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels
Integration of AI in Smart Electric Drivetrains
An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing
A Thermal Management System for Building Block Computing Systems
A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system
A CGRA-Based Approach for Accelerating Convolutional Neural Networks
Quantum-Secure Data Transmission in Smart Grid
Classifying Performance Bottlenecks in Multi-threaded Applications
AI-Driven Novel Approach for Enhancing E-Commerce Accessibility through Sign Language Integration in Web and Mobile Applications
Taxonomy of Proactive Detection Methods of Drunk Driving for Enhancing Traffic Safety
Real-Time Attitude Estimation of Sigma-Point Kalman Filter via Matrix Operation Accelerator
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations
Abstracting Parallel Programming and Its Analysis Towards Framework Independent Development
Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor
Automatic endometrial segmentation in ultrasound images using deep learning
Early Stage Chick Embryonic Heart Outflow Tract Flow Measurement Using High Speed 4D Optical Coherence Tomography
Two-level Routerless Network-on-Chip
Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits
Hardware Attack Models in Tiled Chip Multi-Core Processors: A Survey
Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications
A 94.5% Peak Efficiency, 14mV Output Ripple SC-Buck Step-Up Converter with 1.2-to-5V Output Achieving 20.2% Enhanced Power Efficiency in New PMU Architecture for SoCs
A Robust Methodology for Performance Analysis on Hybrid Embedded Multicore Architectures
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing
Open-AI Driven Open-source Open-access Sustainable ICs Design Flow
Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology
Selective Pruning of Sparsity-Supported Energy-Efficient Accelerator for Convolutional Neural Networks
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board
Design and Analysis of a Nano-photonic Processing Unit for Low-Latency Recurrent Neural Network Applications
Dynamic Service Recommendation Using Lightweight BERT-based Service Embedding in Edge Computing
Thermal Management in 3D Homogeneous NoC Systems Using Optimized Placement of Liquid Microchannels
Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits
An Acceleration for Any-Angle Routing Using Quasi-Newton Method on GPGPU
FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting
Convolutional Neural Networks Inference Accelerator Design using Selective Convolutional Layer
Using the Spring Physical Model to Extend a Cooperative Caching Protocol for Many-Core Processors
An Intelligent Water Quality Measurement Robot Remote-Controlled Via Wireless Communication
Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI
Auto-tuning of Computation Kernels from an FDM Code with ppOpen-AT
A cost/power efficient storage system with directly connected FPGA and SATA disks
An Architecture to Enable Machine-Learning-Based Task Migration for Multi-Core Real-Time Systems
Traffic-Aware Energy-Efficient Hybrid Input Buffer Design for On-Chip Routers
Online Image Sensor Fault Detection for Autonomous Vehicles
A Comparative Study of AI and Low-Code Platforms for SMEs: Insights into Microsoft Power Platform, Google AutoML and Amazon SageMaker
FPU Speedup Estimation for Task Placement Optimization on Asymmetric Multicore Designs
LUSH: Lightweight Framework for User-level Scheduling in Heterogeneous Multicores
Predictable Application Mapping for Manycore Real-Time and Cyber-Physical Systems
Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture
Design and research of self-balancing bicycle control system
A Cloud Based Super-Optimization Method to Parallelize the Sequential Code's Nested Loops
GPU Particle Swarm Optimization Applied to Travelling Salesman Problem
A Distance Estimation Method to Railway Crossing Using Warning Signs
A Novel Data Transfer Scheme of Smart Grid and DTN
Hardware characterization of Integer-Net based seizure detection models on FPGA
An FPGA Scalable Parallel Viterbi Decoder
Accelerated on-Chip Algorithm Based on Semantic Region-Based Partial Difference Detection for LiDAR-Vision Depth Data Transmission Reduction in Lightweight Controller Systems of Autonomous Vehicle
MSCU: Accelerating CNN Inference with Multiple Sizes of Compute Unit on FPGAs
A Buffered Flow Control Scheme with Flit Weight-Based Dropping Mechanism for Efficient Communication in NoC
Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG scheduling
Top-Down Profiling of Application Specific Many-core Neuromorphic Platforms
A survey of main dataflow MoCCs for CPS design and verification
Optimization of Numerous Small Dense-Matrix-Vector Multiplications in H-Matrix Arithmetic on GPU
High-Precision Performance Estimation of Dynamic Dataflow Programs
Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion
A Hybrid Opto-Electrical Floating-point Multiplier
Design and Performance Evaluation of a Manycore Processor for Large FPGA
Autotuning Power Consumption and Computation Accuracy using ppOpen-AT
Low-latency inter-domain communication on the Xen hypervisor
Code Generation of Graph-Based Vision Processing for Multiple CUDA Cores SoC Jetson TX
A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform
Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study
A Near-Memory Dynamically Programmable Many-Core Overlay
Adaptive Time-Based Least Memory Intensive Scheduling
Acceleration of Gravitation Field Analysis for Asteroids by GPU Computation
An Intelligent Plant Dissease Detection System for Smart Hydroponic Using Convolutional Neural Network
An open-source and GUI-capable RISC-V computer system on a low-end FPGA board
Buffer Allocation for Exposed Datapath Architectures
Simplified Quadcopter Simulation Model for Spike-Based Hardware PID Controller using SystemC-AMS
Algorithm to Interconvert SQL and Procedural Visual Queries
16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023
An Analysis Tool for a Programming Contest for High-School Students
Using scheduling entropy amplification in CUDA/OpenMP code to exhibit non-reproducibility issues
Design and Analysis of A Dual-Band Bistatic Backscatter Circuit for Passive RFID Tags
A Preliminary Evaluation of Building Block Computing Systems
A Scalable and Fast Microprocessor Design Space Exploration Methodology
Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster
On-chip Communication Buffer Architecture Optimization Considering Bus Width
A Multi-scale Binarized Neural Network Application Based on All Programmable System on Chip
A High-Throughput Network Intrusion Detection System Using On-Device Learning on FPGA
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System
Hypervisor-Induced Negative Interference in Virtualized Multi-core Platforms: The P4080 Case
Exploring Interference in Knowledge Transfer During the Acquisition of a New Programming Language by Novice Programmers
Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems
Hybrid Hardware-Software Architecture for Quantum Secure IoT Embedded Systems
PortBlocker: Detection and Mitigation of Hardware Trojan through Re-routing and Bypassing
Dynamic VC Organization for Efficient NoC Communication
A function-rich FPGA system of camera image processing for video meeting
Performance Evaluation of CMOS Annealing with Support Vector Machine
An Extended pipeline RISC-V CPU architecture
Scheduling DAGs of Multi-Version Multi-Phase Tasks on Heterogeneous Real-Time Systems
Performance Evaluation of CUDA Parallel Matrix Multiplication using Julia and C++
Design of a Nonvolatile-Neural-Network-Accelerator-Embedded Edge-IoT Device and Its Hardware Emulation
Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores
A Computational Model for Improving the Accuracy of Multi-criteria Recommender Systems
Low-Cost Congestion Detection Mechanism for Networks-on-Chip
Smart Ontology-Based Event Identification
Throttling Control for Bufferless Routing in On-chip Networks
A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-Time Scheduling
Parallel Longest Common Sequence Algorithm on Multicore Systems Using OpenACC, OpenMP and OpenMPI
Temporal Partitioning in Mixed-Criticality NoCs Using Timely Blocking
Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips
Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing
Unified Symbol Framework to Improve UI Comprehension
Hator: A High-Efficiency CGRA-Based 32/64-Bit Hashing Accelerator with Real-Time Performance Analysis
Efficient and Fault-tolerant Object Localization and Classification Based on an Ensemble of Dual Ternary YOLIC Models
Smart Cloud-based Implementation of a Learning Style Index
Design and implementation of vehicle oil online information monitoring system
Hardware Implementation of an Automatic Color Equalization Algorithm for Real-time Image Enhancement
A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code Generation
Enhancing Deep Reinforcement Learning with Compressed Sensing-based State Estimation
Prediction and Early Detection of Heart Disease: A Hybrid Neural Network and SVM Approach
Efficient Search-Space Encoding for System-Level Design Space Exploration of Embedded Systems
Efficient Hardware Architecture for Posit Addition/Subtraction
Heuristic Based Routing Algorithm for Network on Chip
Scalable Dynamic Task Scheduling on Adaptive Many-Core
EEG-based Positive-Negative Emotion Classification Using Machine Learning Techniques
Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures
Performance Optimization of SpMV Using CRS Format by Considering OpenMP Scheduling on CPUs and MIC
Overcoming Limited Data Challenges: Training Large-Scale Deduplication Models through Distributed and Non-Distributed Methods
Surface Type Classification for Autonomous Robots Using Temporal, Statistical and Spectral Feature Extraction and Selection
RELAX: a REconfigurabLe Approximate Network-on-Chip
Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPU
OCA - Code Advisory Tool for OpenMP Parallelization of Sequential Code
Hierarchical Library Based Power Estimator for Versatile FPGAs
Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs
Design of Knowledge Templates and Multi-View Symbols for Experiential Learning
High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture
Enhanced Long Edge First Routing Algorithm and Evaluation in Large-Scale Networks-on-Chip
Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo Module
Scheduling for Multi-core Processor under Process and Temperature Variation
Predictive Modeling for Thread Optimization in OpenMP-Based Parallelization Using Machine Learning
Portability of Vectorization-aware Performance Tuning Expertise across System Generations
Are Mobile Devices More Useful than Conventional Means as Tools for Learning Vocabulary?
Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags
Energy-Efficient Spiking Neural Networks Using Approximate Neuron Circuits and 3D Stacking Memory
Exploiting Model-Level Parallelism in Recurrent Neural Network Accelerators
Times Higher Education Rankings Analysis for Enhancing University Performance Using Multi-Criteria Decision Making
U-Net Hardware Accelerator
The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA
CLTune: A Generic Auto-Tuner for OpenCL Kernels
Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance
Radar and Camera Fusion for Object Forecasting in Driving Scenarios
Integrating Intra-and Intercellular Simulation of a 2D HL-1 Cardiac Model Based on Embedded GPUs
Multicore Power Estimation using Independent Component Analysis Based Modeling
Portable Multicore Resource Management for Applications with Performance Constraints
10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSOC 2016, Lyon, France, September 21-23, 2016
Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality Systems
Assessing the Role of Communication in Scalable Multi-Core Quantum Architectures
Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs
Introducing A-Cell for Scalable and Portable SIMD Programming
Adaptive Long-Term Reference Selection for Efficient Scalable Surveillance Video Coding
Distributed Neural Networks using TensorFlow over Multicore and Many-Core Systems
Designing Compact Convolutional Neural Network for Embedded Stereo Vision Systems
Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records
Network Intrusion Detection System Using Deep Learning Method with KDD Cup'99 Dataset
Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor System
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission
An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs
The ForeC Synchronous Deterministic Parallel Programming Language for Multicores
12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, September 12-14, 2018
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms
Run-Time Scalable NoC for FPGA Based Virtualized IPs
Toward EEG-Based Brain State Recognition for Personalized Neuromodulation
Accelerating Non-Negative Matrix Factorization on Embedded FPGA with Hybrid Logarithmic Dot-Product Approximation
Understanding the Performance Impact of Queue-Based Resource Allocation in Scalable Disaggregated Memory Systems
Comparative Study on Edge Detection Algorithms Using OpenACC and OpenMPI on Multicore Systems
SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis
Novel March WY Approach for Dynamic Fault Detection in Memory BIST
Integrated 3D Active Noise Cancellation Simulation and Synthesis Platform Using Tcl
Faster Method for Tuning the Tile Size for Tile Matrix Decomposition
Reliability Estimation of ML for Image Perception: A Lightweight Nonlinear Transformation Approach Based on Full Reference Image Quality Metrics
Self-Attention-based Sequential Plasma Evolution Simulator for EXL-50U Tokamak
NoobLab: An E-learning Platform for Teaching Programming
A Framework and Its User Interface to Learn Machine Learning Models
Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems
A Resource Allocation Method in Multi-access Edge Computing Environment Based on Deep Reinforcement Learning
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators
On the Design of Reliable Hybrid Wired-Wireless Network-on-Chip Architectures
Improving Memory Access Efficiency for Heterogeneous Multiprocessor Systems
Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures
An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs
Design of a Coarse-Grained Processing Element for Matrix Multiplication on FPGA
Measuring Predictability of Nvidia's GPU Schedulers: Application to the Summation Problem
Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks
Analysis of The Influence of Instagram Social Media Use on User's Consumptive Behavior
DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP
A Semi-Lossless Image Compression Procedure using a Lossless Mode of JPEG
An Auto-Tuning Technique of the Weighted Jacobi-Type Iteration Used for Preconditioners of Krylov Subspace Methods
RVCoreP-32IC: An optimized RISC- V soft processor supporting the compressed instructions
Distributed Decision Fusion for Large Scale IoT- Ecosystem
Enhanced KNN Method for Malicious URL Detection using GCL (Google Index, Counting the number of characters and Length of URL) Extraction Technique
13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019
Construction of Performance Model of Tile CAQR and Performance Result of the Implementation
Fault-Tolerant Ensemble CNNs Increasing Diversity Based on Knowledge Distillation