yusuke1997/dblp-id-title huggingface dataset:
On the feasibility of online malware detection with performance counters
Design Issues in the Development of a Modular Mutliprocessor Communications Network
Oaken: Fast and Efficient LLM Serving with Online-Offline Hybrid KV Cache Quantization
A control processor for a reconfigurable array computer
ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs
SmartOClock: Workload- and Risk-Aware Overclocking in the Cloud
Hardware/Software Tradeoffs in A Variable Word Width, Variable Queue Length Buffer Memory
Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching
DataScalar Architectures
Master of none acceleration: a comparison of accelerator architectures for analytical query processing
Fault-Secure Algorithms for Multiple-Processor Systems
MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Space-Time Algebra: A Model for Neocortical Computation
Architecture of a Hardware Data Interpreter
Raksha: a flexible information flow architecture for software security
Going vertical in memory management: Handling multiplicity by multi-policy
An Investigation of Static Versus Dynamic Scheduling
Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management
30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA
Performance Prediction Tools for Cedar: A Multiprocessor Supercomputer
Efficient Dynamic Scheduling Through Tag Elimination
DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference
Process Only Where You Look: Hardware and Algorithm Co-optimization for Efficient Gaze-Tracked Foveated Rendering in Virtual Reality
PreSET: Improving performance of phase change memories by exploiting asymmetry in write times
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits
Transient fault detection via simultaneous multithreading
Hardware support for WCET analysis of hard real-time multicore systems
A Functional Level Simulation Engine of MAN-YO: A Special Purpose Parallel Machine for Logic Design Automation
Retrospective: The Stanford FLASH Multiprocessor
MGPUSim: enabling multi-GPU performance modeling and optimization
FLATS, a Machine for Numerical, Symbolic and Associative Computing
NIFDY: A Low Overhead, High Throughput Network Interface
A Single-Relation Module for a Data Base Machine
An Investigation of Descriptor Oriented Architecture
HiveMind: a hardware-software system stack for serverless edge swarms
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2015, Portland, OR, USA, June 14, 2015
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism
Gorgon: Accelerating Machine Learning from Relational Data
An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols
Implementation of Precise Interupts in Pipelined Processors
SEESAW: Using Superpages to Improve VIPT Caches
Enhancing boosting with semantic register in a superscalar processor
The road to exascale AI
GCoM: a detailed GPU core model for accurate analytical modeling of modern GPUs
Maya: Using Formal Control to Obfuscate Power Side Channels
RelaxFault Memory Repair
ECMon: exposing cache events for monitoring
Waferscale Network Switches
A Microprogrammed Processor For Interactive Computer Graphics
Better exploration of region-level value locality with integrated computation reuse and value prediction
MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search
pSyncPIM: Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures
Scalable power control for many-core architectures running multi-threaded applications
Technology-Driven, Highly-Scalable Dragonfly Topology
Collision Prediction for Robotics Accelerators
Efficient metadata management for irregular data prefetching
OptiPIM: Optimizing Processing-in-Memory Acceleration Using Integer Linear Programming
Dynamic Memory Dependence Predication
Retrospective: IMPACT: An Architectural Framework for Multiple-Instruction Issue
ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast
Fast Object-Oriented Procedure Calls: Lessons from the Intel 432
Proceedings of the 3rd Annual Symposium on Computer Architecture, Clearwater, FL, USA, January 1976
Cooperative boosting: needy versus greedy power management
Hybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via Gradient Redistribution
SHARP: A Short-Word Hierarchical Accelerator for Robust and Practical Fully Homomorphic Encryption
Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures
Effective ahead Pipelining of Instruction Block Address Generation
Catnap: energy proportional multiple network-on-chip
A Machine-Oriented Resource Management Architecture
Slack: Maximizing Performance Under Technological Constraints
XHarvest: Rethinking High-Performance and Cost-Efficient SSD Architecture with CXL-Driven Harvesting
GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction
Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
täk¯: a polymorphic cache hierarchy for general-purpose optimization of data movement
EyeCoD: eye tracking system acceleration via flatcam-based algorithm & accelerator co-design
Architectural Issues in Designing Symbolic Processors in Optics
Positional Adaptation of Processors: Application to Energy Reduction
CraterLake: a hardware accelerator for efficient unbounded computation on encrypted data
Uniform Theory of the Shuffle-Exchange Type Permutation Networks
Constructing timing-based covert channels in mobile networks by adjusting CPU frequency
CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
Energy-effective issue logic
A Multiprocessor Data Flow Machine that Supports Generalized Procedures
A Simulation Study of Two-Level Caches
A scalable approach to thread-level speculation
Accelerating database analytic query workloads using an associative processor
Heterogeneous Computer Architecture
MESA: Microarchitecture Extensions for Spatial Architecture Generation
Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic
A Decentralized Control, Highly Concurrent Multiprocessor
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing
Debunking the CUDA Myth Towards GPU-based AI Systems: Evaluation of the Performance and Programmability of Intel's Gaudi NPU for AI Model Serving
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor
Clock rate versus IPC: the end of the road for conventional microarchitectures
Phastlane: a rapid transit optical routing network
A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA
Energy-driven integrated hardware-software optimizations using SimplePower
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware
NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing
Some Simplified Performance Modeling Techniques with Applications to a New Ring-Structured Microcomputer Network
Accelerating Simulation of Quantum Circuits under Noise via Computational Reuse
Dynamic IPC/Clock Rate Optimization
(SM)2: Sparse Matrix Solving Machine
Janus: optimizing memory and storage support for non-volatile memory systems
Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units
A Single User Multiprocessor Incorporating Processor Manipulation Facilities
A memory system design framework: creating smart memories
Monitoring Program Behaviour on SUPRENUM
Conjoined Computer Systems: An Architecture for Laboratory Data Processing and Instrument Control
Effective Jump-Pointer Prefetching for Linked Data Structures
NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators
The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs
BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing
Training personalized recommendation systems from (GPU) scratch: look forward not backwards
OUTRIDER: efficient memory latency tolerance with decoupled strands
Parallel Algorithms and Architectures for Rule-Based Systems
Enabling Scientific Computing on Memristive Accelerators
Covert channels through branch predictors: a feasibility study
Structure of an Efficient Duplex Memory for Processing Fault-Tolerant Programs
Perceptron-based prefetch filtering
Can Data-Only Exploits be Detected at Runtime Using Hardware Events?: A Case Study of the Heartbleed Vulnerability
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
Reinforcement Learning-Guided Graph State Generation in Photonic Quantum Computers
Peak Efficiency Aware Scheduling for Highly Energy Proportional Servers
Performance Measurement of Data Communication Systems with Emphasis on Open System Interconnections (OSI)
Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs
No-FAT: Architectural Support for Low Overhead Memory Safety Checks
An Architectural Perspective on a Memory Access Controller
High-Performance Multi-Queue Buffers for VLSI Communication Switches
The Minerva Multi-Micropocessor
EMMA: An Industrial Experience on Large Multiprocessing Architectures
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
Dynamic Decentralized Cache Schemes for MIMD Parallel Processors
A micro-architectural analysis of switched photonic multi-chip interconnects
A Self-Managing Secondary Memory System
HYTE: Flexible Tiling for Sparse Accelerators via Hybrid Static-Dynamic Approaches
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions
Spy in the GPU-box: Covert and Side Channel Attacks on Multi-GPU Systems
A Distributed Multiple-Response Resolver for Value-Ordered Retrieval
Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems
The J-Machine Multicomputer: An Architectural Evaluation
Effects of Building Blocks on the Performance of Super-Scalar Architectures
Computation Reuse in DNNs by Exploiting Input Similarity
Cache Performance of Vector Processors
Limiting the power consumption of main memory
Simultaneous branch and warp interweaving for sustained GPU performance
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability
Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors
Modeling and Measurement of the Impact of Input/Output on System Performance
Fidas: fortifying the cloud via comprehensive FPGA-based offloading for intrusion detection: industrial product
A Hardware Accelerator for Speech Recognition Algorithms
Proceedings of the 8th Annual Symposium on Computer Architecture, Minneapolis, MN, USA, May 1981
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
A Microprocessor-Based Virtual Memory System
Printed Microprocessors
A Case for Two-Way Skewed-Associative Caches
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism
The Dataflow Abstract Machine Simulator Framework
Ecco: Improving Memory Bandwidth and Capacity for LLMs via Entropy-Aware Cache Compression
The Dark Side of DNN Pruning
A Distributed I/O Architecture for HARTS
A Dynamic Storage Scheme for Conflict-Free Vector Access
Branch Prediction Based on Universal Data Compression Algorithms
Multicast Snooping: A New Coherence Method Using a Multicast Address Network
(SM)²-II: A New Version of the Sparse Matrix Solving Machine
Hardware Support for the Concurrent Programming in Loosely Coupled Multiprocessors
Highly Concurrent Stream Synchronization in Many-core Embedded Systems
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
KCM: A Knowledge Crunching Machine
Exploiting small leakages in masks to turn a second-order attack into a first-order attack
On the Use of Registers vs. Cache to Minimize Memory Traffic
STiNG: A CC-NUMA Computer System for the Commercial Marketplace
Non-Speculative Store Coalescing in Total Store Order
ARTERY: Fast Quantum Feedback using Branch Prediction
A Pipelined Pseudoparallel System Architecture for Motion Analysis
Retrospective: Multiscalar Processors
The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer Node
Navigating big data with high-throughput, energy-efficient data partitioning
SCU: a GPU stream compaction unit for graph processing
Cassandra: Efficient Enforcement of Sequential Execution for Cryptographic Programs
Precise exceptions in relaxed architectures
Reference Concepts in a Tree Structured Address Space
Asymptotic improvements to quantum circuits via qutrits
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
HASP 2014, Hardware and Architectural Support for Security and Privacy, Minneapolis, MN, USA, June 15, 2014
Dynamic Processor Allocation in Hypercube Computers
Anton, a special-purpose machine for molecular dynamics simulation
An algorithm for detecting contention-based covert timing channels on shared hardware
Improving virtualization in the presence of software managed translation lookaside buffers
Fractal++: Closing the performance gap between fractal and conventional coherence
A Highly-Configurable Cache Architecture for Embedded Systems
Side channel vulnerability metrics: the promise and the pitfalls
An Experimental System for Computer Science Instruction
Memory Requirements for Balanced Computer Architectures
RAIDR: Retention-aware intelligent DRAM refresh
Address Size Independence in a 16-Bit Minicomputer
Performance Tradeoffs in Cache Design
Cambricon-D: Full-Network Differential Acceleration for Diffusion Models
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
Chip Architectures Under Advanced Computing Sanctions✱
A Microprocessor Oriented Data Acquisition and Control System for Power System Control
Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product
Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging
Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems
Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers
Transient-Fault Recovery Using Simultaneous Multithreading
The Extra Stage Gamma Network
Multiprogramming for Real-Time Applications
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions
Translation ranger: operating system support for contiguity-aware TLBs
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units
Register file prefetching
Yukta: Multilayer Resource Controllers to Maximize Efficiency
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Spectres, virtual ghosts, and hardware support
Eager pruning: algorithm and architecture support for fast training of deep neural networks
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives
Memory bandwidth in deep learning hardware
Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
Guarded Executing and Branch Prediction in Dynamic ILP Processors
Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution
Trace preconstruction
Performance Analysis of the Alpha 21364-BAsed HP GS1280 Multiprocessor
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network
Retrospective: Decoupled Access/Execute Architectures
Compiler and Hardware Support for Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study
Manycore network interfaces for in-memory rack-scale computing
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers
Function Distribution in Computer System Architectures
SeM: A CPU Architecture Extension for Secure Remote Computing
Prefetch-aware shared resource management for multi-core systems
Parallelization Strategy for CELL TV
The Reconfigurable Arithmetic Processor
Dynamic warp subdivision for integrated branch and memory divergence tolerance
LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference
The load slice core microarchitecture
Evaluation of Design Alternatives for a Multiprocessor Microprocessor
Architectural Semantics for Practical Transactional Memory
Investigating the Viability of Maximum Flexibility Selection Function in Bufferless 2D Meshes
On the value locality of store instructions
Fast and Accurate Instruction Fetch and Branch Prediction
Extrinsic and Intrinsic Text Cloning
Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment
Considerations for New Tactical Computer Systems
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
The Gamma network: A multiprocessor interconnection network with redundant paths
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation
Zettafly: A Network Topology with Flexible Non-blocking Regions for Large-scale AI and HPC Systems
Boosting the Performance of Hybrid Snooping Cache Protocols
A Router Architecture for Real-Time Point-to-Point Networks
Multiple Instruction Stream Processor
On Virtual Memories and Micronetworks
MOESI-prime: preventing coherence-induced hammering in commodity workloads
Markov Chain Models for Analyzing Memory Interference in Multiprocessor Computer Systems
A Computer Architecture and its Programming Language
Race-Free Interconnection Networks and Multiprocessor Consistency
Harmony: Collection and analysis of parallel block vectors
STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution
Exploiting Structural Duplication for Lifetime Reliability Enhancement
An Economical Solution to the Cache Coherence Problem
Overview to the Fifth Generation Computer System Project
Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking
Architecture of the Symbolics 3600
Accelerating GPU Hardware Transactional Memory with Snapshot Isolation
PACMAN: attacking ARM pointer authentication with speculative execution
Themis: a network bandwidth-aware collective scheduling policy for distributed training of DL models
A SAT Scalpel for Lattice Surgery: Representation and Synthesis of Subroutines for Surface-Code Fault-Tolerant Quantum Computing
Security Analysis of Processor Instruction Set Architecture for Enforcing Control-Flow Integrity
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism
MTIA: First Generation Silicon Targeting Meta's Recommendation Systems
Reducing the Cost of Branches by Using Registers
The K2 Parallel Processor: Architecture and Hardware Implementation
Predictive Power Management for Multi-core Processors
Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers
Decentralized Priority Control in Data Communication
A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor
Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI
Improving AP1000 Parallel Computer Performance with Message Communication
Unconstrained Speculative Execution with Predicated State Buffering
Parallel Architecture for OPS5
39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA
Parallel Driving for Fast Quantum Computing Under Speed Limits
Single-Address-Space FaaS with Jord
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991
An Adaptive Multimicroprocessor Array Computing Structure for Radar Signal Processing Applications
Evaluation of the SPUR Lisp Architecture
Multiple-banked register file architectures
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors
NetCrafter: Tailoring Network Traffic for Non-Uniform Bandwidth Multi-GPU Systems
Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985
Information Content of CPU Memory Referencing Behavior
A Robust Main-Memory Compression Scheme
Memory management support for tiled array organization
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA
iGPU: Exception support and speculative execution on GPUs
Architecture for Protecting Critical Secrets in Microprocessors
Sparsity-Aware and Re-configurable NPU Architecture for Samsung Flagship Mobile SoC
Enhancing effective throughput for transmission line-based bus
Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor
Pseudo MIMD Array Processor - AAP2
Proceedings of the 4th Annual Symposium on Computer Architecture, College Park, MD, USA, March 1977
Message Communication Protocol and Operation System Design for the Distributed Loop Computer Network (DLCN)
Hardware Implementation of Communication Protocols: A Formal Approach
CPPC: correctable parity protected cache
Towards sustainable in-situ server systems in the big data era
Spatio-temporal memory streaming
SNS's not a synthesizer: a deep-learning-based synthesis predictor
Get Out of the Valley: Power-Efficient Address Mapping for GPUs
Optimizing CPU Performance for Recommendation Systems At-Scale
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates
Achieving High Instruction Cache Performance with an Optimizing Compiler
SAC: Sharing-Aware Caching in Multi-Chip GPUs
MU6-G: A New Design to Achieve Mainframe Performance from a Mini-Sized Computer
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware
A Practical Parallel Garbage Collection Algorithm and Its Implementation
Proposing a new task model towards many-core architecture
Traversing Binary Tree Structures with Shift Register Memories
HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging
HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits
Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management
Instruction set design issues relating to a static dataflow computer
The New Generation of Computer Architecture
Lumina: Real-Time Neural Rendering by Exploiting Computational Redundancy
Continuous Optimization
Architectural Support for Server-Side PHP Processing
A Language for Describing Predictors and Its Application to Automatic Synthesis
ANSMET: Approximate Nearest Neighbor Search with Near-Memory Processing and Hybrid Early Termination
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor
The Chinese Remainder Theorem and the Prime Memory System