yusuke1997/dblp-id-title huggingface dataset:
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs
Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection
Two-terminal resistive switches (memristors) for memory and logic applications
Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search
Security Enhanced Linux on embedded systems: A hardware-accelerated implementation
Hierarchical random-walk algorithms for power grid analysis
Efficient reachability checking using sequential SAT
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
Congestion prediction in floorplanning
TENET: Temporal CNN with Attention for Anomaly Detection in Automotive Cyber-Physical Systems
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture
Low-cost design for repair with circuit partitioning
Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAs
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses
Meeting Job-Level Dependencies by Task Merging
An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning
Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature's Power in Real-World Spatial-Temporal Graph Learning
Oscillation ring based interconnect test scheme for SOC
Design of an efficient memory subsystem for network processor
Network flow modeling for escape routing on staggered pin arrays
A lightweight OpenMP4 run-time for embedded systems
Interconnect RL extraction at a single representative frequency
Testing stuck-open faults of priority address encoder in content addressable memories
Design challenges for 0.1um and beyond: embedded tutorial
A thermal-aware application specific routing algorithm for Network-on-Chip design
A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis
Designing a custom architecture for DCT using NISC technology
Issues in debugging highly parallel FPGA-based applications derived from source code
Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine
Open access overview "industrial experience"
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection
VIDE: a visual VHDL integrated design environment
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software
A mixed-mode extraction flow for high performance microprocessors
Detailed routing by sparse grid graph and minimum-area-captured path search
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating
Improved clock-gating control scheme for transparent pipeline
A near optimal deblocking filter for H.264 advanced video coding
Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCs
Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators
A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression
BTI-aware design using variable latency units
UniPhier: series development and SoC management
Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimization
Tackling close-to-band passivity violations in passive macro-modeling
High-level synthesis for DSP applications using heterogeneous functional units
Current source modeling in the presence of body bias
An application specific Java processor with reconfigurabilities
Optimization methods for lookup-table-based FPGAs using transduction method
Placement with symmetry constraints for analog layout design using TCG-S
Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization
An improved test access mechanism structure and optimization technique in system-on-chip
Fault modeling and testing of retention flip-flops in low power designs
SMoSi: A framework for the derivation of sleep mode traces from RTL simulations
Performance analysis on structure of racetrack memory
Exploiting Don't Caers During Data Sequencing using Genetic Algorithms
A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators
Simultaneous template optimization and mask assignment for DSA with multiple patterning
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization
A bipolar IF amplifier/RSSI for ASK receiver
GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions
Scan-chain Optimization Algorithms for Multiple Scan-paths
On reducing both shift and capture power for scan-based testing
Evaluation of on-chip transmission line interconnect using wire length distribution
Unified non-volatile memory and NAND flash memory architecture in smartphones
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
High-level design for asynchronous logic
Balanced truncation for time-delay systems via approximate Gramians
Low-power multiple-valued current-mode integrated circuit with current-source control and its application
Design and implementation of transducer for ARM-TMS communication
Improving routing efficiency for network-on-chip through contention-aware input selection
Speech recognition chip for monosyllables
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints
A novel framework for multilevel full-chip gridless routing
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design
A DSM-based Polar Transmitter with 23.8% System Efficiency
HyCOMP: A Compiler for ANN-SNN Hybrid Accelerators
Interconnect-driven floorplanning by searching alternative packings
An industrial perspective of power-aware reliable SoC design
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation
Signal-path driven partition and placement for analog circuit
ApproxEye: Enabling approximate computation reuse for microrobotic computer vision
Exploration of approximate multipliers design space using carry propagation free compressors
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits
A model-adaptable MOSFET parameter extraction system
A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique
A fast and effective dynamic trace-based method for analyzing architectural performance
Enhanced Operator Learning for Scalable and Ultra-fast Thermal Simulation in 3D-IC Design
An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips
AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis
Approximate logic synthesis for FPGA by wire removal and local function change
Weakly nonlinear circuit analysis based on fast multidimensional inverse Laplace transform
Efficient BIST design for sequential machines using FiF-FoF values in machine states
Design and verification methods of Toshiba's wireless LAN baseband SoC
End-to-end Compilation is All FPGAs Need: A Unified Overlay-based FPGA Compiler for Deep Learning
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing
A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers
Multi-mode trace signal selection for post-silicon debug
RobustDiCE: Robust and Distributed CNN Inference at the Edge
Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Dynamic Programming Assisted Quantization Approaches for Compressing Normal and Robust DNN Models
Maze routing with OPC consideration
KalmanHD: Robust On-Device Time Series Forecasting with Hyperdimensional Computing
A robust detailed placement for mixed-size IC designs
A New Single-Clock Flip-Clop for Half-Swing Clocking
A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver
Overview on Low Power SoC Design Technology
A static scheduling approach to enable safety-critical OpenMP applications
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR
RCLK-VJ network reduction with Hurwitz polynomial approximation
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes
Discovering the in-Memory Kernels of 3D Dot-Product Engines
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic
Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors
Healthcare of an organization: Using wearable sensors and feedback system for energizing workers
Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm
P 3 M: a PIM-based neural network model protection scheme for deep learning accelerator
Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR application
Alleviate chip I/O pin constraints for multicore processors through optical interconnects
ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations
Faster and Better Spectral Algorithms for Multi-Way Partitioning
Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction
Normally-off computing project: Challenges and opportunities
Optimal die placement for interposer-based 3D ICs
Loadsa: A yield-driven top-down design method for STT-RAM array
New opportunities with the open architecture test system
Binary convolutional neural network on RRAM
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip
Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization
JOP-plus - A processor for efficient execution of java programs extended with GALS concurrency
A new layout-driven timing model for incremental layout optimization
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation
Balloonfish: Utilizing morphable resistive memory in mobile virtualization
Variation-aware resource sharing and binding in behavioral synthesis
Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction
ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress
MACO: A HW-Mapping Co-optimization Framework for DNN Accelerators
SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network
DARPA's adaptive computing systems program
IC Piracy prevention via Design Withholding and Entanglement
A fast machine learning-based mask printability predictor for OPC acceleration
RF design methodologies bridging system-IC-module design
Built-in self at-speed delay binning and calibration mechanism in wireless test platform
FEI: Fusion Processing of Sensing Energy and Information for Self-Sustainable Infrared Smart Vision System
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification
Dynamic and adaptive allocation of applications on MPSoC platforms
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits
Area routing oriented hierarchical corner stitching with partial bin
Model Order Reduction of Large Circuits Using Balanced Truncation
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars
Performance-driven multi-level clustering for combinational circuits
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Reconfigurable synchronized dataflow processor
Row-based area-array I/O design planning in concurrent chip-package design flow
A UML-based approach for heterogeneous IP integration
An analytic calculation method for delay time of RC-class interconnects
An approach to the RF-LSI design for ubiquitous communication appliances
Clock rescheduling for timing engineering change orders
A New Pipelined Architecture for Fuzzy Color Correction
A flexible framework for communication evaluation in SoC design
Graph matching-based algorithms for array-based FPGA segmentation design and routing
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface
A regulated charge pump with low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting
FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds
Design of real-time VGA 3-D image sensor using mixed-signal techniques
Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter
Rate analysis for streaming applications with on-chip buffer constraints
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures
Automated generation of dynamic binary translators for instruction set simulation
Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency
Design of POP-11 (PDP-11 on programmable chip)
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm
TCAD/DA for MPU and ASIC Development
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs
Controlling NBTI degradation during static burn-in testing
Symmetry constraint based on mismatch analysis for analog layout in SOI technology
An efficient combinationality check technique for the synthesis of cyclic combinational circuits
Automatic Test Pattern Generation and Compaction for Deep Neural Networks
C-based behavioral synthesis and verification analysis on industrial design examples
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses
Sequential Printed Multilayer Perceptron Circuits for Super-TinyML Multi-Sensory Applications
S 2 -PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits
A variable-voltage low-power technique for digital circuit system
Physical design techniques for optimizing RTA-induced variations
Improving the scalability of SAMBA bus architecture
Statistical analysis of process variation based on indirect measurements for electronic system design
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition
Delay variation tolerance for domino circuits
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems
A binding algorithm in high-level synthesis for path delay testability
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors
Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation
Security of Neural Networks from Hardware Perspective: A Survey and Beyond
Substrate noise modeling in early floorplanning of MS-SOCs
Bus-aware microarchitectural floorplanning
Safety-Aware Flexible Schedule Synthesis for Cyber-Physical Systems Using Weakly-Hard Constraints
A computer aided engineering system for memory BIST
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Recent Advances in Asynchronous Design Methodologies
Variability mapping at runtime using the PAnDA multi-reconfigurable architecture
BonnCell: Automatic layout of leaf cells
Enhancing the performance of multi-cycle path analysis in an industrial setting
Simultaneous block and I/O buffer floorplanning for flip-chip design
Fast Buffered Delay Estimation Considering Process Variations
An Algebraic Approach to Partial Synthesis of Arithmetic Circuits
Efficient synthesis of speed-independent combinational logic circuits
An any-angle routing method using quasi-Newton method
A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique
Dynamic power management using on demand paging for networked embedded systems
A comparison of the RTU hardware RTOS with a hardware/software RTOS
Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)
An alternative polychronous model and synthesis methodology for model-driven embedded software
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
Efficient matrix exponential method based on extended Krylov subspace for transient simulation of large-scale linear circuits
A deep reinforcement learning framework for optimizing fuel economy of hybrid electric vehicles
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues
Parallelization in Co-Compilation for Configurable Accelerators
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development
Performance driven reliable link design for networks on chips
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model
A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs
SWAT: An Efficient Swin Transformer Accelerator Based on FPGA
Integration of supercubing and learning in a SAT solver
FeMIC: Multi-Operands in-Memory Computing Based on FeFETs
A statistical gate delay model for intra-chip and inter-chip variabilities
Buffer insertion to remove hold violations at multiple process corners
Algorithm for synthesis and exploration of clock spines
Efficient octilinear Steiner tree construction based on spanning graphs
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration
Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration
HyPE: hybrid power estimation for IP-based programmable systems
Approximation Algorithm for Process Mapping on Network Processor Architectures
Secure scan design using shift register equivalents against differential behavior attack
A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support
A unified methodology for power supply noise reduction in modern microarchitecture design
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries
A novel PUF based on cell error rate distribution of STT-RAM
Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation
Function Decomposition and Synthesis Using Linear Sifting
PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoC
TERPS: the embedded reliable processing system
Worst case execution time analysis for synthesized hardware
Dual-output wireless power delivery system for small size large volume wireless memory card
Verification methodology of compatible microprocessors
A note on the relationship between signal probability and switching activity
Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models
A V DD independent temperature sensor circuit with scaled CMOS process
Detailed placement for improved depth of focus and CD control
Soft lists: a native index structure for NOR-flash-based embedded devices
An efficient solution to the storage correspondence problem for large sequential circuits
Data compression via logic synthesis
A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning
Offline program re-mapping to improve branch prediction efficiency in embedded systems
An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems
Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systems
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems
Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing
University LSI design contest
A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance
Trace Compaction using SAT-based Reachability Analysis
CHDStd - A Model for Deep Submicron Design Tools
Theory of Ising Machines and a Common Software Platform for Ising Machines
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis
HDTV1080p HEVC Intra encoder with source texture based CU/PU mode pre-decision
A bandwidth and memory efficient MPEG-4 shape encoder
An automated design flow for 3D microarchitecture evaluation
Fixed-outline thermal-aware 3D floorplanning
Opportunities and challenges for better than worst-case design
PMU-Leaker: Performance Monitor Unit-Based Realization of Cache Side-Channel Attacks
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores
A building block placement tool
Leveraging parallelism in the presence of control flow on CGRAs
Dynamic voltage domain assignment technique for low power performance manageable cell based design
Clock tree optimization for Electromagnetic Compatibility (EMC)
Topological routing path search algorithm with incremental routability test
Invited paper: SPICE-Compatible Modeling and Design for Electronic-Photonic Integrated Circuits
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines
Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form
A WiMAX turbo decoder with tailbiting BIP architecture
Aspects of GPU for general purpose high performance computing
T-SPaCS - A two-level single-pass cache simulation methodology
SIPredict: Efficient post-layout waveform prediction via System Identification
CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip
A reconfigurable accelerator for neuromorphic object recognition
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial
Post-layout logic duplication for synthesis of domino circuits with complex gates
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction
DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures
Signal integrity modeling and measurement of TSV in 3D IC
An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task Model