yusuke1997/dblp-id-title huggingface dataset:
Virtual SoPC rad-hardening for satellite applications
Fault-resilient NoC router with transparent resource allocation
Fast integration of hardware accelerators for dynamically reconfigurable architecture
STARSoC : A C-based platform for rapid prototyping of embedded system
A Fast Prototyping Workflow for Reconfigurable SDR Applications
RecoNoC: A reconfigurable network-on-chip
An application scenario for dynamically reconfigurable FPGAs
Flexible, ultra-low power sensor nodes through configurable finite state machines
AWAIT: An Ultra-Lightweight Soft-Error Mitigation Mechanism for Network-on-Chip Links
Mixed-criticality NoC partitioning based on the NoCDepend dependability technique
Dynamically reconfigurable FIR filter architectures with fast reconfiguration
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling
Automatic saboteur placement for emulation-based multi-bit fault injection
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
A programmable and reconfigurable core for binary image processing
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling
NoCmodel: An extensible framework for Network-on-Chips modeling
How to Secure Embedded Programmable Gate Arrays?
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation
ENOSYS FP7 EU project: An integrated modeling and synthesis flow for embedded systems design
General solutions for MTTF and steady-state availability of NMR systems
Special Purpose Multi-processor for On-line Fault Detection on Induction Motors during Steady State
A hierarchical reconfigurable micro-coded multi-core processor for IoT applications
On implementability of Polymorphic Register Files
Comparative analysis of flexible cryptographic implementations
A SDM-TDM based circuit-switched router for on-chip networks
Dynamically Reconfigurable RF-NoC with Distance-Aware Routing Algorithm
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking
A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs
Dynamic spatially isolated secure zones for NoC-based many-core accelerators
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications
MRAPI resource management layer on reconfigurable systems-on-chip
Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures
11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2016, Tallinn, Estonia, June 27-29, 2016
Towards a Safety and Energy Aware protocol for Wireless Communication
Control Unit for Parallel Embedded System
High-level design using Intel FPGA OpenCL: A hyperspectral imaging spatial-spectral classifier
Proposition of a benchmark for evaluation of cores mapping onto NoC architectures
Co-Design of Massively Parallel Embedded Processor Architectures
Reconciling application power control and operating systems for optimal power and performance
Threshold-based routing algorithm for RF-NoC OFDMA architecture
13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2018, Lille, France, July 9-11, 2018
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management
SystemC design of a smart camera
Integrated Evaluation Platform for Secured Devices
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
A Reconfigurable Multi-Processor Platform for Convolutional and Turbo Decoding
Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era
An Integrated Toolchain for Overlay-centric System-on-chip
Analysis of radiation-induced SEUs on dynamic reconfigurable systems
Exploring Hybrid Memory Caches in Chip Multiprocessors
Measuring memory access latency for software objects in a NUMA system-on-chip architecture
FPGA physical-design automation using Model-Driven Engineering
An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks
A new hardware countermeasure for masking power signatures of crypto cores
Data Transfer Protocols for a Two Slot Based Reconfigurable Platform
Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL
The Xilinx Design Language (XDL): Tutorial and use cases
Invited paper: Design criteria for dependable System-on-Chip architectures
Distributed control for reconfigurable FPGA systems: A high-level design approach
Design-space exploration between FPGA and ASIF
The AV says: Your Hardware Definitions Were Updated!
HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, 20-22 June, 2011
Building and Using System, Algorithmic, and Architectural Power and Energy Models in the FPGA Design
Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005
RecMIN: A reconfiguration architecture for network on chip
A Coding Approach to Improve the Energy Efficiency of Approximate NoCs
High-level model of sensor architecture for hardware and software design space exploration
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m
HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms
Addiguration: Exploring configuration behavior of Spartan-3 devices
Smart technologies for effective reconfiguration: The FASTER approach
A New Client Interface Architecture for the Modified Fat Tree (MFT) Network-on-Chip (NoC) Topology
A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip
Efficient bandwidth regulation at memory controller for mixed criticality applications
14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2019, York, United Kingdom, July 1-3, 2019
9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014, Montpellier, France, May 26-28, 2014
Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems
Adaptive and reconfigurable bubble routing technique for 2D Torus interconnection networks
An FPGA design and implementation framework combined with commercial VLSI CADs
Reconciling performance and predictability on a many-core through off-line mapping
SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications
Exploring the performance of partially reconfigurable point-to-point interconnects
Multi-objective mapping for matrix-based nanocomputer architectures
FPGA Prototyping of a Scan Based System-On-Chip Design
A solution to the data re-ordering problem for multi-pipeline streaming applications on clustered MPSoC
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip
An FPGA target for the StarPU heterogeneous runtime system
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007
Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK
Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip
Translating Java for resource constrained embedded systems
RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs
Centralized traffic monitoring for online-resizable clusters in Networks-on-Chip
LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip
Federated system-to-service authentication and authorization combining PUFs and tokens
System Monitoring and Reconfiguration in Proteo NoC
Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs
Simulations of NoC topologies for generalized hierarchical completely-connected networks
Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip
SoC performance evaluation with ArchC and TLM-2.0
Dynamic resource management in modern multicore SoCs by exposing NoC services
High-level test generation for processing elements in many-core systems
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor
Configurable cache tuning with a victim cache
Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm
A RFID-enabled sensor platform for pervasive monitoring
Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints
3D technologies for reconfigurable architectures
Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system
A Neural Network Based Handover for Multi-RAT Heterogeneous Networks with Learning Agent
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems
Approximation of hyperbolic tangent activation function using hybrid methods
System Level Design of a Dynamically Self-Reconfigurable Image Processing System
Computational self-awareness as design approach for visual sensor nodes
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory
A Low Speed Digital Correlator Architecture Optimized For Resource Savings
Towards a Configurable Many-core Accelerator for FPGA-based embedded systems
FPGA Implemenatation of an Adaptive Filtering: Application on ECG Signal Artefact Suppression in MRI Environment
Approach of an FPGA based adaptive stepper motor control system
Self-adaptive Security at Application Level: a Proposal
Long-Range Dependence and On-chip Processor Traffic
FPGA Acceleration of Approximate KNN Indexing on High- Dimensional Vectors
Emulation of an ASIC power and temperature monitor system for FPGA prototyping
Invited paper: System-wide fault management based on IEEE P1687 IJTAG
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure
Massively Parallel Processor Architectures: A Co-design Approach
A Concept for a Profile-based Dynamic Reconfiguration Mechanism
Side-channel attack resilience through route randomisation in secure real-time Networks-on-Chip
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration
Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware
Mesh and Fat-Tree comparison for dynamically reconfigurable applications
Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs
Secure Architecture in Embedded Systems: an Overview
Enhancing learning of digital systems using a remote FPGA lab
Energy-efficient Execution of Cryptographic Hash Functions on big.LITTLE Architecture
A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates
AMIDAR Project: Lessons Learned in 15 Years of Researching Adaptive Processors
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA
High-Level-Language Compilation for Reconfigurable Computers
Implementation Challenges in Complex Adaptive Systems
Evaluation of speculative execution techniques for high-level language to hardware compilation
Automatic run-time manager generation for reconfigurable MPSoC architectures
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006
Selecting the Optimal Number of Functional Units of Digital Real Time Systems
Re 2 DA: Reliable and reconfigurable dynamic architecture
Secure remote reconfiguration of an FPGA-based embedded system
A framework for effective exploitation of partial reconfiguration in dataflow computing
GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks
Transport layer aware design of network interface in many-core systems
Edge-Computing Perspectives with Reconfigurable Hardware
Dedicated Multiprocessing Unit for Polynomial Evaluation on FPGA in CNC Profile Generation
Dynamically Reconfigurable Architectures for High Speed Vision Systems
Flexible security and its technology limits
Automated composition and execution of hardware-accelerated operator graphs
A reconfigurable distributed architecture for clock generation in large many-core SoC
A framework for hardware-based DVFS management in multicore mixed-criticality systems
A reconfigurable fabric supporting full C/C++ input
SoCRocket - A virtual platform for the European Space Agency's SoC development
12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14, 2017
Approximate Multiply-Accumulate Array for Convolutional Neural Networks on FPGA
CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design
Incremental checkpointing of program state to NVRAM for transiently-powered systems
Efficient congestion-aware selection method for on-chip networks
An adaptive FPGA and its distributed routing
Dataflow programming model for reconfigurable computing
A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfiguration
FPGA SDK for nanoscale architectures
Adaptive parallelism exploitation under physical and real-time constraints for resilient systems
Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validation
Evaluating the feasibility of network coding for NoCs
A Compiler-Centric Infra-Structure for Whole-Board Energy Measurement on Heterogeneous Android Systems
An approach to Co-design of Complex Adaptive Systems
FPGA bitstream protection with PUFs, obfuscation, and multi-boot
Integration of Reconfigurable Logic on Secure Circuits
Experiences on Actor-oriented Design of Reconfigurable Systems
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age
FPGA based traffic sign detection for automotive camera systems
New Three-level Resource Management for Off-line Placement of Hardware Tasks on Reconfigurable Devices
Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms
Fast prototyping environment for embedded reconfigurable units
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors
ISRC: a runtime system for heterogeneous reconfigurable architectures
Session Teaching Reconfigurable Processor: the Biniou Approach
Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications
Online reconfigurable routing method for handling link failures in NoC-based MPSoCs
Implementation of Conditional Execution on a Coarse-Grain Reconfigurable Array
Power management techniques in an FPGA-based WSN node for high performance applications
Execution modeling in self-aware FPGA-based architectures for efficient resource management
A survey on security features in modern FPGAs
Feedback-based admission control for task allocation
Beyond many-core: Commercial workload acceleration in high-end systems
Fast spiking neural network architecture for low-cost FPGA devices
A programming model for reconfigurable computing based in functional concurrency
10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1, 2015
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA
A prototyping environment for high performance reconfigurable computing
Envisioning self-verification of electronic systems
Partial reconfiguration in the implementation of autonomous radio receivers for space
Postponing wearout failures in chip multiprocessors using thermal management and thread migration
Exploiting FPGA block memories for protected cryptographic implementations
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
A Comparison between NoC and Bus Architectures Based on a Real-Application
Novel configurable logic block architecture exploiting controllable-polarity transistors
Formal methods for Embedded Systems Co-design: the FORDESIGN project
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms
The selector-tree network: A new self-routing and non-blocking interconnection network
Investigation of Digital Sensors for Variability Characterization on FPGAs
Practical measurements of data path delays for IP authentication & integrity verification
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration
Using JSON to manage communication between services in the Internet of Things
Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors
Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation
SoCDep 2 : A framework for dependable task deployment on many-core systems under mixed-criticality constraints
Investigating Self-Timed Circuits for the Time-Triggered Protocol
A Coarse-Grain Reconfigurable Machine with Floating-Point Arithmetic Capabilities
Practical Resource Constraints for Online Synthesis
An exploration of heterogeneous systems
Multiple Abstraction Views of FPGA to Map Parallel Applications
Bitfile preservation - Generation of reusable out of context modules
Memory allocation and optimization in system-level architectural synthesis
Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs
Towards a power and energy efficient use of partial dynamic reconfiguration
Communication-centric design for FMC based I/O system
Non-intrusive DVFS emulation in gem5 with application to self-aware architectures
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
A MARTE subset to enable application-platform co-simulation and schedulability analysis of NoC-based embedded systems
Designing formal reconfiguration control using UML/MARTE
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems
Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education
Temperature-based covert channel in FPGA systems
ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip
Towards run-time flexible risk management systems on hybrid platforms
Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins
7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012
S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs
A decentralised, autonomous, and congestion-aware thermal monitoring infrastructure for photonic network-on-chip
Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs
Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet Splitting
FPGA Implementation of a Digital Jitter Measurement Method for SDH Data Streams
Experimental Fault Injection based on the Prototyping of an AES Cryptosystem
Multivariate Stochastic Volatility Model with Cross Leverage
The Deepest Fit
Jointly Modelling Longitudinal and Survival Data
Learning Hierarchical Bayesian Networks for Genome-Wide Association Studies
19th International Conference on Computational Statistics, COMPSTAT 2010, Paris, France, August 22-27, 2010 - Keynote, Invited and Contributed Papers
MCMC Specifics for Latent Variable Models
Supervised Learning from Microarray Data
Bootstrap Prediction in Unobserved Component Models
Bayesian Analysis of Overdispersed Count Data with Application to Teletraffic Monitoring
Partially Linear Models: A New Algorithm and some Simulation Results
Trans-Dimensional Markov Chains and their Applications in Statistics
Estimating Factor Models for Multivariate Volatilities: An Innovation Expansion Method
Bayesian Semiparametric Seemingly Unrelated Regression
Clockwise Bivariate Boxplots
Some Algorithms to Fit some Reliability Mixture Models under Censoring
Anticipated and Adaptive Prediction in Functional Discriminant Analysis
On Multiple-Case Diagnostics in Linear Subspace Method
Building End-User Statistical Applications: An Example Using STABLE
MCMC Model for Estimation Poverty Risk Factors using Household Budget Data
Comparison of Nested Simulated Annealing and Reactive Tabu Search for Efficient Experimental Designs with Correlated Data
Assessing the Association between Environmental Exposures and Human Health
A Visual Future for Statistical Computing
DetMCD in a Calibration Framework
Induction of Association Rules: Apriori Implementation
Integrating Approximate Bayesian Computation with Complex Agent-Based Models for Cancer Research
Stochastic Approximation for Multivariate and Functional Median
Testing for Simplification in Spatial Models
Computational Statistics Solutions for Molecular Biomedical Research: A Challenge and Chance for Both
Some Examples of Statistical Computing in France During the 19th Century
Piece-wise Detection of Spinal Scoliosis
Empirical Dynamics and Functional Data Analysis
Statistical Computing on Web Browsers with the Dynamic Link Library
MCMC Solution to Circle Fitting in Analysis of RICH Detector Data
Mixtures of Weighted Distance-Based Models for Ranking Data
Detecting Multivariate Outliers Using Projection Pursuit with Particle Swarm Optimization
Combining Graphical Models and PCA for Statistical Process Control
Locally and Bayesian Optimal Designs for Binary Dose - Response Models with Various Link Functions
Interactive Graphics for Data Mining
Computational Connections between Robust Multivariate Analysis and Clustering
MD*Book online & e-stat: Generating e-stat Modules from L A T E X
Semiparametric Seasonal Cointegrating Rank Selection
Using Threshold Accepting to Improve the Computation of Censored Quantile Regression
Imputation of Continuous Variables Missing at Random using the Method of Simulated Scores
Sweave: Dynamic Generation of Statistical Reports Using Literate Data Analysis
Improved Fitting of Constrained Multivariate Regression Models using Automatic Differentiation
Exploring Time Series Using Semi- and Nonparametric Methods
Computational Statistics for Pharmacokinetic Data Analysis
Bootstrap Calibration in Functional Linear Regression Models with Applications
Semiparametric Models with Functional Responses in a Model Assisted Survey Sampling Setting : Model Assisted Estimation of Electricity Consumption Curves
Skewness and Fat Tails in Discrete Choice Models
Frailty Factors and Time-dependent Hazards in Modelling Ear Infections in Children Using BASSIST
Analysis of Clustered Multivariate Data from Developmental Toxicity Studies
Weights and Fragments
Variance Stabilization and Robust Normalization for Microarray Gene Expression Data
On the Convergence of Iterated Random Maps with Applications to the MCEM Algorithm
Teaching Statistics with Electronic Textbooks
e-stat: Development of a Scenario for Statistics in Chemical Engineering
Unobserved Heterogeneity in Store Choice Models
Growing and Visualizing Prediction Paths Trees in Market Basket Analysis
Computational Methods for Time Series Analysis
e-stat: Web-based Learning and Teaching of Statistics in Secondary Schools
Induction of Graphical Models from Incomplete Samples
A Comparison of Recent EM Accelerators within Item Response Theory
Mice and Elephants Visualization of Internet Traffic
Robust Factorization of a Data Matrix
An Alternative Pruning Method Based on the Impurity-Complexity Measure
Evaluating the GPH Estimator via Bootstrap Technique