yusuke1997/dblp-id-title huggingface dataset:
Expediting MRSH-v2 Approximate Matching with Hierarchical Bloom Filter Trees
Digital Forensics and Cyber Crime - 11th EAI International Conference, ICDF2C 2020, Boston, MA, USA, October 15-16, 2020, Proceedings
Finding Forensic Artefacts in Long-Term Frequency Band Occupancy Measurements Using Statistics and Machine Learning
Digital Forensics and Cyber Crime - 10th International EAI Conference, ICDF2C 2018, New Orleans, LA, USA, September 10-12, 2018, Proceedings
Towards Automated Malware Behavioral Analysis and Profiling for Digital Forensic Investigation Purposes
A Digital Forensic Approach for Optimizing the Investigation of Hit-and-Run Accidents
Do Dark Web and Cryptocurrencies Empower Cybercriminals?
Amazon Kindle Fire HD Forensics
Understanding the Security of Deepfake Detection
Digital Forensics and Cyber Crime - Third International ICST Conference, ICDF2C 2011, Dublin, Ireland, October 26-28, 2011, Revised Selected Papers
Dealing with the Problem of Cybercrime
Detection of Frame Duplication Type of Forgery in Digital Video Using Sub-block Based Features
Hybrid Intrusion Detection System for Worm Attacks Based on Their Network Behavior
Digital Forensic Readiness Framework for Ransomware Investigation
Crime and Incident Watch for Smart Cities: A Sensor-Based Approach
On the Reliability of Cell Phone Camera Fingerprint Recognition
Power Analysis Attack Based on GA-Based Ensemble Learning
The Role of Perception in Age Estimation
Analysis of Evidence Using Formal Event Reconstruction
Quantifying Paging on Recoverable Data from Windows User-Space Modules
Attribute-Based Proxy Re-encryption with Privacy Protection for Message Dissemination in VANET
Localization and Detection of Vector Logo Image Plagiarism
Removing Noise (Opinion Messages) for Fake News Detection in Discussion Forum Using BERT Model
An Intelligence Criminal Tracker for Industrial Espionage - Applying Digital Data Acquired Onsite to Target Criminals
Awareness of Scam E-Mails: An Exploratory Research Study - Part 2
Development and Initial User Evaluation of a Virtual Crime Scene Simulator Including Digital Evidence
Exploring the Effectiveness of Digital Forensics Tools on the Sony PlayStation Vita
Cloud Forensic Readiness: Foundations
A Hybrid Cloud Deployment Architecture for Privacy-Preserving Collaborative Genome-Wide Association Studies
Automation of MitM Attack on Wi-Fi Networks
CCBA: Code Poisoning-Based Clean-Label Covert Backdoor Attack Against DNNs
Can Image Watermarking Efficiently Protect Deep-Learning-Based Image Classifiers? - A Preliminary Security Analysis of an IP-Protecting Method
Digital Forensics and Cyber Crime - 14th EAI International Conference, ICDF2C 2023, New York City, NY, USA, November 30, 2023, Proceedings, Part I
Gotta Catch'em All! Improving P2P Network Crawling Strategies
Volatility Custom Profiling for Automated Hybrid ELF Malware Detection
Protecting Digital Evidence Integrity by Using Smart Cards
A Multi-carrier Information Hiding Algorithm Based on Layered Compression of 3D Point Cloud Model
Investigating File Encrypted Material Using NTFS $logfile
Yahoo! Messenger Forensics on Windows Vista and Windows 7
PBPAFL: A Federated Learning Framework with Hybrid Privacy Protection for Sensitive Data
ForensiQ: A Knowledge Graph Question Answering System for IoT Forensics
Evidence Gathering in IoT Criminal Investigation
Resurrection: A Carver for Fragmented Files
DynVMDroid: Android App Protection via Code Disorder and Dynamic Recovery
Neural Representation Learning Based Binary Code Authorship Attribution
AndroParse - An Android Feature Extraction Framework and Dataset
An IP Traceback Model for Network Forensics
Software Piracy Forensics: The Need for Further Developing AFC
Digital Forensics and Cyber Crime - First International ICST Conference, ICDF2C 2009, Albany, NY, USA, September 30-October 2, 2009, Revised Selected Papers
Forensic Extractions of Data from the Nokia N900
Decoding HDF5: Machine Learning File Forensics and Data Injection
FindEvasion: An Effective Environment-Sensitive Malware Detection System for the Cloud
An Architecture for the Forensic Analysis of Windows System Artifacts
Auto-Parser: Android Auto and Apple CarPlay Forensics
Law Enforcement 2.0: Regulating the Lawful Interception of Social Media
Towards a New Data Mining-Based Approach for Anti-Money Laundering in an International Investment Bank
Internet Child Pornography, U.S. Sentencing Guidelines, and the Role of Internet Service Providers
The Need for Biometric Anti-spoofing Policies: The Case of Etsy
Are External Auditors Capable of Dealing with Cybersecurity Risks?
A Strategy for Testing Metadata Based Deleted File Recovery Tools
Cybercrime, Censorship, Perception and Bypassing Controls: An Exploratory Study
Password Managers and Vault Application Security and Forensics: Research Challenges and Future Opportunities
Digital Forensics Education: A Multidisciplinary Curriculum Model
A Measurement Study on Interprocess Code Propagation of Malicious Software
Detection of Masqueraded Wireless Access Using 802.11 MAC Layer Fingerprints
Formal Parameterization of Log Synchronization Events within a Distributed Forensic Compute Cloud Database Environment
Optir-SBERT: Cross-Architecture Binary Code Similarity Detection Based on Optimized LLVM IR
Digital Forensics and Cyber Crime - 9th International Conference, ICDF2C 2017, Prague, Czech Republic, October 9-11, 2017, Proceedings
Semantic Modelling of Digital Forensic Evidence
Cyber Crime Undermines Data Privacy Efforts - On the Balance Between Data Privacy and Security
A Novel Methodology for Malware Intrusion Attack Path Reconstruction
A Review and Comparative Study of Digital Forensic Investigation Models
Results of Field Testing Mobile Phone Shielding Devices
Poisoning-Attack Detection Using an Auto-encoder for Deep Learning Models
Regulating Social Network Services for Lawful Interception
Find My IoT Device - An Efficient and Effective Approximate Matching Algorithm to Identify IoT Traffic Flows
Forensic Investigations of Google Meet and Microsoft Teams - Two Popular Conferencing Tools in the Pandemic
The Forensic Value of the Windows 7 Jump List
Adapting to Local Conditions: Similarities and Differences in Anonymous Online Market Between Chinese and English Speaking Communities
Sketch-Based Modeling and Immersive Display Techniques for Indoor Crime Scene Presentation
A Digital Forensic Investigation and Verification Model for Industrial Espionage
Understanding the Brains and Brawn of Illicit Streaming App
Coriander: A Toolset for Generating Realistic Android Digital Evidence Datasets
A Canary in the Voting Booth: Attacks on a Virtual Voting Machine
Fuzzy System-Based Suspicious Pattern Detection in Mobile Forensic Evidence
Research on the Method of Selecting the Optimal Feature Subset in Big Data for Energy Analysis Attack
Advanced Techniques for Reconstruction of Incomplete Network Data
Remote Air-Gap Live Forensics
An Agent Based Tool for Windows Mobile Forensics
Digital Forensics and Cyber Crime - 7th International Conference, ICDF2C 2015, Seoul, South Korea, October 6-8, 2015, Revised Selected Papers
Smartphone Verification and User Profiles Linking Across Social Networks by Camera Fingerprinting
Mozilla Firefox Browsing Artifacts in 3 Different Anti-forensics Modes
fishy - A Framework for Implementing Filesystem-Based Data Hiding Techniques
Measuring the Preference of Image Content for Self-reported Consumers of Child Pornography
Power Analysis Attack Based on BS-XGboost Scheme
Forensic Analysis and Remote Evidence Recovery from Syncthing: An Open Source Decentralised File Synchronisation Utility
An Automated Link Analysis Solution Applied to Digital Forensic Investigations
Defining a Standard for Reporting Digital Evidence Items in Computer Forensic Tools
Unraveling Network-Based Pivoting Maneuvers: Empirical Insights and Challenges
Forensic Artifacts of the flareGet Download Manager
Forensically Sound Retrieval and Recovery of Images from GPU Memory
Detecting and Preventing the Electronic Transmission of Illicit Images and Its Network Performance
Finding Anomalous and Suspicious Files from Directory Metadata on a Large Corpus
Memory Forensics and the Macintosh OS X Operating System
DEML: Data-Enhanced Meta-Learning Method for IoT APT Traffic Detection
Face Recognition Based on Wavelet Transform and Adaptive Local Binary Pattern
Accessing Secure Data on Android Through Application Analysis
A Visualization Scheme for Network Forensics Based on Attribute Oriented Induction Based Frequent Item Mining and Hyper Graph
On Exploring the Sub-domain of Artificial Intelligence (AI) Model Forensics
Analysis of the HIKVISION DVR File System
Quantum Computing Challenges and Impact on Cyber Security
PCWQ: A Framework for Evaluating Password Cracking Wordlist Quality
Digital Forensics Event Graph Reconstruction
A Multi-carrier Information Hiding Algorithm Based on Dual 3D Model Spectrum Analysis
Tracking User Activity on Personal Computers
When Should Virtual Cybercrime Be Brought under the Scope of the Criminal Law?
Digital Forensics and Cyber Crime - 4th International Conference, ICDF2C 2012, Lafayette, IN, USA, October 25-26, 2012, Revised Selected Papers
Make Remote Forensic Investigations Forensic Again: Increasing the Evidential Value of Remote Forensic Investigations
All Bot Net: A Need for Smartphone P2P Awareness
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Logic optimization and synthesis: Trends and directions in industry
Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors
Automatic run-time selection of power policies for operating systems
Issues in Implementing Latency Insensitive Protocols
Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing
Loop distribution for K-loops on Reconfigurable Architectures
Mapping into LUT structures
Microarchitectural floorplanning under performance and thermal tradeoff
Embedded Software in Digital AM-FM Chipset
Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
Multi-precision convolutional neural networks on heterogeneous hardware
Co-simulation based platform for wireless protocols design explorations
A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
An evolutionary approach to hardware encryption and Trojan-horse mitigation
An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis
Effective Software Self-Test Methodology for Processor Cores
Memory-access aware DVFS for network-on-chip in CMPs
Jumping Shift: A Logarithmic Quantization Method for Low-Power CNN Acceleration
Efficient High-Level modeling in the networking domain
A coverage metric for the validation of interacting processes
How to Choose Semiconductor IP? - Embedded Processor
Novel application of spintronics in computing, sensing, storage and cybersecurity
Deep Quasi-Periodic Priors: Signal Separation in Wearable Systems with Limited Data
A Fast Approximation Algorithm for MIN-ONE SAT
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices
Energy-efficient FPGA implementation for binomial option pricing using OpenCL
SoC Design and Test Considerations
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults
A New Approach to Test Generation and Test Compaction for Scan Circuits
A new distributed framework for integration of district energy data from heterogeneous devices
Self-Aligned Double-Patterning Aware Legalization
Analog fault testing through abstraction
Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded Platforms
Virtual Fault Simulation of Distributed IP-Based Designs
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
Hardware/Software Co-Design of a Fuzzy RISC Processor
On-chip analog output response compaction
Explicit transient thermal simulation of liquid-cooled 3D ICs
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation
Optimizing the data placement and transformation for multi-bank CGRA computing system
Runtime power estimation of mobile AMOLED displays
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence
1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995
2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology
Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures
EAST: Efficient Assertion Simulation techniques
SySCIM: SystemC-AMS Simulation of Memristive Computation In-Memory
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment
FloppyFloat: An Open Source Floating Point Library for Instruction Set Simulators
Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V
DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder
Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics
Functional Test Generation for Full Scan Circuits
Virtual Manycore platforms: Moving towards 100+ processor cores
Energy-efficient channel alignment of DWDM silicon photonic transceivers
Improving initialization through reversed retiming
Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays
SPIRE: Inferring Hardware Bottlenecks from Performance Counter Data
Asymmetric underlapped FinFET based robust SRAM design at 7nm node
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics
A GPU-accelerated envelope-following method for switching power converter simulation
Memory testing with a RISC microcontroller
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
The road to energy-efficient systems: From hardware-driven to software-defined
Design of Reliable DNN Accelerator with Un-reliable ReRAM
From device to system: cross-layer design exploration of racetrack memory
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing
Thermal test and monitoring [microelectronic structures]
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point
Co-Design of Sustainable Embedded Systems-on-Chip
Automated Testability Enhancements for Logic Brick Libraries
An FPGA-based accelerator for cortical object classification
Run and be safe: mixed-criticality scheduling with temporary processor speedup
SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis
Two-phase resonant clocking for ultra-low-power hearing aid applications
Make Your SoC Design a Winner: Select the Right Memory IP
BerkMin: A Fast and Robust Sat-Solver
DisPEED: Distributing Packet flow analyses in a swarm of heterogeneous EmbEddeD platforms
Simultaneous Denoising and Compression for DVS with Partitioned Cache-Like Spatiotemporal Filter
How to Choose Semiconductor IP: Embedded Software
SC-DEVS: An efficient SystemC extension for the DEVS model of computation
Double-patterning friendly grid-based detailed routing with online conflict resolution
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams
Mutation analysis with coverage discounting
A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology
Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis
MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge
Siamese Neural Encoders for Long-Term Indoor Localization with Mobile Devices
Physically unclonable functions for embeded security based on lithographic variation
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
A Scalable Architecture for Multi-threaded JAVA Applications
Estimation based power and supply voltage management for future RF-powered multi-core smart cards
A Spectral Approach to Scalable Vectorless Thermal Integrity Verification
UPAQ: A Framework for Real-Time and Energy-Efficient 3D Object Detection in Autonomous Vehicles
NBTI mitigation by optimized NOP assignment and insertion
Digital MOS Circuit Partitioning with Symbolic Modeling
Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010
Approximate associative memristive memory for energy-efficient GPUs
Multilevel thermal simulation of MCM's by system 'MONSTR-M'
XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines
Systematic Figure of Merit Computation for the Design of Pipeline ADC
Testability of 2-level AND/EXOR circuits
March LA: a test for linked memory faults
Core Interconnect Testing Hazards
QR-decomposition architecture based on two-variable numeric function approximation
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique
Unified Modeling of Complex Real-Time Control Systems
Analogue layout generation by World Wide Web server-based agents
Statistical Timing Driven Partitioning for VLSI Circuits
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks
Efficient Power Co-Estimation Techniques for System-on-Chip Design
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Accelerating Authenticated Block Ciphers via RISC-V Custom Cryptography Instructions
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Circuit clustering for delay minimization under area and pin constraints
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications
Gap-free Processor Verification by S 2 QED and Property Generation
Block Attribute-aware Data Reallocation to Alleviate Read Disturb in SSDs
Formal specification and dependability analysis of optical communication networks
Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics?
Multi-Vector Tests: A Path to Perfect Error-Rate Testing
CAD for RF circuits
Efficient simulation and modelling of non-rectangular NoC topologies
MDARTS: Multi-objective Differentiable Neural Architecture Search
An efficient resource-optimized learning prefetcher for solid state drives
Self Recovering Controller and Datapath Codesign
On the construction of guaranteed passive macromodels for high-speed channels
A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring
PhoneBit: Efficient GPU-Accelerated Binary Neural Network Inference Engine for Mobile Phones
Procrastinating voltage scheduling with discrete frequency sets
FPGA based Agile Algorithm-On-Demand Co-Processor
Data Space Oriented Scheduling in Embedded Systems
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration
A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor
Automatic design of low-power encoders using reversible circuit synthesis
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Generation of a Reconfigurable Probabilistic Decision-Making Engine based on Decision Networks: UAV Case Study (Interactive Presentation)
Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing
Time analysable synchronisation techniques for parallelised hard real-time applications
FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional Computing
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips
Security Layers and Related Services within the Horizon Europe NEUROPULS Project
Towards total open source in aeronautics and space?
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Automatic application specific floating-point unit generation
On testability of checkable digital circuits under pseudorandom signals
A unified methodology for a fast benchmarking of parallel architecture
AUTOSAR-based communication coprocessor for automotive ECUs
On Secure Data Flow in Reconfigurable Scan Networks
On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying
Corporate Governance and Management of AI-Driven Product Development: Vehicle Automation
Design methodologies for enabling self-awareness in autonomous systems
GRINCH: A Cache Attack against GIFT Lightweight Cipher
Leakage-Aware Interconnect for On-Chip Network
Design fault directed test generation for microprocessor validation
High Security Smartcards
An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits
Accelerating source-level timing simulation
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length
Architectural support for low overhead detection of memory violations
Strategic directions towards multicore application specific computing
An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era
Connection error location and correction in combinational circuits
HVSM: Hardware-variability aware streaming processors' management policy in GPUs
Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices
SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design
Test preparation methodology for high coverage of physical defects in CMOS digital ICs
Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems
Machine Learning Assisted Differential Distinguishers For Lightweight Ciphers
Efficient OpenMP data mapping for multicore platforms with vertically stacked memory
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Chameleon: Channel efficient Optical Network-on-Chip
Supporting task migration in multi-processor systems-on-chip: a feasibility study
Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT
MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN Training
Consequences of RAM Bitline Twisting for Test Coverage
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography
Flexible Thermal Conductance Model (TCM) for Efficient Thermal Simulation of 3-D ICs and Packages
Eliminating intra-warp conflict misses in GPU
Multiple Behavior Module Synthesis Based on Selective Groupings
Compilation flow for classically defined quantum operations