yusuke1997/dblp-id-title huggingface dataset:
Microprocessors in the era of terascale integration
PUFs Deep Attacks: Enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFs
Component-based and aspect-oriented methodology and tool for Real-Time Embedded Control Systems Design
Analysis and optimization of fault-tolerant embedded systems with hardened processors
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current
Late Breaking Results: Leveraging Approximate Computing for Carbon-Aware DNN Accelerators
Logic optimization with considering boolean relations
Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion Detection
A fast parallel sparse solver for SPICE-based circuit simulators
Embedded tutorial: current trends in the design of automotive electronic systems
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis
Coupled Noise Estimation for Distributed RC Interconnect Model
Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs
An RTL methodology to enable low overhead combinational testing
Design for test and reliability in ultimate CMOS
LiGNN: Accelerating GNN Training Through Locality-Aware Dropout
Static netlist verification for IBM high-frequency processors using a tree-grammar
An efficient learning procedure for multiple implication checks
NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI
Distributed sensor for steering wheel rip force measurement in driver fatigue detection
Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008
FLIC: Fast, lightweight checkpointing for mobile virtualization using NVRAM
AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs
Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement
Multi-level attacks: An emerging security concern for cryptographic hardware
Achieving Crash Consistency by Employing Persistent L1 Cache
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
Towards Energy-Efficient CGRAs via Stochastic Computing
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Temperature-Aware Voltage Selection for Energy Optimization
Minimally buffered single-cycle deflection router
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments
A methodology for embedded classification of heartbeats using random projections
Order determination for frequency compensation of negative-feedback systems
A parallel configuration model for reducing the run-time reconfiguration overhead
Minimizing test power in SRAM through reduction of pre-charge activity
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications
IP routing processing with graphic processors
Enhancements of Model and Method in Lithography Hotspot Identification
A 0.964mW digital hearing aid system
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications
Towards formal verification of real-world SystemC TLM peripheral models - a case study
SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
Rapid Generation of Thermal-Safe Test Schedules
Software Processing Performance in Network Processors
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Converging safety and high-performance domains: Integrating OpenMP into Ada
Using symbolic techniques to find the maximum clique in very large sparse graphs
Automating data reuse in High-Level Synthesis
Approximate quaternary addition with the fast carry chains of FPGAs
Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance
On the relation between simulation-based and SAT-based diagnosis
A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems
Learning-based dynamic reliability management for dark silicon processor considering EM effects
Platform Based on Open-Source Cores for Industrial Applications
PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
I 2 CRF: Incremental interconnect customization for embedded reconfigurable fabrics
An area-efficient multi-level single-track pipeline template
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement
Dependability for high-tech systems: an industry-as-laboratory approach
Design and Behavioral Modeling Tools for Optical Network-on-Chip
Instruction Scheduling for Power Reduction in Processor-Based System Design
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
Accelerate analytical placement with GPU: A generic approach
Masking the Energy Behavior of DES Encryption
Design optimizations to improve placeability of partial reconfiguration modules
An efficient wirelength model for analytical placement
RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore
CIM-Based Parallel Fully FFNN Surface Code High-Level Decoder for Quantum Error Correction
Energy-efficient approximate multiplier design using bit significance-driven logic compression
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997
Panel Session - Vertical integration versus disaggregation
TKD: An Efficient Deep Learning Compiler with Cross-Device Knowledge Distillation
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
Evaluation of design for reliability techniques in embedded flash memories
An integrated framework for joint design space exploration of microarchitecture and circuits
Noise Macromodel for Radio Frequency Integrated Circuits
HyperDyn: Dynamic Dimensional Masking for Efficient Hyper-Dimensional Computing
Towards a Uniform Notation for Memory Tests
Efficient incremental clock latency scheduling for large circuits
Computing with ferroelectric FETs: Devices, models, systems, and applications
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation
Accelerating Local Binary Pattern Networks with Software-Programmable FPGAs
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining
A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision
A dynamically reconfigurable packet-switched network-on-chip
Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives
Scalable progress verification in credit-based flow-control systems
Non-intrusive testing technique for detection of Trojans in asynchronous circuits
HD-I-IoT: Hyperdimensional Computing for Resilient Industrial Internet of Things Analytics
qGDP: Quantum Legalization and Detailed Placement for Superconducting Quantum Computers
Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Fault-tolerant control synthesis and verification of distributed embedded systems
Multi-Language System Design
Voltage island management in near threshold manycore architectures to mitigate dark silicon
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging
Unveiling Eurora - Thermal and power characterization of the most energy-efficient supercomputer in the world
VARSHA: variation and reliability-aware application scheduling with adaptive parallelism in the dark-silicon era
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults
Reliability and performance trade-offs for 3D NoC-enabled multicore chips
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Assessing the Quality Level of Digital CMOS IC's under the Hypothesis of Non-Uniform Distribution of Fault Probabilities
Identification and Exploitation of Symmetries in DSP Algorithms
Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects
Interactive presentation: Implementation of a transaction level assertion framework in SystemC
Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems
Predicting energy and performance overhead of Real-Time Operating Systems
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms
RED: A ReRAM-based Deconvolution Accelerator
Crosstalk Minimization in Logic Synthesis for PLA
Security-Aware Approximate Spiking Neural Networks
DyPIM: Dynamic-Inference-Enabled Processing - In-Memory Accelerator
Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters
Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions
KVSSD: Close integration of LSM trees and flash translation layer for write-efficient KV store
Sustainable energy policies: research challenges and opportunities
Time Constrained Modulo Scheduling with Global Resource Sharing
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Estimation of Power Consumption in Encoded Data Buses
On the use of causal feature selection in the context of machine-learning indirect test
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs
n Code: limiting harmful writes to emerging mobile NVRAM through code swapping
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions
Dynamic reconfigurable puncturing for secure wireless communication
Maximizing Computing Accuracy on Resource-Constrained Architectures
MCMQ: Simulation Framework for Scalable Multi-Core Flash Firmware of Multi-Queue SSDs
A wear-leveling-aware dynamic stack for PCM memory in embedded systems
Temperature-aware dynamic resource provisioning in a power-optimized datacenter
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications
Selective flexibility: Breaking the rigidity of datapath merging
Software estimation using a generic-processor model
Engine control: task modeling and analysis
Design and test of the PowerPC 603 microprocessor
Highly Testable and Compact 1-out-of-n Code Checker with Single Output
A confidence-driven model for error-resilient computing
Industrially proving the SPIRIT consortium specifications for design chain integration
Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System
Reconfigurable Logic for Systems on a Chip
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
On Statistical Timing Analysis with Inter- and Intra-Die Variations
Enabling Memory-Efficient On-Device Learning via Dataset Condensation
A distributed and self-calibrating model-predictive controller for energy and thermal management of high-performance multicores
IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security
LASER: A hardware/software approach to accelerate complicated loops on CGRAs
Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering
Nonuniform Banking for Reducing Memory Energy Consumption
Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017
The RowHammer problem and other issues we may face as memory becomes denser
Instruction Scheduling for Dynamic Hardware Configurations
On hierarchical statistical static timing analysis
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods
Implicit index-aware model order reduction for RLC/RC networks
Structural BIST insertion using behavioral test analysis
Scheduling and energy-distortion tradeoffs with operational refinement of image processing
On the efficacy of NBTI mitigation techniques
Block-level bayesian diagnosis of analogue electronic circuits
Parallel co-simulation using virtual synchronization with redundant host execution
Smart Hammering: A practical method of pinhole detection in MRAM memories
Towards low overhead control flow checking using regular structured control
An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints
Applications of Computation-In-Memory Architectures based on Memristive Devices
Characterizing and Optimizing Hybrid DRAM-PM Main Memory System with Application Awareness
Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs
A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications
Timing-constrained I/O buffer placement for flip-chip designs
Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software Countermeasures
On the verification of synthesized designs using automatically generated transformational witnesses
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games
A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
Deterministic Test Pattern Reproduction by a Counter
Modularity vs. Reusability: Code Generation from Synchronous Block Diagrams
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors
Fully Automatic Test Program Generation for Microprocessor Cores
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Using conjugate symmetries to enhance gate-level simulations
P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection
Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processor
RT-VirtIO: Towards the Real-Time Performance of VirtIO in a Two-Tier Computing Architecture
A minimalist approach to Remote Attestation
High Coverage Concolic Equivalence Checking
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs
Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification
Parallel accelerators for GlimmerHMM bioinformatics algorithm
Static analysis to mitigate soft errors in register files
AFTA: A Formal Delay Model for Functional Timing Analysis
Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation
Worst-case communication time analysis of networks-on-chip with shared virtual channels
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Low-Throughput Event-Based Image Sensors and Processing
Utilizing macromodels in floating random walk based capacitance extraction
Increased reproducibility and comparability of data leak evaluations using ExOT
Leverage Emerging Technologies For DPA-Resilient Block Cipher Design
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression
Improving Design Understanding of Processors leveraging Datapath Clustering
Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator
Cycle-count-accurate processor modeling for fast and accurate system-level simulation
Hardware/software approach for code synchronization in low-power multi-core sensor nodes
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors
Optimal scheduling for fast systolic array implementations
Self-awareness in Cyber-Physical Systems: Recent Developments and Open Challenges
RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing Elements
LESAR: A dynamic line-end spacing aware detailed router
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation
The human intranet: where swarms and humans meet
UHS: An Ultra-fast Hybrid Storage Consolidating NVM and SSD in Parallel
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
FPGA architecture characterization for system level performance analysis
Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices
Resource optimization for CSDF-modeled streaming applications with latency constraints
Sensei: An area-reduction advisor for FPGA high-level synthesis
SecBus: Operating System controlled hierarchical page-based memory bus protection
A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications
Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs
DAC: Dedup-assisted compression scheme for improving lifetime of NAND storage systems
Integration of mixed-signal components into virtual platforms for holistic simulation of smart systems
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification
Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors
Late Breaking Results: Towards Efficient Formal Verification of Dot Product Architectures
A fast and accurate methodology for power estimation and reduction of programmable architectures
Accurate timed RTOS model for transaction level modeling
Formal Verification of Booth Radix-8 and Radix-16 Multipliers
Endurance management for resistive Logic-In-Memory computing architectures
Model Abstraction for Formal Verification
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform
Design-for-debug routing for FIB probing
Extreme-scale computer architecture: Energy efficiency from the ground up ‡
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
Cost and Benefit Models for Logic and Memory BIST
Application mapping for express channel-based networks-on-chip
Step by Step from Specification to Realization of an Electrochemical Microsystem
Ultra-low power electronics with Si/Ge tunnel FET
Reducing the storage requirements of a test sequence by using a background vector
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures
Accurate Estimation of Parasitic Capacitances in Analog Circuits
Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
Approximating checkers for simulation acceleration
Stretching the limits of FPGA SerDes for enhanced ATE performance
SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators
Test and non-test cubes for diagnostic test generation based on merging of test cubes
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles
Cost/Privacy Co-optimization in Smart Energy Grids
Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI
SGRM: Stackelberg Game-Based Resource Management for Edge Computing Systems
SAT-Based Complete Don't-Care Computation for Network Optimization
Binary decision diagram with minimum expected path length
Eliminating False Positives in Crosstalk Noise Analysis
Perspective on Embedded Systems: Challenges, Solutions and Research Priorities
Fan-out of 2 Triangle Shape Spin Wave Logic Gates
PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training
Testing in the year 2020
Active Learning of Abstract System Models from Traces using Model Checking
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Design Automation for Cyber-Physical Production Systems: Lessons Learned from the DeFacto Project
Algorithms for Detailed Placement of Standard Cells
Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Error detection in ternary CAMs using bloom filters
Automatically Realising Embedded Systems from High-Level Functional Models
HePREM: Enabling predictable GPU execution on heterogeneous SoC
REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems
Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement
A Resource-Aware Residual-Based Gaussian Belief Propagation Accelerator Toolflow
A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits
A monitor interconnect and support subsystem for multicore processors
A general approach for highly defect tolerant Parallel Prefix Adder design
Soft delay error analysis in logic circuits
Architectures and modeling of predictable memory controllers for improved system integration
Comparison of GPU Computing Methodologies for Safety-Critical Systems: An Avionics Case Study
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
A novel methodology for designing TSC networks based on the parity bit code
Reliability-driven don't care assignment for logic synthesis
Bus designs for time-probabilistic multicore processors
Event driven data processing architecture
Navigating the Unknown: Uncertainty-Aware Compute-in-Memory Autonomy of Edge Robotics
A Data Analysis Method for Software Performance Prediction
Iterative Abstraction-Based CTL Model Checking
An Integrated Approach for Improving Cache Behavior
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures
Incremental Criticality and Yield Gradients
Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits
In-band Cross-Trigger Event Transmission for Transaction-Based Debug
Verification coverage of embedded multicore applications
The design of sustainable wireless sensor network node using solar energy and phase change memory
Design Of Future Systems
Fault-based attacks on the Bel-T block cipher family
Enabling certification for dynamic partial reconfiguration using a minimal flow
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms
Symbolic Analysis of Nonlinear Analog Circuits
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology
EVT-based worst case delay estimation under process variation
Formal verification of analog circuits in the presence of noise and process variation
Modeling and optimization of hierarchical synchronous circuits
Performance-centric scheduling with task migration for a heterogeneous compute node in the data center
HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search
An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture
Periodic Steady-State Analysis Augmented with Design Equality Constraints
Quantified Synthesis of Reversible Logic