yusuke1997/dblp-id-title huggingface dataset:
Dynamically Reconfigurable Architecture for Image Processor Applications
MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs
Predictive formulae for OPC with applications to lithography-friendly routing
Cellular image processing techniques for VLSI circuit layout validation and routing
Optimal and fast throughput evaluation of CSDF
Characterizing embedded applications for instruction-set extensible processors
Software-based diagnosis for processors
On Computing Exact WCRT for DAG Tasks†
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 4th Design Automation Conference, DAC '67, Los Angeles, California, USA, June 19-22, 1967
Tomorrow's analog: just dead or just different?
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips
On Testing Wave Pipelined Circuits
Efficient Power Estimation for Highly Correlated Input Streams
A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios
Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited
Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
A testing strategy for PLAs
Using simulation to evaluate system performance
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise
Late Breaking Results: Fine-Tuning LLMs for Test Stimuli Generation
CAP: Communication Aware Programming
Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs
Tera-scale computing and interconnect challenges
ACME: advanced counter mode encryption for secure non-volatile memories
An object-oriented, procedural database for VLSI chip planning
Can Short Hypervectors Drive Feature-Rich GNNs? Strengthening the Graph Representation of Hyperdimensional Computing for Memory-efficient GNNs
Deriving a near-optimal power management policy using model-free reinforcement learning and Bayesian classification
Stochastic dominant singular vectors method for variation-aware extraction
WICOP a wire integration computer program
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
Incremental logic synthesis through gate logic structure identification
SuperCopyback: Revisiting Copyback on Modern High-Performance NAND Flash-based SSDs
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience
FF-INT8: Efficient Forward-Forward DNN Training on Edge Devices with INT8 Precision
Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation
Potential-Driven Statistical Ordering of Transformations
CuckoOnsai: An Efficient Memory Authentication Using Amalgam of Cuckoo Filters and Integrity Trees
Specification, Verification and Design of Evolving Automotive Software: Invited
Multilevel Logic Synthesis for Arithmetic Functions
Automatic Sizing of Power/Ground (P/G) Networks in VLSI
Datapath Scheduling for Two-Level Pipelining
Power gating applied to MP-SoCs for standby-mode power management
Challenges and opportunities in electronic textiles modeling and optimization
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together
BIST PLAs, Pass or Fail - A Case Study
Layout-aware synthesis of arithmetic circuits
Enhanced Network Flow Algorithm for Yield Optimization
Two-sided single-detour untangling for bus routing
Leakage-aware intraprogram voltage scaling for embedded processors
NeuroSelect: Learning to Select Clauses in SAT Solvers
AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform Evaluation
Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency
PAS-CIP: An interactive logic design system
Process Independent Constraint Graph Compaction
GRIP: scalable 3D global routing using integer programming
SLIC - Symbolic Layout of Integrated Circuits
High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis
Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism
A digital 3D TCAM accelerator for the inference phase of Random Forest
Temporal Tracing of On-Chip Signals using Timeprints
Efficient on-line testing of FPGAs with provable diagnosabilities
ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading
Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices
VHDL: A Call for Standards
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs
Functional level simulation in FANSIM3 - algorithms, data structures and results
A design system approach to data integrity
Design process analysis: A measurement and analysis technique
RansomBlocker: a Low-Overhead Ransomware-Proof SSD
A new integrated system for PLA testing and verification
Multi-Layer Memory Resiliency
Synthesis of Application-Specific Multiprocessor Architectures
Wire routing by optimizing channel assignment within large apertures
Making DRAM Stronger Against Row Hammering
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis
Towards a natural language interface for CAD
Problem areas and the combination of wall-units to satisfy room relation specification between rooms
Reduction techniques for synchronous dataflow graphs
Efficient Code Generation for Data-Intensive Simulink Models via Redundancy Elimination
PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor
CAD for military systems, an essential link to LSI, VLSI and VHSIC technology
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
The evolution of an integrated data base
Highly efficient entropy extraction for true random number generators on FPGAs
Invited - Cross-layer modeling and optimization for electromigration induced reliability
The relational/network Hybrid data model for Design Automation Databases
Cost of Silicon Viewed from VLSI Design Perspective
Mask Shop Information System
Optimizing code parallelization through a constraint network based approach
Introduction to silicon compilation
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping
EDA challenges and options: investing for the future
Statistical memristor modeling and case study in neuromorphic computing
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA
Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA
A Technology-adaptive Allocation of Functional Units and Connections
A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
S-CDA: A Smart Cloud Disk Allocation Approach in Cloud Block Storage System
The design and programming of a display interface system integrating multi-access and satellite computers
Module Placement for Analog Layout Using the Sequence-Pair Representation
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit
Invited: Security Beyond Bulk Silicon: Opportunities and Challenges of Emerging Devices
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications
A direct finite element solver of linear complexity for large-scale 3-D circuit extraction in multiple dielectrics
Physics matters: statistical aging prediction under trapping/detrapping
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory
The IC Module Compiler, a VLSI system design aid
A placement capability based on partitioning
Bit-Level Analysis of an SRT Divider Circuit
Debugging HW/SW interface for MPSoC: video encoder system design case study
Design Process Model in the Yorktown Silicon Compiler
AWEsim: Asymptotic Waveform Evaluation for Timing Analysis
MyML: User-Driven Machine Learning
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration
A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms
An efficient and effective analytical placer for FPGAs
A hybrid and adaptive model for predicting register file and SRAM power using a reference design
Logic Restructuring with Preserved Logic Blocks
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies
Layout-dependent-effects-aware analytical analog placement
Influence of compiler optimizations on system power
Statistical static timing analysis: how simple can we get?
PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly
EASE: A Design Support Environment for the HDDL ELLA
EDA meets.COM (panel session): how E-services will change the EDA business model
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs
The future of multiprocessor systems-on-chips
DEX-Design Automation system cooperative development
A computerized management control system
BoxRouter: a new global router based on box expansion and progressive ILP
Can BDDs compete with SAT solvers on bounded model checking?
Automatic Generation of Behavioral Models from Switch-Level Descriptions
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification
NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI
Hierarchical approach to exact symbolic analysis of large analog circuits
Proceedings of the 12th Design Automation Conference, DAC '75, Boston, Massachusetts, USA, June 23-25, 1975
Efficient multi-objective synthesis for microwave components based on computational intelligence techniques
Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach
Synchronous path analysis in MOS circuit simulator
Early verification of prototype tooling for IC designs
NAAS: Neural Accelerator Architecture Search
Design automation trends for VLSI in the 1980s (Position Statement)
Adaptive compressed sensing architecture in wireless brain-computer interface
Holistic multi-resource allocation for multicore real-time virtualization
Interleaved multi-bank scratchpad memories: a probabilistic description of access conflicts
Hole analysis for functional coverage data
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy
ECL: A Specification Environment for System-Level Design
Network on chip design and optimization using specialized influence models
Sacha: the Stanford carbon nanotube controlled handshaking robot
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search
An introduction to the N. mPc design environment
X-SAT: An Efficient Circuit-Based SAT Solver
Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat Locality
Software Approaches for In-time Resilience
Privacy preserving localization for smart automotive systems
Engineering Data Management System (EDMS) for computer aided design of digital computers
CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator
Analytical power/timing optimization technique for digital system
QB-trees: towards an optimal topological representation and its applications to analog layout designs
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning
An automated method for producing diagnostic programs
Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system
The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Statistics for Parallelism and Abstraction Level in Digital Simulation
Efficient computation of ECO patch functions
Extending the transaction level modeling approach for fast communication architecture exploration
Scalable Optimal Layout Synthesis for NISQ Quantum Processors
Representing Conditional Branches for High-Level Synthesis Applications
An automated system for testing LSI memory chips
Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors
Power Optimization of Variable Voltage Core-Based Systems
A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies
RELATE: Relationship layout technique
Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard Cells
Architecture and Design of the MARS Hardware Accelerator
Performance-Driven Interconnect Design Based on Distributed RC Delay Model
Design Considerations and Tools for Low-voltage Digital System Design
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy
A heuristic algorithm for PLA block folding
Artificial intelligence in automated design
Validating the Intel Pentium 4 Microprocessor
Channel Density Reduction by Routing Over The Cells
Toward Formalizing a Validation Methodology Using Simulation Coverage
On Path Selection in Combinational Logic Circuits
Extensive evaluation of programming models and ISAs impact on multicore soft error reliability
Interactive on-line computing in structural design
An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits
A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting
Input-Aware Dynamic Timestep Spiking Neural Networks for Efficient In-Memory Computing
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control
CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays
A Fault-Tolerant Neural Network Architecture
SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory
A Test Synthesis Approach to Reducing BALLAST DFT Overhead
Invariance-based concurrent error detection for advanced encryption standard
Ultimate low cost analog BIST
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs
A timing engine inspired graph neural network model for pre-routing slack prediction
Hexagons are the bestagons: design automation for silicon dangling bond logic
Technical Visualizations in VLSI Design
CAD Implications of New Interconnect Technologies
Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge
An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based Microfluidic Biochips
Post-Layout Logic Restructuring for Performance Optimization
Design automation for mask programmable fabrics
Engineering Change in a Non-Deterministic FSM Setting
Sequential equivalence checking of clock-gated circuits
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
SAPredictor: a simple and accurate self-adaptive predictor for hierarchical hybrid memory system
Overview of the MPSoC design challenge
A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Functional level simulation at Raytheon
DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis
Automatic placement algorithms for high packing density V L S I
Post-layout logic optimization of domino circuits
CAF: A computer-assisted floorplanning tool
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique
LiB: A Cell Layout Generator
A statistical simulation method for reliability analysis of SRAM core-cells
CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic Hardware
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
A progressive-ILP based routing algorithm for cross-referencing biochips
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs
Transistor Sizing in CMOS Circuits
Reliability aware power management for dual-processor real-time embedded systems
DFM: where's the proof of value?
Leading-edge and future design challenges - is the classical EDA ready?
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems
Defining coverage views to improve functional coverage analysis
Efficient Circuits for Quantum Search over 2D Square Lattice Architecture
Just Like the Real Thing: Fast Weak Simulation of Quantum Computation
The SLIDE simulator: A facility for the design and analysis of computer interconnections
An efficient layout decomposition approach for triple patterning lithography
Algorithms for automatic transistor sizing in CMOS digital circuits
Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help?
The autonomic operating system research project: achievements and future directions
Fake Node-Based Perception Poisoning Attacks against Federated Object Detection Learning in Mobile Computing Networks
SEDA - Single Exact Dual Approximate Adders for Approximate Processors
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits
Symbolic simulation for functional verification with ADLIB and SDL
General AC Constraint Transformation for Analog ICs
Concurrent Wire Spreading, Widening, and Filling
Standard Cell Placement Using Simulated Sintering
Abstraction of assembler programs for symbolic worst case execution time analysis
Automatic Layout Procedures for Serial Routing Devices
Adaptive window-based sensor attack detection for cyber-physical systems
Minimization for LED-backlit TFT-LCDs
ECR: a low complexity generalized error cancellation rewiring scheme
"A partitioning technique for LSI chips including a bunching algorithm"
An Evolution-Based Approach to Partitioning ASIC Systems
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic
Self-Resetting Latches for Asynchronous Micro-Pipelines
Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial Networks
Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cells
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel)
Performance-impact limited area fill synthesis
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes
Obstacle-avoiding open-net connector with precise shortest distance estimation
Authenticated Call Stack
Improving the Accuracy of Circuit Activity Measurement
Implicit permutation enumeration networks and binary decision diagrams reordering
Elimination of Dynamic hazards by Factoring
Distributed Resonant clOCK grid Synthesis (ROCKS)
System design methodologies for a wireless security processing platform
MILD - A cell-based layout system for MOS-LSI
SCOAP: Sandia controllability/observability analysis program
Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
Design tools for artificial nervous systems
Pursuing more effective graph spectral sparsifiers via approximate trace reduction
SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits
The autopunch system or design automation comes to the sheet metal shop
High-Performance FPGA-based Accelerator for Bayesian Neural Networks
Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets
Neurogenesis Dynamics-inspired Spiking Neural Network Training Acceleration
Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power Implementation
Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis
Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation
An Information Model of Time
HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAs
An interactive electrical graph extractor
Minimizing write amplification to enhance lifetime of large-page flash-memory storage devices
The engineering design environment
The undetectable and unprovable hardware trojan horse
GNN-based concentration prediction for random microfluidic mixers
A test pattern ordering algorithm for diagnosis with truncated fail data
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
ADL: An algorithmic design language for integrated circuit synthesis
Maintaining consistency between systemC and RTL system designs
Data Mining In EDA - Basic Principles, Promises, and Constraints
IMPRES: integrated monitoring for processor reliability and security
SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning model
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators
An interactive test data system for LSI production testing
A reuse-aware prefetching scheme for scratchpad memory
Invited: Accelerating Genome Analysis via Algorithm-Architecture Co-Design
Lightning Talk: Scaling Up Quantum Compilation - Challenges and Opportunities
CGPA: Coarse-Grained Pipelined Accelerators
HOPLA-PLA optimization and synthesis
An extensive logic simulation method of very large scale computer design
Analyzing Hardware Based Malware Detectors
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses
CMOS Stuck-open Fault Detection Using Single Test Patterns
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
IC Design in High-Cost Nanometer-Technologies Era
Memory-Efficient and Real-Time SPAD-based dToF Depth Sensor with Spatial and Statistical Correlation
Handling special constructs in symbolic simulation
Technology-Dependent Transformations for Low-Power Synthesis
Performance and power modeling in a multi-programmed multi-core environment
Invited - Things, trouble, trust: on building trust in IoT systems
Implicit and Incremental Computation of Primes and Essential Primes of Boolean Functions
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory
TA-FTA: transition-aware functional timing analysis with a four-valued encoding
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring
Graphic update of automated logic diagrams
Boolean Matching of Sequential Elements
OTPlace-Vias: A Novel Optimal Transport Based Method for High Density Vias Placement in 3D Circuits
CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUs
High effective-resolution built-in jitter characterization with quantization noise shaping
Adversarial Attack against Modeling Attack on PUFs