yusuke1997/dblp-id-title huggingface dataset:
C-testable systolic arrays
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks
Adversarial Data Poisoning Attack on Quantum Machine Learning in the NISQ Era
Sustainable multi-core architecture with on-chip wireless links
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline
Scalable Hardware Accelerator for Mini-Batch Gradient Descent
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
Machine Learning for Intrusion Detection: Stream Classification Guided by Clustering for Sustainable Security in IoT
Synthetic biology: from modules to systems
Performance-Aware Resource Management of Multi-Threaded Applications on Many-Core Systems
A Hardware Prototype of an MRAM-based Stochastic Computing System
A New CMOS Tunable Transconductor Dedicated to VHF Continuous-Time Filters
A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction
A novel and improved design of a ternary CNTFET-based cell
A new approach to timing driven partitioning of combinational logic
A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects
LoRAFusion: A Crossbar-aware Multi-task Adaption Framework via Efficient Fusion of Pretrained LoRA Modules
Challenges in integrated CMOS transceivers for short distance wireless
Pairwise decomposition of toffoli gates in a quantum circuit
Reducing verification overhead with RTL slicing
PerFT-N: Low-overhead Permanent Fault-Tolerance Mechanism for Neural Processing Units
Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing
Optimization using implicit techniques for industrial designs
Rapid Prototyping for Fuzzy Systems
A Dynamically Reconfigurable RF NoC for Many-Core
CASH: Criticality-Aware Split Hybrid L1 Data Cache
Timing-driven N-way decomposition
Flip-Break: Breaking Flip-flop-based Logic Locking in Sequential Circuits
A Systolic SNN Inference Accelerator and its Co-optimized Software Framework
A fast simulation approach for inductive effects of VLSI interconnects
Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
Jump Search: A Fast Technique for the Synthesis of Approximate Circuits
Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization
Statistical gate delay calculation with crosstalk alignment consideration
Logic Synthesis for Testability
Clustering based acyclic multi-way partitioning
A Distributed Parallel Random Walk Algorithm for Large-Scale Capacitance Extraction and Simulation
Hardware-assisted dynamic power and thermal management in multi-core SoCs
Resource-constrained timing-driven link insertion for critical delay reduction
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models
DigitalPIM: Digital-based Processing In-Memory for Big Data Acceleration
Transition-activity aware design of reduction-stages for parallel multipliers
Routability Prediction for Hierarchical FPGAs
Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCs
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field
A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification
Share memory aware scheduler: balancing performance and fairness
Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack
Efficient Process-in-Memory Architecture Design for Unsupervised GAN-based Deep Learning using ReRAM
Design techniques to improve the device write margin for MRAM-based cache memory
Parallel algorithms for FPGA placement
Efficient method to compute minimum decision chains of Boolean functions
Performance and energy efficient cache migrationapproach for thermal management in embedded systems
Beyond 3G wireless communication system prototype
Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system
Parallel Saturating Fractional Arithmetic Units
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis
Dense layouts for series-parallel circuits
Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources
Resonant Tunneling Transistors for Threshold Logic Circuit Applications
ML-Fusion: Determining Memory Levels for Data Reuse Between DNN Layers
Low swing dual threshold voltage domino logic
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack
Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash Memory
On the Characterization of Multi-Point Nets in Electronic Designs
Operation limits in RTD-based ternary quantizers
TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique
A memory mapping approach for network and controller optimization in parallel interleaver architectures
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks
Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping
Hierarchical model order reduction for signal-integrity interconnect synthesis
An Effective Voltage-drop Aware Analytical Placement Approach
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects
An Effective TSV Self-Repair Scheme for 3D-Stacked ICs
Crash Skipping: A Minimal-Cost Framework for Efficient Error Recovery in Approximate Computing Environments
TinyML Based Biometric Authentication Using PPG Signals for Edge Devices
Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing
Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors
Disruptive technologies and neurally-inspired architectures
A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File
FIFO power optimization for on-chip networks
Hardware architecture and FPGA implementation of a type-2 fuzzy system
Two-prime RSA immune cryptosystem and its FPGA implementation
High speed differential pulse-width control loop based on frequency-to-voltage converters
Efficient Wireless Power Transfer for Heterogeneous Adaptive IoT Systems
A Provably Good Moat Routing Algorithm
Automatic Implementation of Secure Silicon
Perception-guided power minimization for color sequential displays
Varicap threshold logic
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors
VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract
A ubiquitous processor embedded with progressive cipher pipelines
Design of self correcting radiation hardened digital circuits using decoupled ground bus
Modeling and estimating leakage current in series-parallel CMOS networks
Variation tolerant 9T SRAM cell design
Transformers for Secure Hardware Systems: Applications, Challenges, and Outlook
A Reconfigurable and Accurate Circuit-Level Substrate for DRAM Design and Analysis
Fast Consistency Auditing for Massive Industrial Data in Untrusted Cloud Services
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip
Optimal sleep transistor synthesis under timing and area constraints
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
Exploiting multiple functionality for nano-scale reconfigurable systems
Quantitatively Assessing the Cyber-to-Physical Risk of Industrial Cyber-Physical Systems
Analog Circuit Implementation of LIF and STDP Models for Spiking Neural Networks
Resource and delay efficient matrix multiplication using newer FPGA devices
CMOS Transistor Sizing for Minimization of Energy-Delay Product
DX-compactor: distributed X-compaction for SoCs
Secret Sharing and Multi-user Authentication: From Visual Cryptography to RRAM Circuits
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy
Modeling the vertical constraints in VLSI channel routing
STV-Cache: a leakage energy-efficient architecture for data caches
Titanus: Enabling KV Cache Pruning and Quantization On-the-Fly for LLM Acceleration
A globally asynchronous locally dynamic system for ASICs and SoCs
Learning Cache Coherence Traffic for NoC Routing Design
A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints
An energy-efficient CMOS line driver using adiabatic switching
Hardware acceleration of retinal blood vasculature segmentation
Multi-GHz SiGe design methodologies for reconfigurable computing
Boolean satisfiability on a graphics processor
Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications
Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories
Low Voltage Clock Tree Synthesis with Local Gate Clusters
Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM
Neuromorphic Computing based on Resistive RAM
Fine-Grain Program Snippets Generator for Mobile Core Design
Boolean Function Representation Using Parallel-Access Diagrams
Total leakage optimization strategies for multi-level caches
I-cache multi-banking and vertical interleaving
Measuring routing congestion for multi-layer global routing
A new scheme to compute variable orders for binary decision diagrams
An analysis of the robustness of CMOS delay elements
A Low-Power High-Performance Embedded SRAM Macrocell
A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots
Testability profile estimation of VLSI circuits from fault coverage
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device
Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing
A mask double patterning technique using litho simulation by wavelet transform
AutoRAC: Automated Processing-in-Memory Accelerator Design for Recommender Systems
Tool integration using the web-services approach
Cost-Effective Value Predictor for ILP processors through Design Space Exploration
A Board and Projects for an FPGA/Microcontroller-Based Embedded Systems Lab
Novel Simple Models Of Cml Propagation Delay
Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays
Using reiterative LFSR based X-masking to increase output compression in presence of unknowns
Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures
CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories
Low power nanoscale buffer management for network on chip routers
D-GCN: A Dynamic Pruning Accelerator for Deep Graph Convolutional Networks with Hybrid Dataflow
HMC-TRAN: A Tensor-core Inspired Hierarchical Model Compression for Transformer-based DNNs on GPU
Monolithic 8x8 SiPM with 4-bit Current-Mode Flash ADC with Tunable Dynamic Range
Survey of Emerging Technology Based Physical Unclonable Funtions
Would Magnonic Circuits Outperform CMOS Counterparts?
SFC-TRNG: A Stable Fast and Compact True Random Number Generator based on Magnetic Tunnel Junction
Quantum Transfer Learning to Boost Dementia Detection
An Overview of In-memory Processing with Emerging Non-volatile Memory for Data-intensive Applications
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic
Transport in Split Gate MOS Quantum Dot Structures
MinMux: a new approach for global minimization of multiplexers in interconnect synthesis
Timing-Driven Application Mapping for Continuous-Flow Microfluidic Biochips
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
Reduced Overhead Gate Level Logic Encryption
Power gating topologies in TSV based 3D integrated circuits
SMECY: smart multi-core embedded systems
SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash Memory
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation
Ordered escape routing via routability-driven pin assignment
Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment
A 2 Gb/s balanced AES crypto-chip implementation
A practical approach for monitoring analog circuits
A local clocking approach for self-timed datapath designs
A geometric programming aided knowledge based approach for analog circuit synthesis and sizing
Effect of TSV fabrication technology on power distribution in 3D ICs
OPRON: a new approach to planar OTC routing
High throughput architecture for H.264/AVC forward transforms block
A delay measurement method using a shrinking clock signal
GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Timing, energy, and thermal performance of three-dimensional integrated circuits
Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Design of Approximate Logarithmic Multipliers
Pseudo-random behavioral ATPG
High performance technique for database applicationsusing a hybrid GPU/CPU platform
SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the Hardware
A practical CAD technique for reducing power/ground noise in DSM circuits
Defense Systems and IoT: Security Issues in an Era of Distributed Command and Control
A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance
Step-by-Step Tutoring Support for Student Success in Circuit Analysis Courses
Resilient AES Against Side-Channel Attack Using All-Spin Logic
A high-level register optimization technique for minimizing leakage and dynamic power
A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications
Characteristics of MS-CMOS logic in sub-32nm technologies
A hardware-efficient architecture for embedded real-time cascaded support vector machines classification
Low-Power Implementation of Discrete Cosine Transform
VLSI systems for neurocomputing and health informatics
Maximum Current Estimation in Programmable Logic Arrays
Efficient folded VLSI architectures for linear prediction error filters
Design challenges in high performance three-dimensional circuits
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard
Transforming disfigured and disoriented areas into routable switchboxes
Intracortical wireless microsystems for biosensing and neurostimulation
Optimal Topology-Aware PV Panel Floorplanning with Hybrid Orientation
Towards systolic hardware acceleration for local complexity analysis of massive genomic data
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems
TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects
LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks
An Enhanced Analytical Electrical Masking Model for Multiple Event Transients
Redundancy in SAR ADCs
A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers
A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates
GPU implementation of a scalable non-linear congruential generator for cryptography applications
An asynchronous fpga logic cell implementation
Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS
EDA Challenges for Memristor-Crossbar based Neuromorphic Computing
A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework
Power distribution paths in 3-D ICS
Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive Analysis
Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs
Selective-run built-in self-test using an embedded processor
A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers
Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment
Study of leakage current mechanisms in ballistic deflection transistors
Energy-Efficient Quantization-Aware Training with Dynamic Bit-Width Optimization
MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router
Probabilistic maximum error modeling for unreliable logic circuits
A continuous time markov decision process based on-chip buffer allocation methodology
LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration
Loop-List Scheduling for Heterogeneous Functional Units
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I cell SRAM Using FinFET
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points
A Differential Model Approach To Analog Design Automation
Zero overhead watermarking technique for FPGA designs
Applying Hopfield network to find the minimum cost coverage of a Boolean function
Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018
Low-Power Manycore Accelerator for Personalized Biomedical Applications
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms
Fence-Region-Aware Mixed-Height Standard Cell Legalization
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
NBTI-aware flip-flop characterization and design
Design of an RNS reverse converter for a new five-moduli special set
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm
Area-Efficient Area Pad Design for High Pin-Count Chips
Scalable Flip-Flop Clustering Using Divide and Conquer For Capacitated K-Means
Can Stochastic Computing Truly Tolerate Bit Flips?
On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule
Reduced-latency LLR-based SC List Decoder for Polar Codes
Machine Learning Based Acceleration Method for Ordered Escape Routing
Improved performance and yield with chip master planning design methodology
A table-based method for single-pass cache optimization
NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions
Enhanced clustered voltage scaling for low power
Linear Transformations and Exact Minimization of BDDs
Term ordering problem on MDG
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays
Security-by-Design For Smart Electronics
A wave-pipelined router architecture using ternary associative memory
A soft computing approach to hardware software codesign
SenGuard: A Novel Processing In-Sensor Method for Privacy-Enhanced Smart Imaging
Timing-constrained replacement using spare cells for design changes
A performance enhancing hybrid locally mesh globally star NoC topology
Buffer sizing for minimum energy-delay product by using an approximating polynomial
Multi-level fault modeling for transaction-level specifications
Multi-task Scheduling for PIM-based Heterogeneous Computing System
Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic
Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs
Dynamic Computation Migration at the Edge: Is There an Optimal Choice?
Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits
A Tile-based Interconnect Model for FPGA Architecture Exploration
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits
State persistence: a property for guiding test generation
Breaching the Gap: Modelling SRAM-PUFs via Side-Channel Signatures
An analytical model for the upper bound on temperature differences on a chip
Optimizing cyclic data-flow graphs via associativity
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node
Session details: Session 7B: Microelectronic Systems Education
High-level modeling of power consumption in active linear analog circuits
Circuit design of a novel adaptable and reliable L1 data cache
VAER: Via-Aware Escape Routing for Chiplet Interconnection
An improved algorithm for the generalized min-cut partitioning problem
An Oracle-Less Machine-Learning Attack against Lookup-Table-based Logic Locking
Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique
Recent Developments in Performance Driven Steiner Routing: An Overview
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips
Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm
Session details: Session 1B: Emerging Computing and Post-CMOS Technologies
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees
Early stage power management for 3D FPGAs considering hierarchical routing resources
Assert-O: Context-based Assertion Optimization using LLMs
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans
A new algorithm for signal flow determination in CMOS VLSI
Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
A 45.6μ 2 13.4μw 7.1v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS
High-speed architectures for parallel long BCH encoders
Speeding up symbolic model checking by accelerating dynamic variable reordering
On the Theoretical Analysis of Memristor based True Random Number Generator
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits
Novel Approximate Multiplier Designs for Edge Detection Application
On finding the minimum test set of a BDD-based circuit
Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping
An error tolerant CAM with nand match-line organization
GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure Silicon
A Quantitative Study of the Benefits of Area-I/O in FPGAs
RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs
Error Recovery Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
Design and analysis of efficient application-specific on-line page replacement techniques
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems
Optimal partitioning of globally asychronous locally synchronous processor arrays
Closing the Gap between Quantum Algorithms and Machines with Hardware-Software Co-Design
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs
Level shifter planning for timing constrained multi-voltage SoC floorplanning
Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security