yusuke1997/dblp-id-title huggingface dataset:
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data
An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System
CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance
Denotational Semantics of a Behavioral Subset of VHDL
Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Mixed-criticality scheduling with memory bandwidth regulation
Leveraging dominators for preprocessing QBF
GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems
On-line functionally untestable fault identification in embedded processor cores
Robust Reconfigurable Scan Networks
SAT-based redundancy removal
Formal analysis of sporadic overload in real-time systems
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Runtime interval optimization and dependable performance for application-level checkpointing
Surviving Transient Power Failures with SRAM Data Retention
HypoEnergy. Hybrid supercapacitor-battery power-supply optimization for Energy efficiency
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects
Architecture driven partitioning
Towards SEU Fault Propagation Prediction with Spatio-Temporal Graph Convolutional Networks
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating
Access pattern based local memory customization for low power embedded systems
Gain scheduled control for nonlinear power management in CMPs
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs
Ensuring Data Freshness for In-Storage Computing with Cooperative Buffer Manager
A high efficiency hardware trojan detection technique based on fast SEM imaging
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
Towards Exploring the Potential of Alternative Quantum Computing Architectures
Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks
HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler
Modeling static-order schedules in synchronous dataflow graphs
Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits
A cyberphysical synthesis approach for error recovery in digital microfluidic biochips
Faster Optimal Single-Row Placement with Fixed Ordering
Automated Circuit Approximation Method Driven by Data Distribution
Delay Fault Testing of Core-Based Systems-on-a-Chi
Location is All You Need: Efficient Lithographic Hotspot Detection Using Only Polygon Locations
Finding a Common Fault Response for Diagnosis during Silicon Debug
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system
MobiXen: Porting Xen on Android devices for mobile virtualization
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity
$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging
A Novel Approach for EMI Design of Power Electronics
A Signature Test Framework for Rapid Production Testing of RF Circuits
CUFFS: An instruction count based architectural framework for security of MPSoCs
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis
Magnetic memories: From DRAM replacement to ultra low power logic chips
Robust neuromorphic computing in the presence of process variation
Correct runtime operation for NoCs through adaptive-region protection
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
A hardware implementation of a radial basis function neural network using stochastic logic
Object-Oriented Modelling of Parallel Hardware Systems
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping
An integrated platform for advanced diagnostics
New Schemes for Self-Testing RAM
FLInt: Exploiting Floating Point Enabled Integer Arithmetic for Efficient Random Forest Inference
Capturing vulnerability variations for register files
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
Embedded HW/SW platform for on-the-fly testing of true random number generators
MU-RMW: Minimizing Unnecessary RMW Operations in the Embedded Flash with SMR Disk
SimGen: Simulation Pattern Generation for Efficient Equivalence Checking
Coupling Neural Networks and Physics Equations For Li-Ion Battery State-of-Charge Prediction
An Adaptive Dictionary Encoding Scheme for SOC Data Buses
Sequential Circuit Test Generation Using Decision Diagram Models
Exploring SW Performance Using SoC Transaction-Level Modeling
Data Subsetting: A Data-Centric Approach to Approximate Computing
Transaction Based Design: Another Buzzword or the Solution to a Design Problem?
Optimizing power-accuracy trade-off in approximate adders
Next generation architectures can dramatically reduce the 4G deployment cycle
Cross-layer optimized placement and routing for FPGA soft error mitigation
Modeling Noise Transfer Characteristic of Dynamic Logic Gates
Register-Constrained Address Computation in DSP Programs
A scaled random walk solver for fast power grid analysis
Multi-Tenant FPGA-based Reconfigurable Systems: Attacks and Defenses
Cross-architectural design space exploration tool for reconfigurable processors
Meeting the Embedded Design Needs of Automotive Applications
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs
CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal Selection
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing
Toward optimized code generation through model-based optimization
Time Series-based Driving Event Recognition for Two Wheelers
On the Generation of Multiplexer Circuits for Pass Transistor Logic
A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation
A mixed-signal verification kit for verification of analogue-digital circuits
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems
Automatic extraction of assertions from execution traces of behavioural models
ArchOn: Architecture-open Resource-driven Cross-layer Modelling Framework
Digital statistical analysis using VHDL
A link arbitration scheme for quality of service in a latency-optimized network-on-chip
Constraint satisfaction for storage files with Fifos or stacks during scheduling
STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation
Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based Perception
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs
Power minimization for data center with guaranteed QoS
Kernel Scheduling in Reconfigurable Computing
Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI
Using synchronization stalls in power-aware accelerators
Lightweight Anonymous Routing in NoC based SoCs
STAX: statistical crosstalk target set compaction
OpenMFDA: Microfluidic Design Automation in Three Dimensions
TLS-Level Security for Low Power Industrial IoT Network Infrastructures
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006
Exploiting Kernel Compression on BNNs
HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution
P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator
An Imitation Augmented Reinforcement Learning Framework for CGRA Design Space Exploration
Optimal Margin Computation for At-Speed Test
NN compactor: Minimizing memory and logic resources for small neural networks
An Object Oriented Design Method for Reconfigurable Computing Systems
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions
Runtime reconfiguration of custom instructions for real-time embedded systems
BOSON -1 : Understanding and Enabling Physically-Robust Photonic Inverse Design with Adaptive Variation-Aware Subspace Optimization
On-line prediction of NBTI-induced aging rates
Integration, Verification and Layout of a Complex Multimedia SOC
ARTmine: Automatic Association Rule Mining with Temporal Behavior for Hardware Verification
WCET-Centric dynamic instruction cache locking
SiC Processors for Extreme High- Temperature Venus Surface Exploration
Techniques for Reducing Read Latency of Core Bus Wrappers
Time-predictable execution of multithreaded applications on multicore systems
Double-sampling single-loop sigma-delta modulator topologies for broadband applications
Hardware Trojans in eNVM Neuromorphic Devices
Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations
Computing a language-based guarantee for timing properties of cyber-physical systems
An effective approach to automatic functional processor test generation for small-delay faults
An Efficient Reuse System for Digital Circuit Design
Energy-efficient multicore chip design through cross-layer approach
Non-gaussian statistical interconnect timing analysis
A multi-objective decision-theoretic exploration algorithm for platform-based design
CLAIRE: Composable Chiplet Libraries for AI Inference
Formally Verified Redundancy Removal
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
PowerProbe: Run-time power modeling through automatic RTL instrumentation
Determining the minimal number of lines for large reversible circuits
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications
ApproxQA: A unified quality assurance framework for approximate computing
An error-correcting unordered code and hardware support for robust asynchronous global communication
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache
Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories
Leakage and temperature aware server control for improving energy efficiency in data centers
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach
A Model of Computation for Continuous-Time ?-? Modulators
POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems
Power-efficient load-balancing on heterogeneous computing platforms
On-the-fly verification of memory consistency with concurrent relaxed scoreboards
Analysis and design of sub-harmonically injection locked oscillators
Composing heterogeneous components for system-wide performance analysis
Speeding up SystemC simulation through process splitting
Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications
Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor
QBf-based boolean function bi-decomposition
SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applications
Hardware/Software Co-Analysis for Worst Case Execution Time Bounds
An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips
DAOP: Data-Aware Offloading and Predictive Pre-Calculation for Efficient MoE Inference
Using timing analysis for the design of future switched based Ethernet automotive networks
Evaluating matrix representations for error-tolerant computing
GLEAM: Graph-Based Learning Through Efficient Aggregation in Memory
Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?
Statistical modeling with the virtual source MOSFET model
HCFTL: A Locality-Aware Page-Level Flash Translation Layer
HEROIC: Homomorphically EncRypted One Instruction Computer
Worst-case temperature analysis for real-time systems
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore's law?
Using contract-based component specifications for virtual integration testing and architecture design
Layout-Driven High Level Synthesis for FPGA Based Architectures
Opportunities and Challenges in Building Silicon Products in 65nm and Beyond
Mitigation of sense amplifier degradation using input switching
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines
A survey of multi-source energy harvesting systems
EXPERT: Effective and flexible error protection by redundant multithreading
IR-drop analysis of graphene-based power distribution networks
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions
Keep it slow and in time: Online DVFS with hard real-time workloads
Power Gating for Ultra-low Leakage: Physics, Design, and Analysis
Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI
Lifetime Modeling of a Sensor Network
Maze Routing with Buffer Insertion under Transition Time Constraints
Towards the Implementation and Evaluation of Semi-Partitioned Multi-Core Scheduling
On demand dependent deactivation of automotive ECUs
Panel 6.8: The challenges of heterogeneous multicore debug
Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing
Attacking ReRAM-based Architectures using Repeated Writes
Microarchitecture Development via Metropolis Successive Platform Refinement
Compilation of stream programs for multicore processors that incorporate scratchpad memories
Fledge: Flexible Edge Platforms Enabled by In-memory Computing
Algebraic fault analysis of SHA-3
A sensor fusion algorithm for an integrated angular position estimation with inertial measurement units
Multi-objective Tabu Search based topology generation technique for application-specific Network-on-Chip architectures
Clustering based fast clock scheduling for light clock-tree
Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns
Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system
Formal verification of taint-propagation security properties in a commercial SoC design
Simulation method to extract characteristics for digital wireless communication systems
C for System Level Design
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique
Why Systems-on-Chip Needs More UML like a Hole in the Head
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation
Memory fault diagnosis by syndrome compression
Network Synthesis for Industry 4.0
In-memory computing using paths-based logic and heterogeneous components
Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design
SCADPA: Side-channel assisted differential-plaintext attack on bit permutation based ciphers
FORM: A Frame-Oriented Representation Method for Digital Telecommunication System Design
A Stakeholder Analysis of Operational Design Domains of Automated Driving Systems
A System for Modelling and Proving Circuits
On software development to support statistical simulation of analogue circuits
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Test generation based diagnosis of device parameters for analog circuits
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Software Bit-Slicing: A Technique for Improving Simulation Performance
Dynamic Per-Flow Queues for TSN Switches
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
Side-channel attacks from static power: when should we care?
Selection of a fault model for fault diagnosis based on unique responses
Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits
Pipe-BD: Pipelined Parallel Blockwise Distillation
A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation
Synthesis of on-chip control circuits for mVLSI biochips
Analysis of Quantization Across DNN Accelerator Architecture Paradigms
Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible?
Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization
Activity clustering for leakage management in SPMs
Motivating Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Towards AQFP-Capable Physical Design Automation
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
Space-efficient FPGA-accelerated collision detection for virtual prototyping
Batteries and battery management systems for electric vehicles
AGDM: An Adaptive Granularity Data Migration Strategy for Hybrid Memory Systems
Energy analysis methods and tools for modelling and Optimizing monitoring tyre systems
LLM-Based Processor Verification: A Case Study for Neuronnorphic Processor
Dynamic write limited minimum operating voltage for nanoscale SRAMs
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation
A pulsed-index technique for single-channel, low-power, dynamic signaling
Computing synchronizer failure probabilities
A Proposal for Transaction-Level Verification with Component Wrapper Language
Resource prediction for media stream decoding
Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme
Certainty or Intelligence: Pick One!
Signature indexing of design layouts for hotspot detection
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits
Bordersearch: an adaptive identification of failure regions
Bit parallel test pattern generation for path delay faults
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices
The ultra low-power wiseNET system
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic
Revealing side-channel issues of complex circuits by enhanced leakage models
A precise event-driven circuit simulator based on predicted fan-in voltages
Efficient DC Fault Simulation of Nonlinear Analog Circuits
Scan Chain Organization for Embedded Diagnosis
TARN: Trust Aware Routing to Enhance Security in 3D Network-on-Chips
Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
Tightening BDD-based approximate reachability with SAT-based clause generalization ∗
Efficient RC power grid verification using node elimination
Comparison of multi-purpose cores of Keccak and AES
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network
NoC-MPU: A secure architecture for flexible co-hosting on shared memory MPSoCs
A machine learning approach for medication adherence monitoring using body-worn sensors
AIX: A high performance and energy efficient inference accelerator on FPGA for a DNN-based commercial speech recognition
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors
fbPDR: In-depth combination of forward and backward analysis in Property Directed Reachability
Global Placement with Deep Learning-Enabled Explicit Routability Optimization
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems
System-level process variability analysis and mitigation for 3D MPSoCs
Efficient soft error vulnerability estimation of complex designs
An integrated approach for managing the lifetime of flash-based SSDs
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling
Know Your Neighbor: Physically Locating Xeon Processor Cores on the Core Tile Grid
A novel self-healing methodology for RF Amplifier circuits based on oscillation principles
Spanning Tree-based State Encoding for Low Power Dissipation
Minimum-energy LDPC decoder for real-time mobile application
TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction
A Systematic Removal of Minimum Implant Area Violations under Timing Constraint
Bias by Design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic Optimization
High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors
Automated driving safety - The art of conscious risk taking - minimum lateral distances to pedestrians
Computational Intelligence Characterization Method of Semiconductor Device
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect
Head-mounted sensors and wearable computing for automatic tunnel vision assessment
Bounding deadline misses in weakly-hard real-time systems with task dependencies
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM
Optimizing BDDs for time-series dataset manipulation
On-Chip Inductance Models: 3D or Not 3D?
Storage Class Memory with Computing Row Buffer: A Design Space Exploration
Correct High-Level Synthesis: a Formal Perspective
Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems
A Camera with Brain - Embedding Machine Learning in 3D Sensors
Hardware Acceleration of CNN with One-Hot Quantization of Weights and Activations
PATRON: A Pragmatic Approach for Encoding Laser Fault Injection Resistant FSMs
Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs
Exploiting clock skew scheduling for FPGA
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor
Separate compilation and execution of imperative synchronous modules
Accurate prediction of smartphones' skin temperature by considering exothermic components
Systematic stability-analysis method for analog circuits