yusuke1997/dblp-id-title huggingface dataset:
An adaptive super-exponential deflation algorithm for blind deconvolution of MIMO systems using the matrix pseudo-inversion lemma
In-Vivo Dehydration Sensing in Transgenic Tobacco Plants using an Integrated Electrochemical Chip
2-D and 3-D successive packing interleaving techniques and their applications to image and video data hiding
A broadband upconverter unit for double-conversion receivers
Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring Systems
3D-Domino: Ultra-Dense High-Accuracy 3D eDRAM-ROM Compute-In-Memory Based on CAA-IGZO TFT for Edge Large-Scale Model Inference
A 400V Monolithic GaN-on-SOI Half-Bridge with On-Chip Accurate Current Detection for Isolated Power Converters
A column readout channel for infrared and terahertz bolometers with direct analog to digital conversion
A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument
Designing OTA-C filters by SFG approach
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations
Learned Video Compression for YUV 4: 2: 0 Content Using Flow-based Conditional Inter-frame Coding
Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study
A CMOS 2 MHz self-calibrating bandpass filter for personal area networks
Nanopower Sampled Data Wavelet Filter Design using Switched Gain Cell Technique
The node voltage equations and structural conditions of observability for RLC networks over F(z)
Discontinuity-induced bifurcations in TCP/RED communication algorithms
A New Algorithm and its VLSI Architecture Design for Connected Component Labelling
Design of stable 2D IIR digital filters using iterative semidefinite programming
Two-Stage Difference-Based Estimation Method for Timing Skew in TI-ADCs
Anti-Counterfeiting Secured Design of a Bandgap Reference Circuit
A low-power RFID enabled temperature sensor for cold chain management
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering
Hyperspectral reconstruction in biomedical imaging using terahertz systems
Capacitance ratio approximation in SC filters via genetic algorithm
Hierarchical data structure-based timing controller design for plasma display panels
Calculation of Rademacher-Walsh Spectral Coefficients for Systems of Completely and Incompletely Specified Boolean Functions
A compressive piezoelectric front-end circuit for self-powered mechanical impact detectors
Current-mode control to enhance closed-loop performance of asymmetrical half-bridge dc-to-dc converters
Audio classification and scene recognition and for hearing aids
CMOS integrated gas sensor chip using SAW technology
An Offset-Canceling Approximate-DFT Beamforming Architecture for Wireless Transceivers
New phase shift modulator for resonant converters
Distributions of the Number of Solutions to the Network Power Flow Equations
Binary translation process to optimize nanowire arrays usage
A 65nm 10GHz pipelined MAC structure
Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA
Comparison of Virtual Network Embedding Algorithms for Data Center Networks
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS
Analytical synthesis of minimum L2-sensitivity realizations of all-pass digital filters
A high speed camera system based on an image sensor in standard CMOS technology
An efficient MFCC extraction method in speech recognition
Compressed sensing reconstruction: Comparative study with applications to ECG bio-signals
Well-defined design procedure for a three-stage CMOS OTA
On-chip hybrid regulator topology for portable SoCs with near-threshold operation
SiGe HBT power amplifier for IS-95 CDMA using a novel process, voltage, and temperature insensitive biasing scheme
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
Iontophoresis instrumentation for the enhancement of gene therapy in wound healing
Improving the acquisition time of a PLL-based, integer-N frequency synthesizer
Wavelet-based estimation of long-range dependence in MPEG video traces
Quasi-Resonant Interconnects: A Low Power Design Methodology
Simplified pitch detection algorithm of mixed speech signals
Design, Implementation and Performance of an IIoT Node for Vibration Monitoring
Transient Clock Power Estimation of Pre-CTS Netlist
Analysis of On-Chip Metal Micro-Electrode for CMOS ISFETs
Design of Optimum Totally Perfect Connection-Blocks of FPGA
A Class D Amplifier Output Stage with Low THD and High PSRR
Towards suppression of all harmonics in a polyphase multipath transmitter
A resolution-adaptive interpolation filter for video codec
Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation
A heuristic DSP BIST insertion algorithm with minimum area overhead
Haar filtering with pyramidal resistive networks
Recurrent Neural Network Circuit for Automated Detection of Atrial Fibrillation from Raw ECG
A sub-0.5V, 1.5µW rail-to-rail constant gm opamp and its filter application
Modified subband adaptive notch filters for eliminating multiple sinusoids with reduced bias and faster convergence
Towards a Gesture based Human-machine Interface: Fast 3D Tracking of the Human Fingers on High Speed Smart Camera Computers
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits
Width-constrained wire sizing for non-tree interconnections
CREMA: A Parallel Hardware Raytracing Machine
A block-based Markov random field model estimation for contextual classification using Optimum-Path Forest
An improved error concealment algorithm for intra-frames in H.264/AVC
Prime factorization of N-D polynomial matrices
On the Structured Parallelism of Decoders for LDPC Convolutional Codes - an Algebraic Description
A highly compact wideband continuous-time transimpedance low-pass filter
Error vector magnitude (EVM) measurements for GSM/EDGE applications revised under production conditions
An LDPC decoding method for fault-tolerant digital logic
A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR
Low-power and Low-noise Amplifier with Intermittent Operation for Compressed Sensing in EEG Measurement Systems
Collaborative Scalable Visual Compression for Human-Centered Videos
CNN in drug design - Recent developments
Symbol-rate estimation based on filter bank
Encoder-friendly Global-view-depth for Free Viewpoint Video
Design and Implementation of a Miniaturized Spintronic-Based Proximity Sensor
A 28-GHz Massive MIMO Receiver Deploying One-Bit Direct Detection with Wireless Synchronization
A realistic mammalian retinal model implemented on complex cell CNN universal machine
A highly linear low-voltage MOS transconductor
A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications
Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput
An all-CMOS low supply voltage temperature sensor front-end with error correction techniques
Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs
Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain
Binary-Truncated CDMA-Based On-Chip Network
A computer-aided-diagnosis of tonsillitis using tonsil size and color
A differential summing amplifier for analog VLSI systems
Adaptive IIR notch filters: state-space approach
An analytical propagation delay model with power supply noise effects
Dynamic Analysis of RF CMOS Inverter-Based Ring Oscillators using an All-Region MOSFET Charge-Based Model in 28nm FD-SOI CMOS
A novel frequency domain watermarking algorithm with resistance to geometric distortions and copy attack
MPEG-J: Java application engine in MPEG-4
Spike Transmission between Electrically Coupled Sensory Neurons is Improved by Filter Properties
A 3.3-V analog front-end chip for HomePNA applications
High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform
A 1-8 Gb/s optical wireless communication dual-mode receiver
Hardware implementation challenges of modern error control decoders
A low-noise high-sensitivity readout circuit for MEMS capacitive sensors
A New Architecture for a Cyclic Algorithmic D/A Converter
Bandwidth extension for ultra-wideband CMOS low-noise amplifiers
A lossless image coder with context-based minimizing MSE prediction and entropy coding
Smart integrated conditioning electronics for electrostatic vibration energy harvesters
A low in-band phase noise Fractional-N ADPLL based on Switched-Capacitor-DPI
High-speed character recognition system based on a complex hierarchical AER architecture
Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization
Live demonstration: Photon counting and direct ToF camera prototype based on CMOS SPADs
Frequency sensitive self-organizing maps and its application in color quantization
Energy-Efficient Short-Time Fourier Transform for Partial Window Overlapping
An All-digital Phase-locked Loop for Digital Power Management Integrated Chips
Analysis of Dynamic Errors in Tri-level DACs for Continuous-Time Delta-Sigma Modulators
Live demonstration: A stimulation platform for optogenetic and bionic vision restoration
Analysis of supply and ground noise sensitivity in ring and LC oscillators
MEMS-based power delivery control for bursty applications
Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications
Control-oriented design guidelines to extend the stability margin of switching converters
LDO Regulator Optimized on Power Efficiency and Load Transient Response with Voltage Damper and Body Loop Feedback
Image processing using hysteretic cellular neural networks
A robust frequency compensation scheme for LDO regulators
A 1Mb RRAM Macro with Bipolar Forming for Improved Programming Yield and Cell-by-cell Write Verification Scheme
A fast constructive algorithm for fixed channel assignment problem
Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus
A Low-Latency Polynomial Arithmetic Unit for ML-KEM and ML-DSA Standards
A reconfigurable direct RF receiver architecture
A study of synchronization in chaotic autonomous Cuk converters
Local stability analysis and hardware realization of an eigenvector tracking algorithm
An improved frequency and phase synthesis architecture
A mixed-signal tuning approach for continuous-time LPFs
Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures
A fully programmable Reed Solomon 8-bit codec based on a re-shaped Berlekamp Massey algorithm
Design of FIR filters with discrete coefficients via sphere relaxation
A distributed and object-oriented framework for VLSI physical design automation
A band-reject nested-PLL phase-noise reduction scheme for clock-cleaners
An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash
ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies
A model parameter and MAD prediction scheme for h.264 macroblock layer rate control
Class-based neural network method for fault location of large-scale analogue circuits
A Continuous-time Hidden Markov Model for Mean-variance Portfolio Optimization
Steady-State Analysis of Electronic Electrostatic Generators
A lifting based system for optimal compression and classification in the JPEG2000 framework
A PVT-Insensitive Capacitance-to-Digital Converter Using Ring-Based Time-Domain Quantizer
A 1.5-V CMOS fully differential inductorless RF bandpass amplifier
Towards a graphic tool of structural controllability of temporal networks
A 170nW CMOS wake-up receiver with -60 dBm sensitivity using AlN high-Q piezoelectric resonators
A method of inserting binary data into MPEG bitstreams
Selectable starting bit SAR ADC
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin
Analytical Layer Assignment with Simulated Annealing Refinement
39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
A new VLSI structure for an improved near-lossless color image compression algorithm inside wireless endoscopy capsule
High Linearity SAR ADC for High Performance Sensor System
Enabling the 5G: Modelling and Design of High Q Film Bulk Acoustic Wave Resonator (FBAR) for High Frequency Applications
Non-singular terminal sliding mode control and its application for robot manipulators
Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies
Multi-source multi-path video streaming over wireless mesh networks
Recursive semi-blind decoding of a space-time block code over frequency-selective channel
Toward a circuit theory for sensor networks with fading channels
A low power current-mode pixel with on-chip FPN cancellation and digital shutter
Two-dimensional channel rate allocation for SVC over error-prone channel
Non-smooth bifurcations in a 1-D piecewise linear model of a Single Inductor Two-Output DC-DC switching converter
A distributed neural signal sensor system
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
Spectrum-Efficient Precoding Design for Full-Duplex MIMO Relay Systems
Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications
HotAging - Impact of Power Dissipation on Hardware Degradation
A 94.1% Efficiency 20-180W GaN-Based Full-Bridge Wireless Power Receiver for High-Power Wireless Chargers
Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer
An efficiency-improved double hysteresis Buck with adaptive peak inductor current limit
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
A family of MD FFT algorithms of complexity intermediate between the MD Cooley-Tukey FFT and the MD prime-factor FFT
Improved frame and basic unit layers bit allocation scheme for H.264 video transmission over ARQ-based wireless channels
Functional Reverse Engineering on SAT-Attack Resilient Logic Locking
Biologically Plausible Contrast Detection using a Memristor Array
Towards Wireless Addressable Optoelectronic Implants for Large-Scale Optogenetics
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads
Implementation of High Performance IEEE 754-Posit Conversion Hardware
Analysis and improvement of bilateral chopper having current resonant soft-switch
A Simple and Robust Method for Controlling Chaotic Systems
Very low-voltage fully differential amplifier for switched-capacitor applications
Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs
Tones, Saturation, and SNR in Doubel Loop Sigma Delta Modulators
A robust and efficient universal CNN cell circuit using simplicial neuro-fuzzy inferences for fast image processing
A tunable 0.5-1.3 GHz CMOS 2nd order bandpass filter with 50 Omega input-output impedance matching
Design guidelines for 3D RRAM cross-point architecture
Real-time Power Amplifier Impairment Assessment using Nonlinear Polynomial with Memory
"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC
Energy harvesting circuit using integrated transformer
Robust orthogonal adaptive deconvolution
A new algorithm for training multilayer feedforward neural networks
An efficient FPGA implementation of advanced encryption standard algorithm
An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector
Bee Detection for Fruit Cultivation
Effects of charge-based computation non-idealities on CMOS image compression sensors
CNN oriented fast HEVC intra CU mode decision
A sensor system on chip for wireless microsystems
Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes
A low power prototype for a 3D discrete wavelet transform processor
A 2.6GS/s Spectrometer System in 65nm CMOS for Spaceborne Telescopic Sensing
Low-power LDPC decoding based on iteration prediction
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip
Cosegmentation from similar backgrounds
Secure communication system based on a logistic map and a linear feedback shift register
A transmitted-reference low-power reconfigurable ultra-wideband transmitter
A circuit model of human whole blood in a microfluidic dielectric sensor
A 49 μW 6th-Order Chebyshev SSF-Based Low-Pass Analog Filter for IEEE 802.11ax
Computing Extreme Subspaces using Mirsky Theorem
A high data rate QPSK demodulator for inductively powered electronics implants
Designing efficient elliptic Curve Diffie-Hellman accelerators for embedded systems
Weighted Least-Squares Design of 2-D IIR Filters with Arbitrary Frequency Response using Iterative Second-Order Cone Programming
Dynamic Spatial Filtering with Residual Spectral Mapping for Lightweight Multichannel Speech Enhancement
Limit cycles in bang-bang phase-locked loops
Asynchronous interface for locally clocked modules in ULSI systems
Jointly minimum symbol error rate FIR MIMO transmitter and receiver filters for PAM signal vectors
Analytical computation of multipath components in the indoor power grid
Bit-Cell Selection Analysis for Embedded SRAM-Based PUF
Information theoretic analysis of concurrent information transfer and power gain
Continuous-time Leapfrog Filter with Precise Successive Approximation Tuning
Multi-scroll and hypercube attractors from Josephson junctions
Exploring evolutionary dynamics in a class of structured populations
A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply
Ultra Low Power Full Adder Topologies
Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT
Direct assessment of transient singularity in differential-algebraic systems
A 1.8V, 60dB Omega 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance
Adaptive multimedia content personalization
Improved matching pursuit algorithm and architecture for LTE Channel Estimation
Approximate-DCT-derived measurement matrices for compressed sensing
Transceiver parameter detection using a high conversion gain RF amplitude detector
Inductance/area/resistance tradeoffs in high performance power distribution grids
Analysis of class D inverter with irregular driving patterns
Adaptive blind equalization of multichannel FIR systems
Spin wave based synapse and neuron for ultra low power neuromorphic computation system
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation
A spiral learning approach to hardware description languages
A High-Speed CMOS Current Opamp for Very Low Supply Voltage Operation
An M-PSK Modulated Polar Transmitter Based on a Ring Oscillator with Low Power and Low Design Complexity for IoT Applications
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks
Temporally learning floating-gate VLSI synapses
Shot change detection on H.264/AVC compressed video
Reduction of errors in blind identification of FIR systems under order overestimation
Development of hybrid electrical model for CNT based Through Silicon Vias
Electrostatical coupling-spring for micro-mechanical filtering applications
Accurate playfield detection using Area-of-Coverage
A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process
New microwave bandstop filter using lumped and transversal network
Analog-decoder experiments with subthreshold CMOS soft-gates
Pipelining Tomlinson-Harashima precoders
A 1V supply successive approximation ADC with rail-to-rail input voltage range
In-vitro Assessment of the Adaptive Howland Current Source for Bioimpedance Haemolysis Measurements
Electric field focusing and shifting technique in deep brain stimulation using a dynamic tripolar current source
Design of a lower-error fixed-width multiplier for speech processing application
High-speed driver for SiC MOSFET based on class-E inverter
Design and Implementation of a Wideband Digital Interpolating Phase Modulator RF Front-End
Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic
Stable IIR filters - a new design approach
A readout circuit with novel zero-g offset calibration for tri-axes capacitive MEMS accelerometer
Dynamic Gesture Recognition Based on RF Sensor and AE-LSTM Neural Network
Spike-Based Feature Extraction for Noise Robust Speech Recognition Using Phase Synchrony Coding
Mobility support for Bluetooth public access
Modelling power consumption of a H.263 video encoder
FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters
Dependency driven partitioning objects generation for hardware/software partitioning
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS
Analytical model for the mean weights of two adaptive interpolated-FIR filter structures
A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application
Realization of 2D FIR filters using generalized polyphase structure combined with singular-value decomposition
Remote Frequency Calibration of Passive Wireless Microsensors and Transponders using Injection-locked Phase-locked Loop
An efficient design technique of a quantum divider circuit
A 2D DOA estimation algorithm for CDMA system with plane antenna array
Energy-efficient configurable discrete wavelet transform for neural sensing applications
Extended Operational Life for Wearable Health Devices: A Hybrid TinyML and Server-Side ML Approach
Design of High-Frequency BiCMOS Continuous-Time Filters with Low-Output Impedance Transconductor
A Compact Low Power Multi-mode Spiking Neuron using Band to Band Tunneling
A Study on the impact of spectral variability in brain-computer interface
Generation of Signals in a Buck Converter with Sliding Mode Contol
A new write-contention based dual-port SRAM PUF with multiple response bits per cell
Biorthonormal Filter Banks and the Theory of Transfer Matrix Inversion
Hardware-efficient parallel FIR digital filter structures for symmetric convolutions
Detecting Motion on Center Manifolds from a Time Series - An Example
Improved method for blind estimation of the variance of mixed noise using weighted LMS line fitting algorithm
VQNeRV: Vector Quantization Neural Representation for Video Compression
A 1/8-rate clock and data recovery architecture for high-speed communication systems
Tool-Path Optimization using Neural Networks
Modeling the impact of dynamic voltage scaling on 1T-1J STT-RAM write energy and performance
Adaptively-fit, space-variant point spread function model for a spherical lens optical system
Autonomous tuning method for realizing optimal adaptive voltage positioning scheme
Sideband noise reduction in transposed gain oscillators
Performance analysis of multiple access chaotic-sequence spread-spectrum communication systems employing parallel interference cancellation detectors
An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating
A body-biasing of readout circuit for STT-RAM with improved thermal reliability
A flexible design of packets over SONET or directly over fiber
Novel overshoot cancellation in comparator-based pipelined ADC
Multiple domain behavioral modeling using VHDL-AMS
Live Demonstration: Hardware Implementation of Brain-Inspired Amygdala Model
3.3-V baseband Gm-C filters for wireless transceiver applications
A Highly Parallel Fine-Grained Sort-Merge Join on Near Memory Computing
Energy-Efficient Approximate MAC Unit
Flexible Impedance Sensor for In-Line Monitoring of Water and Beverages
Multi-wing butterfly attractors from the modified Lorenz systems
Simplified structures for two-dimensional adaptive notch filters
Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates
A low voltage CMOS transresistance-based variable gain amplifier
Block-pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder
HLS Learning Approach: Efficient Optimization with Instruction Block Diagram