yusuke1997/dblp-id-title huggingface dataset:
Exploring Better Speculation and Data Locality in Sparse Matrix-Vector Multiplication on Intel Xeon
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag
Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array
Fault tolerance in RNS: an efficient approach
FPGA Synthesis Using Function Decomposition
Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays
Refresh-aware loop scheduling for high performance low power volatile STT-RAM
Fault grading of large digital systems
FPGA Implementation of High Speed FIR Filters Using Add and Shift Method
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration
Leakage Power Analysis and Reduction during Behavioral Synthesis
Branch assertion and elimination
Analysis and optimization of pausible clocking based GALS design
Interconnect Estimation for FPGAs under Timing Driven Domains
Detailed Characterization of a Quad Pentium Pro Server Running TPC-D
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths
A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture
Addressing the Tradeoff Between Standard and Custom ICs in System Level Design
Simultaneous Conjugate Gradient and iAFF-UNet for Accurate IR Drop Calculation
Dynamic warp resizing: Analysis and benefits in high-performance SIMT
VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes
TriMedia CPU64 Design Space Exploration
Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams
Low power and high speed multiplication design through mixed number representations
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs
Nesting Forward Automatic Differentiation for Memory-Efficient Deep Neural Network Training
Characterization and design of sequential circuit elements to combat soft error
Analytic processor model for fast design-space exploration
Threshold Logic in a Flash
Alternative strategies for applying min-cut to VLSI placement
Voltage scaling on C-elements: A speed, power and energy efficiency analysis
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
The Architecture of the LR33000: A MIPS Compatible RISC Processor for Embedded Control Applications
Multi-Model Inference Composition of Hyperdimensional Computing Ensembles
Performance and microarchitecture of the i486TM processor
Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry
The Microcore development system: a unified environment for designing new microprocessors
Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation
Achieving Full Parallelism in LSTM via a Unified Accelerator Design
Distributed VLSI Simulation on a Network of Workstations
Extending On-chip Interconnects for rack-level remote resource access
VITAL: fully automatic placement strategies for very large semicustom designs
Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000
AccUDNN: A GPU Memory Efficient Accelerator for Training Ultra-Deep Neural Networks
Alpha Architecture: Hardware Implementation and Software Programming Implications
Exploiting Quiescent States in Register Lifetime
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
FlexGM: An Adaptive Runtime System to Accelerate Graph Matching Networks on GPUs
Optimal Clocking of Circular Pipelines
Area minimization of redundant CORDIC pipeline architectures
Compact and accurate stochastic circuits with shared random number sources
Boolean factoring with multi-objective goals
X-Routing using Two Manhattan Route Instances
Multi-chip packaging for high performance systems
Concurrent Resynthesis for Network Optimization
Using Functional Information and Strategy Switching in Sequential ATPG
Current-based testing for analog and mixed-signal circuits
Clock-skew constrained placement for row based designs
Optical lithography simulation using wavelet transform
Hardware-based Fast Real-time Image Classification with Stochastic Computing
On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems
A 13.3ns double-precision floating-point ALU and multiplier
Reincarnate historic systems on FPGA with novel design methodology
Automatic assertion extraction in gate-level simulation using GPGPUs
Architecture Oriented Logic Optimization for Lookup Table Based FPGAs
Improving power delivery network design by practical methodologies
T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors
TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol
Pulse-mode macromodular systems
The Future of Populist Parallelism
Cycle-Based Timing Simulations Using Event-Stream
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path
On-Chip Multiple Superscalar Processors with Secondary Cache Memories
A Comparison of Redundant CORDIC Rotation Engines
Adaptive memory architecture for real-time image warping
A Method for Analog Circuits Visualization
A study on relating redundancy removal in classical circuits to reversible mapping
Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission
Fine-Grained Management of Thread Blocks for Irregular Applications
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
System-level performance estimation strategy for sw and hw
Red Teaming a Multi-Colored Bluetooth Bulb
System Level Verification of Large Scale Computer
Derivation of a DRAM Memory Interface by Sequential Decomposition
Latch Design for Transient Pulse Tolerance
Compacting randomly generated test sets
AuLoRA: Fine-Grained Loading and Computation Orchestration for Efficient LoRA LLM Serving
RETUNES: Reliable and Energy-Efficient Network-on-Chip Architecture
ASIC design using the high-level synthesis system CALLAS: a case study
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap
Near-optimal oblivious routing on three-dimensional mesh networks
Designing pipelined delay lines with dynamically-adaptive granularity for low-energy applications
SFDoP: A Scalable Fused BFloat16 Dot-Product Architecture for DNN
Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number Generators
Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures
The design of a multi-chip single package digital signal processing module
Reducing State Loss For Effective Trace Sampling of Superscalar Processors
Analog circuit synthesis and exploration in OASYS
RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime
Implementation of fast radix-4 division with operands scaling
FHAM: FPGA-based High-Efficiency Approximate Multipliers via LUT Encoding
Systolic algorithms for tree pattern matching
Symbolic Analysis Methods for Masks, Circuits, and Systems
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
Design Methodology for GMICRO TM /500 TRON Microprocessor
QTIME: A Machine Learning Framework for Timing Side-Channel Analysis in Quantum Circuit Simulators
RoShaQ: High-performance on-chip router with shared queues
Balancing performance and fault detection for GPGPU workloads
DEBBIE: a configurable user interface for CAD frameworks
Balancing Performance and Energy Efficiency of ONoC by Using Adaptive Bandwidth
Register allocation and VDD-gating algorithms for out-of-order architectures
Pensieve: a Machine Learning Assisted SSD Layer for Extending the Lifetime
Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA
A floating-point fused dot-product unit
Locality characteristics of symbolic programs
Lattice-Traversing Design Space Exploration for High Level Synthesis
Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices
Statistical generalization: theory and applications
Framework for massively parallel testing at wafer and package test
FPGA global routing architecture optimization using a multicommodity flow approach
Fault-based alternate test of RF components
CAP: Criticality analysis for power-efficient speculative multithreading
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation
An Adder Using Charge Sharing and its Application in DRAMs
A fuzzy logic controller with reconfigurable, cascadable architecture
The Splash 2 Processor and Applications
Power-Efficient Wakeup Tag Broadcast
Test-access mechanism optimization for core-based three-dimensional SOCs
The matrix transform chip
Compressed Embedded Diagnosis of Logic Cores
Post-layout comparison of high performance 64b static adders in energy-delay space
Thermal-Aware 3D Symmetrical Buffered Clock Tree Synthesis
Retrospective on "Power-Sensitive Multithreaded Architecture"
BioSCAN: A VLSI-Based System for Biosequence Analysis
A GALS Network-on-Chip based on rationally-related frequencies
Accelerating Sub-Block Erase in 3D NAND Flash Memory
Thermal-aware scratchpad memory design and allocation
Benchmarking, Selection and Debugging of Microcontrollers
A Mixed-Mode Delay-Locked-Loop Architecture
The challenge in testing MIMO in a Wi-Fi or WiMAX context
Models of IP's for Automotive Virtual Integration Platforms
Dealing with I/O Devices in the Context of Pervasive System Verification
Exploiting GPU architectures for dynamic invariant mining
VLSI implementation of high-throughput, low-energy, configurable MIMO detector
An Analysis of Path Sensitization Criteria
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor
A CMOS gate array with dynamic-termination GTL I/O circuits
Functional correctness for CMP interconnects
CoPIM: A Collaborative Scheduling Framework for Commodity Processing-in-memory Systems
Efficient MIMD architectures for high-performance ray tracing
Power Compiler: A Gate-Level Power Optimization and Synthesis System
A high performance BiCMOS 32-bit microprocessor
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
Shuffling across rounds: A lightweight strategy to counter side-channel attacks
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding
Technologies for Rapid Prototyping of Multi-Chip Modules
Integrated partitioning and scheduling for hardware/software co-design
Power switch characterization for fine-grained dynamic voltage scaling
Hierarchical simulation-based verification of Anton, a special-purpose parallel machine
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling
Ordered binary decision diagrams and circuit structure
RTDeepEnsemble: Real-Time DNN Ensemble Method for Machine Perception Systems
Array partitioning: a methodology for reconfigurability and reconfiguration problems
A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits
SECRET: Selective error correction for refresh energy reduction in DRAMs
Global bus route optimization with application to microarchitectural design exploration
Rectification of Integer Arithmetic Circuits using Computer Algebra Techniques
A low-power accuracy-configurable floating point multiplier
Improving Witness Search Using Orders on States
Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads
Cache design for mixed criticality real-time systems
Simulation and architecture improvements of atomic operations on GPU scratchpad memory
Strategies for optimal operating point selection in timing speculative processors
Accelerating divergent applications on SIMD architectures using neural networks
A radiation tolerant Phase Locked Loop design for digital electronics
A disruptive computer design idea: Architectures with repeatable timing
Interconnect performance corners considering crosstalk noise
Low-overhead error detection for Networks-on-Chip
Fault detection and automated fault diagnosis for embedded integrated electrical passives
A Multi-Level Memory System Architecture for High-Performance DSP Applications
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory
F-RISC/G: AlGaAs/GaAs HBT Standard Cell Library
Dark silicon aware runtime mapping for many-core systems: A patterning approach
Special Session: How much quality is enough quality? A case for acceptability in approximate designs
An Empirical Study of Hybrid SSD with Optane and QLC Flash
A Cost-Efficient Failure-Tolerant Scheme for Distributed DNN Training
Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systems
Energy-precision tradeoffs in mobile Graphics Processing Units
LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors
RealArch: A Real-Time Scheduler for Mapping Multi-Tenant DNNs on Multi-Core Accelerators
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost
Semi-analytical current source modeling of near-threshold operating logic cells considering process variations
Digital and analog integrated-circuit design with built-in reliability
IEEE P1149 Proposed Standard Testability Bus - An update with case histories
Allocation and Binding During Fault-Secure Microarchitecture Synthesis
Concurrent automatic test pattern generation algorithm for combinational circuits
Transparent mode flip-flops for collapsible pipelines
Design Guidelines and Testability Assessment
Special Issue: Resilient Distributed Estimator with Information Consensus for CPS Security
Functional Verification of the IBM zSeries eServer z900 System
On Design of Efficient Square Generator
Chisel-Q: Designing quantum circuits with a scala embedded language
What does ultra low power requirements mean for side-channel secure cryptography?
Online multiple error detection in crossbar nano-architectures
ND-HMDs: Non-Differentiable Hardware Malware Detectors against Evasive Transient Execution Attacks
Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications
CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks
Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique
The Alpha 21264 microprocessor architecture
Domain Characterization of Transmission Line Models for Efficient Simulation
Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging
Low Latency Approximate Adder for Highly Correlated Input Streams
Probabilistic error propagation in logic circuits using the Boolean difference calculus
The Logic of Fingerprint Upgrade in Deduplicated Storage
An Efficient Hardware Architecture for Finding Frequent Items in Data Streams
Control unit synthesis targeting low-power processors
Parallel-concurrent fault simulation
Deep Recommender Models Inference: Automatic Asymmetric Data Flow Optimization
Efficient floating-point representation for balanced codes for FPGA devices
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection
Partitioning Under Timing and Area Constraints
Model Checking Leveraged Error Localization for Complex RTL Designs
Design for Testability: Today and in the Future
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder
Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
FINEA: An Efficient Neural Network Accelerator Exploiting Factorized Input Features
An eight-issue tree-VLIW processor for dynamic binary translation
Some Techniques for Efficient Symbolic Simulation-Based Verification
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications
A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor
NR-MPA: Non-Recovery Compression Based Multi-Path Packet-Connected-Circuit Architecture of Convolution Neural Networks Accelerator
FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array
A Comparative Evaluation of Adders Based on Performance and Testability
Towards Accelerating Generic Machine Learning Prediction Pipelines
Neural Networks Update
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Workload-Driven Floorplanning for MIPS Optimization
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network
RasP: An Area-efficient, On-chip Network
A Unique Approach to Built-in-Self-Test Circuit Design
Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement
ONAC: Optimal number of active cores detector for energy efficient GPU computing
ChameSC: Virtualizing Superscalar Core of a SIMD Architecture for Vector Memory Access
Fast parallel communication on mesh connected machines with low buffer requirements
A functional diagnostics methodology
Finite State Machine Decomposition Using Multiway Partitioning
Adaptive and pipelined VLSI designs for tree-based codes
A self-timed redundant-binary number to binary number converter for digital arithmetic processors
DualFS: A Coordinative Flash File System with Flash Block Dual-mode Switching
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults
System interface of the NS32532 microprocessor
Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads
Parameterized Posit Arithmetic Hardware Generator
A Scale-Out Enterprise Storage Architecture
Reconsidering CEGAR: Learning Good Abstractions without Refinement
Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment
Assessing the impact of hard faults in performance components of modern microprocessors
Re-compact: Structured Pruning and SpMM Kernel Co-design for Accelerating DNNs on GPUs
Pausible Clocking: A First Step Toward Heterogeneous Systems
Techniques for LI-BDN synthesis for hybrid microarchitectural simulation
COSMA: An Efficient Concurrency-Oriented Space Management Scheme for In-memory File Systems
Hybrid Number Representations with Bounded Carry Propagation Chains
A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis
Computer Architecture in the Many-Core Era
Scheduling Information-Guided Efficient High-Level Synthesis Design Space Exploration
A Register File with Transposed Access Mode
Partial Functional Manipulation Based Wirelength Minimization
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping
On The Impact of Technology Scaling On Mixed PTL/Static Circuits
The PowerPC 601 Design Methodology
A New Functional Test Program Generation Methodology
Timing characterization of clock buffers for clock tree synthesis
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
MSE minimization and fault-tolerant data fusion for multi-sensor systems
CPA-Remap: Critical-Path-Based Physically Aware Remapping Framework for Timing Optimization
TAINT: Tool for Automated INsertion of Trojans
ECC string: Flexible ECC management for low-cost error protection of L2 caches
An automatic test pattern generation program for large ASICs
Boolean Function Representation Based on Disjoint-Support Decompositions
The Spring Scheduling Co-Processor: A Scheduling Accelerator
High-Level State Machine Specification and Synthesis
Quality improvement and cost reduction using statistical outlier methods
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability
VLIW-Processors under Periodic Real Time Constraints
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Hardware Ef.cient LBISTWith Complementary Weights
The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline
Performance Analysis and Optimization of Asynchronous Circuits
A reduced area scheme for carry-select adders
Multifault Testable Circuits Based on Binary Parity Diagrams
Fault Location Based on Circuit Partitioning
Counter-Based Cache Replacement Algorithms
Energy-efficient multi-level cell phase-change memory system with data encoding
A floating point unit for the 68040
DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment
Adaptive Size-Aware Cache Insertion Policy for Content Delivery Networks
Software power estimation and optimization for high performance, 32-bit embedded processors
TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies
Simultaneous area and delay minimum K-LUT mapping for K-exact networks
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic
Exploiting Quantum Assertions for Error Mitigation and Quantum Program Debugging
A statistical critical path monitor in 14nm CMOS
Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design
Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor
Robust and energy-efficient DSP systems via output probability processing
Thermal characterization of cloud workloads on a power-efficient server-on-chip
Low-Latency and Scalable Full-path Indexing Metadata Service for Distributed File Systems
Hierarchical pipelining for behaviors, loops, and operations
An Exact Rectilinear Steiner Tree Algorithm
Design and implementation of a special purpose embedded system for neural machine interface
Advanced Dynamic Scalarisation for RISC-V GPGPUs
A Multiprocessor Architecture for Circuit Simulation
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters
Energy-aware opcode design
In the Driver's Seat of BooleDozer
NUPLet: A Photonic Based Multi-Chip NUCA Architecture
Memory design for selective error protection
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor
ItHELPS: Iterative high-accuracy error localization in post-silicon
An Architectural Power Optimization Case Study using High-level Synthesis
Improved signoff methodology with tightened BEOL corners
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation
ALT: Optimizing Tensor Compilation in Deep Learning Compilers with Active Learning
Rationale for a 3D heterogeneous multi-core processor
Fair share: Allocation of GPU resources for both performance and fairness