yusuke1997/dblp-id-title huggingface dataset:
Enhanced Biased Radiation and Illumination Stress Stability of Solution-processed AlOx Dielectrics using Hydrogen Peroxide
A 100-μW wake-up receiver for UHF transceiver
A dual-band balun LNA resilient to 5-6 GHz WLAN blockers for IR-UWB in 65nm CMOS
Mobile CPU power/performance benchmarking and process technology co-optimization
Electrical Properties of Each Channels in Vertical Stacked Gate-All-Around Nanosheet s-Si pMOSFETs
Comprehensive study of wire bond reliability impacts from wire, molding compound and bond pad contamination
Electrical characterization of process induced effects on non-silicon devices
Deterministic Tagging Technology for Device Authentication
Status and perspectives of embedded Non-Volatile memories
32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation
Characterization and modeling of charge trapping: From single defects to devices
A low power programmable FIR filter using sharing multiplication technique
Design and Evaluation of AlGaN/GaN High Electron Mobility Transistor Comparator
Electro-thermal analysis of IGBT module from 3D CAD model
International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023
Dynamic Stage Element Matching (DSEM) in Pipeline Analog to Digital Converters (ADC)
Comparing the L&S and L-Band Antenna Low-Noise Amplifiers Designed by Multi-Objective Optimization
Cross logic: A new approach for defect-tolerant circuits
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs
6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology
STI fill effect on poly-poly comb IL
Lateral NWFET optimization for beyond 7nm nodes
Design process interactions in shallow trench isolation chemical mechanical planarization for layout diversification and design optimization
A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs
The implementation of HomePlug AV system
Low noise active loop filter for radar PLL applications
Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generators
Wideband inductorless CMOS RF front-end for LTE receivers
Low-power reference buffer for successive approximation register analog-to-digital converters
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops
Ferro-Electronics: From Memory to Computing
Design of AlGaN microring resonators for broadband biphoton excitation
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing
Low-energy signal processing using circuit-level timing-error acceptance
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process
Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier
Time-Based EIS Approach for State-of-Charge Assessment of Li-Ion Battery Cells in Automotive Applications: A Simulation Study
Modelling on GaN Power HEMT with Condideration of Subthreshold Swing Using Artificial Intelligence Technology
Insight into Effects of Introducing Ag-In-Zn-S Quantum Dots on Switching Characteristics of TiO2-Based Memristor
Design of 140GHz Narrow Band-pass Planar Filters Based on Open Loop Resonators
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation
An area compact soft error resident circuit for FPGA
A 5 V pp 10-Bit 100MS/s Current-Steering DAC as MZM Drivers of PNN Systems
A Low-Power Supply-Independent Analog Clock Frequency Divider for About 100 Division Factor
NRAM status and prospects
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
Analytical modeling of parasitics in monolithically integrated 3D inverters
Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control
Effective channel length of MOSFET with halo
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below
An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection
Low Temperature SmartCutTM enables High Density 3D SoC Applications
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process
Design of GaN-based Voltage Reference Circuit for a Wide-Temperature-Range Operation
Design and analysis of IC power delivery with on-chip voltage regulation
An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires
Evaluation of Indium Contamination in CMOS Lines in Context of Superconducting Integrated Circuits
Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications
Impact of local interconnects on ESD design
A brief introduction on contemporary High-Level Synthesis
3D monolithic integration: Stacking technology and applications
Fully analog automatic stray compensation for bridge-based differential capacitive sensor interfaces
Yield and energy tradeoffs of an NVLatch design using radial sampling
Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world
Strained silicon on insulator substrates for fully depleted application
A Flexible Data Acquisition System for Aerospace Applications
A Monolithic Gallium Nitride Driver with Zero-Voltage-Switching and Dead Time Control
A 5.06ppm/°C, -81.5dB-PSRR, 4.85µA Bandgap Reference with Curvature Correction in 55nm CMOS
10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multiprocessor chips applications
Dynamic CMOS-rectifying memristor multiplier architecture for power reduction
Keynote speakers: Molecular Spinterface - From fundamentals to applications
Advanced synaptic transistor device towards AI application in hardware perspective
Towards Ultra-fast Time-based Electrochemical Impedance Spectroscopy of Sensors
Active filters tuning interface
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction
Impact of Al+ implantation on the Switching Characteristics of Al2O3/La2O3/Al2O3 multilayer RRAM devices
Dual-Mode PUF and TRNG Design with Ring Generator on 180nm CMOS
Effects of Moisture Absorption on the Electrical Behaviors of InGaZnO Thin Film Transistors
Real-time digital implementation of a principal component analysis algorithm for neurons spike detection
Robust bias temperature instability refresh design and methodology for memory cell recovery
Self-healing Control and Auto-measurement Technique for Smart Distribution Grid
Dual function heat-spreading and performance of the IBM/ASTRON DOME 64-bit μServer demonstrator
A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits
Graphene based Wearable Sensors for Healthcare
A High Speed Low Power Pipelined SAR Analog to Digital Converter
A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic
A smart device for supporting mechanical ventilo-therapy
A method for real-time measurement of seismic isolation rubber bearing based on embedded MEMS pressure sensors
Optimization problems for plasma-induced damage - A concept for plasma-induced damage design
Analog Computation-in-Memory (CiM) for AI Applications
The Comparison of Dynamic Performance Between Hydrogen Treated and Etched p-GaN HEMTs
A study of scattering structures for high sensitive near-infrared pixels
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS Process
Through silicon via to FinFET noise coupling in 3-D integrated circuits
Radiation effects of floating-gate (FG) and charge-trapping (CT) Flash memory technologies
A 77GHz CMOS Down-Conversion Mixer with High CG Using CCPT-SPT Structure
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices
Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology
A 76-81 GHz CMOS down-conversion mixer for automotive radar
3-Dimensional Integration with High Interconnection Density
Mobile Ionic Field Effect Transistors with Amorphous Dielectrics: Device Demonstration and Modeling
Harnessing intrinsic memristor randomness with Bayesian neural networks
Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuits
Si MPS with CIBH Structure for Fast Recovery Applications
Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits
Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology
Multi-Functionalities and Applications of Dual-Port Ferroelectric FET
Design and process issues for high yield and reliability in thin BOX FD-SOI
Biosequences analysis on NanoMagnet Logic
A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process
Technology push or marketing pull?
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip
A low power fast wakeup flash memory system for embedded SOCs
Development of Neuromorphic Locomotion Generator with Switching Gait by Light Stimulation for Microrobots
Analog to digital converters on plastic foils
Highly reliable anti-fuse technology in sub-16nm technologies for security applications
Modeling SRAM dynamic VMIN
Analog Integrate-And-Fire Neuron in 7 nm FinFET Technology
International Conference on IC Design and Technology, ICICDT 2016, Ho Chi Minh, Vietnam, June 27-29, 2016
A 4 GHz to 6 GHz LNA Design in 12-nm FinFET for Quantum Computing
Design of a voltage reference circuit based on subthreshold and triode MOSFETs in 90nm CMOS
Small Area High Speed Configurable FFT Processor
BEOL-compatible Ta/HZO/W Ferroelectric Tunnel Junction with Low Operating Voltage Targeting for Low Power Application
39 - 67 GHz CMOS Multistage Power Amplifier With Two-Way Power Stage
Variability in Fully Depleted MOSFETs
A 256×256 SPAD Imager Architecture with Multi-Functional Pixel and High Temporal Aperture for Quantum Imaging Applications
Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix
Highly-reliable TaOx reram technology using automatic forming circuit
Exploration of different implementation styles for graphene-based reconfigurable gates
2018 International Conference on IC Design & Technology, ICICDT 2018, Otranto, Italy, June 4-6, 2018
Selectors for high density crosspoint memory arrays: Design considerations, device implementations and some challenges ahead
Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators
Random telegraph noise as a new measure of plasma-induced charging damage in MOSFETs
I 2 C System-on-Chip for bi-dimensional gas-sensor arrays providing extended dynamic-range A/D conversion and row temperature regulation
Interfacial transition layer in thermally grown SiO2 film on 4H-SiC
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models
Understanding Generated RTN as an Entropy Source for True Random Number Generators
A Monolithic Quasi-Resonant Switched-Capacitor Converter with Dual-Loop Time-Based Controller
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications
A 910nW delta sigma modulator using 65nm SOTB technology for mixed signal IC of IoT applications
Cost-Effective Reliable EEPROM Cell Based on Single-poly Structure
Robust Training of Optical Neural Network with Practical Errors using Genetic Algorithm: A Case Study in Silicon-on-Insulator-Based Photonic Integrated Chips
Soft-error resilient Network-on-Chip for safety-critical applications
Characteristics of Ni/AlOx/Pt RRAM devices with various dielectric fabrication temperatures
Modeling Simulation and Circuit Implementation of Millimeter Wave Phase-Locked Loop Based on Simulink
Interface and Doping Engineering of HfO2 Based Multi-Level RRAM: Towards Synaptic Simulation for Neuromorphic Computation
Approximate computing in the nanoscale era
BEOL-compatible Oxide Semiconductor Devices
Dominant Role of Air Ambient in Dynamic Bending Degradation of Flexible LTPS TFTs
High-Voltage Driver for Fully-Integrated Piezoelectric Inkjet Printhead Module
A 32-channel 12-bits single slope A-to-D converter for LHC environment
RISC-V Is Inevitable
All-solid-state Ion Doping Synaptic Transistor for Bionic Neural computing
Thermal experimental and modeling analysis of high power 3D packages
Effect of Mobile Ions on Subthreshold Swing of HfO2-based Ferroelectric Field-Effect Transistors
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit
Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction
Novel photodetectors and image sensors based on silicon-on-insulator substrate
A Ballistic Transport Study for Advanced Transistors in Post-Moore Era: Parasitic Resistance, Self-heating and Cryogenic Analysis
Template-based design optimization for multiple pairing-friendly curve parameters
Optimising Power-Performance in SOI-based Null Convention Logic
A Compact Low Voltage CMOS Current Mirror with High Output Resistance
Fast Locking Technique by Using a Programmable Operational Transconductor for a Phase Lock Loop Design
A Multi-Layered Air-Gap Transmission Line Design for CMOS-Compatible Millimeter-Wave ICs
Synthesis of clock gating logic through factored form matching
IC Design & Technology Co-Development: e-NVM & mmWave enablement of 22FDX™ Technology
GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks
A Gas Medium Approach To Sensitivity Improvement Of MEMS-Based Thermal Acoustic Particle Velocity Sensors
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling
On-chip accurate primary-side output current estimator for flyback LED driver control
Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations
A Slim Transmission Line Design with Patterned Ground Shields for CMOS mm-Wave Integrated Circuits
A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixer
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique
A Comprehensive Electronic Platform for Precision Agriculture Integrating Aerial and Ground Nodes: A Practical Case Study
Investigation of Low Temperature Noise and Current Fluctuation for Advanced Transistors: Characterization and Modeling
About figure-of-merit for continuous-time analog filters
International Conference on IC Design and Technology, ICICDT 2019, Suzhou, China, June 17-19, 2019
2014 IEEE International Conference on IC Design & Technology, ICICDT 2014, Austin, TX, USA, May 28-30, 2014
Challenges in generating true random numbers considering the variety of corners, aging, and attacks
A 28GHz Injection-Locked Voltage-Controlled Oscillator Pair with Tunable Phase Outputs in 130nm CMOS
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source
System Analysis of a SMOX Sensor Impedance Spectroscopy Interface Based on Chopper Stabilized Amplifier with Correlated Multiple Sampling
Two 6 GHz RO PLLs with -254 dB and -243 dB FOM and 0.0016 mm 2 and 0.0048 mm 2 Area
A programmable dynamic range and digital output rate oscillator-based readout interface for MEMS resistive and capacitive sensors
Power measurements and cooling of the DOME 28nm 1.8GHz 24-thread ppc64 μServer compute node
Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks
The design of a phase compensator for the CIC decimation filter
Improved electrical and thermal performances in nanostructured GaN devices
SOI CMOS technology for quantum information processing
The FASTER vision for designing dynamically reconfigurable systems
A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications
Innovative and 3D stacking Micro Electro Mechanical Systems (I-MEMS) for power saving
La-doped ZrO2 based BEoL decoupling capacitors
Integrated front-end/back-end simulation of electromagnetic fields, Lorentz force effects and fast current surges in microelectronic protection devices
Approaches for Optimizing Near Infrared Si Photodetectors Based on Internal Photoemission
Degradation in P-type Poly-Si Thin-Film Transistors under Pulse Bias Stresses
Cost-Effective High-Speed DRAM Testing: Circuit-Level Enhancements with Clock Multiplication and ECC
Characterization of onset tunneling voltage (Vonset) walkout in high-voltage deep trench isolation on SOI
Threshold Voltage Tuning Of 22 nm FD-SOI Devices Fabricated With Metal Gate Last Process
High swing low capacitance ESD RF protections in advanced CMOS technologies
ALD Ta2O5 and Hf-doped Ta2O5 for BEOL compatible MIM
State space model-oriented design for efficiency improvement of Class E power amplifier
Assessment of SiGe quantum well transistors for DRAM peripheral applications
Soft failures in integrated circuits as a matter of ESD events
Effect of High-k Passivation Layer on Electrical Properties of GaN Metal-Insulator-Semiconductor Devices
High-speed and highly accurate evaluation of electrical characteristics in MOSFETs
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing
Wire congestion aware high level synthesis flow with source code compiler
Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design
Towards minimum power analog filters
System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors
Reverse Blocking HEMTs with Stepped P-GaN Drain
Oxygen Vacancy Formation in Charged HfO2: An Ab Initio Study
Memristors Based on Two-Dimensional Layered Halide Perovskites for Neuromorphic Computing
Evaluation of compensation techniques for CMOS operational amplifier design
On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers
Design of low power, wider tuning range CMOS voltage control oscillator for ultra wideband applications
RC triggered active ESD clamps; How should they behave under powered conditions?
SibProMQTT: Protection of the MQTT Communication Protocol Against Sybil Attacks Applied for IoT Devices
Dynamic Circuit Characterization and a Single Ring-Oscillator-Based Test Structure for Its Timing Parameter Extraction
High-Throughput Key Switching Accelerator for Homomorphic Encryption
A capacitively coupled clock distribution network with correction for process dependent skew
A 3-V, 72-µW and 0.042-mm 2 Active-Area Dynamic Comparator in Flexible TFT Technology
A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology
Embracing the new era of AI at the edge
A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune Receiver Scheme for Power Electronics
Dynamic Trapping Related Hysteresis of Effective Output Capacitance in Overvoltage Transients of GaN E-mode Devices
Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters
Gate delay modeling for static timing analysis of body-biased circuits
A 60-GHz Transformer-Based Power Amplifier Supporting 5G n263-band Applications
Investigation of normally-OFF AlGaN/GaN MIS-HEMTs with Al2O3/ZrOx/Al2O3 charge trapping layer
Compact MOS Structure & Design for Ion-Ioff Thermal control in 28nm UTBB FD-SOI CMOS technology
OTS selector devices: Material engineering for switching performance
Nonparabolicity and confinement effects of IIIV materials in novel transistors
Beyond Integer Quantization: Approximate Arithmetic for Machine Learning Accelerators
Embedding hafnium oxide based FeFETs in the memory landscape
Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits
Enablement of CMOS integrated sensor, harvesting and storage applications by ferroelectric HfO2
A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology
Resistive switching performance of memristor with solution-processed stacked MO/2D-materials switching layers
DRC code coverage test a novel QA methodology
SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive
Complex trade-offs - Enablement of moore and more than moore
Systematic Study on Positive Bias Temperature Instability(PBTI) of ZrO2-based Ge nMOSFETs with Interlayer Passivations
A fast CAM-based Watermarking extraction on FPGA
Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation
Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology
Scaling of split-gate flash memory and its adoption in modern embedded non-volatile applications
A back biasing voltage generator for 28nm UTBB-FDSOI RVT CMOS digital circuits
Time-resolved single-photon detectors: Integration challenges in CMOS technologies
Impact of fin shape variability on device performance towards 10nm node
A new aspect of plasma-induced physical damage in three-dimensional scaled structures - Sidewall damage by stochastic straggling and sputtering
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications
Impact of device and interconnect process variability on clock distribution
Spectral variation analysis of integrated silicon photonics devices by using optical wafer probing
Nanoscale power and heat management in electronics
Co-Design and Optimization of a 320 GHz On-Chip Antenna for THz detection in 65nm CMOS Technology
A new statistical setup and hold time definition
Surface orientation dependence of ion bombardment damage during plasma processing
Design of a 3T current reference for low-voltage, low-power operation
On-chip transmission lines for silicon CMOS 6G: From basics to open questions
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS
55 to 59 GHz MMIC non-foster circuit enabled Class-J GaAs pHEMT power amplifier
CMOS compatible GaN-on-Si HEMT technology for RF applications: analysis of substrate losses and non-linearities
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications
Physics-Based Small-Signal Model of Ga2O3 Hot-Electron Transistor
Wurtzite-Structured Ferroelectric Materials Growth and Film Properties
Ge CMOS technology with advanced interface and junction engineering
A Wide Temperature Range 4.6 ppm/°C Piecewise Curvature-Compensated Bandgap Reference With No Amplifiers
Evaluating analog circuit performance in light of MOSFET aging at different time scales
Large-scale Integrated Circuits Simulation Based on CNT-FET Model
The Impact of Etch Depth of D-mode AlGaN/GaN MIS-HEMTs on DC and AC Characteristics of 10 V Input Direct-Coupled FET Logic (DCFL) Inverters
High Phase Accuracy QVCO with Current Reuse and Bulk-Coupled Structure
Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements
The Investigation of Source Field Plate on the Performance of pGaN Gate Device and Dual-Gate Bidirectional Switch using TCAD Simulation
An ultra low power operated logic NVM for passive UHF RFID tag applications
A digitally controlled oscillator suitable for on-chip integration in 65 nm CMOS
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model
GaN Technology for 5G Application
Register grouping for synthesis of clock gating logic
A System-on-Chip for IoT Applications with 16-bit Tiny Processor
Bidirectional interconnect design for low latency high bandwidth NoC