yusuke1997/dblp-id-title huggingface dataset:
Synthesis of task and message activation models in real-time distributed automotive systems
Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
Space-Efficient Bounded Model Checking
Initial transient response of oscillators with long settling time
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits
A low-cost radiation hardened flip-flop
Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata
High Rate Soft Output Viterbi Decoder
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies)
Formal analysis of the startup delay of SOME/IP service discovery
An approach to improve accuracy of source-level TLMs of embedded software
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation
Reasoning about VHDL and VHDL-AMS using Denotational Semantics
Active-mode leakage reduction with data-retained power gating
Sociology of design and EDA
An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory
HyIMC: Analog-Digital Hybrid In-Memory Computing SoC for High-Quality Low-Latency Speech Enhancement
A SW performance estimation framework for early system-level-design using fine-grained instrumentation
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin
Post-Layout Automated Optimization for Capacitor Array in Digital-to-Time Converter
FusionCache: Using LLC tags for DRAM cache
Practical exact synthesis
Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells
Managing Power Consumption in Networks on Chip
Designing Micro/Nano Systems for a Safer and Healthier Tomorrow
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology
On the Degree of Parallelism in Real-Time Scheduling of DAG Tasks
Conditional Deep Learning for energy-efficient and enhanced pattern recognition
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory
EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves
Combining optimizations in automated low power design
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
SparDR: Accelerating Unstructured Sparse DNN Inference via Dataflow Optimization
A Security Architecture for RISC-V based IoT Devices
System level techniques to improve reliability in high power microcontrollers for automotive applications
Swallow: Building an energy-transparent many-core embedded real-time system
Introduction to hardware trojan detection methods
Optimising Resource Management for Embedded Machine Learning
Deterministic software-based self-testing of embedded processor cores
ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms
Stability-aware integrated routing and scheduling for control applications in Ethernet networks
Exploit Analog IFA to Improve Specification Based Tests
Autonomy-driven Emerging Directions in Software-defined Vehicles
You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design
Efficient factorization of DSP transforms using taylor expansion diagrams
Smart, connected and mobile: architecting future electric mobility ecosystems
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Hybrid interconnect design for heterogeneous hardware accelerators
An efficient algorithm for free resources management on the FPGA
DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication
High performance collective communication-aware 3D Network-on-Chip architectures
Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures
Area optimization on fixed analog floorplans using convex area functions
HOT TOPIC - 3D Integration or How to Scale in the 21st Century
Current based PUF exploiting random variations in SRAM cells
Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice
Hardware/software co-design architecture for thermal management of chip multiprocessors
Bosphorus: Bridging ANF and CNF Solvers
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling
SHARC: A streaming model for FPGA accelerators and its application to Saliency
Malleable NoC: dark silicon inspired adaptable Network-on-Chip
MG-DmDSE: Multi-Granularity Domain Design Space Exploration Considering Function Similarity
HyDREA: Towards More Robust and Efficient Machine Learning Systems with Hyperdimensional Computing
A new speculative addition architecture suitable for two's complement operations
Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network
Methodology for EM Fault Injection: Charge-based Fault Model
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems
Assertion-Based Design Exploration of DVS in Network Processor Architectures
Routing table minimization for irregular mesh NoCs
DS-DSE: Domain-specific design space exploration for streaming applications
Optimization of design complexity in time-multiplexed constant multiplications
KIHT: Kaligo-Based Intelligent Handwriting Teacher
One-way shared memory
A fault-tolerant deadlock-free adaptive routing for on chip interconnects
Enabling Security on the Edge: A CHERI Compartmentalized Network Stack
S/DC: A storage and energy efficient data prefetcher
Designer-level verification: an industrial experience story
Remote and Stealthy Fault Attacks on Virtualized FPGAs
A unified methodology for pre-silicon verification and post-silicon validation
A Self-Learning Methodology for Epileptic Seizure Detection with Minimally-Supervised Edge Labeling
ATM Traffic Shaper: ATS
Run-time spatial resource management for real-time applications on heterogeneous MPSoCs
Enhancing multicore reliability through wear compensation in online assignment and scheduling
Reliability analysis reloaded: how will we survive?
Mitigating dark-silicon problems using superlattice-based thermoelectric coolers
Statistical Timing Analysis using Levelized Covariance Propagation
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
A true random number generator based on parallel STT-MTJs
Virtual prototype life cycle in automotive applications
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition
On Modeling Cross-Talk Faults
Energy-aware Placement for SRAM-NVM Hybrid FPGAs
Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells
Analog Transistor Placement Optimization Considering Nonlinear Spatial Variations
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs
Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication
Library-based scalable refinement checking for contract-based design
Test Pattern Generation for Approximate Circuits Based on Boolean Satisfiability
Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP
Stealthy Inference Attack on DNN via Cache-based Side-Channel Attacks
A Formal Approach To The Protocol Converter Problem
Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal Processors
Evaluating the impact of execution parameters on program vulnerability in GPU applications
SCOC3: a space computer on a chip
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level
Accurate QBF-based test pattern generation in presence of unknown values
An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays
Multithreaded code from synchronous programs: Extracting independent threads for OpenMP
Optimizing Imperfectly-Nested Loop Mapping on CGRAs via Polyhedral-Guided Flattening
Domain specific architecture for next generation wireless communication
Deterministic Pattern Generation for Weighted Random Pattern Testing
A novel approach to entirely integrate Virtual Test into test development flow
Power gating design for standard-cell-like structured ASICs
Cache-aware Schedulability Analysis of PREM Compliant Tasks
Big vs little core for energy-efficient Hadoop computing
ReVAMP: ReRAM based VLIW architecture for in-memory computing
Trace-based analysis methodology of program flash contention in embedded multicore systems
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
Decoupling capacitor planning with analytical delay model on RLC power grid
Spatial pattern prediction based management of faulty data caches
Error Generation for 3D NAND Flash Memory
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
Dual-addressing memory architecture for two-dimensional memory access patterns
Parallel and Distributed VHDL Simulation
Efficient variation-aware statistical dynamic timing analysis for delay test applications
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems
Dcha: Distributed-Centralized Heterogeneous Architecture Enables Efficient Multi-Task Processing for Smart Sensing
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs
FFT-based deep learning deployment in embedded systems
On Using Satisfiability-Based Pruning Techniques in Covering Algorithms
TT-SNN: Tensor Train Decomposition for Efficient Spiking Neural Network Training
Design closure driven delay relaxation based on convex cost network flow
On the Volume Calculation for Conditional DAG Tasks: Hardness and Algorithms *
Design of latches and flip-flops using emerging tunneling devices
Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAs
Reliability of Google's Tensor Processing Units for Embedded Applications
A Smart Space application to dynamically relate medical and environmental information
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation
RTL analysis and modifications for improving at-speed test
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits
An H.264 Quad-FullHD low-latency intra video encoder
Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models
High-Level Synthesis versus Hardware Construction
Automatic nonlinear memory power modelling
Optimal design and management of a smart residential PV and energy storage system
Piercing Logic Locking Keys through Redundancy Identification
A calibration based thermal modeling technique for complex multicore systems
Variable-latency design by function speculation
Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks
ADAM: Architecture for write disturbance mitigation in scaled phase change memory
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling
Variation-aware interconnect extraction using statistical moment preserving model order reduction
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs
Statistical aspects of NBTI/PBTI and impact on SRAM yield
A global postsynthesis optimization method for combinational circuits
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture
Production Recipe Validation through Formalization and Digital Twin Generation
Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits
Vulnerability analysis of L2 cache elements to single event upsets
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling
A Parallel Floating Random Walk Solver for Reproducible and Reliable Capacitance Extraction
SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration
High-level synthesis of approximate hardware under joint precision and voltage scaling
Pseudorandom functional BIST for linear and nonlinear MEMS
Generator based approach for analog circuit and layout design and optimization
Asynchronous design for new on-chip wide dynamic range power electronics
Practical way halting by speculatively accessing halt tags
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling
A time-multiplexed FPGA overlay with linear interconnect
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid
Beyond UML to an End-of-Line Functional Test Engine
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Layout driven data communication optimization for high level synthesis
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems
MAPG: Memory access power gating
A method for fast jitter tolerance analysis of high-speed PLLs
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
Prometheus: Processing-in-memory heterogeneous architecture design from a multi-layer network theoretic strategy
Diagnosis of defects on scan enable and clock trees
Power Optimization of Delay Constrained CMOS Bus Drivers
PICELF: An Automatic Electronic Layer Layout Generation Framework for Photonic Integrated Circuits
Performance impacts and limitations of hardware memory access trace collection
IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling
Adaptive Generative Modeling in Resource-Constrained Environments
Combining adaptive alternate test and multi-site
A novel model for system-level decision making with combined ASP and SMT solving
Impact of adaptive voltage scaling on aging-aware signoff
Energy minimization for real-time systems with non-convex and discrete operation modes
Exploiting sporadic servers to provide budget scheduling for ARINC653 based real-time virtualization environments
Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories
Improved synthesis of Clifford+T quantum functionality
A synthesis tool for power-efficient base-band filter design
DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference
PACE: A Piece-Wise Approximate and Configurable Floating - Point Divider for Energy - Efficient Computing
A 100KHz-1GHz Termination-dependent Human Body Communication Channel Measurement using Miniaturized Wearable Devices
Clock skew optimization considering complicated power modes
FPGA Design for Algebraic Tori-Based Public-Key Cryptography
Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems
Optimizing Performance of Persistent Memory File Systems using Virtual Superpages
VeriBug: An Attention-Based Framework for Bug Localization in Hardware Designs
ReCode: the design and re-design of the instruction codes for embedded instruction-set processors
Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems
Reliable estimation of execution time of embedded software
Towards Robust RRAM-Based Vision Transformer Models with Noise-Aware Knowledge Distillation
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators
Stochastic Power Grid Analysis Considering Process Variations
Evolutionary Optimization in Code-Based Test Compression
Data Cache Sizing for Embedded Processor Applications
XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers
TRADER: A Practical Track-Assignment-Based Detailed Router
Resource efficient computing for warehouse-scale datacenters
Combining structural and timing errors in overclocked inexact speculative adders
Context aware power management for motion-sensing body area network nodes
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Functional Analysis Attacks on Logic Locking
Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers
Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures
Non-fractional parallelism in LDPC decoder implementations
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes
SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs
FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams Yourself
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
Automated Modeling of Custom Digital Circuits for Test
QC-Fill: An X-Fill method for quick-and-cool scan test
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption
Adaptive compressed sensing at the fingertip of Internet-of-Things sensors: An ultra-low power activity recognition
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods
Timing modeling and analysis for AUTOSAR-based software development - a case study
Parallel Multi-Objective Bayesian Optimization Framework for CGRA Microarchitecture
Interpolation sequences revisited
A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN
Towards Formally Verified Optimizing Compilation in Flight Control Software
Optimizing Offload Performance in Heterogeneous MPSoCs
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip
Creating a sustainable information and communication infrastructure
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs
Dynamic Scheduling and Clustering in Symbolic Image Computation
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
Model-based protocol log generation for testing a telecommunication test harness using CLP
Multicore soft error rate stabilization using adaptive dual modular redundancy
Interconnect Planning with Local Area Constrained Retiming
Advanced system on a chip design based on controllable-polarity FETs
System Performance Optimization Methodology for Infineon's 32-Bit Automotive Microcontroller Architecture
Cool MPSoC programming
Thermally robust clocking schemes for 3D integrated circuits
Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems
Model Checking of Analog Systems using an Analog Specification Language
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy
The Programmable Logic-in-Memory (PLiM) computer
Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns
Design implications of memristor-based RRAM cross-point structures
Adaptive data placement in an embedded multiprocessor thread library
MAUI: Making aging useful, intentionally
Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC
CISGraph: A Contribution-Driven Accelerator for Pairwise Streaming Graph Analytics
GPUguard: Towards supporting a predictable execution model for heterogeneous SoC
jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking
A Single Phase Latch for High Speed GaAs Domino Circuits
Automated bottleneck-driven design-space exploration of media processing systems
SoC low-power practices for wireless applications
Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator
Minimizing the number of process corner simulations during design verification
Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments
An interprocedural code optimization technique for network processors using hardware multi-threading support
Once For All Skip: Efficient Adaptive Deep Neural Networks
Three years of low-power image recognition challenge: Introduction to special session
2D and 3D integration with organic and silicon electronics
DOTS: DRAM-PIM Optimization for Tall and Skinny GEMM Operations in LLM Inference
TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack Through Frequency-Triggered Key Generation
Health Monitoring of Milling Tools under Distinct Operating Conditions by a Deep Convolutional Neural Network model
Fair energy resource allocation by minority game algorithm for smart buildings
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification
Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers
A Bypass Scheme for Core-Based System Fault Testing
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques
The Future of Flexible HW Platform Architectures Panel Discussion
Improving the energy efficiency of STT-MRAM based approximate cache
Toward polychronous analysis and validation for timed software architectures in AADL
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
Minimization of P-circuits using Boolean relations
High temperature polymer capacitors for aerospace applications
Interconnect test for 3D stacked memory-on-logic
Addressing the healthcare cost dilemma by managing health instead of managing illness: an opportunity for wearable wireless sensors
Critical points based register-concurrency autotuning for GPUs
Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components
High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology
Increased accuracy through noise injection in abstract RTOS simulation
Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges
Memory System Connectivity Exploration
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions
Improved technology mapping using a new approach to Boolean matching
Learning to Skip Ineffectual Recurrent Computations in LSTMs
An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance Sampling
Specification Test Compaction for Analog Circuits and MEMS
A totally self-checking 1-out-of-3 code error indicator
A deblocking filter hardware architecture for the high efficiency video coding standard
Impact of process variation on endurance algorithms for wear-prone memories
Sequential logic rectifications with approximate SPFDs
Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?
Logic synthesis and defect tolerance for memristive crossbar arrays
Static memory allocation by pointer analysis and coloring
Test Compression and Hardware Decompression for Scan-Based SoCs
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs
A low-SER efficient core processor architecture for future technologies