yusuke1997/dblp-id-title huggingface dataset:
Delay-optimal technology mapping for in-memory computing using ReRAM devices
Dynamically Resilient and Agile Fine-Grained Replication Configuration
Early SoC security validation by VP-based static information flow analysis
Compact and complete test set generation for multiple stuck-faults
A probabilistic multicommodity-flow solution to circuit clustering problems
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial)
Fault detection in a testable PLA with low overhead for production testing
Leveraging rule-based designs for automatic power domain partitioning
AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks
AEP: An error-bearing neural network accelerator for energy efficiency and model protection
Test generation for highly sequential circuits
Modeling Non-Slicing Floorplans with Binary Trees
Aging analysis at gate and macro cell level
Romanus: Robust Task Offloading in Modular Multi-Sensor Autonomous Driving Systems
Sequential SPFDs
SAT-based compilation to a non-vonNeumann processor
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations
Improved logic optimization using global flow analysis
Instruction Generation for Hybrid Reconfigurable Systems
An algorithm for improving partitions of pin-limited multi-chip systems
TREX-F: TRustability of Electronics using X-ray based Fingerprinting
Your Agile Open Source HW Stinks (Because It Is Not a System)
LLM4Verilog: Building Large-Scale, High-Quality Data Infrastructure for Verilog Code Generation via Community Efforts
Dependable integrated clinical system architecture with runtime verification
FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SOCs
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
Removing concurrency for rapid functional verification
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs
SPRIM: structure-preserving reduced-order interconnect macromodeling
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists
A Statistical Timing Model for Low Voltage Design Considering Process Variation
Condition graphs for high-quality behavioral synthesis
Input assignment algorithm for decoded-PLAs with multi-input decoders
TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction
Structure preserving reduced-order modeling of linear periodic time-varying systems
Introduction to GPU programming for EDA
Optimum loading dispersion for high-speed tree-type decision circuitry
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
An adaptive two-level management for the flash translation layer in embedded systems
Functional safety methodologies for automotive applications
Application-Aware diagnosis of runtime hardware faults
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks
Single Instruction Isolation for RISC-V Vector Test Failures
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
Spatial correlation modeling for probe test cost reduction in RF devices
Minimizing power across multiple technology and design levels
The need and opportunities of electromigration-aware integrated circuit design
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Lazy-expansion symbolic expression approximation in SYNAP
Optimizing Stochastic Computing for Low Latency Inference of Convolutional Neural Networks
Efficient and accurate analysis of single event transients propagation using SMT-based techniques
Logic Compilation from Graphical Dependency Notation
Robust analog/RF circuit design with projection-based posynomial modeling
Re 2 fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators
SYLON-DREAM: a multi-level network synthesizer
Smart Simulation Using Collaborative Formal and Simulation Engines
Invited Paper: Efficient Design of FHEW/TFHE Bootstrapping Implementation with Scalable Parameters
New faster Kernighan-Lin-type graph-partitioning algorithms
DATC RDF: an academic flow from logic synthesis to detailed routing
RTL Power Optimization with Gate-Level Accuracy
2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration
Timing-driven placement using design hierarchy guided constraint generation
Frequency Domain Analysis of Switching Noise on Power Supply Network
Data Recomputation for Multithreaded Applications
Layout decomposition for double patterning lithography
A Markov chain sequence generator for power macromodeling
Speculative Load Forwarding Attack on Modern Processors
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Efficient synthesis of graph methods: a dynamically scheduled architecture
The effects of energy management on reliability in real-time embedded systems
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits
Incremental component implementation selection: enabling ECO in compositional system synthesis
Hardware/Software Co-testing of Embedded Memories in Complex SOCs
A tabular macromodeling approach to fast timing simulation including parasitics
Robust automated synthesis methodology for integrated spiral inductors with variability
ROAD: Improving Reliability of Multi-core System via Asymmetric Aging
TickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector Processor
Robust Communication with IoT Devices using Wearable Brain Machine Interfaces
Energy-efficiency in presence of deep submicron noise
Fault dictionary compression and equivalence class computation for sequential circuits
Multigrid-Like Technique for Power Grid Analysis
Generator-based Verification
On efficient Monte Carlo-based statistical static timing analysis of digital circuits
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
Application-specific network-on-chip architecture customization via long-range link insertion
Waveform relaxation for transient simulation of two-dimensional MOS devices
Minimizing Channel Density by Shifting Blocks and Terminals
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits
Compression-relaxation: a new approach to performance driven placement for regular architectures
(Invited) FENIX: Flexible and Efficient Hybrid HE/MPC Acceleration with Near-Memory Processing
Fundamental Limits on the Precision of In-memory Architectures
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Accelerating aerial image simulation with GPU
Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-vias
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits
Formal verification at higher levels of abstraction
A Generalized Method for Computing Oscillator Phase Noise Spectra
Large-signal MOSFET modeling using frequency-domain nonlinear system identification
Design things for the internet of things: an EDA perspective
Fast performance analysis of bus-based system-on-chip communication architectures
Efficiency improvements for force-directed scheduling
Partial Detectability Profiles
Floorplanning with Pin Assignment
OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection
The practical application of retiming to the design of high-performance systems
Task management in MPSoCs: An ASIP approach
Reachability analysis using partitioned-ROBDDs
An efficient method for improving the quality of per-test fault diagnosis
Projection-based performance modeling for inter/intra-die variations
Timing uncertainty analysis for time-of-flight systems
A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation
AXNet: approximate computing using an end-to-end trainable neural network
Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs
Decoupling capacitor planning and sizing for noise and leakage reduction
JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations
Implementing high-performance, low-power embedded processors: Challenges and solutions: Designer track
HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks
THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution
Fast incremental netlist compilation of hierarchical schematics
Faultless to a Fault? The Case of Threshold Implementations of Crypto-systems vs Fault Template Attacks
A linear optimal test generation algorithm for interconnect testing
Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system
Compaction-free compressed cache for high performance multi-core system
iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism Removal
CACTI-IO: CACTI with off-chip power-area-timing models
A unified signal transition graph model for asynchronous control circuit synthesis
Breadth-first manipulation of very large binary-decision diagrams
Test register insertion with minimum hardware cost
An efficient implementation of numerical integration using logical computation on stochastic bit streams
iTimerC: common path pessimism removal using effective reduction methods
BARQ: Boundary-Aware Regularized Training for Accurate Inference on Computing-in-Memory Accelerators with Low-Precision A/D Conversion
How Do Errors Impact NN Accuracy on Non-Ideal Analog PIM? Fast Evaluation via an Error-Injected Robustness Metric
Gate sizing using incremental parameterized statistical timing analysis
Analysis and evaluation of a hybrid interconnect structure for FPGAs
M 3 -a multilevel mixed-mode mixed D/A simulator
Aliens: a novel hybrid architecture for resistive random-access memory
Timing Arc based logic analysis for false noise reduction
Usage-Based RTL Subsetting for Hardware Accelerators
Simulation Approaches for Strongly Coupled Interconnect Systems
Improving coverage analysis and test generation for large designs
PHIFACT, a Boolean Preprocessor for Multi-Level Logic Synthesis
Word-Level Augmentation of Formal Proof by Learning from Simulation Traces
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation
Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates
Formal Methods for Emerging Technologies
TSTC: Two-Level Sparsity Tensor Core Enabling both Algorithm Flexibility and Hardware Efficiency
A contamination aware droplet routing algorithm for digital microfluidic biochips
Modeling and simulation of the interference due to digital switching in mixed-signal ICs
Machine-learning-based dynamic IR drop prediction for ECO
SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding
Snake-3D: Differentiable Learning for Cross-Tier Logic Path Snaking Optimization in 3D ICs
Analytical macromodeling for high-level power estimation
Constraint Identification for Timing Verification
Incorporating design flow management in a framework based CAD system
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency
Multi-scale, multi-physics analysis for device, chip, package, and board level
Placement Method Targeting Predictability Robustness and Performance
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion
Technology Mapping on Lookup Table-Based FPGAs for Performance
A methodology for local resonant clock synthesis using LC-assisted local clock buffers
Rapid-Prototyping of Hardware and Software in a Unified Framework
Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs: (Invited Paper)
Non-scan design-for-testability of RT-level data paths
Architectural-level synthesis of digital microfluidics-based biochips
A CAD-based methodology to optimize HLS code via the Roofline model
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms
Fault dictionary compaction by output sequence removal
Unifying synchronous/asynchronous state machine synthesis
Protecting integrated circuits from piracy with test-aware logic locking
Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees
Analysis and optimization of SRAM robustness for double patterning lithography
Cache Optimization For Embedded Processor Cores: An Analytical Approach
Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs
Fault detection and location in reconfigurable VLSI arrays
A novel clock distribution and dynamic de-skewing methodology
Invited Paper: Liquid Computing: Towards Programmable Microfluidics
Efficient full-chip thermal modeling and analysis
True crosstalk aware incremental placement with noise map
A novel linear algebra method for the determination of periodic steady states of nonlinear oscillators
Circuit simulation via matrix exponential method for stiffness handling and parallel processing
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set
GPSCP: A general-purpose support-circuit preconditioning approach to large-scale SPICE-accurate nonlinear circuit simulations
Design verification via simulation and automatic test pattern generation
Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
An auction based pre-processing technique to determine detour in global routing
Configuring multiple scan chains for minimum test time
An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis
Constrained pattern assignment for standard cell based triple patterning lithography
Custom-optimized multiplierless implementations of DSP algorithms
Detection of multiple transitions in delay fault test of SPARC64 microprocessor
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains
A custom cell generation system for double-metal CMOS technology
CoP&R: Co-Optimizing Place-and-Route for Standard Cell Layout via MCTS and AllSAT
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions
Structure optimization in logic schematic generation
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck
An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays
Faster SAT and Smaller BDDs via Common Function Structure
Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection
Counteracting Adversarial Attacks in Autonomous Driving
A Channel Router for Single Layer Customization Technology
Tree-height minimization in pipelined architectures
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
A new approach to effective circuit clustering
Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off
Opportunistic through-silicon-via inductor utilization in LC resonant clocks: concept and algorithms
A loosely coupled parallel algorithm for standard cell placement
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits
Balanced reconfiguration of storage banks in a hybrid electrical energy storage system
Communication synthesis for distributed embedded systems
MONGREL: Hybrid Techniques for Standard Cell Placement
GeoFA: A Geometric Finite Automaton Engine for Efficient Layout Pattern Matching
Symbolic system level reliability analysis
An implicit connection graph maze routing algorithm for ECO routing
Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures
New Passive and Active Attacks on Deep Neural Networks in Medical Applications
Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect
A behavioral simulation tool for continuous-time delta sigma modulators
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Direct synthesis of timed asynchronous circuits
Design space exploration for aggressive test cost reduction in CircularScan architectures
Verifying hardware in its software context
Practical considerations for passive reduction of RLC circuits
GenomeDPU: A Cost-Effective In-Memory Data Processing Unit for GPU-based Genome Analysis
Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
A Scheduling Algorithm for Conditional Resource Sharing
A Framework for Designing Reusable Analog Circuits
Register-transfer level estimation techniques for switching activity and power consumption
A Routing Methodology for Analog Integrated Circuits
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
Race Detection for Two-Phase Systems
Asynchronous circuit placement by lagrangian relaxation
4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs
Python based framework for HDSLs with an underlying formal semantics: (Invited paper)
Reconfigurable machine and its application to logic diagnosis
A Precision-Steerable Electromigration Solver with Physics-Informed Adaptive Graph Partitioning
Low-power programmable routing circuitry for FPGAs
Multipoint Padé approximation using a rational block Lanczos algorithm
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2024, Newark Liberty International Airport Marriott, NJ, USA, October 27-31, 2024
Application driven high level design in the era of heterogeneous computing
A ferroelectric FET based power-efficient architecture for data-intensive computing
A new enhanced SPFD rewiring algorithm
Automatic synthesis of 3D asynchronous state machines
An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks
Transient Noise Bounds using Vectorless Power Grid Verification
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization
Functional timing optimization
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification
A new method towards achieving global optimality in technology mapping
Stochastic analysis of interconnect performance in the presence of process variations
A Stimulus/Response System Based on Hierarchical Timing Diagrams
A general framework for probabilistic low-power design space exploration considering process variation
Boolean minimization and algebraic factorization procedures for fully testable sequential machines
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation
Information Leakage from FPGA Routing and Logic Elements
Invited Paper: Analyzing the Robustness of Neuromorphic Computing in the Presence of Variability in Non-Volatile Memory
Pre-bond testable low-power clock tree design for 3D stacked ICs
ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests
Analytical fault modeling and static test generation for analog ICs
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
An output encoding problem and a solution technique
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators
Assuring application-level correctness against soft errors
NTHU-Route 2.0: a fast and stable global router
Deep submicron defect detection with the energy consumption ratio
Combining circuit level changes with electrical optimization
AyE-Edge: Automated Deployment Space Search Empowering Accuracy yet Efficient Real-Time Object Detection on the Edge
Hazard-non-increasing gate-level optimization algorithms
Standards for System Level Design
Frugal linear network-based test decompression for drastic test cost reductions
Security aspects of neuromorphic MPSoCs
Physical And Reduced-Order Dynamic Analysis of MEMS
Thermal sensor allocation and placement for reconfigurable systems
ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite
Simplifying Boolean constraint solving for random simulation-vector generation
SCArmor: Layer-Bit Joint Hardening with a Fast Genetic Optimization for Cost-Efficient and High-Reliable SC-DCNN Circuits
State retention for power gated design with non-uniform multi-bit retention latches
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022
R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges
Methods for Reducing Events in Sequential Circuit Fault Simulation
Recent research development in PCB layout
Frequency domain simulation of high-Q oscillators with homotopy methods
O-HAS: Optical Hardware Accelerator Search for Boosting Both Acceleration Performance and Development Speed
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
Compatible Observability Don't Cares Revisited
Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis
A general dispersive multiconductor transmission line model for interconnect simulation in SPICE
Incremental CAD
The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs
Towards In-Circuit Tuning of Deep Learning Designs
Multi-level logic optimization for low power using local logic transformations
Synthesis fo the hardware/software interface in microcontroller-based systems
Layout Pattern Generation and Legalization with Generative Learning Models
Data parallel switch-level simulation
IEEE/ACM International Conference On Computer Aided Design, ICCAD 2021, Munich, Germany, November 1-4, 2021
MOC: Multi-Objective Mobile CPU-GPU Co-Optimization for Power-Efficient DNN Inference
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Dynamic power management using adaptive learning tree
Low-power multiple-bit upset tolerant memory optimization
A New Method for Assigning Signal Flow Directions to MOS Transistors
Logic synthesis and a generalized notation for memristor-realized material implication gates
MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device
An efficient method to identify critical gates under circuit aging
Polarized observability don't cares