yusuke1997/dblp-id-title huggingface dataset:
Aggregating processor free time for energy reduction
A hierarchical control scheme for energy quota distribution in hybrid distributed video coding
AsyncStripe: I/O efficient asynchronous graph computing on a single server
seBoost: Selective boosting for heterogeneous manycores
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Memory size estimation for multimedia applications
Software Implementation Techniques for Hw/Sw Embedded Systems
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
Hardware support for real-time operating systems
A power-efficient and high performance FPGA accelerator for convolutional neural networks: work-in-progress
FRA: a flash-aware redundancy array of flash storage devices
Efficient exploration of on-chip bus architectures and memory allocation
An elastic software cache with fast prefetching for motion compensation in video decoding
Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling
Furion: alleviating overheads for deep learning framework on single machine (work-in-progress)
Uninterpreted Co-Simulation for Performance Evaluation of Hw/Sw Systems
Designing VM schedulers for embedded real-time applications
Smart driver for power reduction in next generation bistable electrophoretic display technology
Scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach
System-level design tools: who needs them, who has them, and how much should they cost?
Reliable software for unreliable hardware: embedded code generation aiming at reliability
DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
Dual-pipeline heterogeneous ASIP design
An integer linear programming approach for identifying instruction-set extensions
Retargetable compilation for low power
Power analysis of system-level on-chip communication architectures
Alert-and-transfer: an evolutionary architecture for SSD-based storage systems
Tackling QoS-induced aging in exascale systems through agile path selection
An improved network interface card with query filter for big data systems: work-in-progress
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture
IoT technologies for embedded computing: a survey
Power optimization for universal hash function data path using divide-and-concatenate technique
Complex task activation schemes in system level performance analysis
Fast processor core selection for WLAN modem using mappability estimation
Verification of dynamically reconfigurable embedded systems by model transformation rules
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
Transparent and portable agent based task migration for data-flow applications on multi-tiled architectures
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation
Design entropy concept: a measurement for complexity
DeVos: A learning-based delay model of voltage-scaled circuits: work-in-progress
A New Hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress
An efficient hardware design for cerebellar models using approximate circuits: special session paper
Automatic run-time extraction of communication graphs from multithreaded applications
Human-machine communication for assistive IoT technologies
A design methodology to implement memory accesses in high-level synthesis
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing
Bridging gap between simulation and spreadsheet study
A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory
Towards provably correct hardware/software partitioning using occam
Towards a multi-formalism framework for architectural synthesis: the ASAR project
Energy conscious online architecture adaptation for varying latency constraints in sensor network applications
Architecture Synthesis and Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices
A unified framework for throughput analysis of synchronous data flow graphs under memory constraints: work-in-progress
Accurate estimation of cache-related preemption delay
Working-set-based address mapping for ultra-large-scaled flash devices
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model
Bound-oriented parallel pruning approaches for efficient resource constrained scheduling of high-level synthesis
Remote detection of unauthorized activity via spectral analysis: work-in-progress
From RTL IP to functional system-level models with extra-functional properties
An online wear state monitoring methodology for off-the-shelf embedded processors
Fault injection acceleration by architectural importance sampling
A computational reflection mechanism to support platform debugging in SystemC
Generating interlocked instruction pipelines from specifications of instruction sets
Verification of balancing architectures for modular batteries
A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models
Designing next-generation real-time streaming systems
Exploiting polymorphism in HW design: a case study in the ATM domain
Wireless protocols design: challenges and opportunities
SystemC: a homogenous environment to test embedded systems
Efficient performance analysis of asynchronous systems based on periodicity
Fast exploration of bus-based on-chip communication architectures
Demand-based block-level address mapping in large-scale NAND flash storage systems
Multi-objective mapping for mesh-based NoC architectures
Floorplan driven leakage power aware IP-based SoC design space exploration
Distributed QoS management for internet of things under resource constraints
Efficient search space exploration for HW-SW partitioning
A trace transformation technique for communication refinement
A fast parallel reed-solomon decoder on a reconfigurable architecture
Future automotive systems design: research challenges and opportunities: special session
A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters
Influence of procedure cloning on WCET prediction
A case study in computer-aided codesign of embedded controllers
Comparing the size of .NET applications with native code
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
EPIDETOX: an ESL platform for integrated circuit design and tool exploration
HW/SW partitioning of an embedded instruction memory decompressor
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Efficient arithmetic for lattice-based cryptography: special session paper
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses
Hierarchical ensemble learning for resource-aware FPGA computing: work-in-progress
Design methodologies for securing cyber-physical systems
A novel codesign approach based on distributed virtual machines
A unified formal model of ISA and FSMD
Schedule-aware performance estimation of communication architecture for efficient design space exploration
HySim: a fast simulation framework for embedded software development
Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems
An approach to the adaptation of estimated cost parameters in the COSYMA system
Enabling ultra-low power operation in high-end wireless sensor networks nodes
Code generation from a domain-specific language for C-based HLS of hardware accelerators
To alert, rescue and recover: critical information technologies for managing mega disasters
Future wireless convergence platforms
Optimizing communication in embedded system co-simulation
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation
Secure FPGA circuits using controlled placement and routing
An efficient retargetable framework for instruction-set simulation
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
The construction of a retargetable simulator for an architecture template
Automotive electronics system, software, and local area network
Hardware based frequency/voltage control of voltage frequency island systems
A framework for interactive analysis of timing constraints in embedded systems
Charge allocation for hybrid electrical energy storage systems
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress
International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2020, Singapore, September 20-25, 2020
A CoDesign experience with the MCSE methodology
Instruction set selection for ASIP design
Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems
What will system level design be when it grows up?
System-level power-performance trade-offs in bus matrix communication architecture synthesis
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016
SystemC as completing pillar in industrial OVM based verification environments
Industrial IoT lifecycle via digital twins
Security and privacy challenges in IoT-based machine-to-machine collaborative scenarios
Towards a Model for Hardware and Software Functional Partitioning
The pipeline decomposition tree: : an analysis tool for multiprocessor implementation of image processing applications
A code-generator generator for multi-output instructions
Locality optimization in wireless applications
A standards-based, fully-open software platform for smart embedded systems
On the automatic generation of GPU-oriented software applications from RTL IPs
Microcoded coprocessor for embedded secure biometric authentication systems
Runtime configurable deep neural networks for energy-accuracy trade-off
Resource virtualization in real-time CORBA middleware
Hardware/software partitioning of embedded system in OCAPI-xl
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
A time-predictable system initialization design for huge-capacity flash-memory storage systems
Research issues in smart phones, notepads and related services
Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures
The future of system-level design: can we find the right solutions to the right problems at the right time?
DevScope: a nonintrusive and online power analysis tool for smartphone hardware components
VarEMU: An emulation testbed for variability-aware software
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2018, part of ESWEEK 2018, Torino, Italy, September 30 - October 5, 2018
Worst-case performance analysis of synchronous dataflow scenarios
Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor
A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow
Improved hard real-time scheduling of CSDF-modeled streaming applications
Promises and challenges of mobile embedded system: : an industry perspective
FlexRay schedule optimization of the static segment
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines
Designing digital video systems: modeling and scheduling
A variation-tolerant scheduler for better than worst-case behavioral synthesis
Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?
A performance model and code overlay generator for scratchpad enhanced embedded processors
RTOS-centric hardware/software cosimulator for embedded system design
Driving behavior modeling and estimation for battery optimization in electric vehicles: work-in-progress
Online OLED dynamic voltage scaling for video streaming applications on mobile devices
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Embedded systems education: how to teach the required skills?
An analysis-based approach to composition of distributed embedded systems
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
An example of applying the codesign method MOOSE
A PV aware data placement scheme for read performance improvement on LDPC based flash memory: work-in-progress
The design of a smart imaging core for automotive and consumer applications: a case study
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
System level memory optimization for hardware-software co-design
Holistic design and caching in mobile computing
Completeness bounds and sequentialization for model checking of interacting firmware and hardware
On the roles of functions and objects in system specification
SPARTA: runtime task allocation for energy efficient heterogeneous many-cores
A low-cost memory architecture with NAND XIP for mobile embedded systems
The case for a configure-and-execute paradigm
Exploring programming model-driven QoS support for NoC-based platforms
Hardware neural network accelerators
Memory system design space exploration for low-power, real-time speech recognition
Probabilistic performance risk analysis at system-level
A probabilistic performance metric for real-time system design
The information processing factory: a paradigm for life cycle management of dependable systems
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, part of ESWeek '11 Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011
Complexity challenges towards 4th generation communication solutions
Reliable performance analysis of a multicore multithreaded system-on-chip
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005
A parallelizable approach for mining likely invariants
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper)
Performance debugging of Esterel specifications
A concept of a hardware design environment with the functional language elixir: work-in-progress
Ensuring secure program execution in multiprocessor embedded systems: a case study
On buffering with stochastic guarantees in resource-constrained media players
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
Towards a theory for hardware/software codesign
Towards a synthesis semantics for systemC channels
Pareto-optimization-based run-time task scheduling for embedded systems
Approach to the Synthesis of HW and SW in Codesign
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach
A power estimation methodology for systemC transaction level models
Heterogeneous modeling and simulation of embedded systems in El Greco
Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures
Storage requirement estimation for data intensive applications with partially fixed execution ordering
A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress
Economic learning for thermal-aware power budgeting in many-core architectures
Static analysis for fast and accurate design space exploration of caches
Improving application launch times with hybrid disks
Aspects of system-level design
Nano-engineered architectures for ultra-low power wireless body sensor nodes
Conquering MPSoC complexity with principles of a self-aware information processing factory
Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems
Design-For-Debug in Hardware/Software Co-Design
DOVE: pinpointing firmware security vulnerabilities via symbolic control flow assertion mining (work-in-progress)
A cycle-accurate compilation algorithm for custom pipelined datapaths
A generic multi-unit architecture for codesign methodologies
Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress
Hampering fault attacks against lattice-based signature schemes: countermeasures and their efficiency (special session)
Architectural versus physical solutions for on-chip communication challenges
An energy-efficient patchable accelerator for post-silicon engineering changes
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS 2019, part of ESWEEK 2019, New York, NY, USA, October 13-18, 2019
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits
A performance-oriented hardware/software partitioning for datapath applications
A constructive algorithm for memory-aware task assignment and scheduling
A smart random code injection to mask power analysis based side channel attacks
On-chip communication design: roadblocks and avenues
Runtime requirements monitoring for state-based hardware: work-in-progress
2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014, Uttar Pradesh, India, October 12-17, 2014
Fast parallel application and multiprocessor design space exploration from sequential code
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy estimation for 32-bit microprocessors
Tracking object life cycle for leakage energy optimization
Model checking SystemC designs using timed automata
Key technologies for the next generation wireless communications
A holistic approach to network-on-chip synthesis
Equivalence of transformations of synchronous data flow graphs: work-in-progress
Design space exploration of multi-task processing on space shared FPGAs: work-in-progress
Layering the monitoring action for improved flexibility and overhead control: work-in-progress
Hardware/software selected cycle solution
Symbolic voter placement for dependability-aware system synthesis
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Three-dimensional multiprocessor system-on-chip thermal optimization
The usage of stochastic processes in embedded system specifications
Statistical approach in a system level methodology to deal with process variation
A compilation-based software estimation scheme for hardware/software co-simulation
Correct and non-defensive glue design using abstract models
Design flow for hardware/software cosynthesis of a video compression system
Accurate yet fast modeling of real-time communication
DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress
A generic tool set for application specific processor architectures
Software timing analysis using HW/SW cosimulation and instruction set simulator
Design space exploration and parameter tuning for neuromorphic applications
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007
Driving forces behind SOC development
Dynamic tuning of configurable architectures: the AWW online algorithm
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001
Schedulability analysis of heterogeneous systems for performance message sequence chart
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
Secure non-volatile memory with scratch pad memory using dual encryption mode: work-in-progress
Design optimization of mixed time/event-triggered distributed embedded systems
Formal synthesis and code generation of embedded real-time software
A systematic approach to software peripherals for embedded systems
CRAMES: compressed RAM for embedded systems
Learned buffer management: a new frontier: work-in-progress
Bio-inspired ultra lower-power neuromorphic computing engine for embedded systems
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor
A methodology for control-dominated systems codesign
Dynamic data management for automotive ECUs with hybrid RAM-NVM memory: work-in-progress
Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress
Distributed and low-power synchronization architecture for embedded multiprocessors
LOP: a novel SRAM-based architecture for low power and high throughput packet classification
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations
Designing domain-specific processors
A codesigned on-chip logic minimizer
Hardware/software co-design of an avionics communication protocol interface system: an industrial case study
Run-time adaption for highly-complex multi-core systems
System-of-PUFs: Multilevel security for embedded systems
Modeling reactive systems in Java
Communication synthesis and HW/SW integration for embedded system design
The importance of interfaces: a HW/SW codesign case study
System-on-chip validation using UML and CWL
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems
Hardware implementation of a multi-mode-aware mixed-criticality scheduler: work-in-progress
An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, CODES 1998, Seattle, Washington, USA, March 15-18, 1998
Work-in-Progress: Enabling Edge-based Self-Navigation in Earthquake-Struck Zones
A statechart based HW/SW codesign system
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression
Power-smart system-on-chip architecture for embedded cryptosystems
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems
Portable SystemC-on-a-chip
Run-time resource management based on design space exploration
Going deeper than deep learning for massive data analytics under physical constraints
Predator: a predictable SDRAM memory controller
Generating situation awareness in cyber-physical systems: Creation and exchange of situational information
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings
Fast system-level power profiling for battery-efficient system design
Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper
Whole program compilation for embedded software: the ADSL experiment
Dynamic, non-linear cache architecture for power-sensitive mobile processors
An introduction to the SystemC synthesis subset standard
Emerging non-volatile memories: opportunities and challenges
Workload characterization and its impact on multicore platform design