yusuke1997/dblp-id-title huggingface dataset:
IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014, Aizu-Wakamatsu, Japan, September 23-25, 2014
A Study of Conflicting Pairs of Compiler Optimizations
Performance Validation of the Multicore SoC for Spacecraft Applications
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations
BRISKI: A RISC-V barrel processor approach for higher throughput with less resource tax
The Network Performance Analysis Platform and Its Application to Network Buffer Evaluation of the Embedded System
Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-Criteria Recommender System
Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks
Movie Oriented Positive Negative Emotion Classification from EEG Signal using Wavelet transformation and Machine learning Approaches
Feed-Forward Probabilistic Error Cancellation with Noisy Recovery Gates
On Constructing Cost Models for Online Automatic Tuning Using ATMathCoreLib: Case Studies through the SVD Computation on a Multicore Processor
A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations
Real-Time UAV Attitude Heading Reference System Using Extended Kalman Filter for Programmable SoC
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks
A Cache Aware Multithreading Decision Scheme on GPGPUs
Runtime support for automatic placement of workloads on heterogeneous processors
On the Complexity of Mapping Feasibility in Many-Core Architectures
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores
Parameterizable mobile workloads for adaptable base station optimizations
A Fuzzy-Based Approach for Modelling Preferences of Users in Multi-Criteria Recommender Systems
cReComp: Automated Design Tool for ROS-Compliant FPGA Component
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip
Communication Aware Design Method for Optical Network-on-Chip
Design and Implementation of a Logistic Map-Based Pseudo-Random Number Generator on FPGA
Distributed Data Logger Based on Dual-Core MCU in Motor Drive
TensorRT Implementations of Model Quantization on Edge SoC
Automatic Generation of Fill-in-the-Blank Programming Problems
Generating Realistic Images with NeRF for Training of Autonomous Driving Network
Improving long text classification based on Selective State Space model (Mamba)
Variable Bit-Precision Vector Extension for RISC-V Based Processors
Low Overhead Monitor Mechanism for Fault-Tolerant Analysis of NoC
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time Constraint
Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs
Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation
Stochastic Analysis of Epidemic Routing Based Anycast in Throwbox-Equipped DTNs
Tuning Block Size for QR Factorization on CPU-GPU Hybrid Systems
Towards Latency-Aware Data Acquisition in Wireless Sensor Network
Performance Tuning of Tile Matrix Decomposition
Hardware Implementation of Double Pendulum Pseudo Random Number Generator
Advanced Computational Methods for Pelvic Bone Cancer Detection: Efficacy comparison of Convolutional Neural Networks
Sustainable Aviation: Evaluating Renewable Energy Systems at Changi Airport Using HOMER Pro
Bluetooth Low Energy Based Indoor Positioning on iOS Platform
Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus
Integrating Wireless Technology and Android-Based Mobile Application for Enhanced Limb Lengthening
Graph structure and homophily for label propagation in Graph Neural Networks
Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures
Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster System
SwinGaze: Egocentric Gaze Estimation with Video Swin Transformer
Parallel Implementation of CNN on Multi-FPGA Cluster
Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming
A Novel Yield Improvement Approach for 3D Stacking Neuromorphic Architecture
Improving Auto-Tuning Convergence Times with Dynamically Generated Predictive Performance Models
On the Load Balancing Techniques for GPU Applications Based on Prefix-Scan
Turn-aware Application Mapping using Reinforcement Learning in Power Gating-enabled Network on Chip
A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs
An Information Classification Approach Based on Knowledge Network
Design of The Ultra-Low-Power Driven VMM Configurations for μW Scale IoT Devices
Multikernel Design and Implementation for Improving Responsiveness of Aperiodic Tasks
Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain
Exploring Discriminability of Categorical Anchors for Heterogeneous Domain Adaptation
Lightweight Semantics-Preserving Communication for Real-Time Automotive Software
Innovative Battery Management System: Towards Sustainable Energy Solutions for Electrical Gadgets
Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on Many-core CPUs
Acceleration of DNN-based Hand Pose Estimation with Monocular Camera Using TVM
Dynamic Hand Gesture Recognition Using Effective Feature Extraction and Attention Based Deep Neural Network
Symbols and Rules for a Self-Explanatory Machine Model
Multi-decision Making Based PSO Optimization in Airborne Mobile Sensor Network Deployment
Unleashing Python's Power Inside Oracle: A New Era of Machine Learning with OML4Py
Autotuning of a Cut-Off for Task Parallel Programs
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems
Stackelberg Game Theoretic Approach for Probabilistic Network Coding in Retransmission Mechanism
Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication
On-Chip Lifetime Prediction for Dependable Many-Processor SoCs Based on Data Fusion
Autonomous Driving Robot Using FPGA and BNN with Random Forest
Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes
Tumour Detection using Convolutional Neural Network on a Lightweight Multi-Core Device
2QoSM: A Q-Learner QoS Manager for Application-Guided Power-Aware Systems
Implementation and Modeling for High-performance I/O Hub Used in SPARC M7 Processor-Based Servers
Complex Human Activities Recognition Based on High Performance 1D CNN Model
Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems
IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration
Deep Learning Framework with Arbitrary Numerical Precision
Data and Commands Communication Protocol for Neuromorphic Platform Configuration
Design of a Safety Confirmation System Integrating Wireless Sensor Network and Smart Phones for Disaster
A Novel Approach to Precision Diagnosis of Multiple Sclerosis Brain Lesions Utilizing a Convolutional-based Ensemble Classification Approach for Embedded Systems
Scale Up while Scaling Out Microservices in Video Analytics Pipelines
Systolic Array Based Convolutional Neural Network Inference on FPGA
Performance on SIMD architectures of auto-tuned programs for matrix multiplication
A Real-Time Fault-Tolerant and Power-Efficient Multicore System on Chip
Towards Automatic Code Generation of Run-Time Power Management for Embedded Systems Using Formal Methods
A novel fire monitoring system for electric bicycle shed based on YOLOv8
Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip
Highly Efficient MetaFormer-Based End-to-End Autonomous Driving Model With Token-Pruning
Intelligent congestion control for NoC architecture in Gem5 simulator
Survey of Hardware Acceleration of Genomic Analysis
Going beyond Mean and Median Programs Performances
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications
A Lightweight Action Recognition Method for Deployable Embedded Devices for Human-Computer Interaction
A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture
Execution Right Delegation Scheduling Algorithm for Multiprocessor
A Benes Based NoC Switching Architecture for Mixed Criticality Embedded Systems
Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks
Kernel-Level Dropout for the Convolution Process in Deep Learning
Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator
Clustering-Based Image Registration of Tubule Candidates in Breast Histopathology Images
Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis
A Realization of IO Physical Memory Protection for RISC-V Systems
The Role of Linear Discriminant Analysis for Accurate Prediction of Breast Cancer
FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems
Distributed Neural Network with TensorFlow on Human Activity Recognition Over Multicore TPU
Text Self-Supervision Enhances Visual-Language Learning for Person Re-Identification
Building Scalable and Highly Efficient Accelerators Near the End of Conventional Scaling
Impact of Programming Language Skills in Programming Learning
Phase Distribution Parameter Prediction Using Logistic Model in the Analysis of Two-Phase Flow
Freeze-Safe IoT Hibernation using Power Profile Monitor Based on Communication-Centric Auto-Tuning
Sparse Matrix Ordering Method with a Quantum Annealing Approach and its Parameter Tuning
3D Shared Bus Architecture Using Inductive Coupling Interconnect
Designing Application-Specific Heterogeneous Architectures from Performance Models
Numerical Simulation of 3-D Elastic Moduli with Elliptical Cracks Using FM-DBEM
Why Race-to-Finish is Energy-Inefficient for Continuous Multimedia Workloads
Automatic Glossing Services for E-learning Cloud Environments
11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2017, Seoul, South Korea, September 18-20, 2017
An Image Recognition System for Multiple Video Inputs over a Multi-FPGA System
Patient Similarity using Electronic Health Records and Self-supervised Learning
A Novel SLM-Based Virtual FPGA Overlay Architecture
Deep Learning-Driven Video Summarization on the Cloud: A Pathway to Efficient Storage and Quick Access
Efficient Resource Shared RISC-V Multicore Processor
Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling
A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU
Managing the Latency of Data-Dependent Tasks in Embedded Streaming Applications
Distributed O(N) Linear Solver for Dense Symmetric Hierarchical Semi-Separable Matrices
Energy-Aware Bio-signal Compressed Sensing Reconstruction: FOCUSS on the WBSN-Gateway
FPGA Accelerated Decentralized Reinforcement Learning for Anomaly Detection in UAV Networks
Cross by Pass-Mesh Architecture for On-chip Communication
Adaptation of XAI to Auto-tuning for Numerical Libraries
GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA
An Efficient Hardware Implementation of Activation Functions Using Stochastic Computing for Deep Neural Networks
Time-Based Least Memory Intensive Scheduling
Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy
MITRACA: A Next-Gen Heterogeneous Architecture
Neuronal population biomarkers of temporal difference learning in human impulsive choices
Ising-Based Combinatorial Clustering Using the Kernel Method
Statistical Analysis for Shared Resources Effects with Multi-Core Real-Time Systems
Mobile Learning with Google App Engine
Survey of Network-on-Chip (NoC) for Heterogeneous Multicore Systems
Adaptive V-Set Cache for Multi-core Processors
Automatic Runtime Customization for Variability Awareness on Multicore Platforms
Text Compression Based on an Alternative Approach of Run-Length Coding Using Burrows-Wheeler Transform and Arithmetic Coding
Enhancing Autotuning Capability with a History Database
Adaptive VC Organization and Arbitration for Efficient NoC Design
Parallel Verification in RISC-V Secure Boot
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters
Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure
A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices
A Network-Friendly Disk I/O Optimization Framework in a Virtualized Cloud System
Mini-Batch Training along Convolution Windows for Representation Learning Based on Spike-Time-Dependent-Plasticity Rule
Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs
A Format for Work Specification
Fake Image Detection Using An Ensemble of CNN Models Specialized For Individual Face Parts
Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter
Appropriate Graph-Algorithm Selection for Edge Devices Using Machine Learning
Power Supply for Submerged Camera as Applied to Environmental Monitoring
Sustainable Transportation Solutions: Advancements in Compressed Air Vehicle Technology
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators
Automatic Text Classification as Relevance Measure for Russian School Physics Texts
Fault Detection and Localization for Network-on-Chips in Mixed-Criticality Systems
Recursive Algorithm FIR Filter Quantization and Low-Cost Structure Optimization Design Based on MATLAB and Simulink
A Stacked FPGA utilizing 3D-SRAM with Latency Optimization
Implementation of Edge-cloud Cooperative CNN Inference on an IoT Platform
2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores
The Approximate Discrete Radon Transform: A Case Study in Auto-Tuning of OpenCL Implementations
A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process
Representing Contiguity in Page Table for Memory Management Units
A systematic review of machine learning techniques in online learning platforms
An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips
Lifetime Estimation for Core-Failure Resilient Multi-Core Processors
The Case for Coherence Directories in Memory Cubes
Light-weight Enhanced Semantics-Guided Neural Networks for Skeleton-Based Human Action Recognition
A Novel Supervised Distributed Dictionary Learning based on Learned K-SVD for Image Denoising
IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2015, Turin, Italy, September 23-25, 2015
Sparse Matrix-Vector Multiplication with Reduced-Precision Memory Accessor
Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment
Trends and Challenges in Ensuring Security for Low-Power and High-Performance Embedded SoCs
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
AttFallNet : Attention-Guided Fall Detection System Using Improved YOLOv8 Network
Pushing the Limits of Online Auto-Tuning: Machine Code Optimization in Short-Running Kernels
An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA
A Scalable JPEG Encoder on a Many-Core Array
An Ensemble Approach for Stroke Prediction
Nature-inspired Dragonfly Algorithm for High-Performance and Energy-Efficient Mapping of Deep Neural Networks in Networks-on-Chip
FPGA-Based Implementation of the Stereo Matching Algorithm Using High-Level Synthesis
MAO: Memory Architecture Obfuscation
Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research
Use of Ball-based Movement for Omnidirectional Collaborative Carry Robot Systems
An Efficient Bandit Learning for Matching based Distributed Task Offloading in Fog Computing Network
GRONA : A Framework for Gather-and-Reduce On Near-Memory Accelerators
Algorithm to Determine Extended Edit Distance between Program Codes
A Energy-Efficient Re-configurable Multi-mode Convolution Neuron Network Accelerator
A Performance Evaluation of Multi-programming Model on a Multicore System with Virtual Machines
A Lightweight Folded Keccak-Based SHA-3 for Resource-Constrained Embedded Security
KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores
A Multicore Architecture for High-Performance Scientific Computing Using FPGAs
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
Meta-programming and Multi-stage Programming for GPGPUs
Exploration of an Enhanced Scheduling Approach with Feasibility Analysis on a Single CPU System
A Low Cost and Portable Mini Motor Car System with a BNN Accelerator on FPGA
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation
An Approach to Customization of Compiler Directives for Application-Specific Code Transformations
A Lightweight End-to-end Network for Wearing Mask Recognition on Low-resolution Images
Scalability of Post-Silicon Test Generation for Multi-core RISC-V SOC Validation
Iterative Refinement Quantum Amplitude Estimation
A Toolchain for Deterministic Parallelism on an Embedded Bare-metal Platform
Memory Access Analysis of Many-core System with Abundant Bandwidth
A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors
CNN-based End-to-end Autonomous Driving on FPGA Using TVM and VTA
Privacy-stealing Approach in Distributed IoMT Systems
IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012
SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card
LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures
Harnessing the Power of GenAI tools: Evaluating Response as an Approach to Learning
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach
A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference
Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion
Interlinked Chain Method for Blockchain-Based Collaborative Learning in Vehicular Networks
A Practical High Efficiency Video Coding Solution for Visual Sensor Network using Raspberry Pi Platform
External Memory Breadth-First Search with Delayed Duplicate Detection on the GPU
Model Checking and Artificial Intelligence - 6th International Workshop, MoChArt 2010, Atlanta, GA, USA, July 11, 2010, Revised Selected and Invited Papers
Verifying Robocup Teams
Symbolic Model Checking the Knowledge in Herbivore Protocol
A Symbolic Model Checking Framework for Safety Analysis, Diagnosis, and Synthesis
Relaxation Refinement: A New Method to Generate Heuristic Functions
Solving µ-Calculus Parity Games by Symbolic Planning
A Framework for Model Checking Institutions
The Blowup in Translating LTL to Deterministic Automata
Symbolic Model Checking of Logics with Actions
Using Predicate Abstraction to Generate Heuristic Functions in UPPAAL
Verifying Time and Communication Costs of Rule-Based Reasoners
Program Model Checking via Action Planning
Bounded Model Checking Real-Time Multi-agent Systems with Clock Differences: Theory and Implementation
Model Checking Strategic Equilibria
Distributed Extended Beam Search for Quantitative Model Checking
Towards Partial Order Reduction for Model Checking Temporal Epistemic Logic
Survey on Directed Model Checking
Real-Time Model Checking on Secondary Storage
Proceedings of the Third Workshop on Model Checking and Artificial Intelligence, MoChArt@CONCUR/SPIN 2005, San Francisco, CA, USA, August 27, 2005
Automated Creation of Pattern Database Search Heuristics
Verifying Space and Time Requirements for Resource-Bounded Agents
SAT-Based Verification of Security Protocols Via Translation to Networks of Automata
Automatic Data-Abstraction in Model Checking Multi-Agent Systems
Automated Testing of Planning Models
Checking Liveness Properties of Concurrent Systems by Reinforcement Learning
Automated Verification of Resource Requirements in Multi-Agent Systems Using Abstraction
Improved Bounded Model Checking for a Fair Branching-Time Temporal Epistemic Logic
Scaling Search with Pattern Databases
Model Checking Driven Heuristic Search for Correct Programs
Model Checking and Artificial Intelligence, 4th Workshop, MoChArt IV, Riva del Garda, Italy, August 29, 2006, Revised Selected and Invited Papers
Model Checking and Artificial Intelligence, 5th International Workshop, MoChArt 2008, Patras, Greece, July 21, 2008. Revised Selected and Invited Papers
Planning with Incomplete Information - (Invited Paper)
Experimental Evaluation of a Planning Language Suitable for Formal Verification
Industrial Spectrophotometric Smart Sensor Towards Real-Time Optimization of Textile Dyeing Process
High Resolution Interferometric Temperature Compensation Using Optical Fibers with Different Temperature Coefficients
Characterization of circular array current transducers
Application of capacitive-based contact sensing for a new medical instrument
Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs
Mass and Inertia Estimation Using All-Accelerometer
Coupling Study in a 2D Gimbal-less Quasi-static Piezoelectrically-Actuated MEMS Mirror
Real-time LiDAR module with 64x128-pixel CMOS SPAD array and 940-nm PCSEL
Red Light Running Prediction System using LIDAR
Comparison of Deep Learning and Signal Processing Methods for Removing a Ringing Artifact from Ultrasound Signals
Analysis of output signals of angular position sensors for the use of neural networks
Study on a telemetrie system that works with an inkjet-printed resistive strain gauge
Model fusion for inertial-based personal dead reckoning systems
Development of a wireless sensor network based on electrochemical sensing nodes for smart hydroponic culture
Surface Imprinted Electroimpedance Biosensor for Detecting α-Synuclein for Parkinson's Disease
Sensing and processing of bio-metric signals for use in low cost bio-robotic systems
Traffic Level Monitoring in Urban Scenarios with Virtual Sensing Techniques Enabled by Embedded Machine Learning
Localisation of a sound source in different positions using Kinect sensors
Concept Drift Mitigation on Resource-Constrained IoT Devices via Self-Learning
Embedded platform-based system for early detection of Alzheimer disease through transcranial magnetic stimulation
A Portable Electrochemical Measurement Platform for Wearable-Flexible Sweat Sensors
The error compensation for static hysteresis characteristics of Giant Magneto-Resistance sensor
Measurement setup for industrial communication techniques under electromagnetic interference
Fabrication and characterization of magnetic composite membrane pressure sensor
Microstrip line as microwave tag sensor for monitoring and IoT applications
Monitored Versus Non-Monitored Stimuli in Brain-Computer-Interface Methods for Classifying Workload States During Piloting Tasks
Glucose sensing electrode system based on polymeric microneedles
Reference broadcast frame synchronization for distributed high-speed camera network
Flame-Millimeter-Wave-Interactions: A Radar-Based Sensor Concept
Array of Linear and Nonlinear Electrostatic Energy Harvesters for Broadband Energy Harvesting