yusuke1997/dblp-id-title huggingface dataset:
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices
Network initialization in a switch-level simulator
Minimum Time Maximum Fault Coverage Testing of Spiking Neural Networks
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration
MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis
Energy optimization in Android applications through wakelock placement
FIXER: Flow Integrity Extensions for Embedded RISC-V
Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing
COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators
QBLK: Towards Fully Exploiting the Parallelism of Open-Channel SSDs
Realizable Reduction for Electromagnetically Coupled RLMC Interconnects
Automated critical device identification for configurable analogue transistors
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits
Automated data analysis solutions to silicon debug
Designing Self Test Programs for Embedded DSP Cores
Optimization of the bias current network for accurate on-chip thermal monitoring
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
Simulation-Directed Invariant Mining for Software Verification
Solving graph optimization problems with ZBDDs
Machine learning enabled power-aware Network-on-Chip design
EILID: Execution Integrity for Low-end IoT Devices
Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis
Multi-Partner Project: Green.Dat.AI: A Data Spaces Architecture for Enhancing Green AI Services
Predictive dynamic thermal and power management for heterogeneous mobile platforms
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction
RTL Design Framework for Embedded Processor by using C++ Description
A discrete thermal controller for chip-multiprocessors
PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architecture
Timing Verification with Crosstalk for Transparently Latched Circuits
Throughput optimization and resource allocation on GPUs under multi-application execution
BMC+Fuzz: Efficient and Effective Test Generation
IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design
Self-Checking Scheme for the On-Line Testing of Power Supply Noise
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA
The Modelling of Embedded Systems Using HASoC
Embedded software testing: What kind of problem is this?
TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal Attacks
Dynamic software randomisation: Lessons learnec from an aerospace case study
Resistive Bloom filters: From approximate membership to approximate computing with bounded errors
Post-synthesis leakage power minimization
Formulation of SOC Test Scheduling as a Network Transportation Problem
SOC Testing Methodology and Practice
Exploration and design of embedded systems including neural algorithms
A Parallel LCC Simulation System
ezRealtime: A Domain-Specific Modeling Tool for Embedded Hard Real-Time Software Synthesis
Fast-prototyping using the BTnode platform
Battery-supercapacitor hybrid system for high-rate pulsed load applications
A utility-driven data transmission optimization strategy in large scale cyber-physical systems
A file-system-aware FTL design for flash-memory storage systems
Exploiting special-purpose function approximation for hardware-efficient QR-decomposition
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion
Synthesis with Explicit Dependencies
A Comparing Study of Technology Mapping for FPGA
On-chip fingerprinting of IC topology for integrity verification
ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Spintronic devices as key elements for energy-efficient neuroinspired architectures
CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs
Fast STA Graph Partitioning Framework for Multi-GPU Acceleration
Exploiting on-chip power management for side-channel security
Towards a firmware TPM on RISC-V
A thermally-aware energy minimization methodology for global interconnects
Combining Fault-Injection with Property-Based Testing
An operation rearrangement technique for power optimization in VLIM instruction fetch
Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
An efficient decoupling capacitance optimization using piecewise polynomial models
Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts
Advanced spintronic memory and logic for non-volatile processors
Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs
A Parallel Tempering Processing Architecture with Multi-Spin Update for Fully-Connected Ising Models
Panel: What does the power industry need from the EDA industry and what is the EDA industry doing about it?
A digital processor architecture for combined EEG/EMG falling risk prediction
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators
ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies
Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs
Low Power Oriented CMOS Circuit Optimization Protocol
Scoped identifiers for efficient bit aligned logging
FBLT: a real-time contention manager with improved schedulability
Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day)
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
A New Crosstalk Noise Model for DOMINO Logic Circuits
Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications
Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC)
Statistical Profiling of Micro-Architectural Traces and Machine Learning for Spectre Detection: A Systematic Evaluation
Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory
ASNPC: An Automated Generation Framework for SNN and Neuromorphic Processor Co-Design
Programming MPSoC platforms: Road works ahead!
A diagnosis algorithm for extreme space compaction
A Scalable Mixed Synthesis Framework for Heterogeneous Networks
Towards High-Throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs
Selecting the Optimal Energy Point in Near-Threshold Computing
Nubolic Simulation of AMS Systems with Data Flow and Discrete Event Models
Automatic insertion of low power annotations in RTL for pipelined microprocessors
EASY - a System for Computer-Aided Examination of Analog Circuits
A portable multi-pitch e-drum based on printed flexible pressure sensors
Reliable Services in an Imperfect World
FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption
A Hardware-Friendly Wavelet Entropy Codec for Scalable Video
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits
Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning
A new hybrid solution to boost SAT solver performance
RTLock: IP Protection using Scan-Aware Logic Locking at RTL
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications
High Speed GaAs Subsystem Design using Feed Through Logic
Testing Robustness of Homomorphically Encrypted Split Model LLMs
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning
DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture
Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications
Fast and lightweight support for nested parallelism on cluster-based embedded many-cores
ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs
Performance analysis of multimedia applications using correlated streams
TOP: An Algorithm for Three-Level Optimization of PLDs
On the verification of automotive protocols
RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification
Improving fault tolerance utilizing hardware-software-co-synthesis
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection †
Superword level parallelism aware word length optimization
Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing
Predictive Modeling and Design Automation of Inorganic Printed Electronics
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis
Digital bit stream jitter testing using jitter expansion
uSFI: Ultra-lightweight software fault isolation for IoT-class devices
Overcoming post-silicon validation challenges through quick error detection (QED)
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors
General floorplanning methodology for 3D ICs with an arbitrary bonding style
MAPS: Multi-Fidelity AI-Augmented Photonic Simulation and Inverse Design Infrastructure
REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs
When to stop verification?: Statistical trade-off between expected loss and simulation cost
Qualification and testing process to implement anti-counterfeiting technologies into IC packages
Fast and accurate BER estimation methodology for I/O links based on extreme value theory
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations
Optimizing Data Migration for Garbage Collection in ZNS SSDs
BreachFlows: Simulation-Based Design with Formal Requirements for Industrial CPS (Extended Abstract)
Register Transfer Level VHDL Models without Clocks
Bitstream processing for embedded systems using C++ metaprogramming
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
FARM: Fault-aware resource management in NoC-based multiprocessor platforms
A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators
Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach
Impact of process-variations in STTRAM and adaptive boosting for robustness
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors
Speed optimization for tasks with two resources
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction
CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks
Power and Timing Modeling for ASIC Designs
Discovering Efficient Fused Layer Configurations for Executing Multi-Workloads on Multi-Core NPUs
An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention Time
A Fail-safe Architecture for Automated Driving
Probabilistic State-Based RT-Analysis of SDFGs on MPSoCs with Shared Memory Communication
Formal verification of systemc designs using a petri-net based representation
Correlation between I DDQ testing quality and sensor accuracy
Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays
Register pointer architecture for efficient embedded processors
Defining Cost Functions for Robust IC Design and Optimization
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC
Low-cost protection for SER upsets and silicon defects
Cache conscious data layout organization for embedded multimedia applications
Dynamic scratch-pad memory management for irregular array access patterns
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis
Multi-Node Static Logic Implications for Redundancy Identification
LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog Generation
Hierarchical Characterization of Analog Integrated CMOS Circuits
Embedded Tutorial - ARTEMIS and ENIAC Joint Undertakings: A New Approach to Conduct Research in Europe
Automated construction of fast and accurate system-level models for wireless sensor networks
d 2 -LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Abstract state machines as an intermediate representation for high-level synthesis
Design space exploration of FPGA accelerators for convolutional neural networks
Monomorphism-Based CGRA Mapping Via Space and Time Decoupling
Efficient neural network acceleration on GPGPU using content addressable memory
A calculator for Pareto points
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability
Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building
Decentralized Non-Neighbor Active Charge Balancing in Large Battery Packs
Advanced Optimistic Approaches in Logic Simulation
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs
IP is All About Implementation and Customer Satisfaction
Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis
Improving LLM-Based Verilog Code Generation with Data Augmentation and RL
Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip
Realization of a Virtual Lambda Sensor on a Fixed Precision System
Micro-Network for SoC: Implementation of a 32-Port SPIN network
Using non-volatile memory to save energy in servers
A System-Level Co-Verification Environment for ATM Hardware Design
Minimizing Execution Duration in the Presence of Learning-Enabled Components
On diagnosis of multiple faults using compacted responses
WISER: Deep Neural Network Weight-bit Inversion for State Error Reduction in MLC NAND Flash
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines
REACT: Randomized Encryption with AI-Controlled Targeting for Next-Gen Secure Communication
Video Processing Requirements on SoC Infrastructures
Scan Power Minimization through Stimulus and Response Transformations
Debugging of Toffoli networks
On the use of reset to increase the testability of interconnected finite-state machines
State of health aware charge management in hybrid electrical energy storage systems
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer
Development and Application of Design Transformations in ForSyDe
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design
Generation of complex quantum states via integrated frequency combs
Semiconductor technologies for smart mobility management
Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks
Improving reliability for real-time systems through dynamic recovery
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach
Giant spin hall effect (GSHE) logic design for low power application
Cache coherence enabled adaptive refresh for volatile STT-RAM
Verification of the RF Subsystem within Wireless LAN System Level Simulation
XiNet-pose: Extremely Lightweight Pose Detection for Microcontrollers
Automated synthesis of compact crossbars for sneak-path based in-memory computing
Startup error detection and containment to improve the robustness of hybrid FlexRay networks
Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN
Federated Reinforcement Learning for Optimizing the Power Efficiency of Edge Devices
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels
A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip
Efficient Hardware-assisted Out-place Update for Persistent Memory
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems
Cycle-based Simulation with Decision Diagrams
Exploiting Crosstalk to Speed up On-Chip Buse
Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning
Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation
A cost-effective substantial-impact-filter based method to tolerate voltage emergencies
Minimizing stack memory for hard real-time applications on multicore platforms
A new approach to compress the configuration information of programmable devices
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
An Automated Flow to Map Throughput Constrained Applications to a MPSoC
A Resource Estimation and Verification Workflow in Q# Special session paper
Power Estimation of Behavioral Descriptions
Fast Kriging-based Error Evaluation for Approximate Computing Systems
Using Counter Example Guided Abstraction Refinement to Find Complex Bugs
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA
Securing Cryptographic Circuits by Exploiting Implementation Diversity and Partial Reconfiguration on FPGAs
Decomposition of Instruction Decoder for Low Power Design
AntiDote: Attention-based Dynamic Optimization for Neural Network Runtime Efficiency
Quantum computing with CMOS technology
Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip
Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAs
Optimized Timed Hardware Software Cosimulation without Roll-back
A Throughput-Latency Co-Optimised Cascade of Convolutional Neural Network Classifiers
Real-time trust evaluation in integrated circuits
A UML-Based Design Methodology for Real-Time and Embedded Systems
A systematic approach to automated construction of power emulation models
Scenario-based analysis and synthesis of real-time systems using uppaal
Dynamic power management under uncertain information
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array
Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits
System-assisted analog mixed-signal design
Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation
Cloud-assisted control of ground vehicles using adaptive computation offloading techniques
The Real-Time UML Standard: Definition and Application
Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications
A schedulability test for software migration on multicore system
Mask-cost-aware ECO routing ∗
FlexENM: A Flexible Encrypting-Near-Memory with Refresh-Less eDRAM-Based Multi-Mode AES
A novel background subtraction scheme for in-camera acceleration in thermal imagery
Scan based methodology for reliable state retention power gating designs
Ferroelectric-Superconducting Synergy for Future Computing
RETLab: A fast design-automation framework for arbitrary RET networks
A Coupled Battery State-of-Charge and Voltage Model for Optimal Control Applications
A Novel Unified Architecture for Public-Key Cryptography
Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks
Operation Dependency Graph-Based Scheduling for High-Level Synthesis
Design of Routing-Constrained Low Power Scan Chains
ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training
Model-Based-Design Is Nice But..
Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems
System Theoretic View on Uncertainties
An integrated system-on-chip test framework
Memcomputing: The cape of good hope: [Extended special session description]
The UP2DATE Baseline Research Platforms
Efficient unknown blocking using LFSR reseeding
minFlash: A minimalistic clustered flash array
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis
Reliability-aware design method for CMOS circuits
CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer
Automatic Generation of Complex Properties for Hardware Designs
TPC-GAN: Batch Topology Synthesis for Performance-Compliant Operational Amplifiers Using Generative Adversarial Networks
A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters
Enhanced Q-learning algorithm for dynamic power management with performance constraint
Thermal and Power Integrity Based Power/Ground Networks Optimization
Performance evaluation and design trade-offs for wireless-enabled SMART NoC
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem
Efficient Resource Arbitration in Reconfigurable Computing Environments
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells
Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014
M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors
Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis
Thermal-aware TSV repair for electromigration in 3D ICs
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems
MUSCAT: MUS-based Circuit Approximation Technique
Increasing the power efficiency of PCs by improving the hardware/OS interaction
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology
CARbridge, Reduction of System Complexity by Standardisation of the System-Basis-Chips for Automotive Applications
RAM-Based FPGA's: A Test Approach for the Configurable Logic
Improved sequential ATPG using functional observation information and new justification methods
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding
MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
Towards low power approximate DCT architecture for HEVC standard
SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space
A hybrid framework for design and analysis of fault-tolerant architectures
ENASA: Towards Edge Neural Architecture Search based on CIM acceleration
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
DFM/DFY: should you trust the surgeon or the family doctor?
AutoVision: flexible processor architecture for video-assisted driving