yusuke1997/dblp-id-title huggingface dataset:
LOGEX - an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology
Improved global routing through congestion estimation
Requirements for a Practical Software Engineering Environment
Power modeling of graphical user interfaces on OLED displays
A STT-RAM-based low-power hybrid register file for GPGPUs
Hierarchical Functional Timing Analysis
Executing synchronous dataflow graphs on a SPM-based multicore architecture
Diagnostic system for large scale logic cards and LSI'S
Common feature techniques for discrete optimization
Yale school of architecture
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing
Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions
A Generalized Interconnect Model for Data Path Synthesis
Application level hardware tracing for scaling post-silicon debug
Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization
Enabling Dynamic Heterogeneity Through Core-on-Core Stacking
Automated accelerator generation and optimization with composable, parallel and pipeline architecture
Generating essential primes for a Boolean function with multiple-valued inputs
Enabling energy efficiency in via-patterned gate array devices
Computer aided centrifugal pump design
Are logic synthesis tools robust?
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization
Efficient equivalence checking with partitions and hierarchical cut-points
A fault simulation methodology for VLSI
Supervised design space exploration by compositional approximation of Pareto sets
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation
Using general-purpose programming languages for FPGA design
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction
Exploiting input information in a model reduction algorithm for massively coupled parasitic networks
LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator
Generating ECAD Framework Code from Abstract Models
The future of computer applications in the architectural profession
A Real-time Execution System of Multimodal Transformer through PIM-GPU Collaboration
SAW: system-assisted wear leveling on the write endurance of NAND flash devices
DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency
DAS: An automated system to support design analysis
SPIE: Sparse Partial Inductance Extraction
Energy harvesting and power management for autonomous sensor nodes
Initial placement of gate arrays using least-squares methods
Soft connections: addressing the hardware-design modularity problem
Near-threshold voltage (NTV) design: opportunities and challenges
Seeking the Yield Barrier: High-Dimensional SRAM Evaluation Through Optimal Manifold
Optimisation of global routing for the UK5000 gate array by iteration
PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System
BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
Gate Matrix Layout Synthesis with Two-Dimensional Folding
Design of asynchronous circuits by synchronous CAD tools
A Framework for the Validation of Processor Architecture Compliance
A 1.3GHz fifth generation SPARC64 microprocessor
A new canonical form for fast boolean matching in logic synthesis and verification
Re 4 PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel Attacks
Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch
Accelerated Transition Fault Simulation
SALOGS-IV-A program to perform logic simulation and fault diagnosis
Lightning Talk: Model, Framework and Integration for In-Storage Computing with Computational SSDs
MARSS: a full system simulator for multicore x86 CPUs
An integer arithmetic path expansion algorithm
Synthesis by Spectral Translation Using Boolean Decision Diagrams
Synergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing Optimization
WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms
Sciduction: combining induction, deduction, and structure for verification and synthesis
Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security
ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen Processors
Statistical techniques of timing verification
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
One-chip Bluetooth ASIC Challenges
Overview of an Arithmetic Design System
Design-process integration for performance-based OPC framework
On the optimum two-dimensional allocation problem
Embedding infrastructure IP for SOC yield improvement
Abstract Routing of Logic Networks for Custom Module Generation
A High Performance Routing Engine
MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems
Computer aided design of microprocessor-based systems
Validation of an Architectural Level Power Analysis Technique
Tutorial - mechanical workstation software computer aided engineering in the mechanical design process
EFFEX: an embedded processor for computer vision based feature extraction
A 242mW, 10mm 2 1080p H.264/AVC high profile encoder chip
Exploiting spatiotemporal and device contexts for energy-efficient mobile embedded systems
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine
REAL: a program for REgister ALlocation
Match-making for monolithic 3D IC: finding the right technology node
Computation Offloading by Using Timing Unreliable Components in Real-Time Systems
BLITZCRANK: Factor Graph Accelerator for Motion Planning
A preprocessor for channel routing
Tools and Methodologies for Low Power Design
Fault modeling in a hierarchical simulator
High-level current macro-model for power-grid analysis
Detachable nano-carbon chip with ultra low power
Practical repeater insertion for low power: what repeater library do we need?
On Bit-level Reverse Engineering of Vehicular CAN Bus
Graphics language / one - IBM Corporate-Wide physical design data format
Large-scale placement by grid-warping
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization
Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System
SECRET: smartly EnCRypted energy efficient non-volatile memories
Complex library mapping for embedded software using symbolic algebra
Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFs
Design tools for BioMEMS
An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits
A probabilistic scheduling framework for mixed-criticality systems
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control
ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids
Pref-X: a framework to reveal data prefetching in commercial in-order cores
Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support
VarSim: A Fast and Accurate Variability and Leakage Aware Thermal Simulator
CAD tools for variation tolerance
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study
Percolation Based Synthesis
CMOS: a paradigm for low power wireless?
Attacking Split Manufacturing from a Deep Learning Perspective
Test generation costs analysis and projections
The ITRS design technology and system drivers roadmap: process and status
KFR: Optimal Cache Management with K-Framed Reclamation for Drive-Managed SMR Disks
Programming for FORTRAN compatibility and machine independence
Automated Design Software for Switched-Capacitor IC's with Symbolic Simulator SCYMBAL
Practical experiences from signal probability simulation of digital designs
Computer-aided assignment of manufacturing tolerances
Shared reconfigurable fabric for multi-core customization
Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints
A maximal resolution guided-probe testing algorithm
Circuit simulation based obstacle-aware Steiner routing
WEAVER: a knowledge-based routing expert
Path smoothing via discrete optimization
ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator
CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism
Organized C: A Unified Method of Handling Data in CAD Algorithms and Databases
Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-Chip
Programming challenges & solutions for multi-processor SoCs: an industrial perspective
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks
Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation
An interactive computer graphics space allocation system
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration
What to do about the end of Moore's law, probably!
PHOENIX: Pauli-Based High-Level Optimization Engine for Instruction Execution on NISQ Devices
Noise-Robust Deep Spiking Neural Networks with Temporal Information
On the Circuit Implementation Problem
Towards Efficient Convolutional Neural Network for Embedded Hardware via Multi-Dimensional Pruning
Distributed sleep transistor network for power reduction
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Fast three-level logic minimization based on autosymmetry
Predicting timing violations through instruction-level path sensitization analysis
Transient-simulation guided graph sparsification approach to scalable harmonic balance (HB) analysis of post-layout RF circuits leveraging heterogeneous CPU-GPU computing systems
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
A solenoidal basis method for efficient inductance extraction
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking
FAR-DS: Full-Plane AWE Routing with Driver Sizing
DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design
GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data Parallel Architectures
Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors
Designing ML-resilient locking at register-transfer level
The larger the fairer?: small neural networks can achieve fairness for edge devices
Data Path Tradeoffs Using MABAL
SHIELD: a software hardware design methodology for security and reliability of MPSoCs
A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation
IC specification language
Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion
Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based Designs
A High Level Approach to Co-Designing 3D ICs
WIDAS - Wiring Diagram Assembly System
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Computer-aided circuit layout and design
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices
Layout Optimization of CMOS Functional Cells
A multilayer nanophotonic interconnection network for on-chip many-core communications
Simple metrics for slew rate of RC circuits based on two circuit moments
Relaxation and Clustering in a Local Search Framework: Application to Linear Placement
New Models for Four- and Five-Layer Channel Routing
An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systems
Metasystem: A hierarchically structured graphic tool
NoiseZO: RRAM Noise-Driven Zeroth-Order Optimization for Efficient Forward-Only Training
A new LP based incremental timing driven placement for high performance designs
Defining the bounding edges of a SynthaVision solid model
Modeling crosstalk in statistical static timing analysis
PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation
LOFFS: A Low-Overhead File System for Large Flash Memory on Embedded Devices
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression
Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation
ALICE: an automatic design flow for eFPGA redaction
BOLT-a block oriented design specification language
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems
Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery
Efficient Prime Factorization of Logic Expressions
To split or to conjoin: the question in image computation
In-Place Power Optimization for LUT-Based FPGAs
Abstraction of RTL IPs into embedded software
Hardware-Assisted Fine-Grained Control-Flow Integrity: Towards Efficient Protection of Embedded Systems Against Software Exploitation
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
Gate sizing: finFETs vs 32nm bulk MOSFETs
A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults
Improving Standard-Cell Design Flow using Factored Form Optimization
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System
An updated multilayer printed wiring C-A-D capability
Delay and slew metrics using the lognormal distribution
Maximum Current Estimation in CMOS Circuits
A topologically adaptable cellular router
Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model
Panel: The Electronics Industry Supply Chain: Who Will Do What?
Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs
A programmable configurator
Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool
Algorithms for Approximate FSM Traversal
WCET-centric partial instruction cache locking
ReSMiPS: A ReRAM-based Sparse Mixed-precision Solver with Fast Matrix Reordering Algorithm
PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators
Response compaction with any number of unknowns using a new LFSR architecture
Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming
Optimization of Combinational Logic Circuits Based on Compatible Gates
Synthesis of Software Programs for Embedded Control Applications
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications
Path delay test compaction with process variation tolerance
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule
Design Methodologies for Noise in Digital Integrated Circuits
Fault detection and diagnosis with parity trees for space compaction of test responses
Chip partitioning aid: A design technique for partitionability and testability in VLSI
A transformation based algorithm for reversible logic synthesis
The Power of Simulation for Equivalence Checking in Quantum Computing
CINNAMON: coupled integration and nodal analysis of MOS networks
An Energy-Efficient Kalman Filter Architecture with Tunable Accuracy for Brain-Computer Interfaces
AUTO CARD automated printed circuit board design
A fully-programmable memory management system optimizing queue handling at multi-gigabit rates
Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System
Prime : A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach
Re-Configurable Computing in Wireless
Multi-frequency wrapper design and optimization for embedded cores under average power constraints
Design rule verification based on one dimensional scans
Government actions to increase CAD software productivity
On the generation of scan-based test sets with reachable states for testing under functional operation conditions
POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage
Capturing Designer Expertise the CGEN System
Generative self-supervised learning for gate sizing: invited
SmartBalance: a sensing-driven linux load balancer for energy efficiency of heterogeneous MPSoCs
Deriving Efficient Area and Delay Estimates by Modeling Layout Tools
Deep Integration of Circuit Simulator and SAT Solver
Predicting electromigration mortality under temperature and product lifetime specifications
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS
Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Test generation for LSI: A case study
AIDE - a tool for computer architecture design
Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks
Selecting and successfully implementing a turnkey computer graphics system
Towards trustworthy medical devices and body area networks
Write performance improvement by hiding R drift latency in phase-change RAM
How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs
Synthesizing Stochasticity in Biochemical Systems
Efficient Communication in a Design Environment
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks
Atomlayer: a universal reRAM-based CNN accelerator with atomic layer computation
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Chameleon: a new multi-layer channel router
A general probabilistic framework for worst case timing analysis
Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network
Operational features of an MOS timing simulator
Modeling adaptive streaming applications with parameterized polyhedral process networks
Topological routing of multi-bit data buses
MO-pack: many-objective clustering for FPGA CAD
Apple vs. EMA: electromagnetic side channel attacks on apple CoreCrypto
An 8x8 run-time reconfigurable FPGA embedded in a SoC
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization
A system modeling language translator
Depth optimal incremental mapping for field programmable gate arrays
Non-cycle-accurate sequential equivalence checking
Helios: Heterogeneity-Aware Federated Learning with Dynamically Balanced Collaboration
Multilevel floorplanning/placement for large-scale modules using B*-trees
A computer-aided minimum cost transfer machine layout design
A framework for embedded system specification under different models of computation in SystemC
FaSe: fast selective flushing to mitigate contention-based cache timing attacks
Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case study
Enabling the Design of Behavioral Systems-on-Chip
AdvHunter: Detecting Adversarial Perturbations in Black-Box Neural Networks through Hardware Performance Counters
SEO: Safety-Aware Energy Optimization Framework for Multi-Sensor Neural Controllers at the Edge
Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009
TinySPICE: a parallel SPICE simulator on GPU for massively repeated small circuit simulations
Path delay analysis for hierarchical building block layout system
NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance
Fault simulation of digital logic utilizing a small host machine
The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm
A Neural Network Design for Circuit Partitioning
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching
MTL-Split: Multi-Task Learning for Edge Devices using Split Computing
A summary of architectural involvement with computers
Camouflage: Hardware-assisted CFI for the ARM Linux kernel
Statistical Design Space Exploration for Application-Specific Unit Synthesis
Design data base configuration control
Scalable Hybrid Verification of Complex Microprocessors
Symbols, graphics and architectural education: The pagan experience
Instant-NeRF: Instant On-Device Neural Radiance Field Training via Algorithm-Accelerator Co-Designed Near-Memory Processing
Magic: A VLSI layout system
Accelerator Design for Deep Learning Training: Extended Abstract: Invited
Optimal Aspect Ratios of Building Blocks in VLSI
CDS: An Anti-Aging Calibratable Digital Sensor for Detecting Multiple Types of Fault Injection Attacks
GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference
Force directed mongrel with physical net constraints
Efficient building block based RTL code generation from synchronous data flow graphs
Re-synthesis for cost-efficient circuit-level timing speculation
VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems
CLIMBER: defending phase change memory against inconsistent write attacks
Techniques for Foundry Identification
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM
Processor Vulnerability Discovery
A CAD system for unified hardware-software design
Comet - a fast component placer
Generating test programs to cover pipeline interactions
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms
ILP-based pin-count aware design methodology for microfluidic biochips
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Refined statistical static timing analysis through
Efficient design space exploration via statistical sampling and AdaBoost learning
GTuner: tuning DNN computations on GPU via graph attention network
Architecture-aware FPGA placement using metric embedding
Fogging Effect Aware Placement in Electron Beam Lithography
Simplifying deep neural networks for neuromorphic architectures
ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance
Future systems-on-chip: software of hardware design? (panel session)
A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks
Catch Your Attention: Quality-retaining Power Saving on Mobile OLED Displays
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits
Cluster Refinement for Block Placement
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology
Automatic generation of breakpoint hardware for silicon debug
High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References
Proceedings of the 9th Design Automation Workshop, DAC '72, Dallas, Texas, USA, June 26-28, 1972
Lightning Talk: Memory-Centric Computing
Branch-and-Bound Placement for Building Block Layout
MAS-ISP: A Proxy-Free Online Hyperparameter Optimization Framework for ISP Hardware System
System level design: six success stories in search of an industry
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Recent advances and future prospects in single-electronics
The Design of High-Performance Microprocessors at Digital
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
DDBDD: Delay-Driven BDD Synthesis for FPGAs
The State of EDA in Russian Universities
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory
Freeze!: A New Approach for Testing Sequential Circuits