yusuke1997/dblp-id-title huggingface dataset:
Multi-Partner Project: CyberSecDome - Framework for Secure, Collaborative, and Privacy-Aware Incident Handling for Digital Infrastructure
Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable Memories
Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs
Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE)
An embedded system remotely driving mechanical devices by P300 brain activity
Experimental validation of a tuning algorithm for high-speed filters
Application independent module generation in analog layouts
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design
Sequence reordering to improve the levels of compaction achievable by static compaction procedures
Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters
Late Breaking Results: SoC-FPGA HW Trojan Leaking Data through EM Covert Channel
Mesh Partitioning Approach to Energy Efficient Data Layout
The Scale4Edge RISC-V Ecosystem
Exact Schedulability Analysis for Limited-Preemptive Parallel Applications Using Timed Automata in UPPAAL
Unearthing the Potential of Spiking Neural Networks
Power Efficiency through Application-Specific Instruction Memory Transformations
Sliding-Mode Control to Compensate PVT Variations in dual core systems
Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems
Logic encryption: A fault analysis perspective
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications
Applying UML and MDA to Real Systems Design
Transition-aware real-time task scheduling for reconfigurable embedded systems
Sparsity-oriented sparse solver design for circuit simulation
BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems
Timing Violation Induced Faults in Multi-Tenant FPGAs
Exploiting narrow-width values for improving non-volatile cache lifetime
Achieving efficient packet-based memory system by exploiting correlation of memory requests
Subsystem Exchange in a Concurrent Design Process Environment
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees
Context-sensitive timing automata for fast source level simulation
Crosstalk noise in future digital CMOS circuits
Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA
An industrial design space exploration framework for supporting run-time resource management on multi-core systems
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure
A Public-Key Watermarking Technique for IP Designs
A New Simulation Technique for Periodic Small-Signal Analysis
Design and optimization of FeFET-based crossbars for binary convolution neural networks
Intelligent and collaborative embedded computing in automation engineering
SGPRS: Seamless GPU Partitioning Real-Time Scheduler for Periodic Deep Learning Workloads
Constructing Minimal Spanning/Steiner Trees with Bounded Path Length
Energy efficiency vs. programmability trade-off: architectures and design principles
Leveraging reconfigurability to raise productivity in FPGA functional debug
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Low-latency wireless 3D NoCs via randomized shortcut chips
Integrated placement and skew optimization for rotary clocking
Reconfigurable implementation of GF(2 m ) bit-parallel multipliers
Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance
Battery-Powered Digital CMOS Design
PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A Pretender
General and efficient Response Time Analysis for EDF scheduling
Temperature-aware scheduler based on thermal behavior grouping in multicore systems
Dolmen: FPGA Swarm for Safety and Liveness Verification
CR&P: An Efficient Co-operation between Routing and Placement
Structural Methods for the Synthesis of Speed-Independent Circuits
Securing Mobile Appliances: New Challenges for the System Designer
On-chip 8GHz non-periodic high-swing noise detector
xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Design of partially parallel scan chain
Monitoring active filters under automotive aging scenarios with embedded instrument
Automatic march tests generations for static linked faults in SRAMs
Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systems
Self-checking architectures for fast Hartley transform
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy
Design and test of fixed-point multimedia co-processor for mobile applications
Embedded Systems' Automation following OMG's Model Driven Architecture Vision
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
Design and implementation of scalable, transparent threads for multi-core media processor
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL
Parametric failure modeling and yield analysis for STT-MRAM
AIRCHITECT v2: Learning the Hardware Accelerator Design Space Through Unified Representations
SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsity
Novel designs for thermally robust coplanar crossing in QCA
Coordinate strip-mining and kernel fusion to lower power consumption on GPU
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems
BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Microcontrollers
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
Towards assertion-based verification of heterogeneous system designs
Flexible specification and application of rule-based transformations in an automotive design flow
A new technique for characterization of digital-to-analog converters in high-speed systems
A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding
Electrical calibration of spring-mass MEMS capacitive accelerometers
Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits
Formal Verification of Secure Boot Process
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
Rapid growth of IP traffic is driving adoption of silicon photonics in data centers
Fault-Tolerant Deep Neural Networks for Processing-In-Memory based Autonomous Edge Systems
A Compiler-Based Approach for Improving Intra-Iteration Data Reuse
Maximizing Impossibilities for Untestable Fault Identification
Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle
Integration of ROP/JOP monitoring IPs in an ARM-based SoC
STT-RAM designs supporting dual-port accesses
QF BV model checking with property directed reachability
Operational fault detection and monitoring of a memristor-based LUT
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits
Static Global Register Allocation for Dynamic Binary Translators
A Flexible Specification Framework for Hardware-Software Codesign
Teleoperation as a Step Towards Fully Autonomous Systems
Innovative energy storage solutions for future electromobility in smart cities
TBERT: Dynamic BERT Inference with Top-k Based Predictors
A cache design for probabilistically analysable real-time systems
Processor/Memory Co-Exploration on Multiple Abstraction Levels
SEU effect analysis in an open-source router via a distributed fault injection environment
A Compiler for Automatic Selection of Suitable Processing-in-Memory Instructions
Non-solution implications using reverse domination in a modern SAT-based debugging environment
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC
Measuring and improving the robustness of automotive smart power microelectronics
SoC: fuelling the hopes of the mobile industry
ViX: Analysis-driven Compiler for Efficient Low-Precision Variational Inference
Strong conflict analysis for propositional satisfiability
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Design as you see FIT: System-level soft error analysis of sequential circuits
HaLo-FL: Hardware-Aware Low-Precision Federated Learning
Real-Time Acoustic Perception for Automotive Applications
Thermal resilient bounded-skew clock tree optimization methodology
Advanced Analog Filters for Telecommunications
Late Breaking Results: Automatic Anomaly Detection Method in Physical Unclonable Functions using Data Mining Techniques
An Improved Multi-Level Framework for Force-Directed Placement
Combining graph-based guidance with error effect simulation for efficient safety analysis
Integrated approach to energy harvester mixed technology modelling and performance optimisation
sLET for Distributed Aerospace Landing System
Aging-aware voltage scaling
Vehicle Sequence Reordering with Cooperative Adaptive Cruise Control
A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era
COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors
Abstraction of word-level linear arithmetic functions from bit-level component descriptions
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection
Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks
Experiences with mobile processors for energy efficient HPC
Implementation and quality testing for compact models implemented in Verilog-A
Can beyond-CMOS devices illuminate dark silicon?
Post-Quantum Secure Boot
Ultra-low power: an EDA challenge
Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States
Improving Chip Design Enablement for Universities in Europe - A Position Paper
Interactive Cosimulation with Partial Evaluation
BACH 2 : Bounded reachability checker for compositional linear hybrid systems
Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach
Black-box leakage power modeling for cell library and SRAM compiler
Sampling-based binary-level cross-platform performance estimation
Predicting best design trade-offs: A case study in processor customization
Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent
RTOS Modeling for System Level Design
Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections
AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform
Timing-Driven Global Placement by Efficient Critical Path Extraction
Simple and General Methods for Fixed-Priority Schedulability in Optimization Problems
Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis
Interactive presentation: Pulse propagation for the detection of small delay defects
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms
Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP
Contactless testing: Possibility or pipe-dream?
Performance verification using partial evaluation and interval analysis
ICE: Inline calibration for memristor crossbar-based computing engine
Reconfigurable data converter as a building block for mixed-signal test
Developing Mesochronous Synchronizers to Enable 3D NoCs
Word-Level Counterexample Reduction Methods for Hardware Verification
Framework for Fault Analysis and Test Generation in DRAMs
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation
Delay Sensitivity Polynomials Based Design- Dependent Performance Monitors for Wide Operating Ranges
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach
Challenges and new trends in probabilistic timing analysis
A time predictable Java processor
Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays
FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation
Packet security with path sensitization for NoCs
From Multi-Level to Abstract-Based Simulation of a Production Line
Evaluating Compiler-Based Reliability with Radiation Fault Injection
GOMIL: Global Optimization of Multiplier by Integer Linear Programming
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults
Reducing writes in phase-change memory environments by using efficient cache replacement policies
Self-Learning and Transfer Across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis
Using Reference Attribute Grammar-Controlled Rewriting for Runtime Resource Management
SecureCloud: Secure big data processing in untrusted clouds
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks
A Reliability Concern on Photonic Neural Networks
Refinement of UML/MARTE models for the design of networked embedded systems
Re-engineering cyber-physical control applications for hybrid communication protocols
Figure of Merit Based Selection of A/D Converters
Surprises in Sequential Redundancy Identification
Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi
C Based Hardware Design for Wireless Applications
3D Embedded multi-core: Some perspectives
Understanding turn models for adaptive routing: The modular approach
Time redundant parity for low-cost transient error detection
A Novel SAT All-Solutions Solver for Efficient Preimage Computation
Less is More: Optimizing Function Calling for LLM Execution on Edge Devices
HOST: HLS Obfuscations against SMT ATtack
Statistical Timing Analysis Using Bounds
Innovative System-level Design Environment Based on FORM for Transport Processing System
A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware
Strengthening Digital Twin Applications based on Machine Learning for Complex Equipment
An Efficient Solar Energy Harvester for Wireless Sensor Nodes
Lightweight and Predictable Memory Virtualization on Medium-Size Microcontrollers
Resilience of Deep Learning Applications: Where We are and Where We Want to Go
Run-Time Management of Logic Resources on Reconfigurable Systems
Precision timed industrial automation systems
Area and Timing Estimation for Lookup Table Based FPGAs
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing
Set variation-aware shared LLC management for CPU-GPU heterogeneous architecture
Stage number optimization for switched capacitor power converters in micro-scale energy harvesting
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors
Mapping mixed-criticality applications on multi-core architectures
SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder
Improving Design and Verification Productivity with VHDL-200x
Enabling HPC for QoS-sensitive applications: The MANGO approach
SAT-Based Quantum Circuit Adaptation
A Programmable Multi-Language Generator for CoDesign
Test Pattern Superposition to Detect Hardware Trojans
Automatic workload generation for system-level exploration based on modified GCC compiler
Technology transfer towards Horizon 2020
A hybrid hierarchical approach for multi-layer global routing
I DDT Testing of Embedded CMOS SRAMs
Large power grid analysis using domain decomposition
A Practical Approach for Bus Architecture Optimization at Transaction Level
Matrix-Vector vs. Matrix-Matrix Multiplication: Potential in DD-based Simulation of Quantum Computations
A Quantization Framework for Neural Network Adaption at the Edge
FPGA-to-CPU Undervolting Attacks
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques
Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011
Improved countermeasure against Address-bit DPA for ECC scalar multiplication
Increasing Accuracy of Timing Models: From CPA to CPA+
Structural design optimization for deep convolutional neural networks using stochastic computing
Energy-efficient neural networks using approximate computation reuse
Reliability analysis for integrated circuit amplifiers used in neural measurement systems
Source level performance simulation of GPU cores
Panel Title: Reconfigurable Computing - Different Perspectives
Functional test generation guided by steady-state probabilities of abstract design
Scalable Sequential Optimization Under Observability Don't Cares
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams
VToT: Automatic Verilog Generation via LLMs with Tree of Thoughts Prompting
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
On the automatic generation of SBST test programs for in-field test
An operational matrix-based algorithm for simulating linear and fractional differential circuits
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
A self-propagating wakeup mechanism for point-to-point networks with partial network support
SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity
Test and Testability Techniques for Open Defects in RAM Address Decoders
Roadmap towards ultimately-efficient zeta-scale datacenters
PathSeeker: A Fast Mapping Algorithm for CGRAs
A methodology for FPGA to structured-ASIC synthesis and verification
Variation-aware task allocation and scheduling for improving reliability of real-time MPSoCs
Power supply and power management in Ubicom
Cross-Layer Interactions in CPS for Performance and Certification
DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks
Energy efficiency in cloud-based MapReduce applications through better performance estimation
An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse
FPGA-based networking systems for high data-rate and reliable in-vehicle communications
L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural Networks
Do Temperature and Humidity Exposures Hurt or Benefit Your SSDs?
A Generic RTOS Model for Real-time Systems Simulation with SystemC
A BDD-based frontend for retargetable compilers
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study
Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs
LESS: Big data sketching and Encryption on low power platform
Battery aware stochastic QoS boosting in mobile computing devices
The Integration of On-Line Monitoring and Reconfiguration Functions using IEEE1149.4 Into a Safety Critical Automotive Electronic Control Unit
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
Power and Thermal Analysis of Commercial Mobile Platforms: Experiments and Case Studies
A set-based mapping strategy for flash-memory reliability enhancement
International Workshop on Engineering Simulations for Cyber-Physical Systems, ES4CPS '14, Dresden, Germany, March 28 - 28, 2014
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems
A modeling method by eliminating execution traces for performance evaluation
MetaRTL: raising the abstraction level of RTL design
RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis
NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices
LZW-Based Code Compression for VLIW Embedded Systems
Symbolic Functional Vector Generation for VHDL Specifications
Verifying safety and liveness for the FlexTM hybrid transactional memory
2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany
How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Taming the component timing: A CBD methodology for real-time embedded systems
A Single-supply True Voltage Level Shifter
Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks
VLSI implementation of SISO arithmetic decoders for joint source channel coding
Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming
UML 2.0 - Overview and Perspectives in SoC Design
Power Savings in Embedded Processors through Decode Filer Cache
Energy-modulated computing
Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing
Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow
On-Sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design
Passive reduced order modeling of multiport interconnects via semidefinite programming
An efficient code compression technique using application-aware bitmask and dictionary selection methods
Towards near-threshold server processors
Comb Frequency Division Multiplexing: A Non-Binary Modulation for AirGap Covert Channel Transmission
High-resolution online power monitoring for modern microprocessors
Run-time phase prediction for a reconfigurable VLIW processor
Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology
State of the art verification methodologies in 2015
Ground Plane Partitioning for Current Recycling of Superconducting Circuits
Timing Modeling with AUTOSAR - Current state and future directions
Fault-tolerant 3-D network-on-chip design using dynamic link sharing
Fault Analysis in Networks with Concurrent Error Detection Properties
Variation aware dynamic power management for chip multiprocessor architectures
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction
Arbiter: Alleviating Concurrent Write Amplification in Persistent Memory
Pushing the number of qubits below the "minimum": Realizing compact boolean components for quantum logic
VESPA: Variability emulation for System-on-Chip performance analysis
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation
Modeling and simulation to the design of SigmaDelta fractional-N frequency synthesizer
Feedback control for providing QoS in NoC based multicores
SLoT: A supervised learning model to predict dynamic timing errors of functional units
Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling
Reconfigurable circuit design with nanomaterials
Massively multi-topology sizing of analog integrated circuits
Combinational Equivalence Checking Using Satisfiability and Recursive Learning
ERSA: Error Resilient System Architecture for probabilistic applications
Towards post-quantum security for IoT endpoints with NTRU
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures
Practical concurrent ASIC and system design and verification
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis
CCR: A concise convolution rule for sparse neural network accelerators
Optimizing dynamic trace signal selection using machine learning and linear programming
DfT schemes for resistive open defects in RRAMs
Energy-Aware System Design for Wireless Multimedia