yusuke1997/dblp-id-title huggingface dataset:
Using Amdahl's Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors
Modulare Multiprozessor-Parallelrechnerarchitektur für ein Fuzzy-System
Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture
Combined Resource and Context Model for QoS-Aware Mobile Middleware
Die Bedeutung interner Datensammlewege für die Rechnerarchitkektur
AEM: Availability Enhancing Middleware - An Approach for Enhancing the Availability of Software Applications
Recording a Complex, Multi Modal Activity Data Set for Context Recognition
CAST: A Processor Architecture for the Efficient Execution of Functional Programs
An Anonymous Efficient Private Set Intersection Protocol for Wireless Sensor Networks
The Impact of Hardware Scheduling Mechanismus on the Performance and Cost of Processor Designs
Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes
Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
A Bluetooth Remote Control System
Flexibles Design von Hochleistungsprotokollen mittels höherer Petri-Netze
Parallelrechnernetzwerke mit zyklischer Topologieumschaltung
Self-adaptive Diagnosis and Reconfiguration in ADNA-Based Organic Computing
A Process Model for Hardware Modules in Reconfigurable System-on-Chip
A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols
MICON-Ein Bausteinsystem für frei konfigurierbare Rechnernetze
An Efficient Data Structure for Dynamic Two-Dimensional Reconfiguration
Invasive MPI on Intel's Single-Chip Cloud Computer
Partial Reconfiguration on FPGAs in Practice - Tools and Applications
Parallel Derivative Computation using ADOL-C
Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware
Über hardware-implementierbare Fehlertoleranz bei industriellen Automatisierungssystemen mit sehr hoch integrierten Prozessoren
Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation
Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings
Das fehlertolerante DELTA-System
Reorganisieren von Basisblöcken für Pipeline-Prozessoren
Ein Rechnerkonzept mit assoziativem Arbeitsspeicher - Programmorganisation
Do Iterative Solvers Benefit from Approximate Computing? An Evaluation Study Considering Orthogonal Approximation Methods
A Flexible Reconfiguration Manager for the Erlangen Slot Machine
Parallel Join Processing on Graphics Processors for the Resource Description Framework
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation
Streamlined Network-on-Chip for Multicore Embedded Architectures
A Ubiquitous Control Architecture for Low Power Systems
Plea for a Holistic Analysis of the Relationship between Information Technology and Carbon-Dioxide Emissions
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen
Simultaneous Speculation Scheduling - Dynamische Parallelisierung
Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's
Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids
MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance
A Short History of Computer System Modeling and Measurements at the University of California, Los Angeles
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence
248 GHz Compact Mixer-Last Direct-Conversion Transmitter with I/Q Imbalance and LO Feedthrough Calibration Capability
A 273.48 TOPS/W and 1.58 Mb/mm 2 Analog-Digital Hybrid CIM Processor with Transpose Ternary-eDRAM Bitcell
Consumer energy portal and home energy management system for smart grid applications
A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation
A single-inductor triple-input-triple-output (SITITO) energy harvesting interface with cycle-by-cycle source tracking and adaptive peak-inductor-current control
A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power Amplifiers
NAS battery system design and allocation for improvement of transient stability ATC
Optimization of vapor compression cycle based on genetic algorithm
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator
Practical Challenges in Supporting Function in Memory
A 1.2GS/s 11b Time-Interleaved SAR ADC with Low-Cost Derivative-Based Background Timing-Skew Calibration and Variable-Load Comparators
Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device
A 152μW -99dBm BPSK/16-QAM OFDM Receiver for LPWAN Applications
An 8.3% Efficiency 96-134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line
A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing Alignment
A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup
A digital MDLL using switched biasing technique to reduce low-frequency phase noise
EnTADRL: Deep Reinforcement Learning System-on-Chip for End-to-End Training Acceleration
Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling
Optimal scheduling of conveyor belt systems under Critical Peak Pricing
A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications
Semiconductor innovation into the next decade
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC
A 43.3 bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale data
A 150-to-1050 GHz Terahertz Detector in 65 nm CMOS
Current status and future prospects of the wind energy
A 16-channel TDM analog front-end with enhanced system CMRR for wearable dry EEG recording
Realizing Direct Convolution in Memory with Systolic-RAM
Design of a common LV switchboard to comply with IEC and UL standards
A Multi-Node Body-Channel-Communication System Using Adaptive Gain Control with ExG Readout ICs for Moving VR Users
Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)
A Fully-Connected Time-Modulated Phased-Array Transmitter Featuring Physical Security Directional Link and Multi-Beam PAPR Reduction
A 7Gb/s SC-FDE/OFDM MMSE equalizer for 60GHz wireless communications
A 3.01 mm 2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm
A repetitive control scheme to improve performance of UPQC under distorted source and nonlinear load conditions
A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method
A 1.92nJ/Conv Pulse-Width Locked-Loop Time Domain Readout IC with VCO-Integrator and Pipeline TDC for Wheatstone Bridge Wearable Strain Sensing System
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology
An $8.73\mathrm{G}\Omega$ Input Impedance VCO-Based Neural Front-End with Autonomous Time-Domain Impedance Boosting Technique and Maximum 0.215s Re-Calibration Time
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler
Interpretation of electrochemical double layer capacitors (Supercapacitors) floating ageing by multi-pore model
ROC-Spin: A 28nm 2, 000 Ring-Oscillator-Collapse Spins for Solving Combinatorial Optimization Problems
ESD Protection is About Circuit Design: Practices and Perspectives
A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition
A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory
A 6.1fJ/conv-step 0.0017mm 2 Level Crossing ADC for Compressive Neural Sensing with Event-Driven Ramp Generation and Sparse DAC Switching Scheme
A 2.7W AC-coupled hybrid supply modulator achieving 200MHz envelope-tracking bandwidth for 5G new radio power amplifier
An 8.1-to-353 TOPS/W Energy-Aware Deep-Learning Accelerator Supporting Dynamic Neural Networks
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks
MorphBungee: A 65nm 7.2mm 2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning
Challenge of low voltage and low power IC toward sustainable future
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers
System performance and energy consumption improvement methodology by delay adjustable synchronizer
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
A low-power digital front-end direct-sampling receiver for flexible radios
An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion
A 0.40pJ/Spike 10μs-Latency Asynchronous Spiking Neural Network with Compact Nonideality-Tolerating CIM-Synapses for Always-On Near-Sensor AI
A 33.6nW Capacitively Coupled Chopper Amplifier with Stacked Input-Boosted Gate-and-Bulk-Driven Inverter Achieving 0.59 NEF and 0.42 PEF in 180nm CMOS
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation
Rigorously modelling steam utility systems for mixed integer optimization
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS
A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient response
A pulse-width-adaptive active charge balancing circuit with pulse-insertion based residual charge compensation and quantization for electrical stimulation applications
An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS Process
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications
Detection of high impedance faults in medium voltage distribution networks
A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering
A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction
A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking
Loop-type feeder models for fast distribution system calculations
A 102dB dynamic range audio sigma-delta modulator in 40nm CMOS
A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs
A 24V-to-1.8V Low Input Current Ripple SC Hybrid Converter with Conducted EMI Noise Suppression Mechanism for Automobile Application
A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS
A digital bang-bang phase-locked loop with bandwidth calibration
A 3.1-μW BJT-Based CMOS Temperature-to-Frequency Converter with Untrimmed Inaccuracy of ±1°C (3σ) from -40°C to 140°C
A Synthesizable 0.0060mm 2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme
Individual pitch control for mitigation of power fluctuation of variable speed wind turbines
Outage planning method for electrical power facilities using MOGA
A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement
A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices
A Power-Efficient Current Readout Circuit with VCO-Based 2 nd -Order CT ΔΣ ADC for Electrochemistry Acquisition
A low-voltage low-offset dual strong-arm latch comparator
A PUF-Integrated Power Amplifier with Harmonic Tunable Matching Network-Controlled Spectral Regrowth Technique for RF Fingerprinting in IoT
A 1.44mm 2 4-channel UWB beamforming receiver with Q-compensation in 65nm CMOS
A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology
A Wirelessly-Powered 10Mbps 46-pJ/b Body Channel Communication System with 45% PCE Multi-Stage and Multi-Source Rectifier for Neural Interface Applications
A 2.68mW/Gbps, 1.62-8.1Gb/s Receiver for Embedded DisplayPort Version1.4b to Support 14dB Channel Loss
Improving stability for independent power control of wind-turbine Doubly Fed Induction Generator with SFOC and DPC during grid unbalance
Power quality monitor placement method using adaptive quantum-inspired binary gravitational search algorithm
Dynamic transverse correction method of middle and long term energy forecasting based on statistic of forecasting errors
Impacts of plug-in electric vehicles on distribution networks
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS
A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator
Policies and initiatives for carbon neutrality in nordic heating and transport systems
PRIM-CAEFA: A 64K-spin Packet-based Reconfigurable Ising Machine with Cross-problem Adjustment-free Energy Feedback Annealing
A DVS-based burst mode with automatic entrance point control technique in DC-DC boost converter for wearable devices and IoT applications
A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors
A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications
Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window
22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible film
IEEE Asian Solid-State Circuits Conference, A-SSCC 2024, Hiroshima, Japan, November 18-21, 2024
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing
Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics
A 29.5W Switched-Capacitor based Dual-Output Hybrid Secondary Charger Providing Simultaneous Two-Cell Battery Charging and System Supply Voltage with Input Current Limiting Feature
A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU
A Sub-0.6V, 330 µW, 0.15 mm 2 Receiver Front-End for Bluetooth Low Energy (BLE) in 22 nm FD-SOI with Zero External Components
What are the driving forces of DRAM?
A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration
A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique
A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers
A fully isolated delta-sigma ADC for shunt based current sensing
Design of purchasing costs analysis system for grid companies
A 0.7mm 2 8.54mW FocusNet Display LSI for Power Reduction on OLED Smart-phones
A Triple-Band Radio for WLAN 11b/g/n/ax in 45nm CMOS
200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices
IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, Busan, Korea, Republic of, November 7-10, 2021
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers
5G Lessons Learned and an Outlook on 6G
An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor
Frequency Response Analysis to recognize inductance variation in transformer due to internal short circuit
A 15-Ch. 0.019 mm 2 /Ch. 0.43% Gain Mismatch Orthogonal Code Chopping Instrumentation Amplifier SoC for Bio-Signal Acquisition
A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery
A 300W 1.27kW/inch 3 98.0% Peak Efficiency 48V-to-12V Switch Tank Converter Controller with Integrated Multilevel Driver and Adaptive ZCS On-time Control
Application of neural network in voltage stability assessment in real-time power market
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA
A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition
A sub-threshold to super-threshold Level Conversion Flip Flop for sub/near-threshold dual-supply operation
An element-matched band-pass delta-sigma ADC for ultrasound imaging
A 24% Efficient, 15.36 dBm Output Power, Multi-Standard Digital Polar Transmitter with 7-bit Phase Interpolator-based BFSK Modulator and 23 dB Sidelobe Suppressed PA for Low-Power Wide Area Networks
A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
High-voltage wordline generator for low-power program operation in NAND flash memories
0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron
A 4-Phase Integrated Voltage Regulator with In-Package Inductors Achieving 89.0% Peak Efficiency and 65% Droop Improvement for 6A/2ns Transient
A 2800-μm2 thermal-diffusivity temperature sensor with VCO-based readout in 160-nm CMOS
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors
A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance check
Input-Adaptive and Regulated Multi-Output Power Management Unit for Wireless Power Reception and Distribution in Multi-Unit Implantable Devices
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput
A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS
TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs
A 6.78-MHz Single-Stage Regulating Rectifier with Hysteretic Control and Current-Wave Modulation
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training
A 32×32 SPAD LiDAR Sensor with In-pixel Spatial-temporal Coincidence and Per-SPAD Pulse Delay for Resolution-lossless Imaging
Influential parameters in lightning current passing a grounding system of high voltage substation
A Hybrid-Resonance Single-Stage Dual-Output Rectifier With High Voltage Difference for Wireless Power Transfer System
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing
A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy
A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI
A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers
A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS
Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect
A 200MHz Bandwidth 84% Peak Efficiency AC-Coupled Envelope Tracking Supply Modulator with 10MHz Constant Switching Frequency
A 174nW Event-Driven Keyword Spotting ASIC with DC-Drift-Resilient Dual-Mode Delta/SAR Quantizer and Multiplier-Less Processor
A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing
A 1.27-mW Battery-Powered Multimodal Biosensor Interface IC for Wireless Motion Intention Recognition in Wearable Robots
A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC
Probabilistic OPF using linear fuzzy relation
An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI
A Hybrid Four-Switch Inductor-First Quadratic Step-Down Converter With Internal Ripple Compensated COT Control
A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth
IC challenges in 5G
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching
93% Efficiency and 0.99 power factor in pseudo-linear LED driver
A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2 nd -Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS
Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors
A Calibration-Free 0.7-V 13-bit 10-MS/s Full-Analog SAR ADC with Continuous-Time Feedforward Cascaded (CTFC) Op-Amps
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits
A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver
A multi-agent approach to smart grid energy management
A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantables
A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor
Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors
A 1.08ms Ultrafast Scanning Capacitive Touch-Screen Sensor Interface with Charge-Interpolated Common-Mode Compensation and Host-Based Adaptive Median Filtering
A 0.5-to-1.2V, 310nA Quiescent Current, 3fs-FoM Time-Domain Output-Capacitorless LDO with Propagation-Delay-Triggered Edge Detector
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS
FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition
A 3-D Ising Machine with 12-Way Supply-and-Bulk Injection Locking Oscillators for Combinatorial Problem Solving
A -51dBc-Reference-Spur and 66fsrms-Jitter D-Band PLL with Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector
A single-switch high gain quadratic boost converter based on voltage-lift-technique
IEEE ASSCC 2023/ Session 10/ Paper 10.5
A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter
Relationship between generator affinity and voltage profile improvement