yusuke1997/dblp-id-title huggingface dataset:
Robust and efficient synchronous buck converter with near-optimal dead-time control
27.7 A 0.05mm 2 1V capacitance-to-digital converter based on period modulation
A 20mW 61dB SNDR (60MHz BW) 1b 3 rd -order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS
16.4 0.6-to-1.0V 279μm 2 , 0.92μW temperature sensor with less than +3.2/-3.4°C error for on-chip dense thermal monitoring
IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning
Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache
Embedded Memory Design for Nano-Scale VLSI Systems (Forum)
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications
11.3 A One-Step 325V to 3.3-to-10V 0.5W Resonant DC-DC Converter with Fully Integrated Power Stage and 80.7% Efficiency
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications
3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF
Session 13 Overview: Cryo-CMOS for Quantum Computing Technology Directions Subcommittee
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed
A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement
26.2 A Doherty-Like Load-Modulated Balanced Power Amplifier Achieving 15.5dBm Average Pout and 20% Average PAE at a Data Rate of 18Gb/s in 28nm CMOS
A Single-Chip Optical Phased Array in a 3D-Integrated Silicon Photonics/65nm CMOS Technology
A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering
11.4 A Gm-C RF Quadrature-Current-Generation Technique with 40dB IRR in 0.65V 2mW Multi-Mode CMOS GNSS Receiver
11.3 A hybrid multipath CMOS magnetic sensor with 210µTrms resolution and 3MHz bandwidth for contactless current sensing
A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects
Session 19 overview: Sensors and interfaces: Analog subcommittee
3.7 A fully integrated TV tuner front-end with 3.1dB NF, >+31dBm OIP3, >83dB HRR3/5 and >68dB HRR7
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique
An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductor
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC
16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD
A full-duplex 10GBase-T transmitter hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
23.8 A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction
Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor
A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias
Session 15 Overview: Compute-in-Memory Processors for Deep Neural Networks Machine Learning Subcommittee
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry
8.4 A 4GHz, 0.69%-Accuracy Voltage-Droop Detector with Multiple Remote Sensing and Under 2-Cycle Detection Latency in 2nm GAAFET
A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots
Sensors and MEMS
21.4 A microfluidic-CMOS platform with 3D capacitive sensor and fully integrated transceiver IC for palmtop dielectric spectroscopy
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise
Memory Solutions for Flexible Thin-Film Logic: up to 8kb, >105.9kb/s LPROM and SRAM with Integrated Timing Generation Meeting the ISO NFC Standard
27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU
A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoM A in 22nm FinFET
An 82.4% efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reduction
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications
18.1 A 1.7-to-2.2GHz full-duplex transceiver system with >50dB self-interference cancellation over 42MHz bandwidth
2.7 A hybrid supply modulator with 10dB ET operation dynamic range achieving a PAE of 42.6% at 27.0dBm PA output power
A 5.2GHz microprocessor chip for the IBM zEnterprise™ system
32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope
Towards personalized medicine and monitoring for healthy living
17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation
25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique
A 0.022mm 2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits
MEMS for automotive and consumer electronics
19.3 Reconfigurable SDR receiver with enhanced front-end frequency selectivity suitable for intra-band and inter-band carrier aggregation
A 10Gb/s burst-mode/continuous-mode laser driver with current-mode extinction-ratio compensation circuit
10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range
Session 25 overview: Non-volatile memory solutions: Memory subcommittee
100Gb/s ethernet chipsets in 65nm CMOS technology
A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V
A 0.64-to-0.69THz Beam-Steerable Coherent Source with 9.1dBm Radiated Power and 30.8dBm Lensless EIRP in 65nm CMOS
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales
A 1V 5mA multimode IEEE 802.15.6/bluetooth low-energy WBAN transceiver for biotelemetry applications
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy
A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth
A digital driving technique for an 8b QVGA AMOLED display using ΔΣ modulation
A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS
The 2nd Wave of the Digital Consumer Revolution: Challenges and Opportunities!
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems
F1: High-speed interleaved ADCs
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment
Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits
A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO
25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz offset frequencies in 0.13μm CMOS using an ISF manipulation technique
19.3 An 8.9-to-21.9GHz Single-Core Oscillator with Reconfigurable Class-F -1 and Enhanced-Colpitts Dual-Mode Operation Achieving 209dBc/Hz FoMT
26.4 A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2 Area
A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz
LAGS System Using Data/Instruction Grain Power Control
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS
280GHz and 860GHz image sensors using Schottky-barrier diodes in 0.13μm digital CMOS
Session 8 overview: Millimeter-wave techniques
2.3 Emerald Rapids: 5th-Generation Intel ® Xeon ® Scalable Processors
14.2 A physically unclonable function with BER -8 for robust chip authentication using oscillator collapse in 40nm CMOS
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate
A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler
A 915MHz 120μW-RX/900μW-TX envelope-detection transceiver with 20dB in-band interference tolerance
6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance
11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS
A 1µW-to-1mW energy-aware interface IC for piezoelectric harvesting with 40nA quiescent current and zero-bias active rectifiers
A fully immersible deep-brain neural probe with modular architecture and a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sites
20.4 A 300GHz wirelessly locked 2×3 array radiating 5.4dBm with 5.1% DC-to-RF efficiency in 65nm CMOS
Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM
5.5 A Stacking Mixer-First Receiver Achieving >20dBm Adjacent-Channel IIP3 Consuming less than 25mW
A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization
Session 22 overview: Systems and instruments for human-machine interfaces
A 12A 89.3% Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Regulators
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS
23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
14.7 In-situ techniques for in-field sensing of NBTI degradation in an SRAM register file
A 13μm CMOS SoC for simultaneous multichannel optogenetics and electrophysiological brain recording
24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches
Flash memory - The great disruptor!
16.6 Flexible thin-film NFC transponder chip exhibiting data rates compatible to ISO NFC standards using self-aligned metal-oxide TFTs
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS
A 0.5V 74dB SNDR 25kHz CT ΔΣ Modulator with Return-to-Open DAC
7.2 A 48 ×4013.5 mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter
An 84% Peak Efficiency Bipolar-Input Boost/Flyback Hybrid Converter With MPPT and on-Chip Cold Starter for Thermoelectric Energy Harvesting
A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM
22.8 An AC-input inductorless LED driver for visible-light-communication applications with 8Mb/s data-rate and 6.4% low-frequency flicker
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS
A 0.16mm 2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS
A Double Step-Down Dual-Output Converter with Cross Regulation of 0.025mV/mA and Improved Current Balance
A 60GHz antenna-referenced frequency-locked loop in 0.13μm CMOS for wireless sensor networks
An IEEE 802.11a/b/g SoC for Embedded WLAN Applications
6.8 A pen-pressure-sensitive capacitive touch system using electrically coupled resonance pen
A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna
Session 12 overview: Non-volatile memory solutions
An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protection
A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS
17.8 A compact 130GHz fully packaged point-to-point wireless system with 3D-printed 26dBi lens antenna achieving 12.5Gb/s at 1.55pJ/b/m
A 1.83µJ/classification nonlinear support-vector-machine-based patient-specific seizure classification SoC
Private Equity: Fight them or Invite them
A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40% System Efficiency for Multi-Mode NB-IoT/BLE Applications
15.1 A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface
A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques
4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems
A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC
A 9.5GHz 6ps-Skew Space-Filling-Curve Clock Distribution with 1.8V Full-Swing Standing-Wave Oscillators
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation
A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration
12.2 A mm-Wave/Sub-THz Synthesizer-Free Coherent Receiver with Phase Reconstruction Through Mixed-Signal Kramer-Kronig Processing
15.2 A flexible ISO14443-A compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrier
A sub-1.5° rms Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC
4.3 A 43mm 2 Fully Integrated Legacy Cellular and 5G FR1 RF Transceiver with 24RX/3TX Supporting Inter-Band 7CA/5CA 4×4 MIMO with 1K-QAM
14.3 A 26GHz Full-Duplex Circulator Receiver with 53UB/400MHz(40UB/800MHz) Self-Interference Cancellation for mm-Wave Repeaters
20.3 An 86-to-94.3GHz transmitter with 15.3dBm output power and 9.6% efficiency in 65nm CMOS
A 60GHz CMOS Power Amplifier with Cascaded Asymmetric Distributed-Active-Transformer Achieving Watt-Level Peak Output Power with 20.8% PAE and Supporting 2Gsym/s 64-QAM Modulation
27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imaging
A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28nm Process
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
An Integrated RFID Reader
A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psat and 23.5% PAEpeak Using Scalable Matched-Zone-Expanding Radial Power Combining with EM-Loss Reduction in 40nm Bulk CMOS
22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systems
A Triple-Band Passive RFID Tag
34.1 A 64×64 Implantable Real-Time Single-Charged-Particle Radiation Detector for Cancer Therapy
A 10Gb/s Digital Isolator Using Coupled Split-Ring Resonators with 24kVpk Surge Capability and 100kV/μS Common-Mode Transient Immunity
4.4 A Highly-Integrated 6-Phase Cell-Reused Digital Transmitter Using 1/3 Duty-Cycle LO Signals for Harmonic Rejection
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration
5.4 A sub-µW 36nV/√Hz chopper amplifier for sensors using a noise-efficient inverter-based 0.2V-supply input stage
A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated Search Lines for Data-Center ASICs
IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024
A 1.2V 2MHz BW 0.084mm 2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM
An x86-64 core implemented in 32nm SOI CMOS
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications
8.10 A 5V-to-150V Input-Parallel Output-Series Hybrid DC-DC Boost Converter Achieving 76.4mW/mg Power Density and 80% Peak Efficiency
22.7 A 14b 4.6GS/s RF DAC in 0.18μm CMOS for cable head-end systems
D1: A 7nm ML Training Processor with Wave Clock Distribution
A 4.5GHz LC-VCO with Self-Regulating Technique
A 2/3 inch CMOS Image Sensor for HDTV Applications with Multiple High-DR Modes and Flexible Scanning
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications
6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation
Session 14 overview: Deep-learning processors
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm 2 Die-to-Die Optical Networks
17.2 A 28GHz magnetic-free non-reciprocal passive CMOS circulator based on spatio-temporal conductance modulation
27.9 A 200kS/s 13.5b integrated-fluxgate differential-magnetic-to-digital converter with an oversampling compensation loop for contactless current sensing
7.10 An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS
11.8 Integrated ultrasonic system for measuring body-fat composition
The Art of Scaling: Distributed and Connected to Sustain the Golden Age of Computation
An Inverter-Based Hybrid ΔΣ Modulator
11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management
A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS
4.3 A programmable sub-nanosecond time-gated 4-tap lock-in pixel CMOS image sensor for real-time fluorescence lifetime imaging microscopy
A 240MHz-BW 112dB-DR TIA
A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain soCs
16.1 An ultra-thin flexible CMOS stress sensor demonstrated on an adaptive robotic gripper
A 0.13µm 64Mb multi-layered conductive metal-oxide memory
Optical I/O technology for tera-scale computing
A Wheatstone Bridge Temperature Sensor with a Resolution FoM of 20fJ.K 2
A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode
Good, bad, ugly - 20 years of broadband evolution: What's next?
16.3 An on-Device Generative AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC with Fan-Out Wafer-Level Package
EP2: Lost art? Analog tricks and techniques from the masters
A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging
2.2 "Zen 4c": The AMD 5nm Area-Optimized ×86-64 Microprocessor Core
A 0.25µm logarithmic CMOS imager for emissivity-compensated thermography
A rolling-shutter distortion-free 3D stacked image sensor with -160dB parasitic light sensitivity in-pixel storage node
28.2 A 14GHz battery-operated point-of-care ESR spectrometer based on a 0.13µm CMOS ASIC
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm 2 Voltage/Time Dual-Data-Converter-Based AFE
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications
A 68.6fs rms -Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
An 8K4K-resolution 60fps 450ke - -saturation-signal organic-photoconductive-film global-shutter CMOS image sensor with in-pixel noise canceller
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications
20.5 A Sub-pA ΔΣ Current Amplifier for Single-Molecule Nanosensors
A 6.25GHz 1V LC-PLL in 0.13µm CMOS
19.2 A 12.4% Efficiency, 11dBm Psat, Odd-Harmonics-Recycling, 62-to-92GHz CMOS Frequency Quadrupler Using an Amplitude-Phase Coordinating Technique
IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022
An Inductively-Coupled 64b Organic RFID Tag Operating at 13.56MHz with a Data Rate of 787b/s
A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus
7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate
Foreword Integrated Intelligence is the Future of Systems
An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration
24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
A Closed-Loop 12bit CMOS-Integrated Stress Sensor System with 4bit Adjustable Sensitivity from 178 to 11 kPa/LSB at up to 22.5kS/s and 5bit Dynamic Range Adjustment
A fully intraocular 0.0169mm 2 /pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS
A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter
19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique
A 0.6-to-10GHz Receiver Front-End in 45nm CMOS
A CMOS UWB Camera with 7×7 Simultaneous Active Pixels
IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021
A 0.016mm 2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time