yusuke1997/dblp-id-title huggingface dataset:
A 32-bit Decimal Floating-Point Logarithmic Converter
Towards Arithmetic-Centered Filter Design
Leading Zero Anticipation and Detection-A Comparison of Methods
N-Bit Unsigned Division via N-Bit Multiply-Add
26th IEEE Symposium on Computer Arithmetic, ARITH 2019, Kyoto, Japan, June 10-12, 2019
It Takes Six Ones To Reach a Flaw
Some Formal Tools for Computer Arithmetic: Flocq and Gappa
A systematic approach to the design of structures for addition and subtraction - Case of radix r = m k
The SNAP Project: Design of Floating Point Arithmetic Unit
Algorithms for Multi-Exponentiation Based on Complex Arithmetic
Computer Arithmetic-A Processor Architect's Perspective
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format
IEEE 754-2008 Decimal Floating-Point for Intel
On-line scheme for computing rotation factors
Resource Optimal Design of Large Multipliers for FPGAs
High Density and Performance Multiplication for FPGA
High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography
Modulo-(2 n - 2 q - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues
Heuristics for the Design of Large Multipliers for FPGAs
A Formally-Proved Algorithm to Compute the Correct Average of Decimal Floating-Point Numbers
On-line Multiplication and Division in Real and Complex Bases
Computer arithmetic and ill-conditioned algebraic problems
Approximate Neumann Series or Exact Matrix Inversion for Massive MIMO?
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16
Truncated Logarithmic Approximation
A software implementation of SLI arithmetic
Fused Multiply-Add Microarchitecture Comprising Separate Early-Normalizing Multiply and Add Pipelines
A modular multiplication algorithm with triangle additions
Karatsuba with Rectangular Multipliers for FPGAs
18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France
New 3D Projection Transformation for Point Clouds
Systolic polynomial evaluation and matrix multiplication with multiple precision
15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA
Comparison between Binary64 and Decimal64 Floating-Point Numbers
Optimal Bounds for Floating-Point Addition in Constant Time
Making Interval Arithmetic Robust to Overflow
Parallel Modular Multiplication on Multi-core Processors
Two optimal square-rooting algorithms ussing iterative multiplication
Partitioned algorithms and VLSI structures for large-scale matrix computations
A Generic Modulo-(2 n ±δ) Addition Algorithm via Two-Valued Digit Encoding
Implementation of the single modulus complex ALU
Analysis of arithmetic algorithms: a statistical study
Augmented Arithmetic Operations Proposed for IEEE-754 2018
A Linear-System Operator Based Scheme for Evaluation of Multinomials
Optimistic Parallelization of Floating-Point Accumulation
The Rise of Multiprecision Arithmetic
Hybrid Binary-Ternary Joint Form and Its Application in Elliptic Curve Cryptography
A rational arithmetic processor
A chip-set for a high-speed low-cost floating-point unit
On modulo (2 n +1) arithmetic logic
High-Radix Iterative Algorithm for Powering Computation
A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS
A more efficient residue arithmetic implementation of the FFT
Comparing several GCD algorithms
External Reviewers ARITH 2021
Generating Very Large RNS Bases
Low-Latency and High-Bandwidth Pipelined Radix-64 Division and Square Root Unit
Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor
Efficient Leak Resistant Modular Exponentiation in RNS
The Use of the Multi-Dimensional Logarithmic Number System in DSP Applications
Faster FFTs in Medium Precision
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
Bfloat16 Processing for Neural Networks
A New Family of High.Performance Parallel Decimal Multipliers
Floating-point recurring rational arithmetic system
Multiplication by a Constant is Sublinear
Error detection and correction for addition and subtraction, through use of higher radix extensions of hamming codes
A Historical Perspective on Computer Arithmetic
A Prescale-Lookup-Postscale Additive Procedure for Obtaining a Single Precision Ulp Accurate Reciprocal
Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor
The analysis and design of a class of quotient digit selectors
Pipelined Packet-Forwarding Floating Point: II. An Adder
Multiprocessors for evaluating compound arithmetic functions
Implementation of level-index arithmetic using partial table look-up
The Positive Effects of Stochastic Rounding in Numerical Algorithms
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding
Multiplier Architecture with a Carry-Based Partial Product Encoding
Randomization of Arithmetic Over Polynomial Modular Number System
PQC-AMX: Accelerating Saber and FrodoKEM on the Apple M1 and M3 SoCs
Vector computations on an orthogonal memory access multiprocessing system
Resource Optimal Truncated Multipliers for FPGAs
Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems
HyPoRes: An Hybrid Representation System for ECC
An order preserving finite binary encoding of the rationals
"A novel implementation method for addition and subtraction in residue number systems"
Accurate Parallel Floating-Point Accumulation
Computer Arithmetic - An Algorithm Engineer's Perspective
The design and use of a floating-point (software) simulator for testing the arithmetic behavior of mathematical software
High-speed multiplication and multiple summand addition
Numerical Reproducibility and Accuracy at ExaScale
Computational design alternatives with microprocessor-based systems
Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
Floating-point arithmetic on a reduced-instruction-set processor
Function Evaluation by Table Look-up and Addition
Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
Fault Detection in RNS Montgomery Modular Multiplication
New approach to integer division in residue number systems
A fast algorithm for the symmetric eigenvalue problem
Consequences of a properly implemented computer arithmetic for periodicities of iterative methods
Very high radix division with selection by rounding and prescaling
A Number System Approach for Adder Topologies
19th IEEE Symposium on Computer Arithmetic, ARITH 2009, Portland, Oregon, USA, 9-10 June 2009
Binary Multiplication Radix-32 and Radix-256
An Alternative Approach to Polynomial Modular Number System Internal Reduction
Bounds on Runs of Zeros and Ones for Algebraic Functions
Exact arithmetic using a variable-length P-ADIC representation
2nd IEEE Symposium on Computer Arithmetic, ARITH 1972, College Park, MD, USA, May 15-16, 1972
Reproducible Tall-Skinny QR
Moduli for Testing Implementations of the RSA Cryptosystem
Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor
Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree
An on-line square rooting algorithm
Alternative Split Functions and Dekker's Product
Subquadratic Space Complexity Multiplier for a Class of Binary Fields Using Toeplitz Matrix Approach
Tunable Floating-Point for Energy Efficient Accelerators
An IWS Montgomery Modular Multiplication Algorithm
Error correction in redundant residue number systems
A Decimal Floating-Point Specification
Formal Verification of Floating-Point Division
A comparison of two approaches to multi-operand binary addition
Low-Cost Duplicate Multiplication
A general division algorithm for residue number systems
A combinatoric division algorithm for fixed integer divisors
Modulo-(2 q - 3) Multiplication with Fully Modular Partial Product Generation and Reduction
A feasibility analysis of fixed-slash rational arithmetic
Reduced Latency IEEE Floating-Point Standard Adder Architectures
Residue arithmetic with rational operands
Hybrid Dot-Product Design for FP-Enabled FPGAs
A Radix-8 CMOS S/390 Multiplier
Exponentiation using Division Chains
Hardware starting approximation for the square root operation
Arithmetic on the ELXSI System 6400
An interleaved rational/radix arithmetic system for high-precision computations
Algorithms and multi-valued circuits for the multioperand addition in the binary stored-carry number system
Efficient polynomial L-approximations
Square Root Unit with Minimum Iterations for Posit Arithmetic
Hardware Implementations of Fixed-Point Atan2
Return of the hardware floating-point elementary function
Integer mapping architectures for the polynomial ring engine
A radix-4 on-line division algorithm
Bounding the Round-Off Error of the Upwind Scheme for Advection
Three dimensional IC's and an application to high speed image processor
A modified bi-imaginary number system
Fast Table-Driven Algorithms for Interval Elementary Functions
Table-lookup algorithms for elementary functions and their error analysis
Optimizing Modular Multiplication for NVIDIA's Maxwell GPUs
Leveraging the bfloat16 Artificial Intelligence Datatype For Higher-Precision Computations
Optimal Streamed Linear Permutations
Using loop transformations for precision tuning in iterative programs
Towards Machine-Efficient Rational L ∞ -Approximations of Mathematical Functions
ACRITH: High-Accuracy Arithmetic an advanced tool for numerical computation
Robust Energy-Efficient Adder Topologies
Floating-point computation of functions with maximum accuracy
Shallow multiplication circuits
Calculating in floating sexagesimal place value notation, 4000 years ago
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages
A new real number representation and its operation
Efficient Multiplication in GF(pk) for Elliptic Curve Cryptography
The development of a floating-point validation package
Computation of Decimal Transcendental Functions Using the CORDIC Algorithm
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge
Two methods for fast integer binary-BCD conversion
Revisiting SRT Quotient Digit Selection
Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues
A fast multi-operand multiplication scheme
Implementing infinite precision arithmetic
13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA
Comparison sets: A useful partitioning of the space of floating point operand pairs
A High-Performance Area-Efficient Multifunction Interpolator
Implementation Specific Verification of Divide and Square Root Instructions
Enhanced Vector Math Support on the Intel®AVX-512 Architecture
Multi-operand Floating-Point Addition
Integer division using reciprocals
24th IEEE Symposium on Computer Arithmetic, ARITH 2017, London, United Kingdom, July 24-26, 2017
DSL-Based Modular IP Core Generators: Example FFT and Related Structures
Simplifying Quotient Determination in High-Radix Modular Multiplication
167 MHz Radix-4 Floating Point Multiplier
Exact accumulation of floating-point numbers
Theorems on Efficient Argument Reductions
Error in ulps of the multiplication or division by a correctly-rounded function or constant in binary floating-point arithmetic
On-the-Fly Algorithms and Sequential Machines
VLSI residue multiplier modulo a Fermat number
On fast binary addition in MDS Technologies
Flocq: A Unified Library for Proving Floating-Point Algorithms in Coq
Exchange Algorithm for Evaluation and Approximation Error-Optimized Polynomials
Augmented Precision Square Roots and 2-D Norms, and Discussion on Correctly Rounding sqrt(x^2+y^2)
High-speed computation of unary functions
Sum Propagate Adders
θ(logN) architectures for RNS arithmetic decoding
Arithmetic with Signed Analog Digits
A Parametric Error Analysis of Goldschmidt?s Division Algorithm
Low Latency Pipelined Circular CORDIC
Redundant logarithmic number systems
Gal's Accurate Tables Method Revisited
The design of a vector-radix 2DFFT chip
The SNAP Project: Towards Sub-Nanosecond Arithmetic
Exact rounding of certain elementary functions
Efficient Implementation of Modular Division by Input Bit Splitting
An Iterative Logarithmic Multiplier with Improved Precision
Arithmetic for a high-speed adaptive learning network element
The K5 transcendental functions
The redundant cell adder
A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes
Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context
Arithmetic of finite fields
A New VLSI Vector Arithmetic Coprocessor for the PC
Accelerating Big Integer Arithmetic Using Intel IFMA Extensions
Parallel Prefix Adder Design
Combined system-level redundancy and modular arithmetic for fault tolerant digital signal processing
Intel Nervana Neural Network Processor-T (NNP-T) Fused Floating Point Many-Term Dot Product
Arithmetic Co-transformations in the Real and Complex Logarithmic Number Systems
Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
On the Systematic Creation of Faithfully Rounded Commutative Truncated Booth Multipliers
A Family of High Radix Signed Digit Adders
Effective Continued Fractions
Table-Based versus Shift-And-Add Constant Multipliers for FPGAs
New Area Record for the AES Combined S-Box/Inverse S-Box
A normalization algorithm for truncated p-adic arithmetic
On a tapered floating point system
Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition
Selected RNS Bases for Modular Multiplication
On-line Arithmetic for Detection in Digital Communication Receivers
The status of investigations into the use of continued fractions for computer hardware
Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor
Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing
Automated Design of Floating-Point Logarithm Functions on Integer Processors
Efficient Divide-and-Conquer Multiprecision Integer Division
Fraction-Free RNS Algorithms for Solving Linear Systems
Implementing Multiply-Accumulate Operation in Multiplication Time
On the structure of parallelism in a highly concurrent PDE solver
High-radix modular multiplication for cryptosystems
Multi-operand associative arithmetic
Efficient serial-parallel arrays for multiplication and addition
How to Compute the Area of a Triangle: A Formal Revisit
Correctly Rounded Arbitrary-Precision Floating-Point Summation
New Algorithms for Improved Transcendental Functions on IA-64
Design of a digit-slice on-line arithmetic unit
Efficient elementary function generation with multipliers
Fixed-slash and floating-slash rational arithmetic
An integrated rational arithmetic unit
Rationally biased arithmetic
A Faster Hardware Implementation of the AES S-box
Algorithm design for a 30-bit integrated logarithmic processor
Towards the Post-Ultimate libm
Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders
Semantics for exact floating point operations
Faster numerical algorithms via exception handling
An algorithm for modular exponentiation
Prescaled Integer Division
Automatic Design Space Exploration for an Error Tolerant Application
A General Approach for Improving RNS Montgomery Exponentiation Using Pre-processing
An accurate LNS arithmetic unit using interleaved memory function interpolator
JANUS, an on-line multiplier/divider for manipulating large numbers
A GaAs 32-bit Adder
Radix-64 Floating-Point Divider
The design of a 64-bit integer multiplier/divider unit
Symposium Committee
Using the New VPMADD Instructions for the New Post Quantum Key Encapsulation Mechanism SIKE
A redundant binary Euclidean GCD algorithm
Fast iterative multiplying array
22nd IEEE Symposium on Computer Arithmetic, ARITH 2015, Lyon, France, June 22-24, 2015
Parallel processing in Boolean algebra
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations
RNS Arithmetic Approach in Lattice-Based Cryptography: Accelerating the "Rounding-off" Core Procedure
Optimum array-like structures for high-speed arithmetic
Design of an arithmetic element for serial processing in an iterative structure
Fast matrix solver in GF(2)
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs
Fast Basecases for Arbitrary-Size Multiplication
16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain
Power-Delay Characteristics of CMOS Multipliers
An Efficient Barrett Reduction Algorithm for Gaussian Integer Moduli
Saturating Counters: Application and Design Alternatives
Low-Power Properties of the Logarithmic Number System
Arithmetic Operations in the Polynomial Modular Number System
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root
Verificarlo: Checking Floating Point Accuracy through Monte Carlo Arithmetic
Unrestricted Faithful Rounding is Good Enough for Some LNS Applications
Algorithms for Quad-Double Precision Floating Point Arithmetic
Overflow/underflow-free floating-point number representations with self-delimiting variable-length exponent field
BKM: A new hardware algorithm for complex elementary functions
Reliable Evaluation of the Worst-Case Peak Gain Matrix in Multiple Precision
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Modular Multiplication and Division Algorithms Based on Continued Fraction Expansion
SRT Division Architectures and Implementations
A New Variant of the Barrett Algorithm Applied to Quotient Selection
A minicomputer micxoprogrammable, arithmetic processor
Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters
The end of numerical error
A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm
Worst Cases for Correct Rounding of the Elementary Functions in Double Precision
An Emacs-Cairo Scrolling Bug due to Floating-Point Inaccuracy
A family of CMOS floating point arithmetic chips
Parallel Prefix Adder Design with Matrix Representation
Testing the Sharpness of Known Error Bounds on the Fast Fourier Transform
Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters
Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators
Multiple-Precision Fixed-Point Vector Multiply-Accumulator Using Shared Segmentation
Optimized Binary64 and Binary128 Arithmetic with GNU MPFR
Complex interval division with maximum accuracy
A systolic algorithm for integer GCD computation
The logic of modulo 2 k + 1 adders
Composite Iterative Algorithm and Architecture for q-th Root Calculation
A VLSI Algorithm for Modular Multiplication/Division
Performance Evaluation of an Efficient Double-Double BLAS1 Function With Error-Free Transformation and its Application to Explicit Extrapolation Methods
A software comparison of RNS and PMNS
Towards a Quaternion Complex Logarithmic Number System
The Arithmetic Operators You Will Never See in a Microprocessor
Experimental Software and Hardware Evaluation of Ad-Hoc Constant Division Routines
5th IEEE Symposium on Computer Arithmetic, ARITH 1981, Ann Arbor, MI, USA, May 16-19, 1981
High Intelligence Computing: The New Era of High Performance Computing
Squarers for binary numbers in serial form
High-Performance Left-to-Right Array Multiplier Design
Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees
Digit Elision for Arbitrary-accuracy Iterative Computation
Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization
O(n)-depth circuit algorithm for modular exponentiation
Design of high speed MOS multiplier and divider using redundant binary representation
Vectorized Nonlinear Functions with the RISC-V Vector Extension
Radix-16 Combined Division and Square Root Unit
Prime Factor DFT parallel processor using wafer scale integration
Accelerating Large-Scale HPC Applications Using FPGAs
Higher radix floating point representations
Quotient Approximation Modular Reduction
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes
High-level algorithms for correctly-rounded reciprocal square roots
Considerations in the design of a high speed decimal unit
Understandable arithmetic
Faster Modular Exponentiation Using Double Precision Floating Point Arithmetic on the GPU
Some Functions Computable with a Fused-Mac
Some experiments using interval arithmetic
Quasi-Pipelined Hash Circuits
An Efficient Softcore Multiplier Architecture for Xilinx FPGAs
Simple radix 2 division and square root with skipping of some addition steps
An Open-Source RISC-V Vector Math Library
ADA floating-point arithmetic as a basis for portable numerical software
Algorithm for high speed shared radix 8 division and radix 8 square root
New Results on the Distance between a Segment and Z 2 . Application to the Exact Rounding
Some results about on-line computation of functions
New Technologies for Improved Computing
New Bit-Level Serial GF (2 m ) Multiplication Using Polynomial Basis
Sign detection in Non-Redundant Residue Number System with reduced information
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
Fast and Accurate Bessel Function Computation
Matrix multiplication on LUCAS
ROM-rounding: A new rounding scheme
The impact of parallelism on software
Number-Theoretic Test Generation for Directed Rounding
Compound algorithms for digit online arithmetic
10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991
Table Lookup Structures for Multiplicative Inverses Modulo 2 k
Generation and Analysis of Hard to Round Cases for Binary Floating Point Division
A bit-serial arithmetic unit for rational arithmetic
7th IEEE Symposium on Computer Arithmetic, ARITH 1985, Urbana, IL, USA, June 4-6, 1985
Forword
Mathematical approach to iterative computation networks
Asymmetric Squaring Formulae
High-Precision Anchored Accumulators for Reproducible Floating-Point Summation
Representable Correcting Terms for Possibly Underflowing Floating Point Operations
An Automatable Formal Semantics for IEEE-754 Floating-Point Arithmetic
Acceleration of LU decomposition supporting double-double, triple-double, and quadruple-double precision floating-point arithmetic with AVX2
Mirror arithmetic
Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm
Modular Multiplication using Redundant Digit Division
Fast multiply and divide for a VLSI floating-point unit
Scaling an RNS Number Using the Core Function
Radix-4 square root without initial PLA
Tagged error: tracing numerical error through computations
Case study of the pipelined arithmetic unit for the TI Advanced Scientific Computer
Reducing the number of counters needed for integer multiplication
Dual-Purpose Hardware Algorithms and Architectures - Part 1: Floating-Point Division
Formal Verification of a Chained Multiply-Add Design: Combining Theorem Proving and Equivalence Checking
Ansätze im Research-Controlling
Theologie und High-tech - zwei Seiten einer Medaille? - Philipp Matthäus Hahn Genialer Erfinder, Wegbereiter der Informatik, Mitarbeiter am Reich Gottes
eEurope 2005 - Interoperabilität als Chance für den Mittelstand
Impulse aus der Wirtschaftsinformatik: 5. Liechtensteinisches Wirtschaftsinformatik-Symposium an der Fachhochschule Liechtenstein, Vaduz, Liechtenstein, 2004
Auswirkungen der Unternehmenskonzentration auf das Informatikmanagement
Wie digital ist ihr Geschäft?
Der Einfluss der Information auf Unternehmerund Kundenverhalten in Übergangsländern
Erzielen von nachhaltigen Verkaufserfolgen durch den Einsatz eines CAS-Werkzeuges
Konzeption einer Prozesskostenrechnung für die Raiffeisenbank Feldkirch
Entwicklung von Objektmodellen - Gestaltung und Bereitstellung von Unternehmensmodellen
Sichere Unternehmensnetze Übersicht zum Thema Sicherheit für den Manager
Leistungspotentiale in der Logistik durch Akkommodieren der Informationstechniken