yusuke1997/dblp-id-title huggingface dataset:
Chameleon ART: a non-optimization based analog design migration framework
A neuromorphic design using chaotic mott memristor with relaxation oscillation
Late Breaking Results From Hybrid Design Automation for Field-coupled Nanotechnologies
Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits
RTL - The firmware Design Automation system
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage
Lower Bounds on Test Resources for Scheduled Data Flow Graphs
Determining appropriate precisions for signals in fixed-point IIR filters
The design of an efficient data base to support an interactive LSI layout system
A Unified Design Representation Can Work
What will make your next design experience a much better one?
Test Function Specification in Synthesis
Logic Optimization Algorithm by Linear Programming Approach
PLINT layout system for VLSI chips
Vector potential equivalent circuit based on PEEC inversion
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks
A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling
What does Vibration do to Your SSD?
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation
Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective
CAD challenges in BioMEMS design
Improved Tool and Data Selection in Task Management
Design automation in preliminary design
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems
Computer-aided architectural design
On the costs and benefits of stochasticity in stream processing
WELD - An Environment for Web-based Electronic Design
Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization
Similarity-based wakeup management for mobile systems in connected standby
Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection
Scalable vectorless power grid current integrity verification
Race analysis of digital systems without logic simulation
Parallel Logic Simulation on General Purpose Machines
Virtual to the (near) end: using virtual platforms for continuous integration
MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources
SS-LRU: a smart segmented LRU caching
AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators
PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Learning From A Big Brother - Mimicking Neural Networks in Profiled Side-channel Analysis
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
Exploiting K-Distance Signature for Boolean Matching and G-Symmetry Detection
Software support for the Yorktown Simulation Engine
An efficient finite-domain constraint solver for circuits
Symmetry detection for incompletely specified functions
Tetris: A Streaming Accelerator for Physics-Limited 3D Plane-Wave Ultrasound Imaging
Invited: Achieving PetaOps/W Edge-AI Processing
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs
Regaining throughput using completion detection for error-resilient, near-threshold logic
21st century digital design tools
On Removing Redundancy in Sequential Circuits
T2FSNN: Deep Spiking Neural Networks with Time-to-first-spike Coding
The MCC CAD Framework Methodology Management System
An Efficient Parallel Critical Path Algorithm
A low-power dynamic divider for approximate applications
Cloud platforms and embedded computing: the operating systems of the future
An O (N log N) algorithm for Boolean mask operations
Random Generation of Test Instances for Logic Optimizers
A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph Extraction
SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels
Two-dimensional channel routing and channel intersection problems
Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability Optimization
Routing architecture exploration for regular fabrics
RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Design verification based on functional abstraction
Wear rate leveling: lifetime enhancement of PRAM with endurance variation
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS
A hybrid verification approach: getting deep into the design
Layout Decomposition for Quadruple Patterning Lithography and Beyond
A design flow for application specific heterogeneous pipelined multiprocessor systems
Ripple 2.0: high quality routability-driven placement via global router integration
Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications
A Methodology for Guided Behavioral-Level Optimization
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption
Development and application of a designer oriented cyclic simulator
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Achieving SLC performance with MLC flash memory
DCO-3D: Differentiable Congestion Optimization in 3D ICs
How will the fabless model survive?
A Channelless, Multilayer Router
Auto-interactive schematics to layout translation
Virtual flash chips: rethinking the layer design of flash devices to improve data recoverability
Compact Vector Generation for Accurate Power Simulation
Cost-aware three-dimensional (3D) many-core multiprocessor design
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits
Hierarchical circuit verification
TMEAS, a testability measurement program
A user looks at da - yesterday, today, tomorrow
Virtual Simulation of Distributed IP-based Designs
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization
MINUPROX - an advanced proximity correction technique for the IBM EL-2 electron beam tool
QCADS-a LSI CAD system for minicomputer
Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language
Process variation characterization of chip-level multiprocessors
VVIP: Versatile Vertical Indexing Processor for Edge Computing
Online cache state dumping for processor debug
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Multi-Core Design Automation Challenges
EImprove - Optimizing Energy and Comfort in Buildings based on Formal Semantics and Reinforcement Learning
SAT based exact synthesis using DAG topology families
Resource-aware partitioned scheduling for heterogeneous multicore real-time systems
Placement and Routing for a Field Programmable Multi-Chip Module
APT: An Area-Performance-Testability Driven Placement Algorithm
New Algorithms for Gate Sizing: A Comparative Study
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
Programming Living Cells to Function as Massively Parallel Computers
Enabling On-Device Self-Supervised Contrastive Learning with Selective Data Contrast
MOSFET modeling and circuit design: re-establishing a lost connection (tutorial)
A low-cost conflict-free NoC for GPGPUs
EdGeo: A Physics-guided Generative AI Toolkit for Geophysical Monitoring on Edge Devices
A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts
Rethinking Programming Frameworks for In-Storage Processing
An Efficient Compute-in-Memory based Accelerator for Point-based Point Cloud Neural Networks
Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding
Efficient Tunstall Decoder for Deep Neural Network Compression
A facility for rapid computer-aided generation of precision graphics
MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation
Approximation and Decomposition of Binary Decision Diagrams
Performance trade-off analysis of analog circuits by normal-boundary intersection
PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency
A Quick Safari Through the Reconfiguration Jungle
SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPU
Circuit-based Boolean Reasoning
Supporting Register-based Addressing Modes for in-DRAM PIM ISAs
Performance-Driven Steiner Tree Algorithm for Global Routing
Pulsed-latch aware placement for timing-integrity optimization
Datapath Generator Based on Gate-Level Symbolic Layout
Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation
Exploiting parallelism in a switch-level simulation machine
Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT)
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
Computing Radial Basis Function Support Vector Machine using DNA via Fractional Coding
ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis
Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices
Ultra low power associative computing with spin neurons and resistive crossbar memory
Manipulation and characterization of molecular scale components
Benchmarks for Layout Synthesis - Evolution and Current Status
Space-Efficient Multiversion Index Scheme for PCM-based Embedded Database Systems
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
Hierarchical channel router
System-on-Chip Power Management Considering Leakage Power Variations
Breaking the Barrier of Parallel Simulation of Digital Systems
Software Accelerated Functional Fault Simulation for Data-Path Architectures
Combining proximity criteria with nature-of-the-spot criteria in architectural and urban design space planning problems using a computer-aided space allocation technique: A proposed technique and an example of its application
A unified approach to simulation and timing verification at the functional level
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design
Fully X-tolerant, very high scan compression
Optimizing the Performance of NDP Operations by Retrieving File Semantics in Storage
Convergence-Aware Neural Network Training
SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures
Timing closure through a globally synchronous, timing partitioned design methodology
Phled45: An enhanced version of caesar supporting 45° geometries
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips
On proving the correctness of optimizing transformations in a digital design automation system
Performance Optimization Using Exact Sensitization
Parallel Pattern Fault Simulation of Path Delay Faults
Methodology for compiler generated silicon structures
Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks
Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning
A Graphical Hardware Design Language
PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration
Electronic circuit analysis with on-line graphs via a time-sharing terminal
Using a formal specification and a model checker to monitor and direct simulation
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor
Towards a C++-based design methodology facilitating sequential equivalence checking
An efficient algorithm for multi-layer obstacle-avoiding rectilinear Steiner tree construction
Verification of VHDL Designs Using VAL
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration
SymPhase: Phase Symbolization for Fast Simulation of Stabilizer Circuits
Design optimizations for microprocessors at low temperature
Revisiting the ARM Debug Facility for OS Kernel Security
Lightning Talk: Trinity - Assured Neuro-symbolic Model Inspired by Hierarchical Predictive Coding
Protecting the supply chain for automotives and IoTs
Computing Parametric Yield Adaptively Using Local Linear Models
Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation
The open shop interactive mask design operation at harris semiconductor
Communication architecture based power management for battery efficient system design
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side *
In-Stream Stochastic Division and Square Root via Correlation
Interconnect reliability modeling and analysis for multi-branch interconnect trees
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping
Compiling for energy efficiency on timing speculative processors
Evaluating design trade-offs in customizable processors
An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA
Improved Channel Routing by Via Minimization and Shifting
Precise error determination of approximated components in sequential circuits with model checking
Big.LITTLE system architecture from ARM: saving power through heterogeneous multiprocessing and task context migration
Synthesizing hardware from sketches
Secure scan: a design-for-test architecture for crypto chips
Micro-operation Perturbations in Chip Level Fault Modeling
A Hierarchy Preserving Hierarchical Compactor
On the Computation of the Set of Reachable States of Hybrid Models
Analysis of actual fault mechanisms in CMOS logic gates
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing
EagleRec: Edge-Scale Recommendation System Acceleration with Inter-Stage Parallelism Optimization on GPUs
Automatic Synthesis of Interfaces Between Incompatible Protocols
Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability
Memory Estimation for High Level Synthesis
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution
zkVC: Fast Zero-Knowledge Proof for Private and Verifiable Computing
Bus encoding for low-power high-performance memory systems
Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems
A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip
Education for the Deep Submicron Age: Business as Usual?
Proving correctness of regular expression accelerators
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles
FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDs
Designing a New Automotive DNA
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems
EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
The First EDA MOOC: Teaching Design Automation to Planet Earth
A New Compaction Scheme Based on Compression Ridges
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing
High-Level Synthesis of Fault-Secure Microarchitectures
A layout system for high precision design of progressive die
PseudoSC: A Binary Approximation to Stochastic Computing within Latent Operation-Space for Ultra-Lightweight on-Edge DNNs
Understanding the trade-offs in multi-level cell ReRAM memory design
F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM
Transistor sizing of custom high-performance digital circuits with parametric yield considerations
High-Performance Clock Routing Based on Recursive Geometric Aatching
Low-power bus encoding using an adaptive hybrid algorithm
4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors
A consideration of the number of horizontal grids used in the routing of a masterslice layout
Computer-assisted template layout
PattPIM: A Practical ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions
Flexible Transistor Matrix (FTM)
Invited - Cooperation or competition?: coexistence of safety and security in next-generation ethernet-based automotive networks
Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation
Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits
A General Multi-Layer Area Router
Relevant Issues in High-Level Connectivity Synthesis
HSIS: A BDD-Based Environment for Formal Verification
Computer aided (CA) tools integration and related standards development in a multi-vendor universe (panel session)
An efficient routing database
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Minimising buffer requirements of synchronous dataflow graphs with model checking
Topological Routing in SURF: Generating a Rubber-Band sketch
A New Interactive Supply/Demand Router with Rip-Up Capability for Printed Circuit Boards
BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture
Codar: A Contextual Duration-Aware Qubit Mapping for Various NISQ Devices
Moving a D.A. system from development to production (Position Paper)
Write-back aware shared last-level cache management for hybrid main memory
An automatic system approach to the problem of memory circuit testing & fault diagnosis
A Simplified Six-waveform Type Method for Delay Fault Testing
CAD at the Design-Manufacturing Interface
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Realizable parasitic reduction using generalized Y-Delta transformation
Gate for gate modular replacement of combinational switching networks
Truly Pre-Routing Timing Prediction via Considering Power Delivery Network
MILO: A Microarchitecture and Logic Optimizer
A gate level model for CMOS combinational logic circuits with application to fault detection
CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification
BDDMAP: A Technology Mapper Based on a New Covering Algorithm
Quick detection of difficult bugs for effective post-silicon validation
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System
A Cross-Debugging Method for Hardware/Software Co-design Environments
Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions
Uncertainty and optimization in the design of building subsystems
Error Correction Based on Verification Techniques
Intellectual Property Protection in the EDA Industry
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems
A parameterized mask model for lithography simulation
Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture
Accelerating soft-error-rate (SER) estimation in the presence of single event transients
Incorporating the human factor in color CAD systems
System-Level Power/Performance Analysis for Embedded Systems Design
A Decision Procedure for Bit-Vector Arithmetic
Understanding soft errors in uncore components
Clock Period Minimization with Minimum Delay Insertion
Relax-and-retime: a methodology for energy-efficient recovery based design
Model-based development and verification of control software for electric vehicles
Verification of Transactional Memory in POWER8
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
Leakage in nano-scale technologies: mechanisms, impact and design considerations
A Universal Client for Distributed Networked Design and Computing
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor
Real-time co-scheduling of multiple dataflow graphs on multi-processor systems
Analog System Verification in the Presence of Parasitics Using Behavioral Simulation
Multilevel global placement with retiming
A computer graphic human figure system applicable to kineseology
SuperNet: multimode interconnect architecture for manycore chips
Context-sensitive timing analysis of Esterel programs
A Three-Layer Gridless Channel Router with Compaction
PLA driver selection: an analytic approach
SystemC transaction level models and RTL verification
Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture
Synthesis of high-performance packet processing pipelines
FPGA code accelerators - the compiler perspective
Elmore model for energy estimation in RC trees
Computer aided design of high density printed circuit boards
The minimum width routing of A 2-row 2-layer polycell-layout
GLARE: global and local wiring aware routability evaluation
N-variant IC design: methodology and applications
A totally integrated systems approach to design and manufacturing at McDonnell Douglas Corporation
A model for non interpreted structures of logical systems
Generalized reliability-oriented energy management for real-time embedded applications
Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs
Application of logic synthesis to the understanding and cure of genetic diseases
Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations
Single-molecule electronic detection using nanoscale field-effect devices
An Automated BIST Approach for General Sequential Logic Synthesis
A Tool for Performance Estimation of Networked Embedded End-systems
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine
A probabilistic and energy-efficient scheduling approach for online application in real-time systems
An FPGA-Compatible TRNG with Ultra-High Throughput and Energy Efficiency
An Enhanced Data Model for CAD/CAM Database Systems
Automated energy/performance macromodeling of embedded software
Realizable RLCK circuit crunching
Philo-a VLSI design system
Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards
A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing
A Tree-Based Scheduling Algorithm for Control-Dominated Circuits
Tools for map graphics
SPET: Transparent SRAM Allocation and Model Partitioning for Real-time DNN Tasks on Edge TPU
Static timing analysis for flexible TFT circuits
Circular Self-Test Path: A Low-Cost BIST Technique
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Synthesis-for-testability of controller-datapath pairs that use gated clocks
AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices
Biomedical electronics serving as physical environmental and emotional watchdogs
An Intelligent Compiler Subsystem for a Silicon Compiler
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
A framework for verification of SystemC TLM programs with model slicing: a case study
Speed up of Behavioral A.T.P.G. using a Heuristic Criterion
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores
Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques
FHDnn: communication efficient and robust federated learning for AIoT networks
GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
A New Hybrid Methodology for Power Estimation
Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC