yusuke1997/dblp-id-title huggingface dataset:
Asynchronous and clocked control structures for VLSI based interconnection networks
SEAL: A Single-Event Architecture for In-Sensor Visual Localization
Performance Evaluation of On-Chip Register and Cache Organizations
Data Flow on a Queue Machine
Classification and Performance Evaluation of Instruction Buffering Techniques
REIS: A High-Performance and Energy-Efficient Retrieval System with In-Storage Processing
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
WeeFence: toward making fences free in TSO
SpZip: Architectural Support for Effective Data Compression In Irregular Applications
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs
RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM
Performance Evaluation of Multiple Register Sets
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
Maximizing Performance in a Striped Disk Array
Performance Measurements on HEP - A Pipelined MIMD Computer
A Concept for Test and Reconfiguration of a Fault-Tolerant VLSI Processor System
Architectural Support for Translation Table Management in Large Address Space Machines
PES: proactive event scheduling for responsive and energy-efficient mobile web computing
Timetraveler: exploiting acyclic races for optimizing memory race recording
Proceedings of the 5th Annual Symposium on Computer Architecture, Palo Alto, CA, USA, April 1978
TrioSim: A Lightweight Simulator for Large-Scale DNN Workloads on Multi-GPU Systems
Performance Impact of Task Mapping on the Cell BE Multicore Processor
Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers
Design of a 2 × 2 fault-tolerant switching element
PIPE: A VLSI Decoupled Architecture
Thermal time shifting: leveraging phase change materials to reduce cooling costs in warehouse-scale computers
Rebooting Virtual Memory with Midgard
PLUS: A Distributed Shared-Memory System
Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?
A Multi-Processor Reduction Machine for User-Defined Reduction Languages
The GF11 Supercomputer
Polymorphic On-Chip Networks
Host-Based Dos Attacks and Defense in the Cloud
A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things
The Design of a User-Programmable Digital Interface
27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada
MGS: A Multigrain Shared Memory System
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs
MU6V: A Parallel Vector Processing System
SIMD 2 : a generalized matrix instruction set for accelerating tensor computation beyond GEMM
DReX: Accurate and Scalable Dense Retrieval Acceleration via Algorithmic-Hardware Codesign
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference
Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues
On Endurance of Processing in (Nonvolatile) Memory
A Study of Branch Prediction Strategies
Analysis of the O-GEometric History Length Branch Predictor
Speculation Techniques for Improving Load Related Instruction Scheduling
The Program Decision Logic Approach to Predicated Execution
Early Experience with Message-Passing on the SHRIMP Multicomputer
Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, May 1993
Dynamic Verification of Sequential Consistency
Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999
Mapping Data Flow Programs on a VLSI Array of Processors
The SiLago Method: Next Generation VLSI Architectures and Design Methods
Hybe: GPU-NPU Hybrid System for Efficient LLM Inference with Million-Token Context Window
Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models
Retrospective: Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer
Functional Memory Techniques Applied To The Microprogrammed Control Of An Associative Processor
Divide and Conquer Frontend Bottleneck
Architectural core salvaging in a multi-core processor for hard-error tolerance
Instruction Issue Logic for Pipelined Supercomputers
An abacus turn model for time/space-efficient reconfigurable routing
A Unification Processor Based on a Uniformly Structured Cellular Hardware
Nonblocking Memory Refresh
Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product
RISC I: A Reduced Instruction Set VLSI Computer
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
Dictionary Machines With a Small Number of Processors
Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors
Deterministic and Stochastic Modeling of Parallel Garbage Collection - Towards Real-Time Criteria
The Cytocomputer: A Practical Pipelined Image Processor
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Ten ways to waste a parallel computer
WarmCache: Exploiting STT-RAM Cache for Low-Power Intermittent Systems
A Design-Oriented Computer Engineering Program
An Ultra Low Power System Architecture for Sensor Network Applications
Memory Access Buffering in Multiprocessors
Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM
RAP: Reconfigurable Automata Processor
Issues Related to MIMD Shared-memory Computers: The NYU Ultracomputer Approach
The locality-aware adaptive cache coherence protocol
Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor
Don't Forget the I/O When Allocating Your LLC
Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations
Using Cache Memory to Reduce Processor-Memory Traffic
Design Data for Algol-60 Machines
Rethinking Prefetching for Intermittent Computing
Performance analysis of multi-threaded multi-core CPUs
Power model validation through thermal measurements
COMA: An Opportunity for Building Fault-Tolerant Scalable Shared Memory Multiprocessors
Spatial Memory Streaming
Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications
Retrospective: A Retrospective on the Warp Machines
Proceedings of the 7th Annual Symposium on Computer Architecture, La Baule, France, May 6-8, 1980
Temperature-Aware Microarchitecture
SATORI: Efficient and Fair Resource Partitioning by Sacrificing Short-Term Benefits for Long-Term Gains *
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992
Hardware Translation Coherence for Virtualized Systems
A Retrospective on the Dorado, A High-Performance Personal Computer
A Loop Network for Simultaneous Transmission of Variable-Length Messages
Virtual private caches
Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm
Computer Architecture for Correct Programming
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory
OPAC: A floating-point coprocessor dedicated to compute-bound kernels
CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
Dual-side Sparse Tensor Core
H 2 -LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications
AVM-BTB: Adaptive and Virtualized Multi-level Branch Target Buffer
Performance pathologies in hardware transactional memory
Enabling Compute-Communication Overlap in Distributed Deep Learning Training Platforms
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems
An Efficient Time-Shared Link Processor for Supporting Communication in Parallel Systems with Dynamic Structure
FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining
On the Verification of Computer Architectures Using an Architecture Description Language
Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors
Dynamic Load Balancer in Intel Xeon Scalable Processor: Performance Analyses, Enhancements, and Guidelines
Design and Simulation of the Distributed Loop Computer Network (DLCN)
2QAN: a quantum compiler for 2-local qubit hamiltonian simulation algorithms
An Architecture for a VHSIC Computer
Adaptive Storage Management for Very Large Virtual/Real Storage Systems
Unifying on-chip and inter-node switching within the Anton 2 network
Direct Cache Access for High Bandwidth Network I/O
VM/4: ACOS-4 Virtual Machine Architecture
APRIL: A Processor Architecture for Multiprocessing
Deadlock-Free Multicast Wormhole Routing in Multicomputer Networks
Description and Simulation of Microcode Execution
The Epsilon Dataflow Processor
DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations
Axiomatic hardware-software contracts for security
The Design of an Object Oriented Architecture
Evaluating the Imagine Stream Architecture
Implementation and Evaluation of a List-Processing-Oriented Data Flow Machine
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983
Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking
Exploiting Parallelism in a Switch-Level Simulation Machine
Improving Program Efficiency by Packing Instructions into Registers
HIOS: A host interface I/O scheduler for Solid State Disks
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows
A Pyramidal Approach to Parallel Processing
TDGraph: a topology-driven accelerator for high-performance streaming graph processing
Cache write generate for high performance parallel processing
Spandex: A Flexible Interface for Efficient Heterogeneous Coherence
Generic System Calls for GPUs
A Scalable Front-End Architecture for Fast Instruction Delivery
Virtualizing Transactional Memory
Performance Modeling and Code Partitioning for the DS Architecture
Linebacker: preserving victim cache lines in idle register files of GPUs
Pensieve: Microarchitectural Modeling for Security Evaluation
Securing GPU via region-based bounds checking
Bit-level perceptron prediction for indirect branches
Improved Route Selection Approaches using Q-learning framework for 2D NoCs
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
The impact of management operations on the virtualized datacenter
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
Branch vanguard: decomposing branch functionality into prediction and resolution instructions
Online Pipeline Systems for Recursive Numeric Computations
Neoscope: How Resilient Is My SoC to Workload Churn?
Performance Enhancement of SISD Processors
The Effect of Instruction Fetch Bandwidth on Value Prediction
VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping
Architectural Support for Performance Tuning: A Case Study on the SPARCcenter2000
Evaluating Ruche Networks: Physically Scalable, Cost-Effective, Bandwidth-Flexible NoCs
S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP
Multiple Threads in Cyclic Register Windows
Retrospective: Memory Access Buffering in Multiprocessors
Distributed Arithmetic on a Quantum Multicomputer
Maps: A Compiler-Managed Memory System for Raw Machines
Row-buffer decoupling: A case for low-latency DRAM microarchitecture
HeteroOS: OS Design for Heterogeneous Memory Management in Datacenter
An Instruction Timing Model of CPU Performance
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores
Shared caches in multicores: the good, the bad, and the ugly
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System
Meta TM //TxLinux: transactional memory for an operating system
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Sentry: A novel hardware implementation of classic operating system mechanisms
Studying multicore processor scaling via reuse distance analysis
ReCycle: : pipeline adaptation to tolerate process variation
Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading
Deriving Design Guidelines for Diagnosable Computer Systems
MAD-Max Beyond Single-Node: Enabling Large Machine Learning Model Acceleration on Distributed Systems
R2D2: Removing ReDunDancy Utilizing Linearity of Address Generation in GPUs
The Architecture of a Linda Coprocessor
Perforated Page: Supporting Fragmented Memory Allocation for Large Pages
A Generalized Object Display Processor Architecture
Moving the needle, computer architecture research in academe and industry
Configurable Flow Control Mechanisms for Fault-Tolerant Routing
TWiCe: preventing row-hammering by exploiting time window counters
M3L: A List-Directed Architecture
Security testing of a secure cache design
Evaluating the Performance of Four Snooping Cache Coherency Protocols
Token Coherence: Decoupling Performance and Correctness
Area-Performance Trade-offs in Tiled Dataflow Architectures
Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks
Determining the Minimum Number of Virtual Networks for Different Coherence Protocols
Agile Paging: Exceeding the Best of Nested and Shadow Paging
A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms
Shakti-T: A RISC-V Processor with Light Weight Security Extensions
A 64-bit stream processor architecture for scientific applications
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
Architecture of SOAR: Smalltalk on a RISC
Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
Multi-level Shared Caching Techniques for Scalability in VMP-M/C
Using Network Interface Support to Avoid Asynchronous Protocol Processing in Shared Virtual Memory Systems
Heterogeneous Acceleration Pipeline for Recommendation System Training
Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
Allowing for ILP in an embedded Java processor
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
A Language Implementation Design for a Multiprocessor Computer System
ELSA: Hardware-Software Co-design for Efficient, Lightweight Self-Attention Mechanism in Neural Networks
Chimera: Communication Fusion for Hybrid Parallelism in Large Language Models
A Look-Ahead Data Staging Architecture for Relational Data Base Machines
Support vector regression: exploiting machine learning techniques for leakage modeling
Real-world design and evaluation of compiler-managed GPU redundant multithreading
Lukewarm serverless functions: characterization and optimization
Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor
Prefetching Using Markov Predictors
Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality
A low power and reliable charge pump design for Phase Change Memories
Microarchitectural mechanisms to exploit value structure in SIMT architectures
REYSM, A High Performance, Low Power Multi-Microprocessor Bus
An Architecture for Software-Controlled Data Prefetching
Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables
Hybrid cache architecture with disparate memory technologies
The Performance Potential of Multiple Functional Unit Processors
Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups
Throughout Analysis and Configuration Design of a Shared-Resource Multiprocessor System: PUMPS
New attacks and defense for encrypted-address cache
A case for globally shared-medium on-chip interconnect
NeuRex: A Case for Neural Rendering Acceleration
Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications
MicroScope: enabling microarchitectural replay attacks
MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors
Priority-Driven, Preemptive I/O Controllers for Real-Time Systems
Probabilistic analysis of a crossbar switch
ArtMem: Adaptive Migration in Reinforcement Learning-Enabled Tiered Memory
RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging
A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories
The SPLASH-2 Programs: Characterization and Methodological Considerations
Relaxed Persist Ordering Using Strand Persistency
PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers
Design Considerations for the VLSI Processor of X-tree
OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
Exploiting Spatial Locality in Data Caches Using Spatial Footprints
InvisiMem: Smart Memory Defenses for Memory Bus Side Channel
VIP: virtualizing IP chains on handheld platforms
UGEMM: Unary Computing Architecture for GEMM Applications
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network
Area Efficient Architectures for Information Integrity in Cache Memories
Retrospective: Characterization of Processor Performance in the VAX-11/780
Performance of Memory Configurations for Parallel-Pipelined Computers
The IEEE Computer Society Task Force on Computer Architecture
Distribution of Functions and Control in RPCNET
Software-Extended Coherent Shared Memory: Performance and Cost
Reducing TLB and Memory Overhead Using Online Superpage Promotion
Intermodule Protocol For Register Transfer Level Modules: Representation and Analytic Tools
BOSS: Bandwidth-Optimized Search Accelerator for Storage-Class Memory
Commit-Reconcile & Fences (CRF): A New Memory Model for Architects and Compiler Writers
Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions
Going the Distance for TLB Prefetching: An Application-Driven Study
A scalable architecture for reprioritizing ordered parallelism
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors
Astrea: Accurate Quantum Error-Decoding via Practical Minimum-Weight Perfect-Matching
Intra-disk Parallelism: An Idea Whose Time Has Come
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging
Retrospective: Monsoon: An Explicit Token-Store Architecture
UPP: Universal Predicate Pushdown to Smart Storage
Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures
BitNN: A Bit-Serial Accelerator for K-Nearest Neighbor Search in Point Clouds
CoWLight: Hardware Assisted Copy-on-Write Fault Handling for Secure Deduplication
A Language for the Simulation of Systolic Architectures
Relax: an architectural framework for software recovery of hardware faults
A Performance Comparison of Optimally Designed Computer Systems with and without Virtual Memory
BASTION-SGX: bluetooth and architectural support for trusted I/O on SGX
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads
AsmDB: understanding and mitigating front-end stalls in warehouse-scale computers
Analysis of multithreaded microprocessors under multiprogramming
TaskFusion: An Efficient Transfer Learning Architecture with Dual Delta Sparsity for Multi-Task Natural Language Processing
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks
CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures
NUPEA: Optimizing Critical Loads on Spatial Dataflow Architectures via Non-Uniform Processing-Element Access
VLSI architectures for high speed recognition of context-free languages and finite-state languages
Full-stack, real-system quantum computer studies: architectural comparisons and design insights
µ3L: An HLL-RISC processor for parallel execution of FP-language programs
Implementing a Cache for a High-Performance GaAs Microprocessor
An Abstract Parallel Graph Reduction Machine
Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration
Scrambled Storage for Parallel Memory Systems
Combining Tags With Error Codes
Performance Studies of a Prolog Machine Architecture
Side channel analysis on an embedded hardware fingerprint biometric comparator & low cost countermeasures
Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures
Moguls: a model to explore the memory hierarchy for bandwidth improvements
Line Digraph Iterations and the (d,k) Problem for Directed Graphs
Reducing the Cost of Branches
Dynamic Rerouting Tag Schemes for the Augmented Data Manipulator Network
Unlimited Vector Extension with Data Streaming Support
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling
A First-Order Superscalar Processor Model
Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality
Gist: Efficient Data Encoding for Deep Neural Network Training
Coherent Network Interfaces for Fine-Grain Communication
Branch with Masked Squashing in Superpipelined Processors
Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads
Architecture of the PSC: A Programmable Systolic Chip
Post-silicon CPU adaptation made practical using machine learning
Retrospective: Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors
SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping
A Systolic Multiplier Unit and Its VLSI Design
EVA 2 : Exploiting Temporal Redundancy in Live Computer Vision
GangES: Gang error simulation for hardware resiliency evaluation
Q-BEEP: Quantum Bayesian Error Mitigation Employing Poisson Modeling over the Hamming Spectrum
The virtual write queue: coordinating DRAM and last-level cache policies
Automated design of application specific superscalar processors: an analytical approach
Stream chaining: exploiting multiple levels of correlation in data prefetching
Bouncer: static program analysis in hardware
Tartan: Microarchitecting a Robotic Processor
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Anubis: ultra-low overhead and recovery time for secure non-volatile memories
PowerChief: Intelligent Power Allocation for Multi-Stage Applications to Improve Responsiveness on Power Constrained CMP
Architectural Features of CASSM: A Context Addressed Segment Sequential Memory
Performance of Shared Cache for Parallel-Pipelined Computer Systems
Tolerating Late Memory Traps in ILP Processors
Hardware Support for Inter-Process Communication and Processor Sharing
SecChisel Framework for Security Verification of Secure Processor Architectures
Adaptive CHERI Compartmentalization for Heterogeneous Accelerators
Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations
Reconfigurable Stream Network Architecture
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results
A comparison study of intel SGX and AMD memory encryption technology
Scheduling Page Table Walks for Irregular GPU Applications
47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020