yusuke1997/dblp-id-title huggingface dataset:
AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices
AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference
Synthesis using sequential functional modules (SFMs)
Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test
UI-timer: an ultra-fast clock network pessimism removal algorithm
Front-end-of-line attacks in split manufacturing
Noise analysis of non-autonomous radio frequency circuits
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Selective shielding: a crosstalk-free bus encoding technique
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms
BEATNP: a tool for partitioning Boolean networks
An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations
A methodology for timing model characterization for statistical static timing analysis
An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis
Variation aware optimal threshold voltage computation for on-chip noise sensors
Hardware Accelerator Design for Data Centers
Managing mobile platform power
Analysis of cyclic combinational circuits
Technology migration techniques for simplified layouts with restrictive design rules
A more reliable reduction algorithm for behavioral model extraction
Partial Core Encryption for Performance-Efficient Test of SOCs
An observability-based code coverage metric for functional simulation
Toward efficient spatial variation decomposition via sparse regression
Loop pipelining for high-throughput stream computation using self-timed rings
LLM-Barber: Block-Aware Rebuilder for Sparsity Mask in One-Shot for Large Language Models
Mode connectivity in the QCBM loss landscape: ICCAD Special Session Paper
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design
Fast and efficient phase conflict detection and correction in standard-cell layouts
Open-Source Incubation Ecosystem for Digital Microfluidics - Status and Roadmap: Invited Paper
Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants
Convexity-based algorithms for design centering
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Power Side Channel Attack Analysis and Detection
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002
Techniques for improving the efficiency of sequential circuit test generation
Design-Manufacturing Interface for 0.13 Micron and Below
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
A new method to express functional permissibilities for LUT based FPGAs and its applications
Automatic formal verification of multithreaded pipelined microprocessors
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
Whirlpool PLAs: a regular logic structure and their synthesis
Formal verification meets simulation (tutorial abstract)
Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance
A modified approach to two-level logic minimization
LSMR: Synergy Randomness in Liquid State Machine and RRAM-based Analog-digital Accelerator
Process-variation-tolerant clock skew minimization
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops
Concurrent logic restructuring and placement for timing closure
Temperature measurement of simulated annealing placements
Smartphone Analysis and Optimization based on User Activity Recognition
Toward scalable source level accuracy analysis for floating-point to fixed-point conversion
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs
Invited Paper: Rowhammer Mitigation by Approximate Computing: A Compressed Sensing Case Study
Static timing analysis considering power supply variations
Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters
Access Pattern Reshaping for eMMC-enabled SSDs
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996
Invited Paper: Optimizing Privacy-Preserving Primitives to Support LLM-Scale Applications
Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration
nn-dependability-kit: Engineering Neural Networks for Safety-Critical Autonomous Driving Systems
Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Cost-effective write disturbance mitigation techniques for advancing PCM density
Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems
Robustify ML-Based Lithography Hotspot Detectors
Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly
Electromigration Checking Using a Stochastic Effective Current Model
LUT-HD: Accelerating Hyperdimensional Computing Inference via Efficient Table Lookup
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems
Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis
From micro to nano: MEMS as an interface to the nano world
On primitive fault test generation in non-scan sequential circuits
A signature based approach to regularity extraction
An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids
Portable parallel test generation for sequential circuits
AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Global routing on rhomboidal tiles
SuperPUF: integrating heterogeneous physically unclonable functions
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Negative thinking by incremental problem solving: application to unate covering
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise
Synthesis methodology for built-in at-speed testing
AGAR: a single-layer router for gate array cell generation
Functional comparison of logic designs for VLSI circuits
Design and technology co-optimization near single-digit nodes
Performance-Driven Pre-Assignment Routing for High-Speed Package Designs
Combinatorial algorithms for fast clock mesh optimization
Multi-Level Optimization for Large Scale ASICS
Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis
Technology Mapping of Genetic Circuits: From Optimal to Fast Solutions
Generic ILP versus specialized 0-1 ILP: an update
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring
Incremental multiple-scan chain ordering for ECO flip-flop insertion
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization
Layout-Driven Area-Constrained Timing Optimization by Net Buffering
Analysis of emerging core-based design lifecycle
Layout-driven resource sharing in high-level synthesis
Finite State Machine Decomposition by Transition Pairing
MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs
Post-verification debugging of hierarchical designs
Cloning techniques for hierarchical compaction
Experiments in logic optimization
An Accelerated Steady-State Method for Networks with Internally Controlled Switches
OpenTimer: A High-Performance Timing Analysis Tool
High level design for wearables and IoT
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
A spacing algorithm for performance enhancement and cross-talk reduction
Energy-efficient platform designs for real-world wireless sensing applications
Leaks beyond Bits: Deep Learning-Assisted Side-Channel Attacks on Hyperdimensional Computing Accelerators
Energy budgeting for battery-powered sensors with a known task schedule
Fault Tolerant In-Memory Computing based on Emerging Technologies for Ultra-Low Precision Edge AI Accelerators
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters
F2VD: Fluid Rates to Virtual Deadlines for Precise Mixed-Criticality Scheduling on a Varying-Speed Processor
Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT
Full-chip verification of UDSM designs
Power supply noise aware workload assignment for multi-core systems
Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays
Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
MEIC: Re-thinking RTL Debug Automation using LLMs
Automatic differentiation in circuit simulation and device modeling
Verification of systems containing counters
Reversible logic circuit synthesis
Algorithms for Three-Layer Over-The-Cell Channel Routing
Serial-link bus: a low-power on-chip bus architecture
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management
ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining
SCADET: a side-channel attack detection tool for tracking prime+probe
Engineering details of a stable force-directed placer
OCTS: An Optical Clock Tree Synthesis Methodology for 2.5D Systems
Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems
A Parallel Algorithm for Hierarchical Circuit Extraction
DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training System
Multibank memory optimization for parallel data access in multiple data arrays
Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks
BETA: Behavioral Testability Analysis
Dynamic Response Time Optimization for SDF Graphs
IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023
SNNGX: Securing Spiking Neural Networks with Genetic XOR Encryption on RRAM-based Neuromorphic Accelerator
Verifying dynamic properties of nonlinear mixed-signal circuits via efficient SMT-based techniques
Guiding CNF-SAT search via efficient constraint partitioning
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
High performance test generation for accurate defect models in CMOS gate array technology
A dynamic method for efficient random mismatch characterization of standard cells
A New Model for Over-The-Cell Channel Routing with Three Layers
Multipoint moment matching model for multiport distributed interconnect networks
Energy-efficient architecture for advanced video memory
Impulse response fault model and fault extraction for functional level analog circuit diagnosis
A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding
Early matching of system requirements and package capabilities
Multi-phase Coupled CMOS Ring Oscillator based Potts Machine
Modeling uncertainty in RC timing analysis
HyperSF: Spectral Hypergraph Coarsening via Flow-based Local Clustering
FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays
DAG-aware circuit compression for formal verification
A Force-Directed Maze Router
Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips
On soft error rate analysis of scaled CMOS designs - A statistical perspective
ReSCALE: recalibrating sensor circuits for aging and lifetime estimation under BTI
HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design
BMCFuzz: Hybrid Verification of Processors by Synergistic Integration of Bound Model Checking and Fuzzing
Convertibility verification and converter synthesis: two faces of the same coin
A thermal and process variation aware MTJ switching model and its applications in soft error analysis
Perturb and simplify: multi-level boolean network optimizer
A novel damped-wave framework for macro placement
Equalized interconnects for on-chip networks: modeling and optimization framework
Switching activity analysis considering spatiotemporal correlations
A Timing-Driven Global Router for Custom Chip Design
Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly
A Fast Learning-Driven Signoff Power Optimization Framework
Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives
From statistical model checking to statistical model inference: characterizing the effect of process variations in analog circuits
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
FACAM: Design and Optimization of A Compact Energy Efficient FeFET-Based Analog Content Addressable Memory
Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators
Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards
RNA-ViT: Reduced-Dimension Approximate Normalized Attention Vision Transformers for Latency Efficient Private Inference
Channel-adaptive zero-margin & process-adaptive self-healing communication circuits/systems
Circuit noise evaluation by Padé approximation based model-reduction techniques
Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk)
Performance Optimization of Pipelined Circuits
FastSies: a fast stochastic integral equation solver for modeling the rough surface effect
Fast approximation for peak power driven voltage partitioning in almost linear time
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems
Valid clocking in wavepipelined circuits
Energy efficient runtime approximate computing on data flow graphs
Moment-Based Power Estimation in Very Deep Submicron Technologies
MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper
Design analysis of IC power delivery
Analyzing software influences on substrate noise: an ADC perspective
Fault-based automatic test generator for linear analog circuits
Fast and lossless graph division method for layout decomposition using SPQR-tree
Untangling twisted nets for bus routing
Analytical approach to custom datapath design
Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet Inference
SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement
Functional post-silicon diagnosis and debug for networks-on-chip
Single-Pass Redundancy Addition and Removal
WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography
Quantifying robustness metrics in parameterized static timing analysis
Dynamic partitioning to mitigate stuck-at faults in emerging memories
On the computation of criticality in statistical timing analysis
Zero skew clock routing in multiple-clock synchronous systems
A Trade-off Oriented Placement Tool
Property-specific sequential invariant extraction for SAT-based unbounded model checking
HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural Network
Rebooting Computing and Low-Power Image Recognition Challenge
BeKnight: Guarding Against Information Leakage in Speculatively Updated Branch Predictors
Variable domain transformation for linear PAC analysis of mixed-signal systems
A voltage-frequency island aware energy optimization framework for networks-on-chip
Area minimization for hierarchical floorplans
Exact critical path tracing fault simulation on massively parallel processor AAP2
EarDVFS: Environment-Adaptable RL-based DVFS for Mobile Devices
Predictable Routing
Automatic Kernel Generation for Large Language Models on Deep Learning Accelerators
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net
Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules
Silicon fault diagnosis using sequence interpolation with backbones
Synthesis for Testability Techniques for Asynchronous Circuits
Floorplanning for Embedded Multi-Die Interconnect Bridge Packages
Refining switching window by time slots for crosstalk noise calculation
Simulation-based signal selection for state restoration in silicon debug
Timing-Driven Partial Scan
Fast Full-Chip Parametric Thermal Analysis Based on Enhanced Physics Enforced Neural Networks
Simultaneous power and thermal integrity driven via stapling in 3D ICs
DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning
On the Diagnostic Resolution of Signature Analysis
A robust general constrained random pattern generator for constraints with variable ordering
Test and diagnosis of fault logic blocks in FPGAs
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms
Fast discrete function evaluation using decision diagrams
Switchbox Steiner Tree Problem in Presence of Obstacles
Qubit Mapping for Reconfigurable Atom Arrays
Dynamic redundancy identification in automatic test generation
Throughput-driven IC communication fabric synthesis
LACO: A Latency-Constraint Offline Neural Network Scheduler towards Reliable Self-Driving Perception
FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash
Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits
Simulation and Optimization of the Power Distribution Network in VLSI Circuits
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators
Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper
Predictability: definition, ananlysis and optimization
New Algorithms for the Placement and Routing of Macro Cells
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk
ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network
Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverage
Invited Paper: Learned In-Sensor Visual Computing: From Compression to Eventification
Routability-driven placement and white space allocation
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
Organic electronic device modeling at the nanoscale
Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems
Maximum-information storage system: Concept, implementation and application
TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing
Timing Constraints for Correct Performance
RouteNet: routability prediction for mixed-size designs using convolutional neural network
Timing driven placement
Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits
Exploring high throughput computing paradigm for global routing
Critical path tracing in sequential circuits
HERMES: Homomorphic Encryption over Residual Number System for Multi-level EvaluationS
Constrained aggressor set selection for maximum coupling noise
FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA
Security challenges in smart surveillance systems and the solutions based on emerging nano-devices
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults
Identification of critical paths in circuits with level-sensitive latches
DoS-FPGA: Denial of Service on Cloud FPGAs via Coordinated Power Hammering
Automated generation of efficient instruction decoders for instruction set simulators
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening
Design for manufacturability in submicron domain
Design based analog testing by Characteristic Observation Inference
Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study
An efficient algorithm for time separation of events in concurrent systems
1-Bit Compressed Sensing Based Framework for Built-in Resonance Frequency Prediction Using On-Chip Noise Sensors
Word-level decision diagrams, WLCDs and division
Robust GNN-Based Representation Learning for HLS
Invited Paper: Circuit and Architecture Design with Emerging Computing Paradigms
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
A comparative study of design for testability methods using high-level and gate-level descriptions
Fast wire length estimation by net bundling for block placement
Autonomous sensor-context learning in dynamic human-centered internet-of-things environments
RLC interconnect delay estimation via moments of amplitude and phase response
Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFM
DiCER: distributed and cost-effective redundancy for variation tolerance
Neuromorphic Computing for Graph Analytics
Opening: Introduction to CAD contest at ICCAD 2012: CAD contest
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs
Design/process learning from electrical test
SADE: A Graphical Tool for VHDL-Based System Analysis
Computer-aided design for DNA self-assembly: process and applications
Optimal wiresizing under the distributed Elmore delay model
Test Generation for Acyclic Sequential Circuits with Hold Registers
An Access Pattern-aware Hybrid Learning-based and Conventional Mapping for Solid-State Drives
Stars in VCC: Complementing Simulation with Worst-Case Analysis
Deep learning challenges and solutions with Xilinx FPGAs
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000
Variation-Aware Adaptive Tuning for Nanophotonic Interconnects
DAMOCLES: an observer-based approach to design tracking
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions
A power modeling and characterization method for macrocells using structure information
Dual-Output LUT Merging during FPGA Technology Mapping
Fault behavior dictionary for simulation of device-level transients
Invited Paper: Security Under the Lens: Vulnerabilities in In-Sensor Computing Systems
Allocation of multiport memories for hierarchical data stream
Detecting stability faults in sub-threshold SRAMs
Exploiting soft redundancy for error-resilient on-chip memory design
A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems
ISBA: An independent set-based algorithm for automated partial reconfiguration module generation