yusuke1997/dblp-id-title huggingface dataset:
Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks
Nanosatellite On-Board Computer including a Many-Core Processor
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices
Synthesis of a 8051-Like Microcontroller Tolerant to Transient Faults
On the use of a failure emulator mechanism at nanosatellite subsystems integration tests
A Wireless Embedded System for Measuring the Effects of Ionizing Radiations
Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques
Modular and adaptative test-bed for infrared photodetectors
Optimizing an LDO voltage regulator by evolutionary algorithms considering tolerances of the circuit elements
ICs and MEMS for energy management
Efficient fault injection in QEMU
Embedded Tutorial: Integrated System Hardening Seen from a Security Point of View: Dream or Nightmare?
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment
Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect
Testability Calculation for Digital Circuits with Decision Diagrams
Reliability Evaluation of Voters for Fault Tolerant Approximate Systems
Low-power design under variation using error prevention and error tolerance (invited paper)
Analyzing the Architectural Impact of Transient Fault Effects in SFUs of GPUs
An evaluation of free/open source static analysis tools applied to embedded software
Reliability analysis of majority voters under permanent faults
Optimizing operational amplifiers by metaheuristics and considering tolerance analysis
Vericonn: a tool to generate efficient interconnection networks for post-silicon debug
Parametric Failures and Detection Strategies
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock
Development of Self-Testing Software Components
Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive Standards
A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs
Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs
Proposal of a functional safety methodology applied to fault tolerance in FPGA applications
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors
Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters
Use of ensemble methods for indirect test of RF circuits: can it bring benefits?
Design for Testability Techniques: A Comparative Analysis
Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests
On the evaluation of SEU effects in GPGPUs
Fault tolerance evaluation of RFID tags
Softerror mitigation for multi-core processors based on thread replication
Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level
On the Temperature Dependencies of Analog BIST
Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical path
Transforming nanodevices into nanosystems: The N3XT 1, 000X
Fail-Safe and Test for Electronic Control Systems Using PLCs
IJTAG compatible analogue embedded instruments for MPSoC life-time prediction
Complex delay fault reasoning with sequential 7-valued algebra
Case Study: Horizontal Side-Channel Analysis Attack Against Elliptic Curve Scalar Multiplication Accelerator Under Laser Illumination
Reliability of on-board computer for ITASAT university satellite
An approach for clustering test data
Automated testing of embedded automotive systems from requirement specification models
Testing multiple stuck-at faults of ROBDD based combinational circuit design
Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability Estimation
Efficient metric for register file criticality in processor-based systems
Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring
IEEE Latin-American Test Symposium, LATS 2020, Maceio, Brazil, March 30 - April 2, 2020
Analysis of the implications of stacked devices in nano-scale technologies for analog applications
Estimating Static Parameters of A-to-D Converters from Spectral Analysis
Scan based two-pattern tests: should they target opens instead of TDFs?
Abstractions for Modeling the Effects of Wall Surface Roughness in Silicon Photonic Microring Resonators
Estimating the quality of Oscillation-Based Test for detecting parametric faults
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs
Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications
17th Latin-American Test Symposium, LATS 2016, Foz do Iguacu, Brazil, April 6-8, 2016
Special Session: A Model-Driven Design Tool for Modelling, Simulation and Assertion-Based Verification of Hybrid Automata
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model
Codesign System Modeling for Performance Analysis
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
Checksum based error detection in linearized representations of non linear control systems
Recent progress of software-related electromagnetic compatibility
A comprehensive approach to fault tolerance: Device, circuit, and system techniques
Complex Adaptive Signal Processing for Analog Testing
Resistance of the Montgomery kP Algorithm against Simple SCA: Theory and Practice
Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain
Defect Oriented Testing of an ECL/CMOS Level Converter Circuit
19th IEEE Latin-American Test Symposium, LATS 2018, Sao Paulo, Brazil, March 12-14, 2018
Estimation of dynamic current waveforms using pre-characterization of standard cells
A probabilistic model for stuck-on faults in combinational logic gates
CMOS amplifier with self-correction offset for SerDes applications
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies
Ionizing radiation modeling in DRAM transistors
Qubit-driven Fault Simulation
SITARe: A simulation tool for analysis and diagnosis of radiation effects
Identifying high variability speed-limiting paths under aging
Using Memory to Cope with Simultaneous Transient Faults
Mixed-level identification of fault redundancy in microprocessors
NBTI-aware technique for transistor sizing of high-performance CMOS gates
3D Thermal-aware floorplanner for many-core single-chip systems
Model-based design for wireless body sensor network nodes
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study
Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results
Evaluating coverage collection using the VEasy functional verification tool suite
Measurement and control for risk-based test cases and activities
A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU
An Experimental Comparison of Fault Injection Tools for Microprocessor-based Systems
Minimization of incompletely specified finite state machines based on distinction graphs
A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA
Practical experience designing and debugging an FPGA for a real-time ethernet industrial bus
Dependable on-chip infrastructure for dependable MPSOCs
Performance testing of distributed block-oriented storage over IP networks
12th Latin American Test Workshop, LATW 2011, Beach of Porto de Galinhas, Brazil, March 27-30, 2011
On the consolidation of mixed criticalities applications on multicore architectures
Vmin Testing under Variations: Defect vs. Fault Coverage
Probability aware fault-injection approach for SER estimation
Laser Fault Injection Attacks against Radiation Tolerant TMR Registers
Adaptive position digital control with deadbeat response for a platform on a mobile vehicle
A control path aware metric for grading functional test vectors
State Model Approach for Analog Fault Modeling
SEU fault injection in simulation environments: example of VHDL configuration on FPGA device
Fault masking ratio analysis of majority voters topologies
Diversity TMR: Proof of concept in a mixed-signal case
Error detection method for the ARINC429 communication
Zero-Day Hardware-Supported Malware Detection of Stack Buffer Overflow Attacks: An Application Exploiting the CV32e40p RISC-V Core
Fault-Tolerant Predictive Feedback Control
A digital technique for the evaluation of SSB phase noise of analog/RF signals
A Software Technique for Fault-Tolerant Adaptive Circuits in Spatial Applications
Exploring trade-offs in multi-site wafer testing
Performance evaluation model for test process
TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications
Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs
Testing Embedded Core-Based System Chips
Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any Order
Security and Quantum Computing: An Overview
Analysis of routing algorithms generation for irregular NoC topologies
In-field test of safety-critical systems: is functional test a feasible solution?
Configurable tool to protect processors against SEE by software-based detection techniques
A New Method to Extract the Silicon Film Thickness of Enhancement Mode Fully Depleted SOIN MOSFETs
Parametric DC and noise measurements in a unified test & characterization software tool framework
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems
Self Test Built-in Plan for Data-Path Functional Units
Grouped Feature Selection for SMONs Placement in MCU Performance Screening
System-level diagnosis for WSN: A heuristic
IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, March 11-13, 2019
Rare event diagnosis by iterative failure region locating and elite learning sample selection
Mutation based testing of Web Services
Single Trojan injection model generation and detection
Wafer-Level Die Re-Test Success Prediction Using Machine Learning
15th Latin American Test Workshop - LATW 2014, Fortaleza, Brazil, March 12-15, 2014
Configurable platform for IC combined tests of total-ionizing dose radiation and electromagnetic immunity
A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects
Fault tolerant linear state machines
A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture
Robustness with respect to SEUs of a self-converging algorithm
IoT and Edge Computing: Applications and Reliability Implications
Silicon Lifecycle Management Based on On-Chip Cross-Layer Sensing and Analytics for Space Applications
Evaluating Fault Coverage of Structural and Specification-based Tests Obtained With a Low-Cost Analog TPG Tool
Approximate Computing for Safety-Critical Applications
BugTracer: A system for integrated circuit development tracking and statistics retrieval
Design and test of the RT-NKE task scheduling algorithm for multicore architectures
A Comparison Between Testability Measures Applied to Complex Gates
The Use of Analytical and Simulation Solutions with Statecharts for performance evaluation: A case study of a File Server model
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs
Generating non-uniform distributions for fault injection to emulate real network behavior in test campaigns
2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001
Secured Bus as a Countermeasure against Covert Channels: NEORV32 Case Study
RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC
CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units
Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs
A Fast Reliability Analysis of Image Segmentation Neural Networks Exploiting Statistical Fault Injections
A HW-dependent software model for cross-layer fault analysis in embedded systems
Embedded test and control of analogue/RF circuits using intelligent resources
Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems
Reliability enhancement via Sleep Transistors
3DB Challange for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICs
Dynamic power modulation in baseband OFDM signal processor using application driven metrics: Image transmission and processing
A test time theorem and its applications
PASSAT 2.0: A multi-functional SAT-based testing framework
Test and calibration of MEMS convective accelerometers with a fully electrical setup
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications
The Challenges of Coupling Digital-Twins with Multiple Classes of Faults
Turning JTAG inside out for fast extended test access
High-Level Decision Diagrams based coverage metrics for verification and test
SystemC-AMS high-level modeling of linear analog blocks with power consumption information
A Flexible Approach for Defining Distributed Dependable Tests in SNMP-based Network Management Systems
Gate-level modelling of NBTI-induced delays under process variations
Embedded Tutorial: Access to On-chip Instruments via Functional Ports
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies
Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-core
Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells
A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells
Mutation analysis with high-level decision diagrams
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability
Fault-tolerance in FPGA focusing power reduction or performance enhancement
FPGA-based Stuck-at Fault Emulation in Wavelet-based Image Coding Systems
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies
A Non-Linearity Compensation Technique for Charge-Redistribution SAR ADCs
Multi-condition alternate test of analog, mixed-signal, and RF systems
Digital generation of single tone FM/PM test stimuli: a theoretical analysis
Test Configuration Generation for FPGA Logic Cells
Design dependent SRAM PUF robustness analysis
Soft error reliability predictor based on a Deep Feedforward Neural Network
Methodology for achieving best trade-off of area and fault masking coverage in ATMR
Hybrid De-Embedding for 116 Gbps Test Channels
Heavy Ion-Induced Faults on Programmable UART Controllers Embedded into SRAM-Based FPGA
At Speed Testing Challenges and Solutions for 56Gbps and 112Gbps PAM4 SerDes
Bit-flip injection strategies for FSMs modeled in VHDL behavioral level
Data-Oblivious and Performant: On Designing Security-Conscious Hardware
Spin transfer torque memories for on-chip caches: Prospects and perspectives
Feature Selection for Cost Reduction In MCU Performance Screening
Contrast of a HDL model and COTS version of a microprocessor for soft-error testing
Recovery scheme for hardening system on programmable chips
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays
Influence of sampling frequency on TID response of SAR ADCs
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables
SEU fault-injection in VHDL-based processors: A case study
Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study
Design Optimization Based on Diagnosis Techniques
DeepER-HD: An Error Resilient HyperDimensional Computing Framework with DNN Front-End for Feature Selection
RF and Microwave production test requirements for advanced mixed-signal devices
Processor checkpoint recovery for transient faults in critical applications
Filter Sensitivity Analysis Using the TRAM
Formal Approach to the RTL Testability Analysis
Increasing Reliability in Future Technologies Systems
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection
Evaluating the efficiency of data-flow software-based techniques to detect SEEs in microprocessors
Message from the LATS2015 Chairs
Sequential ATPG Using Combinational Algorithms
A Verification Platform for Human Pose Estimation Models
Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench
Variation-aware and self-healing design methodology for a system-on-chip
A Fault Injection Framework for AI Hardware Accelerators
10th Latin American Test Workshop, LATW 2009, Rio de Janeiro, Brazil, March 2-5, 2009
Testing approximate digital circuits: Challenges and opportunities
Effect of aging on power integrity of digital integrated circuits
Timing issues for an efficient use of concurrent error detection codes
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments
Auxiliary IP blocks for early dependability analysis of small processor based systems
Exploring BDDs to reduce test pattern set
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs
Virtual reconfigurable scan-chains on FPGAs for optimized board test
On-Line BIST for Testing Analog Circuits
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test
A guiding heuristic for the semi-formal verification of high-level designs
PrOCov: Probabilistic output coverage model
Predicting die-level process variations from wafer test data for analog devices: A feasibility study
A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites
Assertion-aware approximate computing design exploration on behavioral models
Internal State Monitoring in RISC-V Microarchitectures for Security Purpose
Accessing on-chip instruments through the life-time of systems
Mutation Operators for Concurrent Programs in Elixir
On the functional test of MESI controllers
Communication fault injection for multi-protocol Java applications testing
Platform for automated HW/SW co-verification, testing and simulation of microprocessors
Single element correction in sorting algorithms with minimum delay overhead
Generic and Detailed Search for TAM Definition in Core-Based Systems
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates
A SystemC-based platform for assertion-based verification and mutation analysis in systems biology
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip
Diagnostic modeling of digital systems with low- and high-level decision diagrams
Mixed signal verification to avoid integration mismatch in complex SoCs
Mutation analysis for SystemC designs at TLM
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network
An Optimal Test Assignment for Monitoring General Topology Networks
Analyzing NBTI impact on SRAMs with resistive-open defects
A metric-guided gate-sizing methodology for aging guardband reduction
7th Latin American Test Workshop, LATW 2006, Buenos Aires, Argentina, March 26-29, 2006
Post-silicon observability enhancement with topology based trace signal selection
"Safe" built-in test and tuning of boost converters using feedback loop perturbations
Soft Error Reliability of SRAM cells during the three operation states
Fault-tolerant architecture with full recovery under presence of SEU
A New FPGA for DSP Applications Integrating BIST Capabilities
Improving error detection with selective redundancy in software-based techniques
Cost/Quality Trade-Off in Synthesis for BIST
Mixed-signal RF Design-for-Test: Is It R (Real) or F (Fake)?
NBTI-aware data allocation strategies for scratchpad memory based embedded systems
Test Automation Viability Analysis Method
On automatic software-based self-test program generation based on high-level decision diagrams
Fast and scalable temperature-driven floorplan design in 3D MPSoCs
Circuit Level Design Methods to Mitigate Soft Errors
Evaluating the Impact of Process Variation on RRAMs
Reliable Diagnosis of Grid-Connected Systems
Ionizing radiation effects on a COTS low-cost RISC microcontroller
Pruning single event upset faults with petri nets
Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiers
Robust DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) Voltage
Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits
Infrastructure for formal and dynamic verification of peripheral programming model
Analysis of Voltage Drop and Temperature Effects on Harmonic Errors Under EMFI on ROs
On High-Quality, Low Energy BIST Preparation at RT-Level
Improved Fault Diagnosis of Analog Circuits using Light Emission Measures
Exploring and Interpreting System Event Logs
Investigations of the diagnosibility of digital networks with BIST
Designing Testable Networks for Transfer Function Realization
Low cost fault detector guided by permanent faults at the end of FPGAs life cycle
Test power reduction via deterministic alignment of stimulus and response bits
Analyzing structure-based techniques for test coverage on a J2ME software product line
Pattern-based injections in processors implemented on SRAM-based FPGAs
NBTI-aware design of integrated circuits: a hardware-based approach
Evaluation of fault attack detection on SRAM-based FPGAs
Functional test generation for DMA controllers
Simplified stimuli generation for scenario and assertion based verification
Reliability Evaluation of RISC-V and ARM Microprocessors Through a New Fault Injection Tool
18th IEEE Latin American Test Symposium, LATS 2017, Bogotá, Colombia, March 13-15, 2017
Design diversity redundancy with spatial-temporal voting applied to data acquisition systems
Very Fast Reliability Test at Wafer Level Applied to a BCD Technology
Acquiring real-time heating of cells in standard cell designs
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems
Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation
Approximate computing: Design & test for integrated circuits
Analysis of single-event upsets in a Microsemi ProAsic3E FPGA
Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC
Using a two-dimensional fault list for compact Automatic Test Pattern Generation
A cache based algorithm to predict HDL modules faults
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits
Failure Safe PLD Based Control System
Large Language Models for Printed Circuit Board Test Generation
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error
Bi-LORD: Bit-Wise Low-Cost Real Numbers Dependability Assessment in AI Applications
Case Study: Automated UPS Testing System for Final Test Applications in Industrial Environments
On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications
Evaluating test reuse of a software product line oriented strategy
Electronic Process Limited Yield
Probabilistic Error Correction in Linear Digital Filters Using Checksum Codes
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware
Dependability evaluation of distributed systems through partitioning fault injection