yusuke1997/dblp-id-title huggingface dataset:
The architecture value engine: measuring and delivering sustainable SoC improvement
2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, California, USA, November 7-10, 2011
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits
GACER: Granularity-Aware ConcurrEncy Regulation for Multi-Tenant Deep Learning
EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation
Dynamic Minimization of Bi-Kronecker Functional Decision Diagrams
QuBRIM: A CMOS Compatible Resistively-Coupled Ising Machine with Quantized Nodal Interactions
Estimating and optimizing BTI aging effects: from physics to CAD
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs
Bounded Model Checking of Speculative Non-Interference
ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication
Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper)
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection
Timing-Aware Fill Insertions with Design-Rule and Density Constraints
Sensitivity analysis of iterative design processes
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications
Combining BMC and Complementary Approximate Reachability to Accelerate Bug-Finding
INDUCTWISE: inductance-wise interconnect simulator and extractor
GauPRE: A Pattern-based Rendering Engine for Gaussian Splatting on Edge Device
QUARK: Quantization-Enabled Circuit Sharing for Transformer Acceleration by Exploiting Common Patterns in Nonlinear Operations
A performance analytical model for Network-on-Chip with constant service time routers
Learning-Based Power Modeling of System-Level Black-Box IPs
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms
Maximally fast and arbitrarily fast implementation of linear computations
Tearing based automatic abstraction for CTL model checking
2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors
DARL: Distributed Reconfigurable Accelerator for Hyperdimensional Reinforcement Learning
Fault-Tolerant Deep Learning Using Regularization
LADIES: an automatic layout system for analog LSI's
Delay-Matching Routing for Advanced Packages
An analytical model for negative bias temperature instability
Formal model of data reuse analysis for hierarchical memory organizations
A Fault Oriented Partial Scan Design Approach
Invited Paper: Resource Management on Heterogeneous Chiplets Systems
A data management interface as part of the framework of an integrated VLSI-design system
Generalized resource sharing
A Combined Logical and Physical Attack on Logic Obfuscation
Generating multiple correlated probabilities for MUX-based stochastic computing architecture
Feedback-Guided Circuit Structure Mutation for Testing Hardware Model Checkers
FPGA placement and routing
Formal deadlock checking on high-level SystemC designs
Learning Deep Neural Network Controllers for Dynamical Systems with Safety Guarantees: Invited Paper
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress
Clock distribution design and verification for PowerPC microprocessors
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling
A novel technique for incremental analysis of on-chip power distribution networks
Designing application-specific networks on chips with floorplan information
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization
Importance sampled circuit learning ensembles for robust analog IC design
Partitioning with cone structures
Reuse of design objects in CAD frameworks
Realizable reduction for RC interconnect circuits
An optimal simultaneous diode/jumper insertion algorithm for antenna fixing
Invited Paper: Overview of 2023 CAD Contest at ICCAD
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions
COTIA: Concolic Testing with Intelligent Agent
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Information theoretic approach to address delay and reliability in long on-chip interconnects
Gotta Hash 'Em All! Accelerating Hash Functions for Zero-Knowledge Proof Applications
Algorithms for MIS vector generation and pruning
A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects
Simulation of digital circuits in the presence of uncertainty
Measuring Error Propagation in Waveform Relaxation Algorithms
All-in-One: A Highly Representative DNN Pruning Framework for Edge Devices with Dynamic Power Management
Functional simulation using binary decision diagrams
Transforming control-flow intensive designs to facilitate power management
Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities
Fast transient power and noise estimation for VLSI circuits
Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers
Combining event and data-flow graphs in behavioral synthesis
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
Layout-Area Models for High-Level Synthesis
Representative Critical Reliability Paths for low-cost and accurate on-chip aging evaluation
Promise: Property Mining for Sequential Synthesis
Pyramids: an efficient computational geometry-based approach for timing-driven placement
Collaborative calibration of on-chip thermal sensors using performance counters
Efficient solution of systems of Boolean equations
Toward Instantaneous Sanitization through Disturbance-induced Errors and Recycling Programming over 3D Flash Memory
Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance
Compiling program control flows into biochemical reactions
Efficient computation of small abstraction refinements
Automatic test generation using neural networks
Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained Applications
Equivalent Lumped Element Model for Electromigration Considering Thermal Effects
A highly efficient optimization algorithm for pixel manipulation in inverse lithography technique
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis
Timing Analysis in Presence of Power Supply and Ground Voltage Variations
Machine learning on FPGAs to face the IoT revolution
Using complete-1-distinguishability for FSM equivalence checking
Cellular neural networks for image analysis using steep slope devices
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
Fast functional simulation using branching programs
Bridging Academic Open-Source EDA to Real-World Usability
TAPE: Thermal-aware agent-based power econom multi/many-core architectures
Error Correction and Detection for Analog AI Computing in Edge Systems
A Detailed Router for Field-Programmable Gate Arrays
Analytical solution of Poisson's equation and its application to VLSI global placement
On the computation of the ranges of detected delay fault sizes
Dynamic server power capping for enabling data center participation in power markets
Symbolic Debugging Scheme for Optimized Hardware and Software
A probabilistic timing approach to hot-carrier effect estimation
Adaptive-precision framework for SGD using deep Q-learning
Precomputation-based sequential logic optimization for low power
NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices
Verifying properties of hardware and software by predicate abstraction and model checking
CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation
An integrated design flow for a via-configurable gate array
Invited Paper: In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar
A local circuit topology for inductive parasitics
Generalized constraint generation for analog circuit design
A design for testability technique for RTL circuits using control/data flow extraction
Automatic Routability Predictor Development Using Neural Architecture Search
Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design
Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing
MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation
A hierarchical approach for generating regular floorplans
Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections
High-performance routing at the nanometer scale
OPTIMIST: state minimization for optimal 2-level logic implementation
Splitting functions in code management on scratchpad memories
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering
WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits
On the Signal Bounding Problem in Timing Analysis
Target Circuit Matching in Large-Scale Netlists Using GNN-Based Region Prediction
Sub-90nm technologies: challenges and opportunities for CAD
High-order Nyström schemes for efficient 3-D capacitance extraction
LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration
Optimizing Resource Utilization Using Transformations
Low-cost single-layer clock trees with exact zero Elmore delay skew
IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows
Device and architecture concurrent optimization for FPGA transient soft error rate
Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning
XPSim: a MOS VLSI simulator
Fault simulation of interconnect opens in digital CMOS circuits
Accelerating 3D Vertical Resistive Memories with Opportunistic Write Latency Reduction
Data Framework for VLSI Design
An algorithm for exploiting modeling error statistics to enable robust analog optimization
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
A novel synthesis algorithm for reversible circuits
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Obstacle-avoiding rectilinear Steiner tree construction
SODA: stencil with optimized dataflow architecture
How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computing
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration
Computing the Error Escape Probability in Count-Based Compaction Schemes
FlowTune: Practical Multi-armed Bandits in Boolean Optimization
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
Latest Advancements to the Industry-Leading EPDA Design Flow for Silicon Photonics: Invited Paper
Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network Inference
VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning
MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN Inference
ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions
Automatic test program generation for pipelined processors
High-performance Hardware Architecture for Tensor Singular Value Decomposition: Invited Paper
Latency tolerance for Throughput Computing: Designer track
Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus
Fill for shallow trench isolation CMP
Exact routing for digital microfluidic biochips with temporary blockages
Cell replication and redundancy elimination during placement for cycle time optimization
Formal derivation of optimal active shielding for low-power on-chip buses
Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D Structures
Invited Paper: Introduction to Hybrid Quantum-Classical Programming Using C++ Quantum Extension
Modeling and synthesis of quality-energy optimal approximate adders
Process and environmental variation impacts on ASIC timing
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits
Language Equation Solving via Boolean Automata Manipulation
Native-conflict-aware wire perturbation for double patterning technology
A fast and robust exact algorithm for face embedding
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper
Confronting and exploiting operating environment uncertainty in predictive analysis of signal integrity
A path-based methodology for post-silicon timing validation
Phase equations for quasi-periodic oscillators
The Safe and Effective Application of Probabilistic Techniques in Safety-Critical Systems
Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space
Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System
CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits
An optimal probe testing algorithm for the connectivity verification of MCM substrates
A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models
Crosstalk Fault Detection by Dynamic Idd
MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization
Stable and compact inductance modeling of 3-D interconnect structures
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators
When Semi-Supervised LVM Meets Frequency-Based Critical Layout Pattern Selection
The Internet of Microfluidic Things: Perspectives on System Architecture and Design Challenges: Invited Paper
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Multilevel design understanding: from specification to logic (invited paper)
DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters
Towards a rich sensing stack for IoT devices
Making split fabrication synergistically secure and manufacturable
The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : lnvited Paper
Cache miss clustering for banked memory systems
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019
An optimal transistor-chaining algorithm for CMOS cell layout
Ultra-low power NEMS FPGA
Towards true crosstalk noise analysis
Fractional Cut: Improved Recursive Bisection Placement
G-Contour: GPU Accelerated Contour Tracing For Large-Scale Layouts
An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications
Fast field solver-programs for thermal and electrostatic analysis of microsystem elements
Partial Scan by Use of Empirical Testability
Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs
Design and integration methods for a multi-threaded dual core 65nm Xeon® processor
RePM: Reconfigurable Elastic Computing for Polynomial Multiplier with Hybrid NTT Algorithm
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA
A Newton waveform relaxation algorithm for circuit simulation
Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning (Invited Paper)
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis
Scheduling a minimum dependence in FSMs
SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with Thermal-Tolerant, Power-Efficient In-situ Light Redistribution
A learning-on-cloud power management policy for smart devices
The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014
A timing model for static CMOS gates
An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM
PostPINN-EM: Fast Post-Voiding Electromigration Analysis Using Two-Stage Physics-Informed Neural Networks
Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy
A new approach to optimal cell synthesis
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking
AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits
Hybrid spectral/iterative partitioning
Node sampling: a robust RTL power modeling approach
Translating concurrent programs into delay-insensitive circuits
LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion
Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU
LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models
AU: Timing Analysis Under Uncertainty
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
A table look-up model using a 3-D isoparametric shape function with improved convergency
SOI Transistor Model for Fast Transient Simulation
STEEL: a technique for stress-enhanced standard cell library design
Aker: A Design and Verification Framework for Safe and Secure SoC Access Control
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints
On theoretical and practical considerations of path selection for delay fault testing
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits
Hybrid Analog-Digital In-Memory Computing
A novel SoC design methodology combining adaptive software and reconfigurable hardware
Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique
Adaptive variable reordering for symbolic model checking
Interconnect scaling implications for CAD
GPU programming for EDA with OpenCL
DevelSet: Deep Neural Level Set for Instant Mask Optimization
A novel framework for multilevel routing considering routability and performance
VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers
POWER7 - Verification challenge of a multi-core processor
SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks
Bounded-skew clock and Steiner routing under Elmore delay
Co-scheduling of HVAC control, EV charging and battery usage for building energy efficiency
HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural Networks
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Electromigration-aware routing for 3D ICs with stress-aware EM modeling
Dynamic transition relation simplification for bounded property checking
Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search
iPRIDE: a parallel integrated circuit simulator using direct method
Digital sensitivity: predicting signal interaction using functional analysis
Noise Resilient Compilation Policies for Quantum Approximate Optimization Algorithm
Clock skew optimization for ground bounce control
A partitioning algorithm for system-level synthesis
Efficient handling of large wiring data in TANGATE
Cycle time and slack optimization for VLSI-chips
Variability inspired implementation selection problem
Imaging, Computing, and Human Perception: Three Agents to Usher in the Autonomous Machine Computing Era
HIMALAYAS - a hierarchical compaction system with a minimized constraint set
Opto-ViT: Architecting a Near-Sensor Region of Interest-Aware Vision Transformer Accelerator with Silicon Photonics
How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K
Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA
Stimulus generation for constrained random simulation
Joint design-time and post-silicon optimization for digitally tuned analog circuits
Fast exact Toffoli network synthesis of reversible logic
Variation-aware performance verification using at-speed structural test and statistical timing
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
New decompilation techniques for binary-level co-processor generation
A Reconfigurable Hardware Library for Robot Scene Perception
Design automation for battery systems
Multi-level logic optimization of FSM networks
The impact of shallow trench isolation effects on circuit performance
Time-Frame Folding: Back to the Sequentiality
Decoupling capacitance efficient placement for reducing transient power supply noise
Lazy group sifting for efficient symbolic state traversal of FSMs
Automated Probe Repositioning for On-Die EM Measurements
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs
A spectrally accurate integral equation solver for molecular surface electrostatics
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit
Layout-driven test generation
Branch Merge Reduction of RLCM Networks
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Waiting false path analysis of sequential logic circuits for performance optimization
Multi-Objective Software-Hardware Co-Optimization for HD-PIM via Noise-Aware Bayesian Optimization
Bit-level arithmetic optimization for carry-save additions
Computation of bus current variance for reliability estimation of VLSI circuits
Behavioral simulation for noise in mixed-mode sampled-data systems
Equivalence Checking for Flow-Based Computing using Iterative SAT Solving
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees
PIGen: Accelerating ReRAM Co-Design via Generative Physics-Informed Modeling
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?
Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware
An exact gate decomposition algorithm for low-power technology mapping
REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations
Sampling schemes for computing OBDD variable orderings
Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators
Are LLMs Any Good for High-Level Synthesis?
Optimal Test Set Design for Analog Circuits
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
Practical, fast Monte Carlo statistical static timing analysis: why and how
Mitigation of intra-array SRAM variability using adaptive voltage architecture
Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm
Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem
A deterministic approach to stochastic computation
Combining partitioning and global routing in sea-of-cells design
Unified adaptivity optimization of clock and logic signals
PowerCool: simulation of integrated microfluidic power generation in bright silicon MPSoCs
Managing power and performance for System-on-Chip designs using Voltage Islands
Design tool integration using object-oriented database views
Battery-aware power management based on Markovian decision processes