yusuke1997/dblp-id-title huggingface dataset:
Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
A lightweight hybrid hardware/software approach for object-relative memory profiling
Factors affecting scalability of multithreaded Java applications on manycore systems
Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems
An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs
Performance Modeling and Analysis for AMD's High Performance Microprocessors
A Cross-platform Evaluation of Graphics Shader Compiler Optimization
Characterizing scalar opportunities in GPGPU applications
Evaluating and mitigating bandwidth bottlenecks across the memory hierarchy in GPUs
Keynote II: Integrated modeling challenges in extreme-scale computing
2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings
A Top-Down method for performance analysis and counters architecture
Benefits of I/O Acceleration Technology (I/OAT) in Clusters
Exploiting spatial architectures for edit distance algorithms
Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces
SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks
Last-Touch Correlated Data Streaming
Statistical usage testing applied to mobile network verification
Carbon-Aware Server Replacement
Accelerating architectural exploration using canonical instruction segments
Designing GPU Architecture for Memory Bandwidth Reservation
Hierarchical cycle accounting: a new method for application performance tuning
Pitfalls of InfiniBand with On-Demand Paging
A comparative benchmarking of the FFT on Fermi and Evergreen GPUs
PTAT: An efficient and precise tool for collecting detailed TLB miss traces
ASTRA-SIM: Enabling SW/HW Co-Design Exploration for Distributed DL Training Platforms
Performance Analysis of Graph Neural Network Frameworks
Trace filtering of multithreaded applications for CMP memory simulation
Considering all starting points for simultaneous multithreading simulation
Cetra: A trace and analysis framework for the evaluation of Cell BE systems
dist-gem5: Distributed simulation of computer clusters
Performance Optimization of Lattice Post-Quantum Cryptographic Algorithms on Many-Core Processors
Cache contention and application performance prediction for multi-core systems
SAPCo Sort: optimizing Degree-Ordering for Power-Law Graphs
Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach
Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
CMPSched$im: Evaluating OS/CMP interaction on shared cache management
Workload Characterization Using Hierarchical PCA
Eliminating on-chip traffic waste: are we there yet?
Performance and energy evaluation of data prefetching on intel Xeon Phi
A statistical machine learning based modeling and exploration framework for run-time cross-stack energy optimization
Can RDMA benefit online data processing workloads on memcached and MySQL?
Assessing the impact of reactive workloads on the performance of Web applications
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications
A semi-preemptive garbage collector for solid state drives
EEMBC and the Purposes of Embedded Processor Benchmarking
Performance-effective operation below Vcc-min
Characterizing the microarchitectural side effects of operating system calls
RAINBOW: Multi-Dimensional Hardware-Software Co-Design for DL Accelerator On-Chip Memory
Experiment flows and microbenchmarks for reverse engineering of branch predictor structures
Evaluation of MindPalace for Chip Design Tradeoffs on Function-as-a-Service
Performance characterization of mobile-class nodes: Why fewer bits is better
MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems
Methodology to optimize the cost/performance of disk subsystems
Reverse State Reconstruction for Sampled Microarchitectural Simulation
Multi-program benchmark definition
FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats
DARTS: Performance-counter driven sampling using binary translators
A study of hardware assisted IP over InfiniBand and its impact on enterprise data center performance
Accel-Bench: Exploring the Potential of Programming Using Hardware-Accelerated Functions
FlexCPU: A Configurable Out-of-Order CPU Abstraction
Estimating internal memory fragmentation for java programs under the binary buddy policy
Online compression of cache-filtered address traces
Elastic traces for fast and accurate system performance exploration
On the Application Level Impact of SSD Performance Anomalies
Selective commitment and selective margin: Techniques to minimize cost in an IaaS cloud
GPU Simulation Acceleration via Parallelization
Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications
DeLTA: GPU Performance Model for Deep Learning Applications with In-Depth Memory System Traffic Analysis
Performance Characterization of Decimal Arithmetic in Commercial Java Workloads
Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events
C^2AFE: Capacity Curve Annotation and Feature Extraction for Shared Cache Analysis
Storage consolidation: Not always a panacea, but can we ease the pain?
An analysis of hard to predict branches
Investigating the TLB Behavior of High-end Scientific Applications on Commodity Microprocessors
Modeling cache coherence misses on multicores
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2024, Indianapolis, IN, USA, May 5-7, 2024
MofySim: A mobile full-system simulation framework for energy consumption and performance analysis
Intel ® in-Memory Analytics Accelerator: Performance Characterization and Guidelines
Quality Time: A simple online technique for quantifying multicore execution efficiency
International IEEE Symposium on Performance Analysis of Systems and Software, ISPASS 2022, Singapore, May 22-24, 2022
SLA-guided energy savings for enterprise servers
Bridging the energy-efficiency gap in a future of massive data
Agave: A benchmark suite for exploring the complexities of the Android software stack
Accelerating Fully Homomorphic Encryption Through Microarchitecture-Aware Analysis and Optimization
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021
An automated framework for characterizing and subsetting GPGPU workloads
Influences of SIMD architectures for scattered data interpolation algorithm
The data-centricity of Web 2.0 workloads and its impact on server performance
DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference
LiveSim: A Fast Hot Reload Simulator for HDLs
CiFlow: Dataflow Analysis and Optimization of Key Switching for Homomorphic Encryption
Real-time image on QoS Web
Gem5-Based Evaluation of CVA6 SoC: Insights into the Architectural Design
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis
Performance Analysis of NVMe SSD-Based All-flash Array Systems
Power modeling and other new features in the Graphite simulator
Scalarization on Short Vector Machines
COSMOS: An LLC Contention Slowdown Model for Heterogeneous Multi-Core Systems
SimBench: A portable benchmarking methodology for full-system simulators
MindPalace: A Framework for Studying Microarchitecture Design of Function-as-a-Service
Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures
Performance Analysis of ARQ Protocols using a Theorem Prover
A software based profiling method for obtaining speedup stacks on commodity multi-cores
Transforming Java programs for concurrency using Double-Checked Locking pattern
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
Comparing multinomial and k-means clustering for SimPoint
Configurational Workload Characterization
RTRBench: A Benchmark Suite for Real-Time Robotics
Portable trace compression through instruction interpretation
Characterization of the data access behavior for TPC-C traces
Combining Simulation and Virtualization through Dynamic Sampling
Acquisition and evaluation of long DDR2-SDRAM access sequences
Roofline Model for UAVs: A Bottleneck Analysis Tool for Onboard Compute Characterization of Autonomous Unmanned Aerial Vehicles
Critical path analysis of the TRIPS architecture
Understanding the Performance Horizon of the Latest ML Workloads with NonGEMM Workloads
A Study on Mesh Hybrid Memory Cube Network
NyuziRaster: Optimizing rasterizer performance and energy in the Nyuzi open source GPU
An updated performance comparison of virtual machines and Linux containers
Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips
Simplified workload characterization using unified prediction
Evaluating Machine LearningWorkloads on Memory-Centric Computing Systems
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
An Analytical Cost Model for Fast Evaluation of Multiple Compute-Engine CNN Accelerators
BioBench: A Benchmark Suite of Bioinformatics Applications
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems
Microarchitectural Performance Evaluation of AV1 Video Encoding Workloads
Community-based Matrix Reordering for Sparse Linear Algebra Optimization
Comparing simulation techniques for microarchitecture-aware floorplanning
A Comparison of Two Approaches to Parallel Simulation of Multiprocessors
A SIMT Analyzer for Multi-Threaded CPU Applications
Prefetching for cloud workloads: An analysis based on address patterns
Efficient Split Counter Mode Encryption for NVM
Geist: a generator for e-commerce & internet server traffic
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling
PriME: A parallel and distributed simulator for thousand-core chips
Profiling an Architectural Simulator
Exploiting temporal locality in network traffic using commodity multi-cores
Using Model Trees for Computer Architecture Performance Analysis of Software Applications
Workload Characterization of Commercial Mobile Benchmark Suites
Computer Aided Engineering of Cluster Computers
Incorporating Instruction-Based Sampling into AMD CodeAnalyst
DSMM: A Dynamic Setting for Memory Management in Apache Spark
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures
Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads?
A Model Driven Approach Towards Improving the Performance of Apache Spark Applications
Using special-purpose hardware to achieve a hundred-fold speedup in molecular dynamics simulations of proteins
Spectral analysis for characterizing program power and performance
NVIDIA GPGPUs Instructions Energy Consumption
Self-monitoring overhead of the Linux perf_ event performance counter interface
Architectural Characterization of Processor Affinity in Network Processing
Eris: Fault Injection and Tracking Framework for Reliability Analysis of Open-Source Hardware
Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework
Quantifying Process Variations and Its Impacts on Smartphones
An evaluation of the POSIX trace standard implemented in RT-linux
Workload Characterization of Nondeterministic Programs Parallelized by STATS
Analyzing CUDA workloads using a detailed GPU simulator
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Fast and cycle-accurate modeling of a multicore processor
An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors
Selecting benchmark combinations for the evaluation of multicore throughput
ViStA: Video Streaming and Analytics Benchmark
The Strong correlation Between Code Signatures and Performance
Splash-3: A properly synchronized benchmark suite for contemporary research
FinGraV: Methodology for Fine-Grain GPU Power Visibility and Insights
Sources of error in full-system simulation
Aestimo: a feedback-directed optimization evaluation tool
Processor Performance Modeling using Symbolic Simulation
Use of simple analytic performance models for streaming data applications deployed on diverse architectures
Dissecting Performance Overheads of Confidential Computing on GPU-based Systems
Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance
Simulation sampling with live-points
Proxy benchmarks for emerging big-data workloads
The big pileup
Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation
An analytic model of optimistic Software Transactional Memory
DRAW: investigating benefits of adaptive fetch group size on GPU
CommBench-a telecommunications benchmark for network processors
Synergistic coupling of SSD and hard disk for QoS-aware virtual memory
GNNMark: A Benchmark Suite to Characterize Graph Neural Network Training on GPUs
JIT-assisted fast-forward embedding and instrumentation to enable fast, accurate, and agile simulation
A taxonomy of out-of-order instruction commit
Multi2Sim Kepler: A detailed architectural GPU simulator
A case for resource efficient prefetching in multicores
Benchmarking Test-Time Unsupervised Deep Neural Network Adaptation on Edge Devices
Mediating Power Struggles on a Shared Server
Efficient profile-based evaluation of randomising set index functions for cache memories
Early design phase power/performance modeling through statistical simulation
Understanding the Software and Hardware Stacks of a General-Purpose Cognitive Drone
Exploring the Efficiency of Data-Oblivious Programs
Pinpointing data locality bottlenecks with low overhead
Exploring speculative parallelism in SPEC2006
Conservative vs. Optimistic Parallelization of Stateful Network Intrusion Detection
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration
TransPimLib: Efficient Transcendental Functions for Processing-in-Memory Systems
Selective profiling of Java applications using dynamic bytecode instrumentation
User- and process-driven dynamic voltage and frequency scaling
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
A modeling framework for reuse distance-based estimation of cache performance
XFeatur: Hardware Feature Extraction for DNN Auto-tuning
Characterizing Dynamic Memory Behavior in WebAssembly Workloads
Performance evaluation of middleware bridging technologies
A Trace-Driven Simulator For Palm OS Devices
A cycle-level SIMT-GPU simulation framework
Checking order-insensitivity using ternary simulation in synchronous programs
Trace-driven simulation of multithreaded applications
An LTE Uplink Receiver PHY benchmark and subframe-based power management
MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks
Reducing BERT Computation by Padding Removal and Curriculum Learning
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
2012 IEEE International Symposium on Performance Analysis of Systems & Software, Austin, TX, USA, 21-23 April, 2013
Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs
An Improved Dynamic Vertical Partitioning Technique for Semi-Structured Data
Empirical evaluation of capacity estimation tools
Understanding the implications of virtual machine management on processor microarchitecture design
Characterizing the latency hiding ability of GPUs
How a single chip causes massive power bills GPUSimPow: A GPGPU power simulator
Reaping the Benefit of Temporal Silence to Improve Communication Performance
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
Panel Discussion: Architectures for the Future
Automatic memory hierarchy characterization
GPUCalorie: Floorplan Estimation for GPU Thermal Evaluation
Evaluation and optimization of multicore performance bottlenecks in supercomputing applications
Characterizing multi-threaded applications based on shared-resource contention
Variability of data dependences and control flow
GSI: A GPU Stall Inspector to characterize the sources of memory stalls for tightly coupled GPUs
Life lessons and datacenter performance analysis
Early-Adaptor: An Adaptive Framework forProactive UVM Memory Management
A single-specification principle for functional-to-timing simulator interface design
Do generational schemes improve the garbage collection efficiency?
An Analysis of Performance Interference Effects in Virtual Environments
Message from the General Chair; ISPASS 2024
MaxSim: A simulation platform for managed applications
Keynote II
POSET-RL: Phase ordering for Optimizing Size and Execution Time using Reinforcement Learning
Reverse engineering of cache replacement policies in Intel microprocessors and their evaluation
OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel
The BlueGene/L pseudo cycle-accurate simulator
TaskPoint: Sampled simulation of task-based programs
Accelerating private-key cryptography via multithreading on symmetric multiprocessors
Userspace Networking in gem5
Cross Binary Simulation Points
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2025, Ghent, Belgium, May 11-13, 2025
Motivation for Variable Length Intervals and Hierarchical Phase Behavior
Wall-clock based synchronization: A parallel simulation technology for cluster systems
SCALE-Sim V3: a Modular Cycle-Accurate Systolic Accelerator Simulator for End-To-End System Analysis
An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters
Trace-based Performance Analysis on Cell BE
Real-Time Characterization of Data Access Correlations
Program behavior characterization in large memory systems
Performance analysis in the real world of on line services
Quantifying the energy efficiency of FFT on heterogeneous platforms
PRISM: Zooming in persistent RAM storage behavior
Addressing service interruptions in memory with thread-to-rank assignment
Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations
Bottleneck Scenarios in Use of the Conveyors Message Aggregation Library
Reciprocal abstraction for computer architecture co-simulation
GPU-Qin: A methodology for evaluating the error resilience of GPGPU applications
A Detailed Model for Contemporary GPU Memory Systems
Partitioning Multi-Threaded Processors with a Large Number of Threads
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2023, Raleigh, NC, USA, April 23-25, 2023
Treelogy: A benchmark suite for tree traversals
A single-pass cache simulation methodology for two-level unified caches
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation
SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In-Memory Systems
SuiteSpecks and SuiteSpots: A methodology for the automatic conversion of benchmarking programs into intrinsically checkpointed assembly code
A full-system approach to analyze the impact of next-generation mobile flash storage
A statistical model of skewed-associativity
Performance analysis of thread mappings with a holistic view of the hardware resources
Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites
Performance characterization experience of multi-tier e-business systems using queuing operational analysis
Performance tradeoffs in sequencer design on a new G4 PowerPC TM microprocessor
ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures
Performance evaluation of real-time scheduling on a multicomputer architecture
Message from the program chair
ConCCL: Optimizing ML Concurrent Computation and Communication with GPU DMA Engines
Machine learning based online performance prediction for runtime parallelization and task scheduling
Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering
Power and performance analysis of network traffic prediction techniques
PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis
A co-phase matrix to guide simultaneous multithreading simulation
Analyzing communication models for distributed thread-collaborative processors in terms of energy and time
Analysis of PARSEC workload scalability
Scale-Model Architectural Simulation
From Flash to 3D XPoint: Performance Bottlenecks and Potentials in RocksDB with Storage Evolution
Opening and keynote 1
Architecture-Level Modeling of Photonic Deep Neural Network Accelerators
PowerSensor3: A Fast and Accurate Open Source Power Measurement Tool
CoolSim: Eliminating traditional cache warming with fast, virtualized profiling
Architectural characterization and similarity analysis of sunspider and Google's V8 Javascript benchmarks
2000 IEEE International Symposium on Performance Analysis of Systems and Software, April 24-35, 2000, Austin, Texas, USA, Proceedings
Lynx: A dynamic instrumentation system for data-parallel applications on GPGPU architectures
Chai: Collaborative heterogeneous applications for integrated-architectures
SEFsim: A Statistically-Guided Fast DRAM Simulator
Evaluation of an InfiniBand Switch: Choose Latency or Bandwidth, but Not Both
Memory access pattern-aware DRAM performance model for multi-core systems
Interactive analysis of large distributed systems with scalable topology-based visualization
CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool
Performance analysis of accelerated biophysically-meaningful neuron simulations
RayFlex: An Open-Source RTL Implementation of the Hardware Ray Tracer Datapath
Genomics-GPU: A Benchmark Suite for GPU-accelerated Genome Analysis
A Workload Characterization of the SPEC CPU2017 Benchmark Suite
Web latency reduction via client-side prefetching
On evaluating request-distribution schemes for saving energy in server clusters
A mathematical hard disk timing model for full system simulation
LIBRA: Enabling Workload-Aware Multi-Dimensional Network Topology Optimization for Distributed Training of Large AI Models
On the Rise of AMD Matrix Cores: Performance, Power Efficiency, and Programmability
CoCoPeLia: Communication-Computation Overlap Prediction for Efficient Linear Algebra on GPUs
Accuracy of performance counter measurements
High-level performance modeling of task-based algorithms
Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-Based GPUs
Performance Prediction for Multi-Application Concurrency on GPUs
Performance analysis of broadcasting algorithms on the Intel Single-Chip Cloud Computer
Workload sanitation for performance evaluation
Scalable, accurate multicore simulation in the 1000-core era
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing
Service capacity measurement by redlining with live production traffic
ADOR: A Design Exploration Framework for LLM Serving with Enhanced Latency and Throughput
Comparative Code Structure Analysis using Deep Learning for Performance Prediction
Data sharing in multi-threaded applications and its impact on chip design
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase Analysis
Characterization and cross-platform analysis of high-throughput accelerators
Energon: A Sustainability-Driven Modeling Framework for AI Data Centers
A study of Thread Level Parallelism on mobile devices
Compiler-directed physical address generation for reducing dTLB power
ARBench: Augmented Reality Benchmark For Mobile Devices
Energy efficiency of lossless data compression on a mobile device: An experimental evaluation
Towards a scalable data center-level evaluation methodology
Combined profiling: A methodology to capture varied program behavior across multiple inputs