yusuke1997/dblp-id-title huggingface dataset:
A new method for evaluating harmonic distortion in push-pull output stages
Design methods for CMOS low-current finely tunable voltage references covering a wide output range
Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator
Fast region-of-interest transcoding for JPEG 2000 images
Hybrid CMOS-RRAM Spiking CNNs with Time-Domain Max-pooling and Integrator Re-use
Adaptive Initialization for Recurrent Photonic Networks using Sigmoidal Activations
Interference resilient transmission scheme for multiband OFDM system in UWB channels
A quadratic-constrained least-squares approach to linear phase orthonormal filter bank design
Push-pull dc/ac inverter for large electroluminescent lamp
Millimeter-wave analysis of directional couplers
Advanced nanometer technology analog layout retargeting for lithography friendly design
A new segmentation technique for noisy multi-component signals using wavelet transform
Neural Networks Using Bit Stream Arithmetic: a Space Efficient Implementation
Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit Module
Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcoding
Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
A CMOS Implementation of a Spike Event Coding Scheme for Analog Arrays
A reference low-complexity structured ASIC
Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware
Implication logic synthesis methods for memristors
Layout-dependent effects aware g m /i D -based many-objective sizing optimization for analog integrated circuits
Constant quality rate control for streaming MPEG-4 FGS video
Reducing error accumulation effect in multithreaded memory systems
An embedded wavelet image coder with parallel encoding and sequential decoding of bit-planes
Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]
The diffserv cognitive network node with Controlled-UDP
Machine Learning Based Design of Magnetic Coupler for Wireless Power Transfer
High gain GaAs 10Gbps transimpedance amplifier with integrated bondwire effects
Highly flexible active notch filter for Cognitive Radio
Adaptive IIR Filtering via a Recursive Total Instrumental Variable Algorithm
An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction
Geometric moment in image watermarking
Frequency Response Masking based Reconfigurable Channel Filters for Software Radio Receivers
Derivation of circuit specification for the UWB impulse radio transceivers
Bias Distribution in ERSFQ VLSI Circuits
B-DTNMOS: a novel bulk dynamic threshold NMOS scheme
Detection of Fake Images Focused on Few Local Blocks
A microprocessor based system for ECG telemedicine and telecare
Development of energy-efficient fast-transient CMOS low-dropout regulators for SoC applications
A low voltage rail to rail V-I conversion scheme for applications in current mode A/D converters
Multilayered LSTM with Parameter Transfer for Vehicle Speed Data Imputation
On the synchronization condition of second-harmonic coupled QVCOs
Image authentication using chaotic mixing systems
Delay and power tradeoffs for static and dynamic register files
Analysis of Common-Mode Induced Even-Order Distortion in a Pseudo-Differential gm-C Filter
MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers
Parallel Implementation of a Cut and Paste Maze Routing Algorithm
Super-resolution image restoration from blurred observations
A necessary and sufficient condition for mismatch shaping in multi-bit DACs
Power-conscious design methodology for class-A switched-current wave filters
Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs
A multibit continuous time sigma delta modulator with successive-approximation quantizer
Improved design of fractional order differentiator using fractional sample delay
A Subband Coding Method for HDTV
Calibration-Enhanced 16-Channel On-Chip Seizure Classifier using Gated Recurrent Network
A sub-1 V, nanopower, ZTC based zero-VT temperature-compensated current reference
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers
Blind adaptive equalizer based on locally generated sub-carrier
A Temporal Neural System
Convergence Control of Relaxation Processes with Fine-Grain Locally-Connected Two-Scale Automata Networks
Low power architectures using localised non-volatile memory and selective power shut-down
Noise-Resilient and Interpretable Epileptic Seizure Detection
Image-reject receivers with image-selection functionality
Averaging attack resilient video fingerprinting
An ultra low-power capacitively-coupled chopper instrumentation amplifier for wheatstone-bridge readout circuits
Efficiency enhancement and linearity trade-offs for cascode vs. common-emitter SiGe power amplifiers in WiMAX polar transmitters
Background calibration of time-interleaved ADC using direct derivative information
On-line signature verification method utilizing feature extraction based on DWT
A method for reducing the variation in "on" resistance of a MOS sampling switch
Four-channel CMOS photoreceiver array for parallel optical interconnects
LSGP: Line-SIFT Geometric Pattern for wide-baseline image matching
A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems
A 16-channel CMOS chopper-stabilized analog front-end acquisition circuits for ECoG detection
A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic Gate
A Near Sensor Edge Computing System for Point Cloud Semantic Segmentation
Motion Compensated Video Compression and Dense Motion Field Coding
Oscillation frequency analysis of N-stage CMOS ring oscillator with wired-OR connections
An efficient non-selective adaptive motion compensated frame rate up conversion
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States
Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice Support
Behavioural Modelling of Mixed Signal ASICs: A new multi-level approach
Analysis and Modeling of ASIC Area at Early-Stage Design for Standard Cell Library Selection
Analysis of Virtual Load Damping Provision from IBR-Dominated Distribution Networks
Circuits and devices with integrated VFETs and RTDs
Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications
Data-stationary Controller for 32-bit Application-specific RISC
A Generalized Signal Quality Estimation Method for IoT Sensors
CMOS variable-gain wide-bandwidth CMFB-free differential current feedback amplifier for ultrasound diagnostic applications
A 3rd order MASH switched-capacitor ΣΔM using ultra incomplete settling employing an area reduction technique
Performance analysis by topology indexed lookup tables
A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes
Master-slave battery charging system using parallel DC-DC converters for thermal safety
A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications
Voltage-mode quaternary FPGAs: An evaluation of interconnections
On Continuous Partial Singular Value Decomposition Algorithms
Robust Stability of Linear Time-Delay Systems: Retarded and Neutral Types
Low complexity LFSR based bit-serial montgomery multiplier in GF(2 m )
A Thin Composite Emission Filter and Fiber Coupled Laser Excitation for Implantable Fluorescence Imager Application
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme
Architecture and implementation of a Software-Defined Radio baseband processor
Optimal resource allocation with node and link capacity constraints in complex networks
A framework for analog-digital mixed-precision neural network training and inference
MIXIC: a MIXed signal Interference Cancellation architecture to enhance a digitizer dynamic range
A 1V 0.54µW fourth order switched capacitor filter with switched opamp technique for cardiac pacemaker sensing channel
Design and switched-capacitor implementation of a new cascade-of-resonators Sigma-Delta converter configuration
A 2 × 50-Gb/s receiver with adaptive channel loss equalization and far-end crosstalk cancellation
An ISFET-based switched current DNA integrator
Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL
All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture
A background subtraction based column-parallel analog-to-information converter for motion-triggered vision sensor
A CAD Environment for Performance and Yield Driven Circuit Design Employing Electromagnetic Field Simulators
A 1.2 V bandgap reference based on transimpedance amplifier
Intrinsic mode functions for gait recognition
Transitional filters based on the classical polynomial approximations
Modulation Scheme Impact on Phase Noise in FMCW Radar for Short-Range Applications
A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO
Orthogonally tunable inductorless RF LNA for adaptive wireless systems
Direct design of phase factor in the common-factor technique for Hilbert-Pairs
Enhancing Identifiability of PUFs with Built-in Compensation through Nonlinear Transformations
Electromagnetic Compatibility Modeling in Low-Noise Medical Sensor Interfaces
A Low-Distortion Current-Mode Signal Generator for Wide-Range Bioimpedance Spectroscopy
Embedded reconfigurable array targeting motion estimation applications
Live demonstration: Asynchronous time-based image sensor (ATIS) camera with full-custom AE processor
A CMOS Image Sensor using Variable Reference Time Domain Encoding
Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model
Further results on primitive factorizations for nD polynomial matrices
A Bio-mimetic Leaf Wetness Sensor
Electronically controllable biquads using single CDBA
A Low noise CMOS image sensor with an emission filter for fluorescence applications
On Absolute Stability of Neural Networks
An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs
Application of Generalized Radial Basis Functions In Speaker Normalization and Identification
Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology
A single-chip real-time programmable video signal processor
A visual attention model for news video
Flexible and Cost Effective Transport Stream Processor for DTV
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method
Low-OSR asynchronous Sigma-Delta modulation high-order buck converter for efficient wideband switching amplification
High effective medical image segmentation with model adjustable method
Design of UWB pulses based on B-splines
A Vertex-Edge Graph Convolutional Network for Skeleton-Based Action Recognition
MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition
Error analysis and complexity optimization for the multiplier-less FFT-like transformation (ML-FFT)
Mathematic Modeling and Circuit Implementation on Multi-Valued Memristor
VLSI design of the shuffle-exchange network for 2D fast transforms
A simplified second-order HMM with application to face recognition
IIR filters with maximum impulse response symmetry
A Steady-state Operation Based Online Parameter Identification Method of Output Capacitor for DC-DC Buck Converters
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers
Construction of parallelized-decoding LDPC codes
An Integrated Smart Sensor for Flow and Temperature with I2C Bus Interface: FTS2
Block Optimal Structures for 2-D Separable-in-Denominator Digital Filters
HRTF Interpolation Through Direct Angular Parameterization
HybridFlow-DNA: A Deep Generative Compression Framework for DNA Storage of Images
Concurrent Sampling with Local Digitization - An Alternative to Analog Test Bus
A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme
A VLSI architecture for vector quantization with optimal search
A low-power MMSE MIMO detector using dynamic voltage wordlength scaling for 4×4 MIMO-OFDM systems
A current-mode spike-based overrange-subrange analog-to-digital converter
A novel post-nonlinear ICA-based reflectance model for 3D surface reconstruction
Recent progress in terahertz monolithic integrated circuits
Using H.264/AVC-based Scalable Video Coding (SVC) for Real Time Streaming in Wireless IP Networks
An improved binary algorithmic A/D converter architecture
A numerical algorithm for computing Neimark-Sacker bifurcation parameters
Flexible Integrated Circuits via Stress-minimized Layout and Ultra-thin Chip
Five-level hybrid DC-DC converter with enhanced light-load efficiency
Wavelet method for high-speed clock tree simulation
TraND: Transferable Neighborhood Discovery for Unsupervised Cross-Domain Gait Recognition
Finite state machine state assignment for area and power minimization
Integrating edge detector and bilateral noise filter for enhancing color images
Optimal resource allocation for multimedia cloud in priority service scheme
Fast mode selection to reduce the encoding complexity of H.264/AVC
Device Circuit Interaction in the Common Source Amplifier
Robustness of Local Adaptive Synchronization Strategies to Topological Variations and Delays
Line-based image coding using adaptive prediction filters
Nonlinear dynamics of a nonideal sigma-delta modulator with periodic input
Unified digital sliding mode control with inductor current ripple reconstruction for DC-DC converters
Live demonstration: Real-time audio restoration using sparse signal recovery
Heap charge pump optimisation by a tapered architecture
A circuit model for open-loop compensation of hysteresis
A directional decomposition: theory, design, and implementation
Inverter-Based Fully-Differential Amplifier with 150 mV minimum Supply Voltage
A population-level approach to temperature robustness in neuromorphic systems
An area efficient design methodology for SEU tolerant digital circuits
A synthesis tool for the multiplierless realization of FIR-based multirate DSP systems
Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders
Arbitrarily Sized Cell Placement by Self-organizing Neural Networks
A two level mode decision algorithm for H.264 high profile intra encoding
Integrated SIMO DC-DC converter with on-line charge meter for adaptive PCCM operation
Gradient sensitivity reduction in current mirrors with non-rectangular layout structures
A Ripple-Based Constant On-Time Controlled DC-DC Buck Converter with Inductor Current Sensing Technique
Methodology for multi-layer interdigitated power and ground network design
Reconfigurable and programmable minimum distance search engine for portable video compression systems
Optimal filtering and smoothing thresholds for high-frequency photoplethysmography signals
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation
A low-power 0.5V regulator with settling enhancement for wireless sensor nodes
Realization of electronically tunable ladder filters using multi-output current controlled conveyors
An Energy-Efficient CMOS Biophotometry Sensor With Incremental DT-∑Δ ADC Conversion
Live Demonstration: Man-in-the-Middle Attack on Edge Artificial Intelligence
Adjustable gamma correction circuit for TFT LCD
Continuous-time noise-shaping modulators with delay elements
Improving the performance of RISC-V softcores on FPGA by exploiting PVT variability and DVFS
Dynamic Droop Scaling for Improving Current Sharing Performance in a System with Multiple Supplies
High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning
Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators
A hand-held neutron detection sensor system
McFIS: Better I-frame for video coding
A Common Invariant Subspace Approach to Exact Order Reduction for Multidimensional Roesser State-Space Models
A composable service model for lossy network elements
Pipelined parallel contrastive divergence for continuous generative model learning
Low power current comparator cell for weak current operations
Parallel sub-convolution filter bank architectures
Low complexity architecture design of MDCT-based psychoacoustic model for MPEG 2/4 AAC encoder
On the wavelet-based elimination of stimulus artifacts in click-evoked otoacoustic emissions
4.7pJ/pulse 7th Derivative Gaussian Pulse Generator for Impulse Radio UWB
Joint source-channel coding of images using punctured convolutional codes and trellis-coded quantization
Impact of Distributed Secondary Control on Transient Stability of Islanded Microgrids
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs
Multi-loop efficient sturdy MASH delta-sigma modulators
An Adaptive CMOS-based PG-ISFET for pH Sensing
Interactive broadcast terminal system using MPEG-2 and MPEG-4
Memorize, Then Recall: A Generative Framework for Low Bit-Rate Surveillance Video Compression
A 15-nW 14-ppm/°C 1.18 V startup-less bandgap-based voltage regulator
No-reference stereo image quality assessment by learning gradient dictionary-based color visual characteristics
Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression
A One-Point-Trimmed 18.4 ppm/°C On-Chip Oscillator with Capacitively-Biased-Diode-based Quasi-Digital Temperature Compensation
A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing
VLSI Architecture of Polynomial Multiplication for BGV Fully Homomorphic Encryption
Generic, scalable and efficient shape coding for visual texture objects in MPEG-4
A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop
Current-mode automated quality control cochlear resonator for bird identity tagging
Acceleration of rate-distortion optimized quantization for H.264/AVC
A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation
High Throughput/Gate FN-Based Hardware Architectures for AES-OTR
A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet
A Memristor Model with a Modified Window Function and Activation Thresholds
Large margin strategies in machine learning
Characterization of charge-pump rectifiers for standard submicron CMOS processes
A signal reconstruction method based on an unwrapping of signals in transform domain
Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters
A low-quiescent current two-input/output buffer amplifier for LCDs
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library
A compact digital frequency synthesizer for GSM IF up/downconverter
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation
A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver
Asynchronous, quasi-Adiabatic (Asynchrobatic) logic for low-power very wide data width applications
A Two-pole Circuit Model for VLSI High-speed Interconnection
FIR digital filter implementation using flattened coefficient
A low power and low voltage continuous time ΣΔ modulator
A new zero-current-switching constant switching frequency boost converter
DET FF topologies: A detailed investigation in the energy-delay-area domain
A 12 Gb/s chip-to-chip AC coupled transceiver
A low-power 8-bit SAR ADC for a QCIF image sensor
A reconfigurable architecture for the FFT operator in a software radio context
Over-the-Cell Routing with Cell Orientations Consideration
New dynamic logic-level converters for high performance application
Design of an efficient memory-based DVB-T channel decoder
Pairing and ordering to reduce hardware complexity in cascade form filter design
A 5 GHz dual-mode WiMAX/WLAN direct-conversion receiver
A novel noise optimization design technique for radio frequency low noise amplifiers
A short tutorial on network calculus. II. Min-plus system theory applied to communication networks
Improving the Testability of VLSI Circuits through Partitioning
Public key protocol for usage-based licensing of FPGA IP cores
1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing
A wide bandwidth, on-line impedance measurement method for power systems, based On PLC techniques
Feedback control of paralleled symmetric systems, with applications to nonlinear dynamics of paralleled power converters
Exact Data Retrieval of Associative Memory with Further Reduced Cross Talk
A comparative study of different chaos based spread spectrum communication systems
FPGA-based radix-4 butterflies for HIPERLAN/2
An inter-image redundancy measure for image set compression
Best Practices for Phase Noise Simulations of Free Running Ring Oscillators for Crystal-Free Narrowband FSK Communication Systems
Privacy-Protected Denoising for Signals on Graphs from Distributed Systems
Design and Analysis of a Current-reuse Transmitter for Ultra-low Power Applications
Miniature Implantable System Dedicated to Bi-Channel Selective Neurostimulation
Complementary pole-pair filters - A new family of transitional filters
Minimization of roundoff noise in state-space digital filters using error feedback and coordinate transformation
Simulation of Transmission Lines with Frequency Dependent Lossed By Indirect Numerical Integration
Calculation of multiple power flow solutions with the Krawczyk method
Hardware architecture design for H.264/AVC intra frame coder
Prototype filter design for oversampled subband adaptive filtering structures
Coding efficiency of bandlimited PWM based burst-mode RF transmitters
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
A novel nonlinear modulation technique for stabilizing DC-DC switching converters
A multiplierless filter bank with deep stopband suppression and narrow transition width
Spatial-Temporal Visual Attention Model for Video Quality Assessment
A study on linear single-loop feedback systems using geometric vectors
Effects of training data distribution on backpropagation generalization
CMOS Current-controlled Oscillators
Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation
Total Least Squares Approach for Fast Learning in Multilayer Neural Networks
Creating a Unique Digital Fingerprint using Existing Combinational Logic
A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems
3-neighborhood motion estimation in CNN silicon architectures
Computing in the Fog with Reconfigurable Gateways
A low cost technique for scan chain diagnosis
A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation
Rail-to-rail tunable CMOS V-I converter
Wide-Band Inductorless and Capacitorless LNTA Based on Cascode Inverters
A time domain measurements procedure of piezoelectric transformers equivalent scheme parameters
Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation
Design of frequency-response-masking FIR filters using SOCP with coefficient sensitivity constraint
Digital foreground calibration methods for SAR ADCs
CMOS outlier rejection circuit
An error pattern ROM compression method for continuous data
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS
Joint source channel coding with Hermitian symmetric DFT codes
Implementation of a programmable 64~2048-point FFT/IFFT processor for OFDM-based communication systems
A High-Quality Analog Oscillator Using Oversampling D/A Conversion Techniques
Cooperative and competitive cellular neural networks
An 8-Channel 0.45mm2/Channel EEG Recording IC with ADC-Free Mixed-Signal In-Channel Motion Artifact Detection and Removal
Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks
Systematic approach for discrete-time to continuous-time transformation of Sigma-Delta modulators