yusuke1997/dblp-id-title huggingface dataset:
NeuroMAX: A High Throughput, Multi-Threaded, Log-Based Accelerator for Convolutional Neural Networks
PrivQuant: Communication-Efficient Private Inference with Quantized Network/Protocol Co-Optimization
Polynomial datapath optimization using constraint solving and formal modelling
An O( n 3 log n )-Heuristic for Microcode Bit Optimization
A realistic variable voltage scheduling model for real-time applications
An efficient algorithm for the net matching problem
Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper
Invited Paper: Solving Fine-Grained Static 3DIC Thermal with ML Thermal Solver Enhanced with Decay Curve Characterization
Scalable and Asynchronous Differential Checkpointing for Intermittently Powered Devices
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators
ABACUS: Address-partitioned Bloom filter on Address Checking for UniquenesS in IoT Blockchain
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits
DeepGate2: Functionality-Aware Circuit Representation Learning
Provably correct high-level timing analysis without path sensitization
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes
Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits
Systolic Array Placement on FPGAs
FlexHE: A flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference
Run-time adaptive on-chip communication scheme
Probabilistic state space search
A fast layer elimination approach for power grid reduction
Robust and passive model order reduction for circuits containing susceptance elements
Decomposing Refinement Proofs Using Assume-Guarantee Reasoning
Dynamic power management of electronic systems
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Fixed-Priority Scheduling and Controller Co-Design for Time-Sensitive Networks
Track assignment: a desirable intermediate step between global routing and detailed routing
AFReP: Application-guided Function-level Registerfile power-gating for embedded processors
CamoPerturb: secure IC camouflaging for minterm protection
Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization
EqMap: FPGA LUT Remapping using E-Graphs
The FAST methodology for high-speed SoC/computer simulation
SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm
Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper)
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
Warranty-aware page management for PCM-based embedded systems
Banked scratch-pad memory management for reducing leakage energy consumption
Copyright protection of designs based on multi source IPs
CIMTester: An Agile Golden-Result-Free BIST Compiler for Robust Compute-In-Memory
iEDISON: an interactive statistical design tool for MOS VLSI circuits
Including inductance in static timing analysis
Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy
Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan
IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs
An escape routing framework for dense boards with high-speed design constraints
Self-Error Detection and Correction Techniques for Reliable and Efficient Selector-Only Memory
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
SLIP: a software environment for system level interactive partitioning
MapFormer: Attention-based multi-DNN manager for throughout & power co-optimization on embedded devices
Automated extraction of expert knowledge in analog topology selection and sizing
Acceleration techniques for dynamic vector compaction
Improving soft-error tolerance of FPGA configuration bits
MACACO: Modeling and analysis of circuits for approximate computing
Molecular organic electronic circuits
DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism
A rigorous framework for convergent net weighting schemes in timing-driven placement
Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration
A History Model for Managing the VLSI Design Process
Accelerating Polynomial Modular Multiplication with Crossbar-Based Compute-in-Memory
DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation
High level synthesis for reconfigurable datapath structures
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Symbolic performance analysis of elastic systems
Heterogeneous B ∗ -trees for analog placement with symmetry and regularity considerations
Fullwave volumetric Maxwell solver using conduction modes
Dictionary-based error recovery in cyberphysical digital-microfluidic biochips
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design
A method for calculating hard QoS guarantees for Networks-on-Chip
A bitmask-based code compression technique for embedded systems
Arbitrary streaming permutations with minimum memory and latency
Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper
Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs
Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time
Retiming for Wire Pipelining in System-On-Chip
BIST design optimization for large-scale embedded memory cores
Practicality of state-machine verification of speed-independent circuits
Towards Effective Training of Robust Spiking Recurrent Neural Networks Under General Input Noise via Provable Analysis
High-Resolution Full-Chip Thermal Resistance Extraction of BEOL Interconnects in 3-D ICs Considering Detailed Via Connectivity
Algorithms for Discrete Function Manipulation
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite
FlexInt: A New Number Format for Robust Sub-8-Bit Neural Network Inference
A Monte Carlo Tree Search Framework for Quantum Circuit Transformation
A variation-aware preferential design approach for memory based reconfigurable computing
Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation
Efficient crosstalk noise modeling using aggressor and tree reductions
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling
Efficient Formal Verification and Debugging of Arithmetic Divider Circuits
A new incremental placement algorithm and its application to congestion-aware divisor extraction
PRIMA: passive reduced-order interconnect macromodeling algorithm
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Sequential engineering change order under retiming and resynthesis
SWAN: mitigating hardware trojans with design ambiguity
Efficient aerial image simulation on multi-core SIMD CPU
2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Analysis of circuit dynamic behavior with timed ternary decision diagram
FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery: Special Session Paper
Fast and accurate emissivity and absolute temperature maps measurement for integrated circuits
Representation and symbolic manipulation of linearly inductive Boolean functions
Multilevel Optimization for Large-Scale Circuit Placement
Dynamic reliability management for near-threshold dark silicon processors
On the use of Bloom filters for defect maps in nanocomputing
Compact lateral thermal resistance modeling and characterization for TSV and TSV array
GLADE: A modern global router considering layer directives
Engineering change using spare cells with constant insertion
TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps
Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation
Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks
ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding
A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD
CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction
Parameterized model order reduction via a two-directional Arnoldi process
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY
Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters
CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile Devices
Accelerated statistical simulation via on-demand Hermite spline interpolations
On application of data mining in functional debug
An Algorithm for Locating Logic Design Errors
Modeling and estimation of power supply noise using linear programming
GNN-Based Performance Prediction of Quantum Optimization of Maximum Independent Set
Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk)
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Efficient parallel power grid analysis via Additive Schwarz Method
Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons
Expected current distributions for CMOS circuits
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
A Hardware-Aware Gate Cutting Framework for Practical Quantum Circuit Knitting
LeapChain: efficient blockchain verification for embedded IoT
Toward codesign in high performance computing systems
On power and fault-tolerance optimization in FPGA physical synthesis
Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption
Just Enough is More: Achieving Sustainable Performance in Mobile Devices under Thermal Limitations
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction
FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs
How to bridge the abstraction gap in system level modeling and design
SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance
Multi-layer global routing considering via and wire capacities
EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler
Mixed-cell-height placement with complex minimum-implant-area constraints
Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints
False Data Injection Attacks on Sensor Systems
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Extraction of circuit models for substrate cross-talk
Hierarchical memory scheduling for multimedia MPSoCs
Inductive equivalence checking under retiming and resynthesis
Statistical behavioral modeling and characterization of A/D converters
Wire-length prediction using statistical techniques
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation
Functional test generation for delay faults in combinational circuits
Architecting data placement in SSDs for efficient secure deletion implementation
Accelerate FPGA Routing with Parallel Recursive Partitioning
LLM-AID: Leveraging Large Language Models for Rapid Domain-Specific Accelerator Development
A Circuit-Based SAT Solver for Logic Synthesis
Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs
A methodology for correct-by-construction latency insensitive design
Performance Efficiency of Context-Flow System-on-Chip Platform
Engineering an Efficient Boolean Functional Synthesis Engine
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures
Efficient Automatic Diagnosis of Digital Circuits
DAMO: Deep Agile Mask Optimization for Full Chip Scale
Computation of signal threshold crossing times directly from higher order moments
Near-optimal energy allocation for self-powered wearable systems
UFO-MAC: A Unified Framework for Optimization of High-Performance Multipliers and Multiply-Accumulators
TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation
OFT: An accelerator with eager gradient prediction for attention training
A just-in-time customizable processor
SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space
Circuit Performance Variability Reduction: Principles, Problems, and Practical Solutions
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
CorDBA: Corners Decoupled Bayesian Approach for yield optimization
Deep-Learning Model Extraction Through Software-Based Power Side-Channel
Automatic Hierarchical Design: Fantasy or Reality? (Panel)
Sensitization criterion for threshold logic circuits and its application
A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers
Tucker Tensor Decomposition on FPGA
Multi-Objective Architecture Search and Optimization for Heterogeneous Neuromorphic Architecture
Incremental learning approach and SAT model for Boolean matching with don't cares
Accelerating garbage collection for 3D MLC flash memory with SLC blocks
ECO timing optimization using spare cells
A routing algorithm for flip-chip design
Test-model based hierarchical DFT synthesis
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines
Factoring and eliminating common subexpressions in polynomial expressions
An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration
Exploitation of Periodicity in Logic Simulation of Synchronous Circuits
A framework for statistical timing analysis using non-linear delay and slew models
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia
Impact of range and precision in technology on cell-based design
Interface specification for reconfigurable components
Cost-effective design of scalable high-performance systems using active and passive interposers
Layout small-angle rotation and shift for EUV defect mitigation
Invited Paper: Toward Secure In-Sensor Intelligence: Threats and Defenses in SNNs
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications
2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008
An efficient macromodeling approach for statistical IC process design
Characterizing the lifetime reliability of manycore processors with core-level redundancy
Single-layer fanout routing and routability analysis for Ball Grid Arrays
A Super-Scheduler for Embedded Reconfigurable Systems
Timing Optimization with Testability Considerations
An algorithm for hierarchical floorplan design
Style: a technology-independent approach to statistical design
Blockage-aware terminal propagation for placement wirelength minimization
DSA-compliant routing for two-dimensional patterns using block copolymer lithography
ROAdNoC: runtime observability for an adaptive network on chip architecture
DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI
Evaluation of Placement Techniques for DNA Probe Array Layout
A framework for accelerating neuromorphic-vision algorithms on FPGAs
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs
Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives
Area-efficient and low-power face-to-face-bonded 3D liquid state machine design
Adapative Error Protection for Energy Efficiency
Period assignment in multidimensional periodic scheduling
The maximum set of permissible behaviors for FSM networks
On-chip interconnect modeling by wire duplication
Optimal P/N width ratio selection for standard cell libraries
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory
Automated abstraction by incremental refinement in interpolant-based model checking
Factoring logic functions using graph partitioning
Provably Good Global Buffering Using an Available Buffer Block Plan
Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997
DISC: Exploiting Data Parallelism of Non-Stencil Computations on CGRAs via Dynamic Iteration Scheduling
Stabilizing schemes for piecewise-linear reduced order models via projection and weighting functions
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL
Towards Energy-Aware Federated Learning via MARL: A Dual-Selection Approach for Model and Client
Engineering education: trends and needs (panel)
Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodes
Contrastive Learning with Temporal Correlated Medical Images: A Case Study using Lung Segmentation in Chest X-Rays (Invited Paper)
Bipolar Timing Modeling Including Interconnects Based on Parametric Correction
A hybrid ASIC and FPGA architecture
How will CAD handle billion-transistor systems? (panel)
DRC-based hotspot detection considering edge tolerance and incomplete specification
Challenges at 45nm and beyond
A Two-Level Two-Way Partitioning Algorithm
Performance-driven partitioning using retiming and replication
CMOS analog circuit stack generation with matching constraints
Quantitative Cost Model and Cost Optimization Methods for Multi-Technology-Node Architecture
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation
CLANS: a high-level synthesis tool for high resolution data converters
Comparing models of computation
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms
Minimum padding to satisfy short path constraints
High-level synthesis using computation-unit integrated memories
CNOT Oriented Synthesis for Small-Scale Boolean Functions Using Spatial Structures of Parallelotopes
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
Memory partitioning and scheduling co-optimization in behavioral synthesis
Redistribution layer routing for wafer-level integrated fan-out package-on-packages
Timing optimization of combinational logic
Optimization and control of V DD and V TH for low-power, high-speed CMOS design
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists
An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design
On mask layout partitioning for electron projection lithography
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Hybrid Power Failure Recovery for Intermittent Computing
Test quality and yield analysis using the DEFAM defect to fault mapper
Efficient estimation of dynamic power consumption under a real delay model
A Hybrid FPGA-ASIC Delayed Feedback Reservoir System to Enable Spectrum Sensing/Sharing for Low Power IoT Devices ICCAD Special Session Paper
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-
Checkpoint Placement for Systematic Fault-Injection Campaigns
LiTformer: Efficient Modeling and Analysis of High-Speed Link Transmitters Using Non-Autoregressive Transformer
Simulating Electromagnetic Radiation of Printed Circuit Boards
Power grid verification under transient constraints
check T c and min T c : Timing Verification and Optimal Clocking of Synchronous Digtal Circuits
A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation
Instruction selection using binate covering for code size optimization
System-level thermal aware design of applications with uncertain execution time
Invited Paper: Pushing SIMD Efficiency in Homomorphic Encryption for Machine Learning via Pattern-Aware Ciphertext Encoding
Optimized power-delay curve generation for standard cell ICs
Non-Negative AdderNet: Algorithm-Hardware Co-design for Lightweight Defense of Adversarial Bit-Flip Attacks
ScaleDNN: Data Movement Aware DNN Training on Multi-GPU
Hybrid techniques for electrostatic analysis of nanowires
Detection of symmetry of Boolean functions represented by ROBDDs
Observability Analysis of Embedded Software for Coverage-Directed Validation
Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree
ZnH2: Augmenting ZNS-based Storage System with Host-Managed Heterogeneous Zones
Co-design of channel buffers and crossbar organizations in NoCs architectures
Critical path isolation for time-to-failure extension and lower voltage operation
HyperNode: An Efficient Node Classification Framework Using HyperDimensional Computing
VLSI Placement Using Uncertain Costs
The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions
APPlaUSE: Area and performance optimization in a unified placement and synthesis environment
2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017
Verification of arithmetic datapaths using polynomial function models and congruence solving
POLAR: placement based on novel rough legalization and refinement
Architecting parallel programs
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment
Genetic design automation
Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN Accelerators
Nyquist data converter testing and yield analysis using behavioral simulation
High-radix on-chip networks with low-radix routers
PUF-Based Authentication
Quantum State Preparation Based on LimTDD
Dynamic compilation for energy adaptation
Triple patterning lithography aware optimization for standard cell based design
BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization
Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise
Parallel Simulation Algorithms for Grid-Based Analog Signal Processors
JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whitespace and Overlap among Complex Rectilinear Modules
A General S-Domain Hierarchical Network Reduction Algorithm
Folding a stack of equal width components
Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization