yusuke1997/dblp-id-title huggingface dataset:
Cell-to-array thermal-aware analysis of stacked RRAM
GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI
Joint source-channel content-based multistream video coding scheme
Design of half sample delay IIR filter using continued fraction expansion
An MRAM-Based Deep In-Memory Architecture for Deep Neural Networks
An ISFET based sensing array with sensor offset compensation and pH sensitivity enhancement
Modeling of layered video for low-bit-rate video conferencing applications
A unified architecture of MD5 and RIPEMD-160 hash algorithms
A Convoluted Journey from CMOS to Spin Waves
Aerial LiDAR-based 3D Object Detection and Tracking for Traffic Monitoring
Cascading Failure Model Considering Multi-Step Attack Strategy
An Auto-offset-removal Circuit for Chemical Sensing based on the PG-ISFET
A systematic framework for high throughput MAP decoder VLSI architectures
Structured design of an integrated subscriber line interface system and circuit
Synchronization Phenomena in RC Oscillators Coupled by One Resistor
Design and implementation of a bidirectional SEPIC-Zeta DC-DC Converter
An FPGA-Friendly Algorithm for QR Code Detection
A mixed analog-digital realization of the LMS algorithm using sigma-delta modulators
High resolution ADC spectral test with known impure source and non-coherent sampling
Design of a low power mixed-signal RAKE receiver
A Hierarchical Parallel Discrete Gaussian Sampler for Lattice-Based Cryptography
Block-level parallel processing for scaling evenly divisible frames
An Algorithmic Ternary A/D, D/A Converter
A Low-Power Voltage-Clamped CMOS pH to Frequency Sensor
High-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver
Optimal Nonrecursive Noise Shaping Filters for Oversampling Data Converters Part 2: Applications
Binary LNS-based naive Bayes hardware classifier for spam control
Ring type switched-capacitor transformer and its applications
RTL/ISS co-modeling methodology for embedded processor using SystemC
Parallelizing video transcoding with load balancing on cloud computing
Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design
Color Tone-Mapping Circuit for a Focal-Plane Implementation
Linear and nonlinear macromodels for power/signal integrity
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA
A Dual-Mode Seamless Transition Low-Dropout Regulator with Improved Load Transient Response for RF Energy-Harvesting Application
A DLL based 10-320 MHz clock synchronizer
The detection bound of the probability of error in compressed sensing using Bayesian approach
High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos
The study of synchronous and frequency demultiplication phase-locking for coupling each other system with two BNRT oscillators
IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, May 25-28, 2025
An efficient homotopy method that can be easily implemented on SPICE
An Ising Machine Based on Millimeter-Wave Coupled LC Oscillators
Buffer planning based on block exchanging
Low-order Fixed Denominator IIR VFD Filter Design
A Novel SoC Design of Adaptive Stabilization Engine for Metastable PUF Source
High Level Synthesis with Testability Constraints
Single channel speech enhancement using subband iterative Kalman filter
A Shuffled Message-passing Decoding Method for Memory-based LDPC Decoders
A fast dual-field modular arithmetic logic unit and its hardware implementation
Complex Cascade Digital Filters
Analysis of aperiodic and chaotic motions in a switched reluctance linear motor
A finite wordlength analysis of an LMS-Newton adaptive filtering algorithm
Segmenting specific object based on logo detection
Silicon spike-based synaptic array and address-event transceiver
Power transfer networks at RF frequencies: new design procedures with implementation roadmap
A novel neural oscillator and its implementation in analog VLSI
Capacitor mismatch error cancellation technique for a successive approximation A/D converter
An Enhanced Scheme for Second-order-statistics Estimation in MIMO-OFDM Systems
CMOS image sensor with watermarking capabilities
Hilbert pair of wavelets via the matching design technique [matched filters]
Harmonic-balance analysis of nonlinear energy harvester models
Filtering heavy noised images using ICI rule for adaptive varying bandwidth selection
Design of low-complexity, non-separable 2-D transforms based on butterfly structures
Simulator-Based Optimization Software for High-Frequency Power-Electronics Circuits
Human vs. computer slot car racing using an event and frame-based DAVIS vision sensor
A Random Number Generator Based on Irregular Sampling and Transient Effect Ring Oscillators
Robustness of One Bit Per Sample Audio Watermarking
Live Demonstration: Capacitive-Based Gesture Recognition System for Human-Machine Interface in Automotive Applications
A FVF based output capacitorless LDO regulator with wide load capacitance range
Low-power 6-bit flash ADC for high-speed data converters architectures
A real-time line extraction algorithm
Robust CMOS Pseudo-resistor and its Applications in Bio-medical Amplifiers
Integrated multi-objective cross-layer optimization for wireless multimedia transmission
Discrete-time modeling of polynomial-based interpolation filters in rational sampling rate conversion
Using Binary Decision Diagrams to Speed up the Test Pattern Generation of Behavioral Circuit Descriptions Written in Hardware Description Languages
Circuit Model of Coupled Transmission Lines with Frequency-Dependent Transformations
Sneak-Path Effect on Chimera states of Memristor-coupled Chua Circuit Networks
A 10-bit 100kS/s SAR ADC With a Monotonic Capacitor Switching Procedure for Single-Ended Inputs in 22nm CMOS FDSOI
A No-Reference Deep Learning Quality Assessment Method for Super-Resolution Images Based on Frequency Maps
Low-complexity global motion estimation based on content analysis
Low power current mode ADC for CMOS sensor IC
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET
Battery voltage prediction for portable systems
Evaluating a bounded slice-line grid assignment in O(nlogn) time
A Mismatch Compensation Scheme for Cyclic-pipelined ADC via Dynamic Element Matching Technique
A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter with automatic tuning system
Stability analysis of higher-order delta-sigma modulators using the describing function method
PLL frequency synthesizer with an auxiliary programmable divider
Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family
Unified Implementation of Electrode and Coil for Inductive Coupling in biomedical applications
Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop
15-40 GHz Broadband Variable Gain Amplifier with 24.5 dB Linear-in-Decibel Gain Control Range in SiGe BiCMOS
Nonlinear processing of n-dimensional phase signals
Preliminary Steps Towards a Low Power Integrated Circuit for AgriTech: a Relaxation Oscillator for Stem Impedance Monitoring
Wiring area optimization in floorplan-aware hierarchical power grids
Lossless Video Compression with Residual Image prediction and Coding (RIPC)
The first ever real bistable memristor
An integrated circuit chaotic oscillator and its application for high speed random bit generation
Jitter model of direct digital synthesis clock generators
A bio-physically inspired silicon neuron
One-Reflection Path Assisted Fingerprint Localization Method with Single Base Station under 6G Indoor Environment
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers
On the Time-frequency Analysis of Trunk Muscles During Sudden Release of Load
Reversible Data Hiding using Histogram-based Difference Expansion
Complexity analysis of next-generation HEVC decoder
Motion Detection by Using Entropy Image and Adaptive State-Labeling Technique
Learning and recalling of phase pattern in coupled BVP oscillators
Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes
Design of a Calorimetric Flow Rate Sensor for On-Body Sweat Monitoring
ALOHA CMOS imager
Passive approximation of tabulated frequency-data by Fourier expansion method
An efficient blind fine synchronization scheme for SCBT systems
Hardware implementation of the depth first search bit stream SPIHT system
An Iterative Reweighted Minimax Algorithm for the Design of FRM-based Two-channel QMF Banks
A Fast Parallel Algorithm for Slicing Floorplans
Mode refinement algorithm for H.264 intra frame requantization
Low-voltage Low-power Amplifiers
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores
Frequency offset compensation for OFDM receiver using rotating concyclic antenna
RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC
Chaotic sequences in ACO algorithms
A Same-Channel Full-Duplex Receiver Using Direct RF Sampling
Accelerating Hyperdimensional Computing with Vector Machines
Data hiding in inter and intra prediction modes of H.264/AVC
QoS-driven scheduling for multimedia applications
Map-reduce inspired loop parallelization on CGRA
Explicit delay metric for interconnect optimization
A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees
Approximation for Run-time Power Management
Direct-digital synthesis using delta-sigma modulated signals
Synchronization Properties in Networks of Hindmarsh-Rose Neurons and their PWL Approximations with Linear Symmetric Coupling
Controller redesign based clock and register power minimization
A convex optimization approach to reducing peak-to-average-power ratio in OFDM
An improvement of FFT-based numerical inversion of two-dimensional Laplace transforms by means of ϵ-algorithm
A quantitative evaluation of C-based synthesis on heterogeneous embedded systems design
Design of Class-Φ3 Power Oscillator
An Approach to the Device-Circuit Co-Design of HyperFET Circuits
Optimization of power consumption for an ARM7-based multimedia handheld device
No-reference image quality assessment using shearlet transform and stacked autoencoders
Performance improvement of autocorrelation detector used in UWB impulse radio
Live Demonstration: Designing CT BP ΣΔ Modulators with www.sigma-delta.de
A hybrid phase-locked loop for CDR Applications
A floating-gate pFET based CMOS programmable analog memory cell array
An Energy-Efficient YOLO Accelerator Optimizing Filter Switching Activity
A piloted notch time-frequency information based variable step-size algorithm
Mitigating Blackout Risk in Power Electronics Penetrated Power Systems through Metrics-Driven Inverter-Based Generator Placement
Low-Power FIR Digital Filter Architectures
An all-subthreshold, 0.75V supply, 2ppm/°C, CMOS Voltage Reference
The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits
Offset compensation in flash ADCs using floating-gate circuits
Stateful logic pipeline architecture
Patch-based salient region detection using statistical modeling in the non-subsampled contourlet domain
Analog continuous-time recurrent decision circuit with high signal-voltage symmetry and delay-time equality
Digital differentiators for narrow band applications in the lower to midband range
Application of entropy-constrained RVQ to coding image subbands
Vertex-based adaptive synchronization of complex networks
Kernel PCA Regression for Missing Data Estimation in DNA Microarray Analysis
A Pipelined Architecture Design for Trilateral Noise Filtering
A Fully Integrated LDO Using Synchronous VTC and Asynchronous Step Detection Recovery for Under-1 V Supply Voltage Application
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning
Analysis of the averaging technique in flash ADCs
Self-calibrating networks-on-chip
An area-efficient systolic division circuit over GF(2 m ) for secure communication
Control Strategy for Efficient Utilisation of Regenerative Power through Optimal Load Distribution in Hybrid Energy Storage System
A consistent Steiglitz-McBride algorithm
An adaptive circuits concept to address mismatch in analog circuits
Quantization-based image steganography without data hiding position memorization
CMOS Optoelectronic Lock-in Amplifier with Semi-Digital Automatic Phase Alignment
ZSCIL: Zero-Shot Class Incremental Learning Method for Signal Recognition
Design of IIR Variable Fractional Delay Digital Filters
A tunable triode-MOSFET transconductor and its application to gm-C filters
A 250 kHz Resistive Frequency-Locked On-Chip Oscillator with 24.7 ppm/°C Temperature Stability and 2.73 ppm Long-Term Stability
A 1.5 GHz high-Q receiver based on current reuse
Bipolar LNA design at different operating frequencies
The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis
A 6.78MHz Regulating Rectifier With Constant On-Time Control for High Resolution and Ultra-Fast Transient Response
Low-power, low-mismatch, highly-dense array of VLSI Mihalas-Niebur neurons
A simple nonautonomous chaotic circuit with a periodic pulse-train input
Design of low complexity programmable FIR filters using multiplexers array optimization
Modeling OpAmp-Induced Harmonic Distorition for Switched-Capacitor Sigma-Delta Modulator Design
Spike-based learning with a generalized integrate and fire silicon neuron
Power/Area Trade-Offs in Low-Power/Low-Area Unary-R-2R CMOS Digital-to-Analog Converters
Power optimization of neural frontend interfaces
Background Inhibition for Drift Compensation using Neuromorphic ISFET Arrays
A 1.8 V CMOS linear transconductor and its application to continuous-time filters
A high-speed blind DFE equalizer using an error feedback filter for QAM modems
Transformer-Based Ultra-Wide Band 43 GHz VCO in 28 nm CMOS for FMCW Radar System
Impact of active areas on electrical characteristics of TiO2 based solid-state memristors
Grouped-moduli residue number systems for fast signal processing
A parallel computation network for the maximm clique problem
A 6-µW AC-Coupled, Two-Step Incremental ∆Σ ADC for High-Density Neural Recording
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits
Statistical analysis of power spectra of signals governed by Markov chains
A Computational Model of the Relationship between Musical Rhythm and Heart Rhythm
Directly Obtaining Matching Points without Keypoints for Image Stitching
A Robust Data Compression Engine Dedicated For FMCW Radar RDM
Low-noise, low-distortion Gilbert current gain-cell and Gilbert cell transconductor
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker
Effect of MOSFET gate-to-drain parasitic capacitance on class-E power amplifier
LLAD: A Low-Latency Active Detection Method for High-Frequency Periodic GPIO Signals in Linux
Given-Rotation-Based Generalized Eigenvalue Decomposition Processor for MU-MIMO Precoding
A modified method for codebook design with neural network in VQ sed image compression
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands
Low-power implantable microsystem intended to multichannel cortical recording
Low-complexity and high quality frame-skipping transcoder
Instantaneous Capacitance Matching based Current Response Algorithm for EM Reliability Analysis
Modified Parabolic Synthesis for Hardware-Oriented Approximation of Unary Functions
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies
Robust adaptive channel estimation of OFDM systems in time-varying narrowband interference
A Novel Architecture for Reducing the Sensitivity of Multibit Sigma-Delta ADCs To DAC Nonlinearity
A 1.5 bit 5 th order CT/DT delta sigma class D amplifier with power efficiency improvement
On dynamic behavior of full range CNNs
Decimation filters for high-speed delta-sigma modulators with passband constraints: General versus CIC-based FIR filters
Application of a multiresolution optical-flow-based method for motion estimation to video coding
CMOS APS imager employing 3.3 V 12 bit 6.3 MS/s pipelined ADC
Novel interconnect infrastructures for massive multicore chips - an overview
A Mixed-Signal Successive Approximation Architecture for Energy-Efficient Fixed-Point Arithmetic in 16nm FinFET
Current Overshoots and Undershoots in Electrical Stimulation: A Circuit-level Perspective of the Origin and Solutions
A Switched-Current Bandpass Delta-Sigma Modulator
A 100-channel hermetically sealed implantable device for wireless neurosensing applications
Efficient inductance calculation for long and medium length rectangular interconnects in VLSI circuits
Wavelet denoising for highly noisy source separation
2-D Digital Filter Architectures without Global Broadcast and Some Symmetry Applications
Bearing angle estimation for sonar micro-array using analog VLSI spatiotemporal processing
High-Throughput Starch Content Estimation using RF Return Loss: Theory, Analysis and Test Instrument Design
An Automated Approach to Accelerate DNNs on Edge Devices
Image co-segmentation via active contours
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management
Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs
Opportunities for Machine Learning in Electronic Design Automation
Design automation of transistor networks, a new challenge
STATE: A Test Structure for Rapid Prediction of Resistive RAM Electrical Parameter Variability
Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs
A Low-Cost Flexible Pipe Sheath for Multi-Parameter Monitoring of Water Distribution
Families of binary coefficient biorthogonal wavelet filters
Transformer feedback based CMOS amplifiers
A computationally efficient second order adaptive lattice filter
VLSI Design of Tree-Based Inference for Low-Power Learning Applications
Modeling discrete event system with distributions using SystemVerilog
A Light-weight and Tamper-resistant AES Implementation by FPGAs
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC
Routing a Multi-Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles
Flow-based computing on nanoscale crossbars: Design and implementation of full adders
Substrate noise modeling with dedicated CAD framework for smart power ICs
Live demonstrator: Challenging the Bio-inspired Artificial Pancreas with a mixed-meal model library
Energy efficient AC computing methodology for wirelessly powered IoT devices
Comparison of the image rejection between the passive and the Gilbert mixer
Feature difference analysis in video authentication system
An adaptive algorithm for narrow-band interference rejection in DSSS systems
A 0.35µm 1.25V piezo-resistance digital ROIC for liquid dispensing MEMS
Empirical Study on the Impact of Few-Cost Proxies
The Photoacoustic Quality-Enhancement Neural Network Processor with the Scalable and End-to-End Architecture by Improving the Sparsity Level
Self-organizing neural grove: effective multiple classifier system with pruned self-generating neural trees
Efficient Camera Control using 2D Visual Information for Unmanned Aerial Vehicle-based Cinematography
Associative search using pseudo-analog memristors
A Tree-structured Non-uniform Filter Bank for Multi-standard Wireless Receivers
A new technique for design CMOS LNA for multi-standard receivers
VLSI Neural Network Implementation of a Hippocampal Model
A Currency Arbitrage Machine Based on the Simulated Bifurcation Algorithm for Ultrafast Detection of Optimal Opportunity
Full system for translational studies of personalized medicine with free-moving mice
A 0.01%THD, 70dB PSRR Single Ended Class D using Variable Hysteresis Control for Headphone Amplifiers
High-frequency Systolic Broadband Beamforming using Polyphase 3D IIR Frequency-planar Digital Filters with Interleaved A/D Sampling
Design of Mth-band FIR filters based on generalized polyphase structure
Mixed-domain receiver architecture for white space software-defined radio scenarios
Lossless Image Compression using Valley Transform
Parallel AIG Refactoring via Conflict Breaking
Adaptive Local Reconstruction for Geometry-based Point Cloud Compression
Scalable Gate-Level Models for Power and Timing Analysis
Design and efficient implementation of high-speed narrow-band recursive digital filters using single filter frequency masking techniques
Design Considerations and Experimental Verification of a 10.5mW 1GS/s Hybrid ADC for Portable Wireless Devices
Two-Channel 1D and 2D Biorthonormal Filter Banks with Causal Stable IIR and Linear Phase FIR Filters
AES Sbox Acceleration Schemes for Low-Cost SoCs
A 32-by-32 CMOS microelectrode array for capacitive biosensing and impedance spectroscopy
Compressive sampling hardware reconstruction
A novel channel identification method for fast wireless communication systems with transmitter and receiver diversity
A Realization Method of an ARMAX Lattice Filter
Filterbank-based fast parallel algorithms for 2-D DHT-based real-valued discrete Gabor transform
Feasible Region Approximation Using Convex Polytopes
Mth-band linear-phase FIR filter interpolators and decimators utilizing the Farrow structure
Adaptive refreshing and read voltage control scheme for FeDRAM
Partial-spectrum-reconstruction digital filter banks
A new board for CNN stereo vision algorithm
Toward complete analog fault coverage with minimal observation points using a fault propagation graph
Texture image retrieval using complex directional filter bank
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture
A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme
A 2.43 mW Multi-frequency Electrical Impedance Tomography ASIC with Dual-Mode Impedance Readout
Closed-form design of fractional order differentiator using discrete cosine transform
Improved generalized-proportionate stepsize LMS algorithms and performance analysis
A low phase noise 2.0 V 900 MHz CMOS voltage controlled ring oscillator
A high resolution and high accuracy R-2R DAC based on ordered element matching
Gate-level simulation of CMOS circuits using the IDDM model
Image Processing by Cellular Memcomputing Structures
An FPGA design framework for large-scale spiking neural networks
A Parallel Acceleration Strategy for Large Aperture Radar Imaging and its Hardware Implementation
Fast mode decision and motion estimation for H.264 (FMDME)
Power Supply Noise in Bang-Bang Control Class D Amplifier
Double locally active memristor-based inductor-free chaotic circuit
Solving Vertex Cover via Ising Model on a Neuromorphic Processor
Optimize FPGA-Based Neural Network Accelerator with Bit-Shift Quantization
High-voltage tolerant circuit design for fully CMOS compatible multiple-time programmable memories
A variant of a radix-10 combinational multiplier
CMOS single-to-differential current amplifier
Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies
A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory
Dynamic Output Resistance Optimization for Duty-cycle Control in Hybrid Capacitive LED Drivers
Tool integrated electromagnetic pulse induction technology to locate buried utilities
An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error Constraint
A fully symmetrical sense amplifier for non-volatile memories
Low-latency hardware architecture for cipher-based message authentication code
Mind the Gap: Bridging Verilog and Computer Architecture
Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002
Exact Design of High-frequency SC Circuits with Low-gain Op Amps
Design considerations and recent advances in CMOS-based microsystems for point-of-care clinical diagnostics
Upper and lower bounds on FSM switching activity