yusuke1997/dblp-id-title huggingface dataset:
On logic synthesis of conventionally hard to synthesize circuits using genetic programming
Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach
Stochastic Computing Architectures for Lightweight LSTM Neural Networks
AdequateDL: Approximating Deep Learning Accelerators
Efficient mapping of nondeterministic automata to FPGA for fast regular expression matching
Verifying Bio-Electronic Systems
Rapid Prototyping of NoC Architectures from a SystemC Specification
Mapping abstract and concrete hardware models for design understanding
Yield-oriented energy and performance model for subthreshold circuits with Vth variations
On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks
On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space Applications: Embedded Tutorial
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults
Embedded Tutorial - RRAMs: How to Guarantee Their Quality Test after Manufacturing?
On the on-line functional test of the Reorder Buffer memory in superscalar processors
Relocation of reconfigurable modules on Xilinx FPGA
CMOS Differential Amplifier as a Physically Unclonable Function
Automatic Generation of Circuits for Approximate String Matching
Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm
Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs
Conversion and interfacing techniques for asynchronous circuits
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
Accuracy Enhancement of Resistor-String Digital-to-Analog Converters through Averaging Dynamic Element Matching
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
Diagnosis of Realistic Defects Based on the X-Fault Model
PMS2UPF: An automated transition from ESL to RTL power-intent specification
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
High performance adaptive sensor interface design through model based estimation of analog non-idealities
A new method for correcting time and soft errors in combinational circuits
An Innovative Data Mining Technique for Automatic Anomaly Detection in Physical Unclonable Functions
Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs
Behavioral model of TRNG based on oscillator rings implemented in FPGA
An intra-cell defect grading tool
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins
A Mixed Approach for Unified Logic Diagnosis
Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology
Bits, Flips and RISCs
Cross-layer resilient system design
Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011
Efficient VHDL implementation of symbol synchronization for software radio based on FPGA
On the role of the power supply as an entry for common cause faults - An experimental analysis
Synthesis and Optimization of Switching Nanoarrays
Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables
Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts
Automatic synthesis of small AdaBoost classifier in FPGA
Digital-driven formal analog verification for asynchronously feed-backed circuitries
Determining MOSFET Parameters in Moderate Inversion
Decoupling capacitance study and optimization method for high-performance VLSIs
Embedded Self Repair by Transistor and Gate Level Reconfiguration
FPGA architectures of the quantization and the dequantization for video encoders
High-Throughput Approximate Multiplication Models in PyTorch
Introduction to approximate computing: Embedded tutorial
Online testing of many-core systems in the Dark Silicon era
On the Functional Test of Special Function Units in GPUs
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm
High speed FPGA implementation of hough transform for real-time applications
Implementation of the ADELITE Microcontroller for Biomedical Applications
Development of On-Chip Calibration for Hybrid Pixel Detectors
A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology
Evaluation of transition untestable faults using a multi-cycle capture test generation method
Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals
Validation and optimization of TMR protections for circuits in radiation environments
D&T Presenter - electronic interactive system for design and test education
Power Dissipation in Basic Global Clock Distribution Networks
Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm
Implementation of Dynamic SISD-SIMD Integer Dividers
Customer return detection with features selection
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms
An Autonomous Clock Frequency Supervision Circuit
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs
Design of Time-to-Digital Converter Output Interface
Self-repairing and tuning reconfigurable electronics for space
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing
Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnects
Transition Faults Testing Based on Functional Delay Tests
Efficient link-level error resilience in 3D NoCs
Structure-preserving modeling of safety-critical combinational circuits
SoCECT: System on Chip Embedded Core Test
Advanced embedded memory testing: Reducing the defect per million level at lower test cost
Probabilistic Testability Analysis and DFT Methods at RTL
Dependability Computation for Fault Tolerant Reconfigurable Duplex System
Energy-aware scheduling of FIR filter structures using a timed automata model
On the mitigation of SET broadening effects in integrated circuits
An analysis of the operation and SET robustness of a CMOS pulse stretching circuit
High side power MOSFET switch driver for a low-power AC/DC converter
Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance
Novel metrics for Analog Mixed-Signal coverage
Advanced rectifier and driver for analog VU meter
Embedded microcontroller system for PilsenCUBE picosatellite
A Low-Cost Combinational Approximate Multiplier
Scheduling of Distributed Applications in HHPCaaS Clouds for Internet of Things
Reliability-Aware Multi-Vth Domain Digital Design Assessment
Modeling timing constraints for automatic generation of embedded test instruments
Fault-Aware Performance Assessment Approach for Embedded Networks
A Comprehensive Analysis of Transient Errors on Systolic Arrays
FPGA Implementation of Strongly Parallel Histogram Equalization
Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification
A double-path intra prediction architecture for the hardware H.265/HEVC encoder
22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs
Efficient triggering of Trojan hardware logic
Using a CISC microcontroller to test embedded memories
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions
Low-cost, customized and flexible SRAM MBIST engine
17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014
Noise determination of a current conveyor in an inverting voltage amplifier configuration
An efficient fault simulation technique for transition faults in non-scan sequential circuits
On the robustness of memristor based logic gates
Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee Application
Incremental SAT Instance Generation for SAT-based ATPG
Fast just-in-time translated simulator for ASIP design
Studying DAC capacitor-array degradation in charge-redistribution SAR ADCs
Hardware and control design of a ball balancing robot
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization
Design methodology for fault tolerant ASICs
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection
A gigabit fully integrated plastic optical fiber receiver for a RC-LED source
Intelligent IGBT driver concept for three-phase electric drive diagnostics
Packet header analysis and field extraction for multigigabit networks
Reduction of complex safety models based on Markov chains
Hybrid on-line self-test architecture for computational units on embedded processor cores
Contention-avoiding custom topology generation for network-on-chip
Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography
On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors
Test pattern decompression in parallel scan chain architecture
Test scheme for switched-capacitor circuits by digital analyses
Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications
Low voltage precharge CMOS logic
Efficient automated speedpath debugging
Lower bounds of the size of Shared Structurally Synthesized BDDs
Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA
Verification approach based on emulation technology
Contradiction Analysis for Inconsistent Formal Models
Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007
Constraint-based test pattern generation at the Register-Transfer Level
The Advanced Circuitry of the Precision Super Capacitances Based on the Classical and Differential Difference Operational Amplifiers
Computation of a nonlinear squashing function in digital neural networks
Test platform for fault tolerant systems design properties verification
Gain reduction by gate-leakage currents in regulated cascodes
Design of a single layer programmable Structured ASIC library
Extended Fault Detection Techniques for Systems-on-Chip
Measuring metastability using a time-to-digital converter
Optimization concepts for self-healing asynchronous circuits
Measurement of power supply noise tolerance of self-timed processor
On Minimizing RTOS Aperiodic Tasks Server Energy Consumption
Instruction set extensions for multi-threading in LEON3
Influence of parasitic memory effect on single-cell faults in SRAMs
The Guiding Light for Chip Testing
Impedance calculation based method for AC fault analysis of mixed-signal circuits
CIVA: Custom instruction vulnerability analysis framework
Are XORs in logic synthesis really necessary?
Modeling and analysis of cracked through silicon via (TSV) interconnections
Design and Simulation of Runtime Reconfigurable Systems
Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes
Test and configuration architecture of a sub-THz CMOS detector array
How to reduce size of a signature-based diagnostic dictionary used for testing of connections
A Survey on Automatic Assertion Miners
A wireless ECG sensor node based on Huffman data encoder
Round-level concurrent error detection applied to Advanced Encryption Standard
DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance
Towards Generation of a Programmable Power Management Unit at the Electronic System Level
0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area
Combining on-line fault detection and logic self repair
A Flexible Technique for the Automatic Design of Approximate String Matching Architectures
Measurement point selection for in-operation wear-out monitoring
On test time reduction using pattern overlapping, broadcasting and on-chip decompression
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures
Testing and design-for-testability solutions for 3D integrated circuits
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling
Resistive switching and synaptic behavior in zirconium doped thin film metal-oxide-metal devices
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Numerical method for DC fault analysis simplification and simulation time reduction
Automated debugging from pre-silicon to post-silicon
Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5V
BSIM4 to PSP Model Conversion for Passive Mixer IM3 Simulation
On the feasibility of combining on-line-test and self repair for logic circuits
Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation
An analog perspective on device reliability in 32nm high-κ metal gate technology
Analysis and optimization of ring oscillator using sub-feedback scheme
A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging
A static analysis approach to data race detection in SystemC designs
Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology
Synthesis of Self-Adaptable Software for Multicore Embedded Systems
System design for enhanced forward-engineering possibilities of safety critical embedded systems
Lazy Man's Resynthesis For Glitching-Aware Power Minimization
An efficient physical design of fully-testable BDD-based circuits
A New 6-bit Flash A/D Converter Using Novel Two-Step Structure
Test Considerations about the Structured ASIC Paradigm
A low voltage sigma delta modulator for temperature sensor
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space
Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems
Optical receivers in 0.35 μm BiCMOS for heterogeneous 3D integration
Selective Hardening of Critical Neurons in Deep Neural Networks
Fault tolerant CAN bus control system implemented into FPGA
Composing data-driven circuits using handshake in the clock-synchronous domain
A synthesis method to propagate false path information from RTL to gate level
Quality assurance in memory built-in self-test tools
Versatile sub-bandgap reference IP core
A comprehensive approach for soft error tolerant Four State Logic
Decreasing test time by scan chain reorganization
The design of dependable flexible multi-sensory System-on-Chips for security applications
Fault diagnosis of crosstalk induced glitches and delay faults
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors
Asynchronous design, Quo Vadis?
A Digital Delay Model Supporting Large Adversarial Delay Variations
Memory Based Analogue Signal Generation Implementation Issues for BIST
Automatically connecting hardware blocks via light-weight matching techniques
A rule-based approach for minimizing power dissipation of digital circuits
An efficient hardware architecture for inter-prediction in H.264/AVC encoders
Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures
Enhanced LEON3 core for superscalar processing
Novel model calibration method based on differential evolution used for SCR model fitting
BioSoC: Highly integrated System-on-Chip for health monitoring
MBIST for LEON3 processor core cache
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology
Decomposition of multi-output logic function in Reed-Muller spectral domain
Optimizing Packet Classification on FPGA
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III
Contribution to Automated Generating of System Power-Management Specification
On using a SPICE-like TSTAC™ eFlash model for design and test
Effective Screening of Automotive SoCs by Combining Burn-In and System Level Test
CMOS variable-gain amplifier for low-frequency applications
Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic
Foreword to the 16th IEEE DDECS Symposium
Statistical analysis of 6T SRAM data retention voltage under process variation
Reducing Output Response Aliasing Using Boolean Optimization Techniques
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories
On the test of single via related defects in digital VLSI designs
APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor
A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technology
Hardware efficient design of Variable Length FFT Processor
Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits
Modeling and Simulation of Thermal Faults in Batteries for Enhanced Safety
The Quest for Test: Will Redundancy Cover All?
Auto-calibration techniques in built-in jitter measurement circuit
Effective mars rover platform design with Hardware / Software co-design
Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing
Low-complexity integrated circuit aging monitor
PE-ICE: Parallelized Encryption and Integrity Checking Engine
Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?
Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC
Hardware-Software Co-Visualization: Developing systems in the holodeck
Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOS
Counterfeit Chip Detection using Scattering Parameter Analysis
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques
Sensor Powering with Integrated MOS Compatible Solar Cell Array
Data compression in hardware - The Burrows-Wheeler approach
Co-design of CML IO and Interposer channel for low area and power signaling
On SAT-Based Model Checking of Speed-Independent Circuits
Interconnect Faults Identification and Localization Using Modified Ring LFSRs
A Novel Compact Dual-Band Bandpass Waveguide Filter
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio
Novel Dummy Rounds Schemes as a DPA Countermeasure in PRESENT Cipher
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006
Software-based self-repair of statically scheduled superscalar data paths
An SOC platform for ADC test and measurement
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology
Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology
Software defined radio - design and implementation of complete platform
Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers
Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches
LC-VCO design automation tool for nanometer CMOS technology
A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique
Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario
On-Chip Current Sensing Approaches for DC-DC Converters
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors
Concurrent Testing of Digital Circuits for Advanced Fault Models
High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories
An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfiguration
Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems
Comparative Study of Safety and Security-Protected AES Designs
Comparing proton and neutron induced SEU cross section in FPGA
Testing analog electronic circuits using N-terminal network
Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC
Asynchronous circuit design: From basics to practical applications
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008
Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA
Self Vth-Compensating CMOS On-Chip Rectifier for Inductively Powered Implantable Medical Devices
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Multiple Errors Detection Technique for RAM
Lightweight Multi-threaded Network Processor Core in FPGA
Architecture for Highly Reliable Embedded Flash Memories
Implementation of FPGA-based Accelerator for Deep Neural Networks
On-line test of embedded systems: Which role for functional test?
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories
A study of path delay variations in the presence of uncorrelated power and ground supply noise
Synthesis of approximate circuits for LUT-based FPGAs
Area-speed efficient modular architecture for GF(2 m ) multipliers dedicated for cryptographic applications
Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs
Design-for-Diagnosis Architecture for Power Switches
A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks
Cycle-accurate software modeling for RTL verification of embedded systems
Automatically Generated Nonlinear Analog Circuit Models Enclosing Variations with Intervals and Affine Forms for Reachability Analysis
Parallel Memory Architecture for Arbitrary Stride Accesses
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017
Implementation of DBFN processor for Synthetic Aperture Radar application
The impact of EFSM composition on functional ATPG
Synthesis of Petri nets into FPGA with operation flexible memories
Mitigating DoS Attacks on CAN: A Priority-Raise Approach and Its Timing Analysis
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
NoGap CL : A flexible common language for processor hardware description
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects
On the Pole-Placement Technique for the Design of a DC-DC Buck Converter Discrete PID Control
Hardware Obfuscation of Digital FIR Filters
LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing
Lightweight cipher resistivity against brute-force attack: Analysis of PRESENT
Mismatch effects and their correction in large area ASICs
Code Coverage Analysis using High-Level Decision Diagrams
Current sensing completion detection in dual-rail asynchronous systems
High-level modeling and testing of multiple control faults in digital systems
Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability