yusuke1997/dblp-id-title huggingface dataset:
Implementation of time-multiplexed sparse periodic FIR filters for FRM on FPGAs
The Speech Recogniton System based on Structure Equivalent Fuzzy RBF Neural Network
TinyML for EEG Decoding on Microcontrollers
A Novel Near Lossless Image Compression Method
Compact current input oversampling modulator design for a scalable high frame rate focal plane arrays
The time derivative neuron
An Ultralow-Power Capacitive Array-Based IR-UWB Transmitter Using Cross-Coupled Oscillator
A 0.12V Fully Integrated Charge Pump with Gate Voltage Optimization for Energy Harvesting Applications
A Robustness Approach to Envelope-Constrained Filtering
Evaluation of detailed modeling of the LP residual in statistical speech synthesis
A monitoring circuit for NBTI degradation at 65nm technology node
Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology
Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors
A global wire planning scheme for Network-on-Chip
Gain and bandwidth boosting techniques for high-speed operational amplifiers
A robust watermarking method based on wavelet and Zernike transform
A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration
Robust three-state PFD architecture with enhanced frequency acquisition capabilities
Low-voltage, low-power and high gain CMOS operational transconductance amplifier
Fractional-Order Model of a Commercial Ear Simulator
Sliding-mode control design of parallel-connected switching converters for modular transformerless DC-AC step-up conversion
Ray-space360: An extension of ray-space for omnidirectional free viewpoint
Machine Learning for X-ray and CT-based COVID-19 Diagnosis
IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
Design of Ultra-Wideband On-Chip Millimter-Wave Bandpass Filter in 0.13-μm (Bi)-CMOS Technology
A 650mW Filterless Class-D Audio Power Amplifier for Mobile Applications in 65-nm Technology
Dual video watermarking for CCL protection and manipulation detection
Fast algorithms for power grid analysis based on effective resistance
A 4th-order analog continuous-time filter designed using standard cells and automatic digital logic design tools
Flexible printed organic photovoltaic antennas for the Internet of Things
Propagation and Reflection of Phase Differences on a Lattice of Coupled Oscillators
Non-causal filters in multipath channel shaping
Robust random chip ID generation with wide-aperture clocked comparators and maximum likelihood detection
A bandpass sigma-delta modulator employing micro-mechanical resonator
Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip
OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links
New Recursive Adaptive Beamforming Algorithms for Uniform Concentric Spherical Arrays with Frequency Invariant Characteristics
A 60-dB Gain OTA operating at 0.25-V power supply in 130-nm digital CMOS process
Reconstruction of neural action potentials using signal dependent sparse representations
Memory Analysis for H.264/AVC Scalable Extension Encoder
Local polynomial modelling of time-varying autoregressive processes and its application to the analysis of event-related electroencephalogram
Efficient Variable Ordering Heuristics for Shared ROBDD
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process
A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors
Emulation of Mycelium's Electrical Activity with Reconfigurable Memristive Spiking Grid
Low Power High Speed Dynamic Comparator
Adaptive low-power bus encoding based on weighted code mapping
A Single-Aperture, Single-Pixel Reader for Optical Frequency Identification
A low-complexity intestinal lumen detection method for wireless endoscopy images
Unsolvable power flow - restoring solutions of the electric power network equations
Computation of Filters Derived from Lowpass Prototypes through Rational Transformations
A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse
Two fast RSA implementations using high-radix montgomery algorithm
Log-Domain Filters Based on LC Ladder Synthesis
Subspace estimation by hierarchical neural PCA: analog/digital implementation constraints
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end
Performance optimization of multiple memory architectures for DSP
An Energy Autonomous and Battery-Free Plant's Electrical Impedance Measurement System
An FPGA-Based High-Throughput Dataflow Accelerator for Lightweight Neural Network
A region-based object tracking scheme using Adaboost-based feature selection
Distributed anti-flocking control for mobile surveillance systems
A CMOS imager with PFM/PWM based analog-to-digital converter
Live Demonstration: A Mobile Diagnostic System for Rapid Detection and Tracking of Infectious Diseases
A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process
Tool-set for NoC-based MPSoC debugging - A protocol view perspective
A time-series processor for sonar mapping and novelty detection
Highly scalable neuromorphic hardware with 1-bit stochastic nano-synapses
A Compressed Sensing Integrate-and-Fire Neuron Concept for Massively Parallel Recordings
An Area-Efficient VCO-Based Hall Sensor Readout System for Autofocus Applications
A Microwave OTA Using a Feedforward-Regulated Cascode Topology
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits
Cancelling the memory effects in RF power amplifiers
High-Performance IIR QMF Banks for Speech Subband Coding
An efficient regular matrix inversion circuit architecture for MIMO processing
Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces
Fingerprint feature matching using CNNs
Systematic test program generation for SoC testing using embedded processor
Design of Network Security Experiment Teaching System Based on Honeypot Technology
ReShare: A Resource-Efficient Weight Pattern Sharing Scheme for Memristive DNN Accelerators
Graph-Based Power Network Routing for Board-Level High Performance Systems
Fischlar-TRECVid-2004: combined text- and image-based searching of video archives
A linearized voltage-controlled oscillator for dual-path phase-locked loops
A new motion and disparity vector prediction technique for H.264 based stereoscopic video coding
A robust FIR filter with in situ error detection
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration
Identifications of Hasler's classes of linear resistive circuit structures
New Approach to LUT Implementation and Accumulation for Memory-based Multiplication
The Generalized Bilinear System: a Class of Nonlinear Discrete Systems
Multi-layer constrained via minimization with conjugate conflict continuation graphs
Multichannel SVD-based image de-noising
A rectifier/AC shunt regulator combo circuit with inherent AM demodulation front-end for wireless powered implants
An adaptive search algorithm based on block classification for fast block motion estimation
Skew symmetry detection using the Walsh spectral coefficients
Accelerated frame-free time-encoded multi-step imaging
A 32×32 single photon avalanche diode imager with delay-insensitive address-event readout
A subspace method for channel estimation of multi-user multi-antenna OFDM system
A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique
An error concealment scheme for entire frame losses based on H.264/AVC
Design and implementation of an ML decoder for tail-biting convolutional codes
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications
Analysis of subsystem integration in aircraft power distribution systems
Power amplifier ACPR simulation using standard harmonic balance tools
Statistical modelling of the MPEG-4 FlexMux
Immitance and telepolation-based procedures to test stability of continuous-discrete bivariate polynomials
Low-Complexity Intra Prediction for Screen Content Coding by Convolutional Neural Network
Fast encoding method for vector quantization based on sorting elements of codewords to adaptively constructing subvectors
Investigation of a least squares method for high order filter synthesis
A Brief Overview of the Complex Biological and Engineering Networks
Cross-layer resilient system design flow
A Wide Tuning Range CMOS Oscillator for an Optoelectronic Retinal Prosthesis System
Systematic Synthesis Procedures for High-Dimensional Chaotic Systems: Methods and Applications
Desynchronize a legacy floating-point adder with operand-dependant delay elements
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator
A formulation for quick evaluation and optimization of digital CMOS circuits
Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm
Optimization of ETSI DSR frontend software on a high-efficient audio DSP
A CMOS Front-End for a Lossy Image Compression Sensor
Functional Testing and Constrained Synthesis of Sequential Architectures
Unsupervised action classification using space-time link analysis
Event detection using multimodal feature analysis
On the effect of time delays in negative feedback amplifiers
A dual-band RF front-end for WCDMA and GPS applications
Error robust video transmission over wireless IP networks with multiuser detection
Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network
Fully Tunable GaAs MESFET OTA-C Integrator Suitable for High-precisio-n Continuous-time Filtering
Crosstalk noise estimation using effective coupling capacitance
Design and analysis of a distributed regenerative frequency divider using distributed mixer
Live Demonstration: Image Segmentation on the FPGA-based Pre-calculating Ising Memory
A Tunable FDD Duplexer using Electrical Balance with N-Path Filters
A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM
Area efficient, high speed parallel counter circuits using charge recycling threshold logic
Fully on-chip temperature, process, and voltage sensors
A self-sensing tristate pad driver for control signals of multiple bus controllers
An adaptive control of the request access bandwidth of the DQRUMA for providing the QoS in an OFDM-based W-ATM system
Investigation of Multi-Layer Perceptron with propagation of glial pulse to two directions
Analysis and synthesis of passive coupled-switched-capacitor-resonator-based RF filters
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit
RF circuit synthesis using particle swarm optimization
A 6 th order, 700-1100 MHz, 3.6 Gb/s RF bandpass ΣΔ ADC with two-tone SFDR 67.2 dB in 65nm CMOS
Sigma delta modulators using semi-uniform quantizers
Simulating Nonuniform Lossy Lines with Frequency Dependent Parameters by the Method of Characteristics
Mixed-signal real-time adaptive blind source separation
Algorithms for Flexible Equalisation in Wireless Communications
Modified current-mode one-cycle control for linear-assisted DC/DC regulator
CMOS voltage-mode analog multiplier
In-material reservoir implementation of reservoir-based convolution
Producing Complex Networks Using Coupled Oscillatory Circuits with Evolutionary Connections
MEMS modules for life-on-a-chip
Further results on convergence of cooperative standard cellular neural networks
The swapping binary-window DAC switching technique for SAR ADCs
Graphical Specification Methods for Digital Telecommuniation ASICs
Multi-Agent Deep Reinforcement Learning Based Distributed Resource Allocation
On Frequency-Weighted l2-Sensitivity Analysis and Minimization of 2-D State-Space Digital Filters Subject to l2-Scaling Constraints
Research Experience as a Way to Improve Retention and Graduation Rates
Antisymmetries in the realization of Boolean functions
A novel approach for functional coverage measurement in HDL
Reconfigurable Radix-2 k ×3 Feedforward FFT Architectures
A beam tracking algorithm for space-time Rake receiver with a new beamformer
Low-voltage Bluetooth/ZigBee complex filter using current mirrors
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects
A routing technique using fuzzy sets theory
A Hysteresis Hyperchaos Generator Family
MLC STT-RAM design considering probabilistic and asymmetric MTJ switching
Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks
Reduce the complexity of frequency-response masking filter using multiplication free filter
Development of an Initial Value Input System for a Ring of Coupled Four Oscillators
Performance Analysis of an Adaptive Subspace Filter for Signal Enhancement
Extended division range 2/3 chain frequency divider with dynamic control word
A modular transconductance reduction technique for very low-frequency Gm-C filters
Low kickback noise techniques for CMOS latched comparators
Novel successive-approximation algorithms
An area efficient 64-bit square root carry-select adder for low power applications
CEPAGE: A toolbox for Central Pattern Generator analysis
A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques
A codesign synthesis from an MPEG-4 decoder dataflow description
Dominating tails in a tandem of queues with long range dependent arrival and service processes
The All-Minors VCCS Matrix Tree Theorem, Half-Resistors and Applications in Symbolic Simulation
Compact CMOS linear transconductor and four-quadrant analogue multiplier
Tradeoffs between wireless communication and computation in closed-loop implantable devices
Side information generation with constrained relaxation for distributed multi-view video coding
Simultaneous Wireless Power and Data Transfer: Overview and Application to Electric Vehicles
Hysteresis neural networks for solving traveling salesperson problems
Successive cancellation decoding of polar codes using stochastic computing
Packetized Pipelined Pillar Feature Net Accelerator for LiDAR 3D Object Detection
ZF-DFE transceiver for time-varying MIMO channels with channel-independent temporal precoder
Phase-Change Memory in Neural Network Layers with Measurements-based Device Models
Efficient allocation of power of two terms in FIR digital filter design using tabu search
A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data
Circuit design from minimized Haar wavelet series
Threshold-Free Interference Cancellation Method for Automotive FMCW Radar Systems
F-SEONS: a second-order frequency-domain algorithm for noisy convolutive source separation
Performance Analysis of Hopfield Neural Networks for DOA Estimation
Non-causal error control for wireless video streaming with noncoherent signaling
A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS
A Study on Introduction of PSD Model for Field Merged Signal and Its Analysis
Efficient Fast-SCAN Flip Decoder for Polar Codes
A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders
Standard Cell Layout Design and Placement Optimization for TFET-Based Circuits
A study on distribution network planning with considering customer's utilization of distributed generators
6G FR3 Band-limited Based DPD using Low-Resolution Σ∆ Feedback Receiver
Incremetal Spatio-Temporal Feature Extraction and Retrieval for Large Video Database
Slack-time aware routing in NoC systems
Novel instructions and their hardware architecture for video signal processing
Japanese character based printed source identification
A time-domain gradient-detection architecture for VLSI analog motion sensors
Mismatch compensation techniques using random data for time-interleaved A/D converters
Fast modular neural nets for face detection
A Novel Approach to the Maximum Peak Power Tracking under Partial Shading conditions
Entrenching Decision Trees in a Robust Molecular Circuit Element
An improved soft BCH decoder with one extra error compensation
Processing of Signals using Level-crossing Sampling
Residue arithmetic bases for reducing delay variation
An Attention Network With Self-Supervised Learning for Rheumatoid Arthritis Scoring
Generalized structure for designing odd-order variable fractional-delay filters
Dynamic charge restoration of floating gate subthreshold MOS translinear circuits
All-digital Time-Mode elliptic filters based on the operational simulation of LC ladders
SPICEInverse: Synthesis of an Accelerated Multiplexed Impedance Measurement Technique for Wearable Low-Power Electrochemical Systems
Meshing strategy of equivalent substrate schematic in SMART power IC
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range
A Self-Calibrating A/D Converter Using T-Model Neural Network
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing
Associative Positive Boolean Functions and their Maxium Stacking Vector Representations
The equivalent transmission-line approach to resonant tunneling problems described by the Kane model
A Fuzzy Neural Network based Adaptive Predictor with P-Controller Compensation for Lossless Compression of Images
A unified framework for least square and mean square based adaptive filtering algorithms
Design and implementation of low-power IIR digital filter systems
Fault collapsing with linear complexity in digital circuits
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder
Bayesian Inference Accelerator for Spiking Neural Networks
A high-speed pattern decoder in MPEG-4 padding block hardware accelerator
Systolic architectures for finite field inversion and division
An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects
A Super-Fast Deep Network for Moving Object Detection
Real-time adaptive signal processing using a dynamic reconfigurable systolic architecture in analog VLSI
A robust adaptive cross microphone array
A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack
Photoacoustic Microscopy Imaging from Acoustic Resolution to Optical Resolution Enhancement with Deep Learning
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation
Bootstrapping Circuit with IGZO TFTs for On-Chip Power Supply Generation
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations
Phase locked loop robustness improvement using non integer order loop filter
A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm 2
A nanopower CMOS bandgap reference with 30ppm/degree C from -30 degree C to 150 degree C
Hybrid A∗ Based Motion Planning for Autonomous Vehicles in Unstructured Environment
Variable ordering on multiway decision graphs
Variance-based digital logic for energy harvesting Internet-of-Things
A 22-bit 110ps time-interpolated Time-to-Digital Converter
A simple variable-width CMOS bump circuit
A Novel Stereo Matching Network for Underwater Scenes
Weighted Hybrid Fusion for Multimodal Biometric Recognition System
An Appraoch of Sequential-Like Parallel Algorithm in Boltzmann Machine
A 0.98 pJ/Cycle 3.7 ppm Long-Term Stability Frequency-Locked Oscillator with Switched-Capacitor and Switched-Resistor Techniques
Comparison of currents in differential log-domain filters with common-mode feedback
Live demonstration: Axon emulator for evaluation of nerve recording systems
An Attention-Based Network for Single Image HDR Reconstruction
An ultra-compact and efficient Li-ion battery charger circuit for biomedical applications
A low-power CMOS power amplifier for ultra wideband (UWB) applications
A UHF RFID reader transmitter with digital CMOS power amplifier
Understanding dynamic behavior of mm-wave CML divider with injection-locking concept
Bias free adaptive exponential notch filter with low constant delay
A 1-V PTAT current reference circuit with 0.05%/V current sensitivity to VDD
An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting
Deep Video Compression for P-frame in Sub-sampled Color Spaces
A highly accurate piezoelectric actuator driver IC for auto-focus in camera module of mobile phone
A new low cost and reconfigurable RSA crypto-processor
PMIL: A Topology Module to Improve MIL-based WSI Classification
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
A 600-pW, 34.6 ppm/°C, -50 °C to 130 °C CMOS Voltage Reference with Leakage-Based Temperature Compensation and Supply Rejection Enhancement Techniques
An Energy Harvesting System with Reconfigurable Piezoelectric Energy Harvester Array for IoT Applications
Wide-band CMOS low noise amplifier for applications in radio astronomy
A 0.12mm 2 K/Ka Band RX Front-end in 40-nm CMOS with Inductor-Less LO Generators
Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs
Identifying Task-Related Brain Functional States Via Cortical Networks
Live Demonstration: A Low-Cost Wireless Instrumentation Control System
Strongly consistent recursive regression estimation under depended observations
Frame loss error concealment for multiview video coding
A new algorithm for single residue digit error correction in Redundant Residue Number System
Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor
Dynamic trellis diagrams for optimized DSP code generation
Single chip tuner design for digital terrestrial television
An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation
Handheld fluorometer for detection of blue/green fluorescence
MTJ based Temperature-Adaptive VCO (TAVCO) for Compensating CP-PLL Frequency Drift
Spectral shaping by generalized transfer function design in frequency modulation Sigma-Delta synthesizers
New designs of frequency selective FIR digital filters
Theory and algorithms for RF sensitivity computation
A 13.2 mW 1.9 GHz Interpolative BAW-based VCO for Miniaturized RF Frequency Synthesis
An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices
Electronically programmable test points for on-chip analog/digital measurements
Live Demonstration: Dual-Sensor Measurement of Camptocormia Trunk Flexion
Capacitances in Compact 7-Parameter Model for Analog Design in Nanoscale Process
Analysis of HBT Vector Modulator Phase Shifters Based on Gilbert Cell for sub-THz Regimes
A configurable VLSI chip for DC motor control for compact, low-current robotic systems
Implementation of non-linear templates using a decomposition technique by a 0.5 μm CMOS CNN universal chip
MTVSM-CIM: A Magnified-TMR VC-SOT-MRAM Computing-in-Memory Macro for Edge AI
Switched-Current Multirate Filtering
A new substrate model and parameter extraction method for DNW RF MOSFETs
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator
Analysis of Bifurcation Points of Nonlinear Resistive Circuits by Curve Tracing Method
FIR MIMO decision feedback equalization for space-time block-coded transmission over multipath-fading channels
Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices
A Tunable Switched-Capacitor 2-Way Power Divider Based on N-Path Filters
A 25 Gb/s full-rate CDR circuit based on quadrature phase generation in data path
Impact of module design on the signal-isolation of mixed-signal RF applications
Topological symbolic simplification for analog design
Linear decoding algorithm obtained from nonlinear analysis of sigma-delta modulators
Evaluation on power reduction applying gated clock approaches
Compact bistable CNNs based on resonant tunneling diodes
A Star Pattern Recognition Technique Based on the Binary Pattern Formed from the FFT Coefficients