yusuke1997/dblp-id-title huggingface dataset:
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications
ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
Automated generation of battery aging models from datasheets
Formal Semantics of VHDL for Verification of Circuit Designs
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS
Design and Implementation of Scalable Low-Power Montgomery Multiplier
Improving FPGA Routing Architectures Using Architecture and CAD Interactions
An Arbitration Tree Adapted to Object Oriented Associative Memories
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique
VDMig: An Adaptive Virtual Disk Migration Scheme for Cloud Block Storage System
HEncode: A Highly Modularized and Efficient FPGA QC-LDPC Encoder using High Level Synthesis
VariPipe: Low-overhead variable-clock synchronous pipelines
The Magic of a Via-Configurable Regular Fabric
Security Evaluation of Quantum Circuit Split Compilation Under an Oracle-Guided Attack
Design and Evaluation of a PVT Variation-Resistant TRNG Circuit
Test generation in circuits constructed by input decomposition
Integrated optoelectronics-to-VLSI packaging technology
An Infrastructure IP for On-Chip Clock Jitter Measurement
Leading-one prediction scheme for latency improvement in single datapath floating-point adders
Power supply and consumption co-optimization of portable embedded systems with hybrid power supply
UBIST version of the SYCO's control section compiler
Temperature-to-power mapping
Hardware-Software Co-Design for Content-Based Sparse Attention
System-Level Specification of Instruction Sets
Forca: Fast and Atomic Remote Direct Access to Persistent Memory
Energy Characterization of Hardware-Based Data Prefetching
Maximum Clique Based Method for Optimal Solution of Pattern Classification
CAST: An Efficient Framework for Schedules Performance Prediction Based on Compact ASTs
A cached system architecture dedicated for the system IO activity on a CPU board
Object relocation in OX
Pulse Ring Oscillator Tuning via Pulse Dynamics
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches
Multi: Reduce Energy Overhead of Criticality-Aware Dynamic Instruction Scheduling for Energy Efficiency
A low-impedance load detector circuit for optical interconnects
Data placement in HPC architectures with heterogeneous off-chip memory
FlexRAM: Toward an Advanced Intelligent Memory System
Functional Locking through Omission: From HLS to Obfuscated Design
Reliable and high performance STT-MRAM architectures based on controllable-polarity devices
Area Optimization for Higher Order Hierarchical Floorplans
GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis
From IP to Platforms
Repair of RAMs With Clustered Faults
Extending VLSI design with higher-order logic
Phi-Test: Perfect Hashed Index Test for Test Response Validation
An Integrated Design Environment for Application Specific Integrated Processor
AceHomo: Accelerating Privacy Preserving Inference Through Dynamic Level Adjustment
Efficient BIST TPG design and test set compaction for delay testing via input reduction
Task assignment by parallel simulated annealing
Empirical performance models for 3T1D memories
Fault-Tolerant Content Addressable Memory
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
An Optical Multichip Module
Interrupt-based hardware support for profiling memory system performance
Run-Time Execution of Reconfigurable Hardware in a Java Environment
InDeF: An Advanced Defragmenter Supporting Migration Offloading on ZNS SSD
On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution
Using Circuits and Systems-Level Research to Drive Nanotechnology
HyperDrone: An Accurate, Robust, Fast, and Energy-Efficient Approach for Drone Classification
KeSCo: Compiler-based Kernel Scheduling for Multi-task GPU Applications
Task model for on-chip communication infrastructure design for multicore systems
Static Function Prefetching for Efficient Code Management on Scratchpad Memory
Equivalence verification for NULL Convention Logic (NCL) circuits
Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design
Challenges in the Formal Verification of Complete State-of-the-Art Processors
A Data Alignment Technique for Improving Cache Performance
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem
Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor
Formal Verification and its Impact on the Snooping versus Directory Protocol Debate
A low-power logic optimization methodology based on a fast power-driven mapping
Characterization of granularity and redundancy for SRAMs for optimal yield-per-area
RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators
HyFarM: Task Orchestration on Hybrid Far Memory for High Performance Per Bit
Resonant frequency divider design methodology for dynamic frequency scaling
Simulation-based functional test justification using a decision-digram-based Boolean data miner
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design
A Lightweight and Adaptive Cache Partitioning Scheme for Content Delivery Networks
Enabling Accurate Performance Isolation on Hybrid Storage Devices in Cloud Environment
CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds
CIDAN: Computing in DRAM with Artificial Neurons
37th IEEE International Conference on Computer Design, ICCD 2019, Abu Dhabi, United Arab Emirates, November 17-20, 2019
Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures
The Design and Evaluation of an Asynchronous Microprocessor
DfT optimization for pre-bond testing of 3D-SICs containing TSVs
Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking
Physical Planning Of On-Chip Interconnect Architectures
Passive compensation for high performance inter-chip communication
Ring data location prediction scheme for Non-Uniform Cache Architectures
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs
32nd IEEE International Conference on Computer Design, ICCD 2014, Seoul, South Korea, October 19-22, 2014
A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping
QuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN Accelerators
Time Domain Simulation of Multiconductor Transmission Lines with Frequency-Dependent Losses
Design and Implementation of the TRIPS Primary Memory System
On a class of (2n-1)-stage rearrangeable interconnection networks
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization
Parallel calculation of shortest paths in sparse graphs on a systolic array
Interconnection delay in very high-speed VLSI
Supporting Pipelined Memory Accesses in Processor Synthesis
The fault dropping problem in concurrent event driven simulation
Statistical Timing Analysis of Combinational Circuits
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion
A reduction scheme to optimize the Wallace multiplier
Reduced complexity test generation algorithms for transition fault diagnosis
Zen and the art of Alpha verification
FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration
Automatic SystemC TLM generation for custom communication platforms
A Compositional Transformation for Formal Verification
FlexRAM: Toward an advanced Intelligent Memory system
Modeling and analysis of non-rectangular transistors caused by lithographic distortions
Profiling Interrupt Handler Performance through Kernel Instrumentation
An accurate Energy estimation framework for VLIW Processor Cores
Practical design and performance evaluation of completion detection circuits
Performance Impact of Addressing Modes on Encryption Algorithms
A VLSI array architecture with dynamic frequency clocking
A Fast Median Filter Using AltiVec
DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural Networks
Power-aware virtual machine mapping in the data-center-on-a-chip paradigm
Design of Concurrent Error-Detectable VLSI-Based Array Dividers
ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovations
HyF2FS: A Filesystem to Fully Exploit the Parallelism of Hybrid Storage
Scheduling under data and control dependencies for heterogeneous architectures
Low-Energy DSP Code Generation Using a Genetic Algorithm
Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures
A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond
Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short Writes
Parallel Cachelets
A Design Methodology for Application-Specific Real-Time Interfaces
Dynamic List-Scheduling with Finite Resources
Modeling and analysis of Phase Change Materials for efficient thermal management
Optimization of Wire Pipelining and Channel Parallelism for 2D-Mesh NoC Physical Design
Tripod: Harmonizing Job Scheduling and Data Caching for Analytics Frameworks
Exploiting eDRAM bandwidth with data prefetching: simulation and measurements
Electromigration median time-to-failure based on a stochastic current waveform
Register Estimation from Behavioral Specifications
A VLSI module for IEEE floating-point multiplication/division/square root
A fast algorithm for mixed-radix conversion in residue arithmetic
RNC: Efficient RRAM-aware NAS and Compilation for DNNs on Resource-Constrained Edge Devices
Multilevel Reverse-Carry Adder
Figures of merit for system path time estimation
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation
Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees
Exploitation of operation-level parallelism in a processor of the CRAY X-MP
Applying Swarm Intelligence to Distributed On-Chip Power Management
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening
High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder
MCOMA: A Multithreaded COMA Architecture
Supercomputing on a Chip: Evolution and Challenges
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File
Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics
Power Constrained Design of Multiprocessor Interconnection Networks
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
Rectilinear Block Placement Using B*-Trees
Fixed-outline Floorplanning through Better Local Search
A high throughput FFT processor with no multipliers
Low-Power Radix-4 Combined Division and Square Root
MixRec: Orchestrating Concurrent Recommendation Model Training on CPU-GPU platform
Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows
Computer aided design and built in self test on the i486TM CPU
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks
Hardware design of a Binary Integer Decimal-based floating-point adder
Energy-efficient data movement with sparse transition encoding
Emulation-based selection and assessment of assertion checkers for post-silicon validation
Ninja: A Hardware Assisted System for Accelerating Nested Address Translation
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation
NVCool: When Non-Volatile Caches Meet Cold Boot Attacks
DPLFS: A Dual-Mode PCM-based Log-Structured File System
RCS: A Redirection Computational Scheduler to Accelerate Straggler Recovery for Erasure Coded Cloud Storage System
Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip
A symbolic-simulation approach to the timing verification of interacting FSMs
Leveraging Firmware Reverse Engineering for Stealthy Sensor Attacks via Binary Modification
On Effective Data Supply For Multi-Issue Processors
VEGA: Implementing a Versatile and Efficient Deep Learning Processor with Graph-Based ALU
25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications
qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework
The MARCO/DARPA Gigascale Silicon Research Center
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Patching Processor Design Errors
Reducing Cost and Tolerating Defects in Page-based Intelligent Memory
The Accuracy and Efficiency of Posit Arithmetic
Optimizing the Thermal Behavior of Subarrayed Data Caches
19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings
Adaptive Selection of an Index in a Texture Cache
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement
3DPX - An Open-Source Methodology for 3D Physical Design Exploration
Estimation of sequential circuit activity considering spatial and temporal correlations
Multiplexor Network Generation in High Level Synthesis
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
POM: a processor model for image processing
An Optimal Algorithm for Spiral Floorplan Designs
RECAP: Region-Aware Cache Partitioning
Fully Differential Optical Interconnects for High-Speed Digital Systems
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
A Feasibility Study of Subthreshold SRAM Across Technology Generations
SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement
Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms
Hardware-Assisted Malware Detection using Explainable Machine Learning
Design of an efficient power distribution network for the UltraSPARC-I microprocessor
Profile-Driven Generation of Trace Samples
Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels
An area-efficient Ternary CAM design using floating gate transistors
Efficient verification of out-of-order behaviors with relaxed scoreboards
Architectural Support for Dynamic Memory Management
Liquid Nitrogen CMOS for Computer Applications
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
FlashMP: Fast Discrete Transform-Based Solver for Preconditioning Maxwell's Equations on GPUs
A Stream Processor Development Platform
An Effective and Balanced Storage Extension Approach for Sharding Blockchain Systems
An empirical study of datapath, memory hierarchy, and network in SIMD array architectures
EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs
A flexible architecture for neural networks
Modeling and reduction of complex timing constraints in high performance digital circuits
Transaction-based debugging of system-on-chips with patterns
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings
Automatic verification of speed-independent circuits with Petri net specifications
ABDTR: Approximation-Based Dynamic Traffic Regulation for Networks-on-Chip Systems
A new architectural-level fault simulation using propagation prediction of grouped fault-effects
Breeze: User-Level Access to Non-Volatile Main Memories for Legacy Software
Simultaneous bidirectional signalling for IC systems
An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling
EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology
High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains
PerfDBT: Efficient Performance Regression Testing of Dynamic Binary Translation
Efficient Table-Based Polynomial on FPGA
Implementing a High-Frequency Pattern Generator Based on Combinational Merging
Sneak path testing and fault modeling for multilevel memristor-based memories
Verification of Timed Circuits with Failure Directed Abstractions
Spintronic logic gates for spintronic data using magnetic tunnel junctions
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
Checking Equivalence for Circuits Containing Incompletely Specified Boxes
HPA: A Hybrid Data Flow for PIM Architectures
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks
Co-Designing a 3D Transformation Accelerator for Versal-Based Image Registration
Speculative Trace Scheduling in VLIW Processors
Symbolic Binding for Clustered VLIW ASIPs
Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs
Combinational Digit-Set Converters for Hybrid Radix-4 Arithmetic
The Commercial Realization of Multi-Chip Modules Quo Vadimus
HW/SW Codesign for Embedded Telecom Systems
MG-Voltage: Characterizing and Mitigating Voltage Noise in MCM-GPU Architectures
Continual hashing for efficient fine-grain state inconsistency detection
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor
Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources
A Path Sensitization Approach to Area Reduction
Prediction-Guided Metadata Backup for Improving Lifetime on Flash-based Swap
Design and analysis of FPGA/FPIC switch modules
A novel architecture for an ATM switch
ASMA: An Anisotropy Scaling Memristor-Based Accelerator for LLM Inference
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects
Archivist: A Machine Learning Assisted Data Placement Mechanism for Hybrid Storage Systems
Early Performance Estimation of Super Scalar Machine Models
Accurate device modeling techniques for efficient timing simulation of integrated circuits
BRASIL: A High-Integrity GPGPU Toolchain for Automotive Systems
Combined optimal and heuristic approaches for multiple constant multiplication
Using regression analysis for GA-based ATPG parameter optimization
A Formally Verified System for Logic Synthesis
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems
Parallel Multiple-Symbol Variable-Length Decoding
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors
BranchSpec: Information Leakage Attacks Exploiting Speculative Branch Instruction Executions
Long term sustainability of differentially reliable systems in the dark silicon era
Amdahl Chip Delay Test System
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine
Thread-aware dynamic shared cache compression in multi-core processors
Automatic Derivation of FSM Specification to Implementation Encoding
A methodology to generate evenly distributed input stimuli by clustering of variable domain
towards A formal Model of Shared Memory Consistency for Intel Itanium TM
The ETCA Data-Flow Functional Computer for Real-Time Image Processing
An approach to verify a large scale system-on-a-chip using symbolic model checking
A Recursive Technique for Computing Lower-Bound Performance of Schedules
Adaptable intrusion detection using partial runtime reconfiguration
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264
Accelerated Verification of Parametric Protocols with Decision Trees
Interface Synthesis using Memory Mapping for an FPGA Platform
Sequential hardware Trojan: Side-channel aware design and placement
A Stripe-Schedule Aware Repair Technique in the Heterogeneous Network for Erasure-coded Clusters
On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W
BDD-based circuit restructuring for reducing dynamic power
Novel architecture for a high performance full custom graphics processor
Efficient Crosstalk Estimation
GAN-BiLSTM-HDC: A Hybrid Framework for Robust and Hardware-Efficient Malware Detection
JOP-alarm: Detecting jump-oriented programming-based anomalies in applications
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS
Module Generators for a Regular Analog Layout
A VLSI residue arithmetic multiplier with fault detection capability
CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM
EM-GAN: Data-Driven Fast Stress Analysis for Multi-Segment Interconnects
Newton: Performance Improvement Through Comparative Analysis
CMOS High-Speed I/Os - Present and Future
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz
ACES: A Transient Simulation Strategy for Integrated Circuits
A hierarchical floorplanning approach
Synthesis of Multi-Dimensional Applications in VHDL
On the estimation of logic complexity for design automation applications
Benchmarking and Analysis of Architectures for CAD Applications
MxN Booth Encoded Multiplier Generator Using Optimized Wallace Trees
International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA
Accelerating the Training of Single Layer Binary Neural Networks using the HHL Quantum Algorithm
Enhancing topological ATPG with high-level information and symbolic techniques
Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization
System-Architectures for Sensor Networks Issues, Alternatives, and Directions
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs
On modeling impact of sub-wavelength lithography on transistors
Bespoke Behavioral Processors
Built-in Self Test for Contect Addressable Memories
An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault Simulation
MALLS: Multi-Agent LLMs for Synthetic Hardware Vulnerability Generation and Detection
RDP 3 : Rapid Domain Platform Performance Prediction for Design Space Exploration
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits
Special Session: Exploring the Ultimate Limits of Adiabatic Circuits
Applying verification intention for design customization via property mining under constrained testbenches
Memory-centric accelerator design for Convolutional Neural Networks
A Novel Convolutional Neural Network Accelerator That Enables Fully-Pipelined Execution of Layers