yusuke1997/dblp-id-title huggingface dataset:
Understanding the landscape of accelerators for vision
A unified instruction set programmable architecture for multi-standard advanced forward error correction
An Efficient Data Reuse Motion Estimation Engine
Bandwidth Efficient Architectures for Convolutional Neural Network
Histogram of oriented gradients front end processing: An FPGA based processor approach
An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders
Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs
Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems
A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks
An ASIC for Energy-Scalable, Low-Power Digital Ultrasound Beamforming
Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera
Approximate Comparator: Design and Analysis
Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model
Shared-variable Synchronization Approaches for Dynamic Data Flow Programs
Full Dimension MIMO (FD-MIMO) - Reduced Complexity System Design and Real-Time Implementation
Design of Low-Power Memory-Efficient Viterbi Decoder
Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems
Pipelined Implementations for Belief Propagation Polar Decoder: From Formula to Hardware
Methodology to Adapt Neural Network on Constrained Device at Topology level
A Hybrid GPU + FPGA System Design for Autonomous Driving Cars
Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators
Statistical analysis of Post-HEVC encoded videos
Reduced-complexity MSGR-based matrix inversion
Traffic-Balanced Topology-Aware Multiple Routing Adjustment for Throttled 3D NOC Systems
A fully-unrolled LDPC decoder based on quantized message passing
Neural Network Based Decision Fusion for Abnormality Detection via Molecular Communications
TernGEMM: GEneral Matrix Multiply Library with Ternary Weights for Fast DNN Inference
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems
H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational Complexity
Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios
Automated gateware discovery using open firmware
Bridge deep learning to the physical world: An efficient method to quantize network
IGRAND Query Reduction using Even Codes
A Practical Two-Stage Optimization for Secure Directional Modulation in UAV Systems
Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
0.35 m 22W Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications
Energy-Adaptive Modulation for RF Power Management under Renewable Energy
Soft decoder architecture of LT codes
iGYM: An Inclusive Augmented Reality Exergame for People of All Abilities
32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application
A Chip Architecture for Compressive Sensing Based Detection of IC Trojans
A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller
Tensorial Hankel Reconstruction for Multi-Frequency Sparse Array with Sensor Failure
Error resilient MRF message passing architecture for stereo matching
Demonstrating Confidence in Radio Frequency Machine Learning Systems
A Secure and Robust Key Generation Method Using Physical Unclonable Functions and Polar Codes
Hardware error correction using local syndromes
Robust tree construction and maintenance for global time synchronization protocols in Wireless Sensor Networks
Design and Analysis of LDPC Decoders for Software Defined Radio
Frequency domain: Efficient and high speed technology for video transmission
An Efficient Hardware Architecture for Lossless Data Compression in Data Center
New simplified sum-product algorithm for low complexity LDPC decoding
Fast and Efficient Decision-Based Attack for Deep Neural Network on Edge
Understanding and Optimizing INT4 Convolution for Accelerated DNN Inference on Tensor Cores
An Efficient Real-Valued Cross-Correlator via Fast Fourier Transform
Successive cancellation decoder for very long polar codes
Graph Coordination for Compact Representation of Regular Dataflow Structures
IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor
Parallel SFSD MIMO detection with SOFT-HARD combination enumeration
A simple and accurate method for white blood cells segmentation using K-means algorithm
A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm
Stable Noise Subspace Estimation Algorithm Suitable for VLSI Implementation
Transparent Embedded Compression in Systems-on-Chip
Ensemble Neural Network Method for Wind Speed Forecasting
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks
A real-time embedded system for human gait analysis
IEEE Workshop on Signal Processing Systems, SiPS 2020, Coimbra, Portugal, October 20-22, 2020
Spatial Feature Based Video Scaling Scheme and its FPGA Implementation for Video Standards Conversion
High-Throughput VLSI Architecture for GRAND
FPGA Prototyping of A Millimeter-Wave Multiple Gigabit WLAN System
Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications
A speed up efficient match kernel for visual estimation and detection
In-Air Ultrasonic 3D-Touchscreen with Gesture Recognition Using Existing Hardware for Smart Devices
Pilot-Assisted Methods for Channel Estimation in MIMO-V-OFDM Systems
Arctangent Processor Design for the Frequency Offset Estimation of IEEE 802.16D Wirelessman-OFDM System
A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes
2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016, Dallas, TX, USA, October 26-28, 2016
Bidirectional interleavers for LDPC decoders using transmission gates
Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study
Beam Alignment for the Cell-Free mmWave Massive MU-MIMO Uplink
FPGA Implementations of LDPC over GF(2 m ) Decoders
A robust RAM-THP architecture for downlink multiuser MISO transmission with user scheduling
Programmable implementation of zero-crossing demodulator on an application specific processor
Resource-Aware Optimization of Modular, Cascade Detection Systems
Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios
Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis
Off-grid radar coincidence imaging based on block sparse Bayesian learning
Connectivity-Probability-Driven Multi-RIS Placement in Irregular Regions
Development and evaluation of scalable video motion estimators on GPU
Machine Learning in Optical Communication Systems and Networks
Algorithmic complexity analysis on data transfer rate and data storage for multidimensional signal processing
Two-dimensional crosstalk avoidance codes
Multidimensional Dataflow Graph Modeling and Mapping for Efficient GPU Implementation
A fixed-point neural network for keyword detection on resource constrained hardware
Exit Chart Aided Irregular Convolutional Code Design for Iterative Downlink SDMA Systems Using Imperfect Channel State Information
2018 IEEE International Workshop on Signal Processing Systems, SiPS 2018, Cape Town, South Africa, October 21-24, 2018
Circlet based framework for red blood cells segmentation and counting
Low-complexity polynomials modulo integer with linearly incremented variable
Inexpensive correctly rounded floating-point division and square root with input scaling
DSP implementation of probabilistic sound source localization
A polar-based demapper of 8PSK demodulation for DVB-S2 systems
Efficient multicore scheduling of dataflow process networks
Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation
A Reconfigurable DNN Training Accelerator on FPGA
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems
Conflict resolution for pipelined layered LDPC decoders
Design and Implementation of a Highly Accurate Stochastic Spiking Neural Network
IPPro: FPGA based image processing processor
High-performance programs by source-level merging of RVC-CAL dataflow actors
Empirical evaluation of multi-device profiling side-channel attacks
Digit recognition with confidence
A low complexity estimation architecture based on noisy comparators
Fast pipeline schedule for an H.264 intra frame encoder with early termination
Fast modified Horn & Schunck method for the estimation of optical flow fields
Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies
A Reconfigurable Memory PUF Based on Tristate Inverter Arrays
Efficient Reconfigurable Vandermonde Matrix Inverter for Erasure-Correcting Generalized Integrated Interleaved Decoding
A Partial Self-Reconfigurable Adaptive FIR Filter System
Globally Assisted Instance Normalization for Bandwidth-Efficient Neural Style Transfer
Memory access characteristics of H.264 video encoder on embedded processor
SAWP: Scaled Adaptive Wavelet Pooling for Audio Classification Tasks
Revisiting GRAND via High Level Synthesis
Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories
Spatial Optical Distortion Correction in an FPGA
Efficient near-MMSE detector for large-scale MIMO systems
Design of high performance timing recovery loops for communication applications
Hardware acceleration for tracking by computing low-order geometric moments
Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications
Automated Architectural Exploration for Signal Processing Algorithms
Programmable in-loop deblock filter processor for video decoders
Manipulation of the Fundamental Frequency Micro-Variations using a Fully Parametric and Computationally Efficient Speech Model
Sphere Decoding for Multiprocessor Architectures
Noise Identification for Data-Augmented Physics-Based State-Space Models
Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC
Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon
Highly Parallel Singular Value Decomposition for Low-Latency MIMO Processing
Efficient Compressed Landweber Detector for Massive MIMO
A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction
A stochastic number representation for fully homomorphic cryptography
Outage Probability Analysis in a Cooperative Non-orthogonal Multiple Access Relaying Network
MEMS Inertial Motion Sensing Watch for Measuring Walking and Running Activities
Dynamic group allocation reconstruction for group sparse signals
Arithmetic Computations Based on Chemical Reaction Networks
A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons
Task-based execution of synchronous dataflow graphs for scalable multicore computing
AdaBoost-assisted Extreme Learning Machine for Efficient Online Sequential Classification
AECRN: A Unified Neural-Network for Improving Hearing Aid Speech Enhancement
A Multi-Domain Architectural Efficiency Metric
Reducing the Complexity of Orthogonal Code Based Synthetic Aperture Ultrasound System
A Novel D-Metric for Blind Detection of Polar Codes
Fix-Point Representation of a Properness-Based Algorithm for Blind I/Q Mismatch Compensation
Mapping visual signal processing onto multi-core platform via algorithm/architecture co-exploration
Pre-Sorted Forward-Backward NB-LDPC Check Node Architecture
Efficient multiplierless architecture for frame synchronization in DVB-S2 standard
Memory-Based List Updating for List Sphere Decoders
Composite data fusion algorithm for miniature vehicles building navigation base in formation flying
Joint Image Deblur and Poisson Denoising based on Adaptive Dictionary Learning
Autonomous Vehicle Positioning with LiDAR-Only Sensing: An Application on the RACECAR Dataset
HM-Detect: A Novel Method for Heart Murmur Detection and Classification Using Machine Learning and Sound Feature Analysis
Improved crosstalk avoidance codes based on a novel pattern classification
Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor
Automating the Verification of SDR Base band Signal Processing Algorithms Developed on DSP/FPGA Platform
Experimental Method of Pitching Scene Retrieval Utilizing Statistically Processed Motion Quantities Defined from Motion Vectors on Blocked Frames
Accelerating Computer Vision Algorithms on Heterogeneous Edge Computing Platforms
Iteratively Decoded Irregular Variable Length Coding and Trellis Coded Modulation
Word-Level Acoustic Modeling of Speech for COVID-19 Detection
AVX-512 Based Software Decoding for 5G LDPC Codes
Simplified Early-Stopping for AED-SC of Polar Codes
Multiresolution Gabor Feature Extraction for Real Time Applications
Movie Classification Using Visual Effect Features
High-Speed Pipelined EGG Processor on FPGA
Optimal dual frequency combination for Galileo mass market receiver baseband
Adaptive Detection and Concealment Algorithm of Defective Pixel
A high-throughput multi-rate LDPC decoder for error correction of solid-state drives
A Two-Step Wideband DOA Estimation Method Based on One-Bit Measurements
Computational complexity of cyclotomic fast Fourier transforms over characteristic-2 fields
2019 IEEE International Workshop on Signal Processing Systems, SiPS 2019, Nanjing, China, October 20-23, 2019
Kolmogorov-Smirnov Test for Spectrum Sensing: From the Statistical Test to Energy Detection
Adaptive Noise Subspace Estimation Algorithm with an Optimal Diagonal-Matrix Step-Size
HMAX image processing pipeline with coupled oscillator acceleration
A new fast satellite selection algorithm for BDS-GPS receivers
2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014
Reconfigurable FIR Lowpass Equalizers
An improved min-sum based column-layered decoding algorithm for LDPC codes
High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications
Morphable DPU: Smart and efficient data path for signal processing applications
An Efficient Data-Aided Initial Frequency Synchronizer for DVB-S2
A Non-EEG Biosignals Dataset for Assessment and Visualization of Neurological Status
Low-Complexity, Sub-Band DPD with Sequential Learning: Novel Algorithms and WARPLab Implementation
Fast Energy Optimization of On-Chip ECC Memories
High speed decoding of non-binary irregular LDPC codes using GPUs
Data-Canonic Real FFT Flow-Graphs for Composite Lengths
Design and Implementation of Autoencoder-LSTM Accelerator for Edge Outlier Detection
Layered Steered Space-Time Codes Using Iterative Detection
Defect-tolerant digital filtering with unreliable molecular electronics
Interference Reduction Modulation Based on Chirp Spread Spectrum for Capsule Endoscopy
Low-Complexity Integer Divider Architecture for Homomorphic Encryption
Wasserstein-Based Similarity Constrained Matrix Factorization for Drug-Drug Interaction Prediction
MIMO Detector Based on Viterbi Algorithm
Method for Decreasing Computation Load and Memory Access Frequency during Interpolation for Video Coding
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks
Energy and Processing Demand Analysis of TLS Protocol in Internet of Things Applications
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning
A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System
Memory-efficient Error Correction Scheme for Flash Memories using GPU
Neuromorphic acceleration for context aware text image recognition
Acceleration of clustering-based superpixel algorithms with low memory costs
Expectation Propagation-Guided Diffusion Detection for Large-Scale MIMO Systems
Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM Systems
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information
Low-cost antenna array via antenna switching for high resolution 2-D DOA estimation
Reconfigurable video decoder with transform acceleration
Fully Convolutional Network-Based DOA Estimation with Acoustic Vector Sensor
Low energy process variation tolerant digital image processing system design based on accuracy-energy tradeoffs
Flexible Channel Estimation for 3GPP 5G IoT on a Vector Digital Signal Processor
Model-based design and implementation of an adaptive digital predistortion filter
COSMIC: a real-time platform for signal processing pipelines
Low Power Multipliers Using Enhenced Row Bypassing Schemes
Power and Thermal Modeling for Communication Systems
Synthesis of Probability Theory Based on Molecular Computation
Efficient scalable hardware architecture for highly performant encoded neural networks
Neural Network-based Vehicle Image Classification for IoT Devices
Audio Enhancement via Noise Reduction through Gabor Expansion
Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China
An information-theoretic framework for joint architectural and circuit level optimization for olfactory recognition processing
Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry
Energy Modeling of Cluster System
Enhancing GNSS signal acquisition through the Gradient method
Sub-spectrogram Segmentation for Environmental Sound Classification via Convolutional Recurrent Neural Network and Score Level Fusion
Improved Ciphertext Multiplication for RNS-CKKS Homomorphic Encryption
Architecture-Aware LDPC Code Design for Software Defined Radio
Error-resilient systems via statistical signal processing
Low-Complexity Architectures for Parallel Long BCH Encoders
Implementing a LoRa Software-Defined Radio on a General-Purpose ULP Microcontroller
An efficient conjugate residual detector for massive MIMO systems
A New Video Compression Scheme Combining Conditional Replenishment and Address Event Representation
Stochastic modeling for floating-point to fixed-point conversion
A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels
Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit
PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design
Generation of Efficient Self-adaptive Hardware Polar Decoders Using High-Level Synthesis
Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit
Design of LT code degree distribution with profiled output ripple size
Non-coherent Off-grid DOA Estimation with Magnitude-only Measurements under a Linear Model
Coarse Self-Synchronization Technique for GNSS Receivers
Methodology and technique to improve throughput of FPGA-based Cal dataflow programs: Case study of the RVC MPEG-4 SP Intra decoder
Energy-efficient HOG-based object detection at 1080HD 60 fps with multi-scale support
Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels
Low Resource Species Agnostic Bird Activity Detection
Model-based dynamic scheduling for multicore implementation of image processing systems
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs
SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel
Enhancing Secrecy Rates in UAV Communications via Phase Optimization and Artificial Noise Beamforming
Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations
A Data Structure-Based Approximate Belief Propagation Decoder for Polar Codes
Speech/Audio Signal Classification Using Spectral Flux Pattern Recognition
Scalable compressive sensing-based multi-user detection scheme for Internet-of-Things applications
Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 m Technology
Low Power Sparse Polynomial Equalizer (SPEQ) for Nonlinear Digital Compensation of an Active Anti-Alias Filter
An Adaptive Nested Scalar Quantization Scheme for Distributed Video Coding
Design space exploration of dataflow-based Smith-Waterman FPGA implementations
Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors
Contrastive Learning in Memristor-Based Neuromorphic Systems
Saliency prediction using scene motion for JND based video compression
Sound Source Localization for Household Robot Algorithms and System Integration
Hierarchical run time deadlock detection in process networks
A Camera-Based Approach to Prevent Fingerprint Hacking
A Genetic Algorithm for Designing Uncoded Space-Time Labelling Diversity Mappers
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node
Processing of synthetic Aperture Radar data with GPGPU
EVA-MAC: An event-based adaptive medium access control for wireless sensor networks
Low-latency software LDPC decoders for x86 multi-core devices
Denoising and baseline correction of ECG signals using sparse representation
Efficient Neuromorphic Signal Processing with Loihi 2
What is the world's fastest connected component labeling algorithm?
An efficient two phase image interpolation algorithm based upon error feedback mechanism
A Low-Complexity Massive MIMO Detector Based on Memory Approximate Message Passing
Partitioning and optimization of high level stream applications for multi clock domain architectures
Real polynomial form of music for uniform linear array
A Scalable Generator for Massive MIMO Baseband Processing Systems with Beamspace Channel Estimation
A Modified BP Bit-Flipping Algorithm for Polar Codes
Software designs of image processing tasks with incremental refinement of computation
Sequential polarization imaging using multi-view fusion
Selective tone reservation for PAPR reduction in wireless communication systems
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding
Cuboid array: A novel 3-D array configuration for high resolution 2-D DOA estimation
HybridKernel: Preemptive kernel with event-driven extension for resource constrained wireless sensor networks
Hardware specialization of machine-learning kernels: Possibilities for applications and possibilities for the platform design space (Invited)
Modified Complementary Joint Sparse Representations: A Novel Post-Filtering to MVDR Beamforming
Processing LSTM in memory using hybrid network expansion model
Digital self-interference cancellation in inter-band carrier aggregation transceivers: Algorithm and digital implementation perspectives
Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime
Pattern Synthesis via Convex Optimization for Microphone Arrays
High-performance sparse fast Fourier transforms
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks
A New Inversionless Berlekamp-Massey Algorithm with Efficient Architecture
A search-less DEC BCH decoder for low-complexity fault-tolerant systems
Combining LDPC, turbo and Viterbi decoders: Benefits and costs
Knowledge Distillation for Optimization of Quantized Deep Neural Networks
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography
An FMCW Ranging Method with Identification Ability
A Geometrical Approach for Highly Efficient Soft Demodulation of Rotated Constellations
Indoor Navigation using Text Extraction
A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids
A Channel-Blind Decoding for LDPC Based on Deep Learning and Dictionary Learning
IP-HDC: Information-Preserved Hyperdimensional Computing for Multi-Task Learning
Custom versus Cell-Based ASIC Design for Many-Channel Correlators
Unified decoder architecture for LDPC/turbo codes
Loop scheduling with memory access reduction under register constraints for DSP applications
Memory capacity aware non-blocking data transfer on GPGPU