yusuke1997/dblp-id-title huggingface dataset:
On improving performance of sparse matrix-matrix multiplication on GPUs
PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata
Speeding up Nek5000 with autotuning and specialization
Automatic Optimization of Communication in Compiling Out-of-Core Stencil Codes
An optimized large-scale hybrid DGEMM design for CPUs and ATI GPUs
On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings
Automating Parallel Runtime Optimizations Using Post-Mortem Analysis
Fast greedy weighted fusion
BLASX: A High Performance Level-3 BLAS Library for Heterogeneous Multi-GPU Computing
The specification of a new Manchester Dataflow machine
Supercomputer-based visualization systems used for analyzing output data of a numerical weather prediction model
A freespace crossbar for multi-core processors
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching
Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster
A simple solution to Lamport's concurrent programming problem with linear wait
International Conference on Supercomputing, ICS'13, Eugene, OR, USA - June 10 - 14, 2013
Parallel and vector conjugate gradient-like algorithms for sparse nonsymmetric linear systems
Synchronized access to streams in SIMD vector multiprocessors
DeCOS: Data-Efficient Reinforcement Learning for Compiler Optimization Selection Ignited by LLM
Clairvoyant: a log-based transformer-decoder for failure prediction in large-scale systems
Performance portable optimizations for loops containing communication operations
AnySeq/GPU: a novel approach for faster sequence alignment on GPUs
Algorithmic modifications to the Jacobi-Davidson parallel eigensolver to dynamically balance external CPU and memory load
Advanced Compilation Techniques in the PARADIGM Compiler for Distributed-memory Multicomputers
Software-defined floating-point number formats and their application to graph processing
Parallelization of FORTRAN code on distributed-memory parallel processors
Cache oblivious stencil computations
Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989
Clustering task graphs for message passing architectures
Cyclic dependence based data reference prediction
Analysis and transformation in the ParaScope editor
Fractal symbolic analysis
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators
Author retrospective for semantical interprocedural parallelization: an overview of the PIPS project
Evaluation of methods to integrate analysis into a large-scale shock shock physics code
A model for dataflow based vector execution
Dynamic memory instruction bypassing
EPIClear: Exploiting Domain-Specific Features for Epistasis Detection Acceleration on Tensor Cores
Eliminating Cache Conflict Misses through XOR-Based Placement Functions
Least-Squares Iterative Solution on a Fixed-Size VLSI Architecture
Profile Driven Weighted Decomposition
SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation
Characterizing memory performance in vector multiprocessors
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design
Distributed Ranges: A Model for Distributed Data Structures, Algorithms, and Views
Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C
An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUs
Orthogonal s-step methods for nonsymmetric linear systems of equations
Scaling up matrix computations on shared-memory manycore systems with 1000 CPU cores
Dynamic memory management in massively parallel systems: a case on GPUs
Low level scheduling using the hierarchical task graph
Henosis: workload-driven small array consolidation and placement for HDF5 applications on heterogeneous data stores
Transfer-learning-based Autotuning using Gaussian Copula
A scalable framework for adaptive computational general relativity on heterogeneous clusters
An evaluation of a compiler optimization for improving the performance of a coherence directory
Can we trust profiling results?: understanding and fixing the inaccuracy in modern profilers
The importance of direct dependences for automatic parallelization
GPU road network graph contraction and SSSP query
Using Additive Modifications in LU Factorization Instead of Pivoting
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
Building a high-performance communication layer over virtual interface architecture on Linux clusters
Keynote: Is there anything more to learn about high performance processors?
Performance Optimization for Parallel Tape Arrays
Array abstractions using semantic analysis of trapezoid congruences
Fast-track cache: a huge racetrack memory L1 data cache
A fast approximate interprocedural analysis for speculative multithreading compilers
Reducing Inter-Vector-Conflicts in Complex Memory Systems
Towards an Adaptive Multi-Power-Source Datacenter
Reducing register ports using delayed write-back queues and operand pre-fetch
CMP off-chip bandwidth scheduling guided by instruction criticality
affinity-on-next-touch: increasing the performance of an industrial PDE solver on a cc-NUMA system
Multi-Node Multi-GPU Datalog
Data Caches for Superscalar Processors
A Macrotask-level Unlimited Speculative Execution on Multiprocessors
Performance analysis of buffered banyan networks under nonuniform traffic
Fused3S: Fast Sparse Attention on Tensor Cores
A Compiler-Directed Distributed Shared Memory System
Active pebbles: parallel programming for data-driven applications
Overlapping communication and computation by using a hybrid MPI/SMPSs approach
Load balancing using work-stealing for pipeline parallelism in emerging applications
Automatic nonblocking communication for partitioned global address space programs
On the conditions for efficient interoperability with threads: an experience with PGAS languages using cray communication domains
Characterizing a new class of threads in scientific applications for high end supercomputers
Hardware support for enforcing isolation in lock-based parallel programs
Geometry based mapping strategies for PDE computations
Timing local streams: improving timeliness in data prefetching
Three-dimensional delaunay refinement for multi-core processors
Distributed-Memory Parallel JointNMF
DEDUPKV: A Space-Efficient and High-Performance Key-Value Store via Fine-Grained Deduplication
Block-iterative finite element computations for incompressible flow problems
Hardware-only stream prefetching and dynamic access ordering
Integrating Task and Data Parallelism Using Shared Objects
Benchmark Tests on the Digital Equipment Corporation Alpha AXP 21164-based AlphaServer 8400, Including a Comparison of Optimized Vector and Superscalar Processing
Implementation and performance evaluation of CONFLEX-G: grid-enabled molecular conformational space search program with OmniRPC
The interaction between virtual channel flow control and adaptive routing in wormhole networks
A3FR: Agile 3D Gaussian Splatting with Incremental Gaze Tracked Foveated Rendering in Virtual Reality
Adaptive reduction parallelization techniques
CommBench: Micro-Benchmarking Hierarchical Networks with Multi-GPU, Multi-NIC Nodes
Inspector/executor load balancing algorithms for block-sparse tensor contractions
Phase-Aware Web Browser Power Management on HMP Platforms
A tile selection algorithm for data locality and cache interference
Proceedings of the 39th ACM International Conference on Supercomputing, ICS 2025, Salt Lake City, UT, USA, June 8-11, 2025
Feedback-directed memory disambiguation through store distance analysis
A Static Parameter Based Performance Prediction Tool for Parallel Programs
A formal framework handling the description and implementation of multigrid algorithms
PICS: a performance-analysis-based introspective control system to steer parallel applications
Quasar-ViT: Hardware-Oriented Quantization-Aware Architecture Search for Vision Transformers
High-speed storage control schemes of HITACHI supercomputer S-820 system
An efficient work-distribution strategy for gridding radio-telescope data on GPUs
Processing data streams with hard real-time constraints on heterogeneous systems
Deep reuse: streamline CNN inference on the fly via coarse-grained computation reuse
Strategies for large-scale structural problems on high-performance computers
ChplBlamer: A Data-centric and Code-centric Combined Profiler for Multi-locale Chapel Programs
/scratch as a cache: rethinking HPC center scratch storage
ABCL/onEM-4: a new software/hardware architecture for object-oriented concurrent computing on an extended dataflow supercomputer
GPULZ: Optimizing LZSS Lossless Compression for Multi-byte Data on Modern GPUs
An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels
Performance evaluation of static and dynamic memory systems on the Cray-2
A case for high performance computing with virtual machines
Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002
Optimization of data prefetch helper threads with path-expression based statistical modeling
Cluster oriented architecture for the mapping of parallel processor networks to high performance applications
Large-scale FFT on GPU clusters
AEGIS: architecture for tamper-evident and tamper-resistant processing
A Register Allocation Technique Using Guarded PDG
Performance impact of proxies in data intensive client-server applications
Parallelization of a Reservoir Simulator
A modern high-performance processor pipeline
Hybrid Algorithms for Complete Exchange in 2D Meshes
Hybrid analysis: static & dynamic memory reference analysis
Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996
Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies
ASPaS: A Framework for Automatic SIMDization of Parallel Sorting on x86-based Many-core Processors
Automating and optimizing data transfers for many-core coprocessors
FT-topo: Architecture-Driven Folded-Triangle Partitioning for Communication-efficient Graph Processing
A new approach for performance analysis of openMP programs
On the scalability of the clusters-booster concept: a critical assessment of the DEEP architecture
Instance-wise points-to analysis for loop-based dependence testing
Implementation of 5-point/9-point multi-level methods on hypercube architectures
Kin : A High Performance Asynchronous Processor Architecture
Utilizing Reuse Information in Data Cache Management
Heterogeneous multi-computer system: a new platform for multi-paradigm scientific simulation
Improving the performance of speculatively parallel applications on the Hydra CMP
The scalability of multigrain systems
Optimization of MPI collective communication on BlueGene/L systems
Communication Strategies for Out-of-Core Programs on Distributed Memory Machines
The design and evaluation of high performance communication using a Gigabit Ethernet
Managing Pages in Shared Virtual Memory Systems: Getting the Compiler into the Game
Load Execution Latency Reduction
Bootstrapping Parameter Space Exploration for Fast Tuning
HPC for the human brain project
Fine-Grained Synchronizations and Dataflow Programming on GPUs
Quantifying performance bottleneck cost through differential analysis
Introducing symbolic problem solving techniques in the dependence testing phases of a vectorizer
Revisiting virtual memory for high performance computing on manycore architectures: a hybrid segmentation kernel approach
Enabling and scaling matrix computations on heterogeneous multi-core and multi-GPU systems
Scalable performance analysis of exascale MPI programs through signature-based clustering algorithms
Proceedings of the 37th International Conference on Supercomputing, ICS 2023, Orlando, FL, USA, June 21-23, 2023
Distributed Shared Memory Systems with Improved Barrier Synchronization and Data Transfer
Compression in cache design
Evaluation of the lock mechanism in a snooping cache
TEAPOT: a toolset for evaluating performance, power and image quality on mobile graphics systems
Access conflicts in multiprocessor memories queueing models and simulation studies
Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine
Exploiting Process Imbalance to Improve MPI Collective Operations in Hierarchical Systems
Transactional conflict decoupling and value prediction
Multi-criteria partitioning of multi-block structured grids
Management of PDE Software for Supercomputing
MD-HM: memoization-based molecular dynamics simulations on big memory system
Reducing latencies of pipelined cache accesses through set prediction
Refereeing conflicts in hardware transactional memory
Automatic Selection of Sparse Matrix Representation on GPUs
Accurate, Fast and Scalable Kernel Ridge Regression on Parallel and Distributed Systems
GPUGuard: mitigating contention based side and covert channel attacks on GPUs
Exploiting domain knowledge to optimize parallel computational mechanics codes
Efficient sparse matrix-vector multiplication on x86-based many-core processors
Less reused filter: improving l2 cache performance via filtering less reused lines
An L2-miss-driven early register deallocation for SMT processors
Parallel Eigenanalysis for Nested Grids
Accelerated Auto-Tuning of GPU Kernels for Tensor Computations
Using predicate path information in hardware to determine true dependences
Partitioning programs for parallel execution
Demystifying automata processing: GPUs, FPGAs or Micron's AP?
The ARMv8 simulator
ConTraPh: Contrastive Learning for Parallelization and Performance Optimization
PA-SSD: A Page-Type Aware TLC SSD for Improved Write/Read Performance and Storage Efficiency
MAGNUS: Generating Data Locality to Accelerate Sparse Matrix-Matrix Multiplication on CPUs
Diligent TLBs: a mechanism for exploiting heterogeneity in TLB miss behavior
Efficient Locality-aware Instruction Stream Scheduling for Stencil Computation on ARM Processors
Symmetry and performance in consistency protocols
Revisiting Loop Tiling for Datacenters: Live and Let Live
ACM International Conference on Supercomputing 25th Anniversary Volume
SmartFuse: Reconfigurable Smart Switches to Accelerate Fused Collectives in HPC Applications
Power-aware resource allocation in high-end systems via online simulation
Low-level router design and its impact on supercomputer system performance
A hybrid scheme for detecting AND-parallelism in prolog programs
Load Balanced Parallel Radix Sort
Using silicon and gallium arsenide technologies for new supercomputer design
Measurements and prediction of contention in multiprocessor operating systems with scientific application workloads
Performance Evaluation of a Parallel I/O Architecture
Real-Time In-Memory Checkpointing for Future Hybrid Memory Systems
Multipath Hierarchies in Interconnection Networks
ARIMA time series modeling and forecasting for adaptive I/O prefetching
Minimizing the Lennard-Jones potential function on a massively parallel computer
Parallelizing algorithms for MIMD architectures with shared memory
Improving performance of all-to-all communication through loop scheduling in PGAS environments
A new method to make communication latency uniform: distributed routing balancing
Revisiting phased transactional memory
Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor
Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000
Distributed storage control unit for the Hitachi S-3800 multivector supercomputer
Parallel Software for Million-scale Exact Kernel Regression
An affine partitioning algorithm to maximize parallelism and minimize communication
Rethinking shared-memory languages and hardware
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs
Heterogeneous way-size cache
An approach to resource-aware co-scheduling for CMPs
Sylva: Sparse Embedded Adapters via Hierarchical Approximate Second-Order Information
Semantical interprocedural parallelization: an overview of the PIPS project
Proceedings of the 7th international conference on Supercomputing, ICS 1993, Tokyo, Japan, July 20-22, 1993
Delay sensitivity-driven congestion mitigation for HPC systems
TokenTLB: A Token-Based Page Classification Approach
Responsiveness without interrupts
Experiences tuning SMG98: a semicoarsening multigrid benchmark based on the hypre library
Efficient Support of Parallel Sparse Computation for Array Intrinsic Functions of Fortran 90
Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999
A parallel genetic algorithm for the graph partitioning problem
Techniques to overlap computation and communication in irregular iterative applications
Hierarchical registers for scientific computers
Partitioned first-level cache design for clustered microarchitectures
An integer linear programming approach for optimizing cache locality
Fast and accurate NCBI BLASTP: acceleration with multiphase FPGA-based prefiltering
Author retrospective for code scheduling and register allocation in large basic blocks
NV-group: link-efficient reduction for distributed deep learning on modern dense GPU systems
Parallel program visualization using SIEVE.1
A version control approach to Cache coherence
Generic topology mapping strategies for large-scale parallel architectures
Using performance models to understand scalable Krylov solver performance at scale for structured grid problems
Minimizing Communication While Preserving Parallelism
Enabling scalability-sensitive speculative parallelization for FSM computations
Sequencer virtualization
Global optimization techniques for automatic parallelization of hybrid applications
Implementing a classic: zero-copy all-to-all communication with mpi datatypes
An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1
The GLOW Cache Coherence Protocol Extensions for Widely Shared Data
OpenFFT: An Adaptive Tuning Framework for 3D FFT on ARM Multicore CPUs
Parallel Algorithms for Parenthesis Matching and Generation of Random Balanced Sequences of Parentheses
The parallel solution of nonsymmetric sparse linear systems using the H* reordering and an associated factorization
Fasor: A Fast Tensor Program Optimization Framework for Efficient DNN Deployment
Realizing the performance potential of the virtual interface architecture
Predicting Parallel Applications Performance on Non-Dedicated Cluster Platforms
Uniform techniques for loop optimization
A Comparison of Parallel Programming Paradigms and Data Distributions for a Limited Area Numerical Weather Forecast Routine
The Effectiveness of Decoupling
Anatomy of a Message in the Alewife Multiprocessor
The role of computer designers in reverse-engineering the brain
Percola: a special purpose programmable 64-bit floating-point processor
From mathematical specifications to parallel programs on a message-based system
Taking GPU Programming Models to Task for Performance Portability
Basic Linear Algebra Computations on the Sperry ISP
Array distribution in SUPERB
Supercomputing about Physical Objects
Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine
Towards the effective parallel computation of matrix pseudospectra
Alpha du centaur: a prototype environment for the design of parallel regular alorithms
Proceedings of the 6th international conference on Supercomputing, ICS 1992, Washington, DC, USA, July 19-24, 1992
A run time support system for multiprocessor machines
JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic
Computation regrouping: restructuring programs for temporal data cache locality
Mini-Ckpts: Surviving OS Failures in Persistent Memory
HPC++: Experiments with the Parallel Standard Template Library
A novel application development environment for large-scale scientific computations
Principles of runtime support for parallel processors
Dynamic removal of redundant computations
Impact of task duplication on static-scheduling performance in multiprocessor systems with variable execution-time tasks
Boosting trace cache performance with nonhead miss speculation
UJOpt: Heuristic Approach for Applying Unroll-and-Jam Optimization and Loop Order Selection
Loop Fusion in High Performance Fortran
STAPL-RTS: An Application Driven Runtime System
Critical power slope: understanding the runtime effects of frequency scaling
On the problem of optimizing data transfers for complex memory systems
Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments
Extending High Performance Fortran for the Support of Unstructured Computations
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
A performance analysis of the Berkeley UPC compiler
Scalability analysis of SPMD codes using expectations
The Threaded Communication Library: Preliminary Experiences on a Multiprocessor with Dual-Processor Nodes
Loop optimization for a class of memory-constrained computations
Post-moore server architecture
Benchmark of the Extended Basic Linear Algebra Subprograms on the NEC SX-2 Supercomputer
Push vs. pull: data movement for linked data structures
From Islands to Archipelago: Towards Collaborative and Adaptive Burst Buffer for HPC Systems
Automatic SIMD vectorization of chains of recurrences
The implications of working set analysis on supercomputing memory hierarchy design
Toward a scalable multi-GPU eigensolver via compute-intensive kernels and efficient communication
The NuMesh: A Modular, Scalable Communications Substrate
Integrated in-system storage architecture for high performance computing
HiPA: history-based piecewise approximation for functions
ORION: Optimizing OLAP Query Execution with Proactive Caching and Separate Operators
EDAN: Towards Understanding Memory Parallelism and Latency Sensitivity in HPC
Effective automatic computation placement and dataallocation for parallelization of regular programs
AUTO-PRUNE: automated DNN pruning and mapping for ReRAM-based accelerator
Scaling MPI to short-memory MPPs such as BG/L
Orchestrating data transfer for the cell/B.E. processor
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures
Automating GPU computing in MATLAB
Graph Convolutional Network Acceleration Using Adiabatic Superconductor Josephson Devices
Vectorization techniques for prolog
A Perspective on Parallel Processing
Optimizing Overlapped Memory Accesses in User-directed Vectorization
An Efficient Uniform Run-time Scheme for Mixed Regular-irregular Applications
Multi-layered unstructured mesh generation
High-level semantic optimization of numerical codes
Pattern-based sparse matrix representation for memory-efficient SMVM kernels
Modeling and optimization of non-blocking checkpointing for optimistic simulation on myrinet clusters
Practice of parallelizing network applications on multi-core architectures
Compiler Reduction of Synchronisation in Shared Virtual Memory Systems
Shifted declustering: a placement-ideal layout scheme for multi-way replication storage architecture
A simulation-based study of scheduling mechanisms for a dynamic cluster environment
Adaptive Data Prefetching Using Cache Information
SSDUP: a traffic-aware ssd burst buffer for HPC systems
Efficient Address Generation for Block-Cyclic Distributions
Generating sequential code from parallel code
A Template for Non-Uniform Parallel Loops Based on Dynamic Scheduling and Prefetching Techniques
A novel renaming mechanism that boosts software prefetching
Performance-detective: automatic deduction of cheap and accurate performance models
Increasing effective IPC by exploiting distant parallelism
MODESTO: Data-centric Analytic Optimization of Complex Stencil Programs on Heterogeneous Architectures
Rethinking graph data placement for graph neural network training on multiple GPUs
A robust parallel solver for block tridiagonal systems