yusuke1997/dblp-id-title huggingface dataset:
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits
A complete power estimation methodology for DSP blocks in FPGAs
Novel and efficient min cut based voltage assignment in gate level
Composite spintronic accuracy-configurable adder for low power Digital Signal Processing
An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations
Nanometer-Scale CMOS Devices
Estimating the probability density function of critical path delay via partial least squares dimension reduction
Multi-mode redundancy removal
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses
Leakage current analysis for intra-chip wireless interconnects
Secure, Scalable and Low-Power Junction Temperature Sensing for Multi-Processor Systems-on-Chip
Volume accumulated double gate junctionless MOSFETs for low power logic technology applications
Behavioral Model of Charge-Trap Transistors for Neuromorphic Systems
High-Throughput Hardware Implementation for Haraka in SPHINCS+
On Efficient and Robust Constraint Generation for Practical Layout Legalization
Design Techniques for Gate-Leakage Reduction in CMOS Circuits
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network
Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current
A 4-PAM interconnect in network-on-chip for high-throughput and latency-sensitive applications
Spiking Domain Feature Extraction with Temporal Dynamic Learning
Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads
An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport
Full-Chip Leakage Verification for Manufacturing Considering Process Variations
Optimal reliability-constrained overdrive frequency selection in multicore systems
A simplified single-inductor dual-output DC-DC buck converter architecture with a fully digital Σ-Δ based controller
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders
Design and analysis of low pass microstrip filters using MATLAB
Fast obstacle-avoiding octilinear steiner minimal tree construction algorithm for VLSI design
Formal Verification of Error Bounds for Resistive-Switching-Based Multilevel Matrix-Vector Multipliers
Regularization-Free Structural Pruning for GPU Inference Acceleration
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems
PARADE: PARAmetric Delay Evaluation under Process Variation
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow
A novel low voltage current compensated high performance current mirror/NIC
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications
Slack allocation for yield improvement in NoC-based MPSoCs
A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm
HW/SW Codesign for Approximate In-Memory Computing
Methodology to optimize critical node separation in hardened flip-flops
Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion
Hotspot Based Yield Prediction with Consideration of Correlations
Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level
HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures
A 2 OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic Routing
A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU
An Adaptive Path Delay Fault Diagnosis Methodology
A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell
Timing-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips
Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips
Algorithmic study on the routing reliability problem
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement
A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems
20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, CA, USA, March 6-7, 2019
Large-Scale Logic-Locking Attacks via Simulation
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring
Cellwise OPC Based on Reduced Standard Cell Library
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models
Addressing the IC Designer's Needs: Integrated Design Software for Faster, More Economical Chip Design
Application of Machine Learning for Quality Risk Factor Analysis of Electronic Assemblies
R2CTA: Reinforcement Learning and Reservoir Computing based Chiplets TSV Assignment
V-SYNC-Aware GPU DVFS Governor for Efficient Game Application Execution on Mobile Devices
Transferring Optical Proximity Correction (OPC) Effect into Optical Mode
Temperature aware energy management for real-time scheduling
Reduced Test Application Time Based on Reachability Analysis
Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014
Low power data-aware STT-RAM based hybrid cache architecture
A Technique for Estimating the Difficulty of a Formal Verification Problem
A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit
Transistor-Level Synthesis for Low-Power Applications
Accurate Model of Metal-Insulator-Semiconductor Interconnects
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips
Thermo-Attack Resiliency: Addressing a New Vulnerability in Opto-Electrical Network-on-Chips
Future Memory Technology Trends and Challenges
Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization
Functional Verification of Networked Embedded Systems
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands
Do Digital Design and Variability Mix like Oil and Water?
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction
Increasing memory yield in future technologies through innovative design
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling
Crosstalk timing windows overlap in statistical static timing analysis
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages
Piezoelectric CMOS Charger: Highest Output-Power Design
An information theoretic framework to compute the MAX/MIN operations in parameterized statistical timing analysis
Defending Against Misspeculation-based Cache Probe Attacks Using Variable Record Table
Measurement of Inherent Noise in EDA Tools
Automatic Test Program Generation from RT-Level Microprocessor Descriptions
Compiler-directed leakage energy reduction for instruction scratch-pad memories
Enhanced Identification of Strong Robustly Testable Paths
Dual Use Circuitry for Early Failure Warning and Test
A Survey of DMFBs Security: State-of-the-Art Attack and Defense
Nonlinear delay-table approach for full-chip NBTI degradation prediction
Optimizing SRAM bitcell reliability and energy for IoT applications
VSIA Quality Metrics for IP and SoC
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics
A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
An Asymmetric SRAM Cell to Lower Gate Leakage
A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs
Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit
Fast Thermal Goodness Evaluation of a 3D-IC Floorplan
Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection
Wireless charge recovery system for implanted electroencephalography applications in mice
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration
Resilient Reorder Buffer Design for Network-on-Chip
Layout-aware Illinois Scan design for high fault coverage coverage
Towards Row Sensitive DRAM Refresh through Retention Awareness
A Fast Lithography Verification Framework for Litho-Friendly Layout Design
A Max Weighted-Matching Based Non-Greedy Post-HLS Power Gating Technique with Comprehensive Power Modeling
Study of the impact of aging on many-core energy-efficient DSP systems
Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications
Noise Interaction Between Power Distribution Grids and Substrate
Process variation sensitivity of the Rotary Traveling Wave Oscillator
Analysis and comparison of XOR cell structures for low voltage circuit design
True Random Number Generation using Latency Variations of Commercial MRAM Chips
A Framework for PCB Design File Reconstruction from X-Ray CT Annotations
A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography
Navigating the Trilemma: Security, Power, and Performance Trade-Offs in Bluetooth Low Energy
Analytical Study of Impact Ionization and Subthreshold Current in Submicron n-MOSFET
VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology
Power Gating with Multiple Sleep Modes
An energy-efficient on-chip memory structure for variability-aware near-threshold operation
In&Out: Restructuring for threshold logic network optimization
A study on impact of loading effect on capacitive crosstalk noise
PreAxC: Error Distribution Prediction for Approximate Computing Quality Control using Graph Neural Networks
A Novel Full Adder Design Using Hybrid Memristor Ratioed Logic
Models For Interconnect Capacitance Extraction
Overview of Reliability Issues in Deep Sub-Micron Digital CMOS Technology and Their Interaction with Circuit Design Considerations
Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation
Scalable methods for the analysis and optimization of gate oxide breakdown
Adaptive-Gravity: A Defense Against Adversarial Samples
Novel and Efficient IR-Drop Models for Designing Power Distribution Network for Sub-100nm Integrated Circuits
An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions
Fully Digital Optimized Testing and Calibration Technique for Sigma Delta ADC's
Quantum Quandaries: Unraveling Encoding Vulnerabilities in Quantum Neural Networks
ASLIC: A Low Power CMOS Analog Circuit Design Automation
A High Performance Radiation-Hard Field Programmable Analog Array
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow
On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays
Thermal sensor allocation for SoCs based on temperature gradients
Protocol-guided analysis of post-silicon traces under limited observability
Erect of regularity-enhanced layout on printability and circuit performance of standard cells
Amoeba-Inspired Stochastic Hardware SAT Solver
8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA
Full Chip Thermal Simulation
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops
Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector
2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA
The effect of SRNR on timing characteristics of signal busses
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization
New Test Access for High Resolution SD ADC's by Using the Noise Transfer Function Evaluation
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays
Yield Improvement by Local Wiring Redundancy
The 50-Million Transistor Chip: The Quality Challenge for 2001
Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications
SAC: A Novel Multi-hop Routing Policy in Hybrid Distributed IoT System based on Multi-agent Reinforcement Learning
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability
Analog behavioral modeling flow using statistical learning method
A low power charge-redistribution ADC with reduced capacitor array
Crosstalk-aware signal probability-based dynamic statistical timing analysis
Power management factors and techniques for IoT design devices
Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay
A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design
In-Circuit Self-Tuning of Clock Latencies
Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells
nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract)
Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping
Optimum domain partitioning to increase functional verification coverage
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
Clock trees: differential or single ended?
Stepped Supply Voltage Switching for energy constrained systems
Fully automated PLL compiler generating final GDS from specification
An Efficient Error Estimation Technique for Pruning Approximate Data-Flow Graphs in Design Space Exploration
Quantum Data Breach: Reusing Training Dataset by Untrusted Quantum Clouds
Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization
Shifting Perspective on DFM
A New Simulation Method for NBTI Analysis in SPICE Environment
IMU-Based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform
SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP)
Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates
A case for exploiting complex arithmetic circuits towards performance yield enhancement
Deep neural network acceleration framework under hardware uncertainty
Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices
Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration
High performance source optimization using a gradient-based method in optical lithography
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Measuring Design Quality by Measuring Design Complexity
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization
Post-fabrication calibration of Near-Threshold circuits for energy efficiency
Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems
Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
A system-level solution for managing spatial temperature gradients in thinned 3D ICs
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits
Ruggedness evaluation and design improvement of automotive power MOSFETs
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy
PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs
ERAVC: Enhanced reliability aware NoC router
Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay
Improving the Efficiency of Power Management Techniques by Using Bayesian Classification
Advancing Analog Reservoir Computing through Temporal Attention and MLP Integration
VC Rating and Quality Metrics: Why Bother?
Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits
Challenges and Opportunities for Hardware-Assisted Security Improvements in the Field
A Low-Power Multi-Pin Maze Routing Methodology
An enlarged-partition based preconditioned iterative solver for parallel power grid simulation
Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process
Stochastic-based multi-stage streaming realization of deep convolutional neural network
Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling
Monotonic-HMDs: Exploiting Monotonic Features to Defend Against Evasive Malware
Computation of Waveform Sensitivity Using Geometric Transforms for SSTA
Design Tools for Packaging
Temperature-aware thread assignment of many-core processor
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines
Interconnect delay and slew metrics using the extreme value distribution
ReMAM: Low energy Resistive Multi-stage Associative Memory for energy efficient computing
A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment
BLCR: Towards Real-time DNN Execution with Block-based Reweighted Pruning
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)
Energy Efficient Signaling in Deep Submicron CMOS Technology
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis
Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory
A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning
A Design Methodology for Matching Improvement in Bandgap References
Efficient directed test generation for validation of multicore architectures
Verification and Validation of Complex Digital Systems: An Industrial Perspective
Design and Analysis of "Tree+Local Meshes" Clock Architecture
Parallel implementation of finite state machines for reducing the latency of stochastic computing
Aging Attack on Systolic Array-Based AI Accelerators via NBTI-Induced Aging
A layer prediction method for minimum cost three dimensional integrated circuits
A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs
Fast and Accurate Waveform Analysis with Current Source Models
Revisiting the Noise Figure Design Metric for Digital Communication Receiver
Deep Learning assisted Cross-Family Profiled Side-Channel Attacks using Transfer Learning
Power Grid Modeling Technique for Hierarchical Power Network Analysis
A Model for Timing Errors in Processors with Parameter Variation
Low Power Testing by Test Vector Ordering with Vector Repetition
Novel SAT-based invariant-directed low-power synthesis
PDL: A New Physical Synthesis Methodology
The Expanding Use of Formal Techniques in Electronic Design
Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation
Estimating true worst currents for power grid electromigration analysis
Design and optimization of power gating for DVFS applications
Combating NBTI Degradation via Gate Sizing
A loop structure optimization targeting high-level synthesis of fast number theoretic transform
Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format
An SEU-Tolerant Programmable Frequency Divider
A Built-In Self-Test Scheme for Differential Ring Oscillators
Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance
A 12-bit CMOS current steering D/A converter with a fully differential voltage output
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar
A Simulation-based strategy used in electrical design for reliability
Impact of Gate-Length Biasing on Threshold-Voltage Selection
Flip Chip Advanced Package Solder Joint Embrittlement Fault Isolation Using TDR
Cross Layer Error Exploitation for Aggressive Voltage Scaling
Workload-aware ASIC flow for lifetime improvement of multi-core IoT processors
Adaptive task allocation for multiprocessor SoCs
Printed Circuit Board Assembly Test Process and Design for Testability
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators
Hotspot Prevention Using CMP Model in Design Implementation Flow
Early Addressing IC and Package Relationship Allows an Overall Better Quality of Complex SOC
Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework
TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks
Estimation and optimization of reliability of noisy digital circuits
Markov source based test length optimized SCAN-BIST architecture
Platform-Based Design: A Tutorial (Tutorial Abstract)
Automatic Functional Vector Generation Using the Interacting FSM Model
High Quality Analog CMOS and Mixed Signal LSI Design
System and Framework for QA of Process Design Kits
Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs
An automated design flow for synthesis of optimal multi-layer multi-shape PCB coils for inductive sensing applications
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
SQRTLIB : Library of Hardware Square Root Designs
Murphy was an optimist: Embracing asymmetry in electronics
Low Overhead System-Level Obfuscation through Hardware Resource Sharing
Optimization strategies to improve statistical timing
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology
Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats
Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels
AutoAnnotate: Reinforcement Learning based Code Annotation for High Level Synthesis
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design
Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder Filters
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration
Combining Advanced Process Technology and Design for Systems Level Integration
Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors