yusuke1997/dblp-id-title huggingface dataset:
A Three-Phase Fully-Integrated Reconfigurable Switched-Capacitor Converter For Near-Threshold Computing
Live demonstration: A 1300 × 800, 700 mW, 30 fps spectral polarization imager
A power and area efficient multi-mode FEC processor
A Reduced Spiking Neural Network Architecture for Energy Efficient Context-Dependent Reinforcement Learning Tasks
Design and Implementation of a Temperature Self-Compensation Balanced Hybrid Ring Oscillator BHRO
An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors
Stability analysis of pulse-width-modulated feedback systems with type 2 modulation: the critical case
Analog implementation of encoded neural networks
Live demonstration: Handwritten digit recognition using spiking deep belief networks on SpiNNaker
. Impulsive noise reduction in DSL using a nonlinear TEQ
A Hall sensor microsystem with continuous gain calibration using fully integrated references
SAT-based ATPG for Path Delay Faults in Sequential Circuits
A 2048 complex point FFT architecture for digital audio broadcasting system
Transform domain approximate QR-LS adaptive filtering algorithm
Realization of Negative Power Reactance
A wavelet packet algorithm for 1D data with no block end effects
A reconfigurable architecture for real-time prediction of neural activity
PSpice switch-based versatile memristor model
Two-level decoupled Hamming network for associative memory under noisy environment
Increasing the immunity to electromagnetic interferences in a bandgap voltage reference
Deterministic parallel computation of Bayesian deblurring using cluster approximations
Unified motor controller based on space vector modulation technique
Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device
A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture
CORDIC-SNN: On-FPGA STDP Learning with Izhikevich Neurons
Ultra Compact and Linear 4-bit Digital-to-Analog Converter in 22nm FDSOI Technology
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms
A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping
Techniques to address increased dimensionality of ASIC library design
AR-C3D: Action Recognition Accelerator for Human-Computer Interaction on FPGA
SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits
An organic complementary differential amplifier for flexible AMOLED applications
A power-aware 2-dimensional bypassing multiplier using cell-based design flow
Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK
Efficient power model for crossbar interconnects
A Low-Power and High-Precision Time- Domain Winner-Take-All Circuit Based on the Group Search Algorithm
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis
Gain mismatch effect of cascaded sigma delta modulator reduced by serial technique
HEVC compressed domain moving object detection and classfication
Chopper Modulation Improves OTA Information Transmission
A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits
High throughput quantification system for egg populations in caenorhabditis elegans
Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs
An efficient FPGA-based database processor for fast database analytics
Low-Voltage Temperature-Independent Current Reference with no External Components
High speed and high resolution WTA circuit
A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance
A scalable baseband phase shifter with 12 GHz I/Q Mixers in 40-nm CMOS for 60 GHz applications
Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC
Inertial and degradation delay model for CMOS logic gates
Hysteretic Error Extraction in Multi-Level Wireline Receivers
Active beamforming with interpolated FIR filterin
Bio-inspired Perceptual Video Encoding based on H.264/AVC
A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filters
A piecewise linear dynamical functional artificial neural network (PWL-DFANN) for nonlinear adaptive time series prediction
Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL
Fault Tolerance Analysis of NoC Architectures
A 2Vpk-pk, diff Input Range 1GS/s Voltage-to-Time Converter with Tunable Distortion Compensation
A Fast Two-Dimensional Quasi-Newton Adaptive Filter
New current-mode sense amplifiers for high density DRAM and PIM architectures
Mathematical analysis of inter-band intermodulation for concurrent dual-band mixers
Integer factorization with a neuromorphic sieve
An efficient reduced-order interconnect macromodel for time-domain simulation
Miniaturized Wirelessly-Powered Biphasic Current Stimulator for Implantable Neurostimulation
Process variation compensation of a 4.6 GHz LNA in 65nm CMOS
A novel feature extraction algorithm for classification of bird flight calls
Linear-prediction whitening with convex combining in constant modulus equalizers
Real-Time Image Inpainting using PatchMatch Based Two-Generator Adversarial Networks with Optimized Edge Loss Function
A modified structure for the design of sharp FIR filters using frequency response masking technique
Approach for physical design in sub-100 nm era
Visual signal processing and image understanding in biomedical systems
DAPPER: A Low Power, Dual Amperometric and Potentiometric Single-Channel Front End
A Robust Super-Regenerative Receiver with Optimal Detection on BER Level
On Various Extensions of the Shannon-Hagelbarger Concavity Theorem
Combination of adaptive filtering and spectral subtraction for noise removal
Analog-to-Digital Converters with embedded IF mixing using variable reference voltages
A 0.65V rail-to-rail constant gm opamp for biomedical applications
An iterative method for optimizing FIR filters synthesized using the two-stage frequency-response masking technique
Pulse-based signal compression for implanted neural recording systems
Fast and accurate 2-D DOA estimation via sparse L-shaped array
Hardware implementation of Moore test on FPGA
Channel equalization using the G-Probe
A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation
A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier
A novel algorithm for time-varying gene regulatory networks identification with biological state change detection
190-MHz CMOS 4-Kbyte Pipelined Caches
Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory
Global resource capacity algorithm with path splitting for virtual network embedding
Event-based Neural Spike Detection Using Spiking Neural Networks for Neuromorphic iBMI Systems
Sobel edge detection processor for a real-time volume rendering system
Low-complexity feedback-channel-free distributed video coding with enhanced classifier
Feature Points based Residual UNet with Nonlinear Decay Rate for Partial Wet Fingerprint Restoration and Recognition
Man or Machine - Design Automation of Delta-Sigma Modulators
Upper and lower performance bounds for chaos-based asynchronous DS-CDMA systems
Energy minimization in dynamic supply voltage scaling systems using data dependent voltage level selection
New adaptive partial distortion search using clustered pixel matching error characteristic
Burst receiver for upstream communications over twisted pair lines
FPGA design of a coordinate descent data detector for large-scale MU-MIMO
Approximate optimal demodulation for multi-user binary coherent chaos-shift-keying communication systems
Rapid Spectrum Sweeping Scanner Exploiting Mixer Harmonics for Cognitive Radio Applications
Iterative Signal Extrapolation Algorithms with Wavelets
Effects of quantization on neural spike sorting
A 57.2-Gb/s PAM4 Driver for a Segmented Silicon-Photonics Mach-Zehnder Modulator with Extinction Ratio >9-dB in 45-nm RF-SOI CMOS Technology
Digitally-controlled RF passive attenuator in 65 nm CMOS for mobile TV tuner ICs
A CMOS continuous-time active biquad filter for gigahertz-band applications
Optimizing vertical common subexpression elimination using coefficient partitioning for designing low complexity software radio channelizers
What did Gustav Robert Kirchhoff stumble upon 150 years ago?
A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems
Elliptic curves cryptosystem implementation based on a look-up table sharing scheme
Maximally flat FIR filters
A Floating-Gate-Based Four-Channel Reconfigurable Analog Front-End Integrated Circuit
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit
Improved feedforward ML timing estimation for PSK signaling
Combined frame memory architecture for motion compensation in video decoding
Buffer Planning for 3D ICs
Toward Enabling Automated Cognition and Decision-Making in Complex Cyber-Physical Systems
A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction
A super-fast online face tracking system for video surveillance
Computational properties of LDI/LDD lattice filters
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration
Design models of resistive crossbar arrays with selector devices
Subspace based blind channel estimation for space time block coded OFDM system
Design of high order and wide coefficient wordlength multiplierless FIR filters with low hardware cost using genetic algorithm
High-Performance Implementations of Classic McEliece KEM on GPUs
Compressive Sensing as Applied to Antenna Arrays: Synthesis, Diagnosis, and Processing
Spatiotemporally Modulated Dual-MLP Architecture for Neural Video Representation and Compression
A 2-0 MASH Delta-Sigma ADC with sub-sampling SAR ADC
Noise model, analysis and characterization of a differential active pixel sensor
A flexible global readout architecture for an analogue SIMD vision chip
Reinforcement Learning for HEVC/H.265 Intra-Frame Rate Control
A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems
Analysis of hard synchronous commutations in switching converters
Constant-quality rate allocation for spectral fine granular scalable (SFGS) video coding
A Toolchain for Open-Loop Compensation of Hysteresis and Creep in Atomic Force Microscopes
A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT Delta Sigma Modulator
Generation of active inductor circuits
Transformerless DC-DC converters with a very high DC line-to-load voltage ratio
A high gain decibel-linear programmable gain amplifier of synthetic aperture radar receiver
CMOS-Based Wheatstone Bridge Stress Sensors Sensitive and Insensitive to Mechanical Stress
Designing optimized pipelined global interconnects: algorithms and methodology impact
Moving Object Detection in Shallow Underwater using Multi-Scale Spatial-Temporal Lacunarity
Synchronization of a network of intermittently coupled capacitor circuits
A Steganographic Scheme based on Wet Paper Codes Suitable for Uniformly Distributed Wet Pixels
High-performance RDFT design for applications of digital radio mondiale
Side-channel Attacks Targeting Classical-Quantum Interface in Quantum Computers
Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech Enhancement
QoS-aware network selection for seamless multimedia service
Semantic image clustering using relevance feedback
CMOS thermal sensing system with simplified circuits and high accuracy for biomedical application
A CAD-oriented method for optimal biasing of amplifiers
A 0.63 nW, 327 ppm/ °C Current Reference using Temperature Compensated CMOS Resistors
A 6-Bit 50MHz Current-Subtracting Two Step Flash Converter
The effect of D/A accuracy on the performance of digital predistortion for RF power amplifiers
A high-throughput VLSI architecture for deblocking filter in HEVC
A hierarchical push-pull scheme for peer-to-peer live streaming
Architectural Exploration of Neuromorphic Compression based Neural Sensing for Next-Gen Wireless implantable-BMI
Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning
Folded-current-steering DAC: an approach to low-voltage high-speed high-resolution D/A converters
Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital Circuit
Channel compensation of modulation spectral features
A CMOS Preamplifier for Electret Microphones
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
A low voltage bulk driven downconversion mixer core
Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology
Towards a fully-integrated solution for capacitor-based neural stimulation
Inductor-less bandwidth-extension technique applied to CMOS differential trans-impedance amplifier
Mew diode string design with very low leakage current for using in power supply ESD clamp circuits
An efficient algorithm for the computation of the reverse jacket transform
JPWL - an extension of JPEG 2000 for wireless imaging
A new 1.8V fierce-gate crystal oscillator based on the constant cell in 28nm CMOS technology for automotive radar applications
Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays
A new architecture to compute the discrete cosine transform using the quadratic residue number system
Spiking-Hybrid-YOLO for Low-Latency Object Detection
Rakeness-Based Compressed Sensing of Atrial Electrograms for the Diagnosis of Atrial Fibrillation
An Efficient FPGA Implementation for Real-Time and Low-Power UAV Object Detection
Current-Mode and Voltage-Mode VLSI Fuzzy Processor Architecture
Searching over DOA Parameter Space via Neural Networks
Live Demonstration: An Intelligent Scalp Diagnosis System using Deep Learning for Scalp Healthcare
Impact of gradient error on switching sequence in high-accuracy thermometer-decoded current-steering DACs
A Dual-Mode Adjustable High-Gain Ultra-Low Noise Transimpedance Amplifier for Fine Dust Detection
A CMOS 10 b 60 Msample/s ADC with ultra fast gain control
Matrix quantization based speech coder at 1200 bps
Streamlining DNN Obfuscation to Defend Against Model Stealing Attacks
On synthetic benchmark generation methods
A low-power VLSI implementation for variable block size motion estimation in H.264/AVC
Body Channel Based Wireless Power Transfer Method for Implantable Bioelectronics
A 60-GHz energy harvesting module with on-chip antenna and switch for co-integration with ULP radios in 65-nm CMOS with fully wireless mm-wave power transfer measurement
Clustering to improve bi-partition quality and run time
On the modeling and the stability of continuous-time Sigma-Delta-Modulators
An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode
On-Device Learning in Memristor Spiking Neural Networks
A novel automatic white balance method for digital still cameras
Transistor Channel Dendrites implementing HMM classifiers
Detection of inter-port bridging faults in dual-port memories
A novel yield aware multi-objective analog circuit optimization tool
Low complexity 2-D Hidden Markov Model for face recognition
Long-Short Term Memory Neural Network Stability and Stabilization using Linear Matrix Inequalities
A 19 pJ-K 2 Temperature Sensor using Sub-VTH Ring Oscillator with 1.28°C/V Line Sensitivity
Digital error correction and calibration of gain non-linearities in a pipelined ADC
Making a stable discrete-time system chaotic via small-amplitude output feedback
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM
Dynamically biased current sensor for current-sensing completion detection
Optimal Scheduling for Conditional Recource Sharing
Design of highly-efficient power-controllable CMOS class E RF power amplifiers
A Rule-Based High Efficient Obstacle-Avoiding RSMT Algorithm for VLSI Routing
Digitally controlled buck converter
A 78nW, 814mV/875nA All-in-One Voltage and Current Reference Using Darlington Pair
A distributed slack bus model and its impact on distribution system application techniques
M-SVC (mixed-norm SVC) - a novel form of support vector classifier
A neglected error source in the CORDIC algorithm
Model-Matching Design of Sample-Rate Changers: Asymptotic Analysis
A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS
Characterization and Mitigation of IR-Drop in RRAM-based Compute In-Memory
Genetically-engineered whole-cell bioreporters on integrated circuits for environmental monitoring
Comparison of digital LQR techniques for DC-DC boost converters with large load range
WiiStick: Enhancing Motion Recognition Capability for Wii Systems
A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting
Multi-dimensional Range Joins on HBM-enabled FPGAs
A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique
Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter
A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning
A method for predicting the ZVS condition for the class E amplifier
An all-digital Sigma-Delta-frequency discriminator of arbitrary order
A CMOS contact imager for locating individual cells
A bio-implantable platform for inductive data and power transfer with integrated battery charging
Quasi-hysteretic floating buck LED driver with adaptive off-time for accurate average current control in high brightness lighting
CheckerBoard binary CNN core
High-frequency sequential decimal multipliers
A Low-Voltage Split Memory Architecture for Binary Neural Networks
MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller
Linearising Sigma-Delta Modulators Using Dither and Chaos
A 7-Bit 0.22 dB Step Variable Attenuator with Flat States and Low Phase Variation at 1.5-13.5 GHz using iNMOS Switches
A conductance-based neuronal network in VLSI for studying the CPR circuit of the crayfish
Frequency Synthesis with Arbitrary Input Clock Rate and Rational K/L Multiplier Ratio
Statistical circuit performance variability minimization under manufacturing variations
Fluorescent Intensity and Lifetime Measurement of Platinum-Porphyrin Film for Determining the Sensitivity of Transcutaneous Oxygen Sensor
Low-voltage closed-loop amplifier circuits based on quasi-floating gate transistors
Comparator common-mode variation effects analysis and its application in SAR ADCs
Measurement of Random Sample Time Jitter for ADCs
Optimized algorithms for binary BCH codes
AnalogSim: a Modeling Framework for SRAM-based Analog In-Memory Computing
Data Reuse method between Heterogeneous Partitions (DRHP) in H.264/AVC motion compensator
A floating-gate transistor based continuous-time analog adaptive filter
Implications of Finite Clock Transition Time for LPTV Circuit Analysis
Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case
Recovery of lost blocks by dynamic pixel interleaving
Automated Synthesis of Quantum Circuits Using Symbolic Abstractions and Decision Procedures
Minimum energy broadcasting in wireless networks (extended abstract)
Perturbation analysis of subspace-based semi-blind MIMO channel estimation approaches
Focal-plane on-line nonuniformity correction using floating-gate adaptation
Design methodology for hardware-efficient fault-tolerant nanoscale circuits
Modeling the Telephone Call Network
Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs
Spike-based learning in VLSI networks of integrate-and-fire neurons
Multi-segment Stretchable Strain Sensor using Time Domain Reflectometry
An Energy-Efficient Delay Insensitive Asynchronous Interface for Globally Asynchronous Locally Synchronous (GALS) System
High-Speed Division Algorithm for Residue Number System
A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems
Detecting Fake Deposit Attacks on Cross-chain Bridges from a Network Perspective
Towards an inductively coupled power/data link for bondpad-less silicon chips
A Blind Spot Detection Warning System based on Gabor Filtering and Optical Flow for E-mirror Applications
A mutual exclusion algorithm for a distributed network of autonomous nodes
Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block
Dual-stylus-arm scratch drive micro-robots controlled by a communication channel
A novel CMOS four quadrant multiplier based on linearization of the long tail differential pair
A Power Efficient Time-to-Current Stimulator for Vagal-Cardiac Connection after Heart Transplantation
A Timing Attack Resistant Lightweight Post-Quantum Crypto-Processor for SPHINCS+
Simulation of Networks with Inconsistent Initial Conditions
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator with Bulk Acoustic Wave Resonators
Multibit quadrature sigma-delta modulator with DEM scheme
Design Technology Co-Optimization for CFET SRAM Cells Considering Double-Sided Signal/Power Routing
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
Data-aware Platform Realization of Videotext Extraction for Content Integration
An FSK modulator at 23.2 MHz with ±0.9% accuracy for the USB power delivery standard
Analytic bounds on amplifier gain-bandwidth product from complex power flow
Periodic orbits and bifurcations in one-dimensional arrays of Chua's circuits
Frequency-domain error analysis of linear multistep methods
A low cost jitter estimation and ADC spectral testing method
Circular stack filters
The Structure of Networks Realized from Terminal Capacity Matrices
Design methodology for optimization of analog building blocks using genetic algorithms
A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module
Mapping nodal power injections to branch flows in connected LTI electrical networks
A maximum likelihood approach to state estimation of complex dynamical networks with unknown noisy transmission channel
Design of security enhanced TPM chip against invasive physical attacks
Two-Layered Oscillatory Neural Networks with Analog Feedforward Majority Gate for Image Edge Detection Application
Properties and modeling of ground structures for reducing substrate noise coupling in ICs
CMOS Rectifier with on-chip Transformer-Coupled Tunable Matching Network for Biomedical Implants
Method for design of analog group delay equalizers
Yield enhancement by means of evolutionary computation techniques
Analysis and Design of Broadband Transitions from Microstrip-to-CV-WSIW for mm-Wave Applications
The effects of source impedance on the linearity of BTJ common-emitter amplifiers
Neuromorphic implementation of active gaze and vergence control
Passive reduced-order macromodeling algorithm for structure dynamics in MEMS systems
Affine Transformation Based Hierarchical Extreme Learning Machine
A hardware efficient implementation of an adaptive subsample delay estimator
A 0.9mW Microphone Uplink System in 65nm CMOS
High-speed high-precision voltage-mode MIN/MAX circuits in CMOS technology
Scaling rules and parameter tuning procedure for analog design reuse in technology migration
Dynamic range boosting for wireless optical receivers
VLSI architecture of dynamically reconfigurable hardware-based cipher
A high-sensitivity CMOS biophotometry sensor with embedded continuous-time ΣΔ modulation
S frame design for multiple description video coding
An FPGA platform for generation of stimulus triggering based on intracortical spike activity in brain-machine-body interface (BMBI) applications
Linearity analysis of CMOS passive mixer
Low power block based FIR filtering cores
Hybrid processor population for odor processing
Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators