yusuke1997/dblp-id-title huggingface dataset:
Workload- and User-aware Battery Lifetime Management for Mobile SoCs
An Asynchronous Synthesis Toolset Using Verilog
Instruction-set extension under process variation and aging effects
Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip
Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs
CHASE: Contract-based requirement engineering for cyber-physical system design
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber"
ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration
Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits
Heterogeneous System-level Specification Using SystemC
Power and performance of read-write aware Hybrid Caches with non-volatile memories
Fast memory footprint estimation based on maximal dependency vector calculation
Interactive presentation: Peripheral-conscious scheduling on energy minimization for weakly hard real-time systems
An algorithm to improve accuracy of criticality in statistical static timing analysis
Lock-free synchronization for dynamic embedded real-time systems
Debugging Low Power Analog Neural Networks for Edge Computing
Are we there yet? Has IP block assembly become as easy as LEGO?
Set Top Box SoC Design Methodology at STMicroelectronics
Acceleration of behavioral simulation on simulation specific machines
General behavioral thermal modeling and characterization for multi-core microprocessor design
A flexible and fast software implementation of the FFT on the BPE platform
Compact structural test generation for analog macros
Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip
The methodological and technological dimensions of technology transfer for embedded systems in aeronautics and space
DroNet: Efficient convolutional neural network detector for real-time UAV applications
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Layout Compaction for Yield Optimization via Critical Area Minimization
Multi-Partner Project: Electric Vehicle Data Acquisition and Valorisation: A Perspective from the OPEVA Project
Combining Simulation and Guided Traversal for the Verification of Concurrent Systems
Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking
PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms
Hard real-time reconfiguration port scheduling
Integrated microfluidic power generation and cooling for bright silicon MPSoCs
Time domain model order reduction by wavelet collocation method
Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
Optimizing data flow graphs to minimize hardware implementation
Cooperative Safety: a Combination of Multiple Technologies
Efficient reliability simulation of analog ICs including variability and time-varying stress
Referencing-in-Array Scheme for RRAM-based CIM Architecture
Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning
HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level
An asynchronous architecture for digital signal processors
Approximation-aware Task Deployment on Asymmetric Multicore Processors
The transprecision computing paradigm: Concept, design, and applications
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture
Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias
Defect tolerance of QCA tiles
Scalable hybrid verification for embedded software
Mapping granularity adaptive FTL based on flash page re-programming
ReSim, a trace-driven, reconfigurable ILP processor simulator
RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends
Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power Control
SPB: Towards Low-Latency CXL Memory via Speculative Protocol Bypassing
A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators
Impact of Magnetic Coupling and Density on STT-MRAM Performance
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
XTENSTORE: Fast Shielded In-memory Key-Value Store on a Hybrid x86-FPGA System
From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions
Optimal control of a grid-connected hybrid electrical energy storage system for homes
System level exploration of a STT-MRAM based level 1 data-cache
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design
Optimizing Assume-Guarantee Contracts for Cyber-Physical System Design
Towards verifying determinism of SystemC designs
DeepRacing: A Framework for Autonomous Racing
Maximizing system performance by balancing computation loads in LSTM accelerators
SAFELOC: Overcoming Data Poisoning Attacks in Heterogeneous Federated Machine Learning for Indoor Localization
Pruning infeasible paths for tight WCRT analysis of synchronous programs
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model
Direct Nonlinear Order Reduction with Variational Analysis
Multi-pumping for resource reduction in FPGA high-level synthesis
Fast and accurate routing demand estimation for efficient routability-driven placement
Flying embedded: the industrial scene and challenges for embedded systems in aeronautics and space
Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance
Online concurrent workload classification for multi-core energy management
Application specific NoC design
Multi-objective distributed run-time resource management for many-cores
OLITS: An Ohm's Law-like traffic splitting model based on congestion prediction
LCache: Log-Structured SSD Caching for Training Deep Learning Models
An Evaluation of Autotuning Techniques for the Compiler Optimization Problems
Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework
Generation of broadside transition fault test sets that detect four-way bridging faults
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
RTL property abstraction for TLM assertion-based verification
Practical Monte-Carlo based timing yield estimation of digital circuits
Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity
The Challenges of Hardware Synthesis from C-Like Languages
WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers
An automated design flow for vibration-based energy harvester systems
BoolGebra: Attributed Graph-Learning for Boolean Algebraic Manipulation
Race to idle or not: balancing the memory sleep time with DVS for energy minimization
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
Power-Efficient Trace Caches
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures
Energy Estimation for Extensible Processors
Capturing and Analyzing IC Design Productivity Metrics
Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities
Thermal-Aware Design and Flow for FPGA Performance Improvement
A high-level analytical model for application specific CMP design exploration
An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation
CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks
Towards trustable storage using SSDs with proprietary FTL
EDA-Aware RTL Generation with Large Language Models
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation
Multicast Parallel Pipeline Router Architecture for Network-on-Chip
A retrospective evaluation of energy-efficient object detection solutions on embedded devices
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
Model-based testing of automotive electronics
Test Data Compression: The System Integrator's Perspective
Novel Pin Assignment Algorithms for Components with Very High Pin Counts
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements
OCCN: A Network-On-Chip Modeling and Simulation Framework
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis
Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior
Variability aware modeling for yield enhancement of SRAM and logic
Automated construction of a cycle-approximate transaction level model of a memory controller
Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems
Accelerating data center decarbonization and maximizing renewable usage with grid edge solutions
OpenC 2 : An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory Macro
Modeling and Analysis for Energy-Driven Computing using Statistical Model-Checking
HAAN: A Holistic Approach for Accelerating Normalization Operations in Large Language Models
Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks
Twine: A Chisel Extension for Component-Level Heterogeneous Design
Dual transitions petri net based modelling technique for embedded systems specification
Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs
Logic analysis and verification of n-input genetic logic circuits
Counterexample-guided SMT-driven optimal buffer sizing
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space
Cross-Layer Approximation For Printed Machine Learning Circuits
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling
Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming
DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters
Relay Propagation Scheme for Testing of MCMs on Large Area Substrates
Towards Safety Verification of Direct Perception Neural Networks
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset
On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems
Advanced 3D Technologies and Architectures for 3D Smart Image Sensors
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Analog IP Testing: Diagnosis and Optimization
AMBEATion: Analog Mixed-Signal Back-End Design Automation with Machine Learning and Artificial Intelligence Techniques
Cantilever-Based Biosensors in CMOS Technology
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes
Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation
Simulation-based design procedure for sub 1V CMOS current reference
Are Our Design for Testability Features Fault Secure?
An Efficient On-Chip Reference Search and Optimization Algorithms for Variation-Tolerant STT-MRAM Read
Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs
A Physical Design Tool for Built-in Self-Repairable Static RAMs
Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture
A Wear Leveling Aware Memory Allocator for Both Stack and Heap Management in PCM-based Main Memory Systems
Tighter integration of BDDs and SMT for Predicate Abstraction
Retargetable generation of code selectors from HDL processor models
Improving Figures of Merit for Quantum Circuit Compilation
Energy efficient MIMO processing: A case study of opportunistic run-time approximations
Run-time deadlock detection in networks-on-chip using coupled transitive closure networks
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network
Fast power loss calculation for digital static CMOS circuits
Far Correlation-based EMA with a precharacterized leakage model
Dynamic Functional Unit Assignment for Low Power
Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips
ReCom: An efficient resistive accelerator for compressed deep neural networks
An Implicit Algorithm for Support Minimization during Functional Decomposition
uHD: Unary Processing for Lightweight and Dynamic Hyperdimensional Computing
Mode-based reconfiguration of critical software component architectures
Efficient Representation and Analysis of Power Grids
Fast low power rule checking for multiple power domain design
A controller testability analysis and enhancement technique
Performance evaluation of wireless NoCs in presence of irregular network routing strategies
CHRT: A criticality- and heterogeneity-aware runtime system for task-parallel applications
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell
Efficient power conversion for ultra low voltage micro scale energy transducers
Embedded randomness and data dependencies design paradigm: Advantages and challenges
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling
Universal number posit arithmetic generator on FPGA
Dynamic cache management in multi-core architectures through run-time adaptation
User-Aware Dynamic Task Allocation in Networks-on-Chip
Hierarchical Modeling and Simulation of Large Analog Circuits
Distributed peak power management for many-core architectures
Re-Examining the Use of Network-on-Chip as Test Access Mechanism
New implementions of predictive alternate analog/RF test with augmented model redundancy
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Systematic design of nanomagnet logic circuits
An efficient method for computing exact path delay fault coverage
Flexible hardware reduction for elliptic curve cryptography in GF(2 m )
Constrained Power Management: Application to a multimedia mobile platform
Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping
Modeling Techniques and Tests for Partial Faults in Memory Devices
PROPHID: a data-driven multi-processor architecture for high-performance DSP
On Automated Trigger Event Generation in Post-Silicon Validation
A conceptual design environment for micromechanisms
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation
dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter
Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508
Pipelets: self-organizing software pipelines for many-core architectures
Reliable Distributed Systems
TagTM - accelerating STMs with hardware tags for fast meta-data access
A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification
Blind Side-Channel SIFA
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture
Analysis and Modeling of Energy Reducing Source Code Transformations
FeReX: A Reconfigurable Design of Multi-Bit Ferroelectric Compute-in-Memory for Nearest Neighbor Search
Pre-synthesis optimization of multiplications to improve circuit performance
Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated Bifurcation
LAD-ECC: Energy-Efficient ECC Mechanism for GPGPUs Register File
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing
A 100 GOPS ASP based baseband processor for wireless communication
Airavat: Improving energy efficiency of heterogeneous applications
A fully-asynchronous low-power framework for GALS NoC integration
Coala: Coalescion-Based Acceleration of Polynomial Multiplication for GPU Execution
Smaller Two-Qubit Circuits for Quantum Communication and Computation
Design Method for Constant Power Consumption of Differential Logic Circuits
MAMUT: Multi-Agent Reinforcement Learning for Efficient Real-Time Multi-User Video Transcoding
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems
Optimizing synchronous systems for multi-dimensional applications
Multimedia Applications of Multiprocessor Systems-on-Chips
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms
Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports
Majority-based Design Flow for AQFP Superconducting Family
Efficient Gröbner basis reductions for formal verification of galois field multipliers
Multi-granularity thermal evaluation of 3D MPSoC architectures
HPXA: A highly parallel XML parser
From Designing Quantum Processors to Large-Scale Quantum Computing Systems
DMRM: Distributed Market-Based Resource Management of Edge Computing Systems
CoMik: A predictable and cycle-accurately composable real-time microkernel
Fault Isolation Using Tests for Non-Isolated Blocks
A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks
Design and analysis of via-configurable routing fabrics for structured ASICs
A circuit-equivalent battery model accounting for the dependency on load frequency
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver
CASTLE: Architecting Assured System-on-Chip Firmware Integrity
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC
Large European Programs in Microelectronic System and Circuit Design
Optical routing for 3D system-on-package
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)
DIET: A Dynamic Energy Management Approach for Wearable Health Monitoring Devices
Probabilistic timing analysis on time-randomized platforms for the space domain
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays
Controlling change propagation and project policies in IC design
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays
Interconnection framework for high-throughput, flexible LDPC decoders
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths
A sensor-assisted self-authentication framework for hardware trojan detection
Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study
Contactless finger and face capturing on a secure handheld embedded device
The energy benefit of level-crossing sampling including the actuator's energy consumption
Optimization of regular expression pattern matching circuits on FPGA
Hacking and protecting IC hardware
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations
GEM-RL: Generalized Energy Management of Wearable Devices using Reinforcement Learning
Crosstalk Alleviation for Dynamic PLAs
Architectures for online error detection and recovery in multicore processors
An Ultra-Low-Power Serial Implementation for Sigmoid and Tanh Using CORDIC Algorithm
Demand code paging for NAND flash in MMU-less embedded systems
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Low Power and Temperature- Resilient Compute-In-Memory Based on Subthreshold-FeFET
The Cyber-Physical Metaverse - Where Digital Twins and Humans Come Together
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Package geometric aware thermal analysis by infrared-radiation thermal images
System Level Verification of Phase-Locked Loop using Metamorphic Relations
Time Properties of the BuST Protocol under the NPA Budget Allocation Scheme
PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform
Prospector: Synthesizing Efficient Accelerators via Statistical Learning
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code
Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning
UIMigrate: Adaptive Data Migration for Hybrid Non-Volatile Memory Systems
Compiler-driven FPGA-area allocation for reconfigurable computing
Distributed hardware matcher framework for SoC survivability
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model
A novel technique to use scratch-pad memory for stack management
Tiny-CFA: Minimalistic Control-Flow Attestation Using Verified Proofs of Execution
BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call
UML 2.0 Profile for Embedded System Design
Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC
TCX: A Programmable Tensor Processor
Streaming BDD manipulation for large-scale combinatorial problems
Learning Assisted Post-Manufacture Testing and Tuning of RRAM-Based DNNs for Yield Recovery
Leveraging variable function resilience for selective software reliability on unreliable hardware
Quantifying hardware security using joint information flow analysis
Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications
Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection
A 150Mbit/s 3GPP LTE Turbo code decoder
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
Multispectral Feature Fusion for Deep Object Detection on Embedded NVIDIA Platforms
Scaling into Ambient Intelligence
Combined system synthesis and communication architecture exploration for MPSoCs
BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture
ChemComp: Compiling and Computing with Chemical Reaction Networks
GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level
Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis
An approach to linear model-based testing for nonlinear cascaded mixed-signal systems
Formal verification of integer multipliers by combining Gröbner basis with logic reduction
Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line
Imperfect linear duplication of combinational circuits
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults
Zebra: Leveraging Diagonal Attention Pattern for Vision Transformer Accelerator
Complementary resistive switch based stateful logic operations using material implication
On ESL verification of memory consistency for system-on-chip multiprocessing