yusuke1997/dblp-id-title huggingface dataset:
Large-scale SOP minimization using decomposition and functional properties
An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Automatic clustering of wafer spatial signatures
SWESS - the middle system of a design automation network
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis
Power grid correction using sensitivity analysis under an RC model
A scan BIST generation method using a markov source and partial bit-fixing
Timing Driven Placement using Physical Net Constraints
Towards a standard hardware description language
Building scalable variational circuit training for machine learning tasks
Commercial gate array physical design automation packages
Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs
SEALing Neural Network Models in Encrypted Deep Learning Accelerators
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Gate-level characterization: foundations and hardware security applications
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic
LoPher: SAT-Hardened Logic Embedding on Block Ciphers
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
Robust IP Watermarking Methodologies for Physical Design
Building block programs for the layout of printed circuit boards utilizing integrated circuit packs (DAPSYS V.2)
On Synthesis-for-Testability of Combinational Logic Circuits
Statheros: Compiler for Efficient Low-Precision Probabilistic Programming
CELTIC - solving the problems of LSI design with an integrated polycell DA system
Quantified Suboptimality of VLSI Layout Heuristics
Random modulo: a new processor cache design for real-time critical systems
Compiler-generated communication for pipelined FPGA applications
Robust design methods for hardware accelerators for iterative algorithms in scientific computing
A True Single-Phase 8-bit Adiabatic Multiplier
Buffer insertion in large circuits with constructive solution search techniques
Refining the SAT decision ordering for bounded model checking
Modeling polyhedral solids bounded by multi-curved parametric surfaces
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources
Performance-aware Wear Leveling for Block RAM in Nonvolatile FPGAs
DeepPUFSCA: Deep learning for Physical Unclonable Function attack based on Side Channel Analysis support
ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems
Nonvolatile memory design based on ferroelectric FETs
An optimum channel-routing algorithm for polycell layouts of integrated circuits
Remembrance of Things Past: Locality and Memory in BDDs
Hybrid Gate-Pulse Model for Variational Quantum Algorithms
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration
Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on the Falcon signature scheme
BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices
System chip test: how will it impact your design?
Flow graph representation
Response Time Analysis and Optimization of DAG Tasks Exploiting Mutually Exclusive Execution
Chain Closure: A Problem in Molecular CAD
The future of system design languages (panel session)
Design partitioning for large-scale equivalence checking and functional correction
Rethinking memory redundancy: optimal bit cell repair for maximum-information storage
New approaches
The CAD-system REGENT
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract)
ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM
GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer Sharing
Multiple fault diagnosis in combinational networks
ATPG for Heat Dissipation Minimization During Scan Testing
User-Centric Energy-Efficient Scheduling on Multi-Core Mobile Devices
A code morphing methodology to automate power analysis countermeasures
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Code compression for low power embedded system design
PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs
Constraint Propagation in an Object-Oriented IC Design Environment
Simulating Improbable Events
Placement algorithms for arbitrarily shaped blocks
Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
SLEUTH - a metal-to-metal audit program in an interactive environment
Improving runtime performance of deduplication system with host-managed SMR storage drives
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration
Applications of a numerical geometry system in engineering
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference
Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs
Design Automation System for ESS in FUJITSU
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification
Towards a user based automated architectural design system: Theory, system operation and future development
Delay-Optimal Technology Mapping by DAG Covering
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent
LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays
Micro Architecture Coverage Directed Generation of Test Programs
FLAG: An FPGA-Based System for Low-Latency GNN Inference Service Using Vector Quantization
Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs
A fast parameter tuning framework via transfer learning and multi-objective bayesian optimization
Synthesis of application-specific memories for power optimization in embedded systems
Efficient fault simulation on many-core processors
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis
Additional papers not available within the printed proceedings
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors
A Gridless Router for Industrial Design Rules
Exact algorithms for delay-bounded steiner arborescences
Partitioning and ordering of logic equations for optimum MOS LSI device layout
On-line operation of CADIC (Computer aided design of integrated circuits)
A methodology to improve timing yield in the presence of process variations
HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference
CarM: hierarchical episodic memory for continual learning
Optimal design of JPEG hardware under the approximate computing paradigm
Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Workshop - technology design rules for design automation
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme
On the efficacy of simplified 2D on-chip inductance models
Resilient Federated Learning on Embedded Devices with Constrained Network Connectivity
Device-Aware Test: A Means to Attack Unmodelled Defects (Invited)
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation
Efficient netlist comparison using hierarchy and randomization
A computer-aided-design system for segmented-folded PLA macro-cells
Adaptive characterization and emulation of delay-based physical unclonable functions using statistical models
Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition
Graph-Guided Transfer Learning to Boost the Efficiency of System-Level Optimization of Analog/Mixed-Signal Circuits
On the topological aspects of the circuit layout problem
Computer Aided Design in D. P. W
Hardware Acceleration of Graph Neural Networks
Fast algorithms for LSI artwork analysis
A Hardware Accelerator for Maze Routing
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks
Concepts of building a design automation system
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components
Retargetable binary utilities
Verification of a Microprocessor Using Real World Applications
Requirement Specification, Analysis and Verification for Autonomous Systems
Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator
Semantics of CAD objects for generalized databases
Xetal-Pro: an ultra-low energy and high throughput SIMD processor
Exploiting data locality in memory for ORAM to reduce memory access overheads
Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008
Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches
AVX Timing Side-Channel Attacks against Address Space Layout Randomization
Efficient State Classification of Finite State Markov Chains
SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism
A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer
Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
Placement algorithm by partitioning for optimum rectangular placement
NVSim-VX s : an improved NVSim for variation aware STT-RAM simulation
Requirement-based design methods for adaptive communications links
An iterative algorithm for placement and assignment of integrated circuits
ChaosINTC: A Secure Interrupt Management Mechanism against Interrupt-based Attacks on TEE
On using control signals for word-level identification in a gate-level netlist
Scan-BIST based on transition probabilities
Hyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM/SRAM Memory
MADMACS: a new VLSI layout macro editor
Remote Atomic Extension (RAE) for Scalable High Performance Computing
Theory-Specific Proof Steps Witnessing Correctness of SMT Executions
Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments
Multi-vendor Tool Integration Experiences (Panel Abstract)
FlexLevel: a novel NAND flash storage system design for LDPC latency reduction
Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing
A workstation-mixed model circuit simulator
In-field aging measurement and calibration for power-performance optimization
Automatic Operator Configuration in the Synthesis of Pipelined Architectures
An approach to placement-coupled logic replication
Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum Autoencoders
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs
Segregation by primary phase factors: a full-wave algorithm for model order reduction
C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs
Guess, solder, measure, repeat: how do I get my mixed-signal chip right?
Best-effort computing: re-thinking parallel software and hardware
Locality aware memory assignment and tiling
TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer
A concept for the editing of hardware resulting in an automatic hardware-editor
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Compact domain-specific co-processor for accelerating module lattice-based KEM
Cognitive radio techniques for wide area networks
The design and implementation of fault insertion capabilities for ISPS
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
INVITED: kCC-Net for Compression of Biomedical Image Segmentation Networks
S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function
CoExe: An Efficient Co-execution Architecture for Real-Time Neural Network Services
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits
Asymmetric Predictive Testing for Aging in SRAMs
Response time analysis for dynamic priority scheduling in ROS2
Timing Driven Placement Using Complete Path Delays
Panel: What Drives EDA Innovation?
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis
Statistical reliability analysis under process variation and aging effects
Restructure-Tolerant Timing Prediction via Multimodal Fusion
One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors
Optimizing quantum circuit placement via machine learning
Critical Path Minimization Using Retiming and Algebraic Speed-Up
Efficient Layout Hotspot Detection via Binarized Residual Neural Network
Near-threshold operation for power-efficient computing?: it depends..
Modular domain-specific implementation and exploration framework for embedded software platforms
Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997
Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Towards a more physical approach to gate modeling for timing, noise, and power
0.18m CMOS and Beyond
Faster symmetry discovery using sparsity of symmetries
BlueSeer: AI-driven environment detection via BLE scans
Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power
GAMMA: a fast prototype design, build, and test process
Speedpath analysis based on hypothesis pruning and ranking
A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip
An Efficient algorithm for Microword Length Minimization
Optimizing windowed arithmetic for quantum attacks against RSA-2048
SAGA: An Experimental Silicon Assembler
Experience with Image Compression Chip Design using Unified System Construction Tools
Automatic Synthesis of Boolean Equations Using Programmable Array Logic
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM
Nutcracker: An Efficient and Intelligent Channel Spacer
Keeping hot chips cool: are IC thermal problems hot air?
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
HDSuper: Algorithm-Hardware Co-design for Light-weight High-quality Super-Resolution Accelerator
Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving
A simulation program for monte carlo analysis and design
Late Breaking Results: Enabling Containerized Computing and Orchestration of ROS-based Robotic SW Applications on Cloud-Server-Edge Architectures
Sphinx: A High-Performance Hybrid Index for Disaggregated Memory With Succinct Filter Cache
ORCA a Sea-of-Gates Place and Route System
Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique
Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment
Resynthesis of Multi-Phase Pipelines
BRIC: Locality-based Encoding for Energy-Efficient Brain-Inspired Hyperdimensional Computing
Analytical Placement: A Linear or a Quadratic Objective Function?
Yield of VLSI circuits: myths vs. reality (panel)
Scheduling and Binding Algorithms for High-Level Synthesis
BNN-YEO: an efficient Bayesian Neural Network for yield estimation and optimization
C3-Flow: Compute Compression Co-Design Flow for Deep Neural Networks
Leveraging Critical Proof Obligations for Efficient IC3 Verification
Scalable selector architecture for x-tolerant deterministic BIST
Embedded Application Design Using a Real-Time OS
Ares: High Performance Near-Storage Accelerator for FHE-based Private Set Intersection
PatterNet: explore and exploit filter patterns for efficient deep neural networks
A discussion of CDLI, a computer description language and associated design aid systems
Representation and generation of rectangular dissections
Statistical ordering of correlated timing quantities and its application for path ranking
Non-gridded graphic input
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks
Accelerating Sparse LU Factorization with Density-Aware Adaptive Matrix Multiplication for Circuit Simulation
Accurate phase-level cross-platform power and performance estimation
Technology Decomposition and Mapping Targeting Low Power Dissipation
PASS: priority assignment of real-time tasks with dynamic suspending behavior under fixed-priority scheduling
A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits
Laser Shield: a Physical Defense with Polarizer against Laser Attacks on Autonomous Driving Systems
VHSIC hardware description (VHDL) development program
Design Data Management in a CAD Framework Environment
Analysis and Design of Latch-Controlled Synchronous Digital Circuits
Network Synthesis for Database Processing Units
Correct-by-construction layout-centric retargeting of large analog designs
Digital Receiver Design Using VHDL Generation from Data Flow Graphs
Template Style Considerations for Sea-of-Gates Layout Generation
High performance dummy fill insertion with coupling and uniformity constraints
Parallel execution of AUTOSAR legacy applications on multicore ECUs with timed implicit communication
Performance-driven Placement of Cell Based IC's
Government interest and involvement in design automation development (Position paper for the Panel Discussion)
SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time Systems
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration
Watermarking of SAT using Combinatorial Isolation Lemmas
Dynamic Local Usage: An Accurate Model for Usage of Tile-Internal Wiring in Global Routing
Fast timing-model independent buffered clock-tree synthesis
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis
Feasibility study of an integrated program for aerospace vehicle design (IPAD)
A Top-Down Design Environment for Developing Pipelined Datapaths
A New Approach to the Rectilinear Steiner Tree Problem
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
Universal logic modules based on double-gate carbon nanotube transistors
COSMOS: A Compiled Simulator for MOS Circuits
Statistical Pattern Based Modeling of GPU Memory Access Streams
Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection
Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System
A Multiprocessor DSP System Using PADDI-2
Subwavelength Lithography and Its Potential Impact on Design and EDA
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
Reducing Bit Writes in Non-volatile Main Memory by Similarity-aware Compression
ChatCPU: An Agile CPU Design and Verification Platform with LLM
Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices
Green data centers and hot chips
Test Program Generation for Functional Verification of PowerPC Processors in IBM
Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017
Global routing and track assignment for flip-chip designs
Redundant via insertion for multiple-patterning directed-self-assembly lithography
DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis
Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture
GS-TG: 3D Gaussian Splatting Accelerator with Tile Grouping for Reducing Redundant Sorting while Preserving Rasterization Efficiency
Effective zero compression on ReRAM-based sparse DNN accelerators
Local Bayesian Optimization For Analog Circuit Sizing
Designing a system on a chip
TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering
Magic's incremental design-rule checker
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications
Designing with LCD: language for computer design
Using embedded infrastructure IP for SOC post-silicon verification
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing
Government interest and involvement in DA from the Sandia viewpoint
Computer-Aided Design of Free-Space Opto-Electronic Systems
LEQA: latency estimation for a quantum algorithm mapped to a quantum circuit fabric
FlexWAFE - A High-end Real-Time Stream Processing Library for FPGAs
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Verification and optimization for LSI & PCB layout
MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses
Scaling Laws of Graph Neural Networks for Atomistic Materials Modeling
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP
A formal design verification system based on an automated reasoning system
Automated interpretation and reduction of in-vehicle network traces at a large scale
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2
Scheduling for Functional Pipelining and Loop Winding
MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar Processors
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware
Towards scalable flow and context sensitive pointer analysis
Emerald: A bus style designer
The scan line approach to design rules checking: Computational experiences
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration
On-chip deep neural network storage with multi-level eNVM
Lightning Talk: Efficiency and Programmability of DNN Accelerators and GPUs