yusuke1997/dblp-id-title huggingface dataset:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
UpTime: Towards Flow-based In-Memory Computing with High Fault-Tolerance
Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems
Thermal aware task sequencing on embedded processors
Computer aided design for analog applications (panel session): an assessment
Using Complementation and Resequencing to Minimize Transitions
Low-cost On-Chip Structures for Combating Die and IC Recycling
Introduction to an LSI test system
Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors
Miss reduction in embedded processors through dynamic, power-friendly cache design
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections
An algorithm for automatic line routing on Schematic Drawings
CVMAX: Accelerator Architecture with Polar Form Multiplication for Complex-Valued Neural Networks
On the Design of Novel Attention Mechanism for Enhanced Efficiency of Transformers
iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development
Partitioning by Probability Condensation
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents
Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips
On designing via-configurable cell blocks for regular fabrics
A systematic method for functional unit power estimation in microprocessors
A test methodology for large logic networks
CYCLONE: automated design and layout of RF LC-oscillators
An integrated design for testability and automatic test pattern generation system: An overview
IP-based Design Methodology
The software engineering technique of data hiding as applied to multi-level model implementation of logical devices in digital simulation
A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks
The IBM VHDL Design System
Stalker: A Framework to Analyze Fragility of Cryptographic Libraries under Hardware Fault Models
Tradeoffs and choices for emerging SoCs in high-end applications
A Technique for Synthesizing Distributed Burst-mode Circuits
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis
Segmented Channel Routing
A general purpose design automation file system
Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench
An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models
Computational Kernels and their Application to Sequential Power Optimization
Synchronous Logic Simulator
Battle Against Fluctuating Quantum Noise: Compression-Aided Framework to Enable Robust Quantum Neural Network
Unified Shapes Checker - a checking tool for LSI
Functional fault modeling and simulation for VLSI devices
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs
Some computer-aided approaches to housing
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints
SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †
GraphAccel: An In-Storage Accelerator for Efficient Graph-Based Vector Similarity Search Using Page Packing and Speculative Search Optimization
TED: A Graphical Technology Description Editor
Digital logic simulation models and evolving technology
AGD: A Learning-based Optimization Framework for EDA and its Application to Gate Sizing
Descriptive databases in some design/manufacturing environments
Initial design concepts for an advanced design automation system
A New Hypergraph Based Rip-Up and Reroute Strategy
Graphic Data Processing
Department of architecture university of illinois
CDB: critical data backup design for consumer devices with high-density flash based hybrid storage
A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model
Proceedings of the 6th annual Design Automation Conference, DAC '69, Miami Beach, Florida, USA, June 8-12, 1969
SCALD: Structured Computer-Aided Logic Design
Cache modeling in probabilistic execution time analysis
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead
ALI: A procedural language to describe VLSI layouts
GPU-based parallelization for fast circuit optimization
Massively Parallel Switch-Level Simulation: A Feasibility Study
CNN-inspired analytical global placement for large-scale heterogeneous FPGAs
Development concerns for a software design quality expert system
Manifestations of Heterogeneity in Hardware/Software Co-Design
Spatial allocation in design and planning
3D-CIMlet: A Chiplet Co-Design Framework for Heterogeneous In-Memory Acceleration of Edge LLM Inference and Continual Learning
Automated design of open web steel joists
Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application
Probabilistic regression suites for functional verification
The application of program verification techniques to hardware verification
BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System
Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design
REAP: Runtime Energy-Accuracy Optimization for Energy Harvesting IoT Devices
"Error free MOS/LSI design system"
Exploring locking & partitioning for predictable shared caches on multi-cores
Failure Recovery in the MICON System
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC
Polaris: Polarity propagation algorithm for combinational logic synthesis
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems
Design Version Management in the GARDEN Framework
Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis
A Semi-Custom Design Flow in High-Performance Microprocessor Design
On Quality Trade-off Control for Approximate Computing Using Iterative Training
Time Multiplexing via Circuit Folding
Tutorial on High-Level Synthesis
Formal modeling and reasoning for reliability analysis
A Hierarchical Approach Test Vector Generation
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification
Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier
Effective data management for VLSI design
RT-MDM: Real-Time Scheduling Framework for Multi-DNN on MCU Using External Memory
A cross-layer approach to cognitive computing: invited
Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective
A fast approach for static timing analysis covering all PVT corners
Address assignment combined with scheduling in DSP code generation
Vortex: variation-aware training for memristor X-bar
Optimality study of resource binding with multi-Vdds
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation
Smart hill climbing for agile dynamic mapping in many-core systems
METRICS: a system architecture for design process optimization
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
Integrated power management in IoT devices under wide dynamic ranges of operation
A unified optimization framework for equalization filter synthesis
CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and Scheduling
Multiple Si layer ICs: motivation, performance analysis, and design implications
Computer aided (CA) tools integration and related standards development (panel session)
A HW/SW Co-Design of Video Dehazing Accelerator Using Decoupled Local Atmospheric Light Prior
Functional Verification Methodology of Chameleon Processor
Factored Radix-8 Systolic Array for Tensor Processing
Laying the power and ground wires on a VLSI chip
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems
FACET: A CAE System for RF Analogue Simulation Including Layout
Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection
Designing logic circuits for probabilistic computation in the presence of noise
A survey of the state-of-the-art of design automation an invited presentation
Are EDA Platform Preferences About to Shift? (Panel Abstract)
Accurate pre-layout estimation of standard cell characteristics
Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms
The Case for Low-Power Photonic Networks on Chip
Position statement - CAD for VLSI
BHDL: A Lucid, Expressive, and Embedded Programming Language and System for PCB Designs
Hardware Emulation for Functional Verification of K5
CPS foundations
Multi-Agent Yield Analysis For Circuit Design
Partial Scan with Pre-selected Scan Signals
Mining global constraints for improving bounded sequential equivalence checking
3D-Flow: Flow-based Standard Cell Legalization for 3D ICs
Incorporating Design Schedule Management into a Flow Management System
A machine learning based hard fault recuperation model for approximate hardware accelerators
Building End-to-End IoT Applications with QoS Guarantees
AutoDCIM: An Automated Digital CIM Compiler
3-D stacked die: now or future?
RE3: Finding Refinement Relations with Relational Mapping Abstraction
Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology
Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations
The day Sherlock Holmes decided to do EDA
The DT-Model: High-Level Synthesis Using Data Transfers
On effective and efficient in-field TSV repair for stacked 3D ICs
High-performance placement for large-scale heterogeneous FPGAs with clock constraints
Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System
Software synthesis from synchronous specifications using logic simulation techniques
FLAW: FPGA lifetime awareness
A new philosophy for interconnection on multilayer boards
SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits
Computer expansion of Boolean expressions
A software system for Automated Placement And Wiring of LSI chips
Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination
Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling
Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design
An Automatic Rectilinear Partitioning Procedure for Standard Cells
Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
3D heterogeneous system integration: application driver for 3D technology development
Implications of technology scaling on leakage reduction techniques
Oscillation Control in Logic Simulation using Dynamic Dominance Grahps
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint
Functional testing of digital systems
Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic
Energy-scalable OFDM transmitter design and control
Workstations (panel discussion): a complete solution to the VLSI designer?
UniCAIM: A Unified CAM/CIM Architecture with Static-Dynamic KV Cache Pruning for Efficient Long-Context LLM Inference
BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors
Use of an on-line, time-shared graphics system to design and document printed circuit boards
Simulation knowledge extraction and reuse in constrained random processor verification
Chip Multi-Processor Generator
Dynamic effort scaling: managing the quality-efficiency tradeoff
A stochastic approach To power grid analysis
A New Hierarchical Layout Compactor Using Simplified Graph Models
A New Structural Pattern Matching Algorithm for Technology Mapping
Hardware/Software Co-Simulation
Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations
The Minimization and Decomposition of Interface State Machines
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints
Data preparation and entry for computer-aided mapping
Partial Scan Design Based on Circuit State Information
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Cyber-physical energy systems: focus on smart buildings
Fault Sneaking Attack: a Stealthy Framework for Misleading Deep Neural Networks
TSN-Builder: Enabling Rapid Customization of Resource-Efficient Switches for Time-Sensitive Networking
Proceedings of the 8th Design Automation Workshop, DAC '71, Atlantic City, NJ, USA, June 28-30, 1971
GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs
Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer
On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage
Future of design automation (Position Paper)
Realistic Fault Modeling for VLSI Testing
Fast illegal state identification for improving SAT-based induction
Deep Reorganization: Retaining Residuals in TinyML
Delay and Area Optimization in Standard-Cell Design
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning
Design aids for the simulation of bipolar gate arrays
Automating hardware security property generation: invited
High-level simulation of substrate noise generation including power supply noise coupling
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
A language for a scientific and engineering database system
DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions
Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded Systems
Towards enhancing analog circuits sizing using SMT-based techniques
VERDI: A computer aided design system for development and city planning
Many-core design from a thermal perspective
An overview of VHDL language and technology
L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network
The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014
Dr. BFS: Data Centric Breadth-First Search on FPGAs
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits
DSA-friendly detailed routing considering double patterning and DSA template assignments
On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
A depth-first branch-and-bound algorithm for optimal PLA folding
Invited - Cross-layer approaches for soft error modeling and mitigation
Verifying SystemC using stateful symbolic simulation
Structure preserving reduction of frequency-dependent interconnect
Design automation challenges for the 1970's
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects
Prive-HD: Privacy-Preserved Hyperdimensional Computing
Some Computer Aided Engineering System design principles
DTR: A Defect-Tolerant Routing Algorithm
Sparse matrix computations on manycore GPU's
Invited: Trainable Discrete Feature Embeddings for Quantum Machine Learning
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy
Self-aligned double patterning decomposition for overlay minimization and hot spot detection
LECSIM: A Levelized Event Driven Compiled Logic Simulation
SKILL: A CAD System Extension Language
Using a computer aided graphics system to help design and draft automotive components
Efficient compression and application of deterministic patterns in a logic BIST architecture
CAD-based Security, Cryptography, and Digital Rights Management
Mckeycutter: A High-throughput Key Generator of Classic McEliece on Hardware
Speed Up of Test Generation Using High-Level Primitives
PLATYPUS: a PLA test pattern generation tool
An instruction-level functionally-based energy estimation model for 32-bits microprocessors
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories
Efficient Simulation of Bipolar Digital ICs
Using a High-Level Test Generation Expert System for Testing In-Car Networks
Array Optimization for VLSI Synthesis
Energy-aware deterministic fault tolerance in distributed real-time embedded systems
Executive Perspective and Vision of the Future of EDA (Panel)
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Static analysis of transaction-level models
The electronics engineer's design station
A general graph based pessimism reduction framework for design optimization of timing closure
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks
Design tool chain for cyber-physical systems: lessons learned
GPart: A GNN-Enabled Multilevel Graph Partitioner
Not so fast my friend: is near-threshold computing the answer for power reduction of wireless devices?
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation
Reducing DRAM Access Latency via Helper Rows
The Titanic: what went wrong!
An Efficient Equivalence Checker for Combinational Circuits
A second chance at automation as a design tool
Design automation status in Japan
Learning Temporal Specifications from Imperfect Traces Using Bayesian Inference
MILLION: MasterIng Long-Context LLM Inference Via Outlier-Immunized KV Product QuaNtization
Will your bridge stand the load? (Position Paper)
Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability
Towards a formally verified hardware root-of-trust for data-oblivious computing
Data structures for CAD object description
TCG-S: orthogonal coupling of P * -admissible representations for general floorplans
TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead
Profile-based optimal intra-task voltage scheduling for hard real-time applications
Optimization of the PLA area
Quality-of-Service for a High-Radix Switch
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory
Hybrid STT-CMOS designs for reverse-engineering prevention
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
Worst-case dynamic power distribution network noise prediction using convolutional neural network
Cocktail: Learn a Better Neural Network Controller from Multiple Experts via Adaptive Mixing and Robust Distillation
UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling
Redundant Operator Creation: A Scheduling Optimization Technique
Advances in Functional Abstraction from Structure
RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks
A low power unsupervised spike sorting accelerator insensitive to clustering initialization in sub-optimal feature space
Test-Set Preserving Logic Transformations
Performance of interconnection rip-up and reroute strategies
Post-Layout Optimization for Deep Submicron Design
Design automation in network computers
Tailor: removing redundant operations in memristive analog neural network accelerators
Computer simulation of foliage shading in building energy loads
Delay Fault Models and Test Generation for Random Logic Sequential Circuits
CLOVER: A Timing Constraints Verification System
Symbolic manipulation of Boolean functions using a graphical representation
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design
HardScope: Hardening Embedded Systems Against Data-Oriented Attacks
Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-oriented Components
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems
Automatic Insertion of BIST Hardware Using VHDL
Physical Unclonable Functions for Device Authentication and Secret Key Generation
Enabling hard constraints in differentiable neural network and accelerator co-exploration
Embedded hardware and software self-testing methodologies for processor cores
SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture
Heuristic Minimization of BDDs Using Don't Cares
Design Automation Standards - Perspectives from a Down-the-Road End User
O'clock: lock the clock via clock-gating for SoC IP protection
Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage
Synthesis of VLSI systems with the CAMAD design aid
Near-optimal, dynamic module reconfiguration in a photovoltaic system to combat partial shading effects
Bristle Blocks: A silicon compiler
AID: Attesting the Integrity of Deep Neural Networks
Register-transfer level digital design automation: The allocation process
DERA: yet another differential fault attack on cryptographic devices based on error rate analysis
LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding
Run-time voltage hopping for low-power real-time systems
Design space exploration using time and resource duality with the ant colony optimization
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis
GALA - an automatic layout system for high density CMOS gate arrays
Design validation in hierarchical systems
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits
A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs
PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT
Manpower training problems and programs
Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation
Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems
Variation-aware analysis: savior of the nanometer era?
Hierarchical Dataflow Modeling of Iterative Applications
MAGENTA: transaction-based statistical micro-architectural root-cause analysis
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits
A version server for computer-aided design data
An automatic scratch pad memory management tool and MPEG-4 encoder case study
Mechanical design/analysis integration on Apollo workstations
Normalization at the arithmetic bit level
Intellectual Property (Panel Abstract)
Parallel programming: can we PLEASE get it right this time?
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM
Enabling Complex Stimuli in Accelerated Mixed-Signal Simulation
Model order reduction of linear networks with massive ports via frequency-dependent port packing