yusuke1997/dblp-id-title huggingface dataset:
Lower bound on latency for VLIW ASIP datapaths
GHM: A generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems
Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method
A Co-optimization Framework with Multi-layer Constraints for Manufacturability
Timing-safe false path removal for combinational modules
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits
An accurate sparse matrix based framework for statistical static timing analysis
Exploiting Uniform Spatial Distribution to Design Efficient Random Number Source for Stochastic Computing
Reduced Overhead Error Compensation for Energy Efficient Machine Learning Kernels
Heuristic Minimazation of Multiple-Valued Relations
Model-based design of resource-efficient automotive control software
Invited Paper: CMOS 2.0 - Redefining the Future of Scaling
Is wire tapering worthwhile?
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems
Modeling of layout-dependent stress effect in CMOS design
A load balancing inspired optimization framework for exascale multicore systems: A complex networks approach
Efficient algorithms for buffer insertion in general circuits based on network flow
Enhancing DNN Accelerator Integrity via Selective and Permuted Recomputation
High-Performance, Low-Power Resonant Clocking: Embedded tutorial
New placement prediction and mitigation techniques for local routing congestion
A framework for testing core-based systems-on-a-chip
Partial Differential Equation Acceleration by Exploiting Value Similarity
Bounds on net lengths for high-speed PCB
Worst-case analysis of discrete systems
A redesign technique for combinational circuits based on gate reconnections
Minimum-Area Sequential Budgeting for FPGA
Multi-level synthesis for safe replaceability
PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM
2D data locality: definition, abstraction, and application
Design space exploration of multi-output logic function approximations
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base
A jumper insertion algorithm under antenna ratio and timing constraints
Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning Accelerators
Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysis
A Behavioral Representation for Nyquist Rate A/D Converters
Circuit reliability: From Physics to Architectures: Embedded tutorial paper
Accelerating Genome Alignment Pipeline with In-NAND Search Technology and Group Testing Techniques
RRAM Based Lightweight User Authentication
Macro-aware row-style power delivery network design for better routability
Foveated HDR: Efficient HDR Content Generation on Edge Devices Leveraging User's Visual Attention
Efficient Task Transfer for HLS DSE
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo
Interconnect design for deep submicron ICs
DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous Platforms
Efficient statistical timing analysis through error budgeting
Non-linear Quantification Scheduling in Image Computation
Techniques for crosstalk avoidance in the physical design of high-performance digital systems
Integrated floorplanning and interconnect planning
Fast Analysis and Optimization of Power/Ground Networks
Static statistical timing analysis for latch-based pipeline designs
AntiSIFA-CAD: A Framework to Thwart SIFA at the Layout Level
Symbolic analysis of large analog circuits with determinant decision diagrams
Layer minimization of escape routing in area array packaging
Replication for logic bipartitioning
LP based cell selection with constraints of timing, area, and power consumption
A General Logic Synthesis Framework for Memristor-based Logic Design
Power analysis of embedded software: a first step towards software power minimization
An enhanced multilevel routing system
Heuristics for Million-scale Two-level Logic Minimization
Regularity extraction via clan-based structural circuit decomposition
An Automata-Theoretic Approach to Behavioral Equivalence
Accelerating N-Bit Operations over TFHE on Commodity CPU-FPGA
An OCV-Aware Clock Tree Synthesis Methodology
A materials- and devices-centric approach to neuromorphic computing
Practical applications of an efficient time separation of events algorithm
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects
Power Grid Fixing for Electromigration-induced Voltage Failures
UML for ESL design: basic principles, tools, and applications
A dormant subcircuit model for maximizing iteration latency
Mixed Signal DFT: A Concise Overview
Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis
Using a single input to support multiple scan chains
Optimizing yield in global routing
Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm
An efficient data reuse strategy for multi-pattern data access
Temperature-aware test scheduling for multiprocessor systems-on-chip
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
High-density reachability analysis
Multilevel tree fusion for robust clock networks
Design of experiments in BDD variable ordering: lessons learned
Simultaneous design and placement of multiplexed chemical processing systems on microchips
The Sizing Rules Method for Analog Integrated Circuit Design
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-Experts
Hybrid Structured Clock Network Construction
Exhaustive simulation need not require an exponential number of tests
Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper)
New methods for speeding up computation of Newton updates in harmonic balance
Testability-Preserving Circuit Transformations
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies
Constraint Satisfaction for Relative Location Assignment and Scheduling
Definition and assignment of complex data-paths suited for high throughput applications
A visual design environment
Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach
COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing
Faster, parametric trajectory-based macromodels via localized linear reductions
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Synthesis of manufacturable analog circuits
Binary decision diagrams and beyond: enabling technologies for formal verification
Module selection and data format conversion for cost-optimal DSP synthesis
Performance optimization of elastic systems using buffer resizing and buffer insertion
A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis
Technology mapping for field-programmable gate arrays using integer programming
Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper
Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses
Cross-program design space exploration by ensemble transfer learning
Security of IoT systems: design challenges and opportunities
Temperature aware task sequencing and voltage scaling
Simultaneous short-path and long-path timing optimization for FPGAs
Exploring aging deceleration in FinFET-based multi-core systems
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
Fault injection attack on deep neural network
Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG
Algorithm selection: a quantitative computation-intensive optimization approach
Interface and cache power exploration for core-based embedded system design
Accelerating Framework of Transformer by Hardware Design and Model Compression Co-Optimization
Delay optimal partitioning targeting low power VLSI circuits
Challenges in post-silicon validation of high-speed I/O links
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning
M3: Mamba-assisted Multi-Circuit Optimization via Model-based RL with Effective Scheduling
A disturb-alleviation scheme for 3D flash memory
EMAT: an efficient multi-task architecture for transfer learning using ReRAM
Incremental placement for layout driven optimizations on FPGAs
QPulseLib: Accelerating the Pulse Generation of Quantum Circuit with Reusable Patterns
Mixed-cell-height detailed placement considering complex minimum-implant-area constraints
Hardware-accelerated data acquisition and authentication for high-speed video streams on future heterogeneous automotive processing platforms
Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
Implicit State Enumeration of Finite State Machines Using BDDs
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems
EI-PIT: A Parallel-in-Time Exponential Integrator Method for Transient Linear Circuit Simulation
AMBER: adaptive energy management for on-chip hybrid video memories
Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper)
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
Learning Based Compact Thermal Modeling for Energy-Efficient Smart Building Management: (invited)
GRPlacer: Improving routability and wire-length of global routing with circuit replacement
A proof-carrying based framework for trusted microprocessor IP
Slack matching mode-based asynchronous circuits for average-case performance
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing
NoCEE: energy macro-model extraction methodology for network on chip routers
Reliable system design: models, metrics and design techniques
Validation and test generation for oscillatory noise in VLSI interconnects
Towards support for design description languages in EDA framework
EPiCarbon: A Carbon Modeling Tool for Electro-Photonic Accelerators
Timing analysis based on primitive path delay fault identification
AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
Single-Qubit Gates Matter for Optimising Quantum Circuit Depth in Qubit Mapping
A Layout-Aware Synthesis Methodology for RF Circuits
Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning
Precise timing verification of logic circuits under combined delay model
Constrained floorplan design for flexible blocks
Counterexample-Guided Choice of Projections in Approximate Symbolic Model Checking
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design
Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinates
Non-volatile Memory Technologies for Edge AI Applications
Architectural partitioning of control memory for application specific programmable processors
Wire density driven global routing for CMP variation and timing
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization
HyperFuzzing for SoC Security Validation
Offshore oil spill monitoring and detection: Improving risk management for offshore petroleum cyber-physical systems: (Invited paper)
FunState - an internal design representation for codesign
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration
Analysis and optimization of power-gated ICs with multiple power gating configurations
Uncertainty quantification for integrated circuits: stochastic spectral methods
Function inlining under code size constraints for embedded processors
Simulation Based Test Generation for Scan Designs
CAD computation for manufacturability: can we save VLSI technology from itself?
Invited Paper: Mindful AI for Pervasive Health and Wellbeing (PHW)
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
Designing with Deception: ML- and Covert Gate-Enhanced Camouflaging to Thwart IC Reverse Engineering
Shaping interconnect for uniform current density
Temperature aware microprocessor floorplanning considering application dependent power load
Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with Macros
A layout dependent full-chip copper electroplating topography model
SAFF: Scalable Acceleration of GNN-based Machine Learning Force Fields using Tensor-Aware Hardware for Molecular Simulation
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator
Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems
An automated SAT-based method for the design of on-chip bit-flip detectors
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs
Low power state assignment targeting two-and multi-level logic implementations
Interpolant generation without constructing resolution graph
Quadratic zero-one programming based synthesis of application specific data paths
Increasing data-bandwidth to instruction-set extensions through register clustering
Efficient simulation of EM side-channel attack resilience
Compacting test vector sets via strategic use of implications
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
Global routing revisited
Parallel PLA fault simulation based on Boolean vector operations
Double-gate SOI devices for low-power and high-performance applications
Buffer insertion under process variations for delay minimization
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs
PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction
State assignment for multilevel logic using dynamic literal estimation
Partitioning of Functional Models of Synchronous Digital Systems
Global signaling over lossy transmission lines
Potter: A Parallel Overlap-Tolerant Router for UltraScale FPGAs
A network-flow approach to timing-driven incremental placement for ASICs
Impact of circuit-level non-idealities on vision-based autonomous driving systems
A Usable Circuit Optimizer for Designers
Gate sizing and device technology selection algorithms for high-performance industrial designs
Characterization and modeling of graphene field-effect devices
A safety and security architecture for reducing accidents in intelligent transportation systems
Operating system scheduling for efficient online self-test in robust systems
Specification and verification of VLSI systems
Improved Logic Synthesis Algorithms for Table Look Up Architectures
Real-time operating systems for embedded computing
Tensor Methods for Generating Compact Uncertainty Quantification and Deep Learning Models
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
CMOS-MEMS integration: why, how and what?
Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet
DiffCCD: Differentiable Concurrent Clock and Data Optimization
The critical path for multiple faults
SNO: Securing Network Function Offloading on FPGA-based SmartNICs in Untrusted Clouds
A SimPLR method for routability-driven placement
Embedded memories in system design - from technology to systems architecture
Parallel Non-Integer Multiple-Cell-Height Node Remapping
NEMESIS: A software approach for computing in presence of soft errors
An Agile Framework for Efficient LLM Accelerator Development and Model Inference
An algorithm for synthesis of system-level interface circuits
Simulation Coverage Enhancement Using Test Stimulus Transformations
Advanced datapath synthesis using graph isomorphism
The design of a cache-friendly BDD library
Variable Ordering and Selection for FSM Traversal
Latency Effects of System Level Power Management Algorithms
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
Thermal-induced leakage power optimization by redundant resource allocation
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools
3D DRC: Design Rule Checking for 3D IC with U-Net-based Non-Manhattan Optimization
Don't Care Sequences and the Optimization of Interacting Finite State Machines
Operation chaining asynchronous pipelined circuits
Protecting Endpoint Devices in IoT Supply Chain
FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis Method
A Hierarchical Methodology to Improve Channel Routing by Pin Permutation
On testable multipliers for fixed-width data path architectures
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Recent research development in flip-chip routing
Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area Overhead
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA
Fine-Granular Computation and Data Layout Reorganization for Improving Locality
A unified theory of timing budget management
Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systems
A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories
A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures
ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest
Fast simulation of VLSI interconnects
Small-delay-fault ATPG with waveform accuracy
Post-Processor for Data Path Synthesis Using Multiport Memories
To SAT or not to SAT: Ashenhurst decomposition in a large scale
A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS
ILP-Driven FPGA Multiplier Synthesis: A Scalable Framework for Area-Latency Co-Optimization
EVE: Environmental Adaptive Neural Network Models for Low-Power Energy Harvesting System
KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase Decomposition
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Mitigating FPGA interconnect soft errors by in-place LUT inversion
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations
Challenges in Power-Ground Integrity
A video driver system designed using a top-down, constraint-driven methodology
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)
Attacks on Image Sensors
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
Noise propagation and failure criteria for VLSI designs
Resilient microprocessor design for improving performance and energy efficiency
Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
DA Vision 2015: From Here to Eternity
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading
Clustering Techniques for Register Optimization During Scheduling Preprocessing
GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing
DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision
Encasing block ciphers to foil key recovery attempts via side channel
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization
ATPG-based logic synthesis: an overview
A new algorithm for the reduction of incompletely specified finite state machines
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
Delay and bus current evaluation in CMOS logic circuits
Reencoding for cycle-time minimization under fixed encoding length
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction
Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits
Automatic generalized phase abstraction for formal verification
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts
Exploration of Timing and Higher-Energy Attacks on Quantum Random Access Memory
The future of clock network synthesis
Instruction set mapping for performance optimization
DREAMS: DFM rule EvAluation using manufactured silicon
CSP: Comprehensively-Sparsified Preconditioner for Efficient Nonlinear Circuit Simulation
Automated detection and verification of parity-protected memory elements
Addressing high frequency effects in VLSI interconnects with full wave model and CFH
NOISY: an electrical noise checker for ULSI
New channel segmentation model and associated routing algorithm for high performance FPGAs
Generating sparse partial inductance matrices with guaranteed stability
Design of a set-top box system on a chip (abstract)
Statistical bipolar circuit design using MSTAT
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
Efficient model reduction of interconnect via approximate system gramians
Accelerating Fully Homomorphic Encryption by Bridging Modular and Bit-Level Arithmetic
Analysis and modeling of CD variation for statistical static timing
Behavior tables: a basis for system representation and transformational system synthesis
A cell-based power estimation in CMOS combinational circuits
The synthesis of combinational logic to generate probabilities
Automating post-silicon debugging and repair
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design
Optimal memoryless encoding for low power off-chip data buses
Parallel logic/fault simulation of VLSI array logic
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality
AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Accelerators
Dynamic variable ordering for ordered binary decision diagrams
Clock Gating Synthesis of Netlist with Cyclic Logic Paths
Electrically driven optical proximity correction based on linear programming
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning
A Data Flow Based Architecture for CAD Frameworks
Fusion of Global Placement and Gate Sizing with Differentiable Optimization
Computer-aided design of electrical energy systems
ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks