yusuke1997/dblp-id-title huggingface dataset:
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design
A Fast Algorithm for Performance-Driven Placement
On timing-independent false path identification
IC Power Distribution Challenges
Resolving the Trilemma in Logic Encryption
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite
Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary search
Post-silicon performance modeling and tuning of analog/mixed-signal circuits via Bayesian Model Fusion
Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis
Statistical defect-detection analysis of test sets using readily-available tester data
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory
Low Power System Scheduling and Synthesis
Assignment of global memory elements for multi-process VHDL specifications
Exploring Target Function Approximation for Stochastic Circuit Minimization
Quantitative Verification and Design Space Exploration under Uncertainty with Parametric Stochastic Contracts
LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism
BoardPUF: Physical Unclonable Functions for Printed Circuit Board Authentication
Cost-free scan: a low-overhead scan path design methodology
Importance of volume discretization of single and coupled interconnects
Synthesis of custom processors based on extensible platforms
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
High throughput pipelined data path synthesis by conserving the regularity of nested loops
PPV-HB: harmonic balance for oscillator/PLL phase macromodels
Temperature-aware leakage minimization technique for real-time systems
RISA: accurate and efficient placement routability modeling
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
STMC: Small-Tile Multiple-Copy Compilation for Reliable Measurement-Based Quantum Computing
Energy-efficient fault tolerance approach for internet of things applications
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
Analog test metrics estimates with PPM accuracy
DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited Paper
Logic optimization by output phase assignment in dynamic logic synthesis
What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
The approximation scheme for peak power driven voltage partitioning
Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design
Timing budgeting under arbitrary process variations
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks
Interconnect-aware high-level synthesis for low power
ConSmax: Hardware-Friendly Alternative Softmax with Learnable Parameters
A design flow dedicated to multi-mode architectures for DSP applications
Final-value ODEs: Stable numerical integration and its application to parallel circuit analysis
WROXIM: A Network-Level Simulation Platform for Wavelength-Routed Optical Networks-on-Chip
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts
Testability analysis and multi-frequency ATPG for analog circuits and systems
Design for Easily Applying Test Vectors to Improve Delay Fault Coverage
SPM management using Markov chain based data access prediction
Achievable bounds on signal transition activity
Robust estimation of parametric yield under limited descriptions of uncertainty
iMACSIM: A Program for Multi-Level Analog Circuit Simulation
Fast poisson solver preconditioned method for robust power grid analysis
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
Approximation algorithm for the temperature-aware scheduling problem
RTL-to-GDS Design Tools for Monolithic 3D ICs
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints
System-level power estimation using an on-chip bus performance monitoring unit
CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs
Test generation for multiple faults based on parallel vector pair analysis
TransLib: An Extensible Graph-Aware Library Framework for Automated Generation of Transformer Operators on FPGA
A comparison on constrain encoding methods for quantum approximate optimization algorithm
Clock skew scheduling for improved reliability via quadratic programming
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm
A New Linear Placement Algorithm for Cell Generation
Diastolic arrays: throughput-driven reconfigurable computing
Adaptive designs for power and thermal optimization
Hierarchical placement for macrocells: a 'meet in the middle' approach
Miller Factor for Gate-Level Coupling Delay Calculation
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Progress in CMOS-memristor integration
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip
On the Interaction Between Power-Aware FPGA CAD Algorithms
Fast flip-chip power grid analysis via locality and grid shells
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
Topological channel routing
Static compaction using overlapped restoration and segment pruning
Retiming gated-clocks and precharged circuit structures
Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously
Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications
Design of power-efficient approximate multipliers for approximate artificial neural networks
Accurate energy breakeven time estimation for run-time power gating
Enabling deep learning at the IoT edge
Ordering Storage Elements in a Single Scan Chain
CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing
A table look-up MOSFET model for analog applications
Leveraging Weakly-hard Constraints for Improving System Fault Tolerance with Functional and Timing Guarantees
Post-placement voltage island generation
An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines
Emerging reconfigurable nanotechnologies: can they support future electronics?
Open3DFlow: An Open-Source EDA Platform for 3D Chip Design with AI Enhancement
Design space exploration for a UMTS front-end exploiting analog platforms
Potential Slack: An Effective Metric of Combinational Circuit Performance
Built-in self-test and fault diagnosis of fully differential analogue circuits
VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs
A simple implementation of determinant decision diagram
Efficient decoupling capacitance budgeting considering operation and process variations
Timing ECO optimization via Bézier curve smoothing and fixability identification
MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs
GPU-accelerated Critical Path Generation with Path Constraints
Electromigration Immortality Check considering Joule Heating Effect for Multisegment Wires
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs
On the escape routing of differential pairs
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers
SPIN-TEST: automatic test pattern generation for speed-independent circuits
Metamorphosis: state assignment by retiming and re-encoding
Two-layer quad trees: a data structure for high-speed interactive layout tools
Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
First order nonlinear device bypass in circuit simulation
A theoretical probabilistic simulation framework for dynamic power estimation
Partial synthesis through sampling with and without specification
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits
CleaNN: Accelerated Trojan Shield for Embedded Neural Networks
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference
ICCAD-2015 CAD Contest in Incremental Timing-driven Placement and Benchmark Suite
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper
CETUS-a versatile custom cell synthesizer
Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper
Selecting partial scan flip-flops for circuit partitioning
APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits
ApproxLUT: A novel approximate lookup table-based accelerator
Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations
Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment
Empyrean ALPS-GT: GPU-accelerated Analog Circuit Simulation
Physical placement driven by sequential timing analysis
Using functional independence conditions to optimize the performance of latency-insensitive systems
A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding
A new feed-through assignment algorithm based on a flow model
Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
Modeling and design for beyond-the-die power integrity
SAGE: Saliency-Aware Grouping for Efficient Mapping of LLMs on Analog Compute-in-Memory
A simultaneous routing tree construction and fanout optimization algorithm
ReSCIM: Variation-Resilient High Weight-Loading Bandwidth In-Memory Computation Based on Fine-Grained Hybrid Integration of Multi-Level ReRAM and SRAM Cells
FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials
The Stickizer: a layout to symbolic converter
GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic Encryption
Constrained multivariable optimization of transmission lines with general topologies
ARO: Autoregressive Operator Learning for Transferable and Multi-fidelity 3D-IC Thermal Analysis With Active Learning
Parameterized model order reduction of nonlinear dynamical systems
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
Tunable sensors for process-aware voltage scaling
Scope - quality retaining display rendering workload scaling based on user-smartphone distance
Memory access aware on-line voltage control for performance and energy optimization
Simulation of coupling capacitances using matrix partitioning
ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view
Polynomial methods for component matching and verification
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing
RACI: A Resource-Aware Cooperative Inference Framework on Heterogeneous Edge Devices
The coming of age of physical synthesis
Accelerating RTL simulation with GPUs
Thermal characterization and optimization in platform FPGAs
Ripple: An effective routability-driven placer by iterative cell movement
Sustainable Hardware Specialization
Exploring cache bypassing and partitioning for multi-tasking on GPUs
2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003
ESL solutions for low power design
Transient Power Management Through High Level Synthesis
3D transient thermal solver using non-conformal domain decomposition approach
Placement Tomography-Based Routing Blockage Generation for DRV Hotspot Mitigation
Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper
EPipe: Pipeline Inference Framework with High-quality Offline Parallelism Planning for Heterogeneous Edge Devices
Performance analysis of concurrent systems with early evaluation
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs
CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper
Uninterpreted modeling using the VHSIC hardware description language (VHDL)
A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC converters
Modeling unbuffered latches for timing analysis
PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis
A new global routing algorithm for FPGAs
Optimum and heuristic algorithms for finite state machine decomposition and partitioning
Estimation of delay test quality and its application to test generation
Frame-based dynamic voltage and frequency scaling for a MPEG decoder
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography
Code partitioning for synthesis of embedded applications with phantom
A quantitative study and estimation models for extensible instructions in embedded processors
Fast seed computation for reseeding shift register in test pattern compression
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing
GeminiII: a second generation layout validation program
Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression
Properties first? a new design methodology for hardware, and its perspectives in safety analysis
Layout-level Hardware Trojan Prevention in the Context of Physical Design
A hierarchical decomposition methodology for multistage clock circuits
Ultrafast Density Gradient Accumulation in 3D Analytical Placement with Divergence Theorem
ABILBO: Analog BuILt-in Block Observer
SHAPE: Scheduling of Fixed-Priority Tasks on Heterogeneous Architectures with Multiple CPUs and Many PEs
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
Jitter-tolerant clock routing in two-phase synchronous systems
The care and feeding of your statistical static timer
Breaking the simulation barrier: SRAM evaluation through norm minimization
Clock Period Minimization of Non-Zero Clock Skew Circuits
VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator
IR-drop based electromigration assessment: parametric failure chip-scale analysis
ASTRA: Automatic Sizing of Transistors with Reasoning Agents
AxBA: an approximate bus architecture framework
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters
Efficient network flow based min-cut balanced partitioning
Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing
An efficient sequential range query model for minimum width/space verification (circuit analysis)
MulCh: a multi-layer channel router using one, two, and three layer partitions
Hill climbing with reduced search space (logic optimization)
Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow
Zac: Towards Automatic Optimization and Deployment of Quantized Deep Neural Networks on Embedded Devices
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Fast statistical model of TiO2 thin-film memristor and design implication
Stable Multiway Circuit Partitioning for ECO
On-line scheduling of hard real-time tasks on variable voltage processor
Nanowire addressing with randomized-contact decoders
Signal integrity optimization on the pad assignment for high-speed VLSI design
An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation
Practical method for obtaining a feasible integer solution in hierarchical layout optimization
MF-MOR: Multi-Fidelity Model Order Reduction for Many-Port Linear Systems in Chip Power Modeling
Resiliency in dynamically power managed designs
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
$\mathcal{D}\mathsf{iCA}$: A Hardware-Software Co-Design for Differential Check-Pointing in Intermittently Powered Devices
ICCAD-2013 CAD contest in mask optimization and benchmark suite
CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming
A unified non-rectangular device and circuit simulation model for timing and power
Sizing and placement of charge recycling transistors in MTCMOS circuits
Efficient validity checking for processor verification
A Probabilistic Approach to Buffer Insertion
Banshee: A Fast LLVM-Based RISC-V Binary Translator
A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices
RISCSparse: Point Cloud Inference Engine on RISC-V Processor
Test set compaction algorithms for combinational circuits
Robin: RWKV Accelerator using Block Circulant Matrices based on FPGA
Parameterized RTL power models for combinational soft macros
Analogue circuit optimization in a graphical environment
Interface synthesis: a vertical slice from digital logic to software components
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures
The hype, myths, and realities of testing 3D integrated circuits
An optimal chip compaction method based on shortest path algorithm with automatic jog insertion
Invited Paper: A Scalable Hardware/Software Co-Design Approach for Efficient Polynomial Multiplication
Differentiable Physical Optimization
Power estimation techniques for integrated circuits
Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting
Logic decomposition during technology mapping
A precorrected-FFT method for simulating on-chip inductance
Hierarchical timing analysis using conditional delays
Revisiting Noise-adaptive Transpilation in Quantum Computing: How Much Impact Does it Have?
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Quantum Neural Network Compression
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects
A Force-Directed Macro-Cell Placer
A novel framework for faster-than-at-speed delay test considering IR-drop effects
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling
ScanNow: A Scan Window-Based Sparse Matrix Multiplication Accelerator Design
Variation-aware task allocation and scheduling for MPSoC
False loops through resource sharing
Why the design productivity gap never happened
Challenges and Opportunities in Broadband and Wireless Communication Designs
The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoC
Fault tolerant placement and defect reconfiguration for nano-FPGAs
Logic partitioning to pseudo-exhaustive test for BIST design
Distributionally Robust Circuit Design Optimization under Variation Shifts
Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection
CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed Graph
ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models
ShiftCAM: A Time-Domain Content Addressable Memory Utilizing Shifted Hamming Distance for Robust Genome Analysis
Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction
Manual rescheduling and incremental repair of register-level datapaths
RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs
Modeling design constraints and biasing in simulation using BDDs
An accurate timing model for fault simulation in MOS circuits
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks
CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper)
Event Driven Simulation Without Loops or Conditionals
Maximum independent sets on transitive graphs and their applications in testing and CAD
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
A new formulation of yield enhancement problems for reconfigurable chips
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction
Transient sensitivity computation for transistor level analysis and tuning
Enhancing the solution quality of hardware ising-model solver via parallel tempering
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
SATformer: Transformer-Based UNSAT Core Learning
Fast detection of node mergers using logic implications
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations
"Energon": Unveiling Transformers from GPU Power and Thermal Side-Channels
WTA: waveform-based timing analysis for deep submicron circuits
Performance analysis of a system of communicating processes
HyperEF 2.0: Spectral Hypergraph Coarsening via Krylov Subspace Expansion and Resistance-Based Local Clustering
Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views
Fanout optimization under a submicron transistor-level delay model
Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits
A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel
Yield prediction for 3D capacitive interconnections
A new methodology to address the growing productivity gap in analog design
PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation
A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Bus-Driven Floorplanning
Architecting 3D vertical resistive memory for next-generation storage systems
Standby power optimization via transistor sizing and dual threshold voltage assignment
Slope Propagation in Static Timing Analysis
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
Carbon nanotubes for potential electronic and optoelectronic applications
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction
A Geometry-Material Aware Point Cloud Transformer for Large-scale Unstructured Thermal Analysis in 2.5D ICs
CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design
Leveraging efficient parallel pattern search for clock mesh optimization
Optimal wire and transistor sizing for circuits with non-tree topology
Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication
Universal statistical cure for predicting memory loss