yusuke1997/dblp-id-title huggingface dataset:
An Efficient Content-Addressable Memory Implementation Using Dynamic Routing
Customising Floating-Point Designs
Facilitating Processor-Based DPR Systems for non-DPR Experts
FCCM 2009, 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings
DSynth: A Pipeline Synthesis Environment for FPGAs
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
Concurrency-Aware Thread Scheduling for High-Level Synthesis
Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation
π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization
Open Source High Performance Floating-Point Modules
Design of a Reconfigurable Processor for NIST Prime Field ECC
FPGA-Based Structures for On-Line FFT and DCT
Reconfigurable Object Detection in FLIR Image Sequences
Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT Devices
A Memory-Efficient FPGA-based Classification Engine
FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards
An Implementation of the Conjugate Gradient Algorithm on FPGAs
AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design
Ph.D. Project: Optimizing the Data Traffic for Large Graph Processing on FPGA via a Stateful Approach
Accommodating Multi-Tenant FPGAs in the Cloud
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path
Reconfigurable Retina-Inspired Looming Detection
Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings
A Comparison of Floating Point and Logarithmic Number Systems for FPGAs
Combining Instruction and Loop Level Parallelism for FPGAs
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip
Design Space Exploration for the BLAST Algorithm Implementation
Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices
Increased Performace of FPGA-Based Color Classification System
A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication
A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs
Impulse C vs. VHDL for Accelerating Tomographic Reconstruction
Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms
FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
Accelerating MPI Collectives with FPGAs in the Network and Novel Communicator Support
Groundhog - A Serial ATA Host Bus Adapter (HBA) for FPGAs
FPGA-based SIMD Processor
A Scalable High Throughput Firewall in FPGA
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis
FPGA Acceleration of Gene Rearrangement Analysis
EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding
Reconfigurable Acceleration of Short Read Mapping
Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA Board
Automated Precision Analysis: A Polynomial Algebraic Approach
On Solving RC5 Challenges with FPGAs
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs
SynADT: Dynamic Data Structures in High Level Synthesis
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
Accelerating Graph Analytics with oneAPI and Intel FPGAs
SCCL: An open-source SystemC to RTL translator
Finding Space-Time Stream Permutations for Minimum Memory and Latency
High-End Reconfigurable Systems for Fast Windows' Password Cracking
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs
Relocating Encrypted Partial Bitstreams by Advance Task Address Loading
Hardware-Software Codesign for Embedded Numerical Acceleration
Reconstructing AES Key Schedules from Decayed Memory with FPGAs
The Impact of Hardware Communication on a Heterogeneous Computing System
Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview
A Multithreaded Soft Processor for SoPC Area Reduction
Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation
HODS: Hardware Object Deserialization Inside SSD Storage
14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings
Vertex-Centric Graph Processing on FPGA
Defect-Tolerant Nanocomputing Using Bloom Filters
A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory
Runlength Compression Techniques for FPGA Configurations
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA
Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog
FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit
Automatic Self-Reconfiguration of System-on-Chip Peripherals
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs
Applying the Flask Security Architecture to Secure SoC Design
Dynamic Reconfiguration to Support Concurrent Applications
Hardware-Friendly Acceleration for Deep Neural Networks with Micro-Structured Compression
Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet Networks
Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study
A Multithreaded VLIW Soft Processor Family
Scheduling Intervals for Reconfigurable Computing
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers
FINESSD: Near-Storage Feature Selection with Mutual Information for Resource-Limited FPGAs
Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator
BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic
Adjustable-Cost Overlays for Runtime Compilation
MPLEM: An 80-processor FPGA Based Multiprocessor System
Transfer Learning on the Edge for a Wireless Application Using an SoC Platform
Bézier Curve Rendering on Virtex(tm)
Implementing a genetic algorithm on a parallel custom computing machine
Evaluating Hardware Compilation Techniques
A C to Hardware/Software Compiler
FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off
Hyperspectral Image Compression on Reconfigurable Platforms
Low-Latency FFT/iFFT RTL Implementation for the FALCON Post-Quantum Signature Algorithm
Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface
16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA
Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA
Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Protecting against Cryptographic Trojans in FPGAs
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications
Automated Placement for Parallelized FPGA FFTs
Bridging the Gap between Advanced Memory and Heterogeneous Architectures
Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management
A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons
FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm
5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ
DES Key Breaking, Encryption and Decryption on the XC6216
Exploiting Memory-Level Parallelism in Reconfigurable Accelerators
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms
Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN
Pipeline Vectorization for Reconfigurable Systems
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
Two-Hit Filter Synthesis for Genomic Database Search
Accelerating Large-Scale Graph Analytics with FPGA and HMC
PRAD: A Bayesian Optimization-based DSE Framework for Parameterized Reconfigurable Architecture Design
A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing
RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions
Scalable P4 Deparser for Speeds Over 100 Gbps
25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Napa, CA, USA, April 30 - May 2, 2017
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture
A Framework for Rule Processing in Reconfigurable Network Systems
Ph.D. Project Investigating Chiplet Interfaces for Efficient Near-Sensor Computing in Visual On-Device Intelligence
Systematically migrating an operational microphysics parameterisation to FPGA technology
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs
Design and implementation of a multicomputer interconnection network using FPGAs
Investigating Performance Losses in High-Level Synthesis for Stencil Computations
Fast Online Placement for Reconfigurable Computing
Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based Systems
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme
Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms
Parallelizing FPGA Technology Mapping through Partitioning
PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos
An FPGA-Based Array Processor for an Ionospheric-Imaging Radar
Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs
An Empirical Study of the Reliability of High-Level Synthesis Tools
HardCilk: Cilk-like Task Parallelism for FPGAs
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors
Scalable Full Hardware Logic Architecture for Gradient Boosted Tree Training
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures
Unlocking the AMD Neural Processing Unit for ML Training on the Client Using Bare-Metal-Programming Tools
A Near-Sensor Image Processing Accelerator for Low-end FPGA Design
Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs
Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUs
GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA
Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems
Realization of Quantized Neural Network for Super-resolution on PYNQ
Reconfigurable Array Media Processor (RAMP)
FCCM 2023 PhD Student Forum Compendium of Abstracts: Held on 9th May, 2023, at Los Angeles, USA
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
Architectures for System-Level Applications of Adaptive Computing
Application Experiments: MPPA and FPGA
Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures
The RAW benchmark suite: computation structures for general purpose computing
Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures
FPGA Montgomery Multiplier Architectures - A Comparison
An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing
An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs
Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs
Implementation of a Configurable Controller for an AC Drive Control: A Case Study
Multi-Core Architecture on FPGA for Large Dictionary String Matching
A Fully-Pipelined FPGA Design for Tree-Reweighted Message Passing Algorithm
Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms
Automatic Interior I/O Elimination in Systolic Array Architecture
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs
A dynamic instruction set computer
Optimization of Logic Use on Stereo Vision Algorithm Example
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs
High-Throughput, Lossless Data Compresion on FPGAs
An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
PAM-Blox: High Performance FPGA Design for Adaptive Computing
Fast and Power Efficient Heapsort IP for Image Compression Application
An FPGA-Based Computing Infrastructure Tailored to Efficiently Scaffold Genome Sequences
Highly Efficient String Matching Circuit for IDS with FPGA
Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units
Accelerating Radiosity Calculations Using Reconfigurable Platforms
Improved Lightweight Implementations of CAESAR Authenticated Ciphers
Kiwi: Synthesis of FPGA Circuits from Parallel Programs
A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs
A System-on-Programmable Chip Approach for MIMO Sphere Decoder
A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine
Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs
Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI
Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA
RBoot: Software Infrastructure for a Remote FPGA Laboratory
Field Programmable Gate Array Based Radar Front-End Digital Signal Processing
On Comparing Financial Option Price Solvers on FPGA
Automating Optimization of Reconfigurable Designs
Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability
Rapid prototyping of a RISC architecture for implementation in FPGAs
High-Throughput and Low-Cost Hardware Accelerator for Privacy Preserving Publishing
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams
Register Binding for FPGAs with Embedded Memory
SpGCN: An FPGA-Based Graph Convolutional Network Accelerator for Sparse Graphs
A Communication Scheduling Algorithm for Multi-FPGA Systems
On the viability of FPGA-based integrated coprocessors
SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional Computing
Ph.D. Project: Holistic Partitioning and Optimization of CPU-FPGA Applications Through Source-to-Source Compilation
A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing
A Hardware MPI Spawn for Distributed Multiprocessing Reconfigurable System on Chip (MP-RSoC)
The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware
Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation
Accurate Performance and Power Prediction for FPGAs Using Machine Learning
Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates
Implementation of RNS Addition and RNS Multiplication into FPGAs
Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices
Digit-Serial DSP Library for Optimized FPGA Configuration
Minerva: Accelerating Data Analysis in Next-Generation SSDs
FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography
Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs
ReBNet: Residual Binarized Neural Network
Reconfigurable Elements for a Video Pipeline Processor
A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators
Memory Mapping for Multi-die FPGAs
A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow
New FPGA Architecture for Bit-Serial Pipeline Datapath
Reconfigurable Designs for Radiosity
A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines
High Throughput Matrix Transposition on HBM-Enabled FPGAs
A Model for Peak Matrix Performance on FPGAs
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms
Hardware Solution to Java Compressed Heap
Towards a Universal FPGA Matrix-Vector Multiplication Architecture
Deep Packet Filter with Dedicated Logic and Read Only Memories
Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks
Pipelined Genetic Propagation
Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose
A Dual-Mode Similarity Search Accelerator based on Embedding Compression for Online Cross-Modal Image-Text Retrieval
Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling
ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference via Iterative Tensor Decomposition
Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs
Real-time Extensions to a C-like Hardware Description Language
Parallel Computation of Skyline Queries
Rapid Overlay Builder for Xilinx FPGAs
Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs
Mixed Precision Processing in Reconfigurable Systems
Compute-In-Memory on FPGAs for Deep Learning: A Review
A Flexible Filter Processor for Fading Channel Simulation
PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs
Secure Remote Control of Field-programmable Network Devices
23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015
A Generator of High-Speed Floating-Point Modules
Low-Cost Stereo Vision on an FPGA
A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems Classification
MaNaBIT: A Versatile Tool for Manipulating and Analyzing FPGA Bitstreams
Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative
Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades
A System on Reconfigurable Chip for Handwritten Digit Recognition
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)
Sorting Large Data Sets with FPGA-Accelerated Samplesort
Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)
Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision
An Efficient FPGA-Based Hardware Accelerator of Fully Quantized Mamba-2
Evaluating Low-Memory GEMMs for Convolutional Neural Network Inference on FPGAs
A PCI-compatible FPGA-coprocessor for 2D/3D image processing
Using MORRPH in an industrial machine vision system
11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings
Automatic Generation of FPGA Kernels From Open Format CNN Models
Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud
Compiler-Assisted Kernel Selection for FPGA-based Near-Memory Computing Platforms
FPGA Circuit Synthesis of Accelerator Data-Parallel Programs
Parameterized Module Generator for an FPGA-Based Electronic Cochlea
Compiling ATR Probing Codes for Execution on FPGA Hardware
Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAs
Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path Compression
A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure
Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform
CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers
A software development system for FPGA-based data acquisition systems
Real-time stereo vision on the PARTS reconfigurable computer
Reconfiguration Control Networks for TMR Systems with Module-Based Recovery
High-Performance Reconfigurable Accelerator for Knowledge Graph Reasoning
Compressed Sensing MRI Reconstruction on Intel HARPv2
Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs
Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis
Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems
Floating-Point Accumulation Circuit for Matrix Applications
A Mixed Precision Methodology for Mathematical Optimisation
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform
Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures
Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels
Scheduling of Hardware Tasks in Reconfigurable Mixed-Criticality Systems
Simultaneous Retiming and Placement for Pipelined Netlists
TBOX-Based Mask Scrambling Against SCA
DPA Resistant AES on FPGA Using Partial DDL
Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters
Chronbench: An Incremental HDL Benchmark Suite
Systolic Architecture for Computational Fluid Dynamics on FPGAs
Simulation and Synthesis of CSP-based Interprocess Communication
On Reconfiguring Cache for Computing
Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators
A Hierarchical Memory Architecture with NoC Support for MPSoC on FPGAs
Implementation of single precision floating point square root on FPGAs
Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism
A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
A Parameterized Stereo Vision Core for FPGAs
A Virtual Machine Approach for High-level FPGA Programming
Automating Elimination of Idle Functions by Run-Time Reconfiguration
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign
Ph.D. Project: Field-Programmable Computing for Bayesian Network Structure Learning
Resource Sharing for Verified High-Level Synthesis
Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms
High Density 8-Bit Multiplier Systolic Arrays For Fpga
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs
Performance Modeling and Comparisons of an FPGA-based Direct Simulation Monte Carlo Solver
FPGA-based Accelerators System with Low Latency Autonomous DMA Engine
An FPGA Implementation for Solving Least Square Problem
Lasa: Abstraction and Specialization for Productive and Performant Linear Algebra on FPGAs
Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems
Hardware/Software Integration in Solar Polarimetry
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency