yusuke1997/dblp-id-title huggingface dataset:
A Secure but still Safe and Low Cost Automotive Communication Technique
ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
Efficient Approximate Decomposition Solver using Ising Model
APTQ: Attention-aware Post-Training Mixed-Precision Quantization for Large Language Models
Measured performance of a programmed implementation of the subscripted D-Algorithm
RELIC-FUN: Logic Identification through Functional Signal Comparisons
Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy
Chameleon-SAT: An Adaptive Boolean Satisfiability Accelerator Using Mixed-Signal In-Memory Computing for Versatile SAT Problems
Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors
Pushing ASIC performance in a power envelope
Computer aided design projects
Program visualization: Graphics support for software development
When bad things happen to good chips (panel session)
Analysis of power consumption on switch fabrics in network routers
Engagement of interactive graphic tools in a CAD-system for digital units
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration
Practical iterated fill synthesis for CMP uniformity
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design
Return-to-Non-Secure Vulnerabilities on ARM Cortex-M TrustZone: Attack and Defense
Delay Estimation VLSI Circuits from a High-Level View
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips
Proceedings of the 11th Design Automation Workshop, DAC '74, Denver, Colorado, USA, June 11-19, 1974
Random fault analysis
HADFL: Heterogeneity-aware Decentralized Federated Learning Framework
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Net weighting to reduce repeater counts during placement
Optimal simultaneous mapping and clustering for FPGA delay optimization
MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware Quantization
Building a layered database for design automation
VLSI Design Language Standardization Effort in Japan
Computer-aided partitioning of behavioral hardware descriptions
Exploiting just-enough parallelism when mapping streaming applications in hard real-time systems
Invited - Who is the major threat to tomorrow's security?: you, the hardware designer
Computer-aided logic design on the TX-2 computer
Entering the hot zone - can you handle the heat and be cool?
The SIMON and SPECK lightweight block ciphers
Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method
Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods
Perspective of the Future Semiconductor Industry: Challenges and Solutions
Lightning Talk: The Incredible Shrinking Black Box Model
Efficient bayesian yield analysis and optimization with active learning
Layout Design Methodologies for Sub-Wavelength Manufacturing
Using BDDs to Verify Multipliers
An Efficient Algorithm for Local Don't Care Sets Calculation
Engineering Change: Methodology and Applications to Behavioral and System Synthesis
Large-scale full-wave simulation
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM
Crop: An Analytical Cost Model for Cross-Platform Performance Prediction of Tensor Programs
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
Single-Event-Upset (SEU) Awareness in FPGA Routing
Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs *
Massively Parallel AIG Resubstitution
An implementation of computer aided test generation techniques
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor
SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution
Hardware Support for Secure Processing in Embedded Systems
Evolution of the design of a high volume automatic car merge
Increasing capabilities in interactive computer graphics terminals
Similarity-aware spectral sparsification by edge filtering
Runtime adjustment of IoT system-on-chips for minimum energy operation
Analysis of Switch-Level Faults by Symbolic Simulation
Shoggoth: Towards Efficient Edge-Cloud Collaborative Real-Time Video Inference via Adaptive Online Learning
Hardware-assisted Service Live Migration in Resource-limited Edge Computing Systems
Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAM
Power-aware placement
Reliability analysis and improvement for multi-level non-volatile memories with soft information
Late Breaking Results: Polynomial Formal Verification of Fast Adders
Synthetic biology: from bacteria to stem cells
Stochastic computation
HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction
A synthesis rule for concurrent systems
Making Complex Timing Relationships Readable: Presburger Formula Simplicication Using Don't Cares
Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers
Tool Integration and Construction Using Generated Graph-Based Design Representations
The chip layout problem: A placement procedure for lsi
Analysis of composition complexity and how to obtain smaller canonical graphs
VAWOM: temperature and process variation aware wearout management in 3D multicore architecture
A hybrid CAD/CAM system for mechanical applications
Memory, Control and Communications Synthesis for Scheduled Algorithms
Detecting False Timing Paths: Experiments on PowerPC Microprocessors
A utilitarian approach to CAD
EnTurbo: Accelerate Confidential Serverless Computing via Parallelizing Enclave Startup Procedure
Safe BDD Minimization Using Don't Cares
Self-aware computing in the Angstrom processor
Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-M
A new approach to multi-layer PCB routing with short vias
Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization
In silico synchronization of cellular populations through expression data deconvolution
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks
Real time emulations: foundation and applications
BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
Macromodeling of digital MOS VLSI Circuits
FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program
Checking architectural outputs instruction-by-instruction on acceleration platforms
Significance driven computation on next-generation unreliable platforms
TYMER: A Yield-based Performance Model for Timing-speculation SRAM
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization
Routing with a Scanning Window-8Ma Unified Approach
On path-based learning and its applications in delay test and diagnosis
Throughput-oriented kernel porting onto FPGAs
Towards fault-tolerant embedded systems with imperfect fault detection
An algorithm for one and half layer channel routing
DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based Filtering
Computer aids systems map-based record systems
Real-time simulated earthquake motion of high rise structures
Tail: An Automated and Lightweight Gradient Compression Framework for Distributed Deep Learning
Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced Cost
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
Compacting privacy-preserving k-nearest neighbor search using logic synthesis
MuSiC: an event-flow computer for fast simulation of digital systems
A Self-Tuning Configurable Cache
A CODASYL CAD data base system
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits
An Efficient Finite Element Method for Submicron IC Capacitance Extraction
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Safety in Autonomous Driving: Can Tools Offer Guarantees?
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances
Functional Verification of Large ASICs
Power analysis of embedded operating systems
A new paradigm for synthesis and propagation of clock gating conditions
Towards global routing with RLC crosstalk constraints
Knowledge-based placement technique for printed wiring boards
Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018
Towards collaborative intelligence: routability estimation based on decentralized private data
Delayed Frontal Solution for Finite-Element Based Resistance Extraction
Hazard detection by a quinary simulation of logic devices with bounded propagation delays
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
ProbLP: A framework for low-precision probabilistic inference
New Placement and Global Routing Algorithms for Standard Cell Layouts
Unified user interface for a CAD system
An Efficient Timing-Driven Global Routing Algorithm
A New Heuristic for Single Row Routing Problems
Introduction to the SRC design sciences program
The VLSI design challenge of the 80's (Position Statement)
An EDA framework for large scale hybrid neuromorphic computing systems
An O-Tree Representation of Non-Slicing Floorplan and Its Applications
Analog Compilation Based on Successive Decompositions
An efficient and versatile scheduling algorithm based on SDC formulation
Optimal Allocation and Binding in High-Level Synthesis
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Computer aided design of integrated circuits
Verification of Hardware Descriptions by Retargetable Code Generation
Computerized design of large capital equipment
A complexity effective communication model for behavioral modeling of signal processing applications
Hierarchical power management for asymmetric multi-core in dark silicon era
A Framework for Satisfying Input and Output Encoding Constraints
An accuration delay modeling technique for switch-level timing verification
ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUs
SRAM-based NBTI/PBTI sensor system design
VLSI Layout Compaction Using Radix Priority Search Trees
Creating an Agile Hardware Design Flow
Modeling switch-level simulation using data flow
Post-silicon validation opportunities, challenges and recent advances
PIRAMED project an integrated CAD/CAM system development
The effect of register-transfer design tradeoffs on chip area and performance
An Analytic Optimization Technique for Placement of Macro-Cells
Cost-effective power delivery to support per-core voltage domains for power-constrained processors
Opportunistic Intermittent Control with Safety Guarantees for Autonomous Systems
Contrastive quant: quantization makes stronger contrastive learning
Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects
Application-specific memory management for embedded systems using software-controlled caches
Verification: what works and what doesn't
Watermarking Graph Partitioning Solutions
A universal technique for fast and flexible instruction-set architecture simulation
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis
KAHLUA: A Hierarchical Circuit Disassembler
Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM
LSI product quality and fault coverage
Balancing Efficiency and Flexibility for DNN Acceleration via Temporal GPU-Systolic Array Integration
An improved switch-level simulator for MOS circuits
Mixed-granularity parallel coarse-grained reconfigurable architecture
High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing
Fast hazard detection in combinational circuits
Power-Aware Deployment and Control of Forced-Convection and Thermoelectric Coolers
Establishment of higher level logic design for very large scale computer
Heuristic Acceleration of Force-Directed Placement
Unified Architectural Support for Secure and Robust Deep Learning
A Dynamic Programming Approach to the Test Point Insertion Problem
The automated generation of architectural form
Opportunities and Obstacles in Low-Power System-Level CAD
AdaS: A Fast and Energy-Efficient CNN Accelerator Exploiting Bit-Sparsity
Efficient Floorplan Area Optimization
A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis
Layout Extraction and Verification Methodology CMOS I/O Circuits
DOCIL: An automatic system for printed circuit board (PCB) designing. A board description language and an algorithm to connect a set of points
Approximate property checking of mixed-signal circuits
AutoSkewBMT: Autonomously Synthesizing Optimized Integrity Authentication Mechanism for DNN Accelerators
Small delay testing for TSVs in 3-D ICs
Yet another silicon compiler
Critical path analysis using a dynamically bounded delay model
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels
Timing-driven placement based on partitioning with dynamic cut-net control
IBM perspectives on the electrical design automation industry (keynote address)
Approaches to Multi-level Sequential Logic Synthesis
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications
INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms
A time-domain RF steady-state method for closely spaced tones
Table lookup techniques for fast and flexible digital logic simulation
LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration
MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing
Obstacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Circuit Board
AARC: Automated Affinity-aware Resource Configuration for Serverless Workflows
Reducing time and effort in IC implementation: a roadmap of challenges and solutions
Evaluating battery aging on mobile devices
An ASIC Methodology for Mixed Analog-Digital Simulation
TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell Methodology
Removing overhead from high-level interfaces
Variation-tolerant circuits: circuit solutions and techniques
Resynthesis and Retiming for Optimum Partial Scan
Iterative and Adaptive Slack Allocation for Performance-Driven Layout and FPGA Routing
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
Dealing with Inductance in High-Speed Chip Design
Universal fault simulation using fault tuples
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter
Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs
Embedded test control schemes for compression in SOCs
PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements
Precedent-based manipulation of VLSI structures
A unified approach to test data analysis
Bridging pre-silicon verification and post-silicon validation
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration
MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Automatic VLSI layout verification
A method for gridless routing of printed circuit boards
Invited: Neuromorphic Architectures Based on Augmented Silicon Photonics Platforms
Schedule Integration Framework for Time-Triggered Automotive Architectures
User documentation for Design Automation at TI
CLUMAP: Clustered Mapper for CGRAs with Predication
Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP Materials
Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional System
DVFS in loop accelerators using BLADES
Scalable Co-Simulation of Functional Models With Accurate Event Exchange
Verification of Interacting Sequential Circuits
Optimum Design of Reliable IC Power Networks Having General Graph Topologies
DFM: don't care or competitive weapon?
UEFI Firmware Fuzzing with Simics Virtual Platform
ROC: DRAM-based Processing with Reduced Operation Cycles
Optimal design of delta-sigma ADCs by design space exploration
Comprehensive Search for ECO Rectification Using Symbolic Sampling
Approximate Reachability with BDDs Using Overlapping Projections
A framework for evaluating design tradeoffs in packet processing architectures
Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs
The Bell Telephone Laboratories automatic graphic schematic drawing program
SC-GNN: A Communication-Efficient Semantic Compression for Distributed Training of GNNs
Changing the Government's role in design automation (Position Paper)
Verifying SystemC using an intermediate verification language and symbolic simulation
TI-TRNG: Technology Independent True Random Number Generator
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis
A State-Machine Synthesizer - SMS
Consistency checking for MOS/VLSI circuits
A Methodology for Accurate Performance Evaluation in Architecture Exploration
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis
A low cost satellite for fast interactive graphics in a time-sharing environment
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory
Automatic Incorporation of On-Chip Testability Circuits
Polynomial datapath optimization using partitioning and compensation heuristics
Optimal design of welded girders
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints
Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems
Multicore design is the challenge! what is the solution?
GENDA - a generalized design automation system for modular hardware
Delay test generation
MEMS CAD Beyond Multi-Million Transistors (Panel)
SMatch: Structural Matching for Fast Resynthesis in FPGAs
Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack
H-ORAM: A Cacheable ORAM Interface for Efficient I/O Accesses
Security analysis of logic obfuscation
A general computer simulation technique for assessments and testing requirements
Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning
A Gaussian mixture model for statistical timing analysis
Quantum Circuit Placement: Optimizing Qubit-to-qubit Interactions through Mapping Quantum Circuits into a Physical Experiment
Retiming Synchronous Circuitry with Imprecise Delays
Statistical logic cell delay analysis using a current-based model
Efficient AC and Noise Analysis of Two-Tone RF Circuits
A PLA based asynchronous micropipelining approach for subthreshold circuit design
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers
IFHE: Intermediate-Feature Heterogeneity Enhancement for Image Synthesis in Data-Free Knowledge Distillation
Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC
Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting
ANGraph: A GNN-Based Performance Prediction Framework for Asynchronous Neuromorphic Hardware
Opportunities in Computer Integrated Manufacturing
Routing Algorithm for Gate Array Macro Cells
Trapped by Your WORDs: (Ab)using Processor Exception for Generic Binary Instrumentation on Bare-metal Embedded Devices
Twenty-Five Years of Electronic Design Automation
FLOSS: FLOw sensitive scheduling on mobile platforms
TinyML: Current Progress, Research Challenges, and Future Roadmap
Coalgebraic Division for Multilevel Logic Synthesis
On-Chip Communication Architecture for OC-768 Network Processors
CLUSTR: A program for structuring design problems
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection
Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise Matching
Symbolic model checking on SystemC designs
Bridge: A Versatile Behavioral Synthesis System
Design For Test Calculus: An algorithm for DFT rules checking
A design verification methodology based on concurrent simulation and clock suppression
vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures
Design Considerations for Battery-Powered Electronics
Clustered VLIW Architectures with Predicated Switching
Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization
An algorithm-architecture co-design framework for gridding reconstruction using FPGAs
A variation tolerant subthreshold design approach
Is there a "Best" Programming Language For Design Automation?
Generation of Performance Sensitivities for Analog Cell Layout
PacTrain: Pruning and Adaptive Sparse Gradient Compression for Efficient Collective Communication in Distributed Deep Learning
Conjuring: Leaking Control Flow via Speculative Fetch Attacks
H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness
Invited: Building Robust Quantum System Software for Technology-Specific Characteristics
CamPUF: physically unclonable function based on CMOS image sensor fixed pattern noise
Logic design automation of MOS combinational networks with fan-in, fan-out constraints
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation
Trusting the trust anchor: towards detecting cross-layer vulnerabilities with hardware fuzzing
Some experimental results on placement techniques
Delay Modeling and Time of Bipolar Digital Circuits
A New Verification Methodology for Complex Pipeline Behavior
CHIME: coupled hierarchical inductance model evaluation
Hermes: an integrated CPU/GPU microarchitecture for IP routing
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms
NNTesting: Neural Network Fault Attacks Detection Using Gradient-Based Test Vector Generation
C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses
NNsim: fast performance estimation based on sampled simulation of GPGPU kernels for neural networks
Hierarchical layout verification
MIMO technology for advanced wireless local area networks
Ever more optimized simulations of fermionic systems on a quantum computer
eButton: A Wearable Computer for Health Monitoring and Personal Assistance
An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs