yusuke1997/dblp-id-title huggingface dataset:
MBStar: A Real-time Communication Protocol for Wireless Body Area Networks
On the Pitfalls of Resource Augmentation Factors and Utilization Bounds in Real-Time Scheduling
Response-Time Analysis of Limited-Preemptive Parallel DAG Tasks Under Global Scheduling
A Real-Time RMI Framework for the RTSJ
NPM-BUNDLE: Non-Preemptive Multitask Scheduling for Jobs with BUNDLE-Based Thread-Level Scheduling
Timing Analysis of Fixed Priority Self-Suspending Sporadic Tasks
Graceful Degradation in Semi-Clairvoyant Scheduling
Autonomy Today: Many Delay-Prone Black Boxes
QoS guarantee using probabilistic deadlines
Integration of RTL and precedence graphs with a static scheduler as verifier
Deadline Assignment and Tardiness Control for Real-Time Data Services
Predictive Thermal Control for Real-Time Video Decoding
Modelling and analysis of a commercial field bus protocol
An Efficient Method for Assigning Harmonic Periods to Hard Real-Time Tasks with Period Ranges
Outstanding Paper Award: Bounding and Shaping the Demand of Mixed-Criticality Sporadic Tasks
Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures
Determining the worst-case blocking sequences for distributed real-time programs
A transaction-based temporal data model that supports prediction in real-time databases
Efficient Synchronization under Global EDF Scheduling on Multiprocessors
One solution for the non-determinism problem in the SCEPTRE 2 fault tolerance technique
CoAdapt: Predictable Behavior for Accuracy-Aware Applications Running on Power-Aware Systems
Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead
On the schedulability analysis for distributed hard real-time systems
Improving Real-Time Feasibility Analysis for Use in Linear Optimization Methods
Interconnection Optimization for Multi-cluster Avionics Networks
Fitting Schedulability Analysis Theory into Model-Driven Engineering
Unikernel-Based Real-Time Virtualization Under Deferrable Servers: Analysis and Realization
Supporting timeliness and security in real-time database systems
KOS: a knowledge-based operating system for real-time onboard applications of artificial intelligence
Sustainable Security & Safety: Challenges and Opportunities
Software models for real-time systems
Real-Time Competitive Environments: Truthful Mechanisms for Allocating a Single Processor to Sporadic Tasks
A multi-agent distributed real-time system for a microprocessor field-bus network
A Coordinated Approach for Practical OS-Level Cache Management in Multi-core Real-Time Systems
27th Euromicro Conference on Real-Time Systems, ECRTS 2015, Lund, Sweden, July 8-10, 2015
Refactoring Asynchronous Event Handling in the Real-Time Specification for Java
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds
Offsets for Scheduling Mode Changes
Worst-Case Execution Time Analysis for Dynamic Branch Predictors
Efficient Worst-Case Execution Time Analysis of Dynamic Branch Prediction
Real-Time Performance of Dynamic Memory Allocation Algorithms
Impact of AS6802 Synchronization Protocol on Time-Triggered and Rate-Constrained Traffic
A Programmable Concurrency Control Service for Real-Time Object Request Brokers
A Sensitivity Analysis of Two Worst-Case Delay Computation Methods for SpaceWire Networks
Minimum and Maximum Utilization Bounds for Multiprocessor RM Scheduling
The effects of cache architecture on the performance of operating systems in multithreaded processors
Semi-partitioned Scheduling of Sporadic Task Systems on Multiprocessors
Investigation of the pessimism in distributed systems timing analysis
15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2-4 July 2003, Porto, Portugal, Proceedings
On the Convolution Efficiency for Probabilistic Analysis of Real-Time Systems
Push Forward: Global Fixed-Priority Scheduling of Arbitrary-Deadline Sporadic Task Systems
Collaborative Resource Allocation in Wireless Sensor Networks
Closed World Specification of Embedded Real-Time Controllers
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks
Analytical Study of Quantitative Timing Properties of Software
Guaranteed deadlines with dynamic recovery blocks in distributed systems
Scheduling of Early Quantum Tasks
Fuzzy-control with a PEARL-based multi-loop controller
ILP-Based Approaches to Partitioning Recurrent Workloads Upon Heterogeneous Multiprocessors
Experiments with parametric verification of real-time systems
Visualisation of real-time software in host-based simulation environment
Integrated validation of real-time system models
Replica-Aware Co-Scheduling for Mixed-Criticality
Energy-Aware Memory Firewalling for QoS-Sensitive Applications
Robust Real-Time Multiprocessor Interrupt Handling Motivated by GPUs
Bounding Worst-Case Access Times in Modern Multiprocessor Systems
Sensitivity Analysis for Fixed-Priority Real-Time Systems
Adding local priority-based dispatching mechanisms to P-NET networks: a fixed priority approach
Timing Failure Detection and Real-Time Group Communication in Quasi-Synchronous Systems
Validating the Design of Real-Time Systems Using a Formal Specification Method
Scheduling periodic tasks on uniform multiprocessors
Synchronous programming of a real-time microcontroller
Error-Driven QoS Management in Imprecise Real-Time Databases
Ada gets groomed for the whole spectrum of real-time duties
Optimal Selection of Preemption Points to Minimize Preemption Overhead
Semi-Partitioned Hard-Real-Time Scheduling under Locked Cache Migration in Multicore Systems
Schedulability Analysis for Multi-Core Systems Accounting for Resource Stress and Sensitivity
Real-Time Scheduling with Regenerative Energy
POSIX-Compatible Application-Defined Scheduling in MaRTE OS
Real-Time Approach for Development of Scientific Space Instrument Software
An ASIC Supporting External Clock Synchronization for Distributed Real-Time Systems
Scheduling analysis of hybrid real-time task sets
Non-blocking Deterministic Replacement of Functionality, Timing, and Data-Flow for Hard Real-Time Systems at Runtime
Reachability-Based Response-Time Analysis of Preemptive Tasks Under Global Scheduling
Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems
Partitioned Fixed-Priority Preemptive Scheduling for Multi-core Processors
Deriving Real-Time Requirements for Software from Safety Analysis
A New Kernel Approach for Modular Real-Time Systems Development
Transaction processing in wireless distributed real-time databases
Establishing Timing Requirements and Control Attributes for Control Loops in Real-Time Systems
Meeting Task Deadlines in a Community of Cooperative Intelligent Systems
Static scheduling of pipelined periodic tasks in distributed real-time systems
Temporal Analysis for Adapting Concurrent Applications to Embedded Systems
Neural networks for multiprocessor real-time scheduling
Non-Preemptive Interrupt Scheduling for Safe Reuse of Legacy Drivers in Real-Time Systems
Worst-case utilization bound for EDF scheduling on real-time multiprocessor systems
XTG-an engineering approach to modelling and analysis of real-time systems
Supporting Component-Based Development in Partitioned Multiprocessor Real-Time Systems
A comparison of fixed-priority and static cyclic scheduling for distributed automotive control applications
Extreme Value Theory for Estimating Task Execution Time Bounds: A Careful Look
Real-Time System Evaluation Techniques: A Systematic Mapping Study
A Data Priority Reload Technique for Real-Time Main Memory Databases
Design of a Learning Fuzzy Production System to Solve an NP-Hard Real-Time Assignment Problem
The Time-Triggered Wireless Architecture
The FTT-Ethernet Protocol: Merging Flexibility, Timeliness and Efficiency
End-to-End Delay Analysis of Distributed Systems with Cycles in the Task Graph
Vulnerability Analysis and Mitigation of Directed Timing Inference Based Attacks on Time-Triggered Systems
Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks
IRTC: integration of knowledge engineering with real-time control
Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems
A Petri Net Based Modelling and Synthesis Technique for Real-Time Systems
The Dependency Management Framework: A Case Study of the ION CubeSat
Improved Tardiness Bounds for Global EDF
The modular multimicroprocessor system architecture for the power turbine control
Camera Networks Dimensioning and Scheduling with Quasi Worst-Case Transmission Time
Relational Cache Analysis for Static Timing Analysis
Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation
Real-Time Scheduling for Data Stream Management Systems
Optimizing Per-Core Priorities to Minimize End-To-End Latencies
Concurrency Control Algorithm for Real-Time Tasks with Read/Write Operations
Fault tolerant real-time global scheduling on multiprocessors
Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems
Theta: an object-oriented operating system for intelligent process monitoring
Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems
Integration of task scheduling and file services in the safety-critical system MELODY
Multi-Objective Memory Bandwidth Regulation and Cache Partitioning for Multicore Real-Time Systems
Multi Sloth: An Efficient Multi-core RTOS Using Hardware-Based Scheduling
Supporting Preemptive Task Executions and Memory Copies in GPGPUs
Foundational Response-Time Analysis as Explainable Evidence of Timeliness
Design of a real-time computer system for relative position robot control
Implementing real-time applications with concurrent objects
Feasibility Analysis of Conditional DAG Tasks
Improved scheduling of control tasks
Towards Efficient Explainability of Schedulability Properties in Real-Time Systems
Improved Prediction for Web Server Delay Control
Timing Constraints of MPEG-2 Decoding for High Quality Video: Misconceptions and Realistic Assumptions
A Hard Real-Time Bus Arbitration Protocol based on EIA-709
Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization
Using ObjectCharts to specify and design electronic systems
Greedy reclamation of unused bandwidth in constant-bandwidth servers
Response Time Analysis of Asynchronous Periodic and Sporadic Tasks Sheduled by a Fixed Priority Preemptive Algorithm
A Rapid Prototyping Approach for Specification and Design of Distributed Automotive Control Systems
A Measurement-Based Model for Parallel Real-Time Tasks
Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
24th Euromicro Conference on Real-Time Systems, ECRTS 2012, Pisa, Italy, July 11-13, 2012
Scheduling Models for Real-Time Systems
Predicting real-time behaviour for data flow computations
Switching Between Left and Right Continuity in Network Calculus
Euromicro '91 Workshop on Real Time Systems, RTS 1991, Université Paris XI, Paris-Orsay, France, June 12-14, 1991, Proceedings
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems
The Global Feasibility and Schedulability of General Task Models on Multiprocessor Platforms
Cache-Aware Timing Analysis of Streaming Applications
Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems
Pessimistic Deadline Ceiling Protocol: a concurrency control protocol under earliest deadline first scheduling
Response Time Analysis for Fixed-Priority Preemptive Uniform Multiprocessor Systems
smARTflight: An Environmentally-Aware Adaptive Real-Time Flight Management System
When object-oriented operating system is time critical
Improvement to Quick Processor-Demand Analysis for EDF-Scheduled Real-Time Systems
Guaranteeing end-to-end deadlines in distributed client-server applications
Run-Time Control to Increase Task Parallelism In Mixed-Critical Systems
Memory Resource Management for Real-Time Systems
Hardware Compute Partitioning on NVIDIA GPUs for Composable Systems
Optimal Program Partitioning for Predictable Performance
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems
Hybrid specification and formal distributed heterogeneous prototyping of distributed real-time systems
MAST: Modeling and Analysis Suite for Real Time Applications
Modeling Cache Coherence to Expose Interference
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations
Surgical Software-less I/O Virtualization
NAMP: A Network-Aware Model Partitioning Framework for Constrained Devices
Local Ratio based Real-time Job Offloading and Resource Allocation in Mobile Edge Computing
Proceedings of the 4th International Workshop on Real-time and IntelliGent Edge computing, RAGE 2025, Irvine, CA, USA, May 6-9, 2025
Adaptive Intrusion Mitigation in Software-Defined Vehicles Using Deep Reinforcement Learning
INVITED: A Position on Network Management and Control for Dynamic Real-Time Systems
INVITED: Optimizing IoT Node Design for Edge Computing Applications
Selective Layer Acceleration with Data-parallel Architecture for DNN Inference Throughput Maximization
Efficient Inference of parallel partitioned hybrid-Vision Transformers
INVITED: Trusted Time for Untrusted Edge Systems
SIM-LDM: Local Dynamic Map Generation Framework using Autonomous Driving Simulator
Modelling Safe and Secure Cooperative Intelligent Transport Systems
Detection of Teamwork Behavior as Meaningful Exploration of Tradespace During Project Design
Modeling Operations of a Custom Hiring Center Using Agent Based Modeling and Discrete Event Simulation
Complex Systems Design & Management Asia - Smart Transportation: Proceedings of the Third Asia-Pacific Conference on Complex Systems Design & Management, CSD&M Asia 2018, December 6-7, 2018, Singapore
A Net-Based Formal Framework for Causal Loop Diagrams
Multi-class Fleet Sizing and Mobility on Demand Service
Modelling the Efficacy of Assurance Strategies for Better Integration, Interoperability and Information Assurance in Family-of-System-of-Systems Portfolios
SMACOF Hierarchical Clustering to Manage Complex Design Problems with the Design Structure Matrix
Leveraging Data Analytics in Systems Engineering - Towards a Quantum Leap in Railway Reliability
Non-physical Painting Restoration in Improved Reality
Evaluation of Using Mobile Devices for 3D Reconstruction of Cultural Heritage Artifacts
"I Went to America to See Ancient Italian Paintings": The Problem of the Re-contextualization of Artworks Uprooted from Their Original Settings
Natural Interaction in Virtual Reality for Cultural Heritage
Towards a Novel User Satisfaction Modelling for Museum Visit Recommender Systems
Exploring Cultural Heritage Using Augmented Reality Through Google's Project Tango and ARCore
Digital Scanning and Non-destructive Techniques for Size Recovering and Rehabilitating the Structural Performance of Traditional Stuccoes
From Exploration of Virtual Replica to Cultural Immersion Through Natural Gestures
Improving Dissemination and Localization of Cultural Heritage Through Multimedia Maps - The Case of Lipari Island
VR Technologies in Cultural Heritage - First International Conference, VRTCH 2018, Brasov, Romania, May 29-30, 2018, Revised Selected Papers
Digital Data, Virtual Tours, and 3D Models Integration Using an Open-Source Platform
DinofelisAR: Users' Perspective About a Mobile AR Application in Cultural Heritage
Application of Fourier-Transform Infrared Spectroscopy (FTIR) for the Study of Cultural Heritage Artifacts
Automatic Creation of a Virtual/Augmented Gallery Based on User Defined Queries on Online Public Repositories
Virtual Assistants for the Cultural Heritage Domain
Appropriate Control Methods for Mobile Virtual Exhibitions
Proposal for an Automated Form Finder System to Deduce the Authentic Morphology of Siirt Cas Houses
Towards Preserving Transylvanian Fortified Churches in Virtual Reality
Exploring European Cultural Heritage Using Conversational Agents
16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions
Algorithms for the optimal state assignment of asynchronous state machines
Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing
Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits
Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs
Bit-serial bidirectional A/D/A conversio
Scalability in computing for today and tomorrow
Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor
Recursive layout generation
Kestrel: Design of an 8-bit SIMD Parallel Processor
Phantom Mode Signaling in VLSI Systems
Systematic objective-driven computer architecture optimization
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
Abacus: a 1024 processor 8 ns SIMD array
Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits
Silicon Adventures-Go Ahead; Be Bold!
Width-Adaptive Data Word Architectures
MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
XXI Century Gigascale Integration (GSI) : The Interconnect Problem
Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure
Multi-Chip Neuromorphic Motion Processing
Trends of Key Advanced Device Technologies
Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements
Non-dissipative rail drivers for adiabatic circuits
Standard CMOS active pixel image sensors for multimedia applications
Architectural Design of a Three Dimensional FPGA
Silicon VLSI processing architectures incorporating integrated optoelectronic devices
Distributed synchronous clocking
An Embedded DRAM for CMOS ASICs
Battery-powered, Wireless MEMS Sensors for High-Sensitivity Chemical and Biological Sensing
The Design of an Asynchronous MIPS R3000 Microprocessor
18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA
Circuits and Microarchitecture for Gigahertz VLSI Designs
Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS
Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics
Problems and Prospects for Electrical Signaling
A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems
Array-of-arrays architecture for parallel floating point multiplication
Architecture Design of Reconfigurable Pipelined Datapaths
Adaptive Circuits Using pFET Floating-Gate Devices
Compact Signed-Digit Adder Using Multiple-Valued Logic
A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina
Clock Distribution Using Cooperative Ring Oscillators
Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits
Low-latency plesiochronous data retiming
Exploring Microprocessor Architectures for Gigascale Integration
Next-Generation RF Circuits and Systems
High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips
Focal-Plane Image and Beam Quality Sensors for Adaptive Optics
Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG
Architectural Considerations for Application-Specific Counterflow Pipelines
An evaluation of bipartitioning techniques
Combined DRAM and logic chip for massively parallel systems
A Low-Power Asynchronous VLSI FIR Filter
Low latency self-timed flow-through FIFOs
Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors
Precise Exceptions in Asynchronous Processors
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
Energy recovery for low-power CMOS
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Analog VLSI circuits for manufacturing inspection
Optimization of combinational and sequential logic circuits for low power using precomputation
Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation
19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA
Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems
A Two-Dimensional, Object-Based Analog VLSI Visual Attention System
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture
System-on-a-Chip VLSI - Is It Finally Really Here?
Interconnect-Dominated VLSI Design
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test
A Column-based Processing Array for High-speed Digital Image Processing
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution
Single-transistor transparent-latch clocking
Fault Scanner for Reconfigurable Logic
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A VLSI Architecture for Modeling Intersegmental Coordination
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
A multi-sender asynchronous extension to the AER protocol
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier
Code density optimization for embedded DSP processors using data compression techniques
Dynamic Receiver Biasing For Inter-Chip Communication
Methods and Circuits for Focal-Plane Computation of Features in CMOS Visual Sensors
Quasi-algebraic decompositions of switching functions
17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA
Visual Sensor with Resolution Enhancement by Mechanical Vibrations
A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips
A Quantitative Approach to Nonlinear Process Design Rule Scaling
Logic Design Considerations for 0.5-Volt CMOS
Dynamic CMOS circuit techniques for delay and power reduction in parallel adders
Automatic synthesis of gate-level timed circuits with choice
Who Put the Sugar in Sydney Harbor?
Efficient retiming under a general delay model
VLSI Architecture: Past, Present, and Future
Area-Universal Circuits with Constant Slowdown
Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip
HAL: heuristic algorithms for layout synthesis
Asynchronous Microengines for Efficient High-level Control
Design Implementation of Intrinsic Area Array ICs
On the performance of level-clocked circuits
Some QoS Aspects of Multimedia Communication
Fairness Property and TCP-Level Performance of Unified Scheduling Algorithm in HSDPA Networks
Universal Multiservice Networks: Third European Conference, ECUMN 2004, Porto, Portugal, October 25-27, 2004. Proceedings
Toward a Distributed Control Plane Architecture for Next Generation Routers
A TCP Protocol Booster for Wireless Networks
Authentication, Authorization, Admission, and Accounting for QoS Applications
The Dynamic Cache-Multicast Algorithm for Streaming Media
Multi-time-Scale Traffic Modeling Using Markovian and L-Systems Models
Scalable Local Mobility Support for the IPv6-Based Wireless Network Using Improved Host Based Routing
Introducing Semantic Technologies in Web Services-Based Application Discovery within Grid Environments
Multimodal Access Enabler Based on Adaptive Keyword Spotting
Integration and Application Platform of Service-Oriented Telecom Businesses
Cost Effective Design of TDM ADM Embedded in WDM Ring Networks
A QoS Based Service Reservation: Supporting Multiple Service in Optical Access Networks
Fuzzy Mobility Management in Cellular Communication Systems