yusuke1997/dblp-id-title huggingface dataset:
15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS
24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor
A 1.2V Dual-Mode GSM/WCDMA - Modulator in 65nm CMOS
31.2 A Ripple-Less Buck Converter with Sub -21.94dB EVM for 5G Low Earth Orbit Application
A 90nm CMOS Dual-Channel Powerline Communication AFE for Homeplug AV with a Gb Extension
A 3μW wirelessly powered CMOS glucose sensor for an active contact lens
High-speed image sensor technologies
Gb/s+ portable wireless communications
Session 27 overview: Biomedical circuits
A 40nm CMOS single-chip 50Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels
Session 17 Overview: DC-DC Converters Power Management Subcommittee
Session 6 overview: Image sensors and displays: IMMD subcommittee
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces
Technologies that could change the world - You decide!
An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance
1D and 2D analog 1.5kHz air-stable organic capacitive touch sensors on plastic foil
A 9.2µA gen 2 compatible UHF RFID sensing tag with -12dBm Sensitivity and 1.25µVrms input-referred noise floor
A self-supplied inertial piezoelectric energy harvester with power-management IC
Next Generation Smart Power Technologies - Challenges and Innovations Enabling Complex SoC Integration
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU
A 500Mb/s -46.1dBm CMOS SPAD Receiver for Laser Diode Visible-Light Communications
22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems
A charge-multiplication CMOS image sensor suitable for low-light-level imaging
A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from -70°C to 130°C
An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage
9.7 A 6.9mW 120fps 28×50 capacitive touch sensor with 41.7dB SNR for 1mm stylus using current-driven ΔΣ ADCs
3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique
Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation
33.4 A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-End and Explainable AI for Memory Studies in Freely Behaving Monkeys
A CMOS Dual-RC frequency reference with ±250ppm inaccuracy from -45°C to 85°C
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS
Advanced MMIC for Passive Millimeter and Submillimeter Wave Imaging
128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode
9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability
A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler
Healthy Radios: Radio & microwave devices for the health sciences
A wireless magnetoresistive sensing system for an intra-oral tongue-computer interface
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS
Some Recent Progress in Bioelectronics
Towards terahertz operation of CMOS
10.6 A 30MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transient
Display Electronics
Session 2 Overview: RF TX/RX design techniques: RF subcommittee
40Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18μm CMOS
Sustainability in silicon and systems development
A High-Density 45nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
5.8 A 20W CMOS/LDMOS All-Digital Transmitter with Dynamic Retiming and Glitch-Free Phase Mapper, Achieving 68%/62% Peak Drain/System Efficiency
A 51A Hybrid Magnetic Current Sensor with a Dual Differential DC Servo Loop and 43mArms Resolution in a 5MHz Bandwidth
5.1 A GaN SLCG-Doherty-Continuum Power Amplifier Achieving >38% 6dB Back-Off Efficiency Over 1.35 to 7.6GHz
Session 3 overview: Processors: High performance digital subcommittee
5.9 A 21-to-31 GHz DPD-Less Quadrature RFDAC with Invariant Impedance and Scalable LO Leakage
An 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers
An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain
A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOS
A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology
A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s
27.4 A 0.75-million-point fourier-transform chip for frequency-sparse signals
5.1 A 60V auto-zero and chopper operational amplifier with 800kHz interleaved clocks and input bias-current trimming
A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS
A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input
Adaptive Intelligence in The New Computing Era
A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster
A 4.4μW 2.5kHz-BW 92.1dB-SNDR 3 rd -Order VCO-Based ADC With Pseudo Virtual Ground Feedforward Linearization
5.7 A 29nW bandgap reference circuit
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing
A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications
27.5 A Wireless Power Transfer System with Up-to-27.9% Efficiency Improvement under Coupling Coefficient Ranging from 0.1 to 0.39 Based on Phase-Shift/Time-Constant Detection and Hybrid Transmission Power Control
A 60µW 60 nV/Hz Readout Front-End for Portable Biopotential Acquisition Systems
A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS
27.4 A BJT-Based Temperature Sensor with an 80fJ.K 2 Resolution FoM
A piezoelectric energy-harvesting interface circuit with fully autonomous conjugate impedance matching, 156% extended bandwidth, and 0.38μW power consumption
A versatile multi-modality serial link
26.2 A Fully Nonlinear Compact 10b Source Driver with Low-Voltage Gamma Slope DAC and Data/Phase Dependent Current Modulation Achieving 2411μm 2 /Channel for Mobile OLED Displays
32.10 A Compact Broadband VSWR-Resilient True-Power-and-Gain Sensor with Dynamic-Range Compensation for Phased-Array Applications
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family
A Reversible Poly-Phase Distributed VCO
Session 22 overview: High-speed optical links: Wireline subcommittee
11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems
Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation
A 5V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction
A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control
27.2 A 25.2mW EEG-NIRS multimodal SoC for accurate anesthesia depth monitoring
A CMOS Image Sensor with a Buried-Channel Source Follower
A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL
A 28nm 68MOPS 0.18\mu\mathrm{J}/\text{Op}$ Paillier Homomorphic Encryption Processor with Bit-Serial Sparse Ciphertext Computing
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology
A 0.076mm 2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS
9.4 A 27µW 0.06mm 2 background resonance frequency tuning circuit based on noise observation for a 1.71mW CT-ΔΣ MEMS gyroscope readout system with 0.9°/h bias instability
A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations
A 0.5-to-480MHz Self-Referenced CMOS Clock Generator with 90ppm Total Frequency Error and Spread-Spectrum Capability
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface
A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect
A 132-to-148GHz CMOS 4TX-4RX FMCW Radar Transceiver Array with Cavity-Backed Antenna-in-Package Achieving 28dBm EIRP
A 0.004mm 2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm 2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications
Full-Duplex 2×2 MIMO Circulator-Receiver with High TX Power Handling Exploiting MIMO RF and Shared-Delay Baseband Self-Interference Cancellation
A 23.6Mb/mm 2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications
EE6: Can artificial intelligence replace my job? The dawn of a new IC industry with AI
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks
Why Can't A Computer Be More Like A Brain? Or What To Do With All Those Transistors?
22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data
The Crucial Role of Semiconductors in the Software-Defined Vehicle
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure
4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density
Session 21 overview: Analog techniques: Analog subcommittee
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS
4.5 A 1.8erms - temporal noise over 110dB dynamic range 3.4µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers, SS-ADC and multiple-accumulation shutter
A 16Gb/s 1 st -Tap FFE and 3-Tap DFE in 90nm CMOS
23.8 A 40Gb/s 14mW CMOS wireline receiver
24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS
21.3 A -106.3dB THD+N Feedback-After-LC Class-D Audio Amplifier Employing Current Feedback to Enable 530kHz LC-Filter Cut-Off Frequency
A ±25A Versatile Shunt-Based Current Sensor with 10kHz Bandwidth and ±0.25% Gain Error from -40°C to 85°C Using 2-Current Calibration
Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS
Session 26 overview: Short-range wireless transceivers: Wireless subcommittee
19.2 A 93.4mm 2 64Gb MLC NAND-flash memory with 16nm CMOS technology
Analog and Power Management Techniques
5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability
A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET
A Sub-1V 810nW Capacitively-Biased BJT-Based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -55°C to 125°C
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays
Spur-free all-digital PLL in 65nm for mobile phones
27.2 A1.2μg/√Hz-resolution 0.4μg-bias-instability MEMS silicon oscillating accelerometer with CMOS readout circuit
18.3 A multi-parameter signal-acquisition SoC for connected personal health applications
5.9 A 37μW dual-mode crystal oscillator for single-crystal radios
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
A 56GHz 23mW Fractional-N PLL with 110fs Jitter
XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis
A $47\text{fs}_{\text{rms}}$-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor
A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5 th -Generation 10nm DRAM Process
A Wideband Blocker-Tolerant Receiver with High-Q RF-Input Selectivity and <-80dBm LO Leakage
20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels
Reversing Scattering to Perform Deep-Tissue Optical Imaging and the Current Need for a Suitable Optoelectronic Solution
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI
23.7 Self-powered 30μW-to-10mW Piezoelectric energy-harvesting system with 9.09ms/V maximum power point tracking time
A blind baud-rate ADC-based CDR
30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization
33.3 An Automotive-Use 2MHz 100VOUT Flicker-Free Frequency-Modulated GaN-Based Buck-Boost LED Driver Achieving Bootstrap Charge Balancing and 16.8dBμV Radiated EMI Noise Reduction
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators
Session 21 overview: Power converters
A Zero-Crossing-Based 8b 200MS/s Pipelined ADC
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core
26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes
A 1/13-inch 30fps VGA SoC CMOS image sensor with shared reset and transfer-gate pixel control
1.3 Analog CMOS from 5 micrometer to 5 nanometer
Design of the Power6 Microprocessor
A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications
A Stimulus-Scattering-Free Pixel-Sharing Sub-Retinal Prosthesis SoC with 35.8dB Dynamic Range Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling
Session 21 overview: Smart SoCs for innovative applications
12.8 Synchronized floating current mirror for maximum LED utilization in multiple-string linear LED drivers
5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm 2 area
28.7 A 0.00378mm 2 Scalable Neural Recording Front-End for Fully Immersible Neural Probes Based on a Two-Step Incremental Delta-Sigma Converter with Extended Counting and Hardware Reuse
A 1.8Gb/s, 2.3pJ/bit, Crystal-Less IR-UWB Transmitter for Neural Implants
E1 Ultimate Limits of Integrated Electronics
A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation
29.2 A 0.021µm 2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery
10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer
IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications
A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb/s Communications
22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS
Will ADCs overtake binary frontends in backplane signaling?
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS
19.1 Receiver with >20MHz bandwidth self-interference cancellation suitable for FDD, co-existence and full-duplex applications
6.1 A Low-Power and Low-Cost 14nm FinFET RFIC Supporting Legacy Cellular and 5G FR1
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture
24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio
4.5 A 64Gb/s 1.4pJ/b/element 60GHz 2×2-Element Phased-Array Receiver with 8b/symbol Polarization MIMO and Spatial Interference Tolerance
Bubble Razor: An architecture-independent approach to timing-error detection and correction
A 2.5-to-3.3GHz CMOS Class-D VCO
5G Wireless Communication: An Inflection Point
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics
A 1.1V 5-to-6GHz reduced-component direct-conversion transmit signal path in 45nm CMOS
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes
A 263GHz 32-Channel EPR-on-a-Chip Injection-Locked VCO-Array
30.1 A Scalable N-Step Equal Split SSHI Piezoelectric Energy Harvesting Circuit Achieving 1170% Power Extraction Improvement and 22nA Quiescent Current with a $\mathbf{1\mu{H}-{to}-10\mu H}$ Low Q Inductor
17.8 A 90.5%-Efficiency 28.7µ VRMS-Noise Bipolar-Output High-Step-Up SC DC-DC Converter with Energy-Recycled Regulation and Post-Filtering for ±15V TFT-Based LAE Sensors
A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS
A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation
A Rectifier-Less Piezoelectric Energy-Harvesting Interface with a Sense & Track MPPT Achieving Single-Cycle Convergence and 568% Shock Power Improvement
A neural stimulator front-end with arbitrary pulse shape, HV compliance and adaptive supply requiring 0.05mm 2 in 0.35μm HVCMOS
A 28nm 18.1µJ /Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assisted Computing
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics
System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV
32.2 Self-Tunable Phase-Shifted SECE Piezoelectric Energy-Harvesting IC with a 30nW MPPT Achieving 446% Energy-Bandwidth Improvement and 94% Efficiency
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS
A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications
A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiver
Beyond CMOS - emerging technologies
17.1 Omnidirectional Magnetoelectric Power Transfer for Miniaturized Biomedical Implants via Active Echo
An integrated power supply system for low-power 3.3V electronics using on-chip polymer electrolyte membrane (PEM) fuel cells
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range
Surface and Tangible Computing, and the "Small" Matter of People and Design
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10 12 Write Endurance and Integrated Margin-Expansion Schemes
8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection
A 14.5mm 2 8nW -59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications
A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step
Virtual Rotating Gesture Recognizable Touch Readout IC for 1.26" Circular Touch Screen Panel
Session 9 overview: High-performance wireless
20.8 Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing
A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS
A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area
A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion
ASIC for a resonant wireless pressure-sensing system for harsh environments achieving ±2% error between -40 and 150°C using Q-based temperature compensation
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX
A 76fsrms Jitter and -40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
A QVGA-range image sensor based on buried-channel demodulator pixels in 0.18μm CMOS with extended dynamic range
A 90nm 12ns 32Mb 2T1MTJ MRAM
29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration
29.5 A Portable 14GHz Dual-Mode Pulse and Continuous-Wave Electron Paramagnetic Resonance Spectrometer Using a Subharmonic Direct Conversion Receiver
A 90Vpp 720MHz GBW linear power amplifier for ultrasound imaging transmitters in BCD6-SOI
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC