yusuke1997/dblp-id-title huggingface dataset:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out
A Built-in Self-Test Method for Write-only Content Addressable Memories
Test as a Key Enabler for Faster Yield Ramp-Up
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads
A built-in scheme for testing and repairing voltage regulators of low-power srams
A novel hybrid delay testing scheme with low test power, volume, and time
Power Constrained Test Scheduling with Dynamically Varied TAM
Special session on machine learning for test and diagnosis
Assessing SRAM test coverage for sub-micron CMOS technologies
A statistical model for fault coverage analysis
A New Method for Software Test Data Generation Inspired by D-algorithm
Comprehensive online defect diagnosis in on-chip networks
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
A New Algorithm for Dynamic Faults Detection in RAMs
Quiescent current estimation based on quality requirements
38th IEEE VLSI Test Symposium, VTS 2020, San Diego, CA, USA, April 5-8, 2020
A Comparative Study of Pre-bond TSV Test Methodologies
New topic session 7B: Challenges and opportunities in test and design for test (DFT) of MEMS sensors
A self-driven test structure for pseudorandom testing of non-scan sequential circuits
Built-In Reseeding for Serial Bist
Online information utility assessment for per-device adaptive test flow
Board-Level Functional Fault Identification using Streaming Data
Fabrication and testing of large-area flexible electronics for displays and sensor arrays
A sampling technique for diagnostic fault simulation
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance
Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection
Tracing the best test mix through multi-variate quality tracking
An approach for designing self-checking logic using residue codes
On completely robust path delay fault testable realization of logic functions
Fault Detection and Diagnosis of Interconnects of Random Access Memories
Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing
A structured design for test methodology
Layout-Based Dual-Cell-Aware Tests
34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016
Contactless test access mechanism for TSV based 3D ICs
Hardware Test: Can We Learn from Software Testing?
Testing methods for a write-assist disturbance-free dual-port SRAM
Testability Alternatives Exploration through Functional Testing
Security of emerging non-volatile memories: Attacks and defenses
Self-adaptive power gating with test circuit for on-line characterization of energy inflection activity
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits
Reliable edge machine learning hardware for scientific applications
A novel technique for interdependent trim code optimization
Multiple redundancy removal during test generation and synthesis
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller
High Level Synthesis of Degradable ASICs Using Virtual Binding
Effective concurrent test for a parallel-input multiplier using modulo 3
Distributed dynamic partitioning based diagnosis of scan chain
A dynamic reconfiguration mechanism to increase the reliability of GPGPUs
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems
Testing and Diagnosing Embedded Content Addressable Memories
Implicit functional testing for analog circuits
Detection of Temperature Sensitive Defects Using ZTC
Built-in parametric test for controlled impedance I/Os
An experimental evaluation of the differential BICS for I DDQ testing
Increasing testability by clock transformation (getting rid of those darn states)
An investigation of circuit partitioning for parallel test generation
36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018
Optimized Stress Testing for Flexible Hybrid Electronics Designs
Innovative practices on functional testing and fault simulation for FuSa
Efficient Transparency Extraction and Utilization in Hierarchical Test
Testing the impact of process defects on ECL power-delay performance
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults
On compacting test sets by addition and removal of test vectors
Efficient built-in self test of regular logic characterization vehicles
An Approach to Modeling and Testing Memories and Its Application to CAMs
On New Current Signatures and Adaptive Test Technique Combination
Implication and Evaluation Techniques for Proving Fault Equivalence
Efficient parallel testing: A configurable and scalable broadcast network design using IJTAG
Test of RAM-based FPGA: methodology and application to the interconnect
Efficient generation of parametric test conditions for AMS chips with an interval constraint solver
1149.4 Based On-Line Quiescent State Monitoring Technique
Performance Test Case Generation for Microprocessors
Special session on reliability and vulnerability of neuromorphic computing systems
Logic BIST and Scan Test Techniques for Multiple Identical Blocks
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms
Exploiting Regularity for Inductive Fault Analysis
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers
Chip Aging and Double Transition Faults
Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks
UPF-based formal verification of low power techniques in modern processors
On the application of local circuit transformations with special emphasis on path delay fault testability
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm
Understanding Power Supply Droop during At-Speed Scan Testing
A Reconfigurable Shared Scan-in Architecture
Design of Redundant Systems Protected Against Common-Mode Failures
On the Use of Fault Dominance in n-Detection Test Generation
Synthesis of locally exhaustive test pattern generators
3D-IC interconnect test, diagnosis, and repair
DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links
A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard
Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip
Improving accuracy of on-chip diagnosis via incremental learning
Innovative Practices Session at VLSI Test Symposium 2024: Analog Testing Technologies for Digital Exploding Society
On Improving the Accuracy Of Multiple Defect Diagnosis
Wafer Pattern Recognition Using Tucker Decomposition
Redundancy removal and simplification of combinational circuits
VLSI procurement and qualification: NASA/GSFC experience, issues and concerns
Special session on quantum systems: Next challenges in design, test, integration
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms
An efficient method to screen resistive opens under presence of process variation
Special Session 8: New Topics: At-Speed Testing in the Face of Process Variations
SCAPEgoat: Side-channel Analysis Library
A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric
Enhancing online error detection through area-efficient multi-site implications
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions
Innovation Practices Track: Testability and Dependability of AI Hardware and Autonomous Systems
Towards a cost-effective hardware trojan detection methodology
Testing High Speed VLSI Devices Using Slower Testers
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
Measurement of Phase and Frequency Variations in Radio-Frequency Signal
Improving diagnosis resolution of a fault detection test set
Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN)
On identifying undetectable and redundant faults in synchronous sequential circuits
Self-test in a VCM driver chip
Electromigration Reliability Analysis of SRAM-based Register Files in GPUs and AI Accelerators
SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security Integration
Building trust in 3PIP using asset-based security property verification
Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise
Random pattern testability of memory control logic
Test compaction by test cube merging for four-way bridging faults
Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective
Innovative practices session 10C formal verification practices in industry
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models
Defect Characterization and Testing of Skyrmion-Based Logic Circuits
Fault tolerant nanoarray circuits: Automatic design and verification
An asynchronous totally self-checking two-rail code error indicator
Testability of floating gate defects in sequential circuits
Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system design
Small-delay defects detection under process variation using Inter-Path Correlation
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
Case Study: Efficient SDD test generation for very large integrated circuits
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding
Fuzz Wars: The Voltage Awakens - Voltage-Guided Blackbox Fuzzing on FPGAs
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
Comparison between the dynamic behavior of maximum length and cyclic shift registers
Special Session: Test Impact of Multi-Die Packages
Defect diagnosis based on DFM guidelines
On Delay-Untestable Paths and Stuck-Fault Redundancy
Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns
29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA
IDDQ Testing of Opens in CMOS SRAMs
Enhanced algorithm of combining trace and scan signals in post-silicon validation
Built-In TPG with Designed Phaseshifts
No Fault Found: The root cause
Incorporating IDDQ testing in BIST: improved coverage through test diversity
Modeling the effects of imperfect production testing on reconfigurable VLSI chips
23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA
Levelized low cost delay test compaction considering IR-drop induced power supply noise
Innovation Practices Track: Advances on Silicon Lifecycle Reliability, Safety and Security
Test Technology Technical Council (TTTC)
Isomorph-redundancy in sequential circuits
Defects and Faults in Quantum Cellular Automata at Nano Scale
A New Bare Die Test Methodology
Generation of high quality tests for functional sensitizable paths
Cluster-Based Test Architecture Design for System-on-Chip
Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification
On-chip current sensing circuit for CMOS VLSI
Accelerated path delay fault simulation
High Precision Adaptive Calibration Feedback in RF Front-end for Digital Pre-distortion Application
Faulty chip identification in a multi chip module system
Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging *
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression
A framework for fast test generation at the RTL
VTS 2004 Best Panel Award
Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures
On a New Outlier Rejection Technique
A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADC
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
Power-safe test application using an effective gating approach considering current limits
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs
A Hybrid Protection Scheme for Reconfigurable Scan Networks
A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags
Sequence Triggered Hardware Trojan in Neural Network Accelerator
Experimental Results for Slow-Speed Testing
Partial scan designs without using a separate scan clock
Computer-aided failure analysis of VLSI circuits using I DDQ testing
Sensing temperature in CMOS circuits for Thermal Testing
On the decline of testing efficiency as fault coverage approaches 100%
Bit line coupling memory tests for single-cell fails in SRAMs
GHz RF Front-end Bandwidth Time Domain Measurement
On CMOS bridge fault modeling and test pattern evaluation
Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures
On the maximum value of aliasing probabilities for single input signature registers
A self-checking ALU design with efficient codes
Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs
A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response Analyses
Innovative Practices Track: Innovative Analog Circuit Testing Technologies
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core
Input and output encoding techniques for on-line error detection in combinational logic circuits
Innovative practices session 11C: Resilience
Test pattern generation for I DDQ : increasing test quality
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic
Full Open Defects in Nanometric CMOS
Detectability Conditions for Interconnection Open Defect
TMO: A new class of attack on cipher misusing test infrastructure
Innovative Practices Track: Session 4 AI Applications in Test
Segmented Addressable Scan Architecture
Design for diagnosability of linear digital filters using time-space expansion
Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
An apparatus for pseudo-deterministic testing
An analysis of feedback bridging faults in MOS VLSI
Interconnect Testing for Networks on Chips
Delay Test Quality Evaluation Using Bounded Gate Delays
On n-detection test sequences for synchronous sequential circuits343
Net diagnosis using stuck-at and transition fault models
New advances in path delay fault testing of combinational circuits
On the check base selection problem for fast adders
A Test Point Insertion Algorithm for Mixed-Signal Circuits
Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model
Prediction of Analog Performance Parameters Using Oscillation Based Test
Test point insertion based on path tracing
Test Set Reordering Using the Gate Exhaustive Test Metric
Test cost and test power conflicts: EDA perspective
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults
A 4-GHz universal high-frequency on-chip testing platform for IP validation
Innovative practices session 2C: New technologies, new challenges - 2
Innovative practices session 6C DFT for functional safety
A Built-In Self-Repair Scheme for NOR-Type Flash Memory
CHEF: CHaracterizing Elusive Logic Circuit Failures
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips
37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019
Test generation and design-for-testability for flow-based mVLSI microfluidic biochips
Machine Learning Based Static and Dynamic Error Calibration in Data Converters
Efficient Fault Collapsing via Generalized Dominance Relations
Testing Embedded Cores Using Partial Isolation Rings
Voltage Tuning for Reliable Computation in Emerging Resistive Memories
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
Test planning and test access mechanism design for stacked chips using ILP
A new approach for testing artificial neural networks
Stuck-Open Fault Leakage and Testing in Nanometer Technologies
Innovative practices session 2C: Design, fabrication and test of flexible electronics
32nd IEEE VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014
Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators
Three-pattern tests for delay faults
Test and Diagnosis of Word-Oriented Multiport Memories
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
Test-point insertion efficiency analysis for LBIST applications
A new functional fault model for system-level descriptions
A guided debugger-based fault injection methodology for assessing functional test programs
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals
Evaluation of detectability in BIST environment
A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs
Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization
Boundary-scan: beyond production test
Application of signal and noise theory to digital VLSI testing
Improving the theory of truth table verification of iterative logic arrays
A new test pattern generation method for delay fault testing
A Scheme for On-Chip Timing Characterization
Special session 4C: Thesis research poster session
An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
Design Validation: Formal Verification vs. Simulation vs. Functional Testing
A structured and scalable test access architecture for TSV-based 3D stacked ICs
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model
Innovative practices session 10C: Advances in DFT and compression
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array
On Cyclic Scan Integrity Tests for EDT-based Compression
Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment
Constructive Derivation of Analog Specification Test Criteria
ICAT: incremental combinational ATPG
Machine-learning based Blind Digital Calibration of Time-Interleaved ADC
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator
Carafe: an inductive fault analysis tool for CMOS VLSI circuits
Expedited response compaction for scan power reduction
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access
Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detector
Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning
Average Leakage Current Estimation of CMOS Logic Circuits
ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing
Ordering of analog specification tests based on parametric defect level estimation
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen
Efficient and product-representative timing model validation
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
Analysis of I DDQ detectable bridges in combinational CMOS circuits
A new delay testing signal scheme robust to power distribution network impedance variation
Special Session: Security Verification of Microelectronic Systems with Integrated AI Accelerators: Scope, Practice, and Challenges
Detecting Intra-Word Faults in Word-Oriented Memories
Quantitative analysis of very-low-voltage testing
Fault-tolerant Neuromorphic Computing with Functional ATPG for Post-manufacturing Re-calibration
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs
Experiences in side channel and testing based Hardware Trojan detection
Reliability Beyond GHz
SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLS
Self-exercising self testing k-order comparators
Efficient Structured Scan Patterns Retargeting for Hierarchical IEEE 1687 Networks
25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA
Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing
Derating based hardware optimizations in soft error tolerant designs
BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability Detection
Innovative practices session 7C: Mixed signal test and debug
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
Special Session: Effective In-field Testing of Deep Neural Network Hardware Accelerators
Revisiting Microelectronics Resilience and Reliability in the Era of AI
Built-in self-test design for large embedded PLAs
19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA
Low-sensitivity to process variations aging sensor for automotive safety-critical applications
From Design to Inspection: Can Inspection-aware Design Enhance Reliability in Advanced Packaging?
Low power compression architecture
Low cost test and tuning of RF circuits and systems
Drop-Connect as a Fault-Tolerance Approach for RRAM-based Deep Neural Network Accelerators
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
Design-for-Testability for Digital Microfluidic Biochips
Automatic synthesis of DUT board circuits for testing of mixed signal ICs
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus
Targeted Custom High-Voltage Stress Patterns on Automotive Designs
CBM-TI: Code-Based Masking against Glitches by Hybridization with Threshold Implementation
Innovative Practices Track: Test of 3D ICs & Chiplets
Hot topic session 12B: Stay relevant with standards-based DFT
New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyond
Segment delay faults: a new fault model
Improvement of SRAM-based failure analysis using calibrated Iddq testing
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design
A novel test generation approach for parametric faults in linear analog circuits
Modeling and test generation for combinational hardware Trojans