yusuke1997/dblp-id-title huggingface dataset:
Dynamic I/O power management for hard real-time systems
Knowledge-based design space exploration of wireless sensor networks
Automatic exploration of VLIW processor architectures from a designer's experience based specification
Communication optimization for thermal reliable optical network-on-chip: work-in-progress
Co-design in the wilderness
First results with eBlocks: embedded systems building blocks
Symbolic model checking of Dual Transition Petri Nets
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support
Task response time optimization using cost-based operation motion
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules
A path analysis based partitioning for time constrained embedded systems
Embedded market: challenges and opportunities
LOCS: a low overhead profiler-driven design flow for security of MPSoCs
Application specific non-volatile primary memory for embedded systems
Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design
Cache-aware optimization of BAN applications
Performance estimation for embedded systems with data and control dependencies
Generation of TLM testbenches using mutation testing
Extended design reuse trade-offs in hardware-software architecture mapping
Energy savings through compression in embedded Java environments
System-level mitigation of WID leakage power variability using body-bias islands
Increasing the throughput of an adaptive router in network-on-chip (NoC)
Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips
Retention state-aware energy management for efficient nonvolatile processors: work-in-progress
Trade-offs in the design of mixed hardware-software systems-a perspective from industry
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009
Optimal functional-unit assignment and buffer placement for probabilistic pipelines
CASTLE: an interactive environment for HW-SW Co-Design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
Interface models
Key research problems in NoC design: a holistic perspective
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
Metronomy: A function-architecture co-simulation framework for timing verification of cyber-physical systems
Operation tables for scheduling in the presence of incomplete bypassing
Heatmap-Aware Low-Cost Design to Resist Adversarial Attacks: Work-in-Progress
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis
Pointer re-coding for creating definitive MPSoC models
Memory accesses management during high level synthesis
Empirical comparison of software-based error detection and correction techniques for embedded systems
Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives
BPR: fast FPGA placement and routing using macroblocks
Power-aware communication optimization for networks-on-chips with voltage scalable links
Methodology for attack on a Java-based PDA
Thread warping: a framework for dynamic synthesis of thread accelerators
Accurate online power estimation and automatic battery behavior based power model generation for smartphones
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors
Architectural analysis and instruction-set optimization for design of network protocol processors
Software Architecture Synthesis for Retargetable Real-time Embedded Systems
Concurrent architecture and schedule optimization of time-triggered automotive systems
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling
Automated data cache placement for embedded VLIW ASIPs
Low energy security optimization in embedded cryptographic systems
BPNet: Branch-pruned conditional neural network for systematic time-accuracy tradeoff in DNN inference: work-in-progress
Design of multi-tasking coprocessor control for Eclipse
Automotive networks: are new busses and gateways the answer or just another challenge?
Improving superword level parallelism support in modern compilers
ASDEN: a comprehensive design framework vision for automotive electronic control systems
A greedy buffer allocation algorithm for power-aware communication in body sensor networks
Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management
Automatic customization of device drivers for IP-cores used with assorted CPU organizations
A multiobjective optimization model for exploring multiprocessor mappings of process networks
Flexible modeling environment for embedded systems design
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress
A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware
On compile-time evaluation of process partitioning transformations for Kahn process networks
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
A HW/SW co-design environment for multi-media equipments development using inverse problem
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators
Testbenches for advanced TLM verification
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture
Design and defect tolerance beyond CMOS
Bottom-up performance analysis considering time slice based software scheduling at system level
Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping
Iterative cache simulation of embedded CPUs with trace stripping
PreGC: Pre-migrating valid pages to relieve performance cliff of 3D solid-state drives: work-in-progress
From self-aware building blocks to self-organizing systems with hierarchical agent-based adaptation
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006
Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models
Lifetime improvement through runtime wear-based task mapping
Providing accurate event models for the analysis of heterogeneous multiprocessor systems
Programmers' views of SoCs
Synthesizing operating system based device drivers in embedded systems
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
Design space minimization with timing and code size optimization for embedded DSP
Configuration-level hardware/software partitioning for real-time embedded systems
Frequency interleaving as a codesign scheduling paradigm
Co-design of security-critical real-time systems to prevent fault injection attacks: work-in-progress
Thermal-aware high-level synthesis based on network flow method
Trends, challenges and needs for lattice-based cryptography implementations: special session
Towards the application of flask security architecture to SoC design: work-in-progress
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors
Automatic phase detection for stochastic on-chip traffic generation
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages
System-level design automation tools for digital microfluidic biochips
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors
Design and programming of embedded multiprocessors: an interface-centric approach
Fast simulation of systems embedding VLIW processors
Saving energy without defying deadlines on mobile GPU-based heterogeneous systems
Code compression as a variable in hardware/software co-design
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs
A distributed smart camera apparatus to enable scene immersion: work-in-progress
A Codesign Environment Supporting Hardware/Software Modeling at Different Levels of Detail
A practical tool box for system level communication synthesis
A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress
Improving platform-based system synthesis by satisfiability modulo theories solving
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Video analytics from edge to server: work-in-progress
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
Design and architectures for dependable embedded systems
A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem
Compiler parallelization of C programs for multi-core DSPs with multiple address spaces
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems
Q-learning based routing for transiently powered wireless sensor network: work-in-progress
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
System-level partitioning with uncertainty
A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
LearnLoc: A framework for smart indoor localization with embedded mobile devices
Efficient self-learning techniques for SAT-based test generation
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS 2017, Seoul, Republic of Korea, October 15-20, 2017
RTOS scheduling in transaction level models
The priority queue as an example of hardware/software codesign
An Object-Oriented Communication Library for Hardware-Software CoDesign
Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems
Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core
Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint
Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor
Software/hardware Co-Design in the MuSE environment
A core flight software system
A dynamic dataflow model suitable for efficient mixed hardware and software implementations of DSP applications
Hardware/software co-design for a wireless sensor network platform
On leveraging approximations for exact system-level design space exploration: work-in-progress
A distributed interleaving scheme for efficient access to WideIO DRAM memory
Facilitating reuse in hardware models with enhanced type inference
Hardware and software architectures for the CELL processor
An accurate and flexible early memory system power evaluation approach using a microcomponent method
Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systems
The RISC-V instruction set architecture optimization and fixed-point math library co-design: work-in-progress
Building heterogeneous reconfigurable systems with a hardware microkernel
R 2 Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores
An efficient direct mapped instruction cache for application-specific embedded systems
A strongly polynomial-time algorithm for over-constraint resolution: efficient debugging of timing constraint violations
How standards will enable hardware/software co-design
The design context of concurrent computation systems
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
How to enable software isolation and boost system performance with sub-block erase over 3D flash memory
Power-performance trade-offs for reconfigurable computing
Static analysis of processor stall cycle aggregation
Optimal acyclic fine-grain scheduling with cache effects for embedded and real time systems
Hardware/software co-design for high performance computing: challenges and opportunities
parSC: synchronous parallel systemc simulation on multi-core host architectures
Are current ESL tools meeting the requirements of advanced embedded systems?
Locality-conscious process scheduling in embedded systems
Specification and OS-based implementation of self-adaptive, hardware/software embedded systems
Exploiting data-redundancy in reliability-aware networked embedded system design
HEFT: A hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs
ARGO: Aging-aware GPGPU register file allocation
Automatic selection of application-specific instruction-set extensions
Soft errors: the hardware-software interface
A task remapping technique for reliable multi-core embedded systems
Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs
Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems
Zero and data reuse-aware fast convolution for deep neural networks on GPU
Extending the SystemC synthesis subset by object-oriented features
Compiler-directed code restructuring for reducing data TLB energy
Fault-aware application scheduling in low-power embedded systems with energy harvesting
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
TSP: Thermal Safe Power - Efficient power budgeting for many-core systems in dark silicon
SEAS: a system for early analysis of SoCs
A practical methodology to validate the statistical behavior of bloom filters
Reliable multiprocessor system-on-chip synthesis
ILP optimal scheduling for multi-module memory
Flattening-based mapping of imperfect loop nests for CGRAs?
Enhanced code density of embedded CISC processors with echo technology
Capacity metric for chip heterogeneous multiprocessors
Early estimation of the size of VHDL projects
Power estimation for architectural exploration of HW/SW communication on system-level buses
Big/little deep neural network for ultra low power inference
Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters
Modifying Min-Cut for Hardware and Software Functional Partitioning
Internet of things or threats?: on building trust in IoT (keynote)
Scheduling with optimized communication for time-triggered embedded systems
A novel parallel deadlock detection algorithm and architecture
2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015
TotalProf: a fast and accurate retargetable source code profiler
Software acceleration using programmable logic: is it worth the effort?
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study
System-level memory optimization for high-level synthesis of component-based SoCs
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003
Compiling code accelerators for FPGAs
Deriving hard real-time embedded systems implementations directly from SDL specifications
A codesign case study in computer graphics
Memory-efficient distribution of regular expressions for fast deep packet inspection
A loop accelerator for low power embedded VLIW processors
Embedded software development on top of transaction-level models
Deterministic service guarantees for nand flash using partial block cleaning
Battery discharge aware energy feasibility analysis
A DP-network for optimal dynamic routing in network-on-chip
Improving polyhedral code generation for high-level synthesis
From ESL 2010 to ESL 2015
Scheduling hardware/software systems using symbolic techniques
Transaction level modeling: an overview
Deriving process networks from weakly dynamic applications in system-level design
Hardware synthesis from a recursive functional language
A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study
Introducing assume-guarantee contracts for verifying robotic applications: work-in-progress
A simulation framework for domain-specific system-on-chips: work-in-progress
A real-time, energy-efficient system software suite for heterogeneous multicore platforms
Logic optimization and code generation for embedded control applications
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform
DistRM: distributed resource management for on-chip many-core systems
Dynamic counters and the efficient and effective online power management of embedded real-time systems
You can catch more bugs with transaction level honey
Efficient behavior-driven runtime dynamic voltage scaling policies
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
A tiny-capacitor-backed non-volatile buffer to reduce storage writes in smartphones
Making the internet-of-things a reality: from smart models, sensing and actuation to energy-efficient architectures
3D nanosystems enable embedded abundant-data computing: special session paper
Optimizing the memory bandwidth with loop fusion
WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress
Graph based communication analysis for hardware/software codesign
Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress
UML and model-driven development for SoC design
RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores
Minimizing system modification in an incremental design approach
Automatic generation of transaction level models for rapid design space exploration
Pack instruction generation for media pUsing multi-valued decision diagram
A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress
Performance and power analysis of computer systems
TigerSwitch: a case study in embedded computing system design
Instruction-level power estimation for embedded VLIW cores
A multicast inter-task communication protocol for embedded multiprocessor systems
Peer-based multithreaded executable co-specification
Software optimization for MPSoC: a mpeg-2 decoder case study
Hardware/software partitioning of software binaries: a case study of H.264 decode
Achieving fast lane detection of autonomous driving by CNN based differentiation: work-in-progress
FlexPath NP: a network processor concept with application-driven flexible processing paths
Fast online synthesis of generally programmable digital microfluidic biochips
An MPEG-2 decoder case study as a driver for a system level design methodology
Novel architecture for loop acceleration: a case study
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Transformation of SDL specifications for system-level timing analysis
An Event-Driven Multi-Threading Architecture for Embedded Systems
Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform
Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations
Compaan: deriving process networks from Matlab for embedded signal processing architectures
An architectural level design methodology for embedded face detection
FEMU: a firmware-based emulation framework for SoC verification
Driving agenda for systems research
On-the-fly computing: self-aware heterogeneous multi-cores
Future challenges in embedded systems
Retargetable generation of TLM bus interfaces for MP-SoC platforms
Performance improvement of block based NAND flash translation layer
PRET DRAM controller: bank privatization for predictability and temporal isolation
HSAemu - A full system emulator for HSA platforms
ADEL: an automatic detector of energy leaks for smartphone applications
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dominator homomorphism based code matching for source-level simulation of embedded software
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks
Demand paging for OneNAND TM Flash eXecute-in-place
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
Specification-based compaction of directed tests for functional validation of pipelined processors
pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment
Leveraging microarchitectural side channel information to efficiently enhance program control flow integrity
A tuneable software cache coherence protocol for heterogeneous MPSoCs
Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation
A security monitoring service for NoCs
TLM/network design space exploration for networked embedded systems
Design technology challenges for system and chip level designs in very deep submicron technologies
Memory access optimizations in instruction-set simulators
A method to derive application-specific embedded processing cores
Designing real-time H.264 decoders with dataflow architectures
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012
Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems
Communication speed selection for embedded systems with networked voltage-scalable processors
Using static analysis for coverage extraction fromemulation/prototyping platforms
Computer security by hardware-intrinsic authentication
A generic wrapper architecture for multi-processor SoC cosimulation and design
Revisiting wear leveling design on compression applied 3D NAND flash memory: work-in-progress
Hardware-software bipartitioning for dynamically reconfigurable systems
Power optimization of system-level address buses based on software profiling
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Statistical physics approaches for network-on-chip traffic characterization
Evaluating register file size in ASIP design
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
On the impact of manufacturing process variations on the lifetime of sensor networks
CODES and co-design: a look back and a look forward
Automated, retargetable back-annotation for host compiled performance and power modeling
A modular simulation framework for architectural exploration of on-chip interconnection networks
Co-design of interleaved memory systems
Correlation Analysis of Discrete Motions
The Landform Reference Ontology (LFRO): A Foundation for Exploring Linguistic and Geospatial Conceptualization of Landforms (Short Paper)
Identifying Resilient Communities in Road Networks: A Path-Based Embedding Approach
Identifying Maps on the World Wide Web
11th International Conference on Geographic Information Science, GIScience 2021, Poznań, Poland (Virtual Conference), September 27-30, 2021 - Part II
Geographic Information Science, 6th International Conference, GIScience 2010, Zurich, Switzerland, September 14-17, 2010. Proceedings
A Conceptual Data Model for Trajectory Data Mining