yusuke1997/dblp-id-title huggingface dataset:
Improvement of saturation characteristics of a frequency-demodulation CMOS image sensor
A dynamically phase adjusting PLL with a variable delay
Static timing: Back to our roots
Post-routing layer assignment for double patterning
Towards the logic defect diagnosis for partial-scan designs
Multi-mode pipelined MPSoCs for streaming applications
Functional decomposition using majority
NVPsim: A simulator for architecture explorations of nonvolatile processors
Conversion of reference C code to dataflow model: H.264 encoder case study
A framework for estimating NBTI degradation of microarchitectural components
Topology exploration for energy efficient intra-tile communication
A slew-rate controlled output driver with one-cycle tuning time
Deep Learning for Mask Synthesis and Verification: A Survey
Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation
Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances
Minimizing total power by simultaneous Vdd/Vth assignment
On the Viability of Decision Trees for Learning Models of Systems
CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper)
On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA
Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS
A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system
Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers
Customized SIMD unit synthesis for system on programmable chip: a foundation for HW/SW partitioning with vectorization
Towards Design Optimization of Analog Compute Systems
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses
MCMM clock tree optimization based on slack redistribution using a reduced slack graph
Mask cost reduction with circuit performance consideration for self-aligned double patterning
The alarms project: A hardware/software approach to addressing parameter variations
Delay Optimization of Combinational Logic by AND-OR Path Restructuring
Automatic insertion of airgap with design rule constraints
Emerging sensing techniques for emerging memories
Super low power 8-bit CPU with pass-transistor logic
Accurate and inexpensive performance monitoring for variability-aware systems
A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs
Relaxed synchronization technique for speeding-up the parallel simulation of multiprocessor systems
A novel basis for logic rewriting
A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform
Parallel cross-layer optimization of high-level synthesis and physical design
Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic
TRECO: dynamic technology remapping for timing engineering change orders
Routing with graphene nanoribbons
Synthesis for SoC architecture using VCores
Future reconfigurable computing system
On the interplay of loop caching, code compression, and cache configuration
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter
Logic synthesis for cellular architecture FPGAs using BDDs
Lifetime-aware design methodology for dynamic partially reconfigurable systems
Adaptive fuzzy control scheduling of window-constrained real-time systems
TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization
HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths
Integrated interconnect circuit modeling for VLSI design
Pruning-based trace signal selection algorithm
Co-design of cyber-physical systems via controllers with flexible delay constraints
A fast method to derive minimum SOPs for decomposable functions
CODA: A concurrent online delay measurement architecture for critical paths
IBM's 50 Million gate ASICs
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information
Efficient ML-Based Transient Thermal Prediction for 3D-ICs
Towards on-chip fault-tolerant communication
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures
A mapping from sequence-pair to rectangular dissection
MMP: a novel placement algorithm for combined macro block and standard cell layout design
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption
Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data
Compiling SU(4) quantum circuits to IBM QX architectures
Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime
Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011
Microarchitecture evaluation with floorplanning and interconnect pipelining
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs
RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing
Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis
DFM reality in sub-nanometer IC design
Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration
PRR: A low-overhead cache replacement algorithm for embedded processors
NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks
From RTL to silicon: The case for automated debug
Retargetable estimation scheme for DSP architecture selection
Automatic synthesis and scheduling of multirate DSP algorithms
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system
Improving the mapping of reversible circuits to quantum circuits using multiple target lines
Refinement strategies for verification methods based on datapath abstraction
A symbolic approach for mixed-signal model checking
SIMULTime: Context-sensitive timing simulation on intermediate code representation for rapid platform explorations
Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes
Forward discrete probability propagation method for device performance characterization under process variations
On the control-subroutine implementation of subprogram synthesis
Hybrid binary-unary hardware accelerator
Reverse BDD-based synthesis for splitter-free optical circuits
Some remarks about spectral transform interpretation of MTBDDs and EVBDDs
Timing Resilience for Efficient and Secure Circuits
A multilevel ℌ-matrix-based approximate matrix inversion algorithm for vectorless power grid verification
Flip-chip routing with IO planning considering practical pad assignment constraints
Intra-vehicle network routing algorithm for wiring weight and wireless transmit power minimization
How Foundry can Help Improve your Bottom-Line? Accuracy Matters!
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005
Not necessarily more switches more routability [sic.]
Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics
An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Data Sanitization on eMMCs
A 3Gb/s 2.08mm 2 100b error-correcting BCH decoder in 0.13µm CMOS process
The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis
Walking pads: Fast power-supply pad-placement optimization
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems
VLSI implementation of a real-time operating system
Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper)
Exploiting coding techniques for logic synthesis of reversible circuits
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee
Probabilistic design in spintronic memory and logic circuit
Synthesis and simulation of digital demodulator for infrared data communication
(Invited paper) energy delivery for self-powered IoT devices
Roles of funding agencies in technology-driven economic development
A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core
A Hybrid Power Model for RTL Power Estimation
MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization
PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis
BddCut: Towards Scalable Symbolic Cut Enumeration
Multi-way partitioning using bi-partition heuristics
A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA
ADMM attack: an enhanced adversarial attack for deep neural networks with undetectable distortions
Minimum implant area-aware placement and threshold voltage refinement
Efficient Computing Platform Design for Autonomous Driving Systems
HS3DPG: Hierarchical simulation for 3D P/G network
An extension of the generalized Hamiltonian method to S -parameter descriptor systems
Challenges in integration of diverse functionalities on CMOS
WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory
APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning
LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration
REMIC: design of a reactive embedded microprocessor core
A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects
Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design
Optimized Array Index Computation in DSP Programs
Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devices
2.5D system integration: a design driven system implementation schema
A low-power triple-mode sigma-delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters
Resource sharing in pipelined CDFG synthesis
CAMO: A novel cache management organization for GPGPUs
Incremental power network analysis using backward random walks
New directions in compiler technology for embedded systems (embedded tutorial)
Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
An autonomous decentralized mechanism for energy interchanges with accelerated diffusion based on MCMC
Vision Control Unit in Fully Self Driving Vehicles using Xilinx MPSoC and Opensource Stack
Fixing Double Patterning violations with look-ahead
Routing path reuse maximization for efficient NV-FPGA reconfiguration
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
Utility of the OpenAccess database in academic research
A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization
Power Consumption in XOR-Based Circuits
On real-time STM concurrency control for embedded software with improved schedulability
A generalized quadrature bandpass sampling in radio receivers
A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial parts
Boosting the Performance of Transistor-Level Circuit Simulation with GNN
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor
A hardware-software co-simulator for embedded system design and debugging
Pulser gating: A clock gating of pulsed-latch circuits
A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling
Thermal modeling for energy-efficient smart building with advanced overfitting mitigation technique
Ferroelectrics: From Memory to Computing
Minimizing clock latency range in robust clock tree synthesis
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management
3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
HOGE: Homomorphic Gate on An FPGA
Prediction of LC-VCOs' tuning curves with period calculation technique
ECO-system: Embracing the Change in Placement
ADEPT-Z: Zero-Shot Automated Circuit Topology Search for Pareto-Optimal Photonic Tensor Cores
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio
High-level synthesis under multi-cycle interconnect delay
Design and implementation of a video-oriented network-interface-card system
Block cache for embedded systems
Partial reluctance based circuit simulation is efficient and stable
Software-cooperative power-efficient heterogeneous multi-core for media processing
A highly efficient AES cipher chip
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications
An Efficient Structural Approach to Board Interconnect Diagnosis
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification
Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling
A High-Throughput Low-Power AES Cipher for Network Applications
Timing optimization by replacing flip-flops to latches
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs
A Circuit Design of 16x16 Multiplier Using Redundant Binary Arithmetic
LPRAM: a low power DRAM with testability
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
Panel: Best ways to use billions of devices on a chip
An oscillator-based true random number generator with process and temperature tolerance
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance
Normally-off MCU architecture for low-power sensor node
A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS
A tail-current modulated VCO with adaptive-bias scheme
FirVer: Concolic Testing for Systematic Validation of Firmware Binaries
Satisfiability and integer programming as complementary tools
Low power architecture and design techniques for mobile handset LSI Medity TM M2
Automatic functional test program generation for microprocessor verification
Merged Logic and Memory Fabrics for AI Workloads
Constraint-based platform variants specification for early system verification
Hardware-software co-design of slimmed optical neural networks
Provably optimal test cube generation using quantified boolean formula solving
A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO
A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli
Longest path selection for delay test under process variation
A scheduling algorithm for multiport memory minimization in datapath synthesis
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Aging mitigation in memory arrays using self-controlled bit-flipping technique
Fair watermarking techniques
A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver
A flexible fixed-outline floorplanning methodology for mixed-size modules
Exploring Graphical Models with Bayesian Learning and MCMC for Failure Diagnosis
Within-die process variations: How accurately can they be statistically modeled?
An introduction to SLDL and Rosetta
Efficient RT-level fault diagnosis methodology
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Invasive Computing for robotic vision
A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs
Disjoint-support Boolean decomposition combining functional and structural methods
Islands of heaters: A novel thermal management framework for photonic NoCs
Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation
Covert channels using mobile device's magnetic field sensors
Trade-off evaluation in embedded system design via co-simulation
O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs
On signal tracing in post-silicon validation
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits
Distributed reconfigurable Battery System Management Architectures
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits
Temperature-aware routing in 3D ICs
Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays
Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence
FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization
Power consumption in CMOS combinational logic blocks at high frequencies
A Hardware Software Cosimulation Backplane with Automatic Interface Generation
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells
MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications
Compiler-Guided data compression for reducing memory consumption of embedded applications
Source-level timing annotation for fast and accurate TLM computation model generation
The design of PCI bus interface
Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019
Wash optimization for cross-contamination removal in flow-based microfluidic biochips
MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits
Parallelism in Deep Learning Accelerators
Containing guardbands
Design of 385 x 385 μm 2 0.165V 270pW fully-integrated supply-modulated OOK transmitter in 65nm CMOS for glasses-free, self-powered, and fuel-cell-embedded continuous glucose monitoring contact lens
Transition-based coverage estimation for symbolic model checking
Many-to-many active cell balancing strategy design
Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faults
Negotiation-based layer assignment for via count and via overflow minimization
Thermal-Aware 3D IC Placement Via Transformation
Timing driven power gating in high-level synthesis
Development of a Support Tool for PCB Design with EMC Constraint
Adaptive remaining hop count flow control: Consider the interaction between packets
Clock tree embedding for 3D ICs
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example
Sequential dependency and reliability analysis of embedded systems
A Physical-Aware Framework for Memory Network Design Space Exploration
19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014
Hardware/software partitioning for platform-based design method
Quantization-aware Optimization Approach for CNNs Inference on CPUs
An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept
Vector-based Dynamic IR-drop Prediction Using Machine Learning
Automatic Test Generation for Linear Analog Circuits under Parameter Variations
Synthesis of low power folded programmable coefficient FIR digital filters (short paper)
A 13.56MHz CMOS active diode full-wave rectifier achieving ZVS with voltage-time-conversion delay-locked loop for wireless power transmission
Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks
COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPU
RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword Spotting
Modeling and minimization of routing congestion
Java based object oriented hardware specification and synthesis
A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Statistical Bellman-Ford algorithm with an application to retiming
Generating stable and sparse reluctance/inductance matrix under insufficient conditions
Enabling multi-layer cyber-security assessment of Industrial Control Systems through Hardware-In-The-Loop testbeds
Computing with coupled Spin Torque Nano Oscillators
A class D audio power amplifier with high-efficiency and low-distortion
A CAD tool for RF MEMS devices
Design automation 2000 (panel session): challenges for gigabit-era
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths
Wire congestion and thermal aware 3D global placement
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems
Design of vehicle position tracking system using short message services and its implementation on FPGA
Timing window wiper: A new scheme for reducing refresh power of DRAM
Data learning based diagnosis
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization
A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies
Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling
Path controllability analysis for high quality designs
A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor
FSM decomposition by direct circuit manipulation applied to low power design
Run-time power control scheme using software feedback loop for low-power real-time application
Data Path Synthesis for BIST with Low Area Overhead
A 65nm CMOS Process Li-ion Battery Charging Cascode SIDO Boost Converter with 89% Maximum Efficiency for RF Wireless Power Transfer Receiver
Knowledge Distillation in Quantum Neural Network Using Approximate Synthesis
DFM/DFY practices during physical designs for timing, signal integrity, and power
Faster projection based methods for circuit level verification
A scalable communication-aware compilation flow for programmable accelerators
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference
3D ReRAM with Field Assisted Super-Linear Threshold (FAST TM ) Selector technology for super-dense, low power, low latency data storage systems