yusuke1997/dblp-id-title huggingface dataset:
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment
Bridging the Gap Between Anomaly Detection and Runtime Verification: H-Classifiers
Exact Grading of Multiple Path Delay Faults
On the limits of machine learning-based test: A calibrated mixed-signal system case study
TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform
DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch
Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider
TIMBER: Time borrowing and error relaying for online timing error resilience
Approximating the age of RF/analog circuits through re-characterization and statistical estimation
Remote measurement of local oscillator drifts in FlexRay networks
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s
Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation
SPARX - A side-channel protected processor for ARX-based cryptography
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies
Platform-based design of wireless sensor networks for industrial applications
Systematic Design for Optimization of High-Resolution Pipelined ADCs
VHDL extensions for complex transmission line simulation
ABC: Abstract prediction Before Concreteness
Exact multi-objective design space exploration using ASPmT
ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
Computation of IP3 using single-tone moments analysis
FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural Networks
Design of Test Modules for the Analysis of MCM Interconnects
Reversible Pebbling Game for Quantum Memory Management
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification
e-Mobility the next frontier for automotive industry
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization
Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs
A black box method for stability analysis of arbitrary SRAM cell structures
Intelligent Architectures for Intelligent Computing Systems
An efficient manipulation package for Biconditional Binary Decision Diagrams
SAT-Based Techniques in System Synthesis
A HMMER hardware accelerator using divergences
EUROSERVER: Share-anything scale-out micro-server design
Training Better CNN Models for 3-D Capacitance Extraction with Neural Architecture Search
Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns
Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning
A hardware implementation of the MCAS synchronization primitive
Low-power design tools: are EDA vendors taking this matter seriously?
Hardware scheduling support in SMP architectures
HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching
Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors
Scalar replacement in the presence of multiple write accesses for high-level synthesis
A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation
Shaping a VLSI wire to minimize Elmore delay
An algorithm to find optimum support-reducing decompositions for index generation functions
Dynamically reconfigurable register file for a softcore VLIW processor
A Game-Theoretic Approach to Real-Time System Testing
The growing importance of microelectronics from a foundry perspective
Component-based design for the future
New safety critical radio altimeter for airbus and related design flow
Self-awareness in autonomous automotive systems
Temperature Effect on Delay for Low Voltage Applications
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences
Estimating functional coverage in bounded model checking
Fault diagnosis of arbiter physical unclonable function
Quater-imaginary base for complex number arithmetic circuits
Clock skew scheduling for timing speculation
Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter
Resource-constrained high-level datapath optimization in ASIP design
Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing
Distributed Grid computing Manager covering Waste Heat Reuse Constraints
Topaz: Mining high-level safety properties from logic simulation traces
DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNs
DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN
The Design of an Asynchronous VHDL Synthesizer
Lifetime adaptive ECC in NAND flash page management
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs
Panel Session - Caution Ahead: The Road to Design and Manufacturing at 32 and 22 nm
Energy efficient transceiver in wireless Network on Chip architectures
Parallel Implementation of Iterative Learning Controllers on Multi-core Platforms
Decentralized Federated Learning in Partially Connected Networks with Non-IID Data
Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks
An efficient and deterministic multi-tasking run-time environment for Ada and the Ravenscar profile on the Atmel AVR®32 UC3 microcontroller
A Methodology for System-Level Analog Design Space Exploration
READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications
Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems
Platform-specific timing verification framework in model-based implementation
Video analytics using beyond CMOS devices
Accelerating biophysical neural network simulation with region of interest based approximation
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining
Case Study: System Model of Crane and Embedded Control
Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF
Parallel Processing Architectures for Reconfigurable Systems
RDF: Reconfigurable Dataflow
Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture
Computing the full quotient in bi-decomposition by approximation
Automatic ADL-based operand isolation for embedded processors
On the efficient reduction of complete EM based parametric models
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk
IP for Embedded Robustness
Evaluation and design exploration of solar harvested-energy prediction algorithm
Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit
Minimizing Communication Conflicts in Network-On-Chip Based Processing-In-Memory Architecture
Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memories
AeroDiffusion: Complex Aerial Image Synthesis with Keypoint-Aware Text Descriptions and Feature-Augmented Diffusion Models
Automatic integration of cycle-accurate descriptions with continuous-time models for cyber-physical virtual platforms
Multi-Partner Project: Secure Hardware Accelerated Data Analytics for 6G Networks: The PRIVATEER Approach
Efficient mapping of quantum circuits to the IBM QX architectures
Design and implementation of a database filter for BLAST acceleration
A Flexible Message Passing Mechanism for Objective VHDL
Modeling and Integration of Peripheral Devices in Embedded Systems
A Template for Predictability Definitions with Supporting Evidence
A highly resilient routing algorithm for fault-tolerant NoCs
Energy-efficient in-memory database computing
SURF algorithm in FPGA: A novel architecture for high demanding industrial applications
Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection
Modeling crosstalk noise for deep submicron verification tools
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation
Cache Bandwidth Contention Leaks Secrets
VeriDevOps: Automated Protection and Prevention to Meet Security Requirements in DevOps
The connected car and its implication to the automotive chip roadmap
Enhancing Testability of System on Chips Using Network Management Protocols
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion
DeepPM: Transformer-based Power and Performance Prediction for Energy-Aware Software
Accurate high level datapath power estimation
Integration of an expert system for analogue layout synthesis into a commercial CAD framework
A Power Optimized Display Memory Organization for Handheld User Terminal
Hybrid Architectural Dynamic Thermal Management
Full-Stack Optimization for CAM-Only DNN Inference
GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction
Contention aware frequency scaling on CMPs with guaranteed quality of service
Automatic Abstraction for Worst-Case Analysis of Discrete Systems
Design and Optimization of Heterogeneous Manycore Systems Enabled by Emerging Interconnect Technologies: Promises and Challenges
Time-division Multiplexing Automata Processor
Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM
An energy-efficient 64-QAM MIMO detector for emerging wireless standards
Adaptive power management in energy harvesting systems
CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back Pressure
Exploring "temperature-aware" design in low-power MPSoCs
Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, ERMAVSS 2016, co-located with IEEE/ACM Design, Automation and Test in Europe Conference (DATE 2016), Dresden, Germany, March 18, 2016
Triple-Skipping Near-MRAM Computing Framework for AIoT Era
Fast Comparisons of Circuit Implementations
Dynamic configuration prefetching based on piecewise linear prediction
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling
Efficient monitoring of loose-ordering properties for SystemC/TLM
DfM in the Analogue and Digital World
Optimizing performance analysis for synchronous dataflow graphs with shared resources
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving
Communication and migration energy aware design space exploration for multicore systems with intermittent faults
Towards Malicious Exploitation of Energy Management Mechanisms
Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking
Methods and Tools for the Design of Electrostatic Micromotors
Computing for Control and Control for Computing
Characterization of stack behavior under soft errors
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding
Smart Thermal Management for Heterogeneous Multicores
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks
Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications
Model Order Reduction for nanoelectronics coupled problems with many inputs
RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains
A complexity adaptive channel estimator for low power
Improving and extending the algebraic approach for verifying gate-level multipliers
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Analysis of the impact of bus implemented EDCs on on-chip SSN
Fault diagnosis in designs with extreme low pin test data compressors
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
Development of a fully implantable recording system for ECoG signals
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor
Reverse engineering of irreducible polynomials in GF(2 m ) arithmetic
Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs
AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator
Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks
High-quality real-time hardware stereo matching based on guided image filtering
Thermal aware design method for VCSEL-based on-chip optical interconnect
Speculative Temporal Decoupling Using fork()
End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification
Synthesis of SI Circuits from Burst-Mode Specifications
Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration
Verification of Proofs of Unsatisfiability for CNF Formulas
Low-power 3D integration using inductive coupling links for neurotechnology applications
SCC thermal model identification via advanced bias-compensated least-squares
A Complete Phase-Locked Loop Power Consumption Model
Statistical model order reduction for interconnect circuits considering spatial correlations
HW-SW integration for energy-efficient/variability-aware computing
Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System
Almost every wire is removable: A modeling and solution for removing any circuit wire
Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator
Context Sensitive Performance Analysis of Automotive Applications
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques
Fast deployment of alternate analog test using Bayesian model fusion
Networked embedded system applications design driven by an abstract middleware environment
Power-driven global routing for multi-supply voltage domains
Sensor networks on the car: State of the art and future challenges
Late Breaking Results: Approximated LUT-Based Neural Networks for FPGA Accelerated Inference
Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's
Low power FSM design using Huffman-style encoding
An on-chip clock generation scheme for faster-than-at-speed delay testing
Qualification and Integration of Complex I/O in SoC Design Flows
An evaluation of a slice fault aware tool chain
GATSim: Abstract timing simulation of GPUs
Compiling SyncCharts to Synchronous C
A Combined Pairing and Chaining Algorithm for CMOS Layout Generation
ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technology
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization
Efficient nonlinear distortion analysis of RF circuits
Accelerating Itemset Sampling using Satisfiability Constraints on FPGA
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Accurate margin calculation for single flux quantum logic cells
Fast positive-real balanced truncation of symmetric systems using cross Riccati equations
NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead
Chip Health Tracking Using Dynamic In-Situ Delay Monitoring
Synthesis of Complex Control Structures from Behavioral SystemC Models
Feedback control of real-time EtherCAT networks for reliability enhancement in CPS
Automatic Lighthouse Generation for Directed State Space Search
Real-time Detection and Localization of DoS Attacks in NoC based SoCs
Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits
Analysis of 3D conjugate heat transfers in electronics
A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint
DuSGAI: A Dual-Side Sparse GEMM Accelerator with Flexible Interconnects
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis
Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stage
Binary ReRAM-based BNN first-layer implementation
Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs
From C Programs to the Configure-Execute Model
A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment
Analog/mixed-signal IP modeling for design reuse
Congestion-controlled best-effort communication for networks-on-chip
Integrated scheduling and synthesis of control applications on distributed embedded systems
RankSearch: An Automatic Rank Search Towards Optimal Tensor Compression for Video LSTM Networks on Edge
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures
On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions
Hybrid prototyping of multicore embedded systems
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform Accelerator
Instruction Set Emulation for Rapid Prototyping of SoCs
Automatic Pruning of Autotuning Parameter Space for OpenCL Applications
SAT-based bit-flipping attack on logic encryptions
Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches
Behavioral level dual-vth design for reduced leakage power with thermal awareness
An approach for redundancy in FlexRay networks using FPGA partial reconfiguration
Carbon nanotube circuits: Living with imperfections and variations
Resource-aware functional ECO patch generation
Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios
Industrial applications
Standard cell library tuning for variability tolerant designs
Cybersecurity Challenges of Autonomous Systems
ScTMR: A scan chain-based error recovery technique for TMR systems in safety-critical applications
The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1
CoupledCB: Eliminating Wasted Pages in Copyback-based Garbage Collection for SSDs
Rapid in-memory matrix multiplication using associative processor
Application-specific power-efficient approach for reducing register file vulnerability
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
A Fully Digital Controlled Off-Chip IDDQ Measurement Unit
Intermittent Computing with Efficient State Backup by Asynchronous DMA
PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging
Wireless sensor networks and beyond
Optimize your power and performance yields and regain those sleepless nights
Hardware and firmware verification and validation: an algorithm-to-firmware development methodology
High-Level Synthesis of Recoverable Microarchitectures
COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories
HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System
Efficient Computation of Deadline-Miss Probability and Potential Pitfalls
HW-SW Optimization of DNNs for Privacy-Preserving People Counting on Low-Resolution Infrared Arrays
Hybrid symbolic-explicit techniques for the graph coloring problem
Parameterized area-efficient multi-standard turbo decoder
On the Optimal OBDD Representation of 2-XOR Boolean Affine Spaces
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems
Providing Response Times Guarantees for Mixed-Criticality Network Slicing in 5G
Moore's Law and ICT Innovation in the Anthropocene
Model Reuse through Hardware Design Patterns
CUDA au Coq: A Framework for Machine-validating GPU Assembly Programs
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices
Deep sub-micron I DDQ testing: issues and solutions
Semantics for Model-Based Validation of Continuous/Discrete Systems
ProxSim: GPU-based Simulation Framework for Cross-Layer Approximate DNN Optimization
C Compiler Retargeting Based on Instruction Semantics Models
Data flow testing for virtual prototypes
A cross-layer adaptive approach for performance and power optimization in STT-MRAM
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators
Thinfilm printed ferro-electric memories and integrated products
ASIC implementations of five SHA-3 finalists
NPU-Accelerated Imitation Learning for Thermal- and QoS-Aware Optimization of Heterogeneous Multi-Cores
LoSCache: Leveraging Locality Similarity to Build Energy-Efficient GPU L2 Cache
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction
Efficient Minarea Retiming of Large Level-Clocked Circuits
Are LLMs Ready for Practical Adoption for Assertion Generation?
Exploiting binary translation for fast ASIP design space exploration on FPGAs
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip
Timing-aware wire width optimization for SADP process
Toward a scalable test methodology for 2D-mesh Network-on-Chips
A Technique for Avoiding Isomorphic Netlists in Architectural Synthesis
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language Model
Towards a highly reliable SRAM-based PUFs
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis
Complexity, quality and robustness - the challenges of tomorrow's automotive electronics
MPFS: A Scalable User-Space Persistent Memory File System for Multiple Processes
tweedledum: A Compiler Companion for Quantum Computing
An analytical method for evaluating Network-on-Chip performance