yusuke1997/dblp-id-title huggingface dataset:
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations
Design of a Test Processor for Asynchronous Chip Test
Improving Test Quality Using Test Data Compression
Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware
A Multi-dimensional Pattern Run-Length Method for Test Data Compression
Power Aware Shift and Capture ATPG Methodology for Low Power Designs
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets
Error masking in compact testing based on the Hamming code and its modifications
An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs
Using Cell Aware Diagnostic Patterns to Improve Diagnosis Resolution for Cell Internal Defects
T2: Statistical Methods for VLSI Test and Burn-in Optimization
Conformance Test of Distributed Transaction Service
A Reseeding Technique for LFSR-Based BIST Applications
Why and How Controlling Power Consumption during Test: A Survey
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code
Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters
Fault and Soft Error Tolerant Delay-Locked Loop
On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis
A Technique for Analyzing On-Chip Power Supply Impedance
Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models
Functional Diagnosis for Graceful Degradation of NoC Switches
On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios
Test Synthesis for Datapaths Using Datapath-Controller Functions
Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach
A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation
IDDT Testing
A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
Effective Error Diagnosis for RTL Designs in HDLs
Efficient built-in self-test algorithm for memory
The Automatic Generation of Basis Set of Path for Path Testing
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications
Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time
Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring Oscillator
A Neural-Network-Based Fault Classifier
Optimal Scan Tree Construction with Test Vector Modification for Test Compression
The HiZ Problem of Power Management IC Testing
A Processor-Based Built-In Self-Repair Design for Embedded Memories
Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing
A New Low-Cost Method for Identifying Untestable Path Delay Faults
A MISR Computation Algorithm for Fast Signature Simulation
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems
Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption
Test Cost Analysis for 3D Die-to-Wafer Stacking
ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box
An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time
Testing and Diagnosis of Interconnect Structures in FPGAs
Test Generation for Weak Resistive Bridges
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks
Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost
Post-silicon Trace Signal Selection Using Genetic Algorithm
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs
Accelerated Functional Testing of Digital Microfluidic Biochips
Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng
Experimental Realization of Quantum Memory and EPS-QKD
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles
E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation
New built-in self-test technique based on addition/subtraction of selected node voltages
29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs
Scan Test Power Simulation on GPGPUs
On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators
A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities
Multi-histogram ADC BIST System for ADC Linearity Testing
Automatic Test Program Generation for Out-of-Order Superscalar Processors
Theory and applications of cellular automata for synthesis of easily testable combinational logic
On Generating Vectors for Accurate Post-Silicon Delay Characterization
On Test Points Enhancing Hardware Security
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing
A Resizing Method to Minimize Effects of Hardware Trojans
Enhancing Fault Simulation Performance by Dynamic Fault Clustering
Embedded core testing using genetic algorithms
25th IEEE Asian Test Symposium, ATS 2016, Hiroshima, Japan, November 21-24, 2016
C-Testing of AI Accelerators *
Test and Reliability Issues in 2.5D and 3D Integration
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests
Spirit: satisfiability problem implementation for redundancy identification and test generation
Aging Impact of Power MOSFETs in Charger with Different Operation Frequency
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test
RTL Concurrent Fault Simulation
Security Verification of RISC-V System Based on ISA Level Information Flow Tracking
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits
An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains
Memory reduction of I DDQ test compaction for internal and external bridging faults
Scan Chain Diagnosis Based on Unsupervised Machine Learning
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits
Test Time Reduction for I DDQ Testing by Arranging Test Vectors
A Case Study on Implementing Compressed DFT Architecture
Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis
Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking
Minimal Delay Test Sets for Unate Gate Networks
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan
Multi-level EDT to Reduce Scan Channels in SoC Designs
Securing Access to Reconfigurable Scan Networks
Extending EDA Environment From Design to Test
Polynomial Formal Verification of Prefix Adders
On Securing Scan Design from Scan-Based Side-Channel Attacks
A Template Attack on Reduction Without Reference Device on Kyber
The New Frontier for Testing: Nano Meter Technologies
Fault Detection for Testable Realizations of Multiple-Valued Logic Functions
Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays
Mentor Graphics DFT to Navigate Nanometer Test Challenges
Distinguishing Resistive Small Delay Defects from Random Parameter Variations
Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
A Postprocessing Procedure of Test Enrichment for Path Delay Faults
Computing stress tests for interconnect defects
27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018
Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits
SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism
Improved Fault Diagnosis for Reversible Circuits
On Covering Structural Defects in NoCs by Functional Tests
NoC Dynamically Reconfigurable as TAM
Design Retargetable Platform System for Microprocessor Functional Test
A Verification Guided Approach for Selective Program Transformations for Approximate Computing
Integrated Test Solution for embedded UHF/RF SOC
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
On Tolerating Variations and Faults in Memristor Crossbar Based Neural Network Accelerators by Network Expansion and Weight Zeroing
Test Limitations of Parametric Faults in Analog Circuits
A High-Speed IDDQ Sensor for Low-Voltage ICs
Locating Critical-Reliability Gates for Sequential Circuits based on the Time Window Graph Model
Counting Gates, Moving Qubits: Evaluating the Execution Cost of Quantum Circuits
Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults
Design of a Radiation Hardened Latch for Low-Power Circuits
A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool
Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing
Concurrent Test Generation
An Evaluation of Test Generation Algorithms for combinational Circuits
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing
Is Low Power Testing Necessary? What does the Test Industry Truly Need?
Using Hopfield Networks to Correct Instruction Faults
Minimizing the Number of Test Configurations for Different FPGA Families
Embedded Test for Highly Accurate Defect Localization
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs
Resistive Bridging Faults DFT with Adaptive Power Management Awareness
Damage Size and Software Safety Demonstration Stress Testing
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption
The Future is Hybrid: Next Generation Data Structures for Formal Verification
Low Cost Bist for Edac Circuits
Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits
Testing RF Components with Supply Current Signatures
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic
Critical Paths Selection and Test Cost Reduction Considering Process Variations
Embedded Test Technology - Brief History, Current Status, and Future Directions
On-Chip Delay Sensor for Environments with Large Temperature Fluctuations
A Diagnosis Method for Interconnects in SRAM Based FPGAs
Realistic Linked Memory Cell Array Faults
Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator
Reconsideration of Software Reliability Measurements
An Authentication-Based Secure IJTAG Network
Memory Fault Simulator for Static-Linked Faults
A Test Architecture for System-on-a-Chip
Reduce Yield Loss in Delay Defect Detection in Slack Interval
ATREX : Design for Testability System for Mega Gate LSIs
Low Power Test Compression with Programmable Broadcast-Based Control
Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates
Expansion of Convolutional Compactors over Galois Field
Scan Compression Implementation in Industrial Design - Case Study
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST
BTI Aging Monitoring based on SRAM Start-up Behavior
Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC
On Design of Fail-Safe Cellular Arrays
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits
Memory Read Faults: Taxonomy and Automatic Test Generation
Tests for Word-Oriented Content Addressable Memories
System Testing using UML Models
Application of Data Mining Based Scan Diagnosis Yield Analysis in a Foundry and Fabless Working Environment
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test
Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing
Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs
Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication
Survey on Traffic Flow-Based Autonomous Driving Simulation Tests
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design
On Improvement in Fault Tolerance of Hopfield Neural Networks
Fast Bridging Fault Diagnosis using Logic Information
A Test and Diagnosis Methodology for RF Transceivers
March SL: A Test For All Static Linked Memory Faults
Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?
Variation-Aware Fault Modeling
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients
A Portable Hardware Trojan Detection Using Graph Attention Networks
DFT and BIST techniques for the future
A Family of Logical Fault Models for Reversible Circuits
Defining SRAM Resistive Defects and Their Simulation Stimuli
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset
A Method to Calculate the Reliability of Component-Based Software
An Efficient Method to Identify Untestable Path Delay Faults
Proceedings of the 20th IEEE Asian Test Symposium, ATS 2011, New Delhi, India, November 20-23, 2011
A Totally Self-Checking Dynamic Asynchronous Datapath
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Property Classification for Functional Verification Based
Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester
A Unified Scheme for Designing Testable State Machines
Non-exhaustive Parity Testing
14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India
A Unified Interconnects Testing Scheme for 3D Integrated Circuits
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths
Design, Verification, and Application of IEEE 1687
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
Formula-Oriented Compositional Minimization in Model Checking
Threshold testing: Covering bridging and other realistic faults
Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method
A Novel Compaction Approach for SBST Test Programs
Test Pattern Length Required to Reach the Desired Fault Coverage
Optimal Redundancy Designs for CNFET-Based Circuits
Redundancy Identification Using Transitive Closure
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms
IDDQ Current Dependency on Test Vectors and Bridging Resistance
Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation
TTEP Introduction
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions
Test by Distributed Monitoring
LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection
A Fault Check Graph Approach for Photonic Router in Network on Chip
A New Approach to Generating High Quality Test Cases
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD
A STAFAN-like functional testability measure for register-level circuits
Power supply current detectability of SRAM defects
Not all Delay Tests Are the Same - SDQL Model Shows True-Time
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs
On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations
Level-Testability of Multi-operand Adders
Achieving Acceptable Bit Error Rate for 40 Gbps Link Using Signal Conditioning Techniques
A New Path Delay Test Scheme Based on Path Delay Inertia
Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal Constraints
Towards Affordable Fault-Tolerant Nanosatellite Computing with Commodity Hardware
A Formal Approach and Testing Process for Failure Modes in Intelligent Algorithms
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations
A Heuristic Algorithm for Automatic Generation of March Tests
Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net Model
Analysis of Software Test Item Generation - Comparison between High Skilled and Low Skilled Engineers
Plug once, test everything
Testing of a parallel ternary multiplier using I 2 L logic
Impact of All-Digital PLL on SoC Testing
Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications
Effective Techniques for High-Level ATPG
Low-Cost One-Port Approach for Testing Integrated RF Substrates
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power
A hierarchical test control architecture for core based design
On No-Reference Error Detection of an Image Stitching System Based on Error-Tolerance
Fault Simulation Acceleration Based on ARM Multi-core CPU Architecture
Practices in Testing of Mixed-Signal and RF SoCs
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits
A Thermal-Driven Test Application Scheme for 3-Dimensional ICs
Low power design and its testability
Delay Fault Diagnosis in Sequential Circuits
Partial Gating Optimization for Power Reduction During Test Application
Practical Aspects of Delay Testing for Nanometer Chips
Detailed Fault Model for Physical Quantum Circuits
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits
Evaluating BIST Architectures for Low Power
Test Pattern Compression for Probabilistic Circuits
Test Data Compression Using Don?t-Care Identification and Statistical Encoding
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage
28th IEEE Asian Test Symposium, ATS 2019, Kolkata, India, December 10-13, 2019
Low Transition LFSR for BIST-Based Applications
Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions
Test Scheduling and Scan-Chain Division under Power Constraint
23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014
Fault Securing Techniques for Yield and Reliability Enhancement of RRAM
Novel Optical Probing System for Quarter-micron VLSI Circuits
On Optimal Power-Aware Path Sensitization
Secure AI Systems: Emerging Threats and Defense Mechanisms
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface
Scan-Based BIST Using an Improved Scan Forest Architecture
Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration
DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits
A class of sequential circuits with combinational test generation complexity under single-fault assumption
On Soft Error Immunity of Sequential Circuits
Optimizing the Streaming of Sensor Data with Approximate Communication
Microsystems Testing: A Challenge
Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs
Total Jitter Measurement for Testing HSIO Integrated SoCs
Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning
A Test Point Insertion Method to Reduce the Number of Test Patterns
Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories
Evolutionary Test Program Induction for Microprocessor Design Verification
Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems
Further Analysis of Laser-induced IR-drop
Detection of Stuck-at and Bridging Fault in Reversible Circuits using an Augmented Circuit
Equivalence Checking Using Independent Cuts
Challenges in Next Generation Mixed-Signal IC Production Testing
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base
Maximum Distance Testing
DFT for Low Cost SOC Test
FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design
Electrical Overstress Prevention & Test Best Practices
Test generation for fault isolation in analog circuits using behavioral models
RiskCap: Minimizing Effort of Error Regulation for Approximate Computing
On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing
Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level
Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel
IDDT ATPG Based on Ambiguous Delay Assignments
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage
Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs
Multicycle-aware At-speed Test Methodology
N-distinguishing Tests for Enhanced Defect Diagnosis
A BIST methodology for at-speed testing of data communications transceivers
A Reliability Model for Object-Oriented Software
Genetic Algorithm Based Test Generation for Sequential Circuits
Manufacturing Test of SoCs
Diagnostic Test Generation Targeting Equivalence Classes
Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool
Integrated Current Sensing Device for Micro IDDQ Test
Identification of Defective TSVs in Pre-Bond Testing of 3D ICs
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis
A Logic Encryption-Enhanced PUF Architecture to Deceive Machine Learning-Based Modeling Attacks
Improved Methods for Accurate Safety Analysis of Real-Life Systems
Test Education in the Global Economy
16th Asian Test Symposium, ATS 2007, Beijing, China, October 8-11, 2007
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing
Reliability Analysis of Approximate Multipliers with Recovery Schemes
Serial transistor network modeling for bridging fault simulation
10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan