yusuke1997/dblp-id-title huggingface dataset:
Si-Backside Side-Channel Leakage Measurement and Simulation
CAN Security Protocol Using Modified MAC
Weather Classification using Convolutional Neural Networks
Fast design space exploration for mixed hardware-software embedded systems
A study of mobile Optical Image Stabilization system for mobile camera
Die matching algorithm for enhancing parametric yield of 3D ICs
Implemetation of image classification CNN using multi thread GPU
HVS-based AR Display Image Enhancement With Delta Look-Up Table Considering Ambient Light
Area and Energy-Efficient Multi-Channel Instrumentation Amplifiers for Biomedical Applications
Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit
Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS
Design and verification of sensorless BLDC motor start-up logic with FPGA
Face detection based on chrominance and luminance for simple design
Design of TETRA Release 2 turbo decoder with low-complexity hardware interleaver
μPnP-WAN: Wide area plug and play sensing and actuation with LoRa
A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver
A simple approach of stability analysis and MPPT control in DC-DC converter with TEM
Placement Initialization via Community Detection
Logic Diagnosis Based on Deep Learning for Multiple Faults
Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection
A Digital ΣΔ Modulated Class-S Transmitter with Two-Step Up-conversion and Filter-less Front End
A 8-bit 300MHz Domino Based Successive Approximation Register ADC
Time-domain temperature sensor using two stage vernier type time to digital converter for mobile application
Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory
Integrated All-GaN Driver for High-voltage DC-DC Power Converters
A Single-Inductor Triple-Source Energy Harvesting Interface for Batterty-Assisted IoT Applications
A hardware-efficient FPGA cochlear model for next generation nonlinear cochlear implant
FAME: Fault Address Memory Structure for Repair Time Reduction
Design of Cardiac Status Indicator and R-R Interval Adjustment Circuits
XSNN: a System-Level Simulator for Spiking Neural Network with Neuron Circuits and Synapse Devices
A design of tunable component for font end module
A Fully 4-bit Quantized MobileNet-SSD
Determining PCIe5 Jitter Margin using SIPI Co-Sim
Convolutional Neural Network Accelerator with Reconfigurable Dataflow
CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain Mining
Tapered-Ratio Compression for Residual Network
Accelerating Embedded WebAssembly Based on FPGA
A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup
Efficient Implementation of Multiple Interleavers in IDMA for 5G
An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology
Development of a verification platform for intelligent surveillance camera systems
A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs)
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM
Production-Oriented Design for High Parallel Test Efficiency
Lightweighted Shallow CTS Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time
Standing wave oscillator based clock distribution
Ultra low power active 60 GHz Bi-CMOS down-conversion mixer
Implementation of Optimal CNN Accelerators for Mobile Devices: Algorithm, Architecture, and Memory System Co-Design
A 28GHz Quadrature Up-conversion Transmitter in 65nm CMOS for 5G mmWave Radio
High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture
Implementation of 3D Hand Gesture Recognition System using FPGA
Design and implementation of a video display processing SoC for full HD LCD TV
A scalable multi-ASIP architecture for standard compliant trellis decoding
Diagnosis of Resistive Nonvolatile-8T SRAMs
Automated architecture exploration for low energy reconfigurable AGU
Low-noise high-speed CMOS CID readout IC
Enhancing Performance and Energy Efficiency of Reconfigurable CNN Accelerator
Digitizing the feedback signal in a magnetic field (AMR) sensor system using delta sigma modulator topology
Information Transmission Focusing on Complex Networks Consisting of Oscillators
Low-offset comparator using capacitive self-calibration
Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping
Task mapping techniques for embedded many-core SoCs
CMOS energy efficient integrated radios for emerging low power standards
Analysis and Design of CRC-based SENT Interface for Future Automotive Applications
Source-Line Shared SOT-MRAM Cell for Energy Efficient Read Operation
A novel frequency-shift readout system for CEA concentration detection application
Hybrid Decoding for Polar Codes
Computation Exactness Exploration of Exact Quantum Adders in NISQ
Implementation of Modular Subtraction Unit for NTT-based Polynomial Multiplier
Design of eMMC controller with multiple channels
Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review
A Lightweight DNN for ECG Image Classification
Verification of massive advanced node SoCs
A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL
Load-Independent Multiple Output WPT System With Fixed Coupling Coils
APAPG: Address Pre-Processed ALPG for High-Speed Linear Test
A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO
A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator
Cryptographie coprocessor design for IoT sensor nodes
Machine Learning based Scan Chain Diagnosis for Double Faults
Marker-based watershed algorithm for segmentation of the infrared images
12-Bit 5 MS/s SAR ADC with Split Type DAC for BLE
Computation of modular multiplicative inverses using residue signed-digit additions
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller
Enhanced Depth Map Estimation in Low Light Conditions for RGB Cameras
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers
Memristor Crossbar Circuits for Neuromorphic pattern Recognition
Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface
Investigate of Mitigation Solution against Hardware Trojans Attack on Evolvable Hardware Platform
A low-power relaxation oscillator with improved thermal stability
Transfer Learning-based Vehicle Classification
Low Jitter and Low Power PLL：Towards The Utopia
Autoencoder-based Knowledge Distillation For Quantized YOLO Detector
Contention and energy aware mapping for real-time applications on Network-on-Chip
PHY Layer Design of OFDM-VLC System based on SoC using Reuse Methodology
A synthesis algorithm for customized heterogeneous multi-processors
A Neural Stimulator IC with Dynamic Voltage Scaling Supply and Energy Recycling for Cochlear Implant in Standard 180nm CMOS Process
A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip
Recent advances in TSV inductors for 3D IC technology
A design and integration of Parametric Measurement Unit on to a 600MHz DCL
CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system design
A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image Registration
Redundancy Analysis based on Fault Distribution for Memory with Complex Spares
Fast Steady-State Thermal Analysis
Multi-band PLL for RF wireless charger at 2.4 GHz and 5.8 GHz
Energy-Efficient Sparse Hyperdimensional Computing for Speech Recognition
Pre-RTL DNN Hardware Evaluator With Fused Layer Support
Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators
Reconfigurable Gaussian filtering TSP readout circuit for Flexible AMOLED Display
Design of Current Sensor in COT DC-DC Converter for IoT applications
63.2pS at 1.2V dynamic comparator in 65nm CMOS technology
77 GHz signal generator with CMOS technology for automotive radar application
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST
The parallelization of convolution on a CNN using a SIMT based GPGPU
7.7Gbps encoder design for IEEE 802.11n/ac QC-LDPC codes
HV switch using differential voltage shaping driver for 13 series li-ion battery cells BMS
Application of Blind Signal Processing in Image Watermarking Systems
Visualization of Neuron Data using Nonlinear Technic
Early Image Termination Technique During STDP Training of Spiking Neural Network
Self-sustainable Triple-input Triple-output Power Management Unit for Battery-less IoT Application with Low-power Time-monitoring MPPT
22/16nm High Speed and Area Efficient Automotive Grade STT-MRAM Memory Compiler for 2~128Mb
A Circular-based TSV Repair Architecture
An SDR-based WSN Testbed for RF Front End Simulation and Experimentation
YOCO: Unified and Efficient Memory Protection for High Bandwidth Memory
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory
A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes
International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020
Hybrid Mesh-Ring wireless Network on Chip for multi-core system
Time Controlled Pre-Emphasis Circuit for Broadband Frequency Operation up to 3.6 Gbps
AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology
A Machine Learning Accelerator for DDoS Attack Detection and Classification on FPGA
Mitigating Message Passing Interference in Trusted Embedded Platforms
Low Power Approximate Multiplier Using Error Tolerant Adder
Building block operating system for 3D stacked computer systems with inductive coupling interconnect
Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication
A Novel Global Maximum Power Point Tracking Method based on Shading Detection
Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell
International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016
Approximate Adder Generation for Image Processing Using Convolutional Neural Network
A High-speed Wireless Data Transfer for Non - Destructive Testing
LogicEdu: Enhancing Computational Logic Understanding through Web-Based Boolean Logic Simplification Tool
A Rule-of-thumb Condition to Avoid Large HRS Current in ReRAM Crossbar Array Design
Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT Variation
5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS
A single inductor multiple output(SIMO) buck/boost DC-DC converter with output error-driven random control
Analysis of the synchronization performance of wireless functional electronic stimulation central pattern generator
A CMOS voltage reference combining body effect with switched-current technique
Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security Applications
Phase Change of Three Coupled Chaotic Circuits to Input Signals
Clustering in Globally Coupled Chaotic Circuits with Changing Weights
Low-power multi-sensor system with normally-off sensing technology for IoT applications
Hybrid CC-LSTM Algorithm for SOC Estimation and Its Dual-Mode Hardware Design
Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory
Hybrid path-diversity-dominant output selection method for Network-on-Chip systems
Row-Efficient Pruning for In-Memory Convolutional Weight Mapping
Design techniques for ultra-efficient computing
Advanced Parasitic Capacitance Extraction using Active Learning
Design of Resonant Converter with Genetic- Algorithm Optimization
Extraction of ROM Data from Bitstream in Xilinx FPGA
Prototyping circuit design for Dielectric Electroactive Polymers energy harvesting
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver
Smart Computational Resource Distribution System with Automatic Classification Interface for CPS
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)
Low Power Loss IGBT Driver Circuit Using Current Drive
Throughput enhancemnet with optimal fragmented MSDU size for fragmentation and aggregation scheme in WLANs
Synergistic Integration: An Optimal Combination of On-Die and Rank-Level ECC for Enhanced Reliability
A Design of high-efficiency Constant On-Time Control DC-DC Buck Converter for Power Management integrated circuits
A Capacitor-less LDO for Mobile Devices with Fast Transient Using High Gain Positive Feedback Loop
International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018
Dynamically changeable secure scan architecture against scan-based side channel attack
Design for testability in nano-CMOS analog integrated circuits using a new design analog checker
High-performance RF-interconnect for 3D stacked memory
Tailoring Backbone Architectures for SSD
A study of META-voltage controlled oscillator and prescaler using 65nm CMOS process: META-VCO and prescaler using 65nm CMOS precess
Digital Calibration of 1.5 bits/stage Algorithmic ADC
A Novel Efficient Approximate Adder Design using Single Input Pair based Computation
A battery-connected all-digital capacitive DC-DC converter with load tracking controller
High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper
An Efficient Sensory System for Intelligent Gas Monitoring Accurate classification and precise quantification of gases/ odors
A study into high-throughput decoder architectures for high-rate LDPC codes
Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis
Integration of dual channel timing formatter system for high speed memory test equipment
Efficient EMS decoding for non-binary LDPC codes
GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair
Neuromorphic Hardware Based on Artificial Synaptic Devices
Wideband Operational Trans-Conductance Amplifier with Feed-Forward Compensation Technique
Low power semi-static TSPC D-FFs using split-output latch
Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth
Development of a Spectral Feature Extraction using Enhanced MFCC for Respiratory Sound Analysis
Wireless low power toxic gas detector based on ADuCM360
A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system
Feature Distribution-based Knowledge Distillation for Deep Neural Networks
Low Power Ternary XNOR using 10T SRAM for In-Memory Computing
Implementation of Wireless Spiking Neural Network for Classifications on MNIST Dataset
Area efficient neuromorphic circuit based on stochastic computation
Multi-Phase Frequency Divider Generator with Process-Independent Automation
FPGA implementation of unified kernel structure for MDCT/IMDCT in audio coding schemes
A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces
A Novel Hybrid Analog Design Optimizer with Particle Swarm Optimization and modern Deep Neural Networks
Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits
RRAM-Based STDP Network for Edge Computing in Wearable/Implantable Devices
An MAE-aware ROI Sampling Model for LiDAR
A Time-Domain Parallel Counter for Deep Learning Macro
Design of NFC transceiver for automotive applications
Optimal Model Analysis for Denoising Monte Calro Rendering Noise
Efficient final output feature map processing method supporting real-time object detection and recognition
Statistical modeling of capacitor mismatch effects for successive approximation register ADCs
CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array
Hash-table and balanced-tree based FIB architecture for CCN routers
A Fast Locking Duty Cycle Corrector with High Accuracy
Digital Twin based Maximum Power Point Estimation for Photovoltaic Systems
Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme
A 200-kHz/6.78-MHz wireless power transmitter featuring concurrent dual-band operation
A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors
Hybrid Concurrent Driving Technique for Large Touch Screen Panels
LEAP: LLW RowHammer Mitigation System
Throughput Improvement of an Autocorrelation Block for Time Synchronization in OFDM-based LiFi
A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology
Digital-to-Analog Converter Architectures Based on Polygonal and Prime Numbers
Cryogenic Characterization of 40nm CMOS for Quantum Control Applications
A Low-power PLL with a Standby Mode
The first study of 10nm-class backside defect using Co-Routine based ETL in DRAM
An Evaluation of Electricity Demand Forecasting Models for Smart Energy Management Systems
Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell
PPG Sensors for The New Normal: A Review
3D Human Motion Reconstruction in Unity With Monocular Camera
A pre-characterization method for multiple single-event transient analysis in cell-based designs
A 0.5-V sub-mW energy-efficient receiver in 0.18-μm CMOS for IoT applications
Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique
Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction
Error Injection & Correction: An efficient formal logic restructuring algorithm
AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNs
Scalability Analysis and Modeling of XPoint-based MRAM
Optimized Image Crop-based Video Retargeting
High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes
Releasing the Memory Bottleneck to Display Video Correctly
An Adaptive PA Modulation Index Controller with Temperature Compensation for DSRC Applications
A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder
Design of multicycle path accelerator for neural network
Design of high efficiency of 98 percent active rectifier with automatic zero voltage and current switching circuit for wireless charging system
International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011
Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle
Signal integrity analysis of heterogeneous integration using Si bridge technology
Twiddle Factor Generator Architecture for Number Theoretic Transform
Smartphone-based Road Condition Sensing using Machine Learning techniques
A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature Sensor
A network architecture design of embedded system for media service in bus
C-AFA: A Conditionally Approximate Full Adder for Efficient DNN Inference in CIM Arrays
Switching Phenomena by Adding a Memristor to a Chaos Circuit
A New Service Time Framework for Expressway Toll Lane Capacity Model
Efficient TSV Fault Detection Scheme For High Bandwidth Memory Using Pattern Analysis
Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design
Leveraging Approximate Computing for IoT Image Transmission
Performance Analysis of a Phase-Change Memory System on Various CNN Inference Workloads
A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment
A 10-bit 250 MS/s Binary Search and Two channel SAR ADC by a two-bit per Conversion with Error Tolerance Ability
High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit
Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach
Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation
Interface Circuits for Piezoelectric Polyvinylidene Fluoride (PVDF) Films
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation
A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain Comparison
Hand gesture recognition using deep learning
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS
Prototype of Low Complexity CNN Hardware Accelerator with FPGA-based PYNQ Platform for Dual-Mode Biometrics Recognition
Full system verification of compatible microprocessors with a dual physical core verification platform
Modelling of Phase Change Memory(PCM) cell for Circuit Simulation
Monolithic MEMS resonator based pressure sensor and readout design
A Ka-band low noise amplifier in 0.15μm GaAs E-mode pHEMT technology
Nonlinear Behavior of Unmanned Aerial Vehicle based on Oscillation Dynamics
High-Level Synthesis Considering Layer Assignment on Timing in 3D-IC
An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA
Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector
Pedestrian detection aided by temporal prior
A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process
Test data reduction method based on berlekamp-massey algorithm
A Method of Prevent Loss of Information in Ill-Posed Problem Based Application using Atmospheric Scattering Model
Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality
Multiple-output LDO regulator applying with constant feedback factor
High performance pulse ring voltage controlled oscillator for Internet of Things
Detecting and assignment of unexpected tasks in SoC design process using genetic programming
Low Power Scan Chain Architecture Based on Circuit Topology
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices
A High Slew-rate Wide-range Capacitive Load Driving Buffer Amplifier with Correlated Dual Positive Feedback Loops
Night-time Vehicle Detection Based on Brake/Tail Light Color
Processing Time Reduction for JPEG Compression Using Pixel Array Conversion
Robust Cascaded Boost Converter with See-Saw Stress-Relief Control
A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction
Energy-Quality Scalability of Hyperdimensional Computing for Character Recognition in 65nm CMOS
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology
A 12-28 Gb/s Temperature Compensated PAM-4 Transmitter with 7B4Q Maximum Transition Avoidance and Fractional-Spaced FFE
Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders
Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS
A Novel Study on a 300°C, High Performance LDO Regulator Using Silicon-On-Insulator Process for Extreme Drill Bit Application
Calibration of M-Channel Time-Interleaved Analog-to-Digital Converters Based on Curve Fitting
Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing
A Cap-less LDO Regulator with Improved Load Regulation using Adaptive Feedback Control and Modified Voltage Damper
Analysis of Chaotic Circuit Networks with One-Way Coupling
Fast Performance and Power Profiler for SRAM Compute-in-Memory-based Accelerators
An Invariant Interconnect Delay Monitoring Circuit for 3D System Scaling
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design
Novel 4-Transistors Ternary Inverter Circuit Using Carbon-Nanotube Field -Effect Transistors
A range-scaled 13b 100MS/s 0.13μm CMOS SHA-free ADC based on a single reference
Overview of Memory Design for Next Generation Applications
Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network
LNA topologies for RX carrier aggregation
Ability to generate output series for Hysteresis Reservoir Computing
Compact CNN Training Accelerator with Variable Floating-Point Datapath
2019 International SoC Design Conference, ISOCC 2019, Jeju, Korea (South), October 6-9, 2019