yusuke1997/dblp-id-title huggingface dataset:
Orion: a power-performance simulator for interconnection networks
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches
Exploiting ILP in Page-based Intelligent Memory
DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage
Whole Execution Traces
Combining Loop Transformations Considering Caches and Scheduling
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
The TM3270 Media-Processor
A probabilistic model for the evaluation of microprogram performance
ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse
CRAM: coded registers for amplified multiporting
Skewed Compressed Caches
Microprogramming instruction systolic arrays
Automated proofs of microprogram correctness
Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory
: Near-Storage Accelerator for High-Performance Log Analytics
Osiris: A Low-Cost Mechanism to Enable Restoration of Secure Non-Volatile Memories
Post-compaction register assignment in a retargetable compiler
Hierarchical microprogram generating system
PockEngine: Sparse and Efficient Fine-tuning in a Pocket
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
Manager-client pairing: a framework for implementing coherence hierarchies
A Framework for Providing Quality of Service in Chip Multi-Processors
Available Parallelism in Video Applications
Enabling interposer-based disintegration of multi-core processors
A shape matching approach for scheduling fine-grained parallelism
Breathing life into a paper tiger (keynote session)
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution
Dynamic microprogramming in a time sharing environment
Pushing the Performance Envelope of DNN-based Recommendation Systems Inference on GPUs
A microprogramming language-directed microarchitecture
Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors
The Last-Level Branch Predictor
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets
A survey of resource allocation methods in optimizing microcode compilers
Dynamic zero compression for cache energy reduction
Architectural opportunities for novel dynamic EMI shifting (DEMIS)
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
A Predictive Performance Model for Superscalar Processors
Phase coupling for horizontal microcode generation
A microprogrammable display processor concept
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+
Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
The LASS hardware processor
FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache
MASCO: An academic exercise in computer design using microprogramming
The SPS-41 and SPS-81 programmable digital signal processors
TileFlow: A Framework for Modeling Fusion Dataflow via Tree-based Analysis
Scalable Speculative Parallelization on Commodity Clusters
Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs
57th IEEE/ACM International Symposium on Microarchitecture, MICRO 2024, Austin, TX, USA, November 2-6, 2024
Asynchronous network of specific microprocessors
AQUOMAN: An Analytic-Query Offloading Machine
A higher level language for micro-programming
Hybrid wireless Network on Chip: a new paradigm in multi-core design
Contention-based congestion management in large-scale networks
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly
SuperCore: An Ultra-Fast Superconducting Processor for Cryogenic Applications
Microcode implemented General Modular Redundancy
Inferred Models for Dynamic and Sparse Hardware-Software Spaces
Proceedings of the 12th annual workshop on Microprogramming, MICRO 1979, Hershey, Pennslylvania, USA, November 18-21, 1979
A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications
Optimal Superblock Scheduling Using Enumeration
A study on the number of memory ports in multiple instruction issue machines
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
Fused-layer CNN accelerators
A Framework for Fine-Grained Program Versioning
Position Paper: Defending Direct Memory Access with CHERI Capabilities
Wavelet transform based pre-processing for side channel analysis
Data flow graph partitioning to reduce communication cost
Trace Processors
LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories
DUAL: Acceleration of Clustering Algorithms using Digital-based Processing In-Memory
Distributed microprogramming
Redefining QoS and customizing the power management policy to satisfy individual mobile users
Ptolemy: Architecture Support for Robust Deep Learning
CrystalBall: Statically analyzing runtime behavior via deep sequence learning
55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022
Neural acceleration for GPU throughput processors
Data-Dependency Graph Transformations for Superblock Scheduling
On Reconfigurable On-Chip Data Caches
Reducing power with dynamic critical path information
An analysis of code density for the two level programmable control of the Nanodata QM-1
The TYR Dataflow Architecture: Improving Locality by Taming Parallelism
ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions
MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021
Power to the people: Leveraging human physiological traits to control microprocessor frequency
Fat Loads: Exploiting Locality Amongst Contemporaneous Load Operations to Optimize Cache Accesses
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Network on Chip Architectures, NoCArc '13, in conjunction with the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7, 2013
Cherry: checkpointed early resource recycling in out-of-order microprocessors
Efficient multiprogramming for multicores with SCAF
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
On inherent untestability of unaugmented microprogrammed control
Graph based retargetable microcode compilation in the MIMOLA design system
Lookahead scheduling
Translation hint buffers to reduce access time of physically-addressed instruction caches
Exploiting semantic commutativity in hardware speculation
Improving Locality Using Loop and Data Transformations in an Integrated Framework
Comparing Program Phase Detection Techniques
Building the Computing System for Autonomous Micromobility Vehicles: Design Constraints and Architectural Optimizations
Design of a microprogramming language
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors
Intersection Prediction for Accelerated GPU Ray Tracing
URPR - An extension of URCR for software pipelining
Conjoined-Core Chip Multiprocessing
Throughput-Effective On-Chip Networks for Manycore Accelerators
Efficient persist barriers for multicores
ZerehCache: armoring cache architectures in high defect density technologies
Register file port requirements of transport triggered architectures
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron
Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources
Architectural tradeoffs for biodegradable computing
Stellar: An Automated Design Framework for Dense and Sparse Spatial Accelerators
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
Short Paper: Device- and Locality-Specific Fingerprinting of Shared NISQ Quantum Computers
An 8-bit AVR-Based Elliptic Curve Cryptographic RISC Processor for the Internet of Things
Two-level hierarchical register file organization for VLIW processors
HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes
Using a configurable processor generator for computer architecture prototyping
Systematic Crosstalk Mitigation for Superconducting Qubits via Frequency-Aware Compilation
ICED: An Integrated CGRA Framework Enabling DVFS-Aware Acceleration
TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory
Microarchitecture choices (implementation of the VAX)
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
RTLcheck: verifying the memory consistency of RTL designs
The architecture of the hardware unification unit and an implementation
Direct execution of C-string compiler texts
Thermal-Aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC
Modulo scheduling with integrated register spilling for clustered VLIW architectures
Reducing register ports for higher speed and lower energy
Performance issues in correlated branch prediction schemes
DarKnight: An Accelerated Framework for Privacy and Integrity Preserving Deep Learning Using Trusted Hardware
Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors
Spectral profiling: Observer-effect-free profiling by monitoring EM emanations
A Case for Clumsy Packet Processors
Modeling and analyzing timing faults in transaction level SystemC programs
Incremental Commit Groups for Non-Atomic Trace Processing
Allocating rotating registers by scheduling
Prophetic branches: a branch architecture for code compaction and efficient execution
Developing survival instincts in computing systems
Futility Scaling: High-Associativity Cache Partitioning
Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations
Cambricon-C: Efficient 4-Bit Matrix Unit via Primitivization
Improving GPU performance via large warps and two-level warp scheduling
A dynamic-programming technique for compacting loops
Complexity effective memory access scheduling for many-core accelerator architectures
Game-based Congestion-aware Adaptive Routing (GCAR) for Proactive Thermal-aware 3D Network-on-Chip Systems
Thread criticality support in on-chip networks
HPS, a new microarchitecture: rationale and introduction
Pipelined microprogrammed control of a real-time signal processor
Why design must change: rethinking digital design
Improving memory bank-level parallelism in the presence of prefetching
Stride directed prefetching in scalar processors
Automatic microcode generation for horizontally microprogrammed processors
Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation
GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware
Height reduction of control recurrences for ILP processors
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events
MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference
Support for High-Frequency Streaming in CMPs
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget
Compiler controlled value prediction using branch predictor based confidence
Charon: Specialized Near-Memory Processing Architecture for Clearing Dead Objects in Memory
A new case for the TAGE branch predictor
Spatula: A Hardware Accelerator for Sparse Matrix Factorization
The impact of delay on the design of branch predictors
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling
Tradeoffs in designing accelerator architectures for visual computing
Sampler: PMU-Based Sampling to Detect Memory Errors Latent in Production Software
SRender: Boosting Neural Radiance Field Efficiency via Sensitivity-Aware Dynamic Precision Rendering
Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors
A faster optimal register allocator
SPAID: software prefetching in pointer- and call-intensive environments
Programming a microcoded processor for speech waveform generation
Towards Developing High Performance RISC-V Processors Using Agile Methodology
Using Interaction Costs for Microarchitectural Bottleneck Analysis
A distributed processor state management architecture for large-window processors
Energy efficient GPU transactional memory via space-time optimizations
A Data-Centric Accelerator for High-Performance Hypergraph Processing
Transparent microprogramming in support of abstract type oriented dynamic vertical migration
A weighted technique for programmable logic devices minimization
Value Profiling
Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code
GURPR * : A New Global Software Pipelining Algorithm
Data movement aware computation partitioning
Microarchitecture modelling through ADL
BBMSS: A bit-splice based microprogram simulation system
Hardware and software tools for the development of a micro-programmed microprocessor
A software pipelining based VLIW architecture and optimizing compiler
RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher
SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue
Imbalanced cache partitioning for balanced data-parallel programs
Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth
Segment gating for static energy reduction in Networks-on-Chip
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor
JigSaw: Boosting Fidelity of NISQ Programs via Measurement Subsetting
Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations
Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization
PiCL: A Software-Transparent, Persistent Cache Log for Nonvolatile Main Memory
Incidental computing on IoT nonvolatile processors
ALTOCUMULUS: Scalable Scheduling for Nanosecond-Scale Remote Procedure Calls
Development tools for user microprogramming
ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator
BBS: Bi-Directional Bit-Level Sparsity for Deep Learning Acceleration
EazyHTM: eager-lazy hardware transactional memory
SSP: Eliminating Redundant Writes in Failure-Atomic NVRAMs via Shadow Sub-Paging
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
AQ2PNN: Enabling Two-party Privacy-Preserving Deep Neural Network Inference with Adaptive Quantization
Encore: low-cost, fine-grained transient fault recovery
AutoBraid: A Framework for Enabling Efficient Surface Code Communication in Quantum Computing
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
The economics of programmable system components
Hardware Support for Constant-Time Programming
Perceptron learning for reuse prediction
The micro-architecture of the ECLIPSE® MV/8000: Conception and implementation
SCARAB: a single cycle adaptive routing and bufferless network
OCRA: An Oblivious Congested Region Avoiding Routing Algorithm for 3D NoCs
11th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2018, Fukuoka, Japan, October 20, 2018
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
Study on logic-based routing for 3D NOCs
A microarchitecture description language for retargeting firmware tools
A microprogrammed data communications procedure controller
The EH Model: Early Design Space Exploration of Intermittent Processor Architectures
Token tenure: PATCHing token counting using directory-based cache coherence
FracDRAM: Fractional Values in Off-the-Shelf DRAM
Micro emulation: When to do it and when not to do it
Microprogrammed subprocessors for compilation and execution of high-level languages
Incremental foresighted local compaction
Some observations on modular design technology and the use of microprogramming
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures
Software pipelining with register allocation and spilling
Viewing Instruction Set Design as an Optimization Problem
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration
Adaptive router architecture based on traffic behavior observability
LogNIC: A High-Level Performance Model for SmartNICs
A scalable NoC topology targeting network performance
Evaluating MMX Technology Using DSP and Multimedia Applications
PARSNIP: performant architecture for race safety with no impact on precision
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
VR-DANN: Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration
Migration implementation by integrating microprogramming and HLL programming
Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation
A resistive TCAM accelerator for data-intensive computing
Long term parking (LTP): criticality-aware resource allocation in OOO processors
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making
Loopback strategy for in-vehicle network processing in automotive gateway network on chip
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management
MeMCISA: Memristor-Enabled Memory-Centric Instruction-Set Architecture for Database Workloads
FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput
Microcode and the protection of intellectual effort
A network of dynamically microprogrammable machines
A tagless coherence directory
Sparsepipe: Sparse Inter-operator Dataflow Architecture with Cross-Iteration Reuse
The development of user microprogramming: A survey and status report
Proceedings of the 9th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2016, Taipei, Taiwan, October 15, 2016
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
Quantifying and improving the efficiency of hardware-based mobile malware detectors
Eureka: Efficient Tensor Cores for One-sided Unstructured Sparsity in DNN Inference
A microcoded multiprocessor crossbar network communications controller
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures
Application of hardware description languages to microprogramming: Method, practice, and limitations
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures
Designing Virtual Memory System of MCM GPUs
Design of a microprogrammed lexical microprocessor
Facilitating superscalar processing via a combined static/dynamic register renaming scheme
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
Procrustes: a Dataflow and Accelerator for Sparse Deep Neural Network Training
Accelerating Extra Dimensional Page Walks for Confidential Computing
Adaptive line placement with the set balancing cache
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
Architecture trade-offs in programmable signal processing
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models
Exploiting Inherent Properties of Complex Numbers for Accelerating Complex Valued Neural Networks
WaveScalar
Architectural Support for Fair Reader-Writer Locking
Draco: Architectural and Operating System Support for System Call Security
Reliability-Aware Task Scheduling using Clustered Replication for Multi-core Real-Time systems
Architectural flexibility in microprogramming
Evolution of the server processor/platform architecture and the critical role of interconnect and future challenges
Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems
Cache automaton
Token flow control
A high-speed dynamic instruction scheduling scheme for superscalar processors
Proteus: a flexible and fast software supported hardware logging approach for NVM
DTexL: Decoupled Raster Pipeline for Texture Locality
Design of a user-microprogrammable building block
Instruction Scheduling and Executable Editing
Exploiting a New Level of DLP in Multimedia Applications
Data relocation and prefetching for programs with large data sets
Optimal selection of functional components for microprogrammable central processing units
Microprogrammed operations for a three-value logic simulator
Filtered runahead execution with a runahead buffer
Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice
Offline symbolic analysis for multi-processor execution replay
GRIP: Graphics Reduced Instruction Processor
Leaky Way: A Conflict-Based Cache Covert Channel Bypassing Set Associativity
GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing
IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations
The use of a writable control memory in a multiprogramming environment
Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers
A systematic methodology to develop resilient cache coherence protocols
Microprogrammed implementation of computer measurement techniques
Secure Prefetching for Secure Cache Systems
A programmable, energy-minimal dataflow compiler and architecture
Predicting Data Cache Misses in Non-Numeric Applications through Correlation Profiling
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator
Code generation schema for modulo scheduled loops
Treelet Prefetching For Ray Tracing
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware
On the testing of microprogrammed processor
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems
A development environment for horizontal microcode programs
CoLT: Coalesced Large-Reach TLBs
Rubik: fast analytical power management for latency-critical systems
Design of an emulator oriented microprogrammable computer
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling
Managing static leakage energy in microprocessor functional units
Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
Notary: Hardware techniques to enhance signatures
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
Enhanced region scheduling on a program dependence graph
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem
Exploring Instruction Fusion Opportunities in General Purpose Processors
Improved instruction formation in the exhaustive local microcode compaction algorithm
Shadow Block: Accelerating ORAM Accesses with Data Duplication
Improving Region Selection in Dynamic Optimization Systems
Flexible processors: a promising application-specific processor design approach
McCore: A Holistic Management of High-Performance Heterogeneous Multicores