yusuke1997/dblp-id-title huggingface dataset:
Architectural Contesting
MaPU: A novel mathematical computing architecture
Fault-Tolerant Adaptive Routing for Two-Dimensional Meshes
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
An Architectural Evaluation of Java TPC-W
Parallel Computing for Irregular Applications
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
A performance analysis framework for optimizing OpenCL applications on FPGAs
Transportation-network-inspired network-on-chip
Processing-in-Memory Enabled Graphics Processors for 3D Rendering
Caches and Hash Trees for Efficient Memory Integrity Verification
Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor
Pitstop: Enabling a Virtual Network Free Network-on-Chip
HARE: Hardware assisted reverse execution
Featherlight Reuse-Distance Measurement
Augmenting low-latency HPC network with free-space optical links
Tapping ZettaRAM TM for Low-Power Memory Systems
CHIPPER: A low-complexity bufferless deflection router
Efficient scrub mechanisms for error-prone emerging memories
CEGMA: Coordinated Elastic Graph Matching Acceleration for Graph Matching Networks
Uncovering and Exploiting AMD Speculative Memory Access Predictors for Fun and Profit
i 2 WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations
Instruction Recycling on a Multiple-Path Processor
RMB - A Reconfigurable Multiple Bus Network
Near-Stream Computing: General and Transparent Near-Cache Acceleration
A market approach for handling power emergencies in multi-tenant data center
CHROME: Concurrency-Aware Holistic Cache Management Framework with Online Reinforcement Learning
Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors
Accelerating Graph Convolutional Networks Using Crossbar-based Processing-In-Memory Architectures
TALCO: Tiling Genome Sequence Alignment Using Convergence of Traceback Pointers
Feedback mechanisms for improving probabilistic memory prefetching
JETC: Joint energy thermal and cooling management for memory and CPU subsystems in servers
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000
Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems
Market Mechanism-Based User-in-the-Loop Scalable Power Oversubscription for HPC Systems
A Design Frame for Hybrid Access Caches
Efficient Memory Side-Channel Protection for Embedding Generation in Machine Learning
Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
SCD: A scalable coherence directory with flexible sharer set encoding
EVE: Ephemeral Vector Engines
Register Renaming and Scheduling for Dynamic Execution of Predicated Code
Transitively Deadlock-Free Routing Algorithms
Handling branches in TLS systems with Multi-Path Execution
Prosperity: Accelerating Spiking Neural Networks via Product Sparsity
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999
Compilers and parallel computing systems
SolarCore: Solar energy driven multi-core architecture power management
Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems
ViTALiTy: Unifying Low-rank and Sparse Approximation for Vision Transformer Acceleration with a Linear Taylor Attention
A low-radix and low-diameter 3D interconnection network design
Variability in Architectural Simulations of Multi-Threaded Workloads
Symbiotic job scheduling on the IBM POWER8
Completely verifying memory consistency of test program executions
Evaluation of a Multithreaded Architecture for Cellular Computing
Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs
Two Techniques for Improving Performance on Bus-Based Multiprocessors
PIM-VR: Erasing Motion Anomalies In Highly-Interactive Virtual Reality World with Customized Memory Cube
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors
The Named-State Register File: Implementation and Performance
MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design Using Mirror Gates
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM
Dynamic power-performance adaptation of parallel computation on chip multiprocessors
Performance-aware speculation control using wrong path usefulness prediction
A Domain-Specific On-Chip Network Design for Large Scale Cache Systems
From Optimal to Practical: Efficient Micro-op Cache Replacement Policies for Data Center Applications
Technology comparison for large last-level caches (L 3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM
Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches
Extending Commodity OpenFlow Switches for Large-Scale HPC Deployments
Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
Impact of Chip-Level Integration on Performance of OLTP Workloads
Rendering Elimination: Early Discard of Redundant Tiles in the Graphics Pipeline
Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors
iCache: An Importance-Sampling-Informed Cache for Accelerating I/O-Bound DNN Model Training
SegScope: Probing Fine-grained Interrupts via Architectural Footprints
MeHyper: Accelerating Hypergraph Neural Networks by Exploring Implicit Dataflows
GPGPU Power Modeling for Multi-domain Voltage-Frequency Scaling
Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors
PM3: Power Modeling and Power Management for Processing-in-Memory
NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search
Ah-Q: Quantifying and Handling the Interference within a Datacenter from a System Perspective
Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources
SizeCap: Efficiently handling power surges in fuel cell powered data centers
Power-efficient computing for compute-intensive GPGPU applications
Coordinated static and dynamic cache bypassing for GPUs
Shortest paths in Dragonfly systems
Root Crash Consistency of SGX-style Integrity Trees in Secure Non-Volatile Memory Systems
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators
Accelerating business analytics applications
TABLA: A unified template-based framework for accelerating statistical machine learning
FIGLUT: An Energy-Efficient Accelerator Design for FP-INT GEMM Using Look-Up Tables
SCOC: High-radix switches made of bufferless clos networks
Prediction router: Yet another low latency on-chip router architecture
Memory-Efficient Hashed Page Tables
Dynamic Optimization of Micro-Operations
CAPE: A Content-Addressable Processing Engine
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET
SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs
Leaky Frontends: Security Vulnerabilities in Processor Frontends
ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction
Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing
SPARK: Scalable and Precision-Aware Acceleration of Neural Networks via Efficient Encoding
DUANG: Fast and lightweight page migration in asymmetric memory systems
A quantitative performance analysis model for GPU architectures
Kelp: QoS for Accelerated Machine Learning Systems
ChargeCache: Reducing DRAM latency by exploiting row access locality
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads
Power-Aware Control Speculation through Selective Throttling
Eliminating microarchitectural dependency from Architectural Vulnerability
TSO-CC: Consistency directed cache coherence for TSO
Delay-Hiding energy management mechanisms for DRAM
Characterization of Direct Cache Access on multi-core systems and 10GbE
Abstraction and microarchitecture scaling in early-stage power modeling
D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory
Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals
Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads
Investigating the Performance of Two Programming Models for Clusters of SMP PCs
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
SLaC: Stage laser control for a flattened butterfly network
HyBP: Hybrid Isolation-Randomization Secure Branch Predictor
NUcache: An efficient multicore cache organization based on Next-Use distance
3D stacking of high-performance processors
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
Characterizing and Comparing Prevailing Simulation Techniques
DPUaudit: DPU-assisted Pull-based Architecture for Near-Zero Cost System Auditing
QuCLEAR: Clifford Extraction and Absorption for Quantum Circuit Optimization
Exploiting Two-Case Delivery for Fast Protected Messaging
CLITE: Efficient and QoS-Aware Co-Location of Multiple Latency-Critical Jobs for Warehouse Scale Computers
CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels
A Hybrid Framework for Fast and Accurate GPU Performance Estimation through Source-Level Analysis and Trace-Based Simulation
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
Memristive Data Ranking
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
Understanding Training Efficiency of Deep Learning Recommendation Models at Scale
Fifth Annual Workshop on Computer Education
4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, HiPINEB@HPCA 2018, Vienna, Austria, February 24, 2018
Fine-Tuning the Active Timing Margin (ATM) Control Loop for Maximizing Multi-core Efficiency on an IBM POWER Server
Enabling distributed generation powered sustainable high-performance data center
Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines Industry Track Paper
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
Practical off-chip meta-data for temporal memory streaming
Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management
Layerweaver: Maximizing Resource Utilization of Neural Processing Units via Layer-Wise Scheduling
Branch-mispredict level parallelism (BLP) for control independence
Improving in-memory database index performance with Intel ® Transactional Synchronization Extensions
A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems
HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array
Exploring Low-Latency Interconnect for Scaling Out Software Routers
Dynamically Specialized Datapaths for energy efficient computing
TinyTS: Memory-Efficient TinyML Model Compiler Framework on Microcontrollers
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging
BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States
Trends in High-Performance Processors
Multithreaded Execution Architecture and Compilation
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator
Architecting an Energy-Efficient DRAM System for GPUs
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations
Gaussian Blending Unit: An Edge GPU Plug-in for Real-Time Gaussian-Based Rendering in AR/VR
PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks
Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Addressing system-level trimming issues in on-chip nanophotonic networks
StreamPIM: Streaming Matrix Computation in Racetrack Memory
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures
CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters
CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design
Cepheus: Accelerating Datacenter Applications with High-Performance RoCE-Capable Multicast
ReTail: Opting for Learning Simplicity to Enable QoS-Aware Power Management in the Cloud
Reducing read latency of phase change memory via early read and Turbo Read
BCoal: Bucketing-Based Memory Coalescing for Efficient and Secure GPUs
Machine Learning-Guided Memory Optimization for DLRM Inference on Tiered Memory
Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links
OASIS: Object-Aware Page Management for Multi-GPU Systems
Improving cache performance using read-write partitioning
Cost effective physical register sharing
CloudCache: Expanding and shrinking private caches
PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems
A complete key recovery timing attack on a GPU
NT-Atom: building tools for performance studies
Billion Transistor Chips in Mainstream Enterprise Platforms of the Future
Understanding the Impact of Socket Density in Density Optimized Servers
InfoShield: a security architecture for protecting information usage in memory
Distributed Prefetch-buffer/Cache Design for High-Performance Memory Systems
Pilot Register File: Energy Efficient Partitioned Register File for GPUs
Architectural framework for supporting operating system survivability
Quantifying the Impact of Architectural Scaling on Communication
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems
ChameleonEC: Exploiting Tunability of Erasure Coding for Low-Interference Repair
Heat Stroke: Power-Density-Based Denial of Service in SMT
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
Impact of Buffer Size on the Efficiency of Deadlock Detection
I-CASH: Intelligently Coupled Array of SSD and HDD
Transition Phase Classification and Prediction
Evaluation of Active Disks for Decision Support Databases
Restore truncation for performance improvement in future DRAM systems
Scaling towards kilo-core processors with asymmetric high-radix topologies
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories
Just Say No: Benefits of Early Cache Miss Determinatio
A Delay Model and Speculative Architecture for Pipelined Routers
Hierarchical Backoff Locks for Nonuniform Communication Architectures
CORDOBA: Carbon-Efficient Optimization Framework for Computing Systems
Chip Multithreading: Opportunities and Challenges
Choco-Q: Commute Hamiltonian-based QAOA for Constrained Binary Optimization
An Argument for Simple COMA
An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent
Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities
Software-Controlled Multithreading Using Informing Memory Operations
Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning
The Sensitivity of Communication Mechanisms to Bandwidth and Latency
BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing
A case for Refresh Pausing in DRAM memory systems
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks
RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference
UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures
Compute Caches
Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020
A Small, Fast and Low-Power Register File by Bit-Partitioning
The 5th International Workshop on High-Performance Interconnection Networks in the ExaScale and Big-Data Era, HiPINEB@HPCA 2019, 17 February 2019, Washington, DC, USA
Enterprise Class Modular Cache Hierarchy
GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
A case for guarded power gating for multi-core processors
2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016
Revet: A Language and Compiler for Dataflow Threads
NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing
Dynamically detecting and tolerating IF-Condition Data Races
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism
Design and Analysis of an APU for Exascale Computing
Catching Accurate Profiles in Hardwar
Speculative Register Reclamation
LEGO: Spatial Accelerator Generation and Optimization for Tensor Applications
Active I/O Switches in System Area Networks
Flit-Reservation Flow Control
Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols
Thread-Spawning Schemes for Speculative Multithreading
GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition
QuickRelease: A throughput-oriented approach to release consistency on GPUs
EFLOPS: Algorithm and System Co-Design for a High Performance Distributed Training Platform
LogTM: log-based transactional memory
Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
Griffin: Rethinking Sparse Optimization for Deep Learning Architectures
Decoupled Vector Architectures
Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining
Value Based BTB Indexing for indirect jump prediction
PRISM: An Integrated Architecture for Scalable Shared Memory
Modeling Value Speculation
Increasing multicore system efficiency through intelligent bandwidth shifting
Understanding the performance-temperature interactions in disk I/O of server workloads
Worth their watts? - an empirical study of datacenter servers
DASC Cache
E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGAs
Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse
CAFO: Cost aware flip optimization for asymmetric memories
IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
The dual-path execution model for efficient GPU control flow
BeaconGNN: Large-Scale GNN Acceleration with Out-of-Order Streaming In-Storage Computing
Permutation Development Data Layout (PDDL)
SPADE: Sparse Pillar-based 3D Object Detection Accelerator for Autonomous Driving
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks
D-Shield: Enabling Processor-side Encryption and Integrity Verification for Secure NVMe Drives
Exploring Hyperdimensional Associative Memory
Energy-efficient interconnect via Router Parking
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows
DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs
A New Scalable Directory Architecture for Large-Scale Multiprocessors
Power punch: Towards non-blocking power-gating of NoC routers
DepGraph: A Dependency-Driven Accelerator for Efficient Iterative Graph Processing
Reconciling Selective Logging and Hardware Persistent Memory Transaction
Effects of Congestion Management on Energy Saving Techniques in Interconnection Networks
Branch History Guided Instruction Prefetching
Sentinel: Efficient Tensor Migration and Allocation on Heterogeneous Memory Systems for Deep Learning
CPU-assisted GPGPU on fused CPU-GPU architectures
Improving Locality of Irregular Updates with Hardware Assisted Propagation Blocking
User-Level Communication in Cluster-Based Servers
A Programmable Co-Processor for Profiling
Creating Converged Trace Schedules Using String Matching
Efficient footprint caching for Tagless DRAM Caches
Accelerating decoupled look-ahead via weak dependence removal: A metaheuristic approach
Safety Hints for HTM Capacity Abort Mitigation
Is hardware innovation over?
LSQCA: Resource-Efficient Load/Store Architecture for Limited-Scale Fault-Tolerant Quantum Computing
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
Predicting the memory bandwidth and optimal core allocations for multi-threaded applications on large-scale NUMA machines
RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems
Cache Memory Design for Network Processors
DLP + TLP Processors for the Next Generation of Media Workloads
Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash
A Spot Capacity Market to Increase Power Infrastructure Utilization in Multi-tenant Data Centers
Spare register aware prefetching for graph algorithms on GPUs
The case for GPGPU spatial multitasking
Tag tables
On Consistency for Bulk-Bitwise Processing-in-Memory
Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance
Performance Evaluation of Tiling for the Register Level
Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications
Exploring architectural heterogeneity in intelligent vision systems
Tacker: Tensor-CUDA Core Kernel Fusion for Improving the GPU Utilization while Ensuring QoS
NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks
Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing
A Write-Friendly and Fast-Recovery Scheme for Security Metadata in Non-Volatile Memories
Optimizing virtual machine scheduling in NUMA multicore systems
Multi-core demands multi-interfaces
Impulse: Building a Smarter Memory Controller
FlashGNN: An In-SSD Accelerator for GNN Training
Stream Floating: Enabling Proactive and Decentralized Cache Optimizations
PREMA: A Predictive Multi-Task Scheduling Algorithm For Preemptible Neural Processing Units
Store vectors for scalable memory dependence prediction and scheduling
Incorporating Predicate Information into Branch Predictors
Revisiting HyperDimensional Learning for FPGA and Low-Power Architectures
Hardware-Accelerated Hypergraph Processing with Chain-Driven Scheduling
SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering
DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability
CORD: cost-effective (and nearly overhead-free) order-recording and data race detection
17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA
Fault-Tolerant Multicast Routing in the Mesh with No Virtual Channels
Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation
Efficient instruction schedulers for SMT processors