yusuke1997/dblp-id-title huggingface dataset:
An Adaptive Input Voltage Current-Balanced Analog Frontend System for Multiple Cell Li-ion Battery Electrochemical Impedance Monitoring
Exploring the Impact of Adding Adversarial Perturbation onto Different Image Regions
Multiple Upsets Tolerance in SRAM Memory
A 20-Gbps low jitter analog clock recovery circuit for ultra-wide band Radio systems
Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC)
All-Digital Successive Approximation TDC in Time-Mode Signal Processing
A hybrid CMOS imager with sensing and energy harvesting capabilities
Joint Representation Learning for Anomaly Detection in Surveillance Videos
VLSI architectures for the implementation of the Wigner distribution
A Digitally Assisted Tunable High Pass Filter Based on Flexible a-IGZO TFTs for Biomedical Applications
Design of low-power and low-phase noise VCO in standard 0.13μm CMOS
Event-driven dynamic power management based on wavelet forecasting theory
Effective routing algorithms based on node usage probability from a complex network perspective
A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing
Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study
A power-on reset pulse generator for low voltage applications
On finite-precision implementation of a decoder for turbo codes
Efficient Cell Segmentation and Classification by Leveraging an Auto Prompt Generator and a New Fine-Tuning Strategy
Process and Temperature Calibration of PLLs with BiST Capabilities
Subblock-level matching layout for analog block-pair and its manufacturability evaluation
A 2mA-2.5V Low Phase Noise Multi-standard VCO
A 95% efficiency Buck-Boost Converter with Full-Cycle Continuous Current Sensing and Adaptive Mode Control
Static floating-point unit with implicit exponent tracking for embedded DSP
A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise
A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring
A Sub-μW Digital Temperature Compensation Architecture for Arbitrary Voltage and Current Reference Generation
A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter
Scaleable check node centric architecture for LDPC decoder
Time-based arithmetic using step functions
A new Temporal-Constraint-Based algorithm by handling temporal qualities for video enhancement
Improvised NanoSPR biosensor system utilizing gold nanorods and nanohole array film
High-frequency dynamic translinear and log-domain circuits in CMOS technology
Passive Wireless Channel Estimation in RF Tag Network
Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs
A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration
Low-Dimensional Conditions for Global Asymptotic Stability of M-D Nonlinear Digital Filters
Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback
Programmable video clock synthesizer with sub 0.5 ns drift
Loop Filter Design Considerations for Noise-Shaping in SAR ADCs
Design of energy-efficient on-chip EEG classification and recording processors for wearable environments
Multiple description video coding based on zero padding
Adaptive arithmetic coding for image prediction errors
Embedding Guide: Improving Watermarking Robustness and Imperceptibility based on Attention and Edge Information
High loop-filter-order ΣΔ-fractional-n frequency synthesizers for use in frequency-hopping-spread-spectrum communication-systems
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder
Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process
Convergence properties of mixed-norm algorithms under general error criteria
Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages
A low-power ratiometric single/differential quasi-digital converter
POCO: Hardware Characterization of Activation Functions using POSIT-CORDIC Architecture
Orthogonalized Linear Discriminant Analysis based on Modified Generalized Singular Value Decomposition
A novel queuing architecture for background calibration of pipeline ADCs
Model trust region technique in parallel Newton's method for training feedforward neural networks
Community structure promotes the emergence of persistence behavior in social networks
A lossless frame recompression scheme for reducing DRAM power in video encoding
A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators
Application of scalable visual sensitivity profile in image and video coding
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization
Case Study: Understanding Internet Anomalies
Zero skew clock routing with tree topology construction using simulated annealing method
Configurable and Intelligent Switched CMOS Current Driver Powering Arrays of Electrothermal Actuators for MEMS Switches
A fully digital ADC using a new delay element with enhanced linearity
A 1.2V buck converter with a novel on-chip low-voltage current-sensing scheme
A widely tunable active RF filter topology
Discrete fractional Fourier transform based on the eigenvectors of Grünbaum tridiagonal matrix
Signature-Based Intrusion Detection System (IDS) for In-Vehicle CAN Bus Network
Memory-based crosstalk canceling CODECs for on-chip buses
Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs
Novel algorithm for the real time multi-feature detection in laser beam welding
A Chip-based Miniature MRI Platform with Integrated PDMS-PCB Coil Frontend for Microlitre-volume Sample Analysis
Frequency domain clutter removal for compressive OFDM ground penetrating radar
Symmetric split-row LDPC decoders
WS-CIM: Enabling Fast and Simultaneous Update for Multi-Macro Compute-in-Memory Architecture Using Weight Sharing Technique
A 10kfps 32×32 integrated test platform for electrical characterization of imagers
ADMM-based infinity norm detection for large MU-MIMO: Algorithm and VLSI architecture
Integrated Charge-pump Phase-locked Loop with SC-loop Filter for Capacitive Microsensor Readout
Adaptive Combination of Two Multi-Sample Multiband-Structured Subband Adaptive Filters
Blind uplink space-time channel estimation for space-time coded multicarrier code division multiple access systems
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity
Quadrature Modulated Filter Banks
Optimized Bit Allocation for Learning-based Video Compression
Adaptive classifiers using ontogenetic neural networks with feedback
Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR
Content based color image adaptive watermarking scheme
An Optimization Algorithm for Color Table Coding of Palette for VVC Based on DPCM and CCLP
A CMOS instrumentation amplifier for wideband bioimpedance spectroscopy systems
Full current-mode techniques for high-speed CMOS SRAMs
Nonlinear effects in electrostatic vibration energy harvesters: Current progress and perspectives
An offset compensation technique for bandgap voltage reference in CMOS technology
A Highly PVT Invariant Low Power Scalable Analog Dynamic Current-Mode Translinear Matrix-Vector Multiplier
Architecture-aware low-density parity-check codes
Chaotic behaviour in a three element memristor based circuit using fourth order polynomial and PWL nonlinearity
A multilevel data reuse scheme for Motion Estimation and its VLSI design
Live demonstration: Convolutional neural network driven by dynamic vision sensor playing RoShamBo
An FPGA-based, multi-channel, real-time, motion artifact detection technique for fNIRS/DOT systems
Live demonstration: "Internet Booster" a novel WEB application platform accelerated by reconfigurable virtual hardware circuits
Frequency-domain steering for negative beamformers in speech enhancement and directional source separation
An Efficient Method for Estimation of Autoregressive Signals Subject to Colored Noise
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM
A New Paradigm for Developing Digital Systems Based on a Multi-Cellular Organization
CMOS cryptosystem using a Lorenz chaotic oscillator
Efficient and Robust Test Generation-Based Timing Analysis
Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters
Remedies for noise degradation due to active Q-Enhancement Circuit
Thermal Modeling and Temperature Driven Placement for FPGAs
A CMOS dB-linear VGA with pre-distortion compensation for wireless communication applications
The energy cost of network security: A hardware vs. software comparison
Analog complex gammatone filter for cochlear implant channels
A temperature compensated linear output RF amplifier with programmable gain control
Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory
Correction of operational amplifier gain error in pipelined A/D converters
Blind estimation and equalization of time-varying channels using the interacting multiple model estimator
Adaptive Hierarchical Multi-objective Fuzzy Optimization for Circuit Design
Enhanced versions of DCSK and FM-DCSK data transmission systems
Low overhead in situ aging monitoring and proactive aging management
A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme
Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits
A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOS
The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations
Investigating stability and bifurcations of a boost PFC circuit under peak current mode control
Precision Agriculture for Small to Medium Size Farmers - An IoT Approach
Electro-active polymers as CNN actuators for locomotion control
Using QBF to increase accuracy of SAT-based debugging
Detailed analyses in prediction of capacitive-mismatch-induced offset in dynamic comparators
IMSSA: Deploying modern state-space models on memristive in-memory compute hardware
A baseband Testbed for Uplink Mobile MIMO WiMAX Communications
An acoustic noise suppression system with reduced musical artifacts
A New Approach of Fractional-Dimension Based Module Clustering for VLSI Layout
On reduced complexity IIR adaptive filters
Biphasic stimulator circuit for a wide range of electrode-tissue impedance dedicated to cochlear implants
Modeling and Characterization of Intra-Body Links for a Smart Contact Lens
Distance sensing for mini-robots: RSSI vs. TDOA
Joint 2D Object Detection and 3D Reconstruction via Adversarial Fusion Mesh R-CNN
A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface
A low power 2.2-2.6GHz CMOS VCO with a symmetrical spiral inductor
CMOS optical receiver chipset for gigabit Ethernet applications
A new approach based on LFF for optimization of dynamic hardware reconfigurations
SSC tracking analysis and a deeper-SSC estimator
Fuzzy temporal representation and reasoning
A power-area-efficient impedance sensor design for 10 × 10 microelectrode array sensing
Area-efficient and fast sign detection for four-moduli set RNS {2 n -1, 2 n , 2 n +1, 22 n +1}
Design for test of a low power multi-standard GPS/GALILEO RF front-end
PMOS vs NMOS ZTC References: A Process Technology-Dependent Analysis Framework
Color video denoising based on adaptive color space conversion
Bulk-Input VCO-Based Sigma-Delta ADCs with Enhanced Linearity in 28-nm FD-SOI CMOS
Design of Diamond and Circular Filters by Semi-definite Programming
Probabilistic Error Modeling for Two-part Segmented Approximate Adders
A subspace constrained constant modulus algorithm for blind array
Worst-case l 1 system identification using perturbed ARMA models
A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications
Low voltage, low power, high performance current conveyors
A self-adaptive body channel communication scheme for backward path loss reduction
CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices
A Delta-Sigma-Modulation Multi-Channel Network with Improved Noise-Shaping Characteristics
A Soft RISC-V Processor IP with High-performance and Low-resource consumption for FPGA
Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes
Global convergence analysis of decomposition methods for support vector machines
Modeling RTOS Components for Instruction Cache Hit Rate Estimation
A novel self-tuning pulse width modulator based on master-slave architecture for a Class D amplifier
An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals
Architecture and Algorithm Co-Design Framework for Embedded Processors in Event-Based Cameras
Support-driven sparse coding for face hallucination
Universal embedded compression engine for LCD TV system-on-a-chip with Band-Expansion Progressive Wavelet Coding
SCiMA: A Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations
Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning
A 16.42 TOPS/mm 2 Reverse Rotating Charge Sharing DRAM Compute-in-Memory Design in 28nm Process
A process independent ESD design methodology
RRAM-PoolFormer: A Resistive Memristor-based PoolFormer Modeling and Training Framework for Edge-AI Applications
Packet scheduling based on Geo Y /G/infinity input process modeling for streaming video
High performance VLSI architecture of fractional motion estimation in H.264 for HDTV
The Effect of Node Centrality on the Evolution of Cooperation in Social Networks
A low latency and area efficient FFT processor for massive MIMO systems
An improved RNS reverse converter for the {2 2n+1 -1, 2 n , 2 n -1} moduli set
An algorithm for multi-layer channel routing problem using chaotic neural networks
Towards quantum information with trapped calcium ions
An algorithm for automatic model-order reduction of nonlinear MEMS devices
Extraction of Fowler-Nordheim parameters of thin SiO 2 oxide film including polysilicon gate depletion: validation with an EEPROM memory cell
Minimizing switchings of the function units through binding for low power
An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners
Analog fault AC dictionary creation - the fuzzy set approach
Cross recurrence verification technique for process variation-resilient analog circuits
Wireless Stimulus-Reflex Detection for Neonatal Monitoring
Parallel palette mode decoding for HEVC SCC
A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity
A first course in electronics
Hybrid inverse halftoning using adaptive filtering
Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition
Novel grid-based power routing scheme for regular controllable-polarity FET arrangements
A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique
Fast and accurate estimation of gain and sample-time mismatches in time-interleaved ADCs using on-chip oscillators
A Low-Voltage High-Performance Differential Static Logic (LVDSL) family
A single stage decimator architecture for sigma-delta demodulators using Laguerre filters
An equivalent-time and clocked approach for continuous-time quantization
A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1 + -Point Modulation
Fault tolerant adaptive filters based on the block LMS algorithm
Learning to Conceive, Design, Implement and Operate Circuits and Systems
A 61 mHz - 3.4 Hz High-pass Capacitively Coupled Analog Frontend with Tunnelling Biasing and Output DC Servo Loop
Perfect tracking control using multirate control in magnetic levitation system
Generic Model for Multi-Phase Ring Oscillators
A Body-Driven, 1.8 nW, 75 dB Gain, Single Stage OTA, for ULV and ULP Applications
Effective capacitance for gate delay with RC loads
Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators
Lossless compression for medical imaging systems using linear/non-linear prediction and arithmetic coding
Conditions and Emulation of Double Pinch-off Points in Fractional-order Memristor
A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator
Mixed-signal flexible architecture for the synthesis of n-port networks
A generalized study of multiphase parallel resonant inverters for high-power applications
High-speed RF multi-modulus prescaler architecture for ΣΔ fractional-N PLL frequency synthesizers
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths
Algorithm and implementation of digital calibration of fast converging Radix-3 SAR ADC
Current source calibration by combination selection of minimum sized devices
Evaluation of a crossbar multiplexer in a lithography-based nanowire technology
On the optimal labeling for pseudo-chaotic phase hopping
A 2.5 Gb/s CMOS Burst-Mode Limiting Amplifier for GPON System
A multilayer feedforward neural network with adaptive lookup table weight
Design of maximally flat group delay filters
Stochastic ΔΣ VCO-ADC Utilizing 4× Staggered Averaging
A low-noise cartesian error feedback architecture
LC-VCO automatic synthesis using multi-objective evolutionary techniques
Network-on-chip link analysis under power and performance constraints
Power-adaptive operational amplifier with positive-feedback self biasing
A portable specification of zero-overhead looping control hardware applied to embedded processors
A mixed-mode temperature control circuit for gas sensors
Shadow removal from natural images
System-Level Modeling and Design of a Temperature Compensated CMOS MEMS Thermal Flow Sensor
Evaluation of Algorithms for Low Energy Mapping onto NoCs
Various superstable synchronous phenomena in switch-coupled relaxation oscillators
Practical considerations in VLSI IC design flow with respect to tool limitations
Joint optimization of error feedback and coordinate transformation for roundoff noise minimization in state-space digital filters
A new full CMOS 2.5 V two-stage line driver with variable gain for ADSL applications
Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard
PLL-Free Quadrature-Amplitude Modulation in Coherent Optical Communication
Hardware accelerators for biocomputing: A survey
Lightweight FPGA Implementation of the Shadow PUF Module for Generating Reconfigurable Proxy PUFs
Mode-Adaptive Subsampling of SAD/SSE Operations for Intra Prediction Cost Reduction
On relation between non-disjoint decomposition and multiple-vertex dominators
Design of an efficient variable-length FFT processor
An efficient balanced truncation realization algorithm for interconnect model order reduction
Parallel converter systems with maximum current limit control scheme for reliability improvement
Analogue adaptive filters using wave synthesis technique
Multi-mode controller CMOS integrated circuit for switching power converters
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC
Contributions to the analysis of second order piecewise linear systems with chaotic oscillations
Live Demonstration: Hardware-Oriented Dual Stream Object Recognition System using Binarized Neural Networks
Current-mode clock distribution
Design of high-speed multiplierless linear-phase FIR filters
Editable asynchronous control logic for SAR ADCs
Transient Analysis of Nonlinear Settling Behavior in Charge-pump Phase-locked Loop Design
Scalable blind calibration of timing skew in high-resolution time-interleaved ADCs
A Precise and Reliable Engine Knock Detection Utilizing Meta Classifier
Integrated Sensor Array Platform for Monitoring Chemical Contaminants in Water Sources
Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's
Design of a CMOS low-voltage low-power circuit for an integrated pulsed ultrasonic distance measurement system
Integral observer approach for chaos synchronization with transmission disturbances
Cut-off frequencies in wide-band systems
Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model
A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers
A wireless neural/EMG telemetry system for freely moving insects
Imaging Transmission Line Impedance Profiles using Passband Signals and Adaptive Sequence Design
Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework
Measuring Photosynthetically Active Radiation with a Multi-Channel Integrated Spectral Sensor
Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits
Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops
A 1 GHz linearized CMOS track-and-hold circuit
A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm
Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor
Analysis of RLC interconnect delay model using second order approximation
International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece
A new algorithm for compressive sensing based on total-variation norm
A 6.78MHz Wireless Power Transfer System With Efficient Global Hysteresis Control for Implantable Medical Devices
Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets
Deflection routing in complex networks
Investigating wind speed-dependent models for electric power transmission lines
Reduction of the effects of spurious PLL tones on A/D converters
Fast and scalable priority encoding using static CMOS
Dynamic hand gesture recognition for wearable devices with low complexity recurrent neural networks
A framework for the design of error-aware power-efficient fixed-width Booth multipliers
Time Domain Multiplexing for Equalized Vibration in Miniaturized Electromagnetic Tactile Pixels
PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design
Computer Formulation of Averaged Models for Periodically-Switched Networks
RC polyphase filter with flat gain characteristic
LIPSFUS: A neuromorphic dataset for audio-visual sensory fusion of lip reading
A novel 1-V class-AB transconductor for improving speed performance in SC applications
Structure and information content in sequences from the single-loop sigma-delta modulator with DC input
On Sequential Diagnosability of 2-Dimensional Meshes and Tori
Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation
A portable phonocardiographic fetal heart rate monitor
Dual queue based rate selecting schedule for throughput enhancement in WLANs
A 2.4µW Wake-up Receiver for wireless sensor nodes with -71dBm sensitivity
An innovative scheduling scheme for high-speed network processors
Fast operators for arbitrary warping maps
Performance of pn-junction diode lumped models for circuit simulators
Down-sampling based video coding with super-resolution technique
A power-efficient architecture for EBCOT tier-1 in JPEG 2000
Complex Cascaded Bandpass SigmaDelta ADC Design
MEIN: A Multicast-Efficient Interconnect Network for Multi-Chiplet DNN Accelerators
Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers
Design of a transistor-mismatch-insensitive switched-current memory cell
Boundaries Between Fast-and Slow-Scale Bifurcations in Parallel-Connected Buck Converters
A threshold voltage variation cancellation technique for analogue peripheral circuits of a display array using poly-Si TFTs
Minimal time reachability problem of some subclasses of timed Petri nets
Image encryption using progressive cellular automata substitution and SCAN
Algorithmic truncation of minimax polynomial coefficients
Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor