yusuke1997/dblp-id-title huggingface dataset:
All-digital frequency and clock synthesis architectures from a signals and systems perspective, current state and future directions
A novel method to count the red blood cells in thin blood films
Upsampling Improvement for Overfitted Neural Coding
Analysis of assessment using signals, systems concept inventory for systems courses
Lyapunov-based stability analysis of supervised and unsupervised adaptive algorithms
Live demonstration: A high-speed-pass asynchronous motion detection sensor
PLL-less clock multiplier with self-adjusting phase symmetry
Design of second order digital differentiator using Richardson extrapolation and fractional delay
A CMOS automatic tuning system to maximize remote powering efficiency
Minimization of L 2 -sensitivity for 2-D state-space digital filters subject to L 2 -scaling constraints
Efficient linear macromodeling via least-squares response approximation
Optical wireless receiver for data delivery to retinal implant
Configuring of Spiking Central Pattern Generator Networks for Bipedal Walking Using Genetic Algorthms
Phase noise analysis of a homodyne radar system driven by a phase-locked loop
Differential pair sense amplifier for a robust reading scheme for memristor-based memories
High accuracy sub-pixel image registration under noisy condition
A Current-Driven Potentiostat Architecture for Achieving Stability Over a Wide Range
A robust differential scan flip-flop
A 2GHz direct digital frequency synthesizer based on multi-channel structure
Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters
Highly sensitive silicon micro-g accelerometers with optical output
Subthreshold CMOS Implementation of the Izhikevich Neuron Model
The upper bound of the second-order modes of linear state-space systems [digital filter example]
A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit
Development of 4-GHz flip-chip VCO module
A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply
Algorithmic ADC Offset Compensation by Non-White Data Chopping
Low-power design for cell search in W-CDMA
Sensor-based Dynamic Control of the Central Pattern Generator for Locomotion
On the duality gap for thermal unit commitment problems
Design of chaotic spread-spectrum sequences with good correlation properties for DS/CDMA
Online seam tracking for laser welding with a vision chip and FPGA enabled camera system
Phase pattern switching in star-coupled Wien-bridge oscillators driven by pulse train
Overview of resistive switching memory (RRAM) switching mechanism and device modeling
SS27 Radiation Protection and Monitoring Experiment on-Board a 1U CubeSat and its Ground Verification
Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip
An Efficient Data Parallelization of the Radix-2 3 (Carbon) FFT on GPU/CPU
A novel MUX-FF circuit for low power and high speed serial link interfaces
An inductive-coupling interconnected application-specific 3D NoC design
State-space averaging of switched-inductor-cell for PWM dc-dc converters considering conduction losses in both operational modes
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications
Design of two-dimensional cosine-modulated oversampled FIR filter banks: PR condition
Robust transition density estimation by considering input/output transition behavior
Slew-rate controlled 800Mbps transmitter in 65nm CMOS
Application of Evolutionary Deep Neural Netwok to Photovoltaic Generation Forecasting
Tensor-based fusion of EEG and FMRI to understand neurological changes in schizophrenia
Improving Pin Accessibility of Standard Cells Through Fin Depopulation
A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths
Parasitic-aware synthesis of RF CMOS switching power amplifiers
The missing observations theorem and a new proof of Levinson's recursion
Design of multi-residue generators using shared logic
8 GHz tunable CMOS quadrature generator using differential active inductors
Closed Form Parameters Estimation for Near Field Sources
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator
Reactance network shaping a sinusoidal pulse with sinusoidal envelope of finite duration
A secure scan chain test scheme exploiting retention loss of memristors
Direct RF sampling continuous-time bandpass Delta-Sigma A/D converter design for 3G wireless applications
Current-mode synthetic control (CSC) technique for high efficiency DC-DC boost converters over a wide load range
Multi-Zone Division-Based Inter Prediction for Versatile Video Coding
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking
A Performance Comparison on Asynchronous Matched-delay Templates
REFET replication for ISFET-based SNP detection arrays
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
Analog circuit sizing with dynamic search window
Design and optimization of continuous-time filters using geometric programming
Optimization of shield structures in analog integrated circuits
Joint carrier and frame synchronization for MPSK demodulation
An Accurate EEG-based Deep Learning Classifier for Monitoring Depth of Anesthesia
Fully Optimized Convolutional Neural Network Based on Small-Scale Crowd
Reconfiguration network design for SEU recovery in FPGAs
A method for online secondary path modeling in active noise control systems
Enhancing power analysis attacks against cryptographic devices
Performance Walls in Machine Learning and Neuromorphic Systems
AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing
Algorithms for nonuniform bandpass sampling in radio receiver
Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiers
Development of DC/DC regulators based on switched-capacitor circuits
VLSI implementation of LS-SVM training and classification using entropy based subset-selection
Blind identifiability of general constellations
Improved Two-Layer Coding Schemes for Motion Picture Sequences
Live Demo: Reconfigurable Low-noise Multichannel Amplifier for Neurochemical Recording
A multi-step P-cell for LNA design automation
Simulation and analysis of distributed PV generation in a LV network using MATLAB-Simulink
A low-power silicon-on-sapphire tunable ultra-wideband transmitter
Resource-Efficient Compilation of Distributed Quantum Circuits for Solving Large-Scale Wireless Communication Network Problems
On-Chip Substrate Noise Suppression Using Clock Randomization Methodology
A UWB CMOS 0.13µm low-noise amplifier with dual loop negative feedback
New graph-based algorithms for partitioning VLSI circuits
Overcoming Impedance-Mismatch Induced Offsets in Background Bond Wire Defect Detection
Drift-free multiple description video coding with redundancy rate-distortion optimization
A 1.5-V supply, video range frequency, Gm-C filter
A parallel sampling scheme for ultra-wideband signal based on the random projection
Design of a reconfigurable AES encryption/decryption engine for mobile terminals
Gain Mismatch Insensitive Time-Interleaved DAC for CT Delta Sigma Modulator by application of a Three-State DAC
An approach for analysing and improving fault tolerance in radio architectures
Deep Brain Neurostimulation Through Engineered Circular Spiral Micro-Coils
Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware
Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition
On the impact of packet-loss impairments on visual attention mechanisms
Empowering the Future Workforce: Enhancing Student Participation and Securing Skilled Professionals through Extracurricular STEM Courses
Challenges and approaches to software defined duplexing radio
A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme
The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement Circuit
Image authentication using content based watermark
Individual Weighting of Unlabeled Data Points via Confidence-Awareness in Semi-Supervised Learning
On the Synchronization of Oscillators Coupled by One Negative Resistor
Live Demonstration: A Mixed-Mode Signal CMOS Chip for Hyperdimensional Computing
Area-efficient memory-based architecture for FFT processing
On the Design of Stabilizing Control for Structured Uncertain Singularly perturbed Systems
Dynamical analysis of single-inductor dual-output DC-DC converters
Economical passive filter synthesis using genetic programming based on tree representation
Parallel randomized KD-tree forest on GPU cluster for image descriptor matching
Iterative MAP multi-user detection of synchronous CDMA with channel distortion
Numerically efficient robustness test for nonlinear circuit models
A 1 V front-end interface for switched-op amp circuits
Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate
New Riemannian metrics for speeding-up the convergence of over- and underdetermined ICA
A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation
StreamDCIM: A Tile-based Streaming Digital CIM Accelerator with Mixed-stationary Cross-forwarding Dataflow for Multimodal Transformer
A New Approach to Reconfigure Faulty Systolic Array
Freewheel duration adjustment circuits for charge-control single-inductor dual-output switching converters
A New Parallel Algorithm for Solving Sparse Linear Systems
Transient analysis of nonlinear transmission lines by hybrid harmonic balance method
Design of low-voltage low-power SC filters for high-frequency applications
ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications
A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs
A New Loss-reduced Distributed Amplifier Structure
A low-cost point-to-multi-point access system based on OFDM transmission
Novel bit manipulation unit for communication digital signal processors
A double loop continuous-time adaptive equalizer
Alternating Greedy Schedules: Enabling Low-Bitwidth Accumulation of Dot Products in Neural Network Computations
Privacy preserving data mining with unidirectional interaction
Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis
Spur reduction in wideband PLLs by random positioning of charge pump current pulses
Design and analysis of rectifying and regulating rectifier with PWM and PFM modes
Hardware implementation of the double-tree scan architecture
Multiplier structures for low power applications in deep-CMOS
Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm
A PPG Readout Integrated With RPTT Estimation in Analog For Blood Pressure Measurement
A novel integration of on-sensor wavelet compression for a CMOS imager
A hybrid approach to I/Q imbalance self-calibration in reconfigurable low-IF receivers
Use of the oscillation based built-in self-test method for smart sensor devices
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels
Naturalness preserving transform for missing frame compensation
NMM-Based Patient-Specific Temporally-Adaptive Stimulation Optimization for Seizure Control
Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing
Multi-routing schemes for ad-hoc wireless networks
Fast system-level exploration of memory architectures driven by energy-delay metrics
Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs
On leakage current temperature characterization using sub-pico-ampere circuit techniques
Simplified depth intra mode selection for 3D video compression
On the Genome Sequence Alignment FPGA Acceleration via KSW2z
A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications
A semi-formal methodology for the functional validation of an industrial DSP system
Analogue Active Filters with Two-Tone Large-Signal Excitation
Stack robust fine granularity scalability
A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications
Loop gain analysis and development of high-speed high-accuracy current sensors for switching converters
Topological criteria for switched mode DC-DC converters
Is Broken Cable Breaking Your Security?
Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for 1024-Channel μECoG
Time-delay direction finding based on canonical correlation analysis [electronic warfare applications]
Recent progress in redox-based resistive switching
Outage in chaos communication
A Kalman filter based on wavelet filter-bank and psychoacoustic modeling for speech enhancement
Signal integrity verification of coupled interconnect lines using efficient eye-diagram determination
A Low-Power Non-Uniform Third-Derivative-Based Sampling Technique for ECG Applications
An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators
A 10MHz to 100MHz bandwidth scalable, fully differential current feedback amplifier
Modified cellular neural network architecture for integrated image sensing and processing
A dual switched-capacitor integrator architecture for versatile, real-time amperometric biosensing
Active-clamp ZVS two-switch flyback converter
Limit cycles in single-stage delta-sigma modulators
CSIA-UIM: A Universal Ising Machine Based on CIM-friendly Spring-Ising Algorithm
A 32×32 cellular test chip targeting new functionalities
Modernizing Hardware Circuits through High-Level Synthesis
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation
Fixed-width CSD multipliers with minimum mean square error
Simulating Phase Noise in Phase-Locked Loops with a Circuit Simulator
Algorithm and Architecture Design for Wide Range ELA Deinterlacer
Testing Stability of Bivariate Continuous-Time System Polynomials
A Novel Scale-free Network Model with Accelerating Growth
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part I - Algorithm
Viewpoint-Adaptive Collage-based Streaming for 4K Light Field Video
On performance of a charging/rewarding scheme in mobile ad-hoc networks
A low-IF, polyphase receiver for DECT [in BiCMOS]
An accurate automatic system for distinguishing neuropathy and healthy electromyography signals
A 16-Channel Neural Recorder with 2.8 nJ/bit, 971.4 kbps sub-2.4 GHz polar transmitter
A bump-circuit-based motion detector using projected-activity histograms
Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception
Series-parallel association of transistors for the reduction of random offset in non-unity gain current mirrors
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration
Analysis of the envelope and the instantaneous phase and frequency of superregenerative oscillators
Dynamic Precision Scaling for Low Power WCDMA Receiver
An enhanced Neuro-Space mapping method for nonlinear microwave device modeling
Parallel memristors: Improving variation tolerance in memristive digital circuits
Self-Learning Neuromorphic Robot Based on Reward-Driven Spiking Neural Network
A 12A 50V half-bridge gate driver for enhancement-mode GaN HEMTs with digital dead-time correction
TG Master-Slave FFs: High-speed optimization
A Novel Memristor-Based Majority Logic and Efficient Approximate Full Adder for Image Processing
Analysis of multi-hypothesis motion compensated prediction for robust video transmission
Another look at the retina as an image scalar quantizer
Enhancing Wake-Up Receivers Reliability through Preamble Filtering and Minimum Energy Coding
A CMOS low sensitivity switched-capacitor video filter
The self-tuned regenerative electromechanical arametric amplifier: A model for Active amplification in the cochlea
Transient error management for partially adaptive router in network-on-chip (NoC)
Image compression using texture modeling
An analog phase prediction based fractional-N PLL
Monolithic Spiral Transformers: A Design Methodology
Blind adaptive equalizer for IIR channels with common zeros
Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devices
Cryogenic Support Circuits and Systems for Silicon Quantum Computers
Supersonic Flow Simulation on IBM Cell Processor based Emulated Digital Cellular Neural Networks
Computation in communication: Spike event coding for programmable analog arrays
QRD-based lattice algorithm for a generalized multichannel least squares adaptive filtering
1kHz 2D silicon retina motion sensor platform
A variant of learning vector quantizer based on the L 2 mean for segmentation of ultrasonic images
ETHFB: a new class of even-length wavelet filters for Hilbert pair design
High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting
A new countermeasure against scan-based side-channel attacks
Live Demonstration: N2 Nanosheet Pathfinding-PDK
A CMOS image sensor with spiking pixels for retinal stimulation
Video Deep Learning Classification for Autonomous Vehicle Navigation
GNeRF: Accelerating Neural Radiance Fields Inference via Adaptive Sample Gating
Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator
Robust design and design automation for flexible hybrid electronics
Silicon Superior Colliculus for the Integration of Visual and Auditory Information with Adaptive Axon Connection
Global adaptive synchronization based upon polytopic observers
A Novel Weighted Hybrid Multi-View Fusion Algorithm for Semi-Supervised Classification
Simple circuit-based solution to problem of residential load participation in demand response
A Human Vision System based Flash Picture Coding Method for Video Coding
Flexible Memory, Bit-Passing and Mixed Logic/Memory Operation of two Intercoupled FeFET Arrays
Delta-Sigma Converters Using Frequency-Modulated Intermediate Values
A Quad Joint Relational Feature for 3D Skeletal Action Recognition with Circular CNNs
Fine-grained splitting methods to address permanent errors in Network-on-Chip links
FPGA implementation of a factorization processor for soft-decision reed-solomon decoding
Fast multilevel floorplanning for large scale modules
Roundoff-noise shaping in filter design
Power IC Design for Testability
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression
Technique for Peak to Average Power Ratio Reduction suited for M-carrier WCDMA Base Station Transmitters
VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation
Low cost logarithmic techniques for high-precision computations
Transformation methods for reducing sensitivities of current-mode CCII-based filters
High-performance multiplierless transform architecture for HEVC
Consideration of transcoding using updatable scalability for selective quality video content delivery method
An Application Specific Vector Processor for CNN-Based Massive MIMO Positioning
IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023
Monitoring System for Kinetic Energy Harvesting in a Mobile Platform
MLIP Cores: Designing Hardware Generators with Programmable Microarchitectural Mechanisms
Single chip implementation of the 1.6 kbps speech vocoder
Two-dimensional partially differential cepstrum and minimum-phase sequence construction
Complex wave filters and wave group-delay equalisers in log-domain
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique
Parameterized SoC design for portable systems
Efficient Multiple-Precision Posit Multiplier
An ultra low-voltage Gm-C filter for video applications
Neuromorphic implementation of attractor dynamics in decision circuit with NMDARs
Complementary structure of memristive devices based passive memory arrays
A Systematic Side-Channel Evaluation of Black Box AES in Secure MCU: Architecture Recovery and Retrieval of PUF Based Secret Key
Signal Identification of DNA Amplification Curves in Custom-PCR Platforms
Readout IC with 40 MSPS in-pixel ADC for future vertex detector upgrades of Large Hadron Collider
Bidirectional buffer for mixed voltage applications
Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System
Three-Dimensional Linear Trajectory Filtering Using the DWT and the Mixed-Domain Approach
A novel C-band CMOS phase shifter for communication systems
Sample-and-hold amplifiers performing internal antialiasing filtering and their applications in digital receivers
A Stable Physically Unclonable Function Based on a Standard CMOS NVR
Neuromorphic devices and architectures for next-generation cognitive computing
A USB 3.0 High Speed Digital Readout System with Dynamic Frame Rate Processing for ISFET Lab-on-Chip Platforms
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power
Rapid prototyping of orthonormal wavelet transforms on FPGAs
High-sensitivity capacitive readout system for resonant submicrometer-scale cantilevers based sensors
Moore test using Gray code
An approach to automatic generation of wave digital structures from PDEs
A wide-band low-noise amplifier with double loop feedback
A low-power visual horizon estimation chip
Hardware Accelerated Marker-Based Accurate Rigid Object 6-DoF Pose Tracking System
Risk Early Warning of Power Systems With Partial State Observations Based on the Graph Attention Neural Network
Hybrid Multivariate Marginal Median Filters
A 4-Channel sEMG ASIC with Real-Time Muscle Fatigue Feature Extraction
Differential Power Analysis of a SHACAL-2 hardware implementation
Fast calculation of the coefficients of the generalized McClellan transform in 2-D FIR filter design
Automatic generation of neural networks for image processing
A 2 GHz CMOS even harmonic mixer for direct conversion receivers
Hardware prototype to emulate the dynamics of power system generators with field programmable analog arrays
Multiple-access Interference Constrained Source Extraction in Wireless Sensor Networks
New Riemannian metrics for improvement of convergence speed in ICA based learning algorithms
Corner proposals from HEVC bitstreams
Silicon Spin Qubit Control and Readout Circuits in 22nm FDSOI CMOS
Design and low-power implementation of an adaptive image rejection receiver
A 250MΩ Input Impedance a-IGZO Front-End for Biosignal Acquisition from Non-Contact Electrodes
A novel time domain method for computing phase noise in resonant oscillators
An empirical approach for digital currency forensics
Performance of Multi-user Chaos-based DS-CDMA System over Multipath Channel
A study of impact of wind power to power system stability using stochastic stability index
Delay uncertainty due to supply variations in static and dynamic full adders
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power
Hilbert transformers with a piecewise-polynomial-sinusoidal impulse response
Bandpass Delta-Sigma modulators synthesis with high loop delay
Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistance for power applications
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier
Multiple description motion coding algorithm for robust video transmission
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy
All-Carbon Spin Logic Sensor for RRAM Arrays
Theory of Information Network - Properties of Minimum Response Time Network
True random number generators as configware for mixed mode programmable systems on chip
Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects
A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture
Methods and needs for transcoding MPEG-4 fine granularity scalability video
Evaluation of multi-level buck converters for low-power applications