yusuke1997/dblp-id-title huggingface dataset:
A Spectral-Scanning Magnetic Resonance Imaging (MRI) Integrated System
A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition
A 98fJ/Bit Current-Starved-Ring-Oscillator-Based TRNG with High PVT Tolerance and Resilience to Frequency Injection Attack Up to 1V
Amorphous silicon logic circuits on flexible substrates
A 4.2pJ/Pixel 480 fps Stereo Vision Processor with Pixel Level Pipelined Architecture and Two-Path Aggregation Semi-Global Matching
A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver
Weightings in Incremental ADCs: A Tutorial Review
Notice of Violation of IEEE Publication PrinciplesA Single-Conversion SiGe BiCMOS Satellite TV LNB Front-End Using an Image Reject Mixer and a Calibrated Full-Rate VCO
A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure
Modeling and simulation of noise in analog/mixed-signal communication systems
A 151nW Second-Order Ternary Delta Modulator for ECG Slope Variation Measurement with Baseline Wandering Resilience
A 900-MHz, 0.8-μm CMOS low noise amplifier with 1.2-dB noise figure
Modeling ionizing radiation effects in solid state materials and CMOS devices
Low-power CMOS receivers for short reach optical communication
Quantum-dot cellular automata by electric and magnetic field coupling
A robust parasitic-insensitive successive approximation capacitance-to-digital converter
A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS
BIF - Battery interface standard for mobile devices
Embedded cooling technologies for densely integrated electronic systems
74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system
An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation
A vector DSP for imaging
APP processing for high performance MIMO systems [receiver symbol detector]
Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO
A new paradigm for very flexible SONET/SDH IP-modules
A Wideband ΔΣ Digital-RF Modulator With Self-Tuned RF Bandpass Reconstruction Filter
A K=3, 2 Mbps low power turbo decoder for 3 rd generation W-CDMA systems
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology
A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16
Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks
A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators
A Beamforming Receiver Using a Time-Modulated LO-Path Vector Modulator Achieving Amplitude and Phase Control with 0.2 dB RMS Gain Error and 1.4 Degree RMS Phase Error
A 12.2μW Interference Robust Wake-Up Receiver
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells
A 97.3 % -Peak-Efficiency Always-Dual-Path Buck-Boost Converter with Single-Mode Operation and Fast Transient Responses
Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS
A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression
A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations
Advances and challenges of computing with FPGAs
An Inverter-Based Amplifier Structure for Neural Signal Recording with an NEF of 1.28 and Area-per-Channel of 0.06mm 2
A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging
A Mechanically Flexible 32-by-32-Element Pitch-Matched Ultrasound Front-End Transceiver with Two-Stage Beamforming for 3D Imaging
A 77-GHz to 90-GHz bidirectional amplifier for half-duplex front-ends
A 65nm 3mA 0.14-m-Accuracy TDR Based Leak Detection SoC for District Heating Networks with I/C Calibration Technique
Portable and Scalable High Voltage Circuits for Automotive Applications in BiCMOS Processes
A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control
A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling
Mixed-signal, 275 °C instrumentation amplifier in bulk CMOS
A 1V 4 GHz-and-10 GHz transformer-based dual-band quadrature VCO in 0.18 μm CMOS
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits
A 100-Bit-Output Modeling Attack-Resistant SPN Strong PUF with Uniform and High-Randomness Response
On the exact design of RF oscillators
ESD design challenges
A yield optimization methodology for mixed-signal circuits
A/D converter fundamentals and trends
Sampling circuits that break the kT/C thermal noise limit
Generalized noise analysis of active mixers by simple linear periodic time-varying circuit model
A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability
A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration
Holisitic device exploration for 7nm node
A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC
Advanced wireless power and data transmission techniques for implantable medical devices
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR
A HomePlugAV SoC in 40nm CMOS technology
Two-stage physical synthesis for FPGAs
An energy conscious methodology for early design exploration of heterogeneous DSPs
A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE
An 8.5-11.5Gbps SONET transceiver with referenceless frequency acquisition
A 0.6V Highly Linear Switched-R-MOSFET-C Filter
A Fully-Integrated 0.11μm CMOS Digital Low-IF DVB-S2 Satellite TV Dual Tuner SOC
PLLs, VCOs, and dividers
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs
A front-end ASIC with high-voltage transmit switching and receive digitization for forward-looking intravascular ultrasound
Development of GaN Monolithic Integrated Circuits for Power Conversion
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking
High-frequency application of MOS compact models and their development for scalable RF model libraries
A DC-10GHz linear-in-dB attenuator in 0.13 μm CMOS technology
A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOS
SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads
A high gain CMOS operational amplifier with negative conductance gain enhancement
1.56 GHz On-chip Resonant Clocking in 130nm CMOS
A low-power single-chip MPEG-2 CODEC LSI
A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters
Supply noise induced jitter modeling and optimization for high-speed interfaces
Fully-monolithic, 600°C differential amplifiers in 6H-SiC JFET IC technology
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression
A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's
CMOS RF design-the low power dimension
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique
A 45-ratio recursively sliced series-parallel switched-capacitor DC-DC converter achieving 86% efficiency
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS
Session 2 - Statistical modeling
A 134-μW 50-MHz Quasi-Dynamic Comparator with A Novel Clock-Free Regenerative Latch
A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel
Circuit Design Techniques for High-Voltage Comparators and Amplifiers
An 8Mb 1T1C ferroelectric memory with zero cancellation and micro-granularity redundancy
An improved wideband PLL with adaptive frequency response that tracks the reference
A 26-32 GHz Dual-Polarization Receiver with Autonomous Polarization Alignment for Fast-Response Mm-Wave MIMO Links in Highly Dynamic Mobile Environments
300-GHz CMOS QPSK transmitter for 30-Gbps dielectric waveguide communication
131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks
Cell Broadband Engine Processor Design Methodology
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme
A surface potential model for predicting substrate noise coupling in integrated circuits
Dynamically reconfigurable NoC for reconfigurable MPSoC
Smart universal control IC for high loaded factor resonant converters
A low-voltage low-power sigma-delta modulator with improved performance in overload condition
A 1 V 900 MHz image-reject downconverter in 0.5 μm CMOS
Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits
A ΔΣ DAC with reduced activity data weighted averaging and anti-jitter digital filter
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors
A novel low-power FPGA routing switch
IEEE Custom Integrated Circuits Conference, CICC 2024, Denver, CO, USA, April 21-24, 2024
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection
A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule
Integration of self assembly for semiconductor microelectronics
Intelligent Neural Interfaces: An Emerging Era in Neurotechnology
Analog Techniques
Equalization algorithms in Millimeter wave communication systems
Mixer-First Extremely Wideband 43-97 GHz RX Frontend with Broadband Quadrature Input Matching and Current Mode Transformer-Based Image Rejection for Massive MIMO Applications
High-performance millimeter-wave beamformers with built-in self-test
A 60GHz Phased Array in CMOS
Session 20 - Manufacturing beyond moore's law
Millimeter-wave full-duplex wireless: Applications, antenna interfaces and systems
Challenges in the design of cognitive radios 1
A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS
A 0.6V 2.2mW 58-to-73GHz divide-by-4 injection-locked frequency divider
64-bit prefix adders: Power-efficient topologies and design solutions
A 0.7cm 2 3.5GHz, -31 dBm Sensitivity Batteryless 5G Energy Harvester Backscattering Chip for Asset Identification in IoT-Enabled Warehouses
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4 th order CT-ΔΣ modulator with 2 nd order noise-shaping and pipelined SAR-VCO based quantizer
Modelling and Measurements on minimum-width transmission-lines from 10-67GHz in 65nm CMOS
A 1 Watt 1-5 GHz Class B push-pull Si/SiGe HBT power amplifier
An integrated 10 GHz quadrature LC-VCO in SiGe: C BiCMOS - technology for low-jitter applications
A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC
Opportunities and challenges in asymmetric device implementation [CMOS device scaling]
5-GHz in-phase coupled oscillators with 39% tuning range
Substrate noise immune design of an LC-tank VCO using sensitivity functions
An Up to 10MHz 6.8% Minimum Duty Ratio GaN Driver with Dual-MOS-Switches Bootstrap and Adaptive Short-Pulse Based High-CMTI Level Shifter Achieving 6.05% Efficiency Improvement
A 15 GHz, 1.8V, variable-gain, modified Cherry-Hooper amplifier
A platform-based highly parallel digital signal processor
A 60mW 1.15mA/channel Class-G Stereo Headphone Driver with 111dB DR and 120dB PSRR
Predictive Modeling of the NBTI Effect for Reliable Design
Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs
An ultra-low power 900 MHz RF transceiver for wireless sensor networks
A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation
A 20 μ W, 0.05mm 2 Duty-Cycled Resistor and Frequency-Locked-Loop-based Wheatstone Bridge Interface for Low Resistance Sensing Systems
A tri-stack buck converter with gate coupling control (GCC) and quasi adaptive dead time control (QADTC)
Analog techniques II
ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies
Recent Advances in III-V Electronics
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates
A Full-Band processor for reduction of RF mixer LO harmonic images
Frequency-Based Measurement of Mismatches Between Small Capacitors
Digital techniques for improved ΔΣ data conversion
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS
IEEE Custom Integrated Circuits Conference, CICC 2022, Newport Beach, CA, USA, April 24-27, 2022
A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines
Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS
A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder
AMD SOC power management: Improving performance/watt using run-time feedback
A 10Gb/s Equalizer with Decision Feedback for High Speed Serial Links
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver
Design of a 3.24μW, 39nV/√Hz chopper amplifier with 5.5Hz noise corner frequency for invasive neural signal acquisition
An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS
A 1 V 0.9 dB NF low noise amplifier for 5-6 GHz WLAN in 0.18 μm CMOS
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking
Design and manufacturing enablement for three-dimensional (3D) integrated circuits (ICs)
An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling
Copper interconnect technology for the 32 nm node and beyond
IEEE Custom Integrated Circuits Conference, CICC 2021, Austin, TX, USA, April 25-30, 2021
A scalable digitalized buffer for gigabit I/O
A highly integrated quad band low EVM polar modulation transmitter for GSM/EDGE applications
A 24-Channel Neurostimulator IC with One-Shot Impedance-Adaptive Channel-Specific Charge Balancing
A design environment for high throughput, low power dedicated signal processing systems
Esd Challenges in Advanced Finfet and Gaa Nanowire cmos Technologies: Designing Diode Based ESD Protection in Advanced State of the Art Technologies
A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy
High-performance analog/mixed-signal characterization techniques
Coupled Inductors for Fast-Response High-Density Power Delivery: Discrete and Integrated
Wireless Power Transfer at Distance
3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry
Micromachined high-Q inductors in 0.18 μm Cu interconnect low-K CMOS
Session 13 - Security circuits and systems
A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability
A comparison of electrical and optical clock networks in nanometer technologies
ANACONDA: robust synthesis of analog circuits via stochastic pattern search
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback
Zero-Crossing-Based Bio-Engineered Sensor
A 1.8-V 3-MS/s 13-bit ΔΣ A/D converter with pseudo data-weighted-averaging in 0.18-μm digital CMOS
Compact modeling of LDMOS working in the third quadrant
Advanced SOI CMOS transistor technologies for high-performance microprocessor applications
Welcome and opening remarks
Optimization and modeling of resonant clocking inductors for the POWER8 TM microprocessor
Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm
Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM
V-band varactor-less interpolative-phase-tuning oscillators with multiphase outputs
A 10-bit, 3 V, 100 MS/s pipelined ADC
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal
A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS
Low-noise CMOS integrated sensing electronics for capacitive MEMS strain sensors
Design considerations of HBM stacked DRAM and the memory architecture extension
Phase Change Memory: Scaling and applications
Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPU
A 2-V 23-μA 5.3-ppm/°C 4th-order curvature-compensated CMOS bandgap reference
Energy efficient SoC design
A VCO-based current-to-digital converter for sensor applications
Holistic Co-Design of Electronics and Photonics for High-Speed Optical Interconnects in SiP and CMOS Platforms
A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOS
A 56 Gb/s 6 mW 300 um 2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS
Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation
A high gain 107 GHz amplifier in 130 nm CMOS
Fixed- and variable-length ring oscillators for variability characterization in 45nm CMOS
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol
Nonlinear behavioral modeling and phase noise evaluation in phase locked loops
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks
High-Q Timing and Inertial Measurement Unit Chip (TIMU) with 3D Wafer-Level Packaging
A true single SoC for UHF mobile RFID reader
A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop
A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems
A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS
An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS
Highly integrated and tunable RF front-ends for reconfigurable multi-band transceivers
An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement
Multiphase RF techniques in CMOS: Applied to beam-forming and full duplex receivers: CICC 2015 educational session
A system-on-chip for pressure-sensitive fabric
A 65nm Resonant Electro-Quasistatic 5-240uW Human Whole-Body Powering and 2.19uW Communication SoC with Automatic Maximum Resonant Power Tracking
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface
An Ultra-Compact Wideband-Linearized Power Amplifier Achieving 0.24° AM-PM Distortion and Supporting 64-/256-/1024-/4096-QAM
A continuous-time input pipeline ADC with inherent anti-alias filtering
Power minimization by simultaneous dual-V th assignment and gate-sizing
A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming
Where is the Inductor: A Review and Comparison of the Hybrid DC-DC Buck Topologies
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A
Area efficient phase calibration of a 1.6 GHz multiphase DLL
A 0.84pJ/cycle Wheatstone Bridge Based CMOS RC Oscillator with Reconfigurable Frequencies
A 25Gb/s laser diode driver with mutually coupled peaking inductors for optical interconnects
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers
An 8-user UMTS channel unit processor for 3GPP base station applications
Modeling the response of Bang-Bang digital PLLs to phase error perturbations
CMOS electronics probe inside a cellular network - Invited review paper
A wireless sensor node for condition monitoring powered by a vibration energy harvester
A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection
A DRAM module generator with an expandable cell array scheme
ASIL-D and AEC-Q100 Grade 0 Compliant Automotive RC Oscillator with Farey Sequence-based Calibration
A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOS
A nonlinear programming and local improvement method for standard cell placement
A 3D mixed-mode ESD protection circuit simulation-design methodology
Test strategies for adaptive equalizers
A CMOS BD-BCI Incorporating Stimulation with Dual-Mode Charge Balancing and Time-Domain Pipelined Recording
S-TFT: an analytical model of polysilicon thin-film transistors for circuit simulation
Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz
A 99-mm 2 , 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system
Architecture and implementation of a bitserial sorter for weighted median filtering
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels
Background ADC calibration in digital domain
A CMOS image sensor with on-chip motion detection and object localization
Design and manufacturability aspect of SOI CMOS RFICs
A 40.68MHz Dual-Output Wireless Power Transfer System Achieving 149.7mW Maximum Power and 90.3%/51.2% RX/E2E Efficiency with 8mm-Diameter RX Coil
A CMOS Bluetooth radio transceiver using a sliding-IF architecture
A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization
An anti-blocker structure MOSFET-C filter for a direct conversion receiver
A 2GHz quadrature hybrid implemented in CMOS technology
Analysis and optimization of IIP2 in CMOS direct down-converters
Integration of CMP Modeling in RC Extraction and Timing Flow
A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter
A switched capacitor regulated charge pump power supply
Device trends and implications on circuit design in advanced CMOS technologies
CMOS sensor for dual fluorescence intensity and lifetime sensing using multicycle charge modulation
Auto-referenced on-die power supply noise measurement circuit
A 13nV/✓Hz 4.5μW Chopper Instrumentation Amplifier with Robust Ripple Reduction and Input Impedance Boosting Techniques
A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO
An ultra-low power injection locked transmitter for wireless sensor networks
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme
Design considerations of recent advanced low-voltage low-temperature-coefficient CMOS bandgap voltage reference
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors
A 0.04-mm 2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration
Non-load-balance-dependent high efficiency single-inductor multiple-output (SIMO) DC-DC converters
System-level noise filtering and linearization
A 1-TFLOPS/W, 28-nm Deep Neural Network Accelerator Featuring Online Compression and Decompression and BF16 Digital In-Memory-Computing Hardware
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow
Proximity communication
A 24GS/s 5-b ADC with closed-loop THA in 0.18μm SiGe BiCMOS
A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS