yusuke1997/dblp-id-title huggingface dataset:
10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application
Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform
Statistical design attribute identification for FinFET outlier and Silicon-to-SPICE gap
ITUS: A Secure RISC-V System-on-Chip
Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon
An RRAM-based Neural Radiance Field Processor
Adversarial and Backdoor Threats in Autonomous-Vehicle and Embodied-AI Systems
Synthesis of SystemC models from SDF Ptolemy descriptions
Architectural Exploration on Racetrack Memories
Improved decoding algorithm for high reliable reed muller coding
FPGA-based vector processor for algebraic equation solvers
On-chip testing of embedded silicon transducers
System-on-System (SoS) architecture for 3-D secure imaging
A low-cost SOC debug platform based on on-chip test architectures
Plenary speaker
A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function
Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing
31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018
Low-voltage zero quiescent current PFM boost converter for portable devices
Energy-Aware Workload Allocation for Distributed Deep Neural Networks in Edge-Cloud Continuum
Opening keynote: Crashing drones and hijacked cameras: Cybertrust meets cyberphysical
MCLB: Dynamic Load Balancing and Implications on GPU Memory Controllers
A robust medium access mechanism for millimeter-wave Wireless Network-on-Chip architecture
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration
An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA
A low-power all-digital phase modulator pair for LINC transmitters
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI
A 1V CMOS low-noise amplifier with inductive resonated for 3.1-10.6GHz UWB wireless receiver
Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology
Design of a sensor node crypto processor for IEEE 802.15.4 applications
DVFS-enabled sustainable wireless NoC architecture
Lightweight Error-Correction Code Encoders in Superconducting Electronic Systems
Hardware-Aware Network Adaptation using Width and Depth Shrinking including Convolutional and Fully Connected Layer Merging
A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip
Intellectual property protection and security of SoCs - An embedded tutorial
Multilevel MPSOC simulation using an MDE approach
Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core
A fully digital power supply noise thermometer
Plenary I: The Internet of important things
A 4K Vision Computing Platform with Convolutional Neural Network Engine on FPGA
TSV sharing through multiplexing for TSV count minimization in high-level synthesis
Design of a low power multistandard transceiver chain based on current-reuse VCO
Logic-Embedded Flip-Flop Adapting Scan-Controlled Semidynamic and Clocked Domino Structures
Lightweight energy prediction framework for solar-powered wireless sensor networks
A novel flow fluidity meter for BiNoC bandwidth resource allocation
Energy-Based Analog Neural Network Framework
Securing Microservices Against Password Guess Attacks using Hardware Performance Counters
OPAMP-Free Ferroelectric Capacitive Computing-in-Memory Accelerator for Energy-Efficient Binary Neural Networks
Multi-Pheromone ACO-based routing in Network-on-Chip system inspired by economic phenomenon
Design of a neural recording amplifier with tunable pseudo resistors
Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology
Keynote speaker: "The Internet of Every-Thing: EDA perspectives"
Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch
A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2
All digital time-to-digital converter using single delay-locked loop
Silicon Debug and DFT for SOC IP
Scalable DU Architecture for IoT massive connection
An Efficient Hardware Design for Fast Implementation of HQC
240 GHz Line-of-Sight MIMO Link Demonstration
Luncheon Speaker: "Introduction to SoC testing"
SoC Design Space Exploration through Automated IP Selection from SystemC IP Library
Performance Evaluation of Flan-T5 in CGLA based Accelerators
A Dual-Function Filter for 5.25GHZ Narrowband and 3.6GHZ-10.1GHZ Ultrawideband Systems
Floorplanning challenges in early chip planning
Designing a SoC to control the next-generation space exploration flight science instruments
Content-aware line-based power modeling methodology for image signal processor
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design
Lithography hotspot detection: From shallow to deep learning
Hybrid multi-swarm optimization based NoC synthesis
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory
A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator
A globally-interconnected modular CMP system with communication on the fly
Low-power high-performance FinFET sequential circuits
Pixel-Parallel SPIHT for frame memory compression
Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers
Application specific component-service-aware trace generation on Android-QEMU
A multiplication reduction technique with near-zero approximation for embedded learning in IoT devices
An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations
An On-Chip Measurement Circuit for Calibration by Combination Selection
Noise Analysis of CMOS Ring Oscillator-based Capacitance Measurement for Lab-on-Chip Application
A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath
N 2 OC: Neural-Network-on-Chip Architecture
DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations
65NM sub-threshold 11T-SRAM for ultra low voltage applications
Area efficient delay-insensitive and differential current sensing on-chip interconnect
A 12 bit split-array switched capacitor power amplifier in 130nm CMOS
A new level shifter in ultra deep sub-micron for low to wide range voltage applications
Improving Error Resilience for Compressed Test Sets by Don't Care Assignment
Constraint-based Code mapping for heterogeneous Chip multiprocessors
Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer
IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011
A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique
Crosstalk-aware Energy Reduction in NoC Communication Fabrics
A merged MuGFET and planar SOI process
Low-Power ECG Anomaly Detector Using an Area-Efficient Artificial Neural Network
Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function
Reliability for IoT and automotive markets
A low complexity UWB PHY baseband transceiver for IEEE 802.15.6 WBAN
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G
Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems
Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits
An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications
Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA
Performance optimization and power efficiency in 3D IC with buffer insertion scheme
An Architecture for On-Chip Face Recognition in a Compressive Image Sensor
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform
A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillators
Mixed-VTH (MVT) CMOS circuit design for low power cell libraries
A multi-level simulation approach in a Simulink-based design tool for FPGAs
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address
A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector
Plenary speaker: "Power-centric timing optimization for low power CPU hardening"
Hybrid Voltage and Current References Based on Double ZTC Points
Software-defined Temporal Decoupling in Virtual Platforms
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs
CATBR-Congestion Aware Traffic Bridging Routing among hierarchical networks-on-chip
A novel low power, variable resolution pipelined ADC
Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup
A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist
COSSEA: Context-based SoC Security Enforcement Architecture
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs
High-level TSV resource sharing and optimization for TSV based 3D IC designs
Method for improving performance in online routing of reconfigurable nano architectures
An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor
An Output-Capacitorless Adaptively Biased Low-Dropout Regulator with Maximum 132-MHz UGF and Without Minimum Loading Requirement
Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
Towards platform level power management in mobile systems
VLSI design and analysis of a critical-band processor for speech recognition
Towards Automating a Software-Centered Development Process that considers Timing Properties
A Trace Based Framework for Validation of SoC Designs with GALS Systems
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost
I/O Constraints Optimization using Machine Learning
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC
A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks
A low jitter delay-locked loop with a realignment duty cycle corrector
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption
A 10-bit Area-efficient Source Driver for Printed OLED Display
Fairness-oriented switch allocation for networks-on-chip
A Comparative Analysis of Security Patterns for Enhancing Security in Safety-Critical Systems
Error-latency Trade-off for Asynchronous Stochastic Computing with ΣΔ Streams for the IoT
The Case for SoC in Future Radio Astronomy
Programmable all-digital adaptive deskewing and phase shifting
Efficient runtime performance monitoring of FPGA-based applications
A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-nm CMOS
Electromyograph data acquisition and application using Cypress Programmable System on Chip
Light-Weight Resilient Flip-flop for Error Detection and Same-cycle Correction in Pipelined Designs
Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis
RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC
Novel lightweight FF-APUF design for FPGA
Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems - Optimization of technology - Architecture - Design
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation
Plenary speaker: "Visions of future SoC design: Why heterogeneous architectures and power matter"
Centralized Priority Management Allocation for Network-on-Chip Router
An efficient power reduction technique for flash ADC
Custom Algorithm-based Fault Tolerance for Attention Layers in Transformers
Architecture for Low Power Large Vocabulary Speech Recognition
Low-power on-chip bus architecture using dynamic relative delays
Online thermal-aware scheduling for multiple clock domain CMPs
Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness
Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies
C 2 IM: A Compact Computing-In-Memory Unit of 10 Transistors with Standard 6T SRAM
A new data acquisition design for breast cancer detection system
Technology trends and implications on SoC design
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder
GELU-MSDF: A Hardware Accelerator for Transformer's GELU Activation Function Using Most Significant Digit First Computation
A Lossless Astronomical Data Compression Scheme with FPGA Acceleration
Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies
A register-transfer level testability analyzer
SIMAX: a SIMD-Based Many-Core Accelerator for Matrix-Vector Multiplication for Transformers
Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory
A novel architecture for discrete chaotic signal generators
32nd IEEE International System-on-Chip Conference, SOCC 2019, Singapore, September 3-6, 2019
An analytical, dynamic, power-performance router model for run-time NoC optimizations
Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below
High throughput and low power FIR filtering IP cores
Generic integer linear programming formulation for 3D IC partitioning
High speed and low power transceiver design with CNFET and CNT bundle interconnect
Thermal modelling of 3D multicore systems in a flip-chip package
27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration
An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications
FPGA Implementation of Addition-based CORDIC-SNN With Izhikevich Neurons
Novel Pulse Detection System Using Differentiation: Optical Experimental Results
A Stochastic Coding Method of EEG Signals for Sleep Stage Classification
A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS
Secure Speculative Core
Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique
Analysis and design of high performance wireless power delivery using on-chip octagonal inductor in 65-nm CMOS
W3A: Design of reconfigurable and multiprocessor systems
A low complexity, low power, programmable QRS detector based on wavelet transform for Implantable Pacemaker IC
Early selection of system implementation choice among SoC, SoP and 3-D Integration
High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow
CoolPression - a hybrid significance compression technique for reducing energy in caches
Plenary speaker: "SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH"
Standards-compliant IP-based ASIC and SoC design
A 100 KS/s 8-10 bit resolution-reconfigurable SAR ADC for bioelectronics application
An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions
A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator
SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC
An improved delay-hopped transmitted-reference ultra wideband architecture
A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier
A high-level compilation toolchain for heterogeneous systems
Clocked semi-floating-gate ultra low-voltage inverting current mirror
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction
Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding
A power-aware scalable pipelined Booth multiplier
A point of care electrochemical impedance spectroscopy device
Cascoded flipped voltage follower based output-capacitorless low-dropout regulator for SoCs
FPGA-based object detection processor with HOG feature and SVM classifier
Quantum Key Distribution Post-processing: A Heterogeneous Computing Perspective
Cyclic QFP Network with Controllable Bistability for Scalable Superconducting Spin Systems
Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC
2nm GAA Cell Architecture Exploration Driven by Automated Standard Cell Layout Generator for Design-Technology Co-Optimization
A Trace-Driven Validation Methodology for Multi-Processor SOCS
A -30 dBm sensitive ultra low power RF energy harvesting front end with an efficiency of 70.1% at -22 dBm
Analysis and design of low-power multi-threshold MCML
A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum Algorithms
A multi-segment clocking scheme to reduce on-chip EMI
A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow
Workload Clustering for Increasing Energy Savings on Embedded MPSoCs
A unified power measurement and management platform for pipelined MPSoC executions
Tutorial: RAM-based Circuits and Architectures for Multimedia and Signal Processing SOCs
Benefits and costs of prediction based DVFS for NoCs at router level
2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007
W2B: Design methodologies for SoCs
3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling
A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects
Energy efficient computation with self-adaptive single-ended body bias
A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays
A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier
Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation
Battery-efficient task execution on portable reconfigurable computing
RV 2 A: Design and Implementation of an Energy-Efficient RISC-V × V Accelerator to exploit Data parallelism at the Edge
Speed control for a hardware based H.264/AVC encoder
A random access analog memory with master-slave structure for implementing hexadecimal logic
Decoupling capacitors for power distribution systems with multiple power supply voltages
Reconfigurable Switched-Capacitor ΔΣ Modulator Topology Design
High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS
Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs
A 0.13μm 1Gb/s/channel store-and-forward network on-chip
H.264 Decoder Implementation on a Dynamically Reconfigurable Instruction Cell Based Architecture
Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images
Beyond Total Locking: Demonstrating and Measuring Mutual Influence on a RO-Based True Random Number Generator on an FPGA
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity
Cardinality Constrained Portfolio Optimization on an Ising Machine
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application
Multifractal on-chip traffic generation under TLM
Virtual white board: Leveraging investments in interface based design and executable specification
Efficient generation of analog circuit models for accelerated mixed-signal simulation
Modeling Attacks Resilient Multiple PUF-CPRNG Architecture Design Methodology
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer
LC-Physical Unclonable Function in Wireless 3D IC for Securing Internet of Things Devices
Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments
A 1.2V wide-band reconfigurable mixer for wireless application in 65nm CMOS technology
Improved memory strategy for logmap turbo decoders
Extended dynamic voltage scaling for low power design
System power analysis with DVFS on ESL virtual platform
A multi-channel frequency detection and monitoring system
ZeKi: A Zero-Knowledge Dynamic Logic Locking Implementation with Resilience to Multiple Attacks
A neural rehabilitation chip with neural recording, peak detection, spike rate counter, and biphasic neural stimulator
Light field data processor design for depth estimation using confidence-assisted disparities
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs
Reinforcement Learning-based Power Management Architecture for Optimal DVFS in SoCs
Thermal-aware mapping and placement for 3-D NoC designs
Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs
Native-conflict-avoiding track routing for double patterning technology
An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors
Tutorial 4B: ADC design - from system architecture to transistor level design
"Unicorns and centaurs: Architecting SOCs for software defined networking"
A Mimo Receiver SOC for CDMA Applications
A multimedia content generation methodology in support to SOC decoder development and validation
Simultaneous bidirectional PAM-4 link with built-in self-test
SRAM word-oriented redundancy methodology using built in self-repair
Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore
An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits
ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation
A floorplan-aware interactive tool flow for NoC design and synthesis
An ultra-low power voltage-to-time converter (VTC) circuit for low power and low speed applications
Advanced clock schemes with dead time techniques for high voltage charge pumps
New quantization error assessment methodology for fixed-point pipeline FFT processor design
Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications
Sub-10 µW CMOS wake-up receiver IP for green SoC designs
Investigation of diode triggered silicon control rectifier turn-on time during ESD events
Mutual inductance modeling for multiple RLC interconnects with application to shield insertion
Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation
SimST: Simulation Framework for Energy-Dataflow Co-Optimization in Spike-Driven Transformer
A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 µm CMOS
I Models and Tools for the Dynamic Reconfiguration of FPGAs
H.264/AVC decoder SoC towards the low cost mobile video player
Machine Learning Based Parameter Tuning for Performance and Power optimization of Multisource Clock Tree Synthesis
Novel ultra low voltage mobile compatible RF MEMS switch for reconfigurable microstrip antenna
Assessing the Circuit Requirements for a Real-Time Spectrum Analyzer on 65-nm CMOS Technology
A 61 μA/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things
Modeling the Impact of Process Variation on Critical Charge Distribution
SoC Scan-Chain verification utilizing FPGA-based emulation platform and SCE-MI interface
An automated control code generation approach for the SegBus platform
A 45nm dual-port SRAM with write and read capability enhancement at low voltage
Analysis of the Sub-µA Fully Integrated NMOS LDO for Backscattering System