yusuke1997/dblp-id-title huggingface dataset:
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking
An SOI-Based 7.5µm-Thick 0.15x0.15mm2 RFID Chip
A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems
HOOP: A Scalable Hybrid DC-DC Converter Ring for High-Performance Computing
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control
33.3 MiBMI: A 192/512-Channel 2.46mm² Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes
36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control
12.4 1.4Gsearch/s 2Mb/mm 2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%
Ultra-low-power analog design
A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI
A universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm 2 radio in 40nm CMOS
Early detection of oxide breakdown through in situ degradation sensing
A 0.12mm 2 Wien-Bridge Temperature Sensor with 0.1°C (3σ) Inaccuracy from -40°C to 180°C
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor
Session 5 Overview: Analog Interfaces Analog Subcommittee
A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference
4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies
A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique
An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies
A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application
A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities
2.7 BayesBB: A 9.6Gbps 1.61ms Configurable All-MessagePassing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS
A 10 th generation 16-core SPARC64 processor for mission-critical UNIX server
A self-duty-cycled and synchronized UWB receiver SoC consuming 375pJ/b for -76.5dBm sensitivity at 2Mb/s
An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvement
11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory
Image Sensors
The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end server processor
An on-chip delay- and skew-insensitive multicycle communication scheme
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee
F3: Circuits and architectures for wireless sensing, radar and imaging
A 2.7nJ/b multi-standard 2.3/2.4GHz polar transmitter for wireless sensor networks
16.2 A Keccak-based wireless authentication tag with per-query key update and power-glitch attack countermeasures
Session 5 overview: RF techniques
An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension
22.5 A 93%-power-efficiency photovoltaic energy harvester with irradiance-aware auto-reconfigurable MPPT scheme achieving >95% MPPT efficiency across 650µW to 1W and 2.9ms FOCV MPPT transient time
A Li-ion-Battery-Input 1-to-6V-Output Bootstrap-Free Hybrid Buck-or-Boost Converter Without RHP Zero Achieving 97.3% Peak Efficiency 6μs Recovery Time and 1.13μs/V DVS Rate
A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS
19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter
11.3 A 160×120-pixel analog-counting single-photon imager with Sub-ns time-gating and self-referenced column-parallel A/D conversion for fluorescence lifetime imaging
Dynamic frequency-switching clock system on a quad-core Itanium® processor
A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing
A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories
26.1 A 4.5mm 2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices
A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
A 90nm CMOS SoC UWB pulse radar for respiratory rate monitoring
A 160×128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter
A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS
Load-Independent Control of Switching DC-DC Converters with Freewheeling Current Feedback
A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth
A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation
20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS
17.6 Rapid and energy-efficient molecular sensing using dual mm-Wave combs in 65nm CMOS: A 220-to-320GHz spectrometer with 5.2mW radiated power and 14.6-to-19.5dB noise figure
27.2 A Voltage-Biased CMOS Hall Sensor with 1.0sµT(3σ) Offset and a 60nT/√Hz Noise-Floor
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer
20.6 LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-Level kNN Acceleration
A 120μW MICS/ISM-band FSK receiver with a 44μW low-power mode based on injection-locking and 9x frequency multiplication
K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL
5.4 A Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor with a Self-Calibrated Inaccuracy of ±0.25° C(3 Σ) from -55°C to 125°C
A mobile-display-driver IC embedding a capacitive-touch-screen controller system
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS
3.2 A 0.0088mm 2 Resistor-Based Temperature Sensor Achieving 92fJ·K 2 FoM in 65nm CMOS
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm 2 Inter-Chiplet Interconnects and 156mW/mm 2 @ 82%-Peak-Efficiency DC-DC Converters
A Polynomial-Predistortion Transmitter for WCDMA
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family
Session 16 overview: Gigahertz data converters
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD
26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology
10.8 A Buck converter with 240pW quiescent power, 92% peak efficiency and a 2×10 6 dynamic range
An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery
A 10.8mW body-channel-communication/MICS dual-band transceiver for a unified body-sensor-network controller
17.10 0.65V-input-voltage 0.6V-output-voltage 30ppm/°C low-dropout regulator with embedded voltage reference for low-power biomedical systems
A 1.8Gpulses/s UWB Transmitter in 90nm CMOS
5.10 A 1A LDO regulator driven by a 0.0013mm 2 Class-D controller
A 256×256 CMOS image sensor with ΔΣ-based single-shot compressed sensing
A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists
20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture
A 16 Mfps 165kpixel backside-illuminated CCD
Session 23 overview: LO generation: RF subcommittee
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications
A 32×32 Pixel 0.46-to-0.75THz Light-Field Camera SoC in 0.13μ m CMOS
9.5 A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor DAC, Non-Overlap DEM and Continuous-Time Quantizer
A Monolithic GaN Direct 48V/1V AHB Switching Power IC with Auto-Lock Auto-Break Level Shifting, Self-Bootstrapped Hybrid Gate Driving, and On-Die Temperature Sensing
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV
Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell Imaging
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS
A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers
A 100Hz 5nT/Hz Low-Pass ΔΣ Servo-Controlled Microfluxgate Magnetometer Using Pulsed Excitation
26.3 Noise Immunity in Capacitive Sensing: Single-Ended AFE Design with Common-Current Subtraction for Mutual- and Self-Capacitance Sensing in 390pF Load
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes
Session 15 overview: Oversampling data converters
Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design
A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applications
Beamforming techniques and RF transceiver design
2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
A silicon 60GHz receiver and transmitter chipset for broadband communications
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS
4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiode
A 59GHz push-push VCO with 13.9GHz tuning range using loop-ground transmission line for a full-band 60GHz transceiver
A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications
A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolution
33.4 An 8A 998A/inch3 90.2% Peak Efficiency 48V-to-1V DC-DC Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking
A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications
A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications
Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System
A 100mW Dual-Band CMOS Mobile-TV Tuner IC for T-DMB/DAB and ISDB-T
11Gb/s monolithically integrated silicon optical receiver for 850nm wavelength
18.3 A single-port duplex RF front-end for X-band single-antenna FMCW radar in 65nm CMOS
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements
A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance
Session 16 overview: Advanced optical and wireline techniques: Wireline subcommittee
2.6 A 190.5GHz mode-switching VCO with 20.7% continuous tuning range and maximum power of -2.1dBm in 0.13µm BiCMOS
8Gb 3D DDR3 DRAM using through-silicon-via technology
2.4 A 25Gb/s 5.8mW CMOS equalizer
A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT
A high-stability emulated absolute current hysteretic control single-inductor 5-output switching DC-DC converter with energy sharing and balancing
A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS
Session 5 overview: Image sensors: IMMD subcommittee
A Fully Integrated 2.4GHz IEEE 802.15.4 Compliant Transceiver for ZigBee Applications
A Bidirectional RF-Combining 60GHz Phased-Array Front-End
MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers
A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI
A Monolithic 3: 1 Resonant Dickson Converter with Variable Regulation and Magnetic-Based Zero-Current Detection and Autotuning
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction
A 1024×8 700ps time-gated SPAD line sensor for laser raman spectroscopy and LIBS in space and rover-based planetary exploration
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process
7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers
A 2.88Gb/s digital hopping UWB transceiver
17.2 A 0.0013mm 2 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin
A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS
A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip
Session 13 overview: High-performance embedded SRAM: Memory subcommittee
Low-Power mm-Wave Components up to 104GHz in 90nm CMOS
A 151mm 2 64Gb MLC NAND flash memory in 24nm CMOS technology
A software-defined radio receiver architecture robust to out-of-band interference
A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6pA input current and offset
24.2 A Reconfigurable Series/Parallel Quadrature-Coupler-Based Doherty PA in CMOS SOI with VSWR Resilient Linearity and Back-Off PAE for 5G MIMO Arrays
A 96Gb/s-Throughput Transceiver for Short-Distance Parallel Optical Links
17.3 A 60GHz on-chip linear radiator with single-element 27.9dBm Psat and 33.1dBm peak EIRP using multifeed antenna for direct on-antenna power combining
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture
A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique
16.2 RNGD: A 5nm Tensor-Contraction Processor for Power-Efficient Inference on Large Language Models
A Bias-Flip Rectifier with a Duty-Cycle-Based MPPT Algorithm for Piezoelectric Energy Harvesting with 98% Peak MPPT Efficiency and 738% Energy-Extraction Enhancement
11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations
A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS
True Random Number Generator with a Metastability-Based Quality Control
1.3 Future Scaling: Where Systems and Technology Meet
A 98.6 % -Peak-Efficiency 1.47A/mm2-Current-Density Buck-Boost Converter with Always Reduced Conduction Loss
A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications
5.6 A 420µW 100GHz-GBW CMOS Programmable-Gain Amplifier leveraging the cross-coupled pair regeneration
12.9 A 1.55×0.85mm 2 3ppm 1.0μA 32.768kHz MEMS-based oscillator
Silicon-resonator-based, 3µA real-time clock with ±5ppm frequency accuracy
A Blocker-Vigilant Channel-Select Filter with Adaptive IIP3 and Power Dissipation
A 10b 500MHz 55mW CMOS ADC
A 92dB-DR 13mW ΔΣ Modulator for Spaceborn Fluxgate Sensors
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI
3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities
23.10 HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity
A Dual-Line Optical Transient Sensor with On-Chip Precision Time-Stamp Generation
"Architecting the future through heterogeneous computing"
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise
A 3W 55% PAE CMOS PA with Closed-Loop 20: 1 VSWR Protection
An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transfer
POWER7 TM local clocking and clocked storage elements
Session 24 overview: Ultra-efficient computing: Application-inspired and analog-assisted digital
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS
A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDs
Gate Work Function Engineering for Nanotube-Based Circuits
A 64Mb MRAM with clamped-reference and adequate-reference schemes
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application
An Integrated Thermal Actuation/Sensing Array with Stacked Oscillators for Efficient and Localized Heating of Magnetic Nanoparticles with Sub-Millimeter Spatial Resolution
A Condition-Adaptive △f 3 -EMI Control GaN Switching Regulator With Modulation Frequency Envelope Tracking For Full-Spectrum Automotive CISPR 25 Compliance
A 0.5V 9.26μW 15.28mΩ/√Hz Bio-Impedance Sensor IC With 0.55° Overall Phase Error
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS
Single-ended transceiver design techniques for 5.33Gb/s graphics applications
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
Digital Circuit Innovations
An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications
A digitally modulated 2.4GHz WLAN transmitter with integrated phase path and dynamic load modulation in 65nm CMOS
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS
An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC
A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET
A 0.032mm 2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range
17.7 A 1.89nW/0.15V self-charged XO for real-time clock generation
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
Personal inertial navigation system employing MEMS wearable ground reaction sensor array and interface ASIC achieving a position accuracy of 5.5m over 3km walking distance without GPS
ES2: "batteries not included." - How little is enough for real energy autonomy?
A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End
A 5A 94.5% Peak Efficiency 9~16V-to-1V Dual-Path Series-Capacitor Converter with Full Duty Range and Low V.A Metric
A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS
A Fast-Readout Mismatch-Insensitive Magnetoresistive Biosensor Front-End Achieving Sub-ppm Sensitivity
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks
21.4 A -108dBc THD+N, 2.3mW Class-H Headphone Amplifier with Power-Aware SIMO Supply Modulator
Session 24 Overview: Advanced Embedded Memories Memory Subcommittee
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS
SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0
A Wireless Power Transfer System with Up-to-20% Light- Load Efficiency Enhancement and Instant Dynamic Response by Fully Integrated Wireless Hysteretic Control for Bioimplants
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
EE2: Do we need to downscale our radios below 20nm?
An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating
A family of 45nm IA processors
A quad-band class-39 RF CMOS receiver for evolved EDGE
13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration
A 360-Channel Speech Preprocessor that Emulates the Cochlear Amplifier
A 2.4GHz ULP OOK single-chip transceiver for healthcare applications
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
24.4 A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction
24.2 A Scalable 134-to-141GHz 16-Element CMOS 2D λ/2-Spaced Phased Array
A BJT-Based CMOS Temperature Sensor Achieving an Inaccuracy of ±0.45°C(3σ) from °50°C to 180°C and a Resolution-FoM of 7.2pJ.K 2 at 150°C
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET
A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellation
2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA
EP3: Empowering the killer SoC applications of 2020
A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals
20.9 An energy-recycling three-switch single-inductor dual-input buck/boost DC-DC converter with 93% peak conversion efficiency and 0.5mm 2 active area for light energy harvesting
A Serial-Link Transceiver with Transition Equalization
A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS
A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks
A Crystal-Less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity
A Current-Feedback Instrumentation Amplifier with 5μV Offset for Bidirectional High-Side Current-Sensing