yusuke1997/dblp-id-title huggingface dataset:
Signal Reduction of Signature Blocks for Transient Fault Debugging
A Novel Differential 12T SRAM Bit-cell Structure with Improved SNM in 16nm FinFET Technology
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits
Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy
How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This?
Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connections
Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs
Application of Residue Sampling to RF/AMS Device Testing
Integrated Test Scheduling, Test Parallelization and TAMDesign
Automatic SoC Level Test Path Synthesis Based on Partial Functional Models
On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage
A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test
Scan Chain Diagnosis-Driven Test Response Compactor
Block Marking and Updating Coding in Test Data Compression for SoC
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits
TTTC Introduction
DFT for High-Quality Low Cost Manufacturing Test
Design of FSM with Concurrent Error Detection Based on Viterbi Decoding
Transistor leakage fault location with ZDDQ measurement
How to Design an Environment Simulator for Safety Critical Software Testing
On Estimation of Fault Efficiency for Path Delay Faults
An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation
Memory test time reduction by interconnecting test items
Testability Prediction for Sequential Circuits Using Neural Network
Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing
Aging-Leakage Tradeoffs Using Multi-Vth Cell Library
Defect Oriented Fault Analysis for SRAM
Test Strategies for Reconfigurable Scan Networks
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos
Dynamic Power Supply Current Testing of SRAMs
IEEE Std 1500 Compliant Infrastructure forModular SOC Testing
Fsimac: a fault simulator for asynchronous sequential circuits
Symbolic Path Sensitization Analysis and Applications
Invalid State Identification for Sequential Circuit Test Generation
A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison Model
Formal Design Techniques - Theory and Engineering Reality
Untestable Fault Identification in Sequential Circuits Using Model-Checking
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models
Lessons Learned from Practical Applications of BIST/B-S Technology
Testing of Non-volatile Logic-Based System Chips
On Test and Diagnostics of Flash Memories
A simple technique for locating gate-level faults in combinational circuits
Efficient Testing of Physically Unclonable Functions for Uniqueness
Forecasting the efficiency of test generation algorithms for digital circuits
A graph coloring based approach for self-checking logic circuit design
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors
A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs
3D Specific Systems: Design and CAD
STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data
Functional test generation for path delay faults
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network
A Low-Cost High-Efficiency True Random Number Generator on FPGAs
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters
Fast fault simulation for BIST applications
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths
Test sequence compaction for sequential circuits with reset states
An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based Hardware
Optimal Seed Generation for Delay Fault Detection BIST
Accessing Embedded DfT Instruments with IEEE P1687
SOC Test Time Minimization Under Multiple Constraints
A ROMless LFSR Reseeding Scheme for Scan-based BIST
Efficient BDD-based Fault Simulation in Presence of Unknown Values
Fault Simulation for VHDL Based Test Bench and BIST Evaluation
Test configurations to enhance the testability of sequential circuits
Dynamic Test Set Generation for Analog Circuits and Systems
Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM
Dynamic Analog Testing via ATE Digital Test Channels
Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning
Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
A Method to Detect Open Defects in Wire Segments of On-Chip Power Grids
Analog signal metrology for mixed signal ICs
Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations
Test Compaction in a Parallel Access Scan Environment
Peak-power reduction for multiple-scan circuits during test application
Vector Restoration Using Accelerated Validation and Refinement
Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects
GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan
A BIST Circuit for IDDQ Tests
Testing programmable interconnect systems: an algorithmic approach
Finite State Machine Synthesis for At-Speed Oscillation Testability
HRAE: Hardware-assisted Randomization against Adversarial Example Attacks
Cell Flipping with Distributed Refresh for Cache Ageing Minimization
ATS Steering Committee
Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity
An Application of Partial Scan Techniques to a High-End System LSI Design
Analog circuit equivalent faults in the D.C. domain
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States
Practical Challenges in Logic BIST Implementation
Training diploma students on ATE-related module
BCH-based Compactors of Test Responses with Controllable Masks
SOC Test Scheduling with Test Set Sharing and Broadcasting
Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell
Spectral Estimation Based Acquisition of Incoherently Under-sampled Periodic Signals: Application to Bandwidth Interleaving
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing
24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015
Twine Stack: A Hybrid Mechanism Achieving Less Cost for Return Address Protection
Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method
Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA
Fast hierarchical test path construction for DFT-free controller-datapath circuits
ATPG for Dynamic Burn-In Test in Full-Scan Circuits
ML Based Diagnosis for Fault Location in Digital Circuits
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module
High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects
Robust Built-In Test of RF ICs Using Envelope Detectors
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator
Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers
PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology
Design for Hierarchical Two-Pattern Testability of Data Paths
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation
Mid-bond Interposer Wire Test
An Expression's Single Fault Model and the Testing Methods
Issues Regarding New Product Release in Semiconductor Manufacturing
An Ultra-High-Speed Test Module and FPGA-Based Development Platform
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs
12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China
Rapid and Energy-Efficient Testing for Embedded Cores
Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic
Automated Test Model Generation from Switch Level Custom Circuits
Generating test items for checking illegal behaviors in software testing
Test Power Reduction by Blocking Scan Cell Outputs
Testing and Diagnosis Techniques for LUT-Based FPGA's
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata
Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *
Framework of Timed Trace Theoretic Verification Revisited
Distributed off-line testing of parallel systems
Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip
Test Power Optimization Techniques for CMOS Circuits
Metastability evaluation method by propagation delay distribution measurement
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
Test Data Compression with Partial LFSR-Reseeding
Stress Test for Disturb Faults in Non-Volatile Memories
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
CryptoScan: A Secured Scan Chain Architecture
Built-In Speed Grading with a Process-Tolerant ADPLL
Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test
Fanout fault analysis for digital logic circuits
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches
A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets
Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing
LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling
Hybrid Pin Control Using Boundary-Scan And Its Applications
Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools
Yield Improvement by Test Error Cancellation
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test
Is IDDQ testing not applicable for deep submicron VLSI in year 2011?
On-Line Testing In Digital Neural Networks
An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability
SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults
Fault Detection in a Tristate System Environment
A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures
Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors
Verifying RISC-V Privilege Transition Integrity Through Symbolic Execution
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection
Parametric Fault Detection in Analog Circuits: A Statistical Approach
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems
Test Integration for SOC Supporting Very Low-Cost Testers
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits
Testing and Design-for-Testability Techniques for 3D Integrated Circuits
Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption
On Utilizing Test Cube Properties to Reduce Test Data Volume Further
Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features
Testability Features of R10000 Microprocessor
Two-Gear Low-Power Scan Test
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks
Two-Tone Signal Generation for Communication Application ADC Testing
A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System
A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits
Evaluation of Entropy Driven Compression Bounds on Industrial Designs
A Framework for Automatic Assembly Program Generator (A 2 PG) for Verification and Testing of Processor Cores
A New Approach for Minimal Environment Construction for Modular Property Verification
Test Coverage Analysis for Designs with Timing Exceptions
A Functional Fault Model with Implicit Fault Effect Propagation Requirements
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories
Yield Improvement and Test Cost Optimization for 3D Stacked ICs
Histogram Based Testing Strategy for ADC
Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft
On the Replacement of Scan Chain Inputs by Primary Input Vectors
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults
On Generating High Quality Tests for Transition Faults
Quantum Key Distribution-Based Framework for Securing Encrypted Communications in Address Resolution Protocol Packet Capture
Digital Rights Management for Paper-Based Microfluidic Biochips
Hardware Trojan Detection Based on Signal Correlation
A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing
Time-to-Digital Converter Architectures Using Two Oscillators with Different Frequencies
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
FPGA-Based Subset Sum Delay Lines
Test/Repair Area Overhead Reduction for Small Embedded SRAMs
Top 5 Issues in Practical Testing of High-Speed Interface Devices
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
Design for Two-Pattern Testability of Controller-Data Path Circuits
MEMS Comb-Actuator Resonance Measurement Method Using the 2nd Harmonics of the GND Current
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
Optimizing Test Access Mechanism under Constraints by Genetic Local Search Algorithm
Built-In Self Test for Analog and Mixed-Signal Designs
Noise-Resilient SRAM Physically Unclonable Function Design for Security
Unified scan design with scannable memory arrays
A New Scan Design Technique Based on Pre-Synthesis Thru Functions
High Quality Testing of Grid Style Power Gating
Testability Improvement During High-Level Synthesis
DRAM Specific Approximation of the Faulty Behavior of Cell Defects
A Lightweight Timing Channel Protection for Shared Memory Controllers
Design Verification and Robust Design Technique for Cross-Talk Faults
Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing
Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set
Delay Testing of MOS Transistor with Gate Oxide Short
A Software-Based Test Methodology for Direct-Mapped Data Cache
On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit
False-Path Removal Using Delay Fault Simulation
Embedded Tutorial Summary: Diagnosis for Accelerating Yield and Failure Analysis
A Microcode-Based Memory BIST Implementing Modified March Algorithm
CA Based Built-In Self-Test Structure for SoC
LUT-based Circuit Approximation with Targeted Error Guarantees
A DFT Selection Method for Reducing Test Application Time of System-on-Chips
On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test
A Method of Static Compaction of Test Stimuli
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits
Rectangular Waveform Generation with Harmonics Suppression
Testing System-On-Chip by Summations of Cores? Test Output Voltages
On Defect Oriented Testing for Hybrid CMOS/Memristor Memory
An effective technique preventing differential cryptanalysis attack
A Random Jitter RMS Estimation Technique for BIST Applications
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method
Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault Sites
Tests for Resistive and Capacitive Defects in Address Decoders
On Using Design Partitioning to Reduce Diagnosis Memory Footprint
Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements
A New Scheme to Extract PUF Information by Scan Chain
Variation Aware Analysis of Bridging Fault Testing
Power Management for Wafer-Level Test During Burn-In
Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis
Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder
An On-Line Timing Error Detection Method for Silicon Debug
Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
Universal test complexity of field-programmable gate arrays
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units
Cost Efficient Methods to Improve Performance of Broadcast Scan
GDDR5 Training
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
On energy efficiency of VLSI testing
A methodology for fault model development for hierarchical linear systems
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips
Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment
Functional Testing of Microprocessors with Graded Fault Coverage
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture
Towards Verifiably Secure Systems-on-Chip Platforms
Power-Aware Test Pattern Generation for At-Speed LOS Testing
Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs
21st IEEE Asian Test Symposium, ATS 2012, Niigata, Japan, November 19-22, 2012
FSimGP^2: An Efficient Fault Simulator with GPGPU
SRAM Array Yield Estimation under Spatially-Correlated Process Variation
Deterministic Algorithms for ATPG under Leakage Constraints
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination
An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique
Optimal test-set generation for parametric fault detection in switched capacitor filters
Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance Parameters
Fault Tolerance of a Tree-Connected Multiprocessor System and its Arraylike Layout
Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation
Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests
Intelligible Test Techniques to Support Error-Tolerance
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models
A cellular array designed from a Multiple-valued Decision Diagram and its fault tests
Leveraging Infrastructure IP for SoC Yield
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation
An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing
Time Domain Reconstruction of Incoherently Undersampled Periodic Waveforms Using Bandwidth Interleaving
Application of a Design for Delay Testability Approach to High Speed Logic LSIs
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops
Path Constraint Solving Based Test Generation for Hard-to-Reach States
Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase
Testing for the programming circuit of LUT-based FPGAs
Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification
On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation
Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems
Specification and Design of a New Memory Fault Simulator
Test Diagnosis of Digital Microfluidic Biochips Using Image Segmentation
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths
Study on the Cost/Benefit/Optimization of Software Safety Test
A BIST Technique for RF Voltage-Controlled Oscillators
On testing safety-sensitive digital systems
Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study
IDDQ Testing Method using a Scan Pattern for Production Testing
A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT
SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
Partizipationsformen und Entwicklung eines gemeinsamen Verständnisses bei der verteilten Anforderungserhebung [Ways of Participation and Development of Shared Understanding in Distributed Requirements Engineering]
SWORE - SoftWiki Ontology for Requirements Engineering
Implementing SPARQL Support for Relational Databases and Possible Enhancements
Discovering Unknown Connections - the DBpedia Relationship Finder
Semantic Wikipedia - Checking the Premises
Mapping Cognitive Models to Social Semantic Spaces - Collaborative Development of Project Ontologies
Collaborative Metadata for Geographic Information
Supporting Requirements Elicitation by Semantic Preprocessing of Document Collections
Alternative Searching Services: Seven Theses on the "Importance of Social Bookmarking"
Exploring the Netherlands on a Semantic Path
Galaxy: IBM Ontological Network Miner
The Social Semantic Web 2007, Proceedings of the 1st Conference on Social Semantic Web (CSSW), September 26-28, 2007, Leipzig, Germany
A Prototype to Explore Content and Context on Social Community Sites
Hello Data Web - Exposing the Data Web
IMAGENOTION - Collaborative Semantic Annotation of Images and Image Parts and Work Integrated Creation of Ontologies
Weaving Space into the Web of Trust: An Asymmetric Spatial Trust Model for Social Networks