yusuke1997/dblp-id-title huggingface dataset:
Ultra low voltage, low power 4-2 compressor for high speed multiplications
Automatic Generation of Transistor Stacks for CMOS Analog Layout
A 55nm Cascode Flipped Voltage Follower for MEMS Microphone Interfaces
An advanced emulated digital retina model on FPGA to implement a real-time test environment
Beyond series and parallel: Coupling as a third relation in memristive systems
An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation
A Linear Arrangement Problem with Applications
Multi-Task Learning for Screen Content Image Coding
A switched controller for fast voltage fed parallel active filter
Pitch-synchronous time alignment of speech signals for prosody transplantation
Smooth wavelets, transform coding, and Markov-1 processes
A CNN-driven locally adaptive CMOS image sensor
17-MS/s 9-bit cyclic ADC with gain-assisted MDAC and attenuation-based calibration
Nonuniform decimation and reconstruction of generalized-bandlimited MD signals
Transfer Function Analysis of the Power Supply Rejection Ratio of Capacitor-Less LDOs
Logic computation using coupled neural oscillators
High-Speed Serial and Semi-Parallel IMPLY-based Approximate Adders through Memristors for In-Memory Computing
A metastability-independent time-to-voltage converter
A Digitally-Controlled Ring Oscillator in 28 nm CMOS technology
Coding for jointly optimizing energy and peak current in deep sub-micron VLSI interconnects
A low-power reconfigurable CMOS power amplifier for wireless sensor network applications
Transversal noise current in split-drain transistors
Multi-Time Method Based on State Equations for RF Circuit Analysis
An accurate sense-fet current limiter with embedded softstart for linear dc/dc converters
A silicon retina with controllable winner-take-all properties
Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface
A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers
Optimal construction of compactly-supported multidimensional wavelets
Digital watermarking for object-based compressed video
Adaptive Decision Feedback Equalization for Filter Bank based Multicarrier Systems
An 8K@120fps Hardware Implementation for Decoder-Side Motion Vector Refinement in VVC
An agent approach to power system distribution networks
Application Specific Memories for ATM Packet Switching
An Extended Overlap-Add Method and -Save Method for Sampling Rate Conversion
Quantization-Robust On-Chip Jitter Measurement Technique for Multiple Local Oscillator Systems
Automatic tuning of high-Q filters based on envelope detection
Unifying methodologies for high fault coverage concurrent and off-line test of digital filters
Spike correlation based learning for unsupervised neural lattice structures
180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance
Capacitive Crosscoupling Biquad Polyphase Filter
Parallel decoding architectures for low density parity check codes
PSRR of bridge-tied load PWM Class D Amps
A 0.18µm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels
Highly secured state-shift local clock circuit to countermeasure against side channel attack
Constant gm rail-to-rail CMOS OpAmp with only one differential pair and switched level shifters
A Multi-Sensing ISFET Array for Simultaneous In-Pixel Detection of Light, Temperature, Moisture and Ions
Idling Car Detection with ConvNets in Infrared Image Sequences
A Novel Method for the Fault Detection of Analog Integrated Circuits
Polarization analyzing CMOS sensor for microchamber/microfluidic system based on image sensor technology
An SRAM-based Stochastic Number Generator for Stochastic Computing
A method for the simulation of switching DC-DC power supplies
Modeling orientation selectivity using a neuromorphic multi-chip system
Behavioral synthesis of datapaths with low leakage power
Built-in selectors self-assembled into memristors
An Excitation Time Model for General-purpose Memristance Tuning Circuit
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS
MPEG complexity reduction by scene adaptive motion estimation
A programmable low voltage switched-current FIR filter
Scalable architecture for word HMM-based speech recognition
Can spike timing dependent plasticity compensate for process mismatch in neuromorphic analogue VLSI?
A portable all-digital pulsewidth control loop for SOC applications
Predictive timing error calibration technique for RF current-steering DACs
Design of A Low Noise Neural Recording Amplifier for Closed-loop Neuromodulation Applications
Analog VLSI design of an adaptive neuromorphic chip for olfactory systems
Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation
Conditions for Hurwitz Stability of Interval Matrices
Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration
An 1.1 V 0.1-1.6 GHz tunable-bandwidth elliptic filter with 6 dB linearity improvement by precise zero location control in 40 nm CMOS technology for 5G applications
Dual Recovery Network with Online Compensation for Image Super-Resolution
Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors
A micropower envelope detector for audio applications
A 3.2 mW 0.13 μm high sensitivity frequency-domain CMOS capacitance interface
Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology
Robust image and video coding with pyramid vector quantisation
Simple parallel weighted order statistic filter implementations
Rapid design and prototyping of universal soft demapper
Design of Limit-Cycle-Free Recursive Transfer Functions for Fixed-Point Direct Form Implementation
Low-distortion delta-sigma topologies for MASH architectures
Unsupervised Multiple Granularities Attention-Attribute Learning for Person Re-Identification
Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency
A Comprehensive Analysis of Charge-Pump-Based Multi-Stage Multi-Output DC-DC Converters
Content based fast prediction unit quadtree depth decision algorithm for HEVC
Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks
Low-power Linear-phase Delay Filters for Neural Signal Processing: Comparison and Synthesis
Modeling of dynamic video traffic
Design and multiplierless implementation of two-channel biorthogonal IIR filter banks with low system delay
Designing CT bandpass ΣΔ modulators with arbitrary STF shapes
Chordal relaxation of OPF for multiphase radial networks
Logic-compatible embedded DRAM design for memory intensive low power systems
Shielding area optimization under the solution of interconnect crosstalk
A High Resolution Chemical Sensing Front-end with Integrated Sigma Delta Quantisation
A 23.4-27.6 GHz "Zig-Zag" VCO with Continuous Frequency Switching for FMCW Radars
Low rank approximation of a set of matrices
IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021
Power-oriented delay budgeting for combinational circuits
Dead time effects in the indirect time-of-flight measurement with SPADs
Hardware Acceleration of DNA Pattern Matching with Binary Memristors
Power efficiency calculation of class E amplifier with nonlinear shunt capacitance
Live Demonstration: A Customizable Medical IR Imaging System for Clinical Diagnosis
Low-Complexity Fully-Digital Phase Noise Suppression for Millimeter-Wave Systems
On the identifiability of bilinear systems
On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps
A High-Density Transcranial Electrical Stimulation System on Chip with Real-Time Bio-Impedance Sensing
A portless SRAM Cell using stunted wordline drivers
An Adaptive Constrained Least Square Approach for Removing Blocking Effect
A simulated annealing based method supporting dual supply voltages in standard cell placement
Analysis of multirate sigma-delta modulators
Assessment of probability density estimation methods: Parzen window and finite Gaussian mixtures
Stochastic analysis of power, latency and the degree of concurrency
Brand and IP protection with physical unclonable functions
A capacitor constructed bypass window switching scheme for energy-efficient SAR ADC
Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver
An efficient VLSI architecture for RSA public-key cryptosystem
Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching
Edge orientation enhancement using optoelectronic VLSI and asynchronous pulse coding
ELT-based wavelet coding of high-fidelity audio signals
A nano-CMOS process variation induced read failure tolerant SRAM cell
A dynamic vision sensor with direct logarithmic output and full-frame picture-on-demand
Live demonstration of DLD-VISU: An eLearning platform for digital logic design
High Slew Rate, Low Voltage BiCMOS and Bipolar Operational Amplifier Architectures with Rail to Rrail Common Mode Input Voltage Swing
Observability analysis by measurement Jacobian matrix for state estimation
CANet: Cellular Aggregation Network for Point Cloud Quality Assessment
Mixed-signal VLSI for neural and fuzzy sequential processors
An heuristic circuit-generation technique for the design-automation of analog circuits
A novel low-power readout structure with 1/2 sub-scan time-delay-integration and DLL-based A/D for 1024×6 infrared focal plane array
N-HAR: A Neuromorphic Event-Based Human Activity Recognition System using Memory Surfaces
A Reconfigurable High-Dynamic Range ∆Σ Front-End with Event-Based Decimation for Bandwidth-Efficient Implantable Neural Interfaces
Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL
A Compressed sensing analog-to-information converter with edge-triggered SAR ADC Core
High-voltage operational amplifier based on dual floating-gate transistors
Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building
Size-Adjustable Photoacoustic Tomography System with Sectorial Ultrasonic Transducer Array
Compactly supported matrix valued wavelets-biorthogonal unconditional bases
A mathematical framework for active circuits based on port equivalence using limit variables
Yield Optimzation of Analog MOS Integrated Including Transistor Mismatch
Substrate noise suppression technique for power integrity of TSV 3D integration
A New Type of Chaotic Attractor with Cellular Neural Networks
Motion information and coding mode reuse for MPEG-2 to H.264 transcoding
A high-swing MOS cascode bias circuit for operation at any current level
Number of stimulation units needed to derive all the phase patterns in pulse-driven star-coupled LC oscillators
Memory Footprint Optimization Techniques for Machine Learning Applications in Embedded Systems
An incremental sigma delta converter for compressive sensing applications
An Integer-only Quantization Framework for Edge Deployment of Large Language Models
A recurrent neural network for nonlinear convex programming
An online fully-digital calibration of leakage noise in MASH continuous time ΔΣ modulators
Quasi-periodic signal analysis using harmonic transform with application to voiced speech processing
VLSI concentric partitioning using interior point quadratic programming
Mixer topology selection for a 1.8 - 2.5 GHz multi-standard front-end in 0.18µm CMOS
A 63.2μW 11-Bit Column Parallel Single-Slope ADC with Power Supply Noise Suppression for CMOS Image Sensors
A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection
Prediction of Subharmonic Oscillation in SIMO DC-DC Converter with Ordered Power Distributive Control in CCM and Peak Current Mode
Device modelling of bendable MOS transistors
A systolic array technique for determining common approximate substrings
Towards the circuit implementation of the Hodgkin-Huxley neuron model: A PWL approach
Switch synchronizing delayed feedback control for piecewise linear systems
A Novel Approach to Solving the Generalized Inverse Frobenius-Perron Problem
A Highly Sensitive 2.5 Gb/s Transimpedance Amplifier in CMOS Technology
Boundary cells in cellular circuits for the minimisation of continuous functionals
Vector transform video coding for packet switched networks
A CMOS bandpass filter with wide-tuning range for wireless applications
Direct temperature to digital converters with low supply sensitivity for power/thermal management
A substrate noise circuit for accurately testing mixed-signal ICs
Neural Network-Based Arithmetic Coding for Inter Prediction Information in HEVC
Joint Source-Channel Modeling and Estimation for Speech Dereverberation
Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL
A relaxation oscillator with multi-phase triangular waveform generation
Relaxing RF component requirements in a Weaver architecture by learning and adapting to the environment
A symbolic SC integrator model for fast time-response simulation
Live Demonstration: A Wearable Armband for Real-Time Control of Multi-DOF Robotic Actuators
A 75-MHz-BW 3rd-order Time-Interleaved Noise-Shaping SAR ADC with Shared EF-CIFF Loop Filter and Ring Buffer
A Temperature-Compensated Class-AB Parametric Residue Amplifier for SAR-Assisted Pipeline ADCs
A low-power two-line inversion method for driving LCD panels
Design rewiring for power minimization [logic design]
A family of SiGe quadrature oscillators for microwave applications
A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs
An On-Chip Dual-Output Switched-Capacitor DC- DC Converter with Fine-Grained Output Control
A robust video encoding scheme to enhance error concealment of intra frames
Comparing the Wavelet OFDM and Windowed OFDM data rate for in-home PLC
A reusable IP FFT core for DSP applications
Secured Dual Mode Logic (DML) as a countermeasure against Differential Power Analysis
An 8-bit 900MS/S two-step SAR ADC
Low-power real-time ECG baseline wander removal: Hardware implementation
A novel system for intrabody communication: touch-and-play
A 3.47 e- Read Noise, 81 dB Dynamic Range Backside-Illuminated Multispectral Imager for Near-Infrared Fluorescence Image-Guided Surgery
A high throughput belief propagation decoder architecture for polar codes
Parallel HDR tone mapping and auto-focus on a cellular processor array vision chip
Hyper-parameter Tuning for Progressive Learning and its Application to Network Cyber Security
Analysis of Traffic Accident Occurrence in Niigata Prefecture of Japan using Open Data
A panoramic endoscope design and implementation for Minimally Invasive Surgery
Compact 2 17 NTT Architecture for Fully Homomorphic Encryption
A compact on-chip IR-drop measurement system in 28 nm CMOS technology
A low-latency NoC router with lookahead bypass
A parameterised block-level layout generation system for CMOS analog ICs
Joint Source-Channel-Authentication Resource Allocation for Multimedia overWireless Networks
Touching Silicon: Educational Use of the Atomic Force Microscope in Circuits and Systems
Invariant sums of higher order sensitivities
Combined Distinguishers to Enhance the Accuracy and Success of Side Channel Analysis
Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter
A 2-path bandpass sigma-delta modulator utilizing a 3-path structure
CMOS transconductor design for VHF filtering applications
A single-chip 600-fps real-time action recognition system employing a hardware friendly algorithm
1-d cellular automaton for pseudorandom number generation and its reconfigurable hardware implementation
A reconfigurable multi-stage frequency response masking filter bank architecture for software defined radio receivers
A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks
An autozeroing floating-gate amplifier with gain adaptation
Measurements of Linear Composite MOSFET Circuits and Further Applications
Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance
Precoded OFDM for power line broadband communication
Design and Optimization of Modular Multiplication for SIDH
An efficient and well-controlled IC system development flow: design approved specification and design guided test plan
Oversampled linear-phase perfect reconstruction filter banks with higher-order feasible building blocks: Structure and parameterization
Intra Encoding Complexity Control with a Time-Cost Model for Versatile Video Coding
Stability analysis supports memristor circuit design
Novel Intrinsic Physical Unclonable Function Design for Post-quantum Cryptography
Diagnosis of assembly failures for System-in-Package RF tuners
A 0.8V, 113nW Single-BJT Sub-BGR Using an nMOS PTAT Amplifier at 0.9V Supply
Restoration from image degraded by white noise based on iterative spectral subtraction method
A Multi-Mode Visual Recognition Hardware Accelerator for AR/MR Glasses
A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
An Algorithm for the Calculation of Generalized Walsh Transform of Boolean Functions
Recent advances in multidimensional systems and signal processing: An overview
Unispherical windows
Power efficient architecture for (3, 6)-regular low-density parity-check code decoder
A novel sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation
Localization of Deep Video Inpainting Based on Spatiotemporal Convolution and Refinement Network
Dual-tree Complex Wavelet Transform Arising from Cosine-sine Modulated Filter Banks
Hardware-based Neural Networks using a Gated Schottky Diode as a Synapse Device
Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-Applications
Survey of Recent Developments for Hardware Trojan Detection
FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations
On shift variance bounds in multi-channel filter banks
Classification of driver's cognitive responses from EEG analysis
Digital, analog and RF design opportunities of three-independent-gate transistors
Defining reactive power in circuit transients via local Fourier coefficients
A 22 Gb/s Directly Modulated Optical Injection-Locked Quantum-Dot Microring Laser Transmitter with Integrated CMOS Driver
Tunable rail-to-rail FGMOS transconductor
Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays
Effect of Circuit Non-Idealities on Active On-Chip Delay Lines
Area optimization of lightweight lattice-based encryption on reconfigurable hardware
A wirelessly tunable low drop-out regulator for subcutaneous muscle prosthesis
Constant addition utilizing flagged prefix structures
Analog 2D fan filters from discrete domain transfer functions
A low power hearing aid computing platform using lightweight processing elements
Towards an Improved Model for 65-nm CMOS at Cryogenic Temperatures
Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems
Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder
Time-domain PLL modeling and RJ/DJ jitter decomposition
A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator
A minimization of the charge injection in switched-current circuits
Design of highly linear tunable CMOS OTA
Approximation and compression of arbitrary time-series based on nonlinear dynamics
Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition
A simple simulation method for analyzing substrate coupling
A 2µA temperature compensated mems-based real time clock with ±4 ppm timekeeping accuracy
10-th order programmable low-pass CMOS integrated pulse-shaping filter
A 24 mW, 80 dB SNR, 50 MHz multi-bit continuous time ΣΔ ADC in 28 nm FD-SOI
Efficient signal processing in embedded Java systems
VLSI implementation of a multicast ATM switch
A 17.1 TOPS/W FP-INT Transformer Inference Accelerator with Sparsity Boosting and Output Importance-Aware Processing
A 10 Gb/s optical receiver in 0.25 µm silicon-on-sapphire CMOS
A subthreshold, low-power, RHBD reference circuit, for earth observation and communication satellites
Compiler and microarchitectural approaches for register file thermal management
Efficient multi-frame motion estimation algorithms for MPEG-4 AVC/JVT/H.264
A monolithic fully-differential CMOS gas sensor microsystem for microhotplate temperatures up to 450°C
Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology
Phase-Variable Control of Parallel Synchronized Triple Bias-Flips Interface Circuit towards Broadband Piezoelectric Energy Harvesting
A new CCII-based pipelined analog to digital converter
VHDL-AMS virtual prototyping of a generator circuit breaker ablation monitoring system
Relaxed tree search MIMO signal detection algorithm design and VLSI implementation
Application of wolf group hierarchy optimization algorithm to fault section estimation in power systems
Low-energy pixel approximation for DVI-based LCD interfaces
A one-layer recurrent neural network for constrained single-ratio linear fractional programming
ZergPPU: an evolutionary multi-mode post processor for vision neural networks
Towards Wave Digital Modeling of Neural Pathways Using Two-Port Coupling Networks
CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control
Memory-Based Contrastive Learning with Optimized Sampling for Incremental Few-Shot Semantic Segmentation
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method
LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine
An 8-bit current mode ripple folding A/D converter
Design of Allpass Fractional Delay Filter and Fractional Hilbert Transformer Using Closed-Form of Cepstral Coefficients
An integrated digital PWM DC/DC converter using proportional current feedback
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders
The recovery of distorted bandlimited almost-periodic signals
Padding-Aware Learned Image Compression
SNR Measurement of Superregenerative Oscillators
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values
A New Compact Architecture for AES with Optimized ShiftRows Operation
Compact low-voltage CMOS current-mode multiplier/divider
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit
A "Nyquist-Like" Noise Theorem for Linear Periodically-Switched RLC Networks
Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology
Improved charge shared scheme for low-energy match line sensing in ternary content addressable memory
An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters
A High-Sensitivity and Wide-Dynamic-Range Image Sensor with Extended-Silicon Responsive Spectrum from 254 nm to 1310 nm
Formulas to generate efficient piecewise-polynomial implementations of narrowband linear-phase FIR filters
A New Technique for Transient Analysis of Periodically Switched Circuits
Supply noise insensitive bandgap regulator using capacitive charge pump DC-DC converter
Full waveform accuracy to estimate delay in coupled digital circuits
Minimum selection GSC and adaptive low-power rake combining scheme
A Novel Relaxed ADMM with Highly Parallel Implementation for Extreme Learning Machine
Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications
An image segmentation method with multi-resolution mechanism
Control of bifurcation in current-programmed DC/DC converters: a reexamination of slope compensation