yusuke1997/dblp-id-title huggingface dataset:
Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform
Design of a miniaturized UWB antenna optimized for implantable neural recording systems
Bandwidth enhancement of planar EBG structure using dissipative edge termination
Design of an Energy Efficient Analog Two-Quadrant Multiplier Cell Operating in Weak Inversion
A 24 GHz Rectifier and Its Applications in Energy Harvesting and Wireless Power Transfer Systems
Continuous calibration of Rogowski coil current transducer
Calibration requires calibration, a case study: Mixed-signal BISC Time-Interleaved ADC
A 0.0053-mm 2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS
A black-box approach to RF LNA design
NoC-MRAM architecture for memory-based computing: Database-search case study
Optimizing Real-Time Performance in Electronically Foveated Dynamic Vision Sensor
GCoL - A General Co-simulator Applied to Wireless Sensor Networks and RTL Design
An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI
23rd IEEE Interregional NEWCAS Conference, NEWCAS 2025, Paris, France, June 22-25, 2025
Study of a high-resolution and low-power CMOS temperature sensor
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks
Analysis of reversion losses in charge pumps and its impact on efficiency for low power design
A compensation scheme for three-stage OTAs with no Miller capacitors
Broadband microwave biosensing based on interdigitated capacitor for Lab-on-Chip applications
Non-linear modeling of MEMS-based oscillators using an analog hardware description language
Memristor-assisted Background Calibration for Analog-to-Digital Converter
High-Speed all-GaN Gate Driver with reduced power consumption
Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups
Ultra Low-Power 2.5µW CMOS Implementation of a Mixed Analog-Digital Wake-Up System Based on Frequency Analysis
Wireless Sensor Patch Suitable for Continuous Monitoring of Contact Pressure in a Clinical Setting
Design and Implementation of an FFT-Based Neural Network Accelerator Using Rapid Single-Flux-Quantum Technology
Ultra Low Power Small Area Active Balun for Low Frequency Biomedical Optical Communication
Deep Learning Based Stress Assessment Using PPG Signals from WESAD Dataset
A Time-Domain Charge-Balancing Method for Neuromodulators
Frequency-to-amplitude converter based FSK receiver for ultra-low power transceivers
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters
Capacitively Isolated 400 Mbps Data Transfer System with 2 Ns Propagation Delay and 5 kV /µs Common Mode Transient Immunity
${\mathrm{V}}_{\text {DD }}$-Scalable and Reference-Less Body-Biased Inverter-Based OTA Exploiting Improved Composite Transistors for ULV/ULP Applications
Low-Power Single-Slope ADC with a Replica Comparator for Always-on CIS Applications
RF powered integrated system for IoT applications
Random Number Generator Based on Micro-Scale Bio-electrochemical Cell System
Collision avoidance improvement using a risky area
Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs
UPF-Aware CDC Structural Verification on RTL
A new integer energy activity measure for parallel bit plane coding
ST-MambaAD: Spatial-Temporal Mamba for Multivariate Time Series Anomaly Detection
Flicker Noise Analysis on Chopper Amplifier
Approximate computing with unreliable dynamic memories
A 0.5V 46.2ppm°C CMOS Voltage Reference Based on Compensated ΔVTH with Wide Temperature Range and High PSRR
A New Current-Mode Subthreshold, High-PSRR MOSFET-Only Bandgap Voltage Reference
A bidirectional short range low power and high data rate W-Band transceiver for network on chip
EPC Gen-2 UHF RFID tags with low-power CMOS temperature sensor suitable for gas applications
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity
New Analytical Boundary Condition for Optimized Outphasing PA Design
Correcting ADC jitter using DPLL timing error signal
FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips
A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations
A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors
Challenges in recording and stimulation of living neural network based on original micro-electrode array (MEA) developments
Earbud-Based UWB Data Link for Multichannel Brain Neural Recording and Stimulation Interfaces
Digital direct-driven speaker architecture using segmented pulse shaping technique
A compact 67 GHz oscillator in 65nm CMOS
A Multilayer Perceptron (MLP) Regressor Network for Monitoring the Depth of Anesthesia
A real time 3D video CMOS sensor with time gated photon counting
Power amplifier design challenges in UHF and VHF transmitters
Fast hierarchical system synthesis based on predictive models
A variable RADIX-2 r algorithm for single constant multiplication
Evaluation of Secure Circuit Styles Using Unipolar Logic Gates
Analysis of the effects of clock imperfections in N-path filters
A high level mixed hardware/software modeling framework for rapid performance estimation
Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs
A High Speed Fully Integrated Capacitive Digital Isolation System in 0.35 µm CMOS for Industrial Sensor Interfaces
21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023
Energy-efficient control through power mode placement with discrete DVFS and Body Bias
A contour preserving FPGA architecture for PAL to XGA format conversion
Efficient parallel-SSHI interface circuit for piezoelectric energy harvesting
A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI
Instrumentation circuitry for an inductive wear debris sensor
An Adaptive Power Management Unit for Self-Sustainable Smart Vision Sensor
An FIR memory polynomial predistorter for wideband RF power amplifiers
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors
Designing Mixed-Signal PLLs regarding Multiple Requirements taking Non-Ideal Effects into Account
Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy
Impact of short-channel effects on velocity overshoot in MOSFET
A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA
A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit
Behavioral Modeling of Nonlinear Power Amplifiers Using Spiking Neural Networks
Zero-power mismatch-independent Digital to Analog converter
A reference-based specification tool for creating reliable library development specifications
A 38 μA wearable biosignal monitoring system with near field communication
A two-step layout-in-the-loop design automation tool
A Wideband Low-Power Current-Reuse RF-to-BB Receiver Using a Clock Strategy Technique
On lossy memristive behavior of metal conductors
A correction code for multiple cells upsets in memory devices for space applications
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology
Analysis, design, and characterization of wireless power transfer systems using conical coils
Low emission, open loop MAC protocol compliant implantable FSK modulator
Construction of Delay-Driven GNR Routing Tree
A hybrid Chaos-AES encryption algorithm and its impelmention based on FPGA
Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices
Mitigation of Mutual Pulling in Two Phase-locked Loops
Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis
A single photon avalanche detector in a 180 nm standard CMOS technology
Broadside FD Antenna Topologies for Nanosat Intersatellite Link
LSTM with Scattering Decomposition-Based Feature Extraction for Binaural Sound Source Localization
Optimize hardware with fixed-point variable length phase factors
High-speed analog processing for real-time fault location in electrical power networks
Direct Magnitude and Phase Measurement in an Inductorless Integrated Vector Network Analyzer for Wideband Ambient Environment Sensing
Non-Linear Sequential SVM Classifier of Epileptic Seizures
Optimized Co-Design of Delta Sigma Modulators and Fir-DACs for High Speed Transmitters
On the importance of bias-dependent charge injection for SET evaluation in AMS Circuits
Investigation and Optimization of Ground Bounce in Switching-Mode Circuits
A Low-Power Wideband Receiver Front-End for NB-IoT Applications
Performance and Stability Characterization of a 3rd Order Continuous-Time Delta-Sigma Modulator with Active Time-Constant Tuning
Ultra Low Latency Implementation of Robust Channel Estimation and Equalization for Industrial Wireless Communication Systems
On-chip voltage regulator without physical inductor
Globally stable, highly parallelizable fast transient circuit simulation via faber series
Study of rough surface to decrease reverberation noise in ultrasonic imaging
A data driven CGRA Overlay Architecture with embedded processors
Variability budgetin pulsed flip-flops
All-digital MEMS tuning-fork self-excited vibration control by phase-relation using TAD-based ADPLL
A Wideband Balun-LNA for Sub-6-GHz 5G NR with Multi-Mode Operation in 22-nm FD-SOI
A fully digital Ultra-wide band sub-GHz pulse generator
A hybrid power delivery method for asynchronous loads in energy harvesting systems
A 900MHz RF energy harvesting module
A Current-Mode Implementation of A Nearest Neighbor STDP Synapse
New Design Opportunities exploiting FDSOI technology for RF Power Amplifier and LNA design
Design of a Reconfigurable Receiver for Nanophotonic Interconnects
Bifrequency characterization of linear time-varying systems
Pre-Global Routing DRC Violation Prediction Using Unsupervised Learning
An FPGA-based adaptive tuning control for a cochlea-mimicking filter channel
Rapid prototyping of microfluidic devices and their applications
A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems
A general scheme for noise-tolerant logic design based on probabilistic and DCVS approaches
Image super-resolution with multi-channel convolutional neural networks
A Low-Noise CMOS Front-End with 534 MΩ Transimpedance Gain for Single-Molecule Signal Acquisition
An 8 Channel Transceiver ASIC to Interface a CMUT Array
Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI
Computational load reduction by downsampling for energy-efficient digital baseband
CMOS Temperature Sensor Utilizing Gate-length-based Threshold Voltage Modulation
Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing
Determining the quality metrics for PUFs and performance evaluation of Two RO-PUFs
Positive feedback technique for DC-gain enhancement of folded cascode Op-Amps
Gated Delay Line Up-Down Counters for Mixed-Signal Processing
A High Dynamic-Range Readout Circuit with Differential Resistance-to-Time Conversion for Gas Sensor
Design-Oriented Active Balun for $6-\text{GHz}$ and Low-Voltage Applications
Architectural impacts of emerging transistors
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator
A Dynamically-Biased Relaxation Oscillator for Low-Power Applications
A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS
A floorplan method for ASIC designs of asynchronous circuits with bundled-data implementation
Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests
FPGA-implementation of pipelined neural network for power amplifier modeling
A Wide-Load-Range Mixed-Mode LDO Regulator with Single-Transistor-Assisted Buffer
RISC-V Resource-Constrained Cores: A Survey and Energy Comparison
A 0.35V 12.9pW 8.3ppm°C 0.012%/V Feedbackcontrolled Voltage Reference in 65 nm CMOS
A dual-level and dual-band class-D CMOS power amplifier for iot applications
High-performance Multi-function HMAC-SHA2 FPGA Implementation
A 3.3 GHz class-E power amplifier with 77% PAE utilising GaN HEMT technology
Bi-Linearity of Back Gated Schottky Barrier Transistors on an Industrial 22nm FDSOI Platform for Efficient In-Hardware Matrix-Vector Multiplication and Addition
Sub-1 V, 4 na CMOS voltage references with digitally-trimmable temperature coefficient
A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks
Prototype of a multispectral and multiwavelength pulse oximeter based on a BQJ sensor
Efficient Arbitrary Sample Rate Conversion for Multi-Standard Digital Front-Ends
A High Data Rate, Wide Dynamic Range Envelope Detector for Short Distance Ultra-Low Power WuRx Applications in 2.4 Ghz ISM-Band
Narrowband Filtering Low-Noise Amplifier for FMCW Automotive Radar Front-Ends
Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator
Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation
Analog Baseband Circuits for Low-power 802-11ba Wake-up Radio in 40-nm CMOS
A Biomedical Imaging System Based on an Integrated Array of Magnetoresistive Sensors
Autonomous energy management interface for electrostatic series-parallel charge pump vibrational energy harvester
Adaptive FOCV MPPT for Piezoelectric Energy Harvesting Circuit
D2ECG: Deep-Shift DNN-based ECG Classifier for Resource Efficient Hardware Implementation
Compact modeling of vertical hall-effect devices: Electrical behavior
An ULP and very efficient adaptively biased LDO regulator for harvesting application
Optical Control of Neural Dynamics Using LED Array
A High-Accuracy Hysteretic DC-DC Converter Using A Spread-Spectrum EMI Suppression Technique with Double Gold Codes
A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces
Direction-of-arrival estimation in a clustered channel model
Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM
A space grade camera for image correlation
Additive companding implementation to reduce ADC constraints for multiple signals digitization
A 138.39 FoMS, 2.8 nW, 65dB, Digital-Based OTA for Bio-Signal Processing Applications
Optimized integrated micro-hotplates in CMOS technology
A Multi-Modal Stimulator System for Visual Prosthesis
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling
Maximally flat property and bandwidth enhancing by transfer function zeroes
Design of a Switched-Mode Operational Amplifier Operating With a 0.5V Supply Voltage
Time-domain simulation of quantization noise mixing and charge pump device noise in fractional-N PLLs
Bienvenue [in French only]
Doherty Power Amplifier Based TR front end Network for 5G Mm-Wave Applications
A novel technique to characterize the spatial intra-pixel sensitivity variations in a CMOS image sensor
Background calibration of integrator leakage in discrete-time delta-sigma modulators
Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path
Low-Power Neural Network Accelerator for Sleep Stage Classification Using Chin Electromyography
Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB
High-Speed and Low-Noise Multichannel System for Broadband Coherent Raman Imaging
High Utilization Vision Transformer Accelerator with Flexible Dataflow
Performance characterization of an SCMA decoder
3A Fault Tolerant Low Side Driver Circuit Design Using Design FMEA for Automotive Applications
Ultra Low Voltage Sub-100 mV Vdd CMOS
An 88-Gb/s/pin Single-Ended PAM-4 Transmitter in 28-nm CMOS With Duty-Cycle-Error and Quadrature-Phase-Error Correction Using Pre-Coded Data Patterns
Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks
A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps
A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator
Skew-Tent Map Based CMOS Random Number Generator with Chaotic Sampling
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron
A temperature compensated relaxation oscillator for SoC implementations
A 433MHz Multi-Mode Wake-Up Receiver Achieving High Sensitivity via Balun LNA and Injection Locked Oscillator
Innovative device source/drain and channel implantation for MOS transistors in ultra low power subthreshold circuit applications
A digitally programmable 50-150dB DC gain operational transconductance amplifier in 130nm CMOS
Application-specific shared last-level cache optimization for low-power embedded systems
Design of an adjustable bias circuit using a single-sided CMOS supply for avalanche photodiodes
Nonlinear Quantization Technique for Multibit Sigma-Delta Modulators
Current TRAM: A Circuit Scheme for Highly-Linear, Tunable V/I Conversion with Ultra-Low Transconductance
Proximity distance estimation based on capacitive coupling between 1mm 3 sensor nodes
Data-Transition Decision Feedback Equalizer with Edge-Emphasis Taps and Raised References
Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching
Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling
Optimally pre-damped switched-inductor piezoelectric energy-harvesting charger
Protecting FPGA bitstreams using authenticated encryption
A 2.45GHz SiGe Power Amplifier with a Novel Digital Predistortion using Orthogonal Sequences
Joint Blind Estimation and Equalization Method Based on Deep Learning for Fast Fading Channels
A 2.9-Gb/s Spread-Spectrum Clocking Transceiver Using Phase Interpolation for Chip-to-Chip Links
Extending Wireless Power Transfer Range for Self-Powered Micro Devices with mm-size Antenna
Accurate and efficient analytical electrical model of antenna for NFC applications
A 4000 Hz CMOS image sensor with in-pixel processing for light measurement and modulation
An efficient algorithm for 3D-IC TSV assignment
A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE
An Ultra-Wideband Amplifier With Compact Magnetically Coupled Feedback Gain Cell
A 2.3nA-to-205nA Clock-Tunable Dynamic Current Reference with a Built-in 2nd-Order Current-Mode Low-Pass Filter and Coarse-Fine Regulation
Comparative Study of Linearized Analysis Frameworks for Mid-Rise TDCs
A 22 nm CMOS .000005 \text{mm}^{2} 0.25 \mathrm{V}$ 2.3pW ISFET Front-End Using Low-Gate-Leakage Thick-Gate-Oxide Transistors for Energy-Efficient Small-Formfactor pH Monitoring
A parallelized layered QC-LDPC decoder for IEEE 802.11ad
A Hybrid 4 th -Order 4-Bit Continuous-Time ΔΣ Modulator in 65-nm CMOS Technology
Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL
Integrated Self-Interference Suppression for Single Antenna Full-Duplex without Circulator
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI
Multi-step capacitor switching scheme for low-power SAR ADC
A High Dynamic Range High Speed Pixel Operating at 100 Million Frames Per Second
Design of A 5-10 GHz Open-Loop Quadrature Clock Generator for High-Speed Wireline Systems
Comparison Study of Averaging Resistor Implementations for Common-Mode Feedback Circuits
A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array
A synthesizable Time to Digital Converter (TDC) with MIMO spatial oversampling method
Generative-Neural-Networks-Based PV-Aware Analog Layout Correction
High-Resolution Hybrid Hardware Implementation of DOA Estimation Using MVDR and MUSIC Algorithms on RFSoC Gen 3 Platform
Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices
A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking
A Trimless, Startup-Free MOS-Based Voltage Reference with 40 mV Variation Across Process and Temperature
Exploring Dielectric Resonator Antennas for Plantar Pressure Monitoring
A Novel Dynamic Memristor Window Function for High Frequency Applications
Design Techniques for Sample-and-Hold with Bootstrapping in Low-Power SAR ADC
Substrate-coupling effect in BiCMOS technology for millimeter wave applications
A Computation-Efficient Solution for Acceleration of Generative Adversarial Network
Ultra-low-power RF transceivers for WBANs in medical applications
Two-level hierarchical fill-buffer for graphics rendering systems
A new digital locking MPPT control for ultra low power energy harvesting systems
Distributed Embedding Approach for Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning
Passive Localization Algorithm using a Highly Integrated Acoustic Sensor Array
10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm
Influence of the output harmonic networks of classes F and F -1 power amplifiers in LINC systems
Advanced modeling technique for bandpass continuous-time delta-sigma modulators
An ultra-low power high-order temperature- compensated CMOS voltage reference
Subsampling techniques applied to 60 GHz wireless receivers in 28 nm CMOS
Nonlinearity Modeling of Chireix Outphasing Power Combiner Under Amplitude Imbalance
A Single Channel Concurrent Data Transmission System for Detection of 4-Electrode Dissolved Oxygen and Temperature
A Low Power Fully Analog MAC Operation Using Standard CMOS Technology for Neural Network Inference
Out-of-Band Digital Predistortion in Joint Communication-Computation Networks for Transmission Standards
Embedded instruments for enhancing dependability of analogue and mixed-signal IPs
A low-power 2.4-GHz combined LNA-VCO structure in 0.13-μm CMOS
Analysis of the impact of finite OFF-state impedance of peaking branch on the efficiency of Doherty amplifiers
Power Consumption Reduction in Digital Beamforming Using Noise Decorrelation
Assessment of 2T2R Logic-in-Memory in a Cycle-to-Cycle Variation-Aware Simulation Environment
Digitally controlled transconductor based on a quantum transconductance
An improved BCD adder using 6-LUT FPGAs
A High-Efficiency LDO With Adaptive PSRR and Bandwidth Enhancements
Motor Task Learning in Brain Computer Interfaces using Time-Dependent Regularized Common Spatial Patterns and Residual Networks
Hardware design of a neural processing unit for bio-inspired computing
Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries
Standard CMOS voltage-mode QLUT using a clock boosting technique
Demonstration of 300 Mbit/s free space optical link with commercial visible LED
Integrated differential high-voltage transmitting circuit for CMUTs
American Sign Language Recognition System Using Wearable Sensors and Machine Learning
Reference-Free Single-Ended Spin-Transfer Torque MRAM with Low-Power Sensing
A Design Method for $\Delta\sum$ Force-Feedback Accelerometer Interface Systems
Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories
A Fully Integrated SCC DC-DC Converter with Novel FMC Controller for Fast Transient Response
Neuro-Headstage with On-Chip Machine Learning and Wireless Charging for Closed-Loop Neurobiological Applications
Low-latency asynchronous networking for the IoT: Routing analog pulse delays using IR-UWB
Automatic generation of parallelized FFT logic for implementation in FPGA chips
ORVD-Trellis based MIMO detection
Integrated transmission lines for complementary cross-coupled bandpass filters in ΣΔ modulators
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic
Self-Contained Power Amplifier for 5G
Quad-Level Carrier Width Modulation demodulator for micro-implants
Short range remote powering of implanted electronics for freely moving animals
Adaptive and digital blind calibration of transfer function mismatch in time-interleaved ADCs
Energy and accuracy in multi-stage stochastic computing
Processor Configurable Sample Rate Converter for RISC-V and 5G Communication