yusuke1997/dblp-id-title huggingface dataset:
Different load models based on particle swarm algorithm for the siting and sizing optimization problem for distributed power
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI
A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface
A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface
A 186µW Glucose Monitoring SoC using Near-Infrared Photoplethysmography
A 1.96Vpp Input-Range 3rd-order Noise-Shaping Pipelined-SAR ADC with Self-Boosted Impedance and Active Charge Sharing for Biosignal Acquisition
LPNA: A 2.75 ms Low-Latency and 0.40 uJ/point Energy-Efficient LiDAR Point-Cloud Neural Network Accelerator with Cylindrical Bin Partitioning
A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS
Mobile display technologies: Past, present and future
A 75.6Gb/S 22-Bit Floating-Point Reconfigurable DSP Accelerator Embedding 2048×256-Point Complex FFT and 26K-Point 1-D Signal Processing
A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration
A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter
Silicon systems security and building a root of trust
A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping
A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers
A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring
A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter
A hybrid PLC-WiMAX based communication system for advanced metering infrastructure
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability
A wide-band divide-by-3 injection-locked frequency divider using tunable MOS resistor
Numercial investigation of the thermal fatigue issue in the next generation nuclear power plants
A 0.003-mm 2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface
A 5.76 Gb/s 79.7 pJ/b 128×32 Massive Deep-Learning Uplink MIMO Detector in 28nm CMOS Technology
Fast and economic generator output adjustment for improvement of transient stability ATC
14nm Broadwell Xeon® processor family: Design methodologies and optimizations
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling
1.55mW 2GHz ERBW 7b 800MS/s 3-stage Pipelined SAR ADC in 28nm CMOS using a Kickback-Cancelling 7T-Dynamic Residue Amplifier with only 16fF Input Capacitance
Task-Specific Low-Power Beamforming MIMO Receiver Using 2-Bit Analog-to-Digital Converters
1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller
A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links
A 65nm 376nA 0.4V linear classifier using time-based matrix-multiplying ADC with non-linearity aware training
A 97.1% Buck-Boost Battery Charger with a Constant Current Extension Technique for 2x Faster Battery Charging with Accurate Termination of Charging Process
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator
Distribution network reconfiguration using genetic algorithm and load flow
A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement
A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications
An 18-nW, 170°C Temperature Range, Voltage and Current Reference Circuit with Low Line Sensitivity
A Dual-Mode Ground-Referenced Signaling Transceiver with a 3-Tap Feed-Forward Equalizer for Memory Interfaces
A 15-mW 2.4-GHz IEEE 802.15.4 transmitter with a FIR-embedded phase modulator
A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS
Stable, Self-Biased and High-Gain Organic Amplifiers with Reduced Parameter Variation Effect
A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction
Condition health monitoring of offshore wind turbine based on wireless sensor network
A single monitor method for voltage sag source location using Hilbert Huang transform
A 2 nd order fully-passive noise-shaping SAR ADC with embedded passive gain
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO
Line inversion-based mobile TFT-LCD driver IC with accurate quadruple-gamma-curve correction
A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS
A THz signal source with integrated antenna for non-destructive testing in 28nm bulk CMOS
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity
A Power Efficient ECG Front-End with Input-Adaptive Gain Reaching 67.6-dB Dynamic Range
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer
A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS
A technique for in-band phase noise reduction in fractional-N frequency synthesizers
Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter
A 389TOPS/W, 1262fps at 1Meps Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation
A 1-V 3.1-ppm/°C 0.8-μW Bandgap Reference with Piecewise Exponential Curvature Compensation
A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW
A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control
An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier
A bipolar gain bridgeless set-up AC/DC converter with power factor correction
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects
A 76-Gbit/s 265-GHz CMOS Receiver
An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM
Multiple-poles multilevel diode-clamped inverter (M 2 DCI) topology for alternative multilevel converter
A 19.58-to-21.38-GHz Low-Power Quad-Core VCO with Compact 3 rd -Order Q-boost Inductors Achieving -191.8-dBc/Hz FoM and -205.4-dBc/Hz FoMA
Semiconductor Chip Design in a Legoland
A 772Mbit/s 8.81bit/nJ 90nm CMOS soft-input soft-output sphere decoder
A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applications
A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibration
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS
A 0.9V 0.022mm 2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique
A 130-to-170 GHz Reconfigurable Heterodyne/Homodyne Transceiver Achieving 20.5-dBm Psat for Emerging Integrated Wireless Access and Backhaul Networks
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge
A 400 × 112 CMOS LiDAR Sensor with Reconfigurable-Resolution Histogramming Time-to-Digital Converters and Sub-cm Depth Refining Filter
A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification
HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling
Low power cross-point memory architecture
A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration
Correlated Dual-Loop Sturdy MASH CT ΔΣ ADC with Indirect Signal Feedforward
An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS
Speed measurement of a general DC brushed motor based on sensorless method
A low-input-swing AC-DC voltage multiplier using Schottky diodes
A 40-nV/VHz 0.0145-mm 2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOS
Comparison of interconnection standards of renewable energy generation
A 7m-range, 4.3mW/Ch. Ultrasound ASIC with Universal Energy Recycling TX for All-Weather Metamorphic Robotic 3D Vision System
Reference Grid Performance Assessment Model for transmission company regulation
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics
Mixed integer programming formulation techniques and applications to Unit Commitment problem
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation
A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDC
Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor
Wireless Charging EEG Monitoring SoC with AI Algorithm-driven Electrical and Optogenetic Stimulation for Epilepsy Control
A Wearable Auto-Patient Adaptive ECG Processor for Shockable Cardiac Arrhythmia
A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD
A 360-456 MHz PLL frequency synthesizer with digitally controlled charge pump leakage calibration
Highly improved SNR differential sensing method using parallel operation signaling for touch screen application
A low power time-of-arrival ranging front end based on a 8-channel 2.2mW, 53ps single-shot-precision Time-to-Digital converter
A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm
A Transient-Enhanced Constant On-Time Buck Converter with Light-Load Efficiency Optimization
A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2 nd -order Noise-Shaping SAR ADC in 65nm CMOS
An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS
A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems
A 71-to-86GHz, 20.4dBm $\mathbf{P}_{\mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOS
A fast-transient quasi-V 2 switching buck regulator using AOT control
A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL
A 3.4-mW 54.24-Mbps burst-mode injection-locked CMOS FSK transmitter
An ultra-low power 169-nA 32.768-kHz fractional-N PLL
A single-inductor dual-input dual-output (SIDIDO) power management with sequential pulse-skip modulation for battery/PV hybrid systems
Research on the operating process of DC De-icer and its De-icing efficiency in China Southern Power Grid
An 18ms-latency wireless high quality codec SoC for full HD streaming
A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step
Future direction of power management in mobile devices
Investigation of VRB-ESS integrated with hybrid power system for building
A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI
Optimal reactive power dispatch by pseudo-gradient guided particle swarm optimization
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access
A high-band IR-UWB chipset for real-time duty-cycled communication and localization systems
Fuzzy embedded PI control algorithm and angle experiments of switched reluctance machine
KDA: Kyber and Dilithium Accelerator for CRYSTALS Suite of Post-Quantum Cryptography in Hybrid Multipath Delay Commutator Pipelined Architecture
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology
Forecasting model for the solar photovoltaics consumption in United States of America
A model predictive control equalization transmitter for asymmetric interfaces in 28nm FDSOI
A 4-channel 5.04 μW 0.325 mm 2 Orthogonal Sampling-Based Parallel Neural Recording System
A 5.2-GHz full-integrated RF front-end by T/R switch, LNA, and PA co-design with 3.2-dB NF and +25.9-dBm output power
A 69.3% Efficiency, 6.78-MHz Wireless Power Delivery System with 0X/1X Regulating Rectifier and Reconfigurable Power Amplifier
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System
Dedicated ICs for wearable body sound monitoring
A 1.3mW 10MHz-BW 71dB-SNDR Two-Step TDCAssisted Continuous-Time Noise-Shaping SAR ADC
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range
Experimental comparison of charging algorithms for a lithium-ion battery
A 10-Bit 1026-Channel Column Driver IC with Partially Segmented Piecewise Linear Digital-to-Analog Converters for Ultra-High-Definition TFT-LCDs with One Billion Color Display
A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface
A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM
A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination
A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector
A 56Gbps PAM-4 optical receiver front-end
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting
A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS
An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI
A 10kHz-BW 24.9μW 90.1dB SNDR Noise-Shaping SAR ADC With Complementary Parametric Amplifiers
A novel matrix converter based resonant dual active bridge for V2G applications
A 69μW Dual-Mode Electrochemical miR-21 Detection SoC with 3 rd -Harmonic Direct-Solution Technique
A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications
A Compact 1,257-Gbps/W Byte-Serial AES Accelerator for IoT Applications in 22 nm
An Output Capacitor-less Low-dropout Regulator using a Wide-range Single-stage Gain-boosted Error Amplifier and a Frequency-dependent Buffer with a Total Compensation Capacitance of 2.5 pF in 0.5 µm CMOS
A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS
An 8-mW 66-GHz Active Circulator with 40dB TX-RX Isolation in 65nm CMOS for Full-Duplex Radios
A 23.9 µW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF
Rotary coding for power reduction and S/N improvement in inductive-coupling data communication
Artificial bee colony algorithm for optimal design of power system stabilizer
IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023
A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization
A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System
A Piezoelectric Energy Harvesting Interface for Irregular High Voltage Input with Partial Electric Charge Extraction with 3.9× Extraction Improvement
A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking
A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems
Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning
Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS
Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVM
The modeling of partial discharge waveforms in power systems equipment
A 1.25pJ/bit 0.048mm 2 AES core with DPA resistance for IoT devices
A 92mW real-time traffic sign recognition system with robust light and dark adaptation
A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT
A 2.34μJ/scan acoustic power scalable charge-redistribution pMUT interface system with on-chip aberration compensation for portable ultrasonic applications
A 185-μW, ±2.5-ppm -40°C-80°C Analog TCXO With A Differential-Pair-Based Polynomial Temperature Compensation Technique
A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref
A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands
A 1.5fJ/conv-step 10b 100kS/s SAR ADC with gain-boosted dynamic comparator
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm 2 all-digital delay-locked loop in 65-nm CMOS
Bio-inspired semiconductors for early detection and therapy
Supercomputer Fugaku: Co-designed with application developers/researchers
A 762-pW 16.3-ps resolution digital pulse width modulator using zooming phase-interpolator
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network
An active guarding technique for substrate noise suppression on LC-tank oscillators
A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks
An overview of lithium-ion batteries for electric vehicles
A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array
A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process
A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector
A 2.56mm 2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS
A 7T-SRAM with data-write technique by capacitive coupling
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation
CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation
Calculation of lightning-induced voltages on overhead power lines using the RBF-FDTD method
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation
Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique
A 0.015-mm 2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs
287-GHz CMOS Transceiver Pixel Array in a QFN Package for Active Imaging
The coordination voltage management with distributed generation in the distribution network
A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads
Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS
Study on system voltage oscillation and voltage stability control
A DC-43.5 GHz CMOS Switched-Type Attenuator with Capacitive Compensation Technique
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer
A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application
A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application
A Compact Optical Image Stabilization Chip with Actuator Trackability Improvement Controller and Double Offset Cancel Hall Amplifier to Improve Camera Shake Correction
An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS
A 550-2260MHz self-adjustable clock generator in 28nm FDSOI
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H
A 66.6 FPS High Quality Gaussian Splats Rendering FPGA Processor with Reconfigurable Computation Architecture
Power sensitivity and algebraic technique for evaluation of penetration level of photovoltaic on DC link of VSC HVDC transmission
33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI
A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting
A Neural Network Accelerator With Integrated Feature Extraction Processor for a Freezing of Gait Detection System
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS
A Low Noise and Linearity Improvement CMOS Image Sensor for Surveillance Camera with Skew-Relaxation Local Multiply Circuit and On-Chip Testable Ramp Generator
A 28-nm 323 TOPS/mm 2 /b and 2007 TOPS/W/b Ternary Latch Based Sparsity-Aware CIM Macro With Double-Sampling Ternary ADC
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
A 10.4 mW electrical impedance tomography SoC for portable real-time lung ventilation monitoring system
A 2.79-mW 0.5%-THD CMOS current driver IC for portable electrical impedance tomography system
A 25-102GHz 2.81-5.64mW tunable divide-by-4 in 28nm CMOS
A W-Band Scalable 1 × 4 Phased-Array Transmitter Front-End with >15/17 dBm OP1dB/Psat in SiGe BiCMOS
A 0.2-0.6 V ring oscillator design using bootstrap technique
-17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boost
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS
An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current
A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator
An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS
An impedance modulated class-E polar amplifier in 90 nm CMOS
A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver
A 21Gb/s Duobinary Transceiver for GDDR interfaces with an Adaptive Equalizer
A 28nm 166.9 TOPS/W x Mb/mm 2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices
Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension