yusuke1997/dblp-id-title huggingface dataset:
Gate movement for timing improvement on row based Dual-VDD designs
Future SoC Design Challenges and Solutions (invited)
Comparative study and prediction modeling of photonic ring Network on Chip architectures
On N-Detect Pattern Set Optimization
Virtual logic netlist: Enabling efficient RTL analysis
Advances in wire routing
Implementation of Multipliers in FPGA Structures
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices
AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections
A case for 3D stacked analog circuits in high-speed sensing systems
Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops
Asymmetric aging of clock networks in power efficient designs
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits
Effect of NDD dosage on hot-carrier reliability in DMOS transistors
Variation-aware speed binning of multi-core processors
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals
On evaluating signal selection algorithms for post-silicon debug
How much is too much error? Analyzing the impact of approximate multipliers on DNNs
Electrical and thermal analysis for design exchange formats in three dimensional integrated circuits
H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators
Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security
Impact of geometry parameter on electromigration reliability in FCBGA package
Adder implementation in reconfigurable resistive switching crossbar
Package-chip co-design to increase flip-chip C4 reliability
A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation
A Novel Method Against Hardware Trojans in Approximate Circuits
Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array
Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors
Design of sub-90nm Circuits and Design Methodologies
Covgen: A framework for automatic extraction of functional coverage models
Machine Learning-Based Pruning Algorithm of Partitioning Techniques for Circuit Simulation
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids
Routing at compile time
Application of Formal Verification to Design Creation and Implementation
Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (invited)
Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method
Characterization of Fast, Accurate Leakage Power Models for IEEE P2416
A new voltage binning technique for yield improvement based on graph theory
Test challenges in embedded STT-MRAM arrays
Automated Shmoo data analysis: A machine learning approach
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan
MOS Modeling, Design Quality, and Modern Analog Design (Tutorial Abstract)
Multi-trap RTN parameter extraction based on Bayesian inference
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask
Device and Technology Challenges for Nanoscale CMOS
Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS
Domain Strategy and Coverage Metric for Validation
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design
A low power detection routing method for bufferless NoC
Automatic register banking for low-power clock trees
Plenary Speech 1P2: Bounding the Endless Verification Loop
A Communication-Centric Observability Selection for Post-Silicon System-on-Chip Integration Debug
Design and Test of Low Voltage CMOS Circuits
Applying the OpenMORE Assessment Program for IP Cores
Word-Level Multi-Fix Rectifiability of Finite Field Arithmetic Circuits
Design and evaluation of physical unclonable function for inorganic printed electronics
An End-to-end Multi-task Object Detection using Embedded GPU in Autonomous Driving
Theory of redundancy for logic circuits to maximize yield/area
DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems
Cycle-accurate Energy Measurement and High-Level Energy Characterization of FPGAs
Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement
Impact of C-elements in asynchronous circuits
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework
Model Extraction Attack against On-device Deep Learning with Power Side Channel
A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA
A Formal Verification Method of Scheduling in High-level Synthesis
SoC Trust Validation Using Assertion-Based Security Monitors
State encoding based NBTI optimization in finite state machines
Embedded Test Leads to Embedded Quality
UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications
Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminology
Controlled-Load Limited Switch Dynamic Logic Circuit
Trojan Assets and Attack Vectors in Processors
SPEED: Scalable and Predictable EnhancEments for Data Handling in Autonomous Systems
Current Calculation on VLSI Signal Interconnects
Efficient Self-Supervised Continual Learning with Progressive Task-Correlated Layer Freezing
SATConda: SAT to SAT-Hard Clause Translator
Quick On-Chip Self- and Mutual-Inductance Screen
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization
A physical model for tunable patch antennas
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test
Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments
An Improved AMG-based Method for Fast Power Grid Analysis
Computation of Soft Error Rates Considering Test Pattern Sequences
Signal domain based reachability analysis in RTL circuits
Exploratory study on circuit and architecture design of very high density diode-switch phase change memories
A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance
Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices
A case study on logic diagnosis for System-on-Chip
All-Optical Reconfigurable Activation Function Based on Saturable Absorption
Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-Variate Approximation
Cost Model Analysis of DFT Based Fault Tolerant SOC Designs
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
Tutorial II: Variability and Its Impact on Design
Fast Current Constraints Generation for Chip Safety
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns
An accurate current source model for CMOS based combinational logic cell
Efficient electro-thermal co-analysis on CPU+GPU heterogeneous architecture
Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's
An automated flow for design validation of switched mode power supply
Mathematical derivation, circuits design and clinical experiments of measuring blood flow volume (BFV) at arteriovenous fistula (AVF) of hemodialysis (HD) patients using a newly-developed photoplethysmography (PPG) sensor
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability
System-on-Chip: Embedded Test Strategies
A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology
Signal integrity analysis and optimization for 3D ICs
Low complexity cross parity codes for multiple and random bit error correction
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs
Comparison of variations in MOSFET versus CNFET in gigascale integrated systems
Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays
Preventing integrated circuit piracy via custom encoding of hardware instruction set
Modeling of PMOS NBTI Effect Considering Temperature Variation
Design methodology of variable latency adders with multistage function speculation
Virtual characterization for exhaustive DFM evaluation of logic cell libraries
Architecting for Physical Verification Performance and Scaling
Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes
Assertion clustering for compacted test sequence generation
Open-ALOE: An Analog Layout Automation Flow for the Open-Source Ecosystem
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs
A non-parametric approach to behavioral device modeling
Low Restoration-Energy Differential Spin Hall Effect MRAM for High-Speed Nonvolatile SRAM Application
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model
Ultra-low swing CMOS transceiver for 2.5-D integrated systems
Joint write policy and fault-tolerance mechanism selection for caches in DSM technologies: Energy-reliability trade-off
Confluence of AI/ML with EDA and Software Engineering
BIST-Guided ATPG
A hybrid RFID and CV system for item-level localization of stationary objects
Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes
Quality-driven methodology for demanding accelerator design
Dynamic NoC platform for varied application needs
PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted Data
The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design
Double Deep Q-Learning Based Irrigation and Chemigation Control
Flexible data allocation for scratch-pad memories to reduce NBTI effects
Design-for-Test Techniques for SoC Designs (Tutorial Abstract)
Power-aware testing in the Era of IoT
Application Specific Worst Case Corners Using Response Surfaces and Statistical Models
Modeling, design and verification platform using SystemC AMS
Design guidelines for embeded NoCs on FPGAs
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors
Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization"
Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software
Manufacturability
Multiple shift-vector importance sampling method using support vector machine and clustering for high-density DRAM designs
Reconfiguring the Mux-Based Arbiter PUF using FeFETs
Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study
Measuring within-die spatial variation profile through power supply current measurements
Wireless Systems-on-a-Chip Design
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits
Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming
Low power adaptive pipeline based on instruction isolation
Efficient Decryption Architecture for Classic McEliece
Technical Subcommittees
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost
Die-level leakage power analysis of FinFET circuits considering process variations
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization
Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior
Digitally programmable SRAM timing for nano-scale technologies
Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction
Watermarking of Quantum Circuits
Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning
Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraints
Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications
SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning
Reverse Engineering Word-Level Models from Look-Up Table Netlists
PETS: Power and energy estimation tool at system-level
An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing
Investigating Crosstalk in Sub-Threshold Circuits
IP Creation and Use What Roadblocks are Ahead or it is Just Clear and Bumpy Road?
How Do You Select A High Quality EDA Tool Flow?
Equivalence checking of scheduling in high-level synthesis
3D IC Packaging Utilizing a Metal Structure for Heat Reduction, Noise Shielding, and High Interconnect Density
Relocatable and resizable SRAM synthesis for via configurable structured ASIC
Digital PUF using intentional faults
Process variation aware crosstalk mitigation for DWDM based photonic NoC architectures
Transaction-based post-silicon debug of many-core System-on-Chips
DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family
Neural Network Partitioning for Fast Distributed Inference
Conference at a Glance
Fast power delivery network analyzer
Dynamic Test Compaction for Bridging Faults
Extending Moore's Law through Advances in Semiconductor Manufacturing Equipment
An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node
An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms
Design of a 10-bit TSMC 0.25um CMOS Digital to Analog Converter
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement
A novel robust signaling scheme for high-speed low-power communication over long wires
State of Hardware Fuzzing: Current Methods and the Potential of Machine Learning and Large Language Models
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis
DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
Analysis of very large resistive networks using low distortion embedding
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS
Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis
Leakage Current Modeling in PD SOI Circuits
Scan BIST Targeting Transition Faults Using a Markov Source
PVT variation impact on voltage island formation in MPSoC design
Multiplexed trace signal selection using non-trivial implication-based correlation
Electromigration-aware placement for 3D-ICs
SCPlace: A statistical slack-assignment based constructive placer
Does Aging Matter? The Curious Case of Fault Sensitivity Analysis
PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits
Employing dynamic body-bias for short circuit power reduction in SRAMs
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC
Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing
Optimizing the Yield of VLSI Circuits
System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC
Ultra-fast variability-aware optimization of mixed-signal designs using bootstrapped kriging
Early-stage determination of current-density criticality in interconnects
Noise-Aware Driver Modeling for Nanometer Technology
Suspicious timing error prediction with in-cycle clock gating
RARA: Dataflow Based Error Compensation Methods with Runtime Accuracy-Reconfigurable Adder
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks
Detection Limit for Intermediate Faults in Memristor Circuits
A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models
A High Performance SIMD Framework for Design Rule Checking on Sony??s PlayStation 2 Emotion Engine Platform
Integrated Implantable Electrode Array and Amplifier Design for Single-chip Wireless Neural Recordings
Decomposition-Based Watermarking of Quantum Circuits
Timing Yield Estimation from Static Timing Analysis
nvXNOR Design with Enhanced Store Capability for BNN Applications
Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness
A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths
Tutorial 1: Emerging Technologies for VLSI Design
Body bias driven design synthesis for optimum performance per area
Formal Verification of a Fully Automated Out-of-Plane Cell Injection System
Process variation tolerant 9T SRAM bitcell design
A PPA- and Security-Aware Physical Design Flow
Circuit-level delay modeling considering both TDDB and NBTI
TSV and DFT cost aware circuit partitioning for 3D-SOCs
eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application
Deep sub-100 nm Design Challenges
Crosstalk pessimism reduction with path base analysis
Language-Based High Level Transaction Extraction on On-chip Buses
Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator Framework
Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory Architecture for Deep Learning Acceleration
DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path
Aging-aware timing analysis considering combined effects of NBTI and PBTI
Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
The Practical Side of Quality
Tabu search based multiple voltage scheduling under both timing and resource constraints
Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design
Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools
Meeting Nanometer DPM Requirements Through DFT
CAP: Configurable resistive associative processor for near-data computing
Design and Evaluation of a Security Scheme for Sensor Networks
Brightening the Optical Flow through Posit Arithmetic
Variation-tolerant hierarchical voltage monitoring circuit for soft error detection
Spintronics-based Reconfigurable Ising Model Architecture
Two New Methods for Accurate Test Set Relaxation via Test Set Replacement
Accurate and Efficient Quantized Reservoir Computing System
Low power scheduling in high-level synthesis using dual-Vth library
TRGP: A Low-Cost Re-Configurable TRNG-PUF Architecture for IoT
FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-Precision Quantized Multiplication on Hardware Accelerators
Region Masking to Accelerate Video Processing on Neuromorphic Hardware
A low power clock network placement framework
SRAM voltage scaling for energy-efficient convolutional neural networks
Testing for Resistive Shorts in FPGA Interconnects
Thermal Trends in Emerging Technologies
Illuminati: A Simulation Framework for Modeling and Evaluating Photonic Neural Networks
Power Delivery Aware Floorplanning for Voltage Island Designs
Enlarging Reliable Pairs via Inter-Distance Offset for a PUF Entropy-Boosting Algorithm
Issues and Challenges in Ramp to Production
Double patterning-aware detailed routing with mask usage balancing
On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem
Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies
A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory
SVM-based real-time hardware Trojan detection for many-core platform
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs
An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
Integration Of Design For Manufacturability (DFM) Practices In Design Flows
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories
Performance entitlement by exploiting transistor's BTI recovery
Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation
Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures
Trends in Low Power Digital System-on-Chip Designs (invited)
Automated silicon debug data analysis techniques for a hardware data acquisition environment
The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange
A variation and energy aware ILP formulation for task scheduling in MPSoC
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies
Yield estimation and statistical design of memristor cross-point memory systems
A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT
Failures and verification solutions related to untimed paths in SOCs
Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)
Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective
A new approach for selecting inputs of logic functions during debug
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Peak Power Reduction in Low Power BIST
Fabrication Technologies for Three-Dimensional Integrated Circuits (invited)
A Low-Dissipation and Scalable GEMM Accelerator with Silicon Nitride Photonics
Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0
A Novel Clocking Strategy for Dynamic Circuits
Towards lightweight Identity-Based Encryption for the post-quantum-secure Internet of Things
High performance training of deep neural networks using pipelined hardware acceleration and distributed memory
Concurrent Fault Detection in Random Combinational Logic
Design Metrics to Achieve Design Quality
Energy-Efficient Persistently Secure Block-Based Differential Checkpointing for Energy Harvesting Devices
Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising Problems