yusuke1997/dblp-id-title huggingface dataset:
Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001
Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors
Unified address translation for memory-mapped SSDs with FlashMap
Dynamic MIPS rate stabilization in out-of-order processors
Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations
New cache designs for thwarting software cache-based side channel attacks
Exploiting Long-Distance Interactions and Tolerating Atom Loss in Neutral Atom Quantum Architectures
Dataflow Implementation of QR Decomposition on a Manycore
Profiling a warehouse-scale computer
QuickSAN: a storage area network for fast, distributed, solid state disks
Techniques for Efficient Processing in Runahead Execution Engines
The Architecture of Sperry Univac 1100 Series Systems
A Case for Hardware-Based Demand Paging
TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory
Cache decay: exploiting generational behavior to reduce cache leakage power
FAST: An FHE Accelerator for Scalable-parallelism with Tunable-bit
A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
Dynamic, Distributed Resource Configuration on SW-Banyans
APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures
A Self-Routing Benes Network
Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance
Fast Temporary Storage for Serial and Parallel Execution
Laconic deep learning inference acceleration
Iimplicitly-Multithreaded Processors
Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain
An Architecture with Comprehensive Facilities of Inter-Process Synchronization and Communication
Structured Machine Design: An Ongoing Experiement
A Design Study of a Shared Resource Computing System
An Algorithm and Architecture Co-design for Accelerating Smart Contracts in Blockchain
A Parallel Pipelined Relational Query Processor: An Architectural Overview
Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶
Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
There's always a bigger fish: a clarifying analysis of a machine-learning-assisted side-channel attack
Smart Memories: a modular reconfigurable architecture
Performance of a Message-Based Multiprocessor
Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials
Decentralized Parallel Algorithms for Matrix Computation
ANVIL: An In-Storage Accelerator for Name-Value Data Stores
SWIPER: Minimizing Fault-Tolerant Quantum Program Latency via Speculative Window Decoding
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
Architecting phase change memory as a scalable dram alternative
A data flow architecture with a paged memory system
Cache Write Policies and Performance
Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching
Improving the future by examining the past
An Advanced Tactical Computer Concept
A Fault Tolerant Multiprocessor Architecture for Real Time Control Applications
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures
FlexNeRFer: A Multi-Dataflow, Adaptive Sparsity-Aware Accelerator for On-Device NeRF Rendering
The Search for Energy-Efficient Building Blocks for the Data Center
Hardware-Software Interactions in SYMBOS-2R's Operating System
Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB
Is SC + ILP=RC?
Perfect Latin Squares and Parallel Array Access
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology
Interconnect design considerations for large NUCA caches
Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data
Bonsai: High-Performance Adaptive Merge Tree Sorting
An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks
A Bit-Slice Cache Controller
Bit mapping for balanced PCM cell programming
Storageless Value Prediction Using Prior Register Values
Warped-Slicer: Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming
Nyx: Virtualizing dataflow execution on shared FPGA platforms
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
EDAM: edit distance tolerant approximate matching content addressable memory
Improving Performance of Small On-Chip Instruction Caches
Bishop: Sparsified Bundling Spiking Transformers on Heterogeneous Cores with Error-constrained Pruning
Complexity/Performance Tradeoffs with Non-Blocking Loads
A New Approach to an Adaptive Computer - An Automatic Recovery Mechanism to Prevent the Occurance of Subtract Errors
Confidential Serverless Made Efficient with Plug-In Enclaves
Constant-Rate Entanglement Distillation for Fast Quantum Interconnects
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism
Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
Introduction to the workshop on trends in machine learning
MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment
Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998
A Multiple Stream Microprocessor Prototype System: AMP-1
Register Relocation: Flexible Contexts for Multithreading
3D-Stacked Memory Architectures for Multi-core Processors
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric
Compiler-Directed Whole-System Persistence
Exploring memory consistency for massively-threaded throughput-oriented processors
Execution Dependence Extension (EDE): ISA Support for Eliminating Fences
Scheduling of Tasks for Distributed Processors
An integrated hardware-software approach to flexible transactional memory
A Multi-User Data Flow Architecture
Missing the Memory Wall: The Case for Processor/Memory Integration
Towards a Taxonomy of Computer Architecture Based on the Machine Data Type View
DCS-ctrl: A Fast and Flexible Device-Control Mechanism for Device-Centric Server Architecture
Synthesis of application-specific heterogeneous multiprocessor systems
A Lightweight AES Implementation Against Bivariate First-Order DPA Attacks
Proceedings of the Workshop on Trends in Machine-Learning (and impact on computer architecture), TIML@ISCA 2017, Toronto, ON, Canada, June 25, 2017
TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software
On the Use of Small 2D Convolutions on GPUs
The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
Architectural Implementations of Abstract Data Type Implementation
Harmonia: balancing compute and memory power in high-performance GPUs
Adaptive memory-side last-level GPU caching
Supply Chain Aware Computer Architecture
WISQ: A Restartable Architecture Using Queues
Expected I-Cache Miss Rates via the Gap Model
IBM System/38 Support for Capability-Based Addressing
End-to-end performance forecasting: finding bottlenecks before they happen
Protozoa: adaptive granularity cache coherence
LINQits: big data on little clients
Vector Processors for Energy-Efficient Embedded Systems
Maximizing CNN Accelerator Efficiency Through Resource Partitioning
Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures
Hardware Support for Interprocess Communication
A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
Topology-Aware Virtualization over Inter-Core Connected Neural Processing Units
Checkpoint Repair for Out-of-order Execution Machines
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
A general class of processor interconnection strategies
Cryogenic computer architecture modeling with memory-side case studies
RISC assessment: A high-level language experiment
Variability in the execution of multimedia applications and implications for architecture
TIE: energy-efficient tensor train-based inference engine for deep neural network
A Methodology for Parallel Processing Design Tradeoffs
ParallAX: an architecture for real-time physics
Increasing ising machine capacity with multi-chip architectures
An In-Network Architecture for Accelerating Shared-Memory Multiprocessor Collectives
Fine-grain task aggregation and coordination on GPUs
Memory Bandwidth Limitations of Future Microprocessors
NDPBridge: Enabling Cross-Bank Coordination in Near-DRAM-Bank Processing Architectures
Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism
Meta's Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences
Flicker: a dynamically adaptive architecture for power limited multicore systems
SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing
Critical Issues in Mapping Neural Networks on Message-Passing Multicomputers
DAP - A Distributed Array Processor
Monsoon: An Explicit Token-Store Architecture
Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures
Selective Value Prediction
GPUs All Grown-Up: Fully Device-Driven SpMV Using GPU Work Graphs
Scalable Load and Store Processing in Latency Tolerant Processors
Intel® Software Guard Extensions (Intel® SGX) Support for Dynamic Memory Management Inside an Enclave
Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM
Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
Side-channel analysis of MAC-Keccak hardware implementations
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
SOFF: An OpenCL High-Level Synthesis Framework for FPGAs
Retrospective: What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha
Practical template-algebraic side channel attacks with extremely low data complexity
Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization
Fault Tolerance of a Class of Connecting Networks
Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs
Virtualizing power distribution in datacenters
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
Ginger: control independence using tag rewriting
Parallelizing an Index Generator for Desktop Search
Side-channel leakage and trace compression using normalized inter-class variance
LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation
An Adaptable Network for Functional Distributed Systems
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping
A Computer Architecture for Dynamic Finite Element Analysis
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Reducing world switches in virtualized environment with flexible cross-world calls
A case for bufferless routing in on-chip networks
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
RACOD: algorithm/hardware co-design for mobile robot path planning
Systematic Hardware Adaptation of Systolic Algorithms
Analytical Modeling and Architectural Modifications of a Dataflow Computer
Understanding data storage and ingestion for large-scale deep recommendation model training: industrial product
Power management of online data-intensive services
EDDIE: EM-Based Detection of Deviations in Program Execution
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine
Superconducting Computing with Alternating Logic Elements
Hardware atomicity for reliable software speculation
Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses
Confidence Estimation for Speculation Control
Express virtual channels: towards the ideal interconnection fabric
DynaSpAM: dynamic spatial architecture mapping using out of order instruction schedules
Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors
PARDIS: A programmable memory controller for the DDRx interfacing standards
Efficient invisible speculative execution through selective delay and value prediction
High-Speed Top-of-Stack Scheme for VLSI Processor: a Management Algorithm and Its Analysis
DS-TPU: Dynamical System for on-Device Lifelong Graph Learning with Nonlinear Node Interaction
Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC
Rerun: Exploiting Episodes for Lightweight Memory Race Recording
WiDGET: Wisconsin decoupled grid execution tiles
HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation
Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation
Modular Routing Design for Chiplet-Based Systems
The Effects of CPU: I/O Overlap on Computer System Configurations
Towards a Shared-Memory Massively Parallel Multiprocessor
A Course in Computer Structures
BOOM: Enabling mobile memory based low-power server DIMMs
Atomic Vector Operations on Chip Multiprocessors
Ensemble-level Power Management for Dense Blade Servers
Utility-based acceleration of multithreaded applications on asymmetric CMPs
A Critique of Multiprocessing von Neumann Style
A Configurable Cloud-Scale DNN Processor for Real-Time AI
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems
Proof of the Equivalent Realizability of a Time-Bound Arbiter and a Runt-Free Inertail Delay
Déjà View: Spatio-Temporal Compute Reuse for' Energy-Efficient 360° VR Video Streaming
DS-GL: Advancing Graph Learning via Harnessing Nature's Power within Scalable Dynamical Systems
Near Data Acceleration with Concurrent Host Access
Performance of a Collision-Free Local Bus Network Having Asynchronous Distributed Control
Cicero: Addressing Algorithmic and Architectural Bottlenecks in Neural Rendering by Radiance Warping and Memory Optimizations
Logic Simulation on Massively Parallel Architectures
Design Considerations for a Processing Server
Flex: High-Availability Datacenters With Zero Reserved Power
Error-Correcting Codes for Semiconductor Memories
Dynamic Function Exchanging Mechanism in Poly-Processor System
SecDir: a secure directory to defeat directory side-channel attacks
Parallelization of Particle Filter Algorithms
Self-Checking Alternating Logic: Sequential Circuit Design
CryoCore: A Fast and Dense Processor Architecture for Cryogenic Computing
The Design of a Multi-Micro-Computer System
Tagged Architecture: How Compelling Are its Advantages?
Retrospective: A Study of Branch Prediction Strategies
A Modeling Approach and Design Tool for Pipelined Central Processors
Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach
36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA
AnySP: anytime anywhere anyway signal processing
Retrospective: RISC I: A Reduced Instruction Set Computer
BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition
Understanding the backward slices of performance degrading instructions
Using a User-Level Memory Thread for Correlation Prefetching
Alternate Path μ-op Cache Prefetching
SoftVN: efficient memory protection via software-provided version numbers
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
SIGARCH Guidelines
DREAM: Enabling Low-Overhead Rowhammer Mitigation via Directed Refresh Management
DNA-based molecular architecture with spatially localized components
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems
WebCore: Architectural support for mobile Web browsing
Empirical Evaluation of the CRAY-T3D: A Compiler Perspective
Experimental Evaluation of On-Chip Microprocessor Cache Memories
Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves
Multiprocessor Cache Analysis Using ATUM
16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors
An Input Interface for Real-Time Digital Sound Generation System
DIRECT - A Multiprocessor Organization for Supporting Relational Data Base Management Systems
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture
ASAP: architecture support for asynchronous persistence
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Architectural Mechanisms to Support Sparse Vector Processing
Releasing efficient beta cores to market early
Qtenon: Towards Low-Latency Architecture Integration for Accelerating Hybrid Quantum-Classical Computing
Maximal Rate Pipelined Solutions to Recurrance Problems
An Architecture with Many Operand Registers to Efficiently Execute Block-Structured Languages
Temporal Streaming of Shared Memory
Joint Encryption and Error Correction Schemes
Data path issues in a highly concurrent machine
STARLET - A Computer Concept Based on Ordered Sets as Primitive Data Types
AMOS: enabling automatic mapping for tensor computations on spatial accelerators with hardware abstraction
A heterogeneous multiprocessor design and the distributed scheduling of its task group workload
Instruction Fetching: Coping with Code Bloat
Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache
Time squeezing for tiny devices
Picture Systems, PS, and The Design of a Channel-To-Channel Computer Interface
Stream-Dataflow Acceleration
Hardware sorter and its application to data base machine
Analysis of a Multiprocessor System with a Shared Bus
Bubble-flux: precise online QoS management for increased utilization in warehouse scale computers
Architectural Considerations for a Microprogrammable Emulating Engine Using Bitslices
A Pipelined Memory Architecture for High Throughput Network Processors
The Vector-Thread Architecture
Check-In: In-Storage Checkpointing for Key-Value Store System Leveraging Flash-Based SSDs
The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor
Viper: Virtual pipelines for enhanced reliability
The Design of Some Language Constructs for Horizontal Microprogramming
The heap/substitution concept - an implementation of functional operations on data structures for a reduction machine
Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems
ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems
Enabling Ahead Prediction with Practical Energy Constraints
DX100: Programmable Data Access Accelerator for Indirection
A Performance Study of Memory Consistency Models
Opportunistic computing in GPU architectures
Increasing Hardware Complexity - A Challenge to Computer Architecture Education
Think Fast: A Tensor Streaming Processor (TSP) for Accelerating Deep Learning Workloads
Learning-Based SMT Processor Resource Distribution via Hill-Climbing
Clank: Architectural Support for Intermittent Computation
Design of a Concurrent Computer for Solving Systems of Linear Equations
Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism
Optimal Pipelining in Supercomputers
Achieving predictable performance through better memory controller placement in many-core CMPs
Cambricon-Q: A Hybrid Architecture for Efficient Training
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
CODOMs: Protecting software with Code-centric memory Domains
Supporting Legacy Libraries on Non-Volatile Memory: A User-Transparent Approach
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product
Enabling Efficient Large Recommendation Model Training with Near CXL Memory Processing
Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer
The IBM z15 High Frequency Mainframe Branch Predictor Industrial Product
A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation
Exploiting Resonant Behavior to Reduce Inductive Noise
Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching
Predicting program phases and defending against side-channel attacks using hardware performance counters
Flumen: Dynamic Processing in the Photonic Interconnect
Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984
Energy Efficient Architecture for Graph Analytics Accelerators
Neo: Towards Efficient Fully Homomorphic Encryption Acceleration using Tensor Core
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching
Evaluation of an Analog Accelerator for Linear Algebra
Accelerating asynchronous programs through event sneak peek
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
Agile, efficient virtualization power management with low-latency server power states
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
An Approach to a Fault-Tolerant System Architecture
SoK: A Study of Using Hardware-assisted Isolated Execution Environments for Security
Regular CC-Banyan Networks
Implementing A Cache Consistency Protocol
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!
The TickerTAIP Parallel RAID Architecture
TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments
Retrospective: Architecture of a Massively Parallel Processor
A Hardware Laboratory for Computer Architecture Research
33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP
Forest: Access-aware GPU UVM Management
Low-Latency Message Communication Support for the AP1000
The Computer Aided Design of Processor Architectures
An Architecture of a Dataflow Single Chip Processor
Reducing memory reference energy with opportunistic virtual caching
The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation
Cache timing side-channel vulnerability checking with computation tree logic
R256: A Research Parallel Processor for Scientific Computation
A Unified Architectural Tradeoff Methodology
Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors
Generation and Analysis of Very Long Address Traces
A Kernel-independent, Pipelined Architecture for Real-Time 2-D Convolution
Automated Exploration of the Design Space for Register Transfer (RT) Systems
Comments on Capabilities, Limitations and Correctness of Petri Nets
The Sequoia Computer: A Fault-Tolerant Tightly-Coupled Multiprocessor Architecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
SnaPEA: Predictive Early Activation for Reducing Computation in Deep Convolutional Neural Networks