yusuke1997/dblp-id-title huggingface dataset:
10kV 4H-SiC IGBT Based on the Multi-floating-zone Junction Terminal Extension(MFZ-JTE) Structure
Design of An Asymmetrical Pseudo-Doherty Load-Modulated Balanced Amplifier with 15-dB Back-Off High Efficiency
Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator
A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS
Millimeter-Wave AlGaN/GaN MIS-HEMTs with Multiple T-Gate Technology
Lensfree on-chip digital holographic microscope with auto-focusing
Design and Fabrication of High Density 3D IPDs (Integrated Passive Devices) on Glass Substrate
Effect of conductive filament morphology on soft error of oxide based Resistive Random Access Memory
Handheld Wireless ECG Recording System Based on Printed Metal-Plate Electrodes for Personalized Healthcare
Large Suppression to Lateral Charge Migration (LCM) Related Error Bits in Charge-Trap TLC 3D NAND Flash
A 11.4-GHz Dual-Mode Multi-Modulus Divider in 65-nm CMOS
A High Power-Added-Efficiency Ku-band Frequency Doubler in 28-nm CMOS for Automotive Radar
High-Throughput Zipper Encoder for 800G Optical Communication System
A 154 FPS Efficient Single-frame Bundle Adjustment Accelerator for High Frame Rate Mobile Robots
Error Bits Recovering in 3D NAND Flash Memory: A Novel State-Shift Re-Program (SRP) Scheme
Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing
Thermal Fatigue Analysis of Microbumps in a 3D TSV Integration Device
A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS
A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm
Reconfigurable Buck-Boost Converter with Stacked Resonant Technology for Dual-Polarity Thermoelectric and Photovoltaic Energy Harvesting
Analysis and Optimization of Thermal Matching between Multi-core Connector and Encapsulated Aluminum Shell
A Configurable, Parallel and High-Performance NTT/INTT Accelerator for Post-Quantum Cryptosystems
Bits Mapping in Triple-level-cell (TLC) Charge-trap (CT) 3D NAND Flash Memory and its Applications to IoT Security
A Wideband Miniaturized dB-Linear Millimeter-Wave Power Detector in 40-nm CMOS
A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs
A 50-Gbaud Linear Burst-Mode Trans-Impedance Amplifier in 28 nm CMOS Technology
A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS
A 930MHz Low Phase Noise MEMS Oscillator
An improved approach of synthesizing of Cu-Ag core-shell nanoparticles
Reliability Design of a X-Band 2× 2 Tile-Type T/R Module under Thermal Shock and Random Vibration
Research and innovation in behavioral decision-making, image recognition, and action control of humanoid robot
Long Short-Term Memory Networks for Behavioral Modeling of A GaN Sequential Power Amplifier
Edge-Optimized AI Architecture: MRAM-based Near Memory Computing Core Balancing between Memory Capacity and Computation
A 40-nA Quiescent Current Buck Converter With ACC/AOT Dual-Mode Control and Fast-Transient Response for IoT Application
Fabrication of Y-cut LiNbO3 Single Crystalline Film and SAW Resonator on Flexible Polyimide Substrate
AppSRAM: Incremental Retraining Method to Compensate for SRAM Failure in Voltage-Scaling Embedded CNN System
An Energy-Efficient Logarithmic-Posit-Based In-SRAM Computing for Neural Network Acceleration
Graph Neural Network Assisted S-Parameter Inference and Control-Word Generation of Terahertz Reconfigurable Intelligent Surface
A 5.24nW-77.2dBm-Sensitivity Wake-Up Receiver with Global Digital Temperature Compensation
Measuring the fracture toughness of low-k thin films used in advanced packaging
A 4-8 GHz Fully-Differential Noise Canceling Low Noise Amplifier in 55-nm CMOS
A 10-bit SAR ADC with adaptive VCO-based comparator for sensor chip
Mobile Grabbing Robot with Target Detection Using Quadric Fitting
A Multiplying Delay-Locked Loop design with low jitter and high linearity
Superior Performances of Dynamic On-State Resistance in 1.9kV GaN-on-Sapphire HEMT
A 7-bit 1-GS/s Flash-SAR ADC with Time Interpolator in 45-nm SOI CMOS
A Power-Efficient $\boldsymbol{4}-\mathbf{V}_{\mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS
A Voltage Domain Code Division Multiplex Based Analog Front End For Energy-Efficient Multi-channel Bio-potential Acquisition
A V-band Power Amplifier for Satellite Communications in 40-nm CMOS
A calibration-free multi-phase sampling Type-II PLL
A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping
A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers
A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects
A 40nm 5-16Tops/W@INT8 eFlash In-Memory Computing SoC Chip with Noise Suppression and Compensation Techniques to Improve the Accuracy
Dynamically Reconfigurable Memory Address Mapping for General-Purpose Graphics Processing Unit
A 1.2 ppm/°C TC, 0.094% Inaccuracy 3-18 V Supply-Range Bandgap Reference with Self-Compensation
CongestionNet: VLSI Congestion Prediction Model Using sFCN with MixConv Layers
Highly Integrated and High Efficiency S-Band Quasi-MMIC Power Amplifier
Optical Phased Array with Reduced Phase Tuning Resolution
Maximum Channel Temperature Estimation for GaN HEMT transistors with n-fingers
A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process
Novel Selective Area Recessed Regrowth-free Ohmic Contacts to High Al-content Barrier
An Analytical Model for doping effect in charge-plasma-based TFET
A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects
A 0.8-V-VIN 3.76-nW 23.1-ppm/°C Low Dropout Regulator Based on Flipped Voltage Follower with Embedded CMOS Voltage Reference
A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization
A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm
Simulation Analysis of Mechanical Response of Wire Bonding in SiP under Thermal-mechanical-electrical Coupling Load
Hardware Based RISC-V Instruction Set Randomization
Self-Tracking Zero-Current Detection Based on Switching Node Ringing for High-Current Buck Converters
Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient
A Reconfigurable High-Precision and Energy-Efficient Circuit Design of Sigmoid, Tanh and Softmax Activation Functions
A DLL-Based Offset Calibration Loop Technology for Wake-Up Receivers
A 120nW, 121 kHz, -20~100°C CMOS Relaxation Oscillator with Digital Current Comparator and On-Chip Voltage and Current Reference
A Robust and Efficiency-Improving Design for Single-Stage Multiple-Output Receiver of Wireless Power Transfer System
An Asynchronous Convolution Process Engine forVGG-16 Neural Network
A Fast and Efficient FPGA-based Level Set Hardware Accelerator for Image Segmentation
Invited Paper: Design of an RRAM In-Memory Computing Scheme for Target Tracking Applications
A Simultaneous Wireless Power and Uplink Data Transfer System with Ultra-Low Crosstalk between the Power and Data Link
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis
An Energy-Efficient Gain-Cell Embedded DRAM Design with Weight Encoding for CNN Applications
A 4x16 Arrayed Current Sensing Front-End Chip for DNA Sequencing
An FPGA-based QDI Asynchronous Circuits Design Methodology
MIV Fault Modeling Method Based on Finite Element Analysis
Analytical Delay Model in Near-Threshold Domain Considering Transition Time
Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming
Efficient Hardware Platform Architecture for High-Precision Stereo Vision Processing
NORP: A Compact Neuromorphic Olfactory Recognition Processor With On-Chip Hybrid Learning
A 405ps/20% Delay Range, 7.4mW/ns BPF-Based Delay Cell with ISI Mitigation for 7.5-8.5GHz IR-UWB Beamforming Receivers
Randomly-Accessible Active Pixel Sensor with Wide Dynamic Range and Reduced Fixed Pattern Noise
A 92.9dB-SNDR 178.2dB-FoMs SAR ADC with kT/C noise cancellation and FIA
High-speed Memristive Walsh-Hadamard Transform for Image Compression
IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023
BISHENG: A 49.38PPM Flexible Multi-Function Printer SoC in 28nm CMOS
LIPFD-NPU: Low-overhead Instruction-driven Permanent Fault Detection for Neural Processing Unit
A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS
Large On/Off and Rectification Ratios, Self-Compliance, High-Uniformity in Pt/Al2O3/TaOx/Ta Self-Rectifying Memristors
A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower
High-Gain PFD/Charge Pump with Gain Proportional to Slew Rate of Up/Down Signals
Low Complexity ECG Biometric Authentication for IoT Edge Devices
A 1.2-mA Fast-Charge Input Buffer with CLS for 4-MS/s SC Oversampling ADC Achieving +1-2.5-ppm/FSR INL
Sufficient Hydroxylation Surface-Activation for Low-Temperature Glass/Glass Direct Bonding
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process
Implementation of Polynomial Fitted Poly-Harmonic Distortion Model with Frequency Defined Device
An Accurate Deep Learning-Based Thermal Reconstruction Technique for Microprocessors Using Embedded Sensors
Design Technology Co-Optimization for Memristor Self-Write Termination Circuits
Two-bit multi-level spin orbit torque MRAM with the fully one-step write operation
Implementation of CNN Heterogeneous Scheme Based on Domestic FPGA with RISC-V Soft Core CPU
A Non-Local Means Denoising Co-Processor with Data Reuse Scheme and Dual-Clock Domain for High Resolution Image Sensor
A high throughput spatially coupled low density generator matrix coding system
A Tunable Monopole Antenna for 5G Communication Applications
Memristor-based Digital Circuits for Realizing the Pavlov's Associative Neural Network
Energy-Efficient ReRAM-Based High-Precision Discrete Fourier Transform for Image Reconstruction
A CMOS Dual Band Low-Loss High-Isolation Switch for 5G New Radio
22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications
A Computing In Memory Scheme Using Unipolar Switching SOT-MRAM
Anomalous NMOSFET hot carrier degradation on DRAM
An AOT Buck Converter with Adaptive TON Extender Achieving 2.5µs Settling Time in 4A Load Transient
Design of a High Jitter Harmonic Injected Ring Oscillator for Entropy Sources
Accelerating Atrous Convolution with Fetch-and-Jump Architecture for Activation Positioning
An Area-Saving Balun for Multiband IoT Transmitter
Modeling of Hot Carrier Injection on Gate-Induced Drain Leakage in PDSOI nMOSFET
A 0.65μW 70nV/rtHz capacitively-coupled chopper instrumentation amplifier for bio-potential sensing in 28-nm CMOS
A Time Domain Analytical Model for Lossy Transmission Lines
Forming-free, Uniform, and Multi-level Resistive Switching in W/AlOxNy/Al2O3/Pt Memristor by Nitrogen Annealing Strategy
Design and Packaging of a W Band CMOS Power Amplifier
A Wide Dynamic Range Burst Mode Transimpedance Amplifier in BiCMOS Technology
A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers
Discrete-Time MASH Delta-Sigma Modulator with an IIR-based Self-Coupling
A Novel Concept of using Double Threshold Voltage Coupling to Improve the linearity of AlGaN/GaN HEMTs for millimeter-wave applications
An IMPLY-based Memristive Multiplier for Computing-in-Memory Systems with Weight-Stationary CNN Acceleration
A Lightweight Magnetic Strong Physical Unclonable Function
A DC-4GHz High Linearity Attenuator with Negative Temperature Coefficient
Low-Power Inductor-Less Optical Receiver for 50G PON in 28nm CMOS
A Novel Fold-Back Current Limiting Protection used in Sub-threshold LDO for Wireless Sensor Applications
A 480W 40-to-60VIN Quadrangle Controlled Four-Switch Buck-Boost Converter with Zero-Freewheeling and Reverse Inductor Current Supply Techniques Achieving 99% Peak Efficiency
Design of 77GHz Automotive Radar Antenna Based on FOWLP
Bonding Process Measurement System Analysis Based on Characteristic Parameter Simulation
Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier
A Ka-band Up-Conversion Mixer in 65-nm CMOS
A High Power Supply Rejection and Low Noise Low-Dropout Regulator for Voltage Controlled Oscillator
90-94GHz power amplifier based on planar space synthesis network
A Low-noise CTIA-based Non-contact PPG Sensor Analog Front End with Chopping and RDAC Compensation Techniques
Design of Improved KY Converter with Low Power ZCD Circuit for Wide Load Current Application
A Full-duplex Transceiver with Integrated Active Quasi-circulator Achieving Self-interference RF Cancellation over Wide Bandwidth
A 2.69 ppm/°C Bandgap Reference with 42 ppm/V Line Sensitivity for Battery Management System
Characteristics of A Novel Quaternary Tunneling Field-Effect Transistor for Low Power Applicaitons
MSeg-SLAM: A Semantic Visual SLAM System for Dynamic Scenes
Experiments and Hygrothermal Stress Analysis for a QFN Package
A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS
A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction
A Ka-Band CMOS Programmable Gain Amplifier with 15 dB Gain Tuning Range for Phased Arrays
Modeling the Resistance Variation of Heterogeneous Integrated Interconnect Structures under Electrical Stress
Multiple-Transmission Zeros Bandstop Filter Based on SAW Resonators and Lumped Elements
Real Time ECG Classification System Based on DWT and SVM
A circuit-algorithm codesign method to reduce the accuracy drop of RRAM based computing-in-memory chip
TEDOP: A Tiny Event-Driven Neural Network Hardware Core Enabling On-Chip Spike-Driven Synaptic Plasticity
Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology
Truncation Error Compensation Technique with Auxiliary Noise Shaping Filter in CT DSM
A Dual-Channel Switching-Linear Series-Connected Hybrid Dynamic Power Supply with Dual-Supply LDOs for Thermo-Optical Tuning
An FPGA-Based Low-Power Mobile-NetV2 Accelerator
A Continuous-Time Readout IC with 0.12 aF/√Hz for Capacitive Inertial Sensors
Robot navigation based on pseudo-binocular stereo vision and linear fitting
Moiré-Based Nanoprecision Bonding Alignment System for Hybrid Integration
Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing
2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020, Nanjing, China, November 23-25, 2020
A High-Speed Parallel FPGA Implementation of Harris Corner Detection
A 10-Mbps 119.2-pJ/bit Software Defined Body Channel Transceiver Employing a CCII-based PGA and a 2.5-bit/cycle ADC in 180-nm CMOS
Dynamic Sensor Arrays Based on Solution-Processed Metal Oxide Semiconductor Thin-Film Transistors
A Fast Bioimpedance Measurement Chip Design Using Dynamic Current
A Fully-Connected and Area-Efficient Ising Model Annealing Accelerator for Combinatorial Optimization Problems
An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC
Invited Paper: Low-Temperature SiO2/SiO2 Wafer Direct Bonding by N2 Plasma Activation
Cooperative surface-activation strategy for low-temperature Cu/SiO2 hybrid bonding
A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS
Floorplanning and Power/Ground Network Design for A Programmable Vision Chip
CRC-Aided Belief Propagation Polar Decoding Scheme for NB-loT Systems
Design of a X-Band 2×2 Phased-Array Transceiver Module Using Chiplet Method
SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer
An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method
A 63dB Gain Range with 0.4dB Gain Error dB-Linear Programmable Gain Amplifier Using Cell-Based Technique
All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations
An Accurate Analytical Model for Small Signal Behavior of MOSFET in Terahertz Applications
A 3μm Pixel Device for Peak Power Mitigation of Global-Shutter Indirect Time of Flight Image Sensor
A 1 st -order noise shaping SAR ADC with dual-capacitor merge-and-split switching scheme for sensor chip
L-Band 10-kW AlGaN/GaN HEMT with operating voltage of 100V
A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS
Design of Approximate Complex Constant Multiplier for Fast Fourier Transform in 28nm CMOS
Design and Development for CIS-WLCSP Using Vertical TSV Technology
A 5.72-μW, 1.02-MHz, -40~125°C, 1μs-Startup Time Relaxation Oscillation with Fully-on-Chip Voltage Reference and LDO Regulator
A CGP-based Efficient Approximate Multiplier with Error Compensation
Hot Carrier Injection Induced Degradation of 14 nm FinFET under High Source-Drain Voltage Bias
Efficient AVS3 Intra Prediction Hardware Design for Real-time Applications
A Highly Linear Multi-Clock Combining Phase Interpolator Insensitive to Interpolation Error
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output
A 64-GBaud 64-QAM Optical Coherent Transmitter with Monolithically Integrated Driver and I/Q Modulator in 45-nm SOI CMOS
6G Technologies - Opportunities and Challenges
A 109.2dB-Dynamic-Range Fully Dynamic Dual-Mode Adjustable Gain Resistive Sensor Interface Circuit
A 96% Peak Efficiency Off-chip Capacitor Free Dimmable Hysteresis Current Control LED Driver
INVITED PAPER: A 4.5-5.4GHz Digital Bang-Bang PLL for Cryogenic Applications
A Wide-Load-Range High-PSR Capless Low-Dropout Regulator with Adaptive Supply-Ripple Cancellation
A protection chip for three lithium cells
A Fully Integrated High-Efficiency All-NMOS Charge Pump for Wide Input Range Ultra-Low Dropout Regulator
Mixed-dimensional Integration for Tetrachromatic Optoelectronic Synaptic Devices Based on 2D/3D WSe2-GaN
A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations
A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology
A 14.39ppm/kPa Stress Sensor with Low Temperature-drift and High Linearity for turbulence Stress
A Broadband 20W GaN High Power Amplifier for Ku-band satellite communication
A 1.65 mW 2.8 GHz Dual-Loops Class-C VCO Achieving 189 dBc/Hz FoM
Design of basic block of neural signal detection chip
A High-Density Large-Ratio Fuse Based Oxide Devices for One-time-programmable Memory Applications
A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS
ROPY-SLAM: a Heterogeneous CPU-FPGA System for Simultaneous Localization and Mapping
First Demonstration of High PAE Performance Using InGaN Channel HEMT for 5G RF Applications
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing
A 2.79 μVrms Noise, 3.6 ppm/°C TC Bandgap Reference for Portable Biopotential Signal Monitoring Systems
A 16.5 mW 4.0 GHz Bandwidth VGA Based on Capacitance Neutralization Technique in 65 nm CMOS
A 1.2-μA SIMO DC-DC Converter with 0.04-mV/mA Cross Regulation under Simultaneous Multi-Channel Loading Transition
A Third-order Sigma-delta Frequency-to-digital Converter Based on Reset Counter and PLL
IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture
An 800MS/s Continuous-Time Pipeline ADC with Switchable FLASH and RDAC for Background Calibration
A Fast Response Digital Low-Dropout Regulator Based on Enhanced Analog Assisted Loop
SiC Trench MOSFET with N-base Super Barrier Rectifier Embedded for Optimizing Reverse Characteristic
The effect of ultrasonic turn-on sequence for dual ultrasonicassisted soldering
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning
A 2GS/s 12bit Time-Interleaved Pipelined ADC in 40nm CMOS
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs
INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS
A 4 nW, -77 dBm Sensitivity Wake-up Receiver with Differential Gate-biased Envelope Detector
A New Method to Extract Mobility Degradation and Parasitic Series Resistance of Nano-scaled MOSFETs
An Index-free Coding Compression Mechanism for Vision Transformers
A Q-Band Low-Noise Amplifier in 40-nm CMOS for Q/V-band satellite communications
A High-PSR High-Precision Fast-Transient-Response Capacitor-Free LDO for LiDAR Receiver SoC
Miniaturized Millimeter-Wave On-Chip Resonator Design in Silicon Technology
Artificial Neural Network based Model for Power GaN HEMTs down to 4.2K
Trends in Optoelectronic IC for Recent Optical Module and Photonics Integration
A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme
Design of a Wireless Compact Implantable Electrochemical Biosensor System for Health Monitoring Application
Microfluidic bioparticle separation and detection system based on standing surface acoustic wave and lensless imaging
A 130-GBaud 2: 1 Analog Multiplexer in 130-nm SiGe BiCMOS
A PVT-Insensitive Ultra-Low Voltage Wakeup Timer With a Capacitance Multiplier Based Hybrid Reconfigurable FLL
FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs
Low-temperature direct and indirect bonding using plasma activation for 3D integration
A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution
Cache-Like Dual-Port SOT-MRAM with Read-while-Write Access Strategy
BaFe12O19 based Ferroelectric Memristor for Applications of True Random Number Generator
Direct Cu-polyimide Bonding Achieved by Surface Activation and Pt-catalyzed Formic Acid Atmosphere
A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error
Design for Enhancing the Performance of Memristive Convolution Neural Network
A Monolithic Integrated E-Mode GaN 48V-to-1V DC-DC Buck Converter with PWM Control
An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response
A Dual-Loop Spread-Spectrum Clock Generator with Accurate Spread Ratio
A Power-Efficient Specific Emitter Identification Hardware Accelerator With SNR-Aware Adaptive Precision Reconfiguration
A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS
An Area-Efficient Ising Machine based on Parallel Stochastic Cellular Automata Tempering
Characterization and Modeling of Trapping Effects in GaAs Enhanced HEMT under High Input Dynamic Range
Design of a fast capacitance sensing circuit for 16× 16 sized sensor array
An FPGA-Based Efficient NTT Accelerator for Post-Quantum Cryptography CRYSTALS-Kyber
A High Voltage Bootstrapped Switch Based SAR ADC for Battery Management System
Cyclical Progress in Design and Technology
Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density
A 77-GHz 1.5-mW Down-Conversion Mixer Using Active Loads Technique in 40-nm CMOS for Automotive Radar Application
A 150-170GHz 5-Bit Vector-Modulated Phase Shifter Based on X-type Phase Inverter Technique
Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector
High-PSR and fast-transient LDO regulator with nested adaptive FVF structure
A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC
A novel high quantum efficiency SiGe Phototransistor detector
A W-Band Low-Noise Amplifier Using Gm-Boosting Technique with Weak Coupling
A 6.9-17.0 GHz Low-noise Amplifier in 65nm CMOS
A High PSR and Fast Transient Response Output-Capacitorless LDO using Gm-Boosting and Capacitive Bulk-Driven Feed-Forward Technique in 22nm CMOS
PPBAM: A Preprocessing-based Power-Efficient Approximate Multiplier Design for CNN