yusuke1997/dblp-id-title huggingface dataset:
Implementing Reconfigurable Datapaths in FPGAs for Adaptive Filter Design
Balancing Logic Utilization and Area Efficiency in FPGAs
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
High performance architecture for object detection in streamed videos
Multi-module Hashing System for SHA-3 & FPGA Integration
FPGA-Based Boundary-Scan Bist
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
A Placement Algorithm for FPGA Designs with Multiple I/O Standards
THOR - The hardware onion router
Rapid design exploration framework for application-aware customization of soft core processors
Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays
MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration
Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing
Configuration Caching and Swapping
Inter-procedural resource sharing in High Level Synthesis through function proxies
Ray Tracing Hardware System Using Plane-Sphere Intersections
Implementation of Elliptic Curve Cryptosystems over GF(2 n ) in Optimal Normal Basis on a Reconfigurable Computer
Patra: Parallel tree-reweighted message passing architecture
An ASIC perspective on FPGA optimizations
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Case Study of a Functional Genomics Application
Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2 m )
From Quartus to VPR: Converting HDL to BLIF with the Titan flow
Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures
sFPGA2 - A scalable GALS FPGA architecture and design methodology
A Flexible Power Model for FPGAs
Weasel: A platform-independent streaming-optimized SATA controller
Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices
A Framework for Developing Parameterised FPGA Libraries
Mapping logic to reconfigurable FPGA routing
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Automatic mapping of algorithms onto multiple FPGA-SRAM modules
PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system
A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2
FPL Demo: Runtime Stream Processing with Resource-Elastic Pipelines on FPGAs
A-U3D: A Unified 2D/3D CNN Accelerator on the Versal Platform for Disparity Estimation
GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization
A Routing Architecture for Mapping Dataflow Graphs at Run-Time
Cooperative multithreading in dynamically reconfigurable systems
An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping
General Purpose Prototyping Platform for Data-Processor Research and Development
Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture
A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip
QPF: Efficient Quadratic Placement for FPGAs
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
Application-specific reconfigurable processors
MARC: A Macintosh NUBUS-Expansion Board Based Reconfigurable Test System for Validating Communication Systems
Finite Field Division Implementation
IPP Watermarking Technique for IP Core Protection on FPL Devices
Limitations of incremental signal-tracing for FPGA debug
Precise Pointer Analysis in High-Level Synthesis
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA
The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead
Task-Parallel Programming of Reconfigurable Systems
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip
Time Predictable CPU and DMA Shared Memory Access
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs
Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)
Statechart-Based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor
How Fast Is Rapid FPGA-based Prototyping: Lessons and Challenges from the Digital TV Design Prototyping Project
Memory Virtualization for Multithreaded Reconfigurable Hardware
Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems
Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration
Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores
Hardware-accelerated regular expression matching for high-throughput text analytics
Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor
Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibrium
Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration
Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs
HCM: An abstraction layer for seamless programming of DPR FPGA
A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications
A highly-efficient and green data flow engine for solving euler atmospheric equations
Pattern-based FPGA logic block and clustering algorithm
Chaotic architectures for secure free-space optical communication
Using Hard Macros to Reduce FPGA Compilation Time
Development of a Telephone Answering Machine in a Lab - FPGAs in Education
Dynamically Reconfigurable Vision-Chip Architecture
Acceleration of Multi-agent Simulation on FPGAs
Using Reconfigurable Hardware to Speed up Product Development and Performance
A Mapping Methodology for Code Trees onto LUT-Based FPGAs
Reconfigurable Hardware SAT Solvers: A Survey of Systems
Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications
Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS
Pipelining computing stages in configurable multicore architectures
MSDF-SGD: Most-Significant Digit-First Stochastic Gradient Descent for Arbitrary-Precision Training
20Gbps C-Based Complex Event Processing
Applying Partial Reconfiguration to Networks-On-Chips
A Dynamically-Reconfigurable Phased Array Radar Processing System
A Smart Network Interface Approach for Distributed Applications on Xilinx Zynq SoCs
NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs
Hardware Implementations of Real-Time Reconfigurable WSAT Variants
Co-ViSu: a Video Super-Resolution Accelerator Exploiting Codec Information Reuse
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits
Prototype Generation of Application-Specific Embedded Controllers for Microsystems
Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform
An Experimental Programmable Environment for Prototyping Digital Circuits
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
Preallocating Resources for Distributed Memory Based FPGA Debug
Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications
FPGA acceleration of the scoring process of X!TANDEM for protein identification
A High-Performance Routing Engine for Large-Scale FPGAs
An Emulation Model for Sequential ATPG-Based Bounded Model Checking
An Approach to Real-Time Visualization of PIV Method with FPGA
Novel FPGA based Haar classifier face detection algorithm acceleration
Accelerated FPGA repair through shifted scrubbing
A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation
Generic Low-Latency NoC Router Architecture for FPGA Computing Systems
Modeling and Exploration of Elastic CGRAs
Reduction calculator in an FPGA based switching Hub for high performance clusters
FPGA PLB Evaluation using Quantified Boolean Satisfiability
Serial and parallel interleaved modular multipliers on FPGA platform
A Layer Model for Systematically Designing Dynamically Reconfigurable Systems
Architectures for SLAM and Augmented Reality Computing
FPGA-Accelerated Reconstruction of Gene Regulatory Networks
A Compiler Intermediate Representation for Reconfigurable Fabrics
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions
Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry
FPGA Based Reconfigurable Architecture for a Compact Vision System
Array Synthesis in SystemC Hardware Compilation
Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware
"All programmable FPGA, providing hardware efficiency to software programmers"
Implementing Graphics Shaders Using FPGAs
A Survey on FPGA Virtualization
Custom instructions with local memory elements without expensive DMA transfers
Lightweight reconfiguration security services for AXI-based MPSoCs
Placement Strategies for 2.5D FPGA Fabric Architectures
A Dual Cache for Performance and Energy Aware Reconfigurable HW
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
Dataflow acceleration of Krylov subspace sparse banded problems
Programmable Logic Has More Computational Power than Fixed Logic
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey
Latch-Based Performance Optimization for FPGAs
Dynamic branch prediction for high-level synthesis
Combating process variation on FPGAS with a precise at-speed delay measurement method
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Heterogeneity Exploration for Multiple 2D Filter Designs
Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach
Power-Driven Design Partitioning
Customized Reconfigurable Interconnection Networks for multiple application SOCS
FPGA-accelerated sliding window classifier with structured features
An FPGA sliding window-based architecture harris corner detector
Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis
Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process
A Parallel FFT Architecture for FPGAs
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing
DO-GPU: Domain Optimizable Soft GPUs
Leveraging Reconfigurability in the Design Process
Dynamically Reconfigurable Cores
SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform
Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition
FPGA-Based Discrete Wavelet Transforms System
Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs
Raising the abstraction level of HDL for control-dominant applications
Building Custom FIR Filters Using System Generator
Demonstrating custom SIMD instruction development for a RISC-V softcore
FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source
Application Partitioning on FPGA Clusters: Inference over Decision Tree Ensembles
A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors
Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data
Shadow And-Inverter Cones
A New FPGA Architecture for Word-Oriented Datapaths
Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers
Aging effects in FPGAs: an experimental analysis
Efficient mapping of mathematical expressions into DSP blocks
Dynamic reconfiguration management based on a distributed object model
Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics
FPGA based Rekeying for cryptographic key management in Storage Area Network
Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings
Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign
Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems
An FPGA Solver for Large SAT Problems
Placement of Linear Arrays
Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases
Effects of I/O routing through column interfaces in embedded FPGA fabrics
A Multi-Context Pipelined Array for Embedded Systems
SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA
Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures
EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs
Interfacing Hardware and Software
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices
Virtualization on the Tartan Reconfigurable Architecture
An Execution Model for Hardware/Software Compilation and its System-Level Realization
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view
FABulous Demo: Open Source FPGA on Sky130
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes
BitBlender: Scalable Bloom Filter Acceleration on FPGAs with Dynamic Scheduling
Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs
NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping
Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics
Enhancements to FPGA design methodology using streaming
Automatc identification of swappable logic units in XC6200 circuitry
FPGA Development Tools: Keeping Pace with Design Complexity
A Dynamic Routing Algorithm for a Bio-inspired Reconfigurable Circuit
Combining Serialisation and Reconfiguration for FPGA Designs
High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA
A Highly-Portable True Random Number Generator Based on Coherent Sampling
Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations
Significant papers from the first 25 years of the FPL conference
Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA
An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization
Snort Offloader: A Reconfigurable Hardware NIDS Filter
Analysis of Performance Variation in 16nm FinFET FPGA Devices
Parallel CRC Computation in FPGAs
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs
A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution
Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration
High Speed Homology Search Using Run-Time Reconfiguration
Reconfigurable Hardware - A Study in Codesign
Improving Timing-Driven FPGA Packing With Physical Information
Accelerating the Merge Phase of Sort-Merge Join
Real-time corner and polygon detection system on FPGA
A reconfigurable accelerator for quantum computations
Educational Use of Field Programmable Gate Arrays
Self Controlling Dynamic Reconfiguration: A Case Study
FPGAs for High Accuracy Clock Synchronization over Ethernet Networks
Portable Pipeline Synthesis for FCCMs
A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming
Solving Satisfiability Problems on FPGAs
Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms
Exploring the potential of reconfigurable platforms for order book update
Area-Efficient Implementation of a Pulse-Mode Neuron Model
Modulo SDC scheduling with recurrence minimization in high-level synthesis
Discrete Event Simulation of Molecular Dynamics with Configurable Logic
Multitasking on FPGA Coprocessors
Real-Time Medical Diagnosis on a Multiple FPGA-based System
Parallel RRT∗ architecture design for motion planning
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS
Maestro-Link: A High Performance Interconnect for PC Cluster
A High-Performance FPGA Accelerator for CUR Decomposition
A run time interpretation approach for creating custom accelerators
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits
FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method
23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System
Instruction-Level Parallelism for Reconfigurable Computing
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine
Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA
Test Standard Serves Dual Role as On-Board Programming Solution
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect
Low Power Coarse-Grained Reconfigurable Instruction Set Processor
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation
FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges
Towards efficient discrete Gaussian sampling for lattice-based cryptography
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard
A Real-Time Stereo Vision System with FPGA
FPGA acceleration of multilevel ORB feature extraction for computer vision
A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device
Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
Source-level debugging for FPGA high-level synthesis
FPGA Acceleration of the Phylogenetic Parsimony Kernel?
Titan: Enabling large and complex benchmarks in academic CAD
An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm
A Survey of Reconfigurable Computing Architectures
Multiple Restricted Multiplication
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation
A-B Nodes Classification for Power Estimation
A high performance alternating projections image demosaicing hardware
A Fast FPGA Implementation of a General Purpose Neuron
Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation
Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique
Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3
Data protection using recursive inverse function
Reconfigurable Systems in Education
An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm
OSSS+R: Modelling and Simulating Self-Reconfigurable Systems
Optimizing under abstraction: Using prefetching to improve FPGA performance
Generating FPGA accelerators for chemical similarity assessment
Recursion in reconfigurable computing: A survey of implementation approaches
Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs
Data-Procedural Languages for FPL-based Machines
Evaluation of an FPGA Implementation of the Discrete Element Method
A High-Performance CNN Processor Based on FPGA for MobileNets
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems
Internet Connected FPL
Non-volatile 3D stacking RRAM-based FPGA
TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures
Parameterized Function Evaluation for FPGAs
Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors
A Framework for Neural Network Inference on FPGA-Centric SmartNICs
AmBRAM s - An analysis tool, method and framework for advanced measurements and reliability assessments on modern nanoscale FPGAs
Broken-Karatsuba multiplication and its application to Montgomery modular multiplication
FPGA modeling techniques for detecting and demodulating multiple wireless protocols
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs
VPR-Gym: A Platform for Exploring AI Techniques in FPGA Placement Optimization
Transparent insertion of latency-oblivious logic onto FPGAs
Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms
A Reconfigurable Computing Scheduler Optimized for Multicore Systems
A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations
Improving memory support in the VTR flow
REACT: Reactive Environment for Runtime Reconfiguration
Evaluating the efficiency of DSP Block synthesis inference from flow graphs
Fault Simulation Using Partially Reconfigurable Hardware
A Flexible Circuit-Switched NOC for FPGA-Based Systems
HeteroSim: A heterogeneous CPU-FPGA simulator
A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA