yusuke1997/dblp-id-title huggingface dataset:
A high-performance, yet simple to design, digital-friendly type-I PLL
A 24V-to-20V 6W 73.2%-Peak-Efficiency Isolated DC-DC Converter Using a Transformer-Based Supply-Generating Technique
Neuromorphic Vision Systems for Mobile Applications
A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization
Efficient per-element distortion contribution analysis via Harmonic Balance adjoints
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator
Single event transient mitigation in cache memory using transient error checking circuits
A programmable pulse UWB transmitter with 34% energy efficiency for multichannel neuro-recording systems
MCAST: an abstract-syntax-tree based model compiler for circuit simulation
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection
An efficiency-enhanced auto-reconfigurable 2x/3x SC charge pump for transcutaneous power transmission
A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers
A 0.5V start-up 87% efficiency 0.75mm 2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration
A merged 2.5 V and 3.3 V 0.25-μm CMOS technology for ASICs
2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018
Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s
Leveraging designer's intent: A path toward simpler analog CAD tools
Analysis of envelope signal injection for improvement of RF amplifier intermodulation distortion
Methodology for I/O cell placement and checking in ASIC designs using area-array power grid
A Tri-Mode Filtering Power Amplifier for 5G Millimeter-Wave Dual-Side LO Injection Systems with Power-Efficiency Enhancement
W-band pulsed radar receiver in low cost CMOS
A digital 120Mb/s MIMO-OFDM baseband processor for high speed wireless LANs
Return-limited inductances: a practical approach to on-chip inductance extraction
A 55-mW, 10-bit, 10 Msample/s Nyquist rate CMOS ADC
Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications
Session 7 - Advances in biomedial sensor systems
Understanding injection locking in negative-resistance LC oscillators intuitively using nonlinear feedback analysis
Modular test generation and concurrent transparency-based test translation using gate-level ATPG
A 64 channel programmable receiver chip for 3G wireless infrastructure
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home
A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13μm CMOS
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling
Power gating implementation for noise mitigation with body-tied triple-well structure
SoC implementation issues for synthesizable embedded programmable logic cores
A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors
A custom processor for node and power management of a battery-less body sensor node in 130nm CMOS
A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre
An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization
A high throughput divider implementation
Fast lock scheme for phase-locked loops
A 32-channel front-end for wireless HID using inverse-STF pre-filtering technique
Emerging memory technologies
A micro-power neural spike detector and feature extractor in .13μm CMOS
A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC
A 9.5 mW 330 μsec 1024-point FFT processor
An offset phase-locked loop spread spectrum clock generator for SATA III
Frequency-independent equivalent circuit model for on-chip spiral inductors
A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping
Design for nanoscale patterning
Strong injection locking of low-Q LC oscillators
Measurement and modeling of noise parameters for desensitized low noise amplifiers
Compact high-power 60 GHz power amplifier in 65 nm CMOS
Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability
PipeRench: A virtualized programmable datapath in 0.18 micron technology
Inherently linear time symmetric pulse width modulation
A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS
Design methodology of the embedded DRAM with the virtual socket architecture
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals
A 116nW multi-band wake-up receiver with 31-bit correlator and interference rejection
A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration
28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization
Design of a CMOS floating-gate resistor for highly linear amplifier and multiplier applications
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR
A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter
A 68/36ppm/ ○ C Tc 32.768Khz-To-1Mhz Rc-Based Oscillator With 72/6Pj Start-Up Energy
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components
Sub-mW/qubit 5.2-7.2GHz 65nm Cryo-CMOS RX for Scalable Quantum Computing Applications
A Fully Synthesized Integrated Buck Regulator with Auto-generated GDS-II in 65nm CMOS Process
Analysis of timing recovery for multi-Gbps PAM transceivers
A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery
Design with sub-10 nm FinFET technologies
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS
RFCMOS extension model accurate up to 40 GHz with distributed junction diode
CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator
Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver
Laser formed connections for programmable wiring
A high Q 200 MHz low-power fully integrated bandpass IF filter
A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode
DSP16000: a high performance, low-power dual-MAC DSP core for communications applications
High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper)
A 2.7 V 900 MHz/1.9 GHz dual-band transceiver IC for digital wireless communication
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security
Modeling & design for variability and reliability
A 1.5GHz 0.2ps RMS jitter 1.5mW divider-less FBAR ADPLL in 65nm CMOS
A CMOS ADSL codec for central office applications
Clock distribution networks for 3-D ictegrated Circuits
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC
System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing
CMOS scaling and beyond
A 4-to-42V Input, 95.5% Efficiency, 3.2μA-IQ, DC-DC Buck Converter Featuring a Leakage-Emulated Bootstrap Re-fresher and Anti-Deadlock Self-Bias Supply for Battery-Powered Automotive Uses
A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression
Understanding the Transient Behavior of Injection Locked LC Oscillators
An Area Optimized 2.5-V 10-b 200-MS/s 200-μA CMOS DAC
Compact modeling of multiple-gate MOSFETs
A Wireless Biopotential Sensing Node with Simultaneous Body-Channel Communication by TX-Coupled 21 Vpp Common-Mode Interference Suppression
A 500MHz Low Phase-Noise A1N-on-Silicon Reference Oscillator
A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA
A 140mA 90nm CMOS low drop-out regulator with -56dB power supply rejection at 10MHz
Die Stacking Technology for Terabit Chip-to-Chip Communications
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS
Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI
A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction
A Somatosensory Feedback System in 180nm CMOS
Phase noise in a synchronized concurrent dual-frequency oscillator
A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices
A 9-Bit configurable current source with enhanced output resistance for cochlear stimulators
A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module
Noise tolerant oscillator design using perturbation projection vector analysis
1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems
A 1.3 GHz CMOS VCO with 28% frequency tuning
A 1.5 GHz, sub-2 mW CMOS dual-modulus prescaler
Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS
Switched-capacitor filter based Type-III compensation for switched-mode Buck converters
Oscillator jitter due to supply and substrate noise
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication
A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs
An open-loop 10GHz 8-phase clock generator in 65nm CMOS
A 28-GHz inverse class-F power amplifier with coupled-inductor based harmonic impedance modulator
A Cryogenic Double-IF SSB Controller with Image Suppression and On-Chip Filtering implemented in 130nm SiGe BiCMOS Technology for Superconducting Qubit Control
Foundry technology for 130nm and beyond SoC
A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS
CMOS low-power transceivers for 60GHz multi Gbit/s communications
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process
A 24/77GHz dual-band BiCMOS frequency synthesizer
A 9.6 mW/Ch 10 MHz Wide-bandwidth Electrical Impedance Tomography IC with Accurate Phase Compensation for Breast Cancer Detection
A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS
Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) design
Extremely thin SOI for system-on-chip applications
OFDM modulator with digital IF and on-chip D/A-converter
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS
A 0.13 μm Low-power Race-free Programmable Logic Array
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations
Comprehending In-memory Computing Trends via Proper Benchmarking
A 280-325 GHz Frequency Multiplier Chain With 2.5 dBm Peak Output Power
Reverse Engineering in the Semiconductor Industry
Hierarchical watermarking in IC design
A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM
A 25Gb/s APD-based burst-mode optical receiver with 2.24ns reconfiguration time in 28nm CMOS
Multi-die Integration Using Advanced Packaging Technologies
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line
Behavioral test benches for digital clock and data recovery circuits using Verilog-A
Using quantum emulation for advanced computation
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy
A 0.18 μm CMOS Capacitive Detection Lab-on-Chip
A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensation
Automated extraction of broadly applicable nonlinear analog macromodels from SPICE-level descriptions
Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking
Gate stack resistance and limits to CMOS logic performance
SiGe digital frequency dividers with reduced residual phase noise
A new IC interconnection scheme and design architecture for high performance ICs at very low fabrication cost - post passivation interconnection
2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation
A Phase-Domain Continuous-Time 2 nd -Order ΔΣ Frequency Digitizer
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%
A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS
High speed, low power, optoelectronic InP-based HBT integrated circuits
A 4-bit 12GS/s data acquisition System-on-Chip including a flash ADC and 4-channel DeMUX in 130nm CMOS
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation
52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator Based on Modular-Unit-Tree with Dynamic Data and Compute Gating
Notice of Violation of IEEE Publication PrinciplesA 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect
A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS
A SOC/SOP co-design approach for mmW CMOS in QFN technology
The first near zero-IF RX, 2-point modulation TX CMOS SOC Bluetooth solution
Wave pipelining YADDs-a feasibility study
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005
A signal integrity-based link performance simulation platform
A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers
A 19-30ppm/°C Temperature Coefficient Sub-Nanowatt CMOS Voltage Reference with 10-µA Sourcing Capability
Efficient analytical modeling techniques for rapid integrated spiral inductor prototyping
Simulator for switched-current integrated circuits
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology
CMOS LSI-based multi-chip flexible retinal prosthesis device for subretinal implantation
AJPEG: A 26.4-pJ/pixel, 252-fps, 128×128 Image Sensor with an In-Sensor Analog DCT Processor for Data Compression
IP reuse creation for system-on-a-chip design
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching
Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays
Development of microelectronic based biosensors
Modeling and simulation of transistor and circuit variability and reliability
A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration
A 4-bit ultra-wideband beamformer with 4ps true time delay resolution
An X- and Ku-Band 8-Element Linear Phased Array Receiver
Measurement results of on-chip IR-drop
A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM
A 900 MS/s 6b interleaved CMOS flash ADC
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems
Signal processing and frequency generation in FMCW RADAR
An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI
A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current Accuracy
A design methodology for integrating IP into SOC systems
A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration
A 40V 10W 93%-efficiency current-accuracy-enhanced dimmable LED driver with adaptive timing difference compensation for solid-state lighting applications
Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform
A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD
Cell characterization for noise stability
A dual-band triple-mode SoC for 802.11a/b/g Embedded WLAN in 90nm CMOS
A 27-39GHz 48Gbit/s 8-Channel Phased Array Transceiver Frontend with Broadband TX/RX Co-Design Optimization
An Analog-Proportional Digital-Integral Multi-Loop Digital LDO with Fast Response, Improved PSR and Zero Minimum Load Current
256-site active neural probe and 64-channel responsive cortical stimulator
High-performance flexible all-digital quadrature up and down converter chip
Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment
A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS
A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS
Implementation of H.324 audiovisual codec for mobile computing
A 0.8V accurately-tuned continuous-time filter
A 104-to-132 GHz 16-way Power Amplifier Using Enhanced Magnetic Coupling Cavity Achieving 21.2 dBm Output Power in 28nm Bulk CMOS
A multi-bit sigma-delta ADC for multi-mode receivers
A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique
An ultra low power variable length decoder for MPEG-2 exploiting codeword distribution
A DSP Reed-Solomon coder
Low-power prediction based data transfer architecture
Blind background calibration of harmonic distortion based on selective sampling
Reconfigurable blocker-resilient receiver with concurrent dual-band carrier aggregation
Millimeter-wave frequency generation and synthesis in Silicon
A LEGO-Like Easy-Stacking Step-Up SC Converter with Ultra-High and Wide VCR Using All Input-Stress-Only Devices
A 18.2mW Subsampling mm-Wave Receiver Employing a Subtractive Anti-Aliasing Active Bandstop Filter at 23GHz
Functional safety SoC for autonomous driving
A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibration
RF building blocks
An Ultra-Wideband Amplifier with A Novel Non- Distributed Butterfly Topology Achieving 2-250 GHz Bandwidth and 4.67 THz GBW in 130nm SiGe BiCMOS
A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibration
A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ converters
A split-foundry asynchronous FPGA
Experimental Verification of Simulation Based Yield Optimization for Power-On Reset Cells
A general weak nonlinearity model for LNAs
ESD design challenges and strategies in deeply-scaled integrated circuits
Session 17 non-traditional computing
Designing a via-configurable regular fabric
Dynamic clock management for low power applications in FPGAs
Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers
A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer
All-digital SoC thermal sensor using on-chip high order temperature curvature correction
An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS
RF-CMOS oscillators with switched tuning
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process
ADC trends and impact on SAR ADC architecture and analysis
A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator
Differential ring oscillators with multipath delay stages
A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification
Coherent functional, electrical and physical modeling of IP blocks using ALF
An Sram-Based Accelerator for Solving Partial Differential Equations
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory
A 5-GHz wireless LAN transmitter with integrated tunable high-Q RF filter
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study
A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications
A 54μW Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion
Ramp signal generation in Voltage mode CCM Random switching Frequency Buck converter for conductive EMI reduction
Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs
Doping of Aluminum Nitride and the Impact on Thin Film Piezoelectric and Ferroelectric Device Performance
Design Technology co-optimization for N10
Clock and data recovery systems
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement
A Monolithic Bandpass Amplifier for Neural Signal Processing with 25-Hz Low-Frequency Cutoff
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET
390-640MHz tunable oscillator based on phase interpolation with -120dBc/Hz in-band noise
A 4-channel 24-27 GHz UWB phased array transmitter in 0.13 μm CMOS for vehicular radar
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm 2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration
A 2.4GHz direct modulated 0.18μm CMOS IEEE 802.15.4 compliant Transmitter for ZigBee
A 69.8 dB SNDR 3 rd -order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver
An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier
Challenges and Innovations in Fully Integrated DC-DC Converters for IoT and Modern Computing Platforms
A -115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique
Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers
An inside body power and bidirectional data transfer IC module pair
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS
A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction
StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing
Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]
A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz
A low-power digital filter IC via soft DSP
A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter
Circuit techniques for enhancing the clock data compensation effect under resonant supply noise
A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance
Silicon germanium and silicon bipolar RF circuits for 2.7 V single chip radio transceiver integration
A one time programming cell using more than two resistance levels of a polyfuse
Moving signals on and off chip
Beyond 1 GHz