yusuke1997/dblp-id-title huggingface dataset:
Executable Workflows: A Paradigm for Collaborative Design on the Internet
A Branching Process Model for Observability Analysis of Combinational Circuits
Speculation on the future of design automation
H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit Identification
A novel algorithm to extract two-node bridges
SoC security architecture: current practices and emerging needs
On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks
Automatic generation of logic diagrams
Selective wordline voltage boosting for caches to manage yield under process variations
MINFLOTRANSIT: min-cost flow based transistor sizing tool
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process
Standard lattices in hardware
Multiplexer restructuring for FPGA implementation cost reduction
Switch Level Random Pattern Testability Analysis
Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation
Designers Workbench - efficient and economical design aids
The synthesis of cyclic combinational circuits
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration
A Multi-Layer Router Utilizing Over-Cell Areas
PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization
PHANES: ReRAM-based photonic accelerator for deep neural networks
Election year: what the electronics industry needs---and can expect---from the incoming administration
Computing bounds for fault tolerance using formal techniques
Data-Efficient Conformalized Interval Prediction of Minimum Operating Voltage Capturing Process Variations
RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Networks
Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation
A mixed-mode simulator
A knowledge based approach to VLSI CAD the redesign system
Test Point Insertion: Scan Paths through Combinational Logic
An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2
You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms
The Layout Synthesizer: An Automatic Netlist-to-Layout System
Statistical Framework for Technology-Model-Product Co-Design and Convergence
A Practical Approach to Multiple-Class Retiming
Pre-layout wire length and congestion estimation
A graphical tool for conceptual design of data base applications
Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSN
An interactive graphical logic design simulation system
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
Table-Lookup Methods for Improved Performance-Driven Routing
Utilization of Multiport Memories in Data Path Synthesis
Power Efficient Mediaprocessors: Design Space Exploration
Eyecharts: constructive benchmarking of gate sizing heuristics
On output response compression in the presence of unknown output values
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited
Multi-Layer Dependability: From Microarchitecture to Application Level
Exploring regular fabrics to optimize the performance-cost trade-off
PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation
Multilevel full-chip routing for the X-based architecture
Cross-layer racetrack memory design for ultra high density and low power consumption
INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding
PLAYER: a PLA design system for VLSI's
Beyond Conventional Defenses: Proactive and Adversarial-Resilient Hardware Malware Detection using Deep Reinforcement Learning
Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability
Plug Your Volt: Protecting Intel Processors against Dynamic Voltage Frequency Scaling based Fault Attacks
Post sign-off leakage power optimization
Integrated automation program (I.A.P.) for an electronic switching system
MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks
A stabilized discrete empirical interpolation method for model reduction of electrical, thermal, and microelectromechanical systems
A Fast Physical Constraint Generator for Timing Driven Layout
Design of command menus for CAD systems
Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator
The McBOOLE logic minimizer
MoC: A Morton-Code-Based Fine-Grained Quantization for Accelerating Point Cloud Neural Networks
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing
FeBiM: Efficient and Compact Bayesian Inference Engine Empowered with Ferroelectric In-Memory Computing
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications
Micro-computer oriented algorithms for delay evaluation of MOS gates
Scheduling the FlexRay bus using optimization techniques
Testability driven statistical path selection
Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor
A system of computer aids for designing logic circuit tests
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
Enhanced Visibility and Performance in Functional Verification by Reconstruction
Analog intellectual property: now? Or never?
New Methods in the Analysis of Logic Minimization Data and Algorithms
A Wear-Leveling-Aware Fine-Grained Allocator for Non-Volatile Memory
Logic Minimization using Two-column Rectangle Replacement
A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer
Efficient incremental analysis of on-chip power grid via sparse approximation
Hypergraph Partitioning with Fixed Vertices
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications
Analysis of full-wave conductor system impedance over substrate using novel integration techniques
Invited: Using Causal Information to Enable More Efficient Robot Operation
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?
A design approach for radiation-hard digital electronics
MRLoc: Mitigating Row-hammering based on memory Locality
LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning
A factorization-based framework for passivity-preserving model reduction of RLC systems
Statistics on logic simulation
nZDC: a compiler technique for near zero silent data corruption
A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems
Improved Cut Sequences for Partitioning Based Placement
Implementation of an Efficient Parallel BDD Package
The placement problem as viewed from the physics of classical mechanics
Will Disign tools catch up to VLSI design
Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
SystemVerilog implicit port enhancements accelerate system design & verification
Boolean satisfiability in electronic design automation
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles
GAN-OPC: mask optimization with lithography-guided generative adversarial nets
Automated compact dynamical modeling: an enabling tool for analog designers
Technology Tracking of Non Manhattan VLSI Layout
Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization
Symbolic timing simulation using cluster scheduling
Spare Allocation and Reconfiguration in Large Area VLSI
Hughes S&CG custom LSI layouts - 'we did it our way'
RICE: Rapid Interconnect Circuit Evaluator
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry
A length adaptive algorithm-hardware co-design of transformer on FPGA through sparse attention and dynamic pipelining
Automated partitioning of hierarchically specified digital systems
Performance Analysis of FlexRay-based ECU Networks
Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips
Software Manufacturing
Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity
E 2 SR: an end-to-end video CODEC assisted system for super resolution acceleration
Were the good old days all that good?: EDA then and now
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers
Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation
Can we really do without the support of formal methods in the verification of large designs?
A contemporary perspective on design automation and VLSI in the 80's (Position Statement)
Raise your game for split manufacturing: restoring the true functionality through BEOL
Coupled circuit/EM simulation for radio frequency circuits
The role of microprogramming in the computer science curriculum
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks
Reliability-aware design to suppress aging
LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA
Formal verification of an IBM CoreConnect processor local bus arbiter core
DyAD: smart routing for networks-on-chip
Software engineering techniques in design automation - a tutorial
SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake Simulation
Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
A Model for Scheduling Protocol-Constrained Components and Environments
Model-driven Validation of SystemC Designs
Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits
Automated nonlinear Macromodelling of output buffers for high-speed digital applications
IC Test Using the Energy Consumption Ratio
The Cilk++ concurrency platform
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits
Rewire: Advancing CGRA Mapping Through a Consolidated Routing Paradigm
F/LOGIC - An interactive fault and logic simulator for digital circuits
A "Dogleg" channel router
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation
An area-efficient consolidated configurable error correction for approximate hardware accelerators
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
Optimization of quantum circuits for interaction distance in linear nearest neighbor architectures
Leveraging sequential equivalence checking to enable system-level to RTL flows
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
Automatic PLA synthesis from a DDL-P description
A data structure for MOS circuits
YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip
RTMobile: Beyond Real-Time Mobile Acceleration of RNNs for Speech Recognition
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances
LATA: a latency and throughput-aware packet processing system
Design Methodology of a 200MHz Superscalar Microprocessor: SH-4
INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps
The second generation motis mixed-mode simulator
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration
Proactive circuit allocation in multiplane NoCs
Creation of ESL power models for communication architectures using automatic calibration
Education panel: designing the always connected car of the future
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes
Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications
Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis
Techniques for Unit-Delay Compiled Simulation
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits
Efficient design-specific worst-case corner extraction for integrated circuits
Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis
Linear ordering and application to placement
Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning
Accurate process-hotspot detection using critical design rule extraction
Routing method for VLSI design using irregular cells
MSI and LSI impact on digital systems testing
Automated transistor sizing for FPGA architecture exploration
Data-driven HLS optimization for reconfigurable accelerators
Symbolic representation with ordered function templates
An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.
Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture
High-performance energy-efficient encryption in the sub-45nm CMOS Era
OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design
An O(nlogn) time algorithm for optimal buffer insertion
Streamline verification process with formal property verification to meet highly compressed design cycle
Layout Compaction with Attractive and Repulsive Constraints
Performance-Driven Scheduling with Bit-Level Chaining
PODEM-X: An automatic test generation system for VLSI logic structures
SuperFast: Fast Supernet Training Using Initial Knowledge
Boolean satisfiability using noise based logic
IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX Applications
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement
Battery-conscious task sequencing for portable devices including voltage/clock scaling
IBM 3081 system overview and technology
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry
Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage
Multilayer printed wiring - computer aided design
The interconnection problem - a tutorial
Transmuting coprocessors: dynamic loading of FPGA coprocessors
Near-optimal placement using a quadratic objective function
A closed-form expression for estimating minimum operating voltage (V DDmin ) of CMOS logic gates
Analog placement with current flow and symmetry constraints using PCP-SP
PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMs
COT - customer owned trouble
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors
Design and Implementation of the NUMAchine Multiprocessor
PROTEST: a tool for probabilistic testability analysis
A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification
NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters
Bumblebee: A MemCache Design for Die-stacked and Off-chip Heterogeneous Memory Systems
Robust design of E/E architecture component platforms
SWAMI: a flexible logic implementation system
Enhanced Controllability for I DDQ Test Sets Using Partial Scan
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
Benchmarks for Cell Synthesis
Assessing the performance limits of parallelized near-threshold computing
Scheduling High-Level Blocks for Functional Simulation
Diagnosis of TCM failures in the IBM 3081 Processor complex
Flexible chip placement via reinforcement learning: late breaking results
PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs
A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips
A Verification Technique for Gated Clock
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
An interactive graphical debugging system
SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems
Efficient maximum data age analysis for cause-effect chains in automotive systems
Generalised CMOS-a technology independent CMOS IC design style
Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications
MPass: Bypassing Learning-based Static Malware Detectors
Sparse 3-D NoCs with Inductive Coupling
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing
APP: Enabling Soft Real-Time Execution on Densely-Populated Hybrid Memory System
Design, CAD and technology challenges for future processors: 3D perspectives
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement
Fast Bit-True Simulation
A Rigorous Graphical Technique for Predicting Sub-harmonic Injection Locking in LC Oscillators
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage
A statistical method for test sequence evaluation
Coverage in interpolation-based model checking
Spectral K -Way Ratio-Cut Partitioning and Clustering
Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks
Hardware authentication leveraging performance limits in detailed simulations and emulations
Behavioral Synthesis Methodology for HDL-Based Specification and Validation
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency
Verification and Management of a Multimillion-Gate Embedded Core Design
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing
Amoeba: A symbolic VLSI layout system
TIGA: Towards Efficient Near Data Processing in SmartNICs-based Disaggregated Memory Systems
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation
MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs
Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
Optimum placement of two rectangular blocks
A universal state-of-charge algorithm for batteries
ESL hand-off: fact or EDA fiction?
SWIM: selective write-verify for computing-in-memory neural accelerators
Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once
LIO-DPC: Accurate and Fast LiDAR-Inertial Odometry with Dynamic Pose Chain
A new heuristic algorithm for reversible logic synthesis
Leveraging Approximate Data for Robust Flash Storage
Spectrum: a hybrid nanophotonic-electric on-chip network
Invited: Challenges and Opportunities of Quantum Optimization in Finance
Quantum-Like Effects in Network-on-Chip Buffers Behavior
A fault simulator for MOS LSI circuits
Late Breaking Results: Automated Hardware Generation of CNN Models on FPGAs
Automated layout in ASHLAR: An approach to the problems of "General Cell" layout for VLSI
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits
Trw's extended sceptre software-dc program (TESS-DC) a non-linear worst case program
PowerLens: An Adaptive DVFS Framework for Optimizing Energy Efficiency in Deep Neural Networks
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
Automated accelerator optimization aided by graph neural networks
Congestion-driven codesign of power and signal networks
Symbolic hierarchical artwork generation system
Analysis and characterization of inherent application resilience for approximate computing
System-Chip Test Strategies (Tutorial)
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
PRO - an automatic string placement program for polycell layout
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models
How to Obtain More Compactable Channel Routing Solutions
Diffusion-based placement migration
Dynamic Sparse Training via Balancing the Exploration-Exploitation Trade-off
Force-Directed Scheduling in Automatic Data Path Synthesis
Microprocessor Testing: Which Technique is Best? (Panel)
Timing Optimization on Mapped Circuits
CAD/CAM - the foundation for Computer Integrated Manufacturing
Backtrack programming in welded girder design
The CRITTER system: Automated critiquing of digital circuit designs
Modular scheduling of guarded atomic actions
An interactive layout system of analog printed wiring boards
Design of a Quantum Walk Circuit to Solve the Subset-Sum Problem
Espresso-Signature: A New Exact Minimizer for Logic Functions
APSS: An automatic PLA synthesis system
PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification
Extracting Schematic-like Information from CMOS Circuit Net-lists
Heterogeneous MP-SoC: the solution to energy-efficient signal processing
A Methodology and Algorithms for Post-Placement Delay Optimization
A fast simulator for the analysis of sub-threshold thermal noise transients
Automating the software design process by means of software design and documentation language
Random walks in a supply network
DETERRENT: detecting trojans using reinforcement learning
Timing Verification Using HDTV
Stonewalls: Experiments in intelligent drafting
An Interpreter for General Netlist Design Rule Checking
An Intelligent Component Database for Behavioral Synthesis
A fast algorithm for context-aware buffer insertion
3D integration for energy efficient system design
Quantifying and coping with parametric variations in 3D-stacked microarchitectures
Analog parallelism in ring-based VCOs
FPGA area reduction by multi-output function based sequential resynthesis
A novel cross-layer framework for early-stage power delivery and architecture co-exploration
Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment
Optimal Clustering for Delay Minimization
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation
Control Flow Divergence Optimization by Exploiting Tensor Cores
R2B: high-efficiency and fair I/O scheduling for multi-tenant with differentiated demands
An Efficient Two-Dimensional Layout Compaction Algorithm
PATH: evaluation of boolean logic using path-based in-memory computing
A High-accurate Multi-objective Exploration Framework for Design Space of CPU
Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory
Ultimate: A hardware logic simulation engine
On Resolution Proofs for Combinational Equivalence
TWIGY - a topological algorithm based routing system
Optimization-Intensive Watermarking Techniques for Decision Problems