yusuke1997/dblp-id-title huggingface dataset:
Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities
Collision array based workload assignment for Network-on-Chip concurrency
Pin accessibility evaluating model for improving routability of VLSI designs
Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge
Automated Full Chip SPICE simulations with self-checking assertions for last mile verification & first pass Silicon of mixed signal SoCs
An IR drop-driven placer for standard cells in a SOC design
Accurate Simulation Environment for Signal Isolation in Mixed-Signal Design
Clock tree tuning using shortest paths polygon
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators
Treat thy secondary (ALMOST) like thy primary- A fair arbiter in master-slave configuration
Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN)
A SpaceWire PHY with Double Data Rate and Fallback Redundancy
Run-time voltage detection circuit for 3-D IC power delivery
Software defined radio based frequency domain chaotic cognitive radio
A scalable and robust rail-to-rail delay cell for DLLs
EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data Transfer
Plenary speaker: Connectivity driven systems: On-chip, off-chip and in-between
Ultra wideband 32-67GHz phase shift keyed modulator
High-PSR CMOS LDO with embedded ripple feedforward and energy-efficient bandwidth extension
Memristor in neuromorphic computing
Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip
Design of a link-controller architecture for multiple serial link protocols
SiGe BiCMOS Process Design Kit for Cryogenic High-Frequency Applications
Cost-optimal design of wireless pre-bonding test framework
Safety Analysis of Machine Learning-Based Applications in Autonomous Driving Platforms Using Digital Twin Simulation and Runtime Monitoring
Efficient stochastic list successive cancellation decoder for polar codes
Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)"
Energy-optimal signaling and ordering of bits for area-constrained interconnects
Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing
Compressive image sensor technique with sparse measurement matrix
An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling
Power minimization of rotary clock design
Accelerating Automated Driving and ADAS Using HW/SW Codesign
Data-Centric Machine Learning Pipeline for Hardware Verification
Concept and design of exhaustive-parallel search algorithm for Network-on-Chip
A low power 32 nanometer CMOS digitally controlled oscillator
An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier For Low-Power RF Receivers
Invited talk: Noise and mismatch in sub 28nm silicon processes
Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture
Low power tri-state register files design for modern out-of-order processors
A 1V-2.39mW capacitor-coupling resonated low noise amplifier for 3-5GHz ultra-wideband system
A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks
Variable-length VLIW encoding for code size reduction in embedded processors
Low-power SOC implementation: What you need to know
A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State Machines
Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operations
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures
Towards formal system-level verification of security requirements during hardware/software codesign
F1A: Networks on chip
A gate sizing method for glitch power reduction
LLM Performance Bottlenecks on CGLA
Multi-objective optimization of radio-frequency front-ends
Comparator testing in a flash A/D converter
Rapid energy estimation of computations on FPGA based soft processors
28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015
Exploiting large on-chip memory space through data recomputation
Enhancing Adversarial Attacks on Single-Layer NVM Crossbar-Based Neural Networks with Power Consumption Information
DLL-based programmable clock multiplier using differential toggle-pulsed latch
European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System
A new generation of C-base synthesis tool and domain-specific computing
Co-Design of Highly Uniform ReRAM Arrays in 180nm CMOS Technology for Neuromorphic Systems
Memories: Exploiting Them and Developing Them
Comparative performance evaluation of wireless and optical NoC architectures
A low power and low area active clock deskewing technique for sub-90nm technologies
A novel half-rate architecture for high-speed clock and data recovery
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology
GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights
Design and implementation of interface circuitry for cmos-based saw gas sensors
Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis
Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study
Designing Algorithm for the High Speed TIQ ADC, with Improved Accuracy
A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications
A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology
From Film to Silicon: The Migration of Document Archiving Technology
Generating hardware and software for RISC-V cores generated with Rocket Chip generator
Footer voltage feedforward domino technique for wide fan-in dynamic logic
Efficient Localization of Origins of PVC based on Random Signal Segmentation
Isosceles Trapezoidal TSVs for High-Density Interconnects in 3D ICs and Crosstalk Analysis
Testing system-on-a-chip using artificial immune system
Variation-tolerant design of D-flipflops
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs
A comparator-based switched-capacitor integrator using a new charge control circuit
A spread spectrum clock generator using digital modulation scheme
Design of a complementary folded-cascode operational amplifier
Optimal power-constrained SoC test schedules with customizable clock rates
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults
Serial RapidlO: Benefiting System Interconnects
TANGO-5: Threat ANalysis and Gem5-based attack simulation for CNN hardware acceleratOrs
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency
Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors
A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processor
FPNA: A Reconfigurable Accelerator for AI Inference at the Edge
Aging-aware reliable multiplier design
Fine Grained Control Flow Checking with Dedicated FPGA Monitors
Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module
Latency-optimization synthesis with module selection for digital microfluidic biochips
ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip
Investigating SAMV Regarding its Suitability For FPGAs
Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison
Design of cost-efficient memory-based FFT processors using single-port memories
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS
System-level design of low-cost FPGA hardware for real-time ICA-based blind source separation
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology
An analytical model to estimate PCM failure probability due to process variations
Crosstalk induced fault analysis in DRAMs
A 1Gbps FPGA-based wireless baseband MIMO transceiver
Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation
Keynote speaker: "The roadway to innovation"
Improving Timing Quality Through Net Topology Optimization in Global Routing
μThingNet: Leveraging Fine-Grained Power Analysis towards A Robust Zero-Day Defender
Morpack Cube: A portable 3D heterogeneous system integration platform
Design of near threshold All Digital Delay Locked Loops
Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array
Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs
Memory cost analysis for OpenFlow multiple table lookup
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework
Energy-Efficient SRAM Design with Data-Aware Dual-Modes L0T Storage Cell for CNN Processors
Cell Switched Network-on-Chip - Candidate for Billion-Transistor System-on-Chips
Design of ultra low power CML MUXs and latches with forward body bias
Power aware parallel computing on asymmetric multiprocessor
System Level Design Methodology for System On Chips using Multi-Threaded Graphs
"High-level synthesis and beyond - From datacenters to IoTs"
W2A: Analog-to-digital converters and low-noise amplifiers
A Digital-Enhanced Interferometric Radar Sensor for Physiological Sign Monitoring
A method for efficient NoC test scheduling using deterministic routing
On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators
Novel time-multiplexing bidirectional on-chip network
PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks
Low power Gm-boosted differential Colpitts VCO
CaPSuLe: A camera-based positioning system using learning
Sleep transistor design in 28nm CMOS technology
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation
Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing
Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET)
Flexible reconfigurable architecture for DSP applications
GATrojan: An Efficient Gate-level Hardware Trojan Detection Approach Using Graph Attention Networks
A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme
An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit
Configurable baseband designs and implementations of WiMAX/LTE dual systems based on multi-core DSP
New low voltage, high PSRR, CMOS bandgap voltage reference
Substrate noise optimization in early floorplanning for mixed signal SOCs
Digital Twin Based Run Time Power Management for Edge SoC using Performance Aware Reinforcement Learning
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2
TSV-based 3D-IC placement for timing optimization
Hardware Security in the Internet of Things: A Survey
Striking a balance between SoC security and debug requirements
Flow oriented routing for NOCS
High-performance adaption of ARM processors into Network-on-Chip architectures
Quantifying trust in autonomous system under uncertainties
A hierarchically-controlled SIMD machine for 2D DCT on FPGAs
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications
On the encoding complexity of systematic polar codes
ILP-based scheme for timing variation-aware scheduling and resource binding
Plenary presentation B
A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs
An Entropy Analysis Based Intrusion Detection System for Controller Area Network in Vehicles
A linearized low-voltage oscillator-mixer
A CMOS low-power low-offset and high-speed fully dynamic latched comparator
Securing FPGA SoC configurations independent of their manufacturers
Impact of technology scaling on RF CMOS
Fused Multiply-Add for Variable Precision Floating-Point
A novel digital loop filter architecture for bang-bang ADPLL
Design of a baseband processor for software radio using FPGAs
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT
DyML: Dynamic Multi-Level flow control for Networks on Chip
Router-level performance driven dynamic management in hierarchical networks-on-chip
18FD-SOI: Case Study at Arm
Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique
A SAR ADC BIST for simplified linearity test
Designing bio-inspired autonomous error-tolerant massively parallel computing architectures
Limitations of integrating field induced aggregation based fault repair automatons with integrated circuits
Lockstep Vs Microarchitecture: A Comparison
A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs
Real-time implementation of H.264 Video Coding
A framework of architectural synthesis for dynamically reconfigurable FPGAs
Delay dependent power optimisation of combinational circuits using AND-Inverter graphs
Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-Chip
A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity
A Radix 2 2 based parallel pipeline FFT processor for MB-OFDM UWB system
A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Silencer!: a tool for substrate noise coupling analysis
An Architectural Design of Process Partitioning and Device Mapping with In-memory Computing for Pedestrian Detection
Hardware architecture of an Internet Protocol Version 6 processor
A Neural-Network-Based Non-linear Interference Cancellation Scheme for Wireless IoT Backhaul with Dual-Connectivity
Adaptive energy-aware latency-constrained DVFS policy for MPSoC
Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array
Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength
Low-noise high input impedance 8-channels chopper-stabilized EEG acquisition system
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery
16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI Hardware Using FPGA
Direction-constrained layer assignment for rectangle escape routing
Memristor crossbar based multicore neuromorphic processors
A ZigBee compliant baseband and MAC processor
ViLoCoN - An ultra-lightweight lossless VLSI video codec
Binary object recognition system on FPGA with bSOM
Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC
A design procedure of predictive RF MOSFET model for compatibility with ITRS
A comparator timing assisted SAR ADC technique with reduced conversion cycles
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation
Mist-Scan: A Secure Scan Chain Architecture to Resist Scan-Based Attacks in Cryptographic Chips
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks
A Novel Test Vector Generation Method for Hardware Trojan Detection
Quality-driven SoC architecture synthesis for embedded applications
An asynchronous on-chip network router with quality-of-service (QoS) support
Robust multi-phase clock generation with reduced jitter
ReAD: ReRAM-Based Computing-In-Memory Design and Optimization by AC-DC Mixed Signal
"Future trends in PC computing and their implications to SoC"
Design of Low Power Digital Phase Lock Loops
A 2 GHz and 5GHz dual-band direct conversion RF frontend for multi-standard applications
Implementation and performance analysis of variable latency adders
Asynchronous circuit design using Handshake Solutions
A Reconfigurable CMOS Power Amplifier Operating from 0.9 TO 2.4 GHZ for WPAN Application
CGA: Combining cluster analysis with genetic algorithm for regression suite reduction of microprocessors
Partitioning-based multiplexer network synthesis for field-data extractors
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors
IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012
Neural recording system with low-noise analog front-end and comparator-based cyclic ADC
Accelerating chip design with machine learning: From pre-silicon to post-silicon
PAT-Noxim: A Precise Power & Thermal Cycle-Accurate NoC Simulator
Secure digital communication based on Lorenz stream cipher
In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU
An Automotive Vision SoC Platform from IVI to AD Level 4
Support vector machine FPGA implementation for video shot boundary detection application
On-demand memory sub-system for multi-core SoCs
Run-time configuration prefetching to reduce the overhead of dynamically reconfiguration
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration
Baseband signal processing in SDR
A formalism of the specifications for library development
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method
A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard
ASIC evaluation of ECHO hash function
Per-flow state management technique for high-speed networks
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology
Evaluating the Performance of Large Language Models for Design Validation
The path to global connectivity - Wireless communication enters the next generation
ChipPower: an architecture-level leakage simulator
Secure Optimized Hardware IP Design using Key-driven Hash Slicing based HLS Watermarking Integrated with Krill-Herd DSE
Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event
One Model, Multiple Verifications: A Framework for Holistic Security Assurance
Design of a power-efficient ARM processor with a timing-error detection and correction mechanism
Developing a Fine-grained Corpus for a Less-resourced Language: the case of Kurdish
Modeling Five Sentence Quality Representations by Finding Latent Spaces Produced with Deep Long Short-Memory Models
An automatic discourse relation alignment experiment on TED-MDB
Knowledge-Based Word Sense Disambiguation with Distributional Semantic Expansion
Adversarial Attack on Sentiment Classification
Authorship Recognition with Short-Text using Graph-based Techniques
AspeRa: Aspect-Based Rating Prediction Based on User Reviews
Pardon the Interruption: Automatic Analysis of Gender and Competitive Turn-Taking in United States Supreme Court Hearings
Amharic Question Answering for Biography, Definition, and Description Questions
The Design and Construction of the Corpus of China English
CSI Peru News: finding the culprit, victim and location in news articles
Recognizing Arrow Of Time In The Short Stories
NLP Automation to Read Radiological Reports to Detect the Stage of Cancer Among Lung Cancer Patients
Implementing a Multi-lingual Chatbot for Positive Reinforcement in Young Learners
Exploring the Use of Lexicons to aid Deep Learning towards the Detection of Abusive Language
Speech Recognition for Tigrinya language Using Deep Neural Network Approach
Evaluating Ways of Adapting Word Similarity
Reading KITTY: Pitch Range as an Indicator of Reading Skill
Understanding the Shades of Sexism in Popular TV Series
A Deep Learning Approach to Language-independent Gender Prediction on Twitter
Construction and Alignment of Multilingual Entailment Graphs for Semantic Inference
KB-NLG: From Knowledge Base to Natural Language Generation
Isolating the Effects of Modeling Recursive Structures: A Case Study in Pronunciation Prediction of Chinese Characters
Emoji Usage Across Platforms: A Case Study for the Charlottesville Event
OCR Quality and NLP Preprocessing
Development of a General Purpose Sentiment Lexicon for Igbo Language
Amharic Word Sequence Prediction
Assessing the Ability of Neural Machine Translation Models to Perform Syntactic Rewriting
English-Ethiopian Languages Statistical Machine Translation
Lipstick on a Pig: Debiasing Methods Cover up Systematic Gender Biases in Word Embeddings But do not Remove Them
Exploring Social Bias in Chatbots using Stereotype Knowledge
Cross-Sentence Transformations in Text Simplification
Learning Trilingual Dictionaries for Urdu - Roman Urdu - English
Entity-level Classification of Adverse Drug Reactions: a Comparison of Neural Network Models
Acoustic Characterization of Singaporean Children's English: Comparisons to American and British Counterparts
An Online Topic Modeling Framework with Topics Automatically Labeled
Augmenting Named Entity Recognition with Commonsense Knowledge
Proceedings of the 2019 Workshop on Widening NLP@ACL 2019, Florence, Italy, July 28, 2019
Context Effects on Human Judgments of Similarity
Principled Frameworks for Evaluating Ethics in NLP Systems
Controlling the Specificity of Clarification Question Generation
Benchmarking Neural Machine Translation for Southern African Languages
Using Attention-based Bidirectional LSTM to Identify Different Categories of Offensive Language Directed Toward Female Celebrities
Towards a Resource Grammar for Runyankore and Rukiga
Exploiting machine algorithms in vocalic quantification of African English corpora
Joint Inference on Bilingual Parse Trees for PP-attachment Disambiguation
Automatic Product Categorization for Official Statistics
Learning and Understanding Different Categories of Sexism Using Convolutional Neural Network's Filters
Polysemous Language in Child Directed Speech
A compositional view of questions
A Framework for Relation Extraction Across Multiple Datasets in Multiple Domains
A Parallel Corpus Mixtec-Spanish
How does Grammatical Gender Affect Noun Representations in Gender-Marking Languages?
Non-Monotonic Sequential Text Generation
Sentiment Analysis Model for Opinionated Awngi Text: Case of Music Reviews
Rethinking Phonotactic Complexity
Evaluating Coherence in Dialogue Systems using Entailment
Mobile Learning: A Pedagogical Framework to Facilitate Distributed Learning through Collaborative Approach for Enhancing English Language Communication Skills
Analysis of Active Learning Activities Transitions and Patterns in Process Oriented Guided Inquiry Learning (POGIL)
Synchronous virtual classrooms: Student perceptions from an online and blended education course
2010 International Conference on Technology for Education, T4E 2010, Mumbai, India, July 1-3, 2010
Role of Virtual Biology Laboratories in Online and Remote Learning
VLSI Education for Computer Science and Engineering Students through Virtual Labs
Geometry via Gestures: Learning 3D Geometry Using Gestures
"Was It Real?" - The Effects of Virtual Reality Communication Skills Training Among University Students in India
Teaching of programming languages: An introduction to dynamic learning objects
Attendance Monitoring in Classroom Using Smartphone & Wi-Fi Fingerprinting
Development and Validation of a Representational Fluency Test for Primary School Students
Model for Rapid, Large-Scale Development of Learning Objects in Multiple Domains
Determining Equivalence of Expressions: An Automated Evaluator's Perspective
Learning from Blended Chemistry Laboratories
QuizFun: Mobile based quiz game for learning
Building Software Testing Skills in Undergraduate Students Using Spiral Model Approach
Automatic Identification of Subject Domain in Engineering Examination Questions