yusuke1997/dblp-id-title huggingface dataset:
System Architecture Optimization for Vertical Power Delivery
CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window Filtering
GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN
ISS-centric modular HW/SW co-simulation
Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks
Sustainable Carbon-Aware and Water-Efficient LLM Scheduling in Geo-Distributed Cloud Datacenters
Bit-Stream Processing with No Bit-Stream: Efficient Software Simulation of Stochastic Vision Machines
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits
A Hybrid Optical-Electrical Analog Deep Learning Accelerator Using Incoherent Optical Signals
A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization
Modeling a single electron turnstile in HSPICE
A comparison between mask- and field-programmable routing structures on industrial FPGA architectures
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA
Computer-aided design of 3d integrated circuits
Performance Optimization of Self-Timed Circuits
Minimizing concurrent test time in SoC's by balancing resource usage
On Advanced Methodologies for Microarchitecture Design Space Exploration
On-chip area-efficient binary sequence storage
Using Lin-Kernighan algorithm for look-up table compression to improve code density
Using data compression in an MPSoC architecture for improving performance
Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration
Efficient Method for Timing-based Information Flow Verification in Hardware Designs
New algorithms for carry propagation
An Embedded Multi-Layer Spiral Square Inductor for Integrated Power Delivery - Physical Design and Analytical Models
VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support
AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design
Tuning Track-based NVM Caches for Low-Power IoT Devices
Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM
Fast instruction cache modeling for approximate timed HW/SW co-simulation
Standard Data Representations for VLSI Algorithm Development
Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2
Parallel hierarchical global routing for general cell layout
Block placement to ensure channel routability
Ultra-Compact and High-Throughput True Random Number Generator for FPGAs
CoLA: Convolutional Neural Network Model for Secure Low Overhead Logic Locking Assignment
A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission
Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and Prospectus
SimTRaX: Simulation Infrastructure for Exploring Thousands of Cores
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators
Delay independent initialization of sequential circuits
Extending Student Labs with SMT Circuit Implementation
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems
Simscape design flow for memristor based programmable oscillators
Side-channel resistant system-level design flow for public-key cryptography
CMOS system-on-a-chip voltage scaling beyond 50nm
Tuning data replication for improving behavior of MPSoC applications
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation
Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing
A high resolution current stimulating probe for use in neural prostheses
On the use of hierarchy in timing verification with statically sensitizable paths
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops
Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors
HCSAs: Hybrid Computing Systolic Arrays for Accelerating Mamba Models with Unified State Space Buffers and Energy-Efficient Dataflow
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system
ART: Customizing Accelerators for DNN-Enabled Real-Time Safety-Critical Systems
A Software Acceptance Testing Technique Based on Knowledge Accumulation
A scalable threshold logic synthesis method using ZBDDs
Reconfigurable solutions for very-long arithmetic with applications in cryptography
A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor
Real-time implementation of a time-frequency analysis scheme
Session details: Session 3B: VLSI for Machine Learning and Artifical Intelligence 1
1-V 7-mW dual-band fast-locked frequency synthesizer
EraseMe: A Defense Mechanism against Information Leakage exploiting GPU Memory
Simultaneous shield and repeater insertion
Optimizing carry lookahead adders for semicustom CMOS
Glitch-free design for multi-threshold CMOS NCL circuits
Dynamic voltage scaling for multitasking real-time systems with uncertain execution time
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators
Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving
Building block layout based on block compaction and two-adjacent-side channel router
Adversarial Perturbation with ResNet
Hardware Trojan Insertion Using Reinforcement Learning
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs
Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies
Full-chip leakage current estimation based on statistical sampling techniques
A Multi-agent Generative Model for Collaborative Global Routing Refinement
A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device
CrossNAS: A Cross-Layer Neural Architecture Search Framework for PIM Systems
HyMacs: hybrid memory access optimization based on custom-instruction scheduling
Graphene Neural Sensors for Next Generation In Vivo Imaging and Optogenetics
Characterization of monotonic static CMOS gates in a 65nm technology
IR-drop Aware Power Network Synthesis for Power Gating Designs
A Machine Learning Based Load Value Approximator Guided by the Tightened Value Locality
Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors
A comprehensive high-level synthesis system for control-flow intensive behaviors
Novel Design for Testability of a Mixed-Signal VLSI IC
Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations
Precision and Performance-Aware Voltage Scaling in DNN Accelerators
Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges
Exact sat-based toffoli network synthesis
Post-route refinement for high-frequency PCBs considering meander segment alleviation
Inverse-Transpilation: Reverse-Engineering Quantum Compiler Optimization Passes from Circuit Snapshots
New optimal layer assignment for bus-oriented escape routing
Efficient simulation of switch-level circuits in a hierarchical simulation environment
Timing and Power Optimization by Gate Sizing Considering False Paths
HT-EMIS: A Deep Learning Tool for Hardware Trojan Detection and Identification through Runtime EM Side-Channels
Highly adaptive and congestion-aware routing for 3D NoCs
Multi-peak bandwidth enhancement technique for multistage amplifiers
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication
A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip
High-performance bidirectional repeaters
Survey of Machine Learning for Electronic Design Automation
Modeling of the transverse delays in modulation-doped heterojunction field-effect transistors
On computational complexity of a detailed routing problem in two dimensional FPGAs
MILS: Modality Interaction Driven Learning for Logic Synthesis
Deep Neural Network accelerator with Spintronic Memory
Design of a nanosensor array architecture
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits
Compression-Assisted Zero-Shot Prompting of Large Language Models (LLMs) for Educational Skill Classification of Microprocessor Curricula
Securing Analog Mixed-Signal Integrated Circuits Through Shared Dependencies
Q-Embroidery: A Study on Weaving Quantum Error Correction into the Fabric of Quantum Classifiers
Chip Pad Migration is a Key Component to High Performance MCM Design
Pipelined network of PLA based circuit design
A denial-of-service resilient wireless NoC architecture
A decoupling technique for CMOS strong-coupled structures
A stochastic-based efficient critical area extractor on OpenAccess platform
Modeling of transmission lines with EM wave coupling by the finite difference quadrature method
Zero clustering: an approach to extend zero compression to instruction caches
An Analytical Model for High-Frequency Through Silicon Vias
A low-power CMOS thyristor based delay element with programmability extensions
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
Feature Fusion based Hotspot Detection with R-EfficientNet
Thermal stress aware 3D-IC statistical static timing analysis
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization
Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems
MSCS: Multi-hop Segmented Circuit Switching
Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures
Hardware Accelerators for Spiking Neural Networks for Energy-Efficient Edge Computing
Reducing parity generation latency through input value aware circuits
Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement
A source-synchronous Htree-based network-on-chip
Event-Driven Spatiotemporal Processing-In-Sensor with Phase Change Memory-based Optical Acceleration
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology
Design Space Exploration for PCM-based Photonic Memory
A Greedy Router with Technology Targetable Output
An Efficient Approach to Sample On-Chip Power Supplies
Toward a Steiner engine: enhanced serial and parallel implementations of the iterated 1-Steiner MRST algorithm
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology
Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach
A new look at hardware maze routing
Energy efficient synchronization techniques for embedded architectures
Clock partitioning for testability
CAMeleon: Reconfigurable B(T)CAM in Computational RAM
Minimizing Error of Stochastic Computation through Linear Transformation
Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability
Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration
Unlocking Approximations through Selective Source Code Transformations
A SiGe BiCMOS linear regulator with wideband, high power supply rejection
Autotile: Autonomous Task-tiling for Deep Inference on Battery-less Embedded System
A Novel Static D-Flip-Flop Topology for Low Swing Clocking
Generating concise assertions with complete coverage
Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits
Going Small: Using the Insect Brain as a Model System for Edge Processing Applications
LASER: layout-aware analog synthesis environment on laker
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays
On the use of Deep Autoencoders for Efficient Embedded Reinforcement Learning
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits
Virtual register renaming: energy efficient substrate for continual flow pipelines
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate
A new algorithm for the largest compositionally progressive solution of synchronous language equations
Design limitations in deep sub-0.1µm CMOS SRAM
Self-resetting stage logic pipelines
Electrical models for vertical carbon nanotube capacitors
A Scalable BFloat16 Dot-Product Architecture for Deep Learning
Low Cost Hybrid Spin-CMOS Compressor for Stochastic Neural Networks
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks
On wiring overlap layouts
A Senior-Level Analog IC Design Course built on Open-Source Technologies
Predictive Warp Scheduling for Efficient Execution in GPGPU
On Path Delay Fault Testing of Multiplexer - Based Shifters
A low power, variable resolution two-step flash ADC
Characterization of logic circuit techniques for high leakage CMOS technologies
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
Floorplan area optimization using genetic algorithms
Area minimization algorithm for parallel prefix adders under bitwise delay constraints
Towards Self-Aware Systems-on-Chip Through Intelligent Cross-Layer Coordination
Adaptive compressive sensing for low power wireless sensors
A Novel Side-Channel Timing Attack on GPUs
Online circuit reliability monitoring
A new algorithm for layout of dark field alternating phase shifting masks
RAMA: a self-assembled multiferroic magnetic QCA for low power systems
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
An asynchronous multiplier
On-die CMOS voltage droop detection and dynamiccompensation
A low-power and high-linear double-balanced switching mixer
Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA
A novel droplet routing algorithm for digital microfluidic biochips
A simple DDS architecture with highly efficient sine function lookup table
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks
A programmable and scalable technique to design spintronic logic circuits based on magnetic tunnel junctions
APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests
Protecting Deep Neural Network Intellectual Property with Architecture-Agnostic Input Obfuscation
Emotion Detection in Older Adults Using Physiological Signals from Wearable Sensors
Manufacturing yield of QCA circuits by synthesized DNA self-assembled templates
Towards design and validation of mixed-technology SOCs
Efficient and Secure On-Chip Reconfigurable Voltage Regulation for IoT Devices
3D-SWIFT: a high-performance 3D-stacked wide IO DRAM
A systolic algorithm and architecture for image thinning
Confidence Counter Modelling for Value Predictor
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs
Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology
An empirical study of crosstalk in VDSM technologies
A personal computer based VLSI design curriculum
Memory Chip BIST Architecture
Lifetime reliability assessment with aging information from low-level sensors
Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems
An indirect current sensing technique for IDDQ and IDDT tests
Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths
Minimal period retiming under process variations
A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on Adaptive Duty-cycling BPSK Modulated Class-E Amplifier
Delay model for reconfigurable logic gates based on graphene PN-junctions
Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Leakage power minimization for the synthesis of parallel multiplier circuits
DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks
VLSI Design Methods for Low Power Embedded Encryption
A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores
Gate-Controlled Memristors and their Applications in Neuromorphic Architectures
Slack borrowing in flip-flop based sequential circuits
Influence of metallic tubes on the reliability of CNTFET SRAMs: error mechanisms and countermeasures
Multi-Transverse-Mode Silicon Photonics for Quantum Computing
Reticle floorplanning of flexible chips for multi-project wafers
Memory-based computing for performance and energy improvement in multicore architectures
Formal Analysis Provides Parameters for Guiding Hyperoxidation in Bacteria using Phototoxic Proteins
Retiming algorithms with application to VLSI testability
Quantum information processing beyond polarization encoding
Three-valued automated reasoning on analog properties
Using soft-edge flip-flops to compensate NBTI-induced delay degradation
Design and characterization of an and-or-inverter (AOI) gate for QCA implementation
Power-efficient ASIC synthesis of cryptographic sboxes
Low power ATPG for path delay faults
On Applying Set Covering Models to Test Set Compaction
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic
EdgeGuard: Robust and Fault-Aware Design for Resilient Edge Computing AI Accelerators
Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices
A VLSI Self-Compacting Buffer for DAMQ Communication Switches
Embedded Neurally Inspired Visual Processing
Dynamic context management for low power coarse-grained reconfigurable architecture
Repeater and current-sensing hybrid circuits for on-chip interconnects
VLSI synthesis of a programmable DWT chip for the optimal choice of a prototype wavelet
The future of high-speed cryptography: new computing platforms and new ciphers
DRAM based Intrinsic Physical Unclonable Functions for System Level Security
On the detection and elimination of superfluous level-sensitive latches
A Homomorphic Encryption Scheme Based on Affine Transforms
Evolutionary Standard Cell Synthesis of Unconventional Designs
Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation
Efficient Delay Test Generation for Modular Circuits
High-Density FeFET-based CAM Cell Design Via Multi-Dimensional Encoding
HW/SW partitioning techniques for multi-mode multi-task embedded applications
Securely outsourcing power grid simulation on cloud
System level design of real time face recognition architecture based on composite PCA
Fast ECO Leakage Optimization Using Graph Convolutional Network
Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method
Logic in Wire: Using Quantum Dots to Implement a Microprocessor
LiteNoC: Developing Low-Cost Network-on-Chips for Deep Neural Networks
Interactive optimal channel router for critical nets
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis
MirrorFS: Cross-Layered File System for SSD-based In-Storage Computing
A Runtime-Reconfigurable Hardware Encoder for Spiking Neural Networks
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration
COCOA: Content-Oriented Configurable Architecture Based on Highly-Adaptive Data Transmission Networks
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
A Storage Structure for Graph-Oriented Databases Using an Array of Element Types
Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips
On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing
Aging-Induced Failure Prognosis via Digital Sensors
Modeling QCA for area minimization in logic synthesis
Forensics of Transpiled Quantum Circuits
FLexiTASK: A Flexible FPGA Overlay for Efficient Multitasking
Design for Eliminating Operation Specific Power Signatures from Digital Logic
SERN: Modeling and Analyzing the Soft Error Reliability of Convolutional Neural Networks
Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications
A new balanced 4-moduli set {2 k , 2 n - 1, 2 n + 1, 2 n+1 -1} and its reverse converter design for efficient fir filter implementation
3D direct vertical interconnect microprocessors test vehicle
Feed-Forward XOR PUFs: Reliability and Attack-Resistance Analysis
Magnetic In/Near-Sensor Architectures: From Raw Sensing to Smart Processing
Variability-aware design of double gate FinFET-based current mirrors
An efficient multiprocessor implementation scheme for real-time DSP algorithms
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques
Exploring Remote Power Attacks Targeting Parallel Data Encryption On Multi-Tenant FPGAs
A high speed and leakage-tolerant domino logic for high fan-in gates
A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs
Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors
Harnessing Heterogeneity for Targeted Attacks on 3-D ICs
Parallel genetic algorithm for channel routing
Scan testing of asynchronous sequential circuits
Soft error rate computation in early design stages using boolean satisfiability
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection
An Efficient Cache Management Scheme for Capacitor Equipped Solid State Drives
Restricted Clustered Neural Network for Storing Real Data
Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints
Inevitability of Phase-locking in a Charge Pump Phase Lock Loop using Deductive Verification
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector
A low-power correlator
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation
Symbolic Multi-Level Verification of Refinement
A lithography-friendly structured ASIC design approach
Digital CMOS logic operation in the sub-threshold region
High CMRR current mode operational amplifier with a novel class AB input stage