yusuke1997/dblp-id-title huggingface dataset:
When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation
Detection of False Positive and False Negative Samples in Semantic Segmentation
Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs
Microsystems Testing: an Approach and Open Problems
A methodology for the design of dynamic accuracy operators by runtime back bias
Delay models for the sea-of-wires array synthesis system
An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal Devices
Compositional, efficient caches for a chip multi-processor
A Practical Learning-Based FTL for Memory Constrained Mobile Flash Storage
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
Path selection and sensor insertion flow for age monitoring in FPGAs
Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines
Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis
Thermal optimization using adaptive approximate computing for video coding
Monitoring of MTL specifications with IBM's spiking-neuron model
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures
SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors
GentleCool: Cooling aware proactive workload scheduling in multi-machine systems
Energy reduction by workload adaptation in a multi-process environment
Constant-time admission control for Deadline Monotonic tasks
Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling
A Formal Verification Methodology for Checking Data Integrity
Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters
One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs
A high performance SEU-tolerant latch for nanoscale CMOS technology
A universal symmetry detection algorithm
Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systems
MNT Bench: Benchmarking Software and Layout Libraries for Field-Coupled Nanocomputing
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults
Space of DRAM fault models and corresponding testing
Design and implementation of a group-based RO PUF
Using structural relations for checking combinationality of cyclic circuits
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Large scale RLC circuit analysis using RLCG-MNA formulation
Performance Analysis of SoC Architectures Based on Latency-Rate Servers
Aging-aware timing analysis and optimization considering path sensitization
Design of an intrinsically-linear double-VCO-based ADC with 2 nd -order noise shaping
Fast and accurate protocol specific bus modeling using TLM 2.0
A scan partitioning algorithm for reducing capture power of delay-fault LBIST
MCTA: A Multi-Stage Co-Optimized Transformer Accelerator with Energy-Efficient Dynamic Sparse Optimization
Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting
FaulTM: error detection and recovery using hardware transactional memory
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Flex memory: Exploiting and managing abundant off-chip optical bandwidth
Instruction Cache Energy Saving Through Compiler Way-Placement
Using Transaction Level Modeling techniques for wireless sensor network simulation
Locality-Aware Process Scheduling for Embedded MPSoCs
STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ
Applying Reservation-based Scheduling to a μC-based Hypervisor: An industrial case study
A fast BDD Minimization Framework for Approximate Computing
Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks
Statistical Model Checking of Approximate Circuits: Challenges and Opportunities
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems
GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation
Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs
Novel magnetic burn-in for retention testing of STTRAM
Human-Centered Digital Twin for Industry 5.0
Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs
Online binding of applications to multiple clock domains in shared FPGA-based systems
Polynomial-time subgraph enumeration for automated instruction set extension
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications
A SAT-based fitness function for evolutionary optimization of polymorphic circuits
Quality-aware media scheduling on MPSoC platforms
Developing an integrated verification and debug methodology
Scenario extraction for a refined timing-analysis of automotive network topologies
System level synthesis for virtual memory enabled hardware threads
An algebra for modeling continuous time systems
Exploiting Functional Dependencies in Finite State Machine Verification
Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks
Make it reversible: Efficient embedding of non-reversible functions
Hardware/Software Design Space Exploration for a Reconfigurable Processor
PhoNoCMap: An application mapping tool for photonic networks-on-chip
A Faster Counterexample Minimization Algorithm Based on Refutation Analysis
Soft error rate analysis for sequential circuits
Integrating UML into SoC Design Process
HME: A lightweight emulator for hybrid memory
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization
Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model
Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?
Bi-Level Optimization Accelerated DRC-Aware Physical Design Automation for Photonic Devices
Functional Scan Chain Testing
Approaches to On-chip Testing of Mixed Signal Macros in ASICs
Assertion-Based Verification through Binary Instrumentation
A fine-grained performance model for GPU architectures
Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation
Extending Synchronous Languages for Generating Abstract Real-Time Models
A Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles (Interactive Presentation)
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance
TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration
Formal specification and systematic model-driven testing of embedded automotive systems
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis
Post-Silicon Validation of the IBM POWER9 Processor
Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment
Side-channel plaintext-recovery attacks on leakage-resilient encryption
An Efficient Sequential SAT Solver With Improved Search Strategies
System level assessment of an optical NoC in an MPSoC platform
Current source modeling for power and timing analysis at different supply voltages
Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS
Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods
Device attestation: Past, present, and future
Compact Test Pattern Generation For Multiple Faults In Deep Neural Networks
TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems
Optimizations of an application-level protocol for enhanced dependability in FlexRay
A layered approach for testing timing in the model-based implementation
FlexBench: Reuse of Verification IP to Increase Productivity
Testing Arithmetic Coprocessor in System Environment
Analog Printed Spiking Neuromorphic Circuit
An evolution programming approach on multiple behaviors for the design of application specific programmable processors
On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC
Design Automation for Deepsubmicron: Present and Future
Automatic Formal Verification of Fused-Multiply-Add FPUs
A new architecture for power network in 3D IC
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation
Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces
Moving from co-simulation to simulation for effective smart systems design
Automatic pipelining from transactional datapath specifications
Computation of Buffer Capacities for Throughput Constrained and Data Dependent Inter-Task Communication
Fixed origin corner square inspection layout regularity metric
Formally Verifying Analog Neural Networks with Device Mismatch Variations
Transforming Structural Model to Runtime Model of Embedded Software with Real-Time Constraints
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications
Lemma localization: a practical method for downsizing SMT-interpolants
Automated Hardware Security Countermeasure Integration Inside High Level Synthesis
Demonstration of an in-band reconfiguration data distribution and network node reconfiguration
SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments
Built-in intermediate voltage testing for CMOS circuits
SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis
Architecture-Level Performance Estimation for IP-Based Embedded Systems
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI
A flexible UWB Transmitter for breast cancer detection imaging systems
Model predictive control over delay-based differentiated services control networks
G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators
An efficient algorithm for multi-domain clock skew scheduling
TEEM: Online Thermal- and Energy-Efficiency Management on CPU-GPU MPSoCs
Autonomous Hyperloop Control Architecture Design using MAPE-K
Early failure prediction by using in-situ monitors: Implementation and application results
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead
From Simulink to NoC-based MPSoC on FPGA
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)
A New Parameterizable Power Macro-Model for Datapath Components
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
An Approximate Multiplane Network-on-Chip
Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories
Search-in-Memory (SiM): Conducting Data-Bound Computations on Flash Chip for Enhanced Efficiency
Architectural Simulation in the Context of Behavioral Synthesis
Area Optimization of Analog Circuits Considering Matching Constraints
Nano Security: From Nano-Electronics to Secure Systems
Fast Computation of Data Correlation Using BDDs
ISPT-Net: A Noval Transient Backward-Stepping Reduction Policy by Irregular Sequential Prediction Transformer
Sequentially constructive concurrency: a conservative extension of the synchronous model of computation
Shape optimization of a power MOS device under uncertainties
High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions
Automated Traffic Scenario Description Extraction Using Video Transformers
A New Approach for Computation of Timing Jitter in Phase Locked Loops
Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Trident: A comprehensive timing error resilient technique against choke points at NTC
ROLDEF: RObust Layered DEFense for Intrusion Detection Against Adversarial Attacks
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks
Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks
Pareto front analog layout placement using Satisfiability Modulo Theories
An abstraction-guided simulation approach using Markov models for microprocessor verification
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications
A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms
Lessons learned from the EU project T-CREST
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
par-gem5: Parallelizing gem5's Atomic Mode
Formal model for system-level power management design
Performance optimal speed control of multi-core processors under thermal constraints
A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing
Verifying Instruction Set Simulators using Coverage-guided Fuzzing *
Fast and precise cache performance estimation for out-of-order execution
From exaflop to exaflow
Gaussian mixture error estimation for approximate circuits
Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifter
HOT TOPIC - Concurrent SoC development and end-to-end planning
Parametric Fault Diagnosis for Analog Systems Using Functional Mapping
Decision ordering based property decomposition for functional test generation
Preemption delay analysis for floating non-preemptive region scheduling
Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling
OC-DLRM: Minimizing the I/O Traffic of DLRM Between Main Memory and OCSSD
Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning
Graphical Model Debugger Framework for embedded systems
Fail-Operational Automotive Software Design Using Agent-Based Graceful Degradation
Avoiding false negatives in formal verification for protocol-driven blocks
Exploring topologies for source-synchronous ring-based network-on-chip
Deep Learning-Based Circuit Recognition Using Sparse Mapping and Level-Dependent Decaying Sum Circuit Representations
A scalable method for the generation of small test sets
ReRAM-based accelerator for deep learning
Wavefront Technology Mapping
ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory
A 370-MHz memory built-in self-test state machine
Microarchitectural support for program code integrity monitoring in application-specific instruction set processors
A detailed methodology to compute Soft Error Rates in advanced technologies
Maximizing IO performance via conflict reduction for flash memory storage systems
Low-cost checkpointing in automotive safety-relevant systems
HyAtten: Hybrid Photonic-Digital Architecture for Accelerating Attention Mechanism
Error correction in single-hop wireless sensor networks - A case study
Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs
A universal communication model for an automotive system integration platform
Formulation of Design Space Exploration Problems by Composable Design Space Identification
Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective
TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware
Proven correct monitors from PSL specifications
Engineering trust with semantic guardians
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits
Securing a RISC-V architecture: A dynamic approach
Estimation of Linux Kernel Execution Path Uncertainty for Safety Software Test Coverage
AstroByte: Multi-FPGA Architecture for Accelerated Simulations of Spiking Astrocyte Neural Networks
Testing of Quantum Dot Cellular Automata Based Designs
CALLOC: Curriculum Adversarial Learning for Secure and Robust Indoor Localization
Scalar Metric for Temporal Locality and Estimation of Cache Performance
A Novel Delay Calibration Method Considering Interaction between Cells and Wires
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
How to use Knowledge in an Analysis Process
1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA
Cute-Lock: Behavioral and Structural Multi-Key Logic Locking Using Time Base Keys
Efficient Spectral-Aware Power Supply Noise Analysis for Low-Power Design Verification
dibSIM: a parallel functional logic simulator allowing dynamic load balancing
A Data Center Demand Response Policy for Real-World Workload Scenarios in HPC
An hybrid architecture to detect transient faults in microprocessors: An experimental validation
Sparsity-Aware Caches to Accelerate Deep Neural Networks
Space sensitive cache dumping for post-silicon validation
Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip
Incremental ABV for functional validation of TL-to-RTL design refinement
Application-specific memory performance of a heterogeneous reconfigurable architecture
GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing
Compositional analysis of switched ethernet topologies
Control Flow Driven Splitting of Loop Nests at the Source Code Level
A low-power, high-performance approximate multiplier with configurable partial error recovery
The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation
Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries
Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming
Processor Verification using Symbolic Execution: A RISC-V Case-Study
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor
A Design Methodology for the Exploitation of High Level Communication Synthesis
Utilization difference based partitioned scheduling of mixed-criticality systems
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches
Scrub Unleveling: Achieving High Data Reliability at Low Scrubbing Cost
PIMLC: Logic Compiler for Bit-Serial Based PIM
Heterogeneous multi-core platform for consumer multimedia applications
Polychrony for Refinement-Based Design
Sensitized path PUF: A lightweight embedded physical unclonable function
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis
NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions
Embedding Hardware Approximations in Discrete Genetic-Based Training for Printed MLPs
Evaluation of Interconnects with TDR
Data Freshness Optimization on Networked Intermittent Systems
User-specific skin temperature-aware DVFS for smartphones
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor
Supervisor synthesis for controller upgrades
A Heuristic for Test Scheduling at System Level
Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessor
A RRAM-based FPGA for Energy-efficient Edge Computing
Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues
Adaptive Droplet Routing for MEDA Biochips via Deep Reinforcement Learning
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory
SH-4 RISC microprocessor for multimedia, game machine
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling
Efficient minimization of fully testable 2-SPP networks
Security challenges in automotive hardware/software architecture design
High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches
A formal approach to design space exploration of protocol converters
On-chip source synchronous interface timing test scheme with calibration
Silicon proof of the intelligent analog IP design flow for flexible automotive components
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os
In-place memory mapping approach for optimized parallel hardware interleaver architectures
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm
A built-in quiescent current monitor for CMOS VLSI circuits
Symbolic Reliability Analysis and Optimization of ECU Networks
Incremental Online Verification of Dynamic Cyber-Physical Systems
Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers
FeFET and NCFET for Future Neural Networks: Visions and Opportunities
Fusion: A Safe and Secure Software Platform for Autonomous Driving
Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applications
Automated Masking of Software Implementations on Industrial Microcontrollers
Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGs
From embedded multi-core SoCs to scale-out processors
KalmMind: A Configurable Kalman Filter Design Framework for Embedded Brain-Computer Interfaces
Design automation for IEEE P1687
Process Variation Aware Issue Queue Design
Functional verification methodology based on formal interface specification and transactor generation
A flexible BIST strategy for SDR transmitters
Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
A Flexible Object-Oriented Software Architecture for Smart Wireless Communication Devices
A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level
Efficient Design Validation Based on Cultural Algorithms
A neural machine interface architecture for real-time artificial lower limb control
Self-Aware MIMO Beamforming Systems: Dynamic Adaptation to Channel Conditions and Manufacturing Variability
Towards Specification and Testing of RISC-V ISA Compliance ⋆
Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW