yusuke1997/dblp-id-title huggingface dataset:
Ultra-low voltage wideband inductorless balun LNA with high gain and high IP2 for sub-GHz applications
Static timing analysis based circuit-limited-yield estimation
A new recursive algorithm for estimating the adaptive function coefficients autoregressive (AFAR) models in impulsive noise environment
A Hierarchical Multiprocessor Achitecture for Video Coding Applications
Wideband Optical Fiber Signal Transmission System of 300MHz Bandwidth Using LED
Uniform Circular Broadband Beamformer with Selective Frequency and Spatial Invariant Region
A reconfigurable parallel FPGA accelerator for the adapt-then-combine diffusion LMS algorithm
Towards Ultra-Low-Power Realization of Analog Joint Source-Channel Coding using MOSFETs
A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications
Parameterized and low power DSP core for embedded systems
A 1 Gbps UWB OOK Receiver with Double PLL All-Digital CDR and Data Packet Re-Synchronizer
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator
Fast sensitivity analysis of transmission line networks
A wide band CMOS RF power detector
Compressed sensing SAR moving target imaging in the presence of basis mismatch
Robust video multicast under rate and channel variability with applications to wireless LANs
Analysis of nonlinear dynamic arrays, through spatial mode decomposition
Architecture and VLSI Design of a VLSI Neural Signal Processor
A Subharmonic Injection-Locked Self-Oscillating Mixer
A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions
A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit
On dynamic delay and repeater insertion
2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents
Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices
A 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interface
Hybrid neural network architecture for age identification of ancient Kannada scripts
A 9mW direct RF sampling GPS receiver front-end in 0.13µm BiCMOS
A high resolution FPGA-based merged delay line TDC with nonlinearity calibration
TinyBird-ML: An ultra-low Power Smart Sensor Node for Bird Vocalization Analysis and Syllable Classification
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator
Live Demonstration: IMU-based Human Activity Recognition towards Camptocormia Measurement at Home
Cryo-CMOS Mixed-Signal Circuits for Scalable Quantum Computing: Challenges and Future Steps
Single-inductor multiple-output switching converters with bipolar outputs
Adaptive power reconfigurability for decreasing power dissipation of wireless personal area network receivers
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic
A distortion model for pipeline Analog-to-Digital converters
Multi-layer scalable LPC audio format
Augmenting vector quantization with interval arithmetics for image-coding applications
Design of a Tunable Block Floating-Point Quantizer with Fractional Exponent
Real-time polygon extraction from complex images
Ultra-Low Latency and High Throughput Key-Value Store Systems Over Ethernet
An Analogue CMOS Defuzzication Circuit with Representation of Triangular Membership Functions
A congestion-driven buffer planner with space reservation
Live demonstration: A compact all-CMOS spatiotemporal compressed sensing video camera
Performance comparison of hybrid partial response detectors over frequency-selective fading channels
Area-efficient partial-clique-energy MRF pair design with ultra-low supply voltage
An Improved Temperature Compensation Technique for Current Biasing
A new low-voltage charge pump circuit for PLL
Spectral Approach to Logical Distribution-Free Classification Problem
Instantaneous Stereo Depth Estimation of Real-World Stimuli with a Neuromorphic Stereo-Vision Setup
Graphene-based, Frequency-Domain Self-Trigger for Low SNR Air Showers-induced Pulses
New Types of Digital Comparators
PARC: a new pyramidal FPGA architecture based on a RISC processor
Direct digital synthesizer with tunable phase and amplitude error feedback structures
Automated Programming of a Ring-Structured Multiprocessor Digital Filter IC
A low-power signal-recycling mixer and baseband amplifier with current reuse
Analysis and Implementation of DC-coupled Compact and Power Efficient Lumped Driver for Single-Ended Optical Modulators in SiGe 250 nm BiCMOS Technology
Transient sensitivity computation in circuit simulation
Design and optimization of integrated switching regulators using pre-computed lookup tables
A wide dynamic range and fast update rate integrated interface for capacitive sensors array
Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing
Very Low-power Flexible GF(p) Elliptic-curve Crypto-processor for Non-time-critical Applications
Nonylphenol biodegradation kinetics estimation using neural networks
Neuromorphic Autonomous Spiking Encoding
Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing
A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit
Digital offset compensation of time-interleaved ADC using random chopper sampling
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
Automatic Detection of Solder Joint Defects on Integrated Circuits
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling
Narrowband FSK Transceiver Circuit for Wireless Power and Data Transmission in Biomedical Implants
A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters
Detrended fluctuation analysis of brain hemisphere magnetic resonnance images to detect cerebral arteriovenous malformations
An Approach for Voiced/Unvoiced Decision of Colored Noise-Corrupted Speech
Low noise linear voltage regulator for use as an on-chip PLL supply in microprocessors
A 1.2 - 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS
CMOS dynamic comparators for pipeline A/D converters
Lightweight and CCA2-Secure Hardware Implementation of Binary Ring-LWE
A novel estimator for the velocity of a mobile station in a micro-cellular system
A low-voltage, low-power amplifier created by reasoning-based, systematic topology synthesis
Fast mesh-based motion estimation employing an embedded block model
Data harvesting from seabed-mounted observation instruments using optical wireless communication on underewater drone
Bifurcation analysis of on-chip LC VCOs
High-speed CMOS track-and-hold with an offset cancellation replica circuit
CAMC: A Multi-Chiplet Accelerator With Heterogeneous Memory-Based Computing Architecture For DNN Training
Architecture and implementation of a development board for low-power education
The use of reduced two's-complement representation in low-power DSP design
Passive rectifier/regulator combo circuits with embedded bandgap voltage reference
Design of Orthogonal Wavelet Filters with Minimum RMS Bandwidth Using A Symbolic Approach
A 2.8V RWDM BTL Class-D power amplifier using an FGMOS comparator
Spatially interleaved architecture for high-frequency data converters
SET and RESET pulse characterization in BJT-selected phase-change memories
Integrated circuit implementation of a cortical neuron
Carrier frequency offset estimation for OFDM systems
A Switched-Capacitor-Based Analog Computer for Solving the 1-D Wave Equation
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions
Design of multi-stage latency adders using detection and sequence-dependence between successive calculations
A novel readout technique for magnetoresistive sensors in automotive anti-lock braking systems
Channel characterization using jitter measurements
Modified predictive motion estimation for reduced-resolution video from high-resolution compressed video
A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers
Fault attack on FPGA implementations of Trivium stream cipher
L-simulator: a magPEEC-based new CAD tool for simulating magnetic-enhanced IC inductors of 3D arbitrary geometry
A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology
On segmented channel routability
A Transient-Enhanced Fully-Integrated LDO Regulator for SoC Application
A Low-complexity High-speed QR Decomposition Implementation for MIMO Receivers
Recursive Allpass Filter Design using Least-Squares Techniques
A sub-mA, high-gain CMOS low-noise amplifier for 2.4 GHz applications
Reducing logic encryption overhead through gate level key insertion
Improved hierarchial intra prediction based on adaptive interpolation filtering for lossless compression
Multi-Objective Strategies for Stripped-Functionality Logic Locking
Identifying translinear loops in the circuit topology
A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering
On the performance of TPC-based STBC coded MIMO-OFDM system over IMT2000 channels
A multimodal investigation of in vivo muscle behavior: System design and data analysis
A high resolution digital CMOS time-to-digital converter based on nested delay locked loops
Depth estimation and view synthesis for narrow-baseline video
On tri-state buffer inference in HDL synthesis
Open computation tree logic with fairness
A hardware accelerator for video segmentation using programmable morphology PE array
Biologically inspired artificial neural network algorithm which implements local learning rules
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs
An MDAC synapse for analog neural networks
A blind LWT-based audio watermarking using fast Walsh Hadamard transform and singular value decomposition
Interpolation based symmetrical predictor structure for lossless image coding
An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model
Time-delayed Network Reconstruction based on Nonlinear Continuous Dynamical Systems
ASP: A daptive Sparse LUT-based Bit-Slice Accelerator for Efficient CNN Inference
A new synthesis methodology for reliable RF front-end Design
SlimSeiz: Efficient Channel-Adaptive Seizure Prediction Using a Mamba-Enhanced Network
Adaptive filtering-based iterative channel estimation for MIMO wireless communications
A loudness enhancement technique for speech
Analytical mode-dependent rate and distortion models for H.264/SVC coarse grain scalability
Self-aware Cross-component Prediction Model Based on Template for Screen Content Coding
Sliding-Mode Voltage Control of Dynamic Power Supply for CCM
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction
Feedback Receivers: Specification and State-of-the-Art Review
Queue-based Spatiotemporal Filter and Clustering for Dynamic Vision Sensor
A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensors
Thermal aware timing budget for buffer insertion in early stage of physical design
Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC
Ziksa: On-chip learning accelerator with memristor crossbars for multilevel neural networks
A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix
Inductorless RF amplifier with tuneable band-selection and image rejection
A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators
A CMOS Inverter-Like Class-D/E Power Amplifier with No RF-Choke and No Dead-Time Requirement
Evaluating the Feasibility of Electrical Impedance Tomography for Monitoring Knee Angle and Muscle Strength: Towards Application in Total Knee Replacement Rehabilitation
Modeling dynamics of memristive nano-structures
Bifurcation from a 3-D hysteresis piecewise-constant circuit
Design and modeling of on-chip monolithic transformers with patterned ground shield
An Efficient Single Core Flexible Processor Architecture for 4096-bit Montgomery Modular Multiplication and Exponentiation
Optimization of frequency-response-masking based FIR filters with reduced complexity
Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters
A compensation technique for integrator's pole error in cascaded sigma-delta modulators
A low-voltage neutralised class AB switched-current technique
Enhancing HDR Video Compression based on Deep Effective Bit Depth Adaptation
Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks
Low-voltage bulk-driven mixer with on-chip balun
A resource balancing approach to SoC test scheduling
An ISFET Array for Ion Multiplexing with an Integrated Sensor Learning Algorithm
Annotated 3D Point Cloud Dataset for Traffic Management in Simulated Urban Intersections
Capacitive-Based Gesture Recognition System for Human-Machine Interface in Automotive Applications
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform
A novel metric representation for low-complexity log-MAP decoder
VLSI architectures for stereoscopic video disparity matching and object extraction
Low-Resource Hardware Architecture for Semi-Global Stereo Matching
Approach to Simulating Acoustics in Supersonic Flow by means of Multidimensional Vector-WDFs
Level Converting Scan Flip-flops
Wave digital filter based analog circuit emulation on FPGA
Reverse engineering of the visual system using networks of spiking neurons
The chemical current-conveyor: a new microchip biosensor
High Performance CMOS Macromodule Layout Synthesis
Application of Passive Nonlinear Network Concept in Digital Signal Processing
SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation
Automatic face recognition system using neural networks
A new approach for controlling series-connected IGBT modules
A Novel Fast Algorithm based on SMDWT for Visual Processing Applications
Proving Stability of Delta-Sigma Modulator Using Invariant Sets
Robust watermarking of music signals by cepstrum modification
Spintronic devices for ultra-low power neuromorphic computation (Special session paper)
A new class of even length wavelet filters
A low power thyristor-based CMOS programmable delay element
A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension
A High Dynamic Range 100Mhz AGC-Amplifier with a Linear and Temperature Compensated Gain Control
Community detection enhancement in networks using proper weighting and partial synchronization
Tolerance analysis for electronic circuit design using the method of moments
A current-mode stimulator circuit with two-step charge balancing background calibration
Piecewise Linear Chaotic Maps in Current Mode CMOS Circuits: Nonlinear Distortion Analysis
A Fast 2-D Convolution Technique for Deep Neural Networks
Design of FlexRay-MOST gateway using static segments and control messages
A fast FPGA-based deep convolutional neural network using pseudo parallel memories
MOSGRAD-a tool for simulating the effects of systematic and random channel parameter variations
Design Techniques Aimed at 3 Volt CMOS Delta Sigma Converters
Statistical Analysis Based H.264 High Profile Deblocking Speedup
11 GHz UGBW Op-amp with feed-forward compensation technique
Hardware Architecture of an SVD based MIMO OFDM Channel Estimator
A 180-nW static power UWB IR transmitter front-end for energy harvesting applications
Low-dropout regulators: Hybrid-cascode compensation to improve stability in nano-scale CMOS technologies
High quality Motion JPEG2000 coding scheme based on the human visual system
A genetic algorithm for determining multiple routes and its applications
DSP engine design for LINC wireless transmitter systems
A Sequential Constrained Least-Square Method for Minimax Design of Linear-phase FIR filters with Time-domain Constraints
A Second Generation Linear Low Voltage BiCMOS OTA
Semi-iterative analog turbo decoding
Behavioral synthesis of asynchronous systems: a methodology
Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators
A TCMS-based architecture for GALS NoCs
Combining sdm-based circuit switching with packet switching in a NoC for real-time applications
A Design Scheme to Stabilize the Active Gain Enhancement Amplifier
A Semi-blind Algorithm for Most Significant Tap Detection in Channel Estimation of OFDM Systems
Using FPGAs to solve the Hamiltonian cycle problem
Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops
A memristive astable multivibrator based on 555 timer
A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process
NCOD: Near-Optimum Video Compression for Object Detection
Fractional-Order Shelving Filter Designs for Acoustic Applications
Wavelet analysis of current measurements for mixed-signal circuit testing
Rate-Optimal Static Scheduling of DSP Data Flow Graphs onto Multiprocessors using Circuit Contraction
Design issues on request migration for video-on-demand services
Multifunctional RF Transmitters for Next Generation Wireless Transceivers
Fine timing synchronization using power delay profile for OFDM systems
A complete spurs distribution model for direct digital period synthesizers
Active noise control with bias free pre-inverse adaptive system
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity
Challenges and directions of ultra low energy wireless sensor nodes for biosignal monitoring
Wearable Bowel Sound Monitoring with Quality Enhancement using U-net
A high speed low power CMOS clock driver using charge recycling technique
A PPM Gaussian pulse generator for ultra-wideband communications
On Periodically Time-Varying Two-Dimensional State-Space Filters
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
Novel ultra low voltage transconductance amplifier
An improved model for delay/energy estimation in near-threshold flip-flops
Performance of a Quasi-Newton Adaptive Filtering Algorithm for a CDMA Indoor Wireless System
A current-mode spiking neural classifier with lumped dendritic nonlinearity
High-speed Fluorescence Imaging System for Freely Moving Animals
A phase-shift self-oscillating stereo class-D amplifier for battery-powered applications
Parameter optimization of deterministic dynamic element matching DACs for accurate and cost-effective ADC testing
IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020
Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition Graphs
Object-based rate control for MPEG-4 video object coding
Lattice Wave Digital Filter Design for Arbitrarily Specified Amplitude Characteristics by Phase Approximation
Region detection using color similarity
A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift
High-speed high-precision analog rank order filter in CMOS technology
A cost effective architecture design of inverse quantization and multichannel processing for MPEG-2 audio decoding
Design Constraint on Feedback Gain Vector of Switching Regulators for Local Stability
Global Interconnect Optimization in the Presence of On-chip Inductance
A new NMOS four-quadrant analog multiplier
High frequency and low power semi-synchronous PFM state machine
Design of high-order type-II delay-locked loops using a Gaussian transfer function approach
An Energy Efficient Implementation of On-demand MAC Protocol in Medical Wireless Body Sensor Networks
Transform domain energy modeling of natural images for wireless SoftCast optimization
Universal discrete model and linear algebra representation for variant OFDM-CDMA systems
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning
Path Planning for Semi-Flocking-Controlled Mobile Sensor Networks on Mobility Maps
Investigation of state transition phenomena in cross-coupled chaotic circuits
VLSI systolic array architecture for the lattice structure of the discrete wavelet transform
Analysis of Section Scaling for Multiple-Size DLD Microfluidic Particle Separation
Asymptotic Stability of Linear Shift-Variant Difference Equations with Diamond-Shaped Uncertainties
Modular and efficient architecture for H.263 video codec VLSI
Designing Complex Delta Sigma Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation
Zero-crossing-prediction-based Single-slope ADC with a Constant Charge Bias Amplifier for Low Power Image Sensors
Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits
Use of Common Parts in Masking Filters for Complexity Reduction in FRM-Based FIR Filters
Anew algorithm for motion-compensated frame interpolation
A Timing Skew Calibration Method for Time-Interleaved FATI ADCs
A mm-wave analog adaptive array with genetic algorithm for interference mitigation
A ± 1.5 V high frequency four quadrant current multiplier
The Influence of Text-guidance on Visual Attention
Flux harmonic spectrum processing of direct torque controlled induction motor
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters
A second-order cone programming approach for minimax design of 2-D FIR filters with low group delay
Synthesis of hybrid filter banks by global frequency domain least square solving
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads
Approximation Algorithms for the k-Edge-Connectivity Augmentation Problem
A SPT treatment to the bit serial realization of the sign-LMS based adaptive filter
On the implementation of mceliece with CCA2 indeterminacy by SHA-3
Accurately weighting subbands in temporal wavelet transform
Efficient Integer-Arithmetic-Only Convolutional Networks with Bounded ReLU
Noise Immune, Low-Skew, Pulse Width Retainable Analog Glitch-Filter
Boundary Filters for Finite-Length Signals and Time-Varying Filter Banks
Cooperative dynamics coordinated by stochastic noise in a multi-cell system
Twisted Transformers for Low Coupling RF and Mixed Signal Applications
Quantitative Indicators for Quality of Fit Assessment in Power System Model Validation Problems
A noise cancelling envelope detector for low power wireless sensor applications
A new CAM based S/S -1 -box look-up table in AES
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits
A 1.6MHz Swing-Boosted Relaxation Oscillator with ±0.15%/V 23.4ppm/°C Frequency Inaccuracy using Voltage-to-Delay Feedback
A 40 nm CMOS T/H-less flash-like stroboscopic ADC with 23dB THD and >50 GHz effective resolution bandwidth
An Always-On tinyML Acoustic Classifier for Ecological Applications
A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs
Approximate In-Memory Computing using Memristive IMPLY Logic and its Application to Image Processing
Fundamental Limits on the Computational Accuracy of Resistive Crossbar-based In-memory Architectures
Resource-Efficient FPGA Implementation of Advanced Encryption Standard
Impact of Physical Design on PUF Behavior: A Statistical Study
Estimation of time-varying autocorrelation and its application to time-frequency analysis of nonstationary signals
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage
Reaction-diffusion CNN chip. II. Applications
Ultra-low-power flash memory in standard 0.35µm CMOS for passive microwave RFID transponders
Low power real time electronic neuron VLSI design using subthreshold technique
Sensitivity-enhanced OEIC with capacitance multiplier for reduced lower-cutoff frequency