yusuke1997/dblp-id-title huggingface dataset:
Machine Learning-Based Tomato Leaf Disease Diagnosis Using Radiomics Features
Tuning Wavelength of the Localized Mode Microcavity by Applying Different Oxygen Flows
Quantum-Inspired Neural Network on Handwriting Datasets
Authentication and Transaction Security in E-business
Privacy in Danger: Let's Google Your Privacy
Design for Security Functions of Chipboard Software
Privacy and Computing: a Cultural Perspective
Design and Analysis of a Practical E-Voting Protocol
OECD 'Guidelines for the Security of Information Systems"
A Survey on Non-transferable Anonymous Credentials
On the Fundamentals of Anonymity Metrics
A Method of Detecting and Eradicating Known and Unknown Viruses
Location Privacy Issues in Wireless Sensor Networks
Privacy Awareness: A Means to Solve the Privacy Paradox?
Protection of the Proprietary Information of Organisations in the Asian-Pacific Region
The Relationship between Data Protection Legislation and Information Security Related Standards
Marrying Transparency Tools with User-Controlled Identity Management
Identity Management Systems in Healthcare: The Issue of Patient Identifiers
Moral identification in Identity Management Systems
History of Privacy
Security Policy Satisfiability and Failure Resilience in Workflows
On the Internet, Things Never Go Away Completely - The growing problem of Internet data persistence
Comparing Identity Management Frameworks in a Business Context
Putting Identifiers in the Context of eHealth - Introduction of a Model
Automating Identity Management and Access Control
A Model-based Analysis of Tunability in Privacy Services
Security and Control of Information Technology in Society, Proceedings of the IFIP TC9/WG9.6 Working Conference on Security and Control of Information Technology in Society on board M/S Illich and ashore at St. Petersburg, Russia, 12-17 August, 1993
Social and Political Dimensions of Identity
Traffic Flow Confidentiality in IPsec: Protocol and Implementation
Applied Ethics and eHealth: Principles, Identity, and RFID
Testing Privacy Awareness
Recent Development in Information Technology Security Evaluation - The Need for Evaluation Criteria for Multilateral Security
Data Protection and the Use of Biometric Data in the EU
Information Technology versus Security in Russia
Young People's Gender and Identity Work in a Swedish Internet Community
User Control Problems and Taking User Empowerment Further
Using Identity-Based Public-Key Cryptography with Images to Preserve Privacy
The Need for a Paradigm Shift in Addressing Privacy Risks in Social Networking Applications
On the Cutting Edge between Privacy and Security
The SBC Model as a Conceptual Framework for Reporting IT Crimes
Self, Script, and Situation: identity in a world of ICTs
Generic Predefined Privacy Preferences for Online Applications
Identity Deployment and Management in Wireless Mesh Networks
ICT and Social Work: a Question of Identities?
Software Security - The Dangers of Abstraction
The Future of Identity in the Information Society - Proceedings of the Third IFIP WG 9.2, 9.6/ 11.6, 11.7/FIDIS International Summer School on The Future of Identity in the Information Society, Karlstad University, Sweden, August 4-10, 2007
Education in IT Security at Bachelor and Master Levels Using a Systemic-Holistic Approach
Data Retention and Anonymity Services - Introducing a New Class of Realistic Adversary Models
Security of Wireless Communication
Symbiosis Among IT Security Standards, Policies, and Criteria
When Spiders Bite: The Use, Misuse, and Unintended Consequences of "Silent Information"
Preparation of Specialists in the Area of Information Technology Security
Privacy in the Metaverse - Regulating a complex social construct in a Virtual World
Is International Law on Security of Information Systems Emerging?
An Overview of Electronic Passport Security Features
Identification and Tracking of Individuals and Social Networks using the Electronic Product Code on RFID Tags
The Future of Identity in the Information Society - 4th IFIP WG 9.2, 9.6/11.6, 11.7/FIDIS International Summer School, Brno, Czech Republic, September 1-7, 2008, Revised Selected Papers
Enhancing Multilateral Security in and by Reputation Systems
The Conference in Perspective
Implantable RFID Chips - Security versus Ethics
Privacy implications of RFID: an assessment of threats and opportunites
Computer Crime in Slovakia
A Survey on Transparency Tools for Enhancing Privacy
Utopians, Cyberpunks, Players, and Other Computer Criminals: Deterrence and the Law
A Forensic Framework for Tracing Phishers
Knowledge Based Organization - An identification model
The Day at St Petersburg
Collaborative Knowledge Networks - Lessons to Learn from a Large Automotive Company
Privacy-friendly Identity Management in eGovernment
The Current State of INFOSEC Legislation
Enterprise Identity Management - What's in it for Organisations?
Preparing System Security Policies
Privacy and Data Protection in a User-Centric Business Model for Telecommunications Services
Investigating Anonymity in Group Based Anonymous Authentication
Digital Identity and Anonymity - Desi Manifestations and Regulation
A Decomposition-Based Memristive Crossbar Solver and FPGA-Accelerated Hardware Implementation
An Effective Macro Placement Framework with Reinforcement Learning and Monte Carlo Tree Search
Asymmetric-access aware optimization for STT-RAM caches with process variations
How Vulnerable are Large Language Models (LLMs) against Adversarial Bit-Flip Attacks?
LDAX : A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis
M2VT: A Multi-Output Encoder Accelerator for Multiple-Way Video Transcoding
New performance/power/area efficient, reliable full adder design
Simplified delay design guidelines for on-chip global interconnects
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM
On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques
5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
New timing and routability driven placement algorithms for FPGA synthesis
A congestion-driven placement framework with local congestion prediction
A VLSI-based digital multilayer neural network architecture
Skew-bounded low swing clock tree optimization
ARCS: an architectural level communication driven simulator
A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier
Design topology aware physical metrics for placement analysis
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs
An evolutionary approach for standard-cell library reduction
Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations
Energy efficient architecture of sensor network node based on compression accelerator
A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010
Partitioning Algorithms for Corner Stitching
Automated verification of temporal properties specified as state machines in VHDL
Orthogonal code generator for 3G wireless transceivers
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs
Co-optimization of TSV assignment and micro-channel placement for 3D-ICs
Active shields: a new approach to shielding global wires
An automated unique tagging system using CMOS process variation
Performance verification of high-performance ASICs using at-speed structural test
Harvesting-aware energy management for multicore platforms with hybrid energy storage
DARPA's Data Driven Discovery of Models (D3M) and Software Defined Hardware (SDH) Programs
DFM: swimming upstream
Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory
A Bootstrapped NMOS Charge Recovery Logic
Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization
In-order pulsed charge recycling in off-chip data buses
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions
A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults
Maximizing memory data reuse for lower power motion estimation
Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test
A framework for 1-D compaction with forbidden region avoidance [VLSI layout]
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors
A nine-context programmable optically reconfigurable gate array with semiconductor lasers
A New Full Adder Cell for Low-Power Applications
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
A countermeasure against power analysis attacks for FSR-based stream ciphers
VLSI routing on the pipelined hypercube and related networks
P-ReTI: Silicon Photonic Accelerator for Greener and Real-Time AI
12bits 40mhz pipelined ADC with duty-correction circuit
Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
A Placement Optimization Framework for Non-Integer Multiple-Height Cells
A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
A Scalable, Deterministic Approach to Stochastic Computing
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004
Buffering of frequent accesses for reduced cache aging
Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic Hardware
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty
A novel 32-bit scalable multiplier architecture
An Exact Input Encoding Algorithm for BDDs Representing FSMs
The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits
hChain: Blockchain Based Healthcare Data Sharing with Enhanced Security and Privacy Location-Based-Authentication
A High-accurate Multi-objective Ensemble Exploration Framework for Design Space of CPU Microarchitecture
HW/SW partitioning using discrete particle swarm
Impact of Error Rate Misreporting on Resource Allocation in Multi-tenant Quantum Computing and Defense
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer
Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning
Complementary nano-electromechanical switches for ultra-low power embedded processors
Cluster miss prediction for instruction caches in embedded networking applications
Process variation mitigation via post silicon clock tuning
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators
Wiring pitch integrates MCM design domains
PositCL: Compact Continual Learning with Posit Aware Quantization
Reducing temperature variability by routing heat pipes
Resource-Constrained Algebraic Transformation for Loop Pipelining
Gate-Level Models for Fast Cross-Level Power Density Estimation
An Exploration of a Heterogeneous Neural Configuration of SNNs
Novel architectures for efficient (m, n) parallel counters
Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs
Protected IP-core test generation
Enhancing Information Security Courses With a Remotely Accessible Side-Channel Analysis Setup
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits
Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry
VLSI implementation of an automatic Q tuning system
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks
XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism
Detecting Hardware Trojans using Model Guided Symbolic Execution
Quantum Image Processing: A Comparative Study of NEQR and FRQI Encoding Schemes with Hybrid Processing
On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results
An energy-efficient truly all-digital temperature sensor for SoC applications
RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable Convolution
DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTL
Computing Complex Functions using Factorization in Unipolar Stochastic Logic
KDTree-SOM: Self-organizing Map based Anomaly Detection for Lightweight Autonomous Embedded Systems
Comprehensive Analysis of Generated Single Event Transients in Most Common Logic Cells of Skywater's 130-nm Technology
Dynamic Beam Width Tuning for Energy-Efficient Recurrent Neural Networks
A low power based system partitioning and binding technique for multi-chip module architectures
Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-Chip
Analysis of Adaptive CMOS Down Conversion Mixers
Enhancing error resilience for reliable compression of VLSI test data
SCALENet: A SCalable Low power AccELerator for Real-time Embedded Deep Neural Networks
Hardware Assurance: Trojans, Counterfeits, and Security in an Interconnected World
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI
Adapting Convolutional Neural Networks for Indoor Localization with Smart Mobile Devices
Implementation analysis of NoC: a MPSoC trace-driven approach
Performance driven standard-cell placement using the genetic algorithm
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip
Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP Systems
TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations
Run-time energy management of manycore systems through reconfigurable interconnects
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array
Two-layer via-free routing in channels and switchboxes
A simulation methodology for reliability analysis in multi-core SoCs
Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects
T-algorithm-based logic simulation on distributed systems
DPQ-HD: Post-Training Compression for Ultra-Low Power Hyperdimensional Computing
A new decompression system for the configuration process of SRAM-based FPGAS
Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption
MAYAVI: A Cyber-Deception Hardware for Memory Load-Stores
qMC: A Formal Model Checking Verification Framework For Superconducting Logic
A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration
Clock-Wirelength-Driven Detailed Placement
True In-memory Computing with the CRAM: From Technology to Applications
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs
Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias
In-Memory Computing: The Next-Generation AI Computing Paradigm
Simulation of reconfigurable memory core yield
RAPA: reliability-aware priority arbitration strategy for network on chip
A New Routing Strategy to Improve Success Rates of Quantum Computers
An automated design approach to map applications on CGRAs
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation
Automated formal verification of scheduling with speculative code motions
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits
A protocol extraction strategy for control point insertion in design for test of transition signaling circuits
CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links
RT level reliability enhancement by constructing dynamic TMRS
Fast and accurate wire delay estimation for physical synthesis of large ASICs
An approximation algorithm for fully testable kEP-SOP networks
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing
A zero-overhead IC identification technique using clock sweeping and path delay analysis
Instruction scheduling using MAX-MIN ant system optimization
The Applications of NVM Technology in Hardware Security
Noise estimation due to signal activity for capacitively coupled CMOS logic gates
Investigating modern layout representations for improved 3d design automation
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density
Enabling architectural innovations using non-volatile memory
A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes
Unified architecture level energy-efficiency metric
An optimal algorithm for maximum two planar subset problem [VLSI layout]
Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery
An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)
Low power high speed analog-to-digital converter for wireless communications
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table
Graphene-PLA (GPLA): a Compact and Ultra-Low Power Logic Array Architecture
A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation
Low power test generation for path delay faults using stability functions
Real-time address trace compression for emulated and real system-on-chip processor core debugging
Congestion Mitigation During Placement
LPN-based Device Authentication Using Resistive Memory
Topological via minimization and routing
Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators
A novel low-power and in-place split-radix FFT processor
STEP: a unified design methodology for secure test and IP core protection
Synergistic integration of code encryption and compression in embedded systems
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement
Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
On the Effectiveness of Piecewise Activation Approximations for Long-Term Short-Memory Networks
An effective approach for large scale floorplanning
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V
DRMA: dynamically reconfigurable MPSoC architecture
A Method for Phase Noise Analysis of RF Circuits
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
Dummy fill aware buffer insertion during routing
Resiliency in Connected Vehicle Applications: Challenges and Approaches for Security Validation
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits
A GF(p) elliptic curve group operator resistant against side channel attacks
Experiences with Remote Teaching an Embedded Systems Course
A buffered crossbar-based chip interconnection framework supporting quality of service
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices
Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation
FEKIS: a fast architecture-level thermal analyzer for online thermal regulation
CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarker
Exploring Generalization of Shoup Modular Multiplier
A comparison of FinFET based FPGA LUT designs
A 65 nm CMOS low power RF front-end for L1/E1 GPS/Galileo signals
High performance data-path synthesis via communication metrics
Voltage-Boosted Synchronizers
Power Reducing Techniques for Clocked CMOS PLAs
Neural system design with the integrated neurocomputing architecture
A novel buffer circuit for energy efficient signaling in dual-VDD systems
Session details: Session 6A: Special Session -1: Machine Learning and Hardware Attacks
Improved timing closure by early buffer planning in floor-placement design flow
Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM
Session details: Session 6B: Special Session - 2: Application-oriented Hardware Security Challenges and Solutions
Single-Pass Symbolic Learning for Real-Time Embedded Security
MB-FICA: multi-bit fault injection and coverage analysis
Improving the Quality of the High-Level Synthesis Estimation Results through Multi-Level Predictive Models
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications
Green Computing: New Challenges and Opportunities
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems
Optimizing Reliability and Energy Efficiency in Heterogeneous Multicore Systems: A Novel Task Deployment Strategy
MPEG-2 Video Decoder for DVD
An Efficient Distributed Machine Learning Inference Framework with Byzantine Fault Detection
Cooling of integrated circuits using droplet-based microfluidics
A Tutorial-style Single-cycle Fast Fourier Transform Processor
Algorithm and Hardware Support for Branch Anticipation
MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache
Optimum wire sizing of RLC interconnect with repeaters
Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits
AI-Powered Knowledge Graphs for Neuromorphic and Energy-Efficient Computing
A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design
Enhancing Solver-based Generic Side-Channel Analysis with Machine Learning
A multi-stage leakage aware resource management technique for reconfigurable architectures
BPhoton-CNN: An Ultrafast Photonic Backpropagation Accelerator for Deep Learning
Compiler assisted architectural exploration for coarse grained reconfigurable arrays
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design
Efficient shift-adds design of digit-serial multiple constant multiplications
Memory Unit Design for Real Time DSP Applications
Design and Implementation of Real-Time Multi-sensor Vision Systems
A new paradigm for general architecture routing
A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning
Design Recovery for Incomplete Combinational Logic
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation
A Deep Multimodal Representation Learning Framework for Accurate Molecular Properties Prediction
Minimum implant area-aware gate sizing and placement
MEDASec: Logic Encryption Scheme for Micro-electrode-dot-array Biochips IP Protection
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test
Why Is It So Hard to Make Secure Chips?
An efficient model for frequency-dependent on-chip inductance
54x54-bit radix-4 multiplier based on modified booth algorithm