yusuke1997/dblp-id-title huggingface dataset:
Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications
Least squares IIR filter design on a logarithmic frequency scale
Live demonstration: A 768 × 640 pixels 200Meps dynamic vision sensor
AGMixer: Age Estimation Using Gender Feature and Improved Ordinal Loss
A quadrature-modulator for 0.6-2.6 GHz with frequency doubler
Cluster-based informed agents selection for flocking with a virtual leader
A computationally efficient scheme for estimating linear noisy input-output systems
Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection
Computation of projections and eigen distribution in half-planes and disks
A new CMOS readout circuit for uncooled bolometric infrared focal plane arrays
A Single-Wavelength Photonic Network on Chip Design Based on Optical Orthogonal Codes
A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application
Efficient VLSI Architecture of Bluestein's FFT for Fully Homomorphic Encryption
Low-voltage floating-gate CMOS buffer
Rules for systematic synthesis of all-transistor analogue circuits by admittance matrix expansion
Information security display system based on temporal psychovisual modulation
A runtime auto scalable power-efficient instruction-cache design
Stability Test for 2-D LSI System Via a Unit Circle Test for Complex Polynomials
Wideband Digitally Controlled True Time Delay for Beamforming in a 40 nm CMOS Technology
Detection of quatratic interaction in signals using the Wigner bispectrum
Low-latency Buffering for Mixed-precision Neural Network Accelerator with MulTAP and FQPipe
An SOI 4 transistors self-refresh ultra-low-voltage memory cell
An Error-Surface-Based Fractional Motion Estimation Algorithm and Hardware Implementation for VVC
An LSSD Compliant Scan Cell for Flip-Flops
SNR measurement based on linearity test for ADC BIST
A Parallel Force Direct Based VLSI Standard Cell Placement Algorithm
A 12-bit SAR ADC with background self-calibration based on a MOSCAP-DAC with dynamic body-biasing
SSDC: A Scalable Sparse Differential Checkpoint for Large-scale Deep Recommendation Models
Design and Data Management for Magnetic Racetrack Memory
A fast block matching for SIMD processors using subsampling
Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture
A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement
Quantum computing and quantum complexity theory
Device Engineering Strategy of Zr-Doped HfOx Ferroelectric Memory for Unconventional Computing Applications
Low Frequency Rotary Traveling Wave Oscillators
IIR M-Th Band Filters with Allpass Components
A DVS-CIS Sensor Data Receiver on FPGA with a 10 Gbps MIPI Controller
Extra Bit Generation for High-Speed Time-Based Flash ADCs in 65nm CMOS
P2E-LGAN: PPG to ECG Reconstruction Methodology using LSTM based Generative Adversarial Network
Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN
A SPAD Based dToF Pixel with Log/Linear Multi-mode Operation for LiDAR Applications
1.5V CMOS current reference with extended temperature operating range
Power-efficient, gate-based Digital-to-Time converter in CMOS
An all-digital data recovery circuit optimization using Matlab/Simulink
Circuit modeling to predict the performance of force-cooled cold plate structures
The design of a multi-mode/multi-system capable software radio receiver
A Compact 11-Bit Source-Driver with Adder-Embedded Hybrid DAC for Mobile OLED Displays
SoC platform based design of MPEG-2/4 AAC audio decoder
CMOS bulk input technique
Perceptual image quality assessment combining free-energy principle and sparse representation
On the basins of attraction of parallel connected buck switching converters
Live Demonstration: A Video Denoising Co-processor with Non-local Means Algorithm for FHD 30fps Image Sensor
Chaotic behavior of the Newton-Raphson method with the optimal multiplier for ill-conditioned power systems
Approximating Nonlinear Activation Function Using Genetic Programming
On IIR Filter Design
Synthesis and optimization of analog VLSI filters from VHDL-AMS parse trees
Emerging resistive memories for low power embedded applications and neuromorphic systems
Efficient Reprogramming of Memristive Crossbars for DNNs: Weight Sorting and Bit Stucking
A low distortion and fast settling automatic gain control amplifier in CMOS technology
Low-Complexity and Reliable Moving Objects Detection and Tracking for Aerial Video Surveillance with Small UAVS
A high-PSRR and low-noise CMOS-based reference with barrel shifting and notch filtering
Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ
An area efficient digital amplitude modulator in 90nm CMOS
Modeling sigma-delta modulator non-idealities in SIMULINK(R)
On the exact realisation of LC ladder finite transmission zeros in log-domain: a theoretical study
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration
A novel topology in reversed nested miller compensation using dual-active capacitance
"Noninvasive" techniques for syllabic companding in signal processors
Optimized dynamic translinear implementation of the Gaussian wavelet transform
A property of Jacobian matrices and some of its consequences
Stability issues in cascade connected switching converters for DC microgrid applications
A low power 2.4 GHz front end with MEMS lattice based channel filtering at RF
Energy-efficient time-interleaved and pipelined SAR ADCs
A Multi-Farm Irrigation Scheduling System (MISS) for Arid and Semi-Arid Regions: A Realistic Scenario
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations
On the synchronization region in networks of coupled oscillators
Feasibility of B-mode diagnostic ultrasonic energy transfer and telemetry to a cm 2 sized deep-tissue implant
Comparison of two class E amplifiers for EER transmitter
Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver
Inductor-current zero-crossing detection mixed-signal CMOS circuit for a DCM-operated 3-level switching power converter
Chaos Detection in Time Series: A Statistical Approach
Design and implementation of an H infinity controller for a bi-directional DC-DC converter
Gradient based interpolation for division of focal plane polarization imaging sensors
Excitatory and Inhibitory Memristive Synapses for Spiking Neural Networks
Virtual Network Embedding for Switch-Centric Data Center Networks
Low-power and low-area CMOS quadrature RC oscillator with capacitive coupling
Hybrid trigonometric differential evolution for optimizing harmonic distribution
A 0.8µm CMOS programmable IIR SC filter
Pupil localization for gaze estimation using unsupervised graph-based model
Identifying systematic spatial failure patterns through wafer clustering
An ultra low-power low-voltage programmable temperature detection circuit
Intercell Wireless Communication in Software-defined Metasurfaces
Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit
Short-circuit power analysis of an inverter driving an RLC load
A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning
Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle
A linear transconductor and its application in an analog filter in 120nm CMOS
Implementation of Floating Charged Memristor Emulator utilizing DVCCTA
An Orthogonal Pulse Amplitude Modulation Signaling for High-Speed Wireline Communications
Rosenstark-like Representation of Feedback Amplifier Resistance
A many-core platform implemented for multi-channel seizure detection
Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices
Data-Free Network Pruning for Model Compression
A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters
A Burst-mode Cryogenic Thermal Imager Readout IC with Spatial and Temporal Compression
Synchronization of two LC- oscillators using capacitive coupling
A Compact 25-32 GHz High IMRR Double Quadrature CMOS Transmitter for 5G Applications
On noise-to-state stability of random nonlinear systems with switchings
A free but efficient class AB two-stage operational amplifier
A Novel Deep Learning Model for Link Prediction of Knowledge Graph
Highly Reliable PUF Circuits Using Efficient Post-Processing Stabilization Technique
An industry-driven laboratory development for mixed-signal IC test education
Novel universal active block: a universal current conveyor
Analyzing mixed carbon nanotube bundles: A current density study
A least-squares based method for IIR filtering with noisy input-output data
Large-signal simulation of a distributed power supply system with power factor correction
Design of a Reconfigurable Multi-Sensor Testbed for Autonomous Vehicles and Ground Robots
A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator
A 2.8 nV/√ Hz Chopper Amplifier for Bridge Readout with Dual Ripple Reduction and Noise- Nonlinearity -Cancelling Loop
On Model Parameter Estimation for H.264/AVC Rate Control
Functional modeling techniques for a wireless LAN OFDM transceiver
Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits
CAR-Lite: A Multi-Rate Cochlea Model on FPGA
A precise 90° quadrature OTA-C VCO between 50-130 MHz
All-digital High-dynamic Automatic Gain Control
Monolithic CMOS HD radio: Architecture design and front-end implementation
Practical operation considerations for memristive integrating sensors
Design and implementation of passive memristor emulators using a charge-flux approach
Measurement verification of estimation method for time errors in a time-interleaved A/D converter system
Efficient Edge Matching using Improved Hierarchical Chamfer Matching
In-situ Monitoring for Slack Time Violation Without Performance Penalty
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing
VeriBench: Benchmarking Large Language Models for Verilog Code Generation and Design Synthesis
Low-power digital filtering using approximate processing with variable canonic signed digit coefficients
Efficient Recursive Computation of 1D and 2D-Quincunx IIR Wavelets
Disposable CMOS passive RFID transponder for patient monitoring
Incorporating Immediate Online Feedback System and Concept Map into Electrical Circuits Course
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach
An analysis of matching in the Tau cell log-domain filter
A novel implementation of dithered digital delta-sigma modulators via bus-splitting
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events
A 16-valued logic FPGA architecture employing analog memory circuit
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW
On inconsistent initial conditions for linear time-invariant differential-algebraic equations
A 36-V H-bridge driver interface in a standard 0.35-μm CMOS process
A novel MPEG-4 rate control method with spatial resolution conversion for low bit-rate coding
Magnetoresistance Sensor with Analog Frontend for Lab-on-Chip Malaria Parasite Detection
Occluded human body segmentation and its application to behavior analysis
3D position sensing using a Hopfield neural network stereo matching algorithm
An LMI approach to the design of 2D FIR multirate filter banks
Zero-Aware Regularization for Energy-Efficient Inference on Akida Neuromorphic Processor
A new time-variant neural based approach for nonstationary and non-linear system identification
An LSI implementation of a bit-parallel cellular multiplier over GF(2 4 ) using secure charge-sharing symmetric adiabatic logic
PSCS: A Physiological Sound Compression System Based on Compressive Sensing with Self-Adaptive Compression Ratio and Optimized DCT
Non-linear learning factor control for statistical adaptive background subtraction algorithm
Power-Aware Computing on GPGPU Systems Using ML Classification Techniques
Tradeoffs between residue number system and traditional FIR filters
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology
Granular Spintronics-based Reservoir Computing for Temporal Applications
A 64×64 pixels UWB wireless temporal-difference digital image sensor
PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
MaskCRT-B: Masked Conditional Residual Transformer for Learned B-frame Coding
A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length
A New Approach to Floorplan Area Optimization: To Slice or not to Slice?
A Multiplexed Electrochemical Measurement System for Characterization of Implanted Electrodes
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications
Control methodology for on-chip switching power supplies for biomedical implants
Low-power traceback MAP decoding for double-binary convolutional turbo decoder
Architecture of a Digital Pixel Sensor Array using 1-bit Hilbert Predictive Coding
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison
Integer linear programming method for spatial temporal mapping of the Viterbi decoder
Ultrahigh-G Accelerometer Readout IC with Adaptive Gain Path for Shock Resilience
A Clock-Tuned Digital Memristor Emulator
On the analysis and design of second-order harmonic oscillators
Live demonstration: Single-exposure HDR image acquisition based on tunable balance between local and global adaptation
A radix-4 single-precision floating point divider based on digit set interleaving
Improved ultrasound digital beamforming using single-bit sigma-delta modulators with band-pass decimation filters
A 1.25 V FGMOS filter using translinear circuits
A Multiple Charge Extractions and Multiple Precharge Interface Circuit for Piezoelectric Energy Harvesting
A cascaded MAP-based linear prediction (CMAP-LP) error concealment technique for consecutive block losses
A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters
A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process Variations
Hacking Health: Unveiling Vulnerabilities in BLE-Enabled Wearable Sensor Nodes
1-GHz Operational Amplifier with Multipath Nested Miller Compensation
Novel PUF based on Generalized Galois Ring Oscillators with 10 -15 EER and 0.53% BER
Chaotic symbolic dynamics modulation in MIMO systems
An enhancement study on the SDSL upstream receiver
A practical hafnium-oxide memristor model suitable for circuit design and simulation
A Novel Method for Discrete Coefficient FIR Digital Filter Design
A parallel algorithm for the diagonalization of symmetric matrices
Bandwidth considerations for a CALLUM transmitter architecture
Design of a self-timed asynchronous parallel FIR filter using CSCD
Cooperative Path Planner for UAVs using ACO ALgorithm with Gaussian Distribution Functions
A CMOS implementation of time-interleaved high-pass Delta Sigma modulator
Direction scalability of adaptive directional wavelet transform: An approach using block-lifting based DCT and SPIHT
A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation
Design of a 4.4 to 5 GHz LNA in 0.25µm SiGe BiCMOS technology
RIRI scheme: A robust instant-responding ratiochronous interface with zero-latency penalty
Micropower two-stage amplifier employing recycling current-buffer Miller compensation
A wideband transformer-coupled frequency quadrupler using an asymmetrical balun in 0.25μm SiGe for backhaul communication
A 12-bit Segmented Current-Steering DAC With High-Speed Deserializer
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories
An application-level methodology to guide the design of intelligent-processing, power-aware passive RFIDs
Fast iris detection for personal identification using modular neural networks
Double-via insertion enhanced X-architecture clock routing for reliability
An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients
Design of a digital reaction-diffusion system for restoring blurred fingerprint images
Video error concealment by using Kalman-filtering technique
A CMOS Square-law Programmable Floating Resistor
Per-survivor processing Viterbi decoder for Bluetooth applications
A readout circuit for capacitive biosensors with integrated SAR A/D conversion
Determination of supercapacitor metrics using a magnitude-only method
Predictive valley current controller for two inductor buck converter
Frequency domain analysis of double sampling phase-locked loop
Design techniques for low-voltage fully differential CMOS switched-capacitor amplifiers
Structured Camera Pose Estimation for Mosaic-Based Omnidirectional Imaging
A Hybrid CMOS Photonic 25Gbps Microring Transmitter with a -0.5-1.2V Direct-Coupled Drive
DSP Implememntation of Fast FIR Filtering Algorithms Using Short FFT's
An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners
A novel estimation procedure for the aperture time in asynchronous sinusoidal PWM systems
Low-Power High Sensitive Capacitance Read-Out Circuit Using a-InGaZnO TFTs
Improved local optimization for adaptive bases non-rigid image registration
On the security of a class of image encryption schemes
TCache: An energy-efficient DRAM cache design
On the Comparison Between Architectures for the Implementation of Distributed Arithmetic
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism
A 512×512-cell associative CAM/Willshaw memory with vector arithmetic
Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems
An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference
Best Practices for Designing and Training Neural Networks Subjected to Random Variations
Bounded Rationality Optimizes the Performance of Networked Systems in Prisoner's Dilemma Game
Large Memristor Crossbars for Analog Computing
Co-existence of chaos-based and conventional digital communication systems
Spectral mode decomposition of propagating wave in five-coupled bistable oscillators
A 0.012mm 2 Inverter-Based Ring-Oscillator with Power-Supply Voltage Noise Isolator for Quantum Applications in 22-nm FD-SOI CMOS
Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation
Hardware accelerator design for video segmentation with multi-modal background modelling
Sigma-delta analog to digital converter architecture based upon a modulator design employing a mirrored integrator
On the regularity of orthonormal wavelets designed via the zero-pinning technique
CMOS Ring-Oscillator-Based Electrochemical Capacitance Imager with Frequency-Division-Multiplexed Readout
A technique for high-speed circuits on SOI using look-ahead type active body bias control
A real-time automatic lipreading system
The implementation of PFCMS using cepstrum information
Live Demonstration: A Portable High-Speed Ion-Imaging Platform using a Raspberry Pi
Design and Analysis of an Energy-efficient Duo-Core SRAM-based Compute-in-Memory Accelerator
High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM
An Embedded Environmental Control Micro-chamber System for RRAM Memristor Characterisation
Live Demonstration: Computing Spike-based Convolutions on GPUs
Probabilistic analysis of MPEG-4 error resilience tools in W-CDMA environments
Real-time event-driven spiking neural network object recognition on the SpiNNaker platform
MIMO Noise Suppression Preserving Spatial Cues for Sound Source Localization in Mobile Robot
High-pass Delta Sigma modulator: from system analysis to circuit design
LNA design optimization with reference to ESD protection circuitry
Convergence regions of Newton method in power flow studies: Numerical studies
Low complexity OFDM receiver using Log-FFT for coded OFDM system
Rotating stall analysis using signal-adapted filter bank and Cohen's time-frequency distributions
A Universal Interface Between PC and Neural Networks Hardware
High-frequency DC-DC conversion : fact or fiction
Robust distributed beamforming for two-way wireless relay systems
Time Domain Analog Wavelet Transform in Real-Time
Micromachined Display Ouptut for a Cellular Neural Network
Flexible Energy-Efficient Implementation of Adaptive Spiking Encoder for Neuromorphic Processors
Biorthogonal filter banks constructed from four halfband filters
On VLSI decompositions for deBruijn graphs
A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution
A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS
BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention
Signal analysis of externally linear filters
Weighted pole and zero sensitivity minimization for state-space digital filters
A Behavioral Model for Lithium Batteries based on Genetic Programming
A 1.6 mW 5.4 GHz transformer-feedback gm-boosted current-reuse LNA in 0.18/μm CMOS
Generic analytical solution for calculating the harmonic characteristics of multilevel sinusoidal PWM inverter
Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
VLSI design and implementation of analog CMOS 2nd generation current conveyors
An automatic word length determination method
A Batteryless and Single-Inductor DC-DC Boost Converter for Thermoelectric Energy Harvesting Application with 190mV Cold-Start Voltage
Bayesian Deep Active Learning for Analog Circuit Performance Classification
Circuits and systems engineering education through interdisciplinary team-based design projects
A New Bivariate MAP Estimator for DT-CWT-based Video Denoising
A low-voltage CMOS linear transconductor suitable for analog multiplier application
Data-Driven Modeling of the Koopman-Oriented Chua Circuit Based on Reservoir Computers
Delay bound determination for timing closure satisfaction
Exploring strategy selection in populations via a continuous evolutionary game dynamics
Rate-distortion optimization with adaptive weighted distortion in high Efficiency Video Coding
Concept Drift Detection Methods for Deep Learning Cognitive Radios: A Hardware Perspective
A Versatile Non-Overlapping Signal Generator for Efficient Power-Converters Operation
Face recognition with the robust feature extracted by the generalized Foley-Sammon transform
A time-based CMOS image sensor
Spatial/temporal decimation on 3DPAC for very low bit rate video transmission
A Pulse Train Controlled Single-Input Dual-Output Buck Converter
Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors
Interpolation factor analysis for jointly optimized frequency-response masking filters
A new digital true random number generator based on delay chain feedback loop
On the Distributions of the Relative Phase of Complex Wavelet Coefficients
ASIC hardware implementation of the IDEA NXT encryption algorithm
Analysis of rational sample rate conversion using image response combining
Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic
Terminals and ports
Automatic Symbolic Characterization of SC Multirate Circuits with Finite Grain Operational Amplifiers
An 8b 240 MS/s 1.36 mm 2 104 mW 0.18 um CMOS ADC for DVDs with dual-mode inputs
A sixth-order subsampling continuous-time bandpass delta-sigma modulator
No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications
On pre-whitened sign algorithms
12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip
Real-Time ORB Accelerator with ROS Integration for Embedded FPGA SoCs
An Adaptive Quantization Method for CNN Activations