yusuke1997/dblp-id-title huggingface dataset:
Wireless communication integrated circuits with CMOS-compatible SiGe HBT technology modules
A 0.7pArms Electrochemical Readout IC for Continuous Monitoring of Antibody Biologics in Upstream Biomanufacturing
A time-domain latch interpolation technique for low power flash ADCs
A 62.5 Gb/s multi-standard SerDes IC
FLEXBAR: A crossbar switching fabric with improved performance and utilization
Power Management for the Internet of Things
Dual-loop direct VCO modulation for spread spectrum clock generation
A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation
ESD protection design for RF integrated circuits: new challenges
A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement
Zero-pole modulation and demodulation for noise reduction in charge amplifiers
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT
Improved method for measuring frequency ratios in GSM mobile phones
PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs
Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis
A 43.5mW 77GHz receiver front-end in 65nm CMOS suitable for FM-CW Automotive Radar
A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS
A 0.13μm CMOS fully differential receiver with on-chip baluns for 60GHz broadband wireless communications
An 8-Bit 4-GS/s 120-mW CMOS ADC
A 0.5-V 2.07-fJ/b 497-F 2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in
Measurement and analysis of delay variation due to inductive coupling
An 111pW Voltage Reference with a Diode-Leakage-Decoupling Replica for High-Temperature Miniature IoT Systems
A simplified method for phase noise calculation
A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS
A 2.67GΩ 454nVrms 14.9μW Dry-Electrode Enabled ECG-on-Chip with Arrhythmia Detection
A Wideband Saw-Less Transmitter Operating in Closed-Loop With Embedded N-Path Filtering
A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation
A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel
2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015
A new direction in ASIC high-performance clock methodology
Optimum area allocation for minimum mismatch [IC device area optimization]
A bus architecture centric configurable processor system
A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS
A Li-ion Battery Input 96.8% Peak Efficiency Single- Inductor Off-Chip-Capacitor-Free 2-Switch LED Driver with Two-Color Mixing Capability
Energy Efficient ADC Design Techniques
FEXT Crosstalk Cancellation for High-Speed Serial Link Design
A CMOS high efficiency +22 dBm linear power amplifier
Successful modular process technology for system-on-a-chip applications
A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector
A low-voltage OP amp with digitally controlled algorithmic approximation
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel
A 1.6pJ/b 65Gb/s Si-Dielectric-Waveguide based Multi-Mode Multi-Drop sub-THz Interconnect in 65nm CMOS
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects
A Wide Output Voltage Range Single-Input-Multi-Output Hybrid DC-DC Converter Achieving 87.5% Peak Efficiency With a Fast Response Time and Low Cross Regulation for DVFS Applications
Smart integrated temperature sensor - mixed-signal circuits and systems in 32-nm and beyond
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement
RF ESD protection strategies - the design and performance trade-off challenges
Cellular handset integration - SIP vs. SOC and best design practices for SIP
Estimation of passive mixer output bandwidth using switched-capacitor techniques
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow
A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology
Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices
A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation
N-path filters and mixer-first receivers: A review
3DIC Design Challenges, Early Solutions and Future Recommendations
A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities
Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors
A 150nA IQ, 850mA ILOAD, 90% Efficiency over 10μA to 400mA Loading Range
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller
A 0.18-μm CMOS fully integrated 0.7-6 GHz PLL-based complex dielectric spectroscopy system
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
A 12V-to-PoL CCC-Based Easy-Scalable Multiple-Phase Hybrid Converter with Auto VCF Balancing and Inactive CF Charging
An energy-efficient ring-oscillator digital PLL
A batteryless wireless system with MTCMOS/SOI circuit technology
A 60 GHz Power Amplifier in 90nm CMOS Technology
Modular Flexible 80-dB-DR Artifact-Resilient EEG Headset with Distributed Pulse-Based Feature Extraction and Multiplier-Less Neuromorphic Boosted Seizure Classifier
Proceedings of the IEEE Custom Integrated Circuits Conference, CICC 2003, San Jose, CA, USA, September 21 - 24, 2003
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW
4C 3-Level Hybrid Buck Converter for 12~48V-to-1V Point-of-Load Applications
Mismatch characterization of small metal fringe capacitors
A 133.6-µW 1kHz-BW Multi-Bit 2nd-Order Incremental ADC Achieving 115.4-dB SNDR with Low-Cost Coarse-Sorting DEM and Zip-Extended-Counting
AOT-controlled dual-mode AVP buck regulator with AEAF mechanism
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration
A Fully-Printed Organic Smart Temperature Sensor for Cold Chain Monitoring Applications
Interface socket design methodology to generate embedded DRAM macros
A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR
Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology
A Fully-Dynamic Capacitive Touch Sensor with Tri-Level Energy Recycling and Compressive Sensing Technique Achieving 1513 Hz Framerate and 10.66 pJ/Step Energy Efficiency
A single chip DMT modem for high-speed WLANS
Slew-aware buffer insertion for through-silicon-via-based 3D ICs
Crosstalk Reduction with Nonlinear Transmission Lines for High-Speed VLSI System
Process variability at the 65nm node and beyond
RF CMOS is more than CMOS: Modeling of RF passive components
Considerations for Accurate Behavioral Modeling of High-Speed SC ΣΔ Modulators
Advances in RF packaging technologies for next-generation wireless communications applications [RFIC]
Flexible selfbiased 66.7nJ/c.s. 6bit 26S/s successive-approximation C-2C ADC with offset cancellation using unipolar Metal-Oxide TFTs
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example
Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz
A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion
A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution
Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)
A wideband 77GHz, 17.5dBm power amplifier in silicon
An Idle-Tone Free Dynamic Element Matching Algorithm
PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology
Flexible 16nJ/c.s. 134S/s 6b MIM C-2C ADC using Dual Gate Self-aligned Unipolar Metal-Oxide TFTs
Strain for CMOS performance improvement
V TH -hopping scheme for 82% power saving in low-voltage processors
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications
Signal and data processors
Millimeter-wave 14dBm CMOS power amplifier with input-output distributed transformers
A fully integrated translational tracking filter with >40dB blocker attenuation and >68dB harmonic rejection in 40nm for Digital TV tuner applications
A low-triggering circuitry for dual-direction ESD protection
Silicon-based THz circuits, systems and applications (Forum)
Trends, Possibilities and Limitations of Silicon Photonic Integrated Circuits and Devices
A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC
A self oscillating class D audio amplifier with 0.0012% THD+N and 116.5 dB dynamic range
A 2 GB/s high speed link with differential simultaneous bi-directional IO
Indirect phase noise sensing for self-healing voltage controlled oscillators
A 'digital' 6-bit ADC in 0.25 μm CMOS
Embedded high-speed BCH decoder for new-generation NOR flash memories
A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver
An all-digital PWM-based ΔΣ ADC with an inherently matched multi-bit quantizer
High-speed wireline transceivers and clocking
Physical Model for Power Supply Noise and Chip/Package Co-Design in Gigascale Systems with the Consideration of Hot Spots
A Phase-Modulation Phase-Shifting Phased-Array Transmitter with 10-Bit Fast-Locking Phase Self-Calibration and 0/2.5/6/12dB Power Back-Offs Efficiency Enhancement
Advanced compact model for short-channel MOS transistors
Chipmunk: A systolically scalable 0.9 mm 2 , 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference
A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS
Behavioral model for D/A converters as VSI virtual components
A 350uW 2GHz FBAR transformer coupled Colpitts oscillator with close-in phase noise reduction
A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V
An 81.0% Peak Efficiency, 1.0W/cm 3 Miniaturized 5V/1A AC-DC Converter Using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching
A cost-effective digital front-end realization for 20-bit ΣΔ DAC in 0.13 μm CMOS
Session 23 - Modeling emerging devices
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering
Energy efficiency maxima for wireless communications: 5G, IoT, and massive MIMO
Watt-Level Triple-Mode Quadrature SFCPA with 56 Peaks for Ultra-Deep PBO Efficiency Enhancement Using IQ Intrinsic Interaction and Adaptive Phase Compensation
A low-power integrated power converter for an electromagnetic vibration energy harvester with 150 mV-AC cold startup, frequency tuning, and 50 Hz AC-to-DC conversion
Session 2 - Low power analog
Low-voltage pipelined ADC using opamp-reset switching technique
Ultra-thin silicon-on-sapphire component technology for short reach parallel optical interconnects
Tessellation-enabled shader for a bandwidth-limited 3D graphics engine
Design considerations for low-power receiver front-end in high-speed data links
A 0.8 V asynchronous ADC for energy constrained sensing applications
A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision
An Integrated Burst-Mode 2R Receiver Employing Fast Residual Offset Canceller for XGS-PON in 40-nm CMOS
A Multi-Port Dual Polarized Antenna Coupled mm-Wave CMOS Receiver with Element-level Pattern and Notch Programmability and Passive Interferer Rejection Capability
A 30GHz 4-way Series Doherty Digital Polar Transmitter Achieving 18% Drain Efficiency and -27.6dB EVM while Transmitting 300MHz 64-QAM OFDM Signal
A fast analytical technique for estimating the bounds of on-chip clock wire inductance
An Energy Scalable Computational Array for Sensor Signal Processing
Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes
Practical dynamic element matching techniques for 3-level unit elements
A 11μW Sub-pJ/bit reconfigurable transceiver for mm-sized wireless implants
Low-power low-noise highly ESD robust LNA, and VCO design using above-IC inductors
A 40 Gb/s transversal filter in 0.18 μm CMOS using distributed amplifiers
A 5.8nW, 45ppm/°C on-chip CMOS wake-up timer using a constant charge subtraction scheme
A central office combined ADSL-VDSL line driver solution in .35μm CMOS
NECoBus: a high-end SOC bus with a portable and low-latency wrapper-based interface mechanism
Integrated Inductor Actively Engaging Metal Filling Rules
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE
A 300-kHz 3-Level Flyback Converter Achieving 93% Peak Efficiency and 50% Reduction in Transformer Size
Designing reliable analog circuits in an unreliable world
A 110µW 99.5dB-SNDR 20kHz-BW Intrinsically Linear CTDSM with Hybrid Gm-Boosting OTA and Tri-Level FIR DACs
A 100 MHz two-phase four-segment DC-DC converter with light load efficiency enhancement in 0.18 μm CMOS technology
A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs
An 86.7%-Efficient Three-Level Boost Converter with Active Voltage Balancing for Thermoelectric Energy Harvesting
A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS
Advanced ternary CAM circuits on 0.13 μm logic process technology
A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration
A DTMOST-based Temperature Sensor with 3σ Inaccuracy of ±0.9°C for Self-Refresh Control in 28nm Mobile DRAM
Process integration and manufacturing issues
Energy-efficient Mixed-mode support vector machine processor with analog Gaussian kernel
A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16: 1 multiplexer and 1: 16 demultiplexer for optical communication systems
A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS
Wide-bandwidth fully integrated Cartesian feedback transmitter
A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique
A 17pJ/bit 915MHz 8PSK/O-QPSK transmitter for high data rate biomedical applications
An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter
An energy-harvesting stamp-sized reader for distance-immune interrogation of passive wireless sensors
A 3.25 Gb/s injection locked CMOS clock recovery cell
E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables
A precision CMOS amplifier using floating-gates for offset cancellation
A BiCMOS ultra-wideband 3.1-10.6GHz front-end
Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited)
Ultra-Low Power Receivers for IoT Applications: A Review
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver
Wireline transmitter and receiver design techniques
A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure
Circuit aging prediction for low-power operation
Time Domain NIRS Optode based on Null/Small Source-Detector Distance for Wearable Applications
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface
The importance of including thermal effects in estimating the effectiveness of power reduction techniques
SOI Hall effect sensor operating up to 270°C
A novel equivalent circuit for on chip transmission lines modeling
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers
An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R
PSP-Based Scalable MOS Varactor Model
A data-driven micropipeline structure using DSDCVSL
A 47.3-MHz SAW resonator based CMOS second-order bandpass sigma-delta modulator with 54-dB peak SNDR
R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip
A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS
A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer
Parallel gain enhancement technique for switched-capacitor circuits
Test methods and ICs for high-speed serdes
An 8bit 3GHz Si/SiGe HBT sample-and-hold
A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology
A Fully Integrated, Dual Channel, Flip Chip Packaged 113 GHz Transceiver in 28nm CMOS supporting an 80 Gb/s Wireless Link
An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS
A 12.5mg mm-Scale Inductively-Powered Light-Directivity-Enhanced Highly-Linear Bidirectional Optogenetic Neuro-Stimulator
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power
Modeling substrate noise generation in CMOS digital integrated circuits
An AC-Coupled Stacked Dual Active Bridge Hybrid DC-DC Converter for Battery-to-Processor Power Delivery with 87.2% Peak Efficiency and High Accuracy Loadline Regulation
A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization
A 7.4μJ.ppm2 Resistance Sensor with ±120ppm (3σ) 1-Point-Trimmed Inaccuracy and <4ppm/°C Temperature Drift from -55°C to 125°C
Phase noise and timing jitter in oscillators
A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator
Polysilicon vertical actuator powered with waste heat
Overlapped inductors and its application on a shared RF front-end in a MultiStandard IC
A 0.16mm 2 450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques
A burn-in tolerant dynamic circuit technique
Recent Advances in High-Performance Frequency Synthesizer Design
On the modeling of LDMOS RF power transistors
A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillators
A sub-100µW 2GHz differential colpitts CMOS/FBAR VCO
Corner models: Inaccurate at best, and it only gets worst ..
A 92MHz, 80dB peak SNR SC bandpass ΣΔ modulator based on a high GBW OTA with no Miller capacitors in 0.35μm CMOS technology
A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider
Session 14 - Emerging technology, power and cooling
Reconfigurable Asynchronous Logic
A 0.18μm CMOS 1000 frames/sec, 138dB Dynamic Range Readout Circuit for 3D-IC IR Focal Plane Arrays
Low-cost fully integrated BiCMOS transceiver for pulsed 24-GHz automotive radar sensors
Inductor- and Transformer-based Integrated RF Oscillators: A Comparative Study
Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die Connectivity
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications
Elastic shared resource scheduling SOC interconnect architecture for real-time system
Integrated IC design approach based on software engineering paradigm
Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation
Design of high-speed circuits for optical communication systems
Enabling flexible datacenter interconnect networks with WDM silicon photonics
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset
A CMOS cell generation system for two-dimensional transistor placement
Nanometer design intricacies
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS
Circuit technologies for mm-wave wireless systems on silicon
A 415 MHz direct digital quadrature modulator in 0.25-μm CMOS
An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS
SRAM read current variability and its dependence on transistor statistics
The challenge of lead-free electronics for aerospace electronic systems
A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications
A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications
A field programmable system chip which combines FPGA and ASIC circuitry
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application
Highly efficient CMOS rectifier assisted by symmetric and voltage-boost PV-cell structures for synergistic ambient energy harvesting
Advanced Multiphasing: Pushing the Envelope of Fully Integrated Power Conversion
The challenge of designing global signals in UDSM CMOS
High-Power, Efficient THz Generation in Silicon for Broadband Sensing and Wireless Communication
A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL
A 800 mW, full-rate ADSL-RT analog frontend IC with integrated line driver
An efficient bus architecture for system-on-chip design
Ditherng Skip Modulator with a Width Controller for Ultra-wide-load High-Efficiency DC-DC Converters
Discrete-time, cyclostationary phase-locked loop model for jitter analysis
A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS
Loop finder analysis for analog circuits
A 1V 9-86 fJ/Conv.Step 72.5dB-SNDR Level-Crossing Pipelined ADC with Triggered Sampling and Level Feedback
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration
A 9.2-GHz digital phase-locked loop with peaking-free transfer function
Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates
A self-regulated voltage/current-mode integrated power management with seamless mode transition and extended input-voltage range
A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer
Design of organic complementary circuits for RFID tags application
Methods for finding globally maximum-efficiency impedance matching networks with lossy passives
A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration
A 30V Step-Up Regulator with Shunt-Current-Reuse Controller for >85% Efficiency over 200µA-100mA Loading Range
A 1.7-GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System
Tracking Fmax Degradation of a RISC-V CPU with Synthesizable Odometer Aging Sensors
Computational field programmable architecture
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
Heterogeneous routing architecture for low-power FPGA fabric
Measurement and analysis of contact plug resistance variability
A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation
A 10mV-input boost converter with inductor peak current control and zero detection for thermoelectric energy harvesting
Differentially-shielded monolithic inductors
A 43.8µW per Channel Biopotential Readout System using Frequency Division Multiplexing with Cable Motion Artifact Suppression
A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256