yusuke1997/dblp-id-title huggingface dataset:
Rethinking Node Allocation Strategy for Data-intensive Applications in Consideration of Spatially Bursty I/O
Algorithms for Block Bidiagonal Systems on Vector and Parallel Computers
Compiler aided checkpointing using crash-consistent data structures in NVMM systems
An efficient approach to computing fixpoints for complex program analysis
Author retrospective for a NUCA substrate for flexible CMP cache sharing
Improving performance by matching imbalanced workloads with heterogeneous platforms
An asymmetric clustered processor based on value content
Communication conscious radix sort
Highly Efficient Implementation of MPI Point-to-Point Communication Using Remote Memory Operations
RT-kNNS Unbound: Using RT Cores to Accelerate Unrestricted Neighbor Search
Classification-Driven Search for Effective SM Partitioning in Multitasking GPUs
Examination of a Memory Access Classification Scheme for Pointer-Intensive and Numeric Programs
MEMPLEX: A Memory System with Replication and Migration of Data for Multi-Chiplet NUMA Architectures
A General Algorithm for Tiling the Register Level
Graph Prefetching Using Data Structure Knowledge
Integral Knapsack Problems: Parallel Algorithms and Their Implementations on Distributed Systems
Performance modeling as the key to extreme scale computing
Violated dependence analysis
The Galley Parallel File System
Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model
The DMBC: Architecture and Fundamental Operations
An optimal distributed load balancing algorithm for homogeneous work units
Characterizing and improving the use of demand-fetched caches in GPUs
Using Asynchronous and Bulk Communications to Construct an Optimizing Compiler for Distributed-Memory Machines with Consideration Given to Communications Costs
Optimization and bottleneck analysis of network block I/O in commodity storage systems
Can software reliability outperform hardware reliability on high performance interconnects?: a case study with MPI over infiniband
Evaluating the feasibility of using memory content similarity to improve system resilience
Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications
Parallel Two-Level Simulated Annealing
Use of parallel level 3 BLAS in LU factorization on three vector multiprocessors the ALLIANT FX/80, the CRAY-2, and the IBM 3090 VF
An execution strategy and optimized runtime support for parallelizing irregular reductions on modern GPUs
A Compiler Algorithm for Optimizing Locality in Loop Nests
A Cellular Automation Methodology for Solving the Wave Equation
High-performance CUDA kernel execution on FPGAs
DualFS: a new journaling file system without meta-data duplication
Proceedings of the 21th Annual International Conference on Supercomputing, ICS 2007, Seattle, Washington, USA, June 17-21, 2007
Speedup of band linear recurrences in the presence of resource constraints
HykSort: a new variant of hypercube quicksort on distributed memory architectures
Proceedings of the 15th international conference on Supercomputing, ICS 2001, Sorrento, Napoli, Italy, June 16-21, 2001
Optimal local register allocation for a multiple-issue machine
Boundary integral domain decomposition of hierarchical memory multiprocessors
Detailed cache coherence characterization for OpenMP benchmarks
High performance RDMA-based MPI implementation over InfiniBand
The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures
GRU: Exploring Computation and Data Redundancy via Partial GPU Computing Result Reuse
A general performance model for parallel sweeps on orthogonal grids for particle transport calculations
Depth Contention-free Broadcasting on Torus Networks
Optimizing Sparse Matrix-Vector Multiplication for Large-Scale Data Analytics
Proceedings of the 3rd International Workshop on Runtime and Operating Systems for Supercomputers, ROSS 2013, Eugene, Oregon, USA, June 10, 2013
Accelerating reduction and scan using tensor core units
SnuQS: scaling quantum circuit simulation using storage devices
A study of process arrival patterns for MPI collective operations
Evaluating the effect of replacing CNK with linux on the compute-nodes of blue gene/l
TAPE: a transactional application profiling environment
Blue Gene/Q: design for sustained multi-petaflop computing
AEQUITAS: Coordinated Energy Management Across Parallel Applications
Impact of Selection Functions on Routing Algorithm Performance in Multicomputer Networks
Data locality enhancement by memory reduction
Automatic transformation of FORTRAN loops to reduce cache conflicts
Analysis of non-strict functional implementations of the Dongarra-Sorensen eigensolver
Parallel computer ADENART - its architecture and application
Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache
Performance benefits of large execution atomic units in dynamically scheduled machines
RayJoin: Fast and Precise Spatial Join
VICO: demand-driven verification for improving compiler optimizations
High-performance code generation for stencil computations on GPU architectures
SLIDEX: A Novel Architecture for Sliding Window Processing
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes
Poster: programming clusters of GPUs with OMPSs
On the Utility of Threads for Data Parallel Programming
Author's retrospective for: improving the performance of speculatively parallel applications on the hydra CMP
Automatic Energy Efficient Parallelization of Uniform Dependence Computations
A coordinate-oblivious index for high-dimensional distance similarity searches on the GPU
Space-round tradeoffs for MapReduce computations
High Speed Interconnection Using the Clos Network
Poster: DVFS management in real-processors
New shape analysis techniques for automatic parallelization of C codes
LibWater: heterogeneous distributed computing made easy
O3BNN: an out-of-order architecture for high-performance binarized neural network inference with fine-grained pruning
Arkade: k-Nearest Neighbor Search With Non-Euclidean Distances using GPU Ray Tracing
Search and replication in unstructured peer-to-peer networks
Predictive dynamic thermal management for multimedia applications
Software and hardware parallelism on the iWarp multi-computer
Divide-and-conquer: a bubble replacement for low level caches
LU Factorization with Maximum Performances on FPS Architectures 38/64 BIT
Abstractions to separate concerns in semi-regular grids
Life span strategy - a compiler-based approach to cache coherence
Performance degradation due to multiprogramming and system overheads in real workloads: case study on a shared memory multiprocessor
Proceedings of the 12th international conference on Supercomputing, ICS 1998, Melbourne, Australia, July 13-17, 1998
Power efficiency in a partially reconfigurable multiprocessor system
Automatic Partitioning Techniques for Solving Partial Differential Equations on Irregular Adaptive Meshes
Efficient parallel algorithms for betweenness- and closeness-centrality in dynamic graphs
Optimizing and Load Balancing Metacomputing Applications
Decomposable and responsive power models for multicore processors using performance counters
The architecture of the DIVA processing-in-memory chip
Transparently consistent asynchronous shared memory
Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors
An analysis of computational workloads for the ORNL Jaguar system
Major Research Activities in Parallel Processing in Japan
FLORIA: A Fast and Featherlight Approach for Predicting Cache Performance
Decoupling Synchronization and Data Transfer in Message Passing Systems of Parallel Computers
Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects
VMM emulation of Intel hardware transactional memory
Computational challenges in large-scale air pollution modelling
Unified Compilation Techniques for Shared and Distributed Address Space Machines
Integrating collective I/O and cooperative caching into the "clusterfile" parallel file system
Deep Blue System Overview
Seamless optimization of the GEMM kernel for task-based programming models
Enabling energy-efficient DNN training on hybrid GPU-FPGA accelerators
Toward Automatic Partitioning of Arrays on Distributed Memory Computers
uiCA: accurate throughput prediction of basic blocks on recent intel microarchitectures
TransMetric: architecture independent workload characterization for transactional memory benchmarks
BiRFIA: Selective Binary Rewriting for Function Interception on ARM
On sparse matrix reordering for parallel factorization
Parasight: a high-level debugger/profiler architecture for shared-memory multiprocessor
Author retrospective for synthesizing transformations for locality enhancement of imperfectly-nested loop nests
Multilevel hierarchical matrix multiplication on clusters
The roadrunner project and the importance of energy efficiency on the road to exascale computing
Scalable algorithms for compact spanners on real world graphs
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools
The HyperDynamic architecture (massively parallel message-passing machine) - architecture and performance
Design and Scheduling of Mesh Array of Hardware Unifiers for Large-Scale Unification
Adding a vector unit to a superscalar processor
FuseIM: Fusing Probabilistic Traversals for Influence Maximization on Exascale Systems
SRC: virtual i/o caching: dynamic storage cache management for concurrent workloads
Scalable Parallel Memory Architecture with a Skew Scheme
Analysis of Interprocedural Side Effects in a Parallel Programming Environment
Does it matter?: OMPSanitizer: an impact analyzer of reported data races in OpenMP programs
PeerWave: Exploiting Wavefront Parallelism on GPUs with Peer-SM Synchronization
EMC-Y: Parallel Processing Element Optimizing Communication and Computation
A Computer Graphics Rendering Algorithm for Use on a SIMD Machine
Multiprocessor Scalability Predictions Through Detailed Program Execution Analysis
A Device-Side Execution Model for Multi-GPU Task Graphs
Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor
Practical and efficient point insertion scheduling method for parallel guaranteed quality delaunay refinement
Gaussian Elimination on Message Passing Architecture
Cephalo: Harnessing Heterogeneous GPU Clusters for Training Transformer Models
Calipers: a criticality-aware framework for modeling processor performance
Gated SSA-based Demand-Driven Symbolic Analysis for Parallelizing Compilers
A Cost-Comparison Approach for Adaptive Distributed Shared Memory
Improving Gang Scheduling through job performance analysis and malleability
OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses
Addressing bandwidth contention in SMT multicores through scheduling
A Stall-Aware Warp Scheduling for Dynamically Optimizing Thread-level Parallelism in GPGPUs
CoLa: Towards Communication-efficient Distributed Sparse Matrix-Matrix Multiplication on GPUs
Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
Acceleration of derivative calculations with application to radial basis function: finite-differences on the intel mic architecture
Data dependence analysis on multi-dimensional array references
Parallelizing cryo-EM 3D reconstruction on GPU cluster with a partitioned and streamed model
The Potential of Data Value Speculation to Boost ILP
A methodology for high-level synthesis of communication on multicomputers
Tuning high-performance scientific codes: the use of performance models to control resource usage during data migration and I/O
Hybrid CPU/GPU clustering in shared memory on the billion point scale
Performance of the Vectorial Processor VEC-SM2 Using Serial Multiport Memory
Recycling waste: exploiting wrong-path execution to improve branch prediction
An architectural framework for migration from CISC to higher performance platforms
Mesh and pyramid algorithms for iconic indexing
Exploring hardware overprovisioning in power-constrained, high performance computing
Cosmic microwave background map-making at the petascale and beyond
Compiler supported high-level abstractions for sparse disk-resident datasets
Memory-conscious collective I/O for extreme scale HPC systems
BranchTap: improving performance with very few checkpoints through adaptive speculation control
Accelerating sparse matrix computations via data compression
Design of a next generation sampling service for large scale data analysis applications
Wavefront parallelization of recurrent neural networks on multi-core architectures
AutoParBench: a unified test framework for OpenMP-based parallelizers
Compiler-directed data prefetching in multiprocessors with memory hierarchies
The privatizing DOALL test: a run-time technique for DOALL loop identification and array privatization
Input Range Generation for Compiler-Induced Numerical Inconsistencies
A performance bound analysis of multistage combining networks using a probabilistic model
SRC: Damaris - using dedicated i/o cores for scalable post-petascale HPC simulations
TSM2: optimizing tall-and-skinny matrix-matrix multiplication on GPUs
Latency and energy aware value prediction for high-frequency processors
ReGraph: A Graph Processing Framework that Alternately Shrinks and Repartitions the Graph
Strategies for Cache and Local Memory Management by Global Program Transformation
Cluster-Partitioning Approaches to Mapping Parallel Programs onto a Hypercube
Lazy evaluation and the logic variable
FMI: Fast and Cheap Message Passing for Serverless Functions
Performance analysis of a synchronous, circuit-switched interconnection cached network
Semi-iterative methods on distributed memory multiprocessor architectures
A gossip-based approach to exascale system services
Application Level Scheduling of Gene Sequence Comparison on Metacomputers
Dynamic cache clustering for chip multiprocessors
Using many-core hardware to correlate radio astronomy signals
Write-Aware Management of NVM-based Memory Extensions
Optimal software pipelining of loops with control flows
Loop Fusion in Matrix Multiplications with Sparse Dependence
A deterministic fault-tolerant and deadlock-free routing protocol in 2-D meshes based on odd-even turn model
Power efficient job scheduling by predicting the impact of processor manufacturing variability
Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach
Tuning the continual flow pipeline architecture
Profitable loop fusion and tiling using model-driven empirical search
A low-complexity issue logic
Tools for top-down performance analysis of GPU-accelerated applications
Locality-Driven Dynamic GPU Cache Bypassing
Scalable parallelization for the solution of phonon Boltzmann Transport Equation
A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors
Optimizing latency and throughput for spawning processes on massively multicore processors
Improved automatic testcase synthesis for performance model validation
Handling task dependencies under strided and aliased references
A Parallel Block Cyclic Reduction Algorithm for the Fast Solution of Elliptic Equations
Elastodynamics on clustered vector multiprocessors
Performance optimization of reactive molecular dynamics simulations with dynamic charge distribution models on distributed memory platforms
Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009
Register-sensitive selection, duplication, and sequencing of instructions
Efficient Resolution of Sparse Indirections in Data-Parallel Compilers
Characteristics of adaptive runtime systems in HPC
Compile-Time Minimisation of Load Imbalance in Loop Nests
Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping
Efficient scheduling of recursive control flow on GPUs
A regression-based approach to scalability prediction
Thrifty interconnection network for HPC systems
A performance perspective on energy efficient HPC links
Parallel Triangular Decompositions of an Oil Refining Simulation
Scalability of the Nutch search engine
Adaptive runtime tuning of parallel sparse matrix-vector multiplication on distributed memory systems
Reducing Communication by Honoring Multiple Alignments
ProfDP: A Lightweight Profiler to Guide Data Placement in Heterogeneous Memory Systems
WisIO: Automated I/O Bottleneck Detection with Multi-Perspective Views for HPC Workflows
Problem space promotion and its evaluation as a technique for efficient parallel computation
Quantifying the effectiveness of load balance algorithms
Performance of a shared memory system for vector multiprocessors
How I learned to stop worrying about user-visible endpoints and love MPI
GreenPar: Scheduling Parallel High Performance Applications in Green Datacenters
Automatic loop transformations and parallelization for Java
Code scheduling and register allocation in large basic blocks
Mapping and scheduling HPC applications for optimizing I/O
MPIPP: an automatic profile-guided parallel process placement toolset for SMP clusters and multiclusters
Petaflop/s, seriously
Lynx: Using OS and Hardware Support for Fast Fine-Grained Inter-Core Communication
Accurate memory signatures and synthetic address traces for HPC applications
A hybrid hardware/software approach to efficiently determine cache coherence Bottlenecks
Optimizing the linear fascicle evaluation algorithm for many-core systems
SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference
An experimental approach to performance measurement of heterogeneous parallel applications using CUDA
Efficient computation of sum-products on GPUs through software-managed cache
OpaQue: Program Output Obfuscation for Quantum Software Circuits in Quantum Clouds
Function, latency, bandwidth, power: towards a better computer
SRC: an automatic code overlaying technique for multicores with explicitly-managed memory hierarchies
FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache
Optimizing Data Aggregation by Leveraging the Deep Memory Hierarchy on Large-scale Systems
Satisfiability Test with Synchronous Simulated Annealing on the Fujitsu AP1000 Massively-Parallel Multiprocessor
Superlinear Speedup for Parallel Backtracking
Author retrospective for software trace cache
System architecture of parallel processing system -Harry-
Using accurate arithmetics to improve numerical reproducibility and stability in parallel applications
Parallelizing pruned landmark labeling: dealing with dependencies in graph algorithms
Modeling correlated workloads by combining model based clustering and a localized sampling algorithm
Mint: realizing CUDA performance in 3D stencil methods with annotated C
Statistical Treatment of Variable MPI Latencies and MPI-Communication Hiding for Matrix-Free Finite Element Operators
Proceedings of the 2nd International Workshop on Runtime and Operating Systems for Supercomputers, ROSS '12, Venice, Italy, June 29, 2012
Dynamic Load Balancing of Data Parallel Applications on a Distributed Network
An adaptive software library for fast Fourier transforms
A practical tile size selection model for affine loop nests
Local Area Metacomputing for Multidisciplinary Problems: A Case Study for Fluid/Structure Coupled Simulation
Fast cluster failover using virtual memory-mapped communication
Quantum mechanical approaches to information processing
Hardware Implementation Issues of Data Prefetching
FULL-W2V: fully exploiting data reuse for W2V on GPU-accelerated systems
Parallel calculations on the wind-driven oceanic circulation using Fourier pseudospectral methods
Optimizing horizontal microprograms for vectorial loops with timed petri nets
Large files, small writes, and pNFS
A QHD-capable parallel H.264 decoder
Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, Australia, June 28 - July 01, 2006
An optimized tensor completion library for multiple GPUs
Architecture-independent Locality-improving Transformations of Computational Graphs Embedded in k -Dimensions
Limited early value communication to improve performance of transactional memory
Analyzing memory access intensity in parallel programs on multicore
Single-particle 3d reconstruction from cryo-electron microscopy images on GPU
Incorporating Application Dependent Information in an Automatic Code Generating Environment
The Tera computer system
Many-core GPU computing with NVIDIA CUDA
BurstZ: a bandwidth-efficient scientific computing accelerator platform for large-scale data
PARSEC: hardware profiling of emerging workloads for CMP design
Evaluating the Limits of Message Passing via the Shared Attraction Memory on CC-COMA Machines: Experiences with TCGMSG and PVM
On Optimizing Distributed Tucker Decomposition for Sparse Tensors
MegTaiChi: dynamic tensor-based memory management optimization for DNN training
Processor allocation and loop scheduling on multiprocessor computers
Performance evaluation of the IBM SP and the Compaq AlphaServer SC
Design and implementation of bandwidth-aware memory placement and migration policies for heterogeneous memory systems
Dual path instruction processing
Scalable On-the-fly Detection of the First Races in Parallel Programs
Fuzzy fairness controller for NVMe SSDs
The Design and Implementation of Zero Copy MPI Using Commodity Hardware with a High Performance Network
Performance evaluation of a formally supercomputer-based Monte Carlo program on a T800 transputer network
Performance evaluation of a new routing strategy for irregular networks with source routing
Diagnosis and optimization of application prefetching performance
Continuous Replica Placement schemes in distributed systems
CRAMG: A Communication-Reduced Algebraic Multigrid Method
Efficiently emulating high-bitwidth computation with low-bitwidth hardware
Inferential queueing and speculative push for reducing critical communication latencies
A generalized vision of some parallel bidiagonal systems solvers
Applying Segment Routing to k-ary n-cube Networks
Extending the I test to direction vectors
A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests
Design and Evaluation of Dynamic Access Ordering Hardware
Light-FP: Analyze Floating-Point Error in a Highly Condensed Approach
Network-on-chip for a partially reconfigurable FPGA system
Supercomputers: where are the lost cycles?
Scaling the issue window with look-ahead latency prediction
A systematic approach to improving data locality across Fourier transforms and linear algebra operations
Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008
Poster: revisiting virtual channel memory for performance and fairness on multi-core architecture
Loop partitioning for distributed memory multiprocessors as unimodular transformations
Advanced collective communication in aspen
SMIO: I/O similarity aware virtual machine management invirtual desktop environments
A User Level Program Transformation Tool
A framework for efficient reuse of binary code in Java
Data-Localization for Fortran Macro-Dataflow Computation Using Partial Static Task Assignment
SnuCL: an OpenCL framework for heterogeneous CPU/GPU clusters
A framework for determining useful parallelism
Implementing partition on vector computers
Exploiting parallelism in automatic differentiation
Using Memory in the Cedar System
SRC: automatic extraction of SST/macro skeleton models
MG-αGCD: Accelerating Graph Community Detection on Multi-GPU Platforms
Proceedings of the 11th international conference on Supercomputing, ICS 1997, Vienna, Austria, July 7-11, 1997
FT-BLAS: a high performance BLAS implementation with online fault tolerance
Towards low-latency I/O services for mixed workloads using ultra-low latency SSDs
Very high-speed communication in large MIMD supercomputers