yusuke1997/dblp-id-title huggingface dataset:
Classification of Component Vulnerabilities in Java Service Oriented Programming (SOP) Platforms
Modular coordination of multiple autonomic managers
Component-Based Software Engineering, 9th International Symposium, CBSE 2006, Västerås, Sweden, June 29 - July 1, 2006, Proceedings
Real-Time Scheduling Techniques for Implementation Synthesis from Component-Based Software Models
Model-Driven Safety Evaluation with State-Event-Based Component Failure Annotations
DEECO: an ensemble-based component system
Defining and Checking Deployment Contracts for Software Components
TESTEJB - A Measurement Framework for EJBs
Component-Based Software Engineering, 11th International Symposium, CBSE 2008, Karlsruhe, Germany, October 14-17, 2008. Proceedings
A Component Model to Manage the Heterogeneity and Dynamism in Mobile Applications
An Empirical Study of the Component Dependency Resolution Search Space
Timing analysis of component-based embedded systems
Dynamic Reconfiguration and Access to Services in Hierarchical Component Models
Correct Components Assembly for a Product Data Management Cooperative System
A Component Model Engineered with Components and Aspects
A component-based open-source framework for general-purpose recommender systems
Synthesis of Connectors from Scenario-Based Interaction Specifications
Towards mode switch handling in component-based multi-mode systems
An MDE approach to address synchronization needs in component-based real-time systems
A Modeling Approach to Analyze the Impact of Error Propagation on Reliability of Component-Based Systems
Extending the Rubus Component Model with GPU-Aware Components
Capturing Web Services Provider Constraints - An Algorithmic Approach
Rapid prototyping of domain-specific architecture languages
Parameterised architectural patterns for providing cloud service fault tolerance with accurate costings
A specification schema for software connectors
On Component Identification Approaches - Classification, State of the Art, and Comparison
Automating information flow control in component-based distributed systems
Integration of Extra-Functional Properties in Component Models
Quantifying the parallelism in BPMN processes using model checking
Towards a Systematic Method for Identifying Business Components
Architecture Based Deployment of Large-Scale Component Based Systems: The Tool and Principles
Components mobility for energy efficiency of digital home
On-Demand Quality-Oriented Assistance in Component-Based Software Evolution
Model-Based Transaction Service Configuration for Component-Based Development
Defining "Predictable Assembly"
A component-based meta-level architecture and prototypical implementation of a reflective component-based programming and modeling language
Finding a Needle in the Haystack: A Technique for Ranking Matches Between Components
A Contracting System for Hierarchical Components
Unlocking the Grid
An automated round-trip support towards deployment assessment in component-based embedded systems
Object-Oriented Component-Based Design using Behavioral Contracts: Application to Railway Systems
A Model Transformation Approach for the Early Performance and Reliability Analysis of Component-Based Systems
Component-based specification of software architecture constraints
Proceedings of the 18th International ACM SIGSOFT Symposium on Component-Based Software Engineering, CBSE 2015, Montreal, QC, Canada, May 4-8, 2015
A Practical Approach for Finding Stale References in a Dynamic Service Platform
OccuRE: An Occupancy REasoning Platform for Occupancy-Driven Applications
Automatic Protocol Conformance Checking of Recursive and Parallel Component-Based Systems
Evolution management of extra-functional properties in component-based embedded systems
Control Encapsulation: A Calculus for Exogenous Composition of Software Components
Component Composition Using Feature Models
Impact of Virtual Memory Managers on Performance of J2EE Applications
A Generative Middleware for Heterogeneous and Distributed Services
Runtime modularity in complex structures: a component model for fine grained runtime adaptation
A Process for Resolving Performance Trade-Offs in Component-Based Architectures
Domain-Specific Software Component Models
GLoo: A Framework for Modeling and Reasoning About Component-Oriented Language Abstractions
Automated Creation and Assessment of Component Adapters with Test Cases
Towards Encapsulating Data in Component-Based Software Systems
Integrating Functional and Architectural Views of Reactive Systems
Experiences from Developing a Component Technology Agnostic Adaptation Framework
Component Based Game Development - A Solution to Escalating Costs and Expanding Deadlines?
Learning from the future of component repositories
Towards verified synthesis of ProCom, a component model for real-time embedded systems
Strategies for a Component-Based Self-adaptability Model in Peer-to-Peer Architectures
A Framework for Reliability Assessment of Software Components
Ada-CCM: Component-Based Technology for Distributed Real-Time Systems
A new approach to detect potential race conditions in component-based systems
Testing Framework Components
Proceedings of the 15th ACM SIGSOFT Symposium on Component Based Software Engineering, CBSE 2012, part of Comparch '12 Federated Events on Component-Based Software Engineering and Software Architecture, Bertinoro, Italy, June 25-28, 2012
Qinna, a Component-Based QoS Architecture
Iterative and incremental development of component-based software architectures
Performance Prediction for Component Compositions
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit
Railway Signaling Safety-critical Software Testing Based on Dynamic Decision Table
Testing Delay Faults in Embedded CAMs
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing
Design and Implementation of EMIB Testing on 2.5D FPGA Transceiver
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences
A DFT Approach for Path Delay Faults in Interconnected Circuits
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection
Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters
Power Aware Embedded Test
IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency
4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India
An External Test Approach for Network-on-a-Chip Switches
DCScan: A Power-Aware Scan Testing Architecture
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip
Testing Clock Distribution Networks
Reducing test application time for full scan circuits by the addition of transfer sequences
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill
Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise
A Scan Matrix Design for Low Power Scan-Based Test
A Transition Isolation Scan Cell Design for Low Shift and Capture Power
A case study of failure analysis and guardband determination for a 64M-bit DRAM
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction
A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA
Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing
A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories
Intermittent and Transient Fault Diagnosis on Sparse Code Signatures
Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories
Fault tolerant multistage interconnection networks with widely dispersed paths
Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China
HYPERA: High-Yield Performance-Efficient Redundancy Analysis
High Level Fault Injection for Attack Simulation in Smart Cards
Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip
Formal verification of data-path circuits based on symbolic simulation
Learning from Production Test Data: Correlation Exploration and Feature Engineering
Test Time Minimization in Reconfigurable Scan Networks
Using genetic algorithms for test case generation in path testing
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description
A Reduced Code Linearity Test Method for Pipelined A/D Converters
Verification Methodology for Self-Repairable Memory Systems
A Few Design Techniques for the "Dependability" of a SOC
Software Fault Localization Based on Combining Information Retrieval and Mutation Analysis
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock
Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures
A Scan Chain Adjustment Technology for Test Power Reduction
FPGA-Based Fault Injection for Microprocessor Systems
A Digital BIST Methodology for Spread Spectrum Clock Generators
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing
Generation of tenacious tests for small gate delay faults in combinational circuits
Test and Diagnosis of Analog Circuits Using Moment Generating Functions
A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions
Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE
A Novel Seed Selection Algorithm for Test Time Reduction in BIST
Current Testable Design of Resistor String DACs
13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan
On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits
Optimal System-on-Chip Test Scheduling
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan
A Consistent Scan Design System for Large-Scale ASICs
A Dictionary-Based Test Data Compression Method Using Tri-State Coding
Memory Efficient ATPG for Path Delay Faults
High Precision Result Evaluation of VLSI
On-Line Instruction-Checking in Pipelined Microprocessors
Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations
An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction
Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected Graphs
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation
Interconnect Open Defect Diagnosis with Physical Information
A Hybrid Flow for Memory Failure Bitmap Classification
Designing Multiple Scan Chains for Systems-on-Chip
Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces
Mining Complex Boolean Expressions for Sequential Equivalence Checking
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects
Yield Increase of VLSI after Redundancy-Repairing
Programmable Scan-Based Logic Built-In Self Test
Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity
Selection of Paths for Delay Testing
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST
Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique
Diagnosis Of Byzantine Open-Segment Faults
An Automatic Circuit Extractor for RTL Verification
Testing approach within FPGA-based fault tolerant systems
Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter
A New March Test for Process-Variation Induced Delay Faults in SRAMs
Pre-silicon Noise to Timing Test Methodology
Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning
Accelerated Test Points Selection Method for Scan-Based BIST
Design and Implementation of Self-Testable Full Range Window Comparator
A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range
Delay Defect Characterization Using Low Voltage Test
A New Scheme For The Fault Diagnosis Of Multiprocessor Systems
Exploitation of parallelism in group probing for testing massively parallel processing systems
Efficient Trojan Detection via Calibration of Process Variations
Efficient Test Compaction for Pseudo-Random Testing
Test data compression based on clustered random access scan
A High Reliability FPGA Chip Identification Generator Based on PDLs
Design-for-testability in reversible logic circuits based on bit-swapping
A Design for testability Method Using RTL Partitioning
Characteristics Variability Evaluation of Actual LSI Transistors with Nanoprobing
On Enhancing the Security of Streaming Scan Network Architecture
Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications
A BIC Sensor Capable of Adjusting IDDQ Limit in Tests
On Detecting Transition Faults in the Presence of Clock Delay Faults
Methods and Apparatus to Support Multiple Synchronous Clocks with a Single Clock Mesh
Bridging the Gap between Microelectronics and Micromechanics Testing
Boolean process-an analytical approach to circuit representation (II)
Adaptive Board-Level Functional Fault Diagnosis Using Decision Trees
Optimum Test Set for Bridging Fault Detection in Reversible Circuits
An approach to diagnose logical faults in partially observable sequential circuits
Test Compression / Decompression Based on JPEG VLC Algorithm
Deep Learning Based Test Compression Analyzer
Low Cost Dynamic Test Methodology for High Precision ΣD ADCs
Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test
Scan Test Data Volume Reduction for SoC Designs in EDT Environment
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay
Fault Diagnosis of Analog Circuits Based on Multi-Scale 1D Convolutional Neural Network
Exploring the Mysteries of System-Level Test
Optimized Test Error Detection by Probabilistic Retest Recommendation Models
Verification of Asynchronous Circuits with Bounded Inertial Gate Delays
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
A Monobit Built-In Test and Diagnostic System for Flexible Electronic Interconnect
Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers
Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits
Fault-dependent/independent Test Generation Methods for State Observable FSMs
Deterministic test generation for non-classical faults on the gate level
Perspectives on Test Data Mining from Industrial Experience
Fault-Tolerant Strategies and Their Design Methods for Application Software
An Efficient Peak Power Reduction Technique for Scan Testing
Modified Scan Flip-Flop for Low Power Testing
Session Summary III: Power-Aware Testing: Present and Future
On Acceleration of Logic Circuits Optimization Using Implication Relations
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification
System Level LBIST Implementation
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor
A Practical DFT Approach for Complex Low Power Designs
Diagnosis of Transistor Shorts in Logic Test Environment
Properties of Maximally Dominating Faults
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST
Compressing Functional Tests for Microprocessors
On-chip EOL Prognostics Using Data-Fusion of Embedded Instruments for Dependable MP-SoCs
Hardware-Accelerated Workload Characterization for Power Modeling and Fault Injection
Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands
Self-Dual Duplication for Error Detection
Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study
A Unified Formal Model for Proving Security and Reliability Properties
An effective BIST design for PLA
A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality
The Application of BIST-Aided Scan Test for Real Chips
An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
Test Length for Random Testing of Sequential Machines Application to RAMs
Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling System
Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction
Design for Testability: The Path to Deep Submicron
An Accurate Analysis of Microprocessor Design Verification
Burn-In Stress Test of Analog CMOS ICs
Portable/Desktop Testing Solution for Engineering with Cloud
RTL design of 16-bit RISC Processor Using Vedic Mathematics
A Simple Wrapped Core Linking Module for SoC Test Access
A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure
Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron Irradiation
Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks
Diagnosis of delay faults due to resistive bridges, delay variations and defects
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors
CooLBIST: An Effective Approach of Test Power Reduction for LBIST
Yield Ramp up by Scan Chain Diagnosis
CIPA: Concurrent IC and PCB Authentication Using On-chip Ring Oscillator Array
Optimal Schemes for ADC BIST Based on Histogram
Adaptive Mitigation of Parameter Variations
A variable reordering method for fast optimization of binary decision diagrams
Dynamic Fine-Grain Power Gating Design in WiNoC
Totally Self Checking reconfigurable duplication system with separate internal fault indication
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions
Optimized Pre-bond Test Methodology for Silicon Interposer Testing
Fault Dictionary Based Scan Chain Failure Diagnosis
Can Monitoring System State + Counting Custom Instruction Sequences Aid Malware Detection?
Managing Test and Repair of Embedded Memory Subsystem in SoC
A design-for-test technique for multistage analog circuits
A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead
Simulating Open-Via Defects
Time-Multiplexed Online Checking: A Feasibility Study
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling
Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures
SFCM-HT: Hardware Trojan Detection Based on Sequence Features with a Combination Model
Sequential logic path delay test generation by symbolic analysis
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement
A waveform simulator based on Boolean process
DFT Challenges in Next Generation Multi-media IP
Adding Testability to an Asynchronous Interconnect for GALS SoC
A Post-Silicon Debug Support Using High-Level Design Description
A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding
An Approach to Improve the Resolution of Defect-Based Diagnosis
Compactor Independent Direct Diagnosis
Post-Silicon Timing Validation Method Using Path Delay Measurements
Answers to the Key Issues
Test Pattern Selection for Defect-Aware Test
Design Error Diagnosis Based on Verification Techniques
Accelerating Strategy for Functional Test of NoC Communication Fabric
Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition
An Access Timing Measurement Unit of Embedded Memory
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors
ATE Features for IDDQ Testing
A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC
Preferential Fault-Tolerant based TF32 Floating Point Adder for Mission Critical Systems
PATROL: An Evolutionary APproach to Automatic Test Pattern Generation for Hardware TROjan Detection Leveraging PSO-GA Hybrid Techniques
Invited Talk 2: EDA to the Rescue of the Silicon Roadmap
An Application of IDD Spectrum Testing Method to the Fault Analysis
Scan Chain Adaptation through ECO
Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter
Compaction-based test generation using state and fault information
33rd IEEE Asian Test Symposium, ATS 2024, Ahmedabad, India, December 17-20, 2024
Testability forecasting for sequential circuits
Testability Exploration of 3-D RAMs and CAMs
A New Active IC Metering Technique Based on Locking Scan Cells
Fast computation of C-MISR signatures
Testable Realizations for ESOP Expressions of Logic Functions
Identification of robust untestable path delay faults
Recruiting Fault Tolerance Techniques for Microprocessor Security
SAR TDC Architecture with Self-Calibration Employing Trigger Circuit
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability
A built-in self-test and self-diagnosis scheme for embedded SRAM
Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing
Effects of Advances in Analog, Mixed Signal and IO Circuits on Test Strategies
On Scan Chain Diagnosis for Intermittent Faults
At-Speed Current Testing
Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection
Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault
Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications
A New Access Protocol for Elevating the Security of IJTAG Network
Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications
Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing
A Systematic Way of Functional Testing for VLSI Chips
The Potential and Limitation of Probability-Based Combinational Equivalence Checking
Current Testing for Nanotechnologies: A Demystifying Application Perspective.
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?
IEEE 31st Asian Test Symposium, ATS 2022, Taichung City, Taiwan, November 21-24, 2022
TSV Stress-Aware ATPG for 3D Stacked ICs
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package
Session Summary V: Is Component Interconnection Test Enough for Board or System Test
Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
Accumulation-based concurrent fault detection for linear digital state variable systems
Testing Embedded Systems by Using a C++ Script Interpreter
Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models