yusuke1997/dblp-id-title huggingface dataset:
Double-sampling analog-look-ahead second order ΣΔ modulator with reduced dynamics
A Simple Bandgap Reference Based on VGO Extraction with Single-Temperature Trimming
Bifurcation and Chaos in CMOS Inverters Ring Oscillator
Live Demonstration: Electrotactile feedback from an electronic skin through flexible electrode matrix
Order evaluation for realization of MIMO multidimensional systems
Digital signal processing engine design for polar transmitter in wireless communication systems
Customizable DSP architecture for ASIP core design
A Tunable CMOS Thyristor-Based Pulse Generator for Integrated Sensor Interface Applications
A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications
A Comparison of Analog DFE Architectures for Disk-Drive Applications
A Simplified Model for a NbO2 Mott Memristor Physical Realization
LogSimViT: Logarithmic Similar Pattern Skipping for Hardware Acceleration of ViT
A flexible biphasic pulse generating and accurate charge balancing stimulator with a 1μW neural recording amplifier
Photo album compression By leveraging temporal-spatial correlations and HEVC
Application of two-layered tabu search to optimal allocation of UPFC for maximizing transmission capability
Automated design and layout generation for switched current circuits
Possible definition of quantum bits in coupled quantum dots
The Chip Design of A 32-b Logarithmic Number System
A 67.51 dB SNDR 137.8 µW SAR-Assisted Slope ADC with High-Linearity Analog Slope and Low Switching Energy
tinyRadar: LSTM-based Real-time Multi-target Human Activity Recognition for Edge Computing
Fast global motion estimation for sprite generation
Self-powered active pixel sensors for ultra low-power applications
A High Dynamic Range CMOS Image Sensor using Programmable Linear-Logarithmic Counter for Low Light Imaging Applications
On adaptive wavelet packets
Function-Reused Oscillator-PA for IoT Applications
Motion estimation with Second Order Prediction
Limitations and precision requirements for read-out of passive, linear, selectorless RRAM arrays
DDFS with New Sinusoid Approximation based on Harmonics Removal
A 300mV Low-voltage start-up circuit for energy harvesting systems
A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder
A 1.5 V 5.2 nW 60 dB-DR Lowpass Filter With Self-Compansated Gain in 0.35 μm CMOS Suitable for Biomedical Applications
An integrated multi-scroll circuit with floating-gate MOSFETs
A Neuron-Based ISFET Array Architecture with Spatial Sensor Compensation
A fully programmable log-domain bandpass filter using multiple-input translinear elements
IIR Filter-Based Spiking Neural Network
Memristor Crossbar Design Framework for Quantum Computing
Design of a low power impulse-radio ultra-wide band wireless electrogoniometer
An area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems
A broadcast-based test scheme for reducing test size and application time
Low-Power Current-Mode Algorithmic ADC
Design Considerations for a Closed-loop Digital Class-D Audio Amplifier
Can SMASH Smash MASH?
Climbing obstacles via bio-inspired CNN-CPG and adaptive attitude control
Minimal circuit and state space realization of generalized 3-D lattice-ladder discrete filters
A four-antenna baseband multipath emulator for millimeter-wave channels
A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load
On-chip bidirectional transceiver
Current-Mirror Based Ambient Light Rejection Technique for VLC Receiver
Efficient residue arithmetic based parallel fixed coefficient FIR filters
Rigorous and Realistic Control of Piecewise Linear Chaos
Concealable Physically Unclonable Functions and Key Generation Using a Geiger Mode Imager
Stability analysis of SSN biochemical networks
Predictive coding on-sensor compression
A post layout watermarking method for IP protection
A 1.4 V 10-bit 20 MSPS pipelined A/D converter
Error neutralisation in switched current memory cells
A Dynamic Charge-Transfer-Based Crossbar with Low Sensitivity to Parasitic Wire-Resistance
Estimating Performance Characteristics of Loop Transformations
An improvement to fine granularity scalability based on H.26L
A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS
Novel MOSFET-only bandgap voltage reference
Non-fragile H∞ filter design for polytopic 2-D systems in Fornasini- Marchesini model
Fast parasitic-aware synthesis methodology for high-performance analog circuits
Rate-compatible and high-throughput architecture designs for encoding LDPC codes
A Ka-band Phase Shifting Low Noise Amplifier with Gain Error Compensation for 5G RF beam forming array using 14nm FinFET CMOS
An analysis of noise in timing-based communications over local area networks
Automatic synthesis of analog and mixed-signal fuzzy controllers with emphasis in power consumption
System on Chip for Closed Loop Neuromodulation Based on Dual Mode Biosignals
CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry Applications
Hardware Model Based Simulation of Spiking Neuron Using Phase Plane
Understanding weak loop filter nonlinearities in continuous time ΔΣ converters
Neural Networks for Optimization Problems in Graph Theory
On the invariance of the second-order modes of continuous-time systems under general frequency transformation [analog filters]
Dynamics of Hodgkin Huxley Neuron across chips implemented on a reconfigurable platform
HengNet: An Ultra-lightweight Model with Two-level Reuse Algorithm for Seizure Detection and Prediction
Layer assignment algorithm for RLC crosstalk minimization
Linear current mode imager with low fix pattern noise
On the improvement of blind MOE detector via a posteriori adaptation and adaptive step-size
Time Interval Digitization with an Integrated 32-Phase Oscillator
Set-membership affine projection algorithm with variable data-reuse factor
Analog CMOS charge model for molecular redox electron-transfer reactions and bio-chemical pathways
New architecture for miniaturized fluorescence analysis
A mini-invasive multi-function bladder urine pressure measurement system
A Systolic Array Architecture for SVM Classifier for Machine Learning on Embedded Devices
Optimized decoding scheme for erroneous MPEG-4 FGS bitstream
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators
A mixed PLL/DLL architecture for low jitter clock generation
A Novel Cyclic D/A Converter
Programmable FIR filter with adder-based computing engine
Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture
Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems
Data transmission with adjustable security exploiting chaos-based pseudorandom number generators
A 16-Bit Current Sample/Hold Circuit Using a Digital CMOS Process
A novel efficient and accurate analytical method for determining the swing of internal nodes in digital filters
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits
Second-level NIST Randomness Tests for Improving Test Reliability
Indirect inverse adaptive control based on neural networks using dynamic back propagation for nonlinear dynamic systems
A neuromorphic sound localizer for a smart MEMS system
Implementation of Synapses with Hodgkin Huxley Neurons on the FPAA
A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing
An optimal feature set for seizure detection systems for newborn EEG signals
Chaos based modulations from an information theory perspective
Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials
A Gm-Compensated 46-101 GHz Broadband Power Amplifier for High-Resolution FMCW Radars
Toward Designing Thermally-Aware Memristance Decoder
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM
Improved halftone image data hiding with intensity selection
Multi-layer perceptron with pulse glial chain having oscillatory excitation threshold
Power Analysis of a Chaos-based Random Number Generator for Cryptographic Security
An automatic face recognition system based on wavelet transforms
Double change detection method for moving-object segmentation based on clustering
Integrated routing resource assignment for RLC crosstalk minimization
A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication
4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration
A compliance current circuit with nanosecond response time for ReRAM characterization
A 0.53mW ultra-low-power 3D face frontalization processor for face recognition with human-level accuracy in wearable devices
A generic multilevel multiplying D/A converter for pipelined ADCs
A Time-Division-Multiplexing Scheme for Simultaneous Wavelength Locking of Multiple Silicon Micro-Rings
System level model for transcutaneous optical telemetric link
DC tolerance analysis of electronic circuits by linear programming techniques
Design of 2-D Allpass Digital Filters for Delay Equalisation
A fixed-point harmonic balance approach for circuit simulation under modulated carrier excitation
Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time
Input stimulus comparison using an adaptive FPGA-based testing system
The continuing evolution of digital cameras and digital photography systems
Feature selective template mode filtering
Correction of the Timing Mismatch Error in Four-Channel Time-Interleaved DACs
Joint optimization of error feedback and coordinate transformation for roundoff noise minimization in 2D state-space digital filters
A Non-uniform Resolution Step GHz 7-bit Flash A/D Converter for Wideband OFDM Signal Conversion
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing
A BiCMOS 10Gb/s adaptive cable equalizer
A Converter with Fixed Switching Frequency Adaptive Multi-Mode Control Scheme
EEPNet: Efficient Edge Pixel-based Matching Network for Cross-Modal Dynamic Registration between LiDAR and Camera
A low-area interconnect architecture for chip multiprocessors
Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants
A variable-rate harmonic speech coder with efficient spectral quantization
Genetic Motifs as a Blueprint for Mismatch-Tolerant Neuromorphic Computing
A 3D Tiled Low Power Accelerator for Convolutional Neural Network
Block precoder-based energy constrained DFE
Scalable giga-pixels/s binary image morphological operations
Live Demonstration: Low-Power Static Neural Network Circuits for Long-Term Change Detection
A 10 Bit Semi-Algorithmic Current Mode DAC
Signal extrapolation based on wavelet transform
A 2.7μJ/classification Machine-Learning based Approximate Computing Seizure Detection SoC
A single-event upset hardening technique for high speed MOS Current Mode Logic
Observation of a Pinched-Loop in a Current-Excited Inductive Circuit
CMOS Millimeter-Wave Signal Sources and Detectors
An N-Path Band-Pass Filter with Parametric Gain-Boosting
Analysis and numerical integration of nonlinear systems using MD passive circuits
10Gbit/s 2mW inductorless transimpedance amplifier
Restoration of color images subjected to interchannel blurring
Improving simulation efficiency for circuit-level power estimation [CMOS]
A 40V High-Speed Low-FoM Capacitive Level Shifter with Feedback Discharge Control for Floating Supply Gate Drivers on BCD Technology
A generic model for constructing three-stage amplifiers
Nonspeculative decimal signed digit adder
Adaptive Control-Based Voltage Regulation of a Magnetically Coupled Multiport DC-DC Converter for Electrified Vehicles Applications
Application of neural networks with CSD coefficients for human face recognition
GASA: Rank-Sliced GAther-Scatter Activations and Application to Sparsity-Preserving Parameter-Efficient Fine-Tuning
Theory of T-junction floorplans in terms of single-sequence
AxRA: Approximate Rowhammer Attack for Modern DRAM Systems
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique
A general analysis on the timing jitter in D/A converters
Sampled analog architecture for DCT and DST
Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator
Blind Estimation Using Higher-Order Cumulants
A high precision CMOS current mirror/divider
High performance multirate SC circuits with predictive correlated double sampling technique
Prediction of the laser sheet bending using neural network
Some characterizations of interval systems: further extensions and applications
SRAM Physically Unclonable Functions Implemented on Silicon Germanium
Multiple-target localization and estimation of MIMO radars with unknown transmitted signals
Halide and GENESIS for Generating Domain-Specific Architecture of Guided Image Filtering
A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range
Cluster-based distributed active current timer for hardware Trojan detection
A Novel OTA with Dual Bulk-driven Input Stage
A low latency and low power dynamic Carry Save Adder
Bayer pattern based digital zooming approach
Analysis and optimization of sequential circuit element to combat single-event timing upsets
New bit-parallel systolic multipliers for a class of GF(2m)
Dual-mode sigma-delta modulator for wideband receiver applications
On-Line Event-Driven Hand Gesture Recognition Based on Surface Electromyographic Signals
A 90nm CMOS Bio-potential Signal Readout Front-end with Improved Powerline Interference Rejection
Memristor plasticity enables emergence of synchronization in neuromorphic networks
Electronic skin and electrocutaneous stimulation to restore the sense of touch in hand prosthetics
Power dissipation limits and large margin in wireless sensors
iSSA: An incremental stochastic simulation algorithm for genetic circuits
Rate-Aware Learned Speech Compression
Bifurcation and chaos of Chen's equation
AlphaBlend: Hardware-Algorithm Co-design with Mixed-Alphabet Set Multipliers for DNN Workloads
Second-order sampling of wideband signals
Charge Pump Capacitance Ratio Read Out Design System Approach
Toward In-System Monitoring of OpenCL-Based Designs on FPGA
Memristive Quaternary Content-Addressable Memories for Implementing Boolean Functions
A Digitally-Controlled Fully Differential Low Noise Current Source
Design of a frequency reference based on a PVT-independent transmission line delay
The design of nonuniform-band maxmally decimated filter banks
A 270 MHz, 1.8 V fully differential CMOS operational amplifier for switched capacitor channel select filters in wide-band wireless applications
Memory exploration utilizing scheduling effects in high-level synthesis
A low noise amplifier chain for digital satellite radio applications
Retina model with real time implementation
High-Throughput Digital Readout System for Real-Time Ion Imaging using CMOS ISFET Arrays
A 1-GHz direct digital frequency synthesizer in an FPGA
A returned energy architecture for improved photovoltaic systems efficiency
A passive CMOS low-pass filter for high speed and high SNDR applications
Polynomial expansions over GF(2) based on fastest transformation
The design of a light barrier system as an undergraduate laboratory project
Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
A New Digital Filter Structure Generated by the Schwarz Matrix Form
Two-Type-Interlaced Structure and LBR Test Applied to the Conventional Filter Realization
A semi-static threshold-triggered delay element for low power applications
A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation
Performance analysis of a correlation-based optical flow algorithm under noisy environments
A realistic network traffic forecasting method based on VMD and LSTM network
A hierarchical ZnO nanostructure gas sensor for human breath-level acetone detection
A 7 mW 2.5 GHz spread spectrum clock generator using switch-controlled injection-locked oscillator
On computing multi-dimensional extreme eigen and singular subspaces
Performance enhanced op-amp for 65nm CMOS technologies and below
Design trade-offs of a symmetric linearized CMOS LC VCO
Propagation of Measurement Errors through the DFT
Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators
Optimal design of composite digital filters using convex-concave procedure
High performance Molecular Dynamic simulation on single and multi-GPU systems
An architecture for low-power compressed sensing and estimation in wireless sensor nodes
An analog correlator for a WCDMA receiver
Towards bendable piezoelectric oxide semiconductor field effect transistor based touch sensor
Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI
The Use of Identified Models in the Control of a Chaotic Circuit
Multiplexing chaotic signals in the presence of noise
IIR Digital Filters for Sampling Structure Conversion and Deinterlacing of Video Signals
A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique
A low power CMOS low noise amplifier for ultra-wideband wireless applications
A brief overview of some recent advances in complex dynamical networks control and synchronization
Dual VDD block based CMOS image sensor - preliminary evaluation
Post-production adaptation of RF circuits for application-specific performance metrics
A proportionate type block-oriented functional link adaptive filter for sparse nonlinear systems
Analysis of a type of digital chaotic cryptosystem
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS
Single-phase three-level converter for power factor correction
Universal Switched-Capacitor Converter for DC-DC, AC-DC, and DC-AC Applications
In-memory adder functionality in 1S1R arrays
A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs
Progressive scrambling for MP3 audio
The Computation of Line Spectrum Pair Frequencies using Tschirnhaus Transform
Uncertainty Quantification of Lithium-Ion Batteries with Polynomial Chaos
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array
Visualization of SystemC Designs
5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS
Low-Cost Reservoir Computing using Cellular Automata and Random Forests
A Physical Reservoir Computing Processor for ECG-to-PCG Signals Prediction
A Genetic Algorithm for the Design and Optimization of FRM Digital Filters Over a Canonical Double-Base Multiplier Coefficient Space
A wideband power-efficient inductive wireless link for implantable microelectronic devices using multiple carriers
DCE3 - An universal real-time clustering engine
A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS
A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC
A Compact Low-Noise Digital Pixel with 15-bit Two-Step PFM-based ADC for IRFPAs
A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator
A study on detecting image hiding by feature analysis
A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems
Pediatric Size Swallowable Glass Pill for Digestive Motility Analysis
Pseudo-Resistor Based Attenuator as an Efficient Electrode Driver for Sinusoidal Stimulation of Retinas
Accelerating Large-Scale DLRM Inference through Dynamic Hot Data Rearrangement
A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA
A micropower comparator for high power-efficiency hearing aid class D amplifiers
A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology
A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time Sigma-Delta modulators
Rules maps for scheduling algorithm knowledge
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive
Agriculture Impact on Climate Change and Climate Change Impact on Agriculture - Low Power Design
Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity
Novel radix-2k division algorithm
Improved Factorization for Sample Rate Conversion In Software Defined Radios
Area-efficient fully integrated dual-band class-E/F power amplifier with switchable output power for a BPSK/OOK transmitter
The homotopy cintinuation method to approach voltage collapse of electric power systems
What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?
Hybrid intelligent system for daily maximum temperature forecasting in smart grids
Analog baseband channel for GSM/UMTS/WLAN/Bluetooth reconfigurable multistandard terminals
Cell clinics for bioelectronic interface with single cells
Digital photography-How long will it last?
Fast cycle-accurate compile based simulator for reconfigurable processor
KKT-condition inspired solution of DVFS with limited number of voltage levels
Retiming for BIST-Sequential Circuits
A Failure Detection Technique for Au-Plated CMOS Microelectrode Arrays
Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference
Design Trade-offs in Buck Converters for Low-Energy Wireless Transceivers
Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors
Live Demonstration: A High-Resolution Plantar Insole System for Lower Body Estimation
Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier
Enhanced adaptive playout scheduling and loss concealment techniques for Voice over IP networks
A programmable array of silicon neurons for the control of legged locomotion
Predicting fast-scale instabilities in switching power converters: a ripple-based unified perspective
An Efficient Emotion Detection Scheme for Popular Music
Two-sided projection method in variational equation model order reduction of nonlinear circuits
Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems
Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and Decoder
Combined Linear Prediction and Subspace Based Blind Equalizers
An FPGA based implementation of G.729
A hybrid multimode BCH encoder architecture for area efficient re-encoding approach
Adaptive end-to-end optimization of mobile video streaming using QoS negotiation
Optimizing the Design of Switch-Mode Power Supplies with Battery Back-Up and Power Factor Correction
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS
Two-Stage OTA Design Based on Settling-Time Constraints
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip
Integration of dynamic vision sensor with inertial measurement unit for electronically stabilized event-based vision
Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network
An analogue approach to the design of motion estimators for digital video encoding
Performance analysis for MIMO systems using zero forcing detector over Rice fading channel
A design method of low delay FIR bandpass filters
CMOS Current-Mode Chaotic Neurons
Pipelined belief propagation polar decoders
A capacitor-less low-dropout regulator for SoC with bi-directional asymmetric buffer
On the Persistency of Excitation for Blind Channel Estimation in Cyclic Prefix Systems
A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit
Theoretical analysis of underwater simultaneous light Information and power transfer using inverted N parallel code shift keying with power splitting reciver
Mismatch-based timing errors in current steering DACs
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques
Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems
ADS-B Signal Detection via Time-Frequency Analysis for Radio Astronomy Applications
Spatially Scalable Video-Based Point Cloud Compression
Fully integrated CMOS capacitive sensor for Lab-on-Chip applications