yusuke1997/dblp-id-title huggingface dataset:
A noise-power-area optimized novel programmable gain and bandwidth instrumentation amplifier for biomedical applications
Quadrature oscillator solution suitable with arbitrary and electronically adjustable phase shift
On the equivalence of various methods for finding the periodic steady state solution of nonlinear networks
Controlling a switched beam array antenna using PLL frequency synthesizers based on the congruence modulo
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic
A 1 GHz CMOS transimpedance amplifier for chip-to-chip optical interconnects
A Chopper-Stabilized Bandgap Reference with a Double-Sampled FIR Filter in 180-nm CMOS
Shift register multi-phase clock based downsampled floating tap DFE for serial links
A new switched capacitor circuit for parallel-pixel image processing [vision sensor integrated signal processing]
A Smart Neuroscience Platform with Wireless Power Transmission for Simultaneous Optogenetics and Electrophysiological Recording
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing
Low operating voltage and short settling time CMOS charge pump for MEMS applications
A 64×64 image energy harvesting configurable image sensor
Improving Video Coding at Scene Cuts using Attention based Adaptive Bit Allocation
A discrete-time technique for the steady state analysis of nonlinear switched circuits with inconsistent initial conditions
Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory
Enhancing amplifiers/filters bandwidth by transfer function zeroes
Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers
Video segmentation using multiscale feature extraction and fusion
Time Efficient Method for MOS Circuit Extraction
A 2.7 V CMOS dual-mode baseband filter for GSM and WCDMA
A scalable 3-phase polar decoder
Low-Noise High-Linearity 56Gb/s PAM-4 Optical Receiver in 45nm SOI CMOS
A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e
Design and analysis of a micropower low-voltage bang-bang control class D amplifier
Architecture and optimization of high-throughput belief propagation decoding of polar codes
BDD decomposition for mixed CMOS/PTL logic circuit synthesis
Boost-buck inverter variable structure control for grid-connected photovoltaic systems
Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design
A Low Forward Bias Active Diode Circuit for Electrostatic Energy Harvesters
Bandpass sigma-delta (Σ-Δ) architecture based efficient FM demodulator for software radio
A grounded-output 5-switch bipolar buck-boost converter topology for switching power amplifiers
A critique of SVD-based image coding systems
A new, efficient and flexible error detection approach for compressed visual contents
Design of class AB output stages using the structural methodology
Digital Multiplication using Continuous Valued Digits
Timing-driven X-architecture router among rectangular obstacles
An efficient filter bank architecture for the cross-term reduced processing of discrete time-frequency distributions
Stability study of a voltage-mode buck regulator using system poles approach
Markovian level set for echocardiographic image segmentation
Bifurcation and complex phenomena in chaotic systems coupled by transmission line
A 3.1 Gbin/s advanced entropy coding hardware design for AVS3
A Survey on Recent Developments in SCOAP-based Hardware Trojan Detection Strategies
A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line Transceiver
Implementation of a high-speed low-power 32-bit adder in 70nm technology
A frame stream controller IP
A model for an ARMA process split in sub-bands
Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technology
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers
Network-adaptive rate control with unequal loss protection for scalable video over Internet
Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT)
An All-Digital Time-Domain Compute-in-Memory Engine for Convolutional Neural Networks in 22nm
PUF-based Lightweight Mutual Authentication Protocol for Internet of Things (IoT) Devices
A resistor-less overload detector for dc/dc linear regulators
Practical review of advanced CDMA receivers with emphasis in the downlink
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs
Generalized analysis of soft-switching DC-DC converters
A Linear-Regression-Assisted Trimming Scheme for CMOS Voltage Reference
An efficient and high quality rasterization algorithm and architecture in 3D graphics systems
A 48V Input Merged Cross-Connected Double Step-Down Converter with Package-Integrated GaN Switches and Silicon Controller IC
Carbon nanotube circuit design choices in the presence of metallic tubes
MIMO detection in analog VLSI
Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes
Exact discretization of differential equations by s-z transform
Feature competition in a spike-based winner-take-all VLSI network
ASIP Decoder Architecture for Convolutional and LDPC Codes
Analog Cellular Neural Network with Application to Artial Differential Equations with Variable Mesh-Size
A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization
An Novel Interpretable Fine-grained Image Classification Model Based on Improved Neural Prototype Tree
Concept of transformer-feedback degeneration of low-noise amplifiers
ActionView: a Movement-analysis Ambulatory Monitor in Elderly Homecare Systems
e-Glass: A Wearable System for Real-Time Detection of Epileptic Seizures
Simple yet effective algorithms for block and I/O buffer placement in flip-chip design
Towards Optimal Green Plant Irrigation: Watering and Body Electrical Impedance
A semiblind receiver based upon multiple constrained subspace MUD for long-code downlink multirate DS-CDMA systems
Binary descriptor based SIFT and hardware implementation
Improved Low-distortion DeltaSigma ADC Topology
A comparison of algorithms for sound localization
Sliding-mode approach for start-up control and voltage regulation of a boost converter driving a constant power load
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders
A comparison of quantization noise levels of LDI and wave digital circulator allpass filters
A stepwise constant conductance approach for simulating resonant tunneling diodes
A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatch
Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks
Improved contrast sensitivity DVS and its application to event-driven stereo vision
Multimodal Structure Segmentation and Analysis of Music using Audio and Textual Information
A 14-bit pipelined ADC with digital background nonlinearity calibration
Fair Scheduling Through Collaborative Filtering on Multicore Systems
Live Demonstration: A self-powered ultraviolet radiation monitoring platform based on nonvolatile processor
IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017
Optimized Transformer Models: ℓ′ BERT with CNN-like Pruning and Quantization
A 2.8 μW 0.022 mm2 8 MHz Monolithic Relaxation Oscillator
Seamless roaming in wireless networks for video streaming
A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network
Application of the SD to LCTI systems 1
Complex Phenomena in SEPIC Converter Based on Sliding Mode Control
Analysis of measurement delay errors in an Ethernet based communication infrastructure for power systems
A neural recording system for monitoring shark behavior
Low-complexity decision directed method for carrier frequency offset estimation of IEEE 802.11ad
Improved near-lossless HEVC codec for depth map based on statistical analysis of residual data
Spiking-HDC: A Spiking Neural Network Processor with HDC Classifier Enabling Transfer Learning
Analog VLSI Chip for Stereocorrespondence
An FPGA-based Closed-loop Approach of Angular Displacement for a Resolver-to-Digital-Converter
Low complexity iterative multimedia resource allocation based on game theoretic approach
A high speed feature matching architecture for real-time video stabilization
Jointly minimum MSE transmitter and receiver FIR MIMO filters in the presence of near-end crosstalk and additive noise
An AI-Edge Platform with Multimodal Wearable Physiological Signals Monitoring Sensors for Affective Computing Applications
Spectral analysis of Internet topology graphs
A 13.5-MHz relaxation oscillator with ±0.5% temperature stability for RFID application
Design of wavelet filters based on digital complex allpass filters
Hardware-based support vector machine classification in logarithmic number systems
VLSI processor architecture for real-time GA processing and PE-VLSI design
Adaptive multiple switching strategy toward an ideal NoC
The best approximation to C 2 functions and its error bounds using Gaussian hidden units
High-speed processor for quantum-computing emulation and its applications
Design of projection matrix for compressive sensing by nonsmooth optimization
Canonical PWL network and multilayer perceptron-like networks: A unified view
Implementation of a Stereo Matching algorithm onto a Manycore Embedded System
Design and optimization of CMOS class-E power amplifier
A 0.756-ppm/°C Time-Domain-Based Curvature-Compensated Bandgap Reference
Face recognition system with PCA and moment invariant method
Frequency Shift of Two-Dimensional Real Coefficient Zero Phase Fir Digital Filters
Low-power DA-converters for display applications using stepwise charging and charge recovery
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS
A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link
Partial differential equation models for continuous multidimensional systems
Optimization and implementation of continuous time DSP-systems by using granularity reduction
A single-chip CMOS visual orientation sensor
An optical tracker based registration method using feedback for robot-assisted insertion surgeries
Design method for orientation-selective CNN filters
Averaging method via all numerical computation applied to weakly-nonlinear coupled oscillator systems
Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA
Integrator Based on Local-Feedback Voltage Amplifier and Offset Compensation
Vertically-Integrated Three-Dimensional SOI Photodetectors
On optimal approximation of orthogonal polygons
A sub-100 nW Power, Compact CTDSM with a Band-To-Band Tunnelling Loop Filter
An improved analysis and design methodology for RF Class-E power amplifiers with finite DC-feed inductance and switch On-resistance
Tracking tongue movements for environment control using particle swarm optimization
Relay effects in multiple-node Resonant Inductive Coupling Wireless Power Transfer systems
An effective initial solution algorithm for globally convergent homotopy methods
DCD-based simplified matrix inversion for MIMO-OFDM
A current-mode ADC with adaptive quantization
FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities
Linear range extension of a phase-frequency-detector with saturated output
Piecewise Linear Performance Models for Analog Mixed-Signal Verification
A 30μW, 3.3dB NF CMOS LNA for wearable WSN applications
A Sinusoidal Signal Generator Using a Constant Gain Finite Impulse Response (FIR) Filter for Electrical Bioimpedance Spectroscopy
Exploring Teaching Methods for Courses on Radiation Hardening Technology in ICs
Neuromorphic cochlea implants
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider
SmartNMC: A 1Mb-200µW-20fps near-imager spatio-temporal inference hardware module
Implementation of channel demodulator for DAB system
A Wearable Electrooculogram System with Parallel Motion Artifact Sensing and Reduction
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures
A novel adaptive multi-mode search algorithm for fast block-matching motion estimation
Live Demonstration: An FPGA-Based Emulation of an Event-Based Vision Sensor Using Commercially Available Camera
Rate control for advance video coding (AVC) standard
Constrained circuit optimization via library table genetic algorithms
Supervoxel Segmentation using Spatio-Temporal Lazy Random Walks
Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code
HLS Implementation of Linear Discriminant Analysis Classifier
Continuous-Time Adaptive Delay System
Nyquist VCO-based ADC with Programmable Pulse Shaping Filter for Mitigation of Blockers
Multiresolution Image Coding Using IIR Digital Filters
A modeling platform for efficient characterization of phase-locked loop Delta Sigma frequency synthesizers
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates
Synchronization of multihop ad hoc networks using connected dominating sets
A Scalable and Programmable Sound Synthesizer
Safety Assurance System for Electric Vehicles Based on Infrared LiDAR
Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults
Live Demonstration: Benchmarking Analogue Performance of Emerging Random Access Memory Technologies
A 2-GHz integrated CMOS reflective-type phase shifter with 675° control range
Design of variable Laguerre filters
Analysis of the Transient Bahviour of Unconstrained Frequency-Domain Adaptive Filters
Boosted readout for CMOS APS pixels
Live Demonstration: Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation
Dynamic voltage and frequency scaling circuits with two supply voltages
Effective early termination using adaptive search order for frame rate up-conversion
Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver
Scheduling of Iterative Computing Hardware Units for Accuracy and Energy Efficiency
A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning
Securing On-Chip Learning: Navigating Vulnerabilities and Potential Safeguards in Spiking Neural Network Architectures
A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems
NMOS-only Class-D Output Stages based on Charge Pump Architectures
An SoC compatible linearity test approach for precision ADCs using easy-to-generate sinusoidal stimuli
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system
Delay modeling of CMOS/CPL logic circuits
A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes
A New Architecture of the Phase Frequency Detector with Improved Gain and Minimal Blind Zone for Fast Settling PLLs
High Speed Monolithic Read-Out System for High Energy Physics Experiments
On the design of real and complex FIR filters with flatness and peak error constraints using semidefinite programming
1-V continuous-time linear equalizer for up to 2 Gb/s over 50-m SI-POF
A Low Energy Two-step Successive Approximation Algorithm for ADC Design
Fast sub-pixel inter-prediction - based on texture direction analysis (FSIP-BTDA) [video coding applications]
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems
Gain Enhancement Technique for High-Speed Switched-Capacitor Circuits
Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system
Monaural separation of independent acoustical components
A 635 μW non-contact compensation IC for body channel communication
Architectural design and analysis toolbox to implement shortest path algorithms in hardware
Analysis of Continuous-Time Digital Signal Processors
Backpropagating Errors Through Memristive Spiking Neural Networks
Fundamental Performance Limits in Lossy Polyphase Systems: Apparent Power and Optimal Compensation
Mesh-star Hybrid NoC Architecture with CDMA Switch
A 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach
Fast Analog Layout Retargeting with Device Abstraction
Maximizing power harvest in a distributed photovoltaic system
Node Operation Reduced Decoding for LDPC Codes
Finite iteration DT-CNN - new design and operating principles
A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer
Taylor-series technique for moving source localization in the presence of sensor location errors
A New Approach for the Selection of Test Points for Fault Diagnosis
Greedy Channel Selection for Dynamic Spectrum Access Radios
Real time radar target detection under jamming conditions using wavelet transform on FPGA device
Fast soft-output Viterbi decoding for duo-binary turbo codes
A Compact Measurement Technique for Detector Capacitance of Charge Amplifiers
Power exploration of multimedia applications realized on embedded cores
Design and implementation of a reconfigurable FIR filter
Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics
A 5 GHz fully integrated VCO in a SiGe bipolar technology
Open Two-State Quantum Systems Solved by Harmonic Balance
Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems
Accurate VHDL-based simulation of Sigma-Delta modulators
An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches
Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes
A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell
Design of Interleaved Multithreading for Network Processors on Chip
Ordering chaos of Chua's circuit - A feedback control approach
Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance
A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing
CORDIC Based Pipeline Architecture for All-pass Filters
Accurate Prediction of Resonant Converters' ZVS Behavior in the Time Domain
Software-Defined Networking Architecture for NoC-based Many-Cores
Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications
An embedded low power FIR filter
Performance and RLC crosstalk driven global routing
Frequency dependence of magnetic flux profile in the presence of metamaterials for wireless power transfer
A novel video key frame extraction algorithm
Step-up versus step-down DC/DC converters for RF-powered systems
Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode Feedforward
An updated Cardiovascular Simulation Toolbox
A post-processing method for vector quantization to achieve higher PSNR and nearly constant bit rate
Adversarial Sample Generation for Lithography Hotspot Detection
Quantified Satisfiability-based Simultaneous Selection of Multiple Local Approximate Changes under Maximum Error Bound
Parallel Architecture of List Sphere Decoders
Super-stable energy based switching control scheme for DC-DC buck converter circuits
A back telemetry-capable active high efficiency rectifier in standard CMOS process
A 3 rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization
High frequency transformer modeling
Low voltage 2-path SC bandpass ΔΣ modulator without bootstrapper
An efficient and fair scheduling policy for multiprocessor platforms
General Formulas for the Ideal Flat Gain in the Case of Double Broadband Matching
Symbolic noise analysis in analog integrated circuits
A Formal Approach To Pipeline Optimization in Synthesis of Digital Signal Processors with Fine Grain Parallelism
Impulse sensitivity functions of oscillators
GES: a new image quality assessment metric based on energy features in Gabor transform domain
Period Doubling Route to Chaos in Open Loop Boost Converters under Constant Power Loading and Discontinuous Conduction Mode Conditions
Fast Interframe Transfrom Coding Based on Characteristics of Transform Coefficients and Frame Difference
Machine Learning for Improving Timing Accuracy
A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes
Localization based audio source separation by sub-band beamforming
Electric field for detecting open leads in CMOS logic circuits by supply current testing
Optimum register assignment for heterogeneous register-set architectures
P 2 E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform
A 1.2 V rail-to-rail differential mode input linear CMOS transconductor
A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links
A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces
Design Optimization of Multi-Input Reconfigurable Capacitive DC-DC Converters: A CAD Tool Approach
Design considerations of synaptic device for neuromorphic computing
A power-efficient architecture for high-speed D/A converters
MDFT filter bank multicarrier systems with multiple transmission zeros
A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications
Efficient Implementation of Activation Function on FPGA for Accelerating Neural Networks
CAD system for design and simulation of data converters
High-performance iterative BCH decoder architecture for 100 Gb/s optical communications
A nanowatt bandgap voltage reference for ultra-low power applications
Instruction-based delay fault self-testing of pipelined processor cores
A method for optimal SINR under non-i.i.d. interferences
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis
FPGA-based Fault-injection and Data Acquisition of Self-repairing Spiking Neural Network Hardware
A low-complexity low-distortion topology for wideband delta-sigma ADCs
A Pixel Scale Digital to Analog Converter for Liquid Crystal on VLSI Displays
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm
Improving Scalability of NoC-Based Neuromorphic Hardware with Compressed AER (C-AER) Protocol
Tunable floating-gate low-voltage transconductor
Robust analytical design of equiripple comb FIR filters
SHP-FsNTT: A Scalable and High-Performance NTT Accelerator Based on the Four-step Algorithm
Joint transcoding of multiple MPEG video bitstreams
Low-power, implantable sensing system for signal detection from the central or peripheral nervous system
ECG compression using multiscale recurrent patterns with period normalization
A simple voltage reference with ultra supply independency
A scanning thermal microscopy system with a temperature dithering, servo-controlled interface circuit
A high frequency bandpass continuous-time filter with automatic frequency and Q-factor tuning
Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system
Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors
Adaptive Search Range Motion Estimation Algorithm for H.264/AVC
The CRLB for bilinear systems and its biomedical applications
Fake Satellite Image Detection via Parallel Subspace Learning (PSL)
A probabilistic test instrument using a ΣΔ-encoded amplitude/phase-signal generation technique
Brain electrical activity in epilepsy: characterization of the spatio-temporal dynamics with cellular neural networks based on a correlation dimension analysis
Globally integrated power and clock distribution network
A Non-Intrusive, Single-Sided Car Traffic Monitoring System Based on Low-Cost BLE Devices
A SystemC extension for behavioral level quantification of noise coupling in mixed-signal systems
Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique
A low-power receiver for simultaneous electrocardiogram and respiration rate detection
An Adaptive Shuttering Scheme for Speed-Artifact-Free Swipe Fingerprint Sensor