yusuke1997/dblp-id-title huggingface dataset:
Sub-20 nm design technology co-optimization for standard cell logic
Block-based Static Timing Analysis with Uncertainty
SERA-Float: A Soft Error Resilient Approximate Floating-Point Computing Format
Thinking and Moving: An Efficient Computing Approach for Integrated Task and Motion Planning in Cooperative Embodied AI Systems
Optimal offloading control for a mobile device based on a realistic battery model and semi-markov decision process
Diagnosing root causes of system level performance violations
Mathematical yield estimation for two-dimensional-redundancy memory arrays
A coloring approach to the structural diagnosis of interconnects
Hierarchical partitioning for field-programmable systems
Definition and solution of the memory packing problem for field-programmable systems
Circuit Comparison by Hierarchical Pattern Matching
Architectural-space exploration of approximate multipliers
Formal verification coverage: computing the coverage gap between temporal specifications
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers
A Routing System for Mixed A/D Standard Cell LSIs
Spiking Transformer Hardware Accelerators in 3D Integration
A fast algorithm for the optimal state assignment of large finite state machines
Transformational partitioning for co-design of multiprocessor systems
Efficient layout generation and evaluation of vertical channel devices
Efficient Analytical Placement Algorithm with Hybrid Fence Region Constraints Using Non-Newtonian Fluid Model
A novel design methodology for high performance and low power digital filters
Event driven adaptively controlled explicit simulation of integrated circuits
System energy consumption is a multi-player game
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search
Encoding Multiple Outputs for Improved Column Compaction
Stronger Mixed-Size Placement Backbone Considering Second-Order Information
AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow
VLSI Design and Experimental Demonstration of Photonic Interposers in Thin-Film Lithium Niobate
Intranets and EDA: impact, application, and technology
Invited Paper: Towards the Imagenets of ML4EDA
Reflections on Trusting TrustHUB
ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits
Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA Algorithms
TAU 2015 Contest on Incremental Timing Analysis: Incremental Timing and CPPR Analysis
Piecewise approximate circuit simulation
Machine Learning-Based Test Pattern Generation for Neuromorphic Chips
FinFETs for nanoscale CMOS digital integrated circuits
Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
System-wide energy minimization for real-time tasks: lower bound and approximation
Hyle: An HLS Framework for Hyperdimensional Computing Accelerators on FPGAs
Retiming for High-performance Superconductive Circuits with Register Energy Minimization
MU-MIMO Detection Using Oscillator Ising Machines
On trojan side channel design and identification
Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
GPU Acceleration in VLSI Back-end Design: Overview and Case Studies
A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model
FBT: filled buffer technique to reduce code size for VLIW processors
A model for comparing synchronization strategies for parallel logic-level simulation
Energy efficient address assignment through minimized memory row switching
A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks
ModSpec: An open, flexible specification framework for multi-domain device modelling
Temporal and spatial idleness exploitation for optimal-grained leakage control
Methodology for low power test pattern generation using activity threshold control logic
Application-specific buffer space allocation for networks-on-chip router design
Automated Synthesis of Custom Networks-on-Chip for Real World Applications
Design-for-debugging of application specific designs
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
2011 TAU power grid simulation contest: Benchmark suite and results
Estimating noise in RF systems
Floorplanning by Topological Constraint Reduction
On breakable cyclic definitions
Time domain current waveform simulation of CMOS circuits
Path Sensitization in Critical Path Problem
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning
Modeling and synthesis of behavior, control and dataflow (tutorial)
Clock Scheduling and Clocktree Construction for High Performance ASICS
SMATO: Simultaneous mask and target optimization for improving lithographic process window
On-chip Optical Routing with Waveguide Matching Constraints
System partitioning to maximize sleep time
Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network Accelerators
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits
Efficient use of large don't cares in high-level and logic synthesis
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving
A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AI
A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis
Incorporation of Inductors in Piecewise Approximate Circuit Simulation
Are proximity attacks a threat to the security of split manufacturing of integrated circuits?
Full-Chip Thermal Map Estimation for Commercial Multi-Core CPUs with Generative Adversarial Learning
Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models
Addressing Thermal Throttling in HBM
Endurance Enhancement of Multi-Level Cell Phase Change Memory
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test
Optimization based passive constrained fitting
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems
Optimality and Stability Study of Timing-Driven Placement Algorithms
Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing
Design-aware mask inspection
Improving platform energy: chip area trade-off in near-threshold computing environment
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Thread-criticality aware dynamic cache reconfiguration in multi-core system
Mixed-mode simulation of compiled VHDL programs
ACQUA: Adaptive and cooperative quality-aware control for automotive cyber-physical systems
Chemical-mechanical polishing aware application-specific 3D NoC design
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm
Detailed placement for modern FPGAs using 2D dynamic programming
Multi-Package Co-Design for Chiplet Integration
A Method for Concurrent Decomposition and Factorization of Boolean Expressions
Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips
Sneak path free reconfiguration of via-switch crossbars based FPGA
Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating Cost
The Crossing Distribution Problem
Calculating Resetability and Reset Sequences
Probabilistic construction and manipulation of free Boolean diagrams
Rapid-INR: Storage Efficient CPU-Free DNN Training Using Implicit Neural Representation
Overview of 2020 CAD Contest at ICCAD
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks
Fast, Robust and Accurate Detection of Cache-Based Spectre Attack Phases
A cross-layer approach for resiliency and energy efficiency in near threshold computing
Synthesis of statically analyzable accelerator networks from sequential programs
Pad assignment for die-stacking System-in-Package design
Performance-driven synthesis of asynchronous controllers
A tutorial on logic synthesis for lookup-table based FPGAs
Flexible module generation in the FACE design environment
EMSim+: Accelerating Electromagnetic Security Evaluation with Generative Adversarial Network
Generalized Boolean symmetries through nested partition refinement
BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation
On the global fanout optimization problem
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Time-Constrained Loop Pipelining
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits
Provably secure camouflaging strategy for IC protection
COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge Inference
Debugging with dominance: On-the-fly RTL debug solution implications
OpenDesign flow database: the infrastructure for VLSI design and design automation research
Capacitance Extraction via Machine Learning with Application to Interconnect Geometry Exploration
Scalable compositional minimization via static analysis
DECOR - tightly integrated Design Control and Observation
eXpect: On the Security Implications of Violations in AXI Implementations
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
State look ahead technique for cycle optimization of interacting finite state Moore machines
Neuromorphic Architectures for Scientific Computing: a Structural Characterization Case Study
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
Characteristic faults and spectral information for logic BIST
Post-silicon timing characterization by compressed sensing
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs
Delay and area optimization for compact placement by gate resizing and relocation
PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning
GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design
On the rapid prototyping and design of a wireless communication system on a chip (abstract)
Invited Paper: 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation
HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing
Fidelity metrics for estimation models
An iterative improvement algorithm for low power data path synthesis
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory
Attack Directories on ARM big.LITTLE Processors
Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based Library
AESHA: Accelerating Eigen-decomposition-based Sparse Transformer with Hybrid RRAM-SRAM Architecture
Signature hiding techniques for FPGA intellectual property protection
Multi-Level Logic Minimization Across Latch Boundaries
Proactive temperature balancing for low cost thermal management in MPSoCs
Re-Tangle: A ReRAM-based Processing-in-Memory Architecture for Transaction-based Blockchain
NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations
Brain-Inspired Trustworthy Hyperdimensional Computing with Efficient Uncertainty Quantification
PUF-G: A CAD Framework for Automated Assessment of Provable Learnability from Formal PUF Representations
Stable and efficient reduction of substrate model networks using congruence transforms
A fast wavelet collocation method for high-speed VLSI circuit simulation
Computationally efficient standard-cell FEM-based thermal analysis
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis
Multiversion Concurrency Control on Intermittent Systems
Scalable power grid transient analysis via MOR-assisted time-domain simulations
CONVINCE: a cross-layer modeling, exploration and validation framework for next-generation connected vehicles
FastRoute3.0: a fast and high quality global router based on virtual capacity
Selective instruction set muting for energy-aware adaptive processors
Low-overhead design technique for calibration of maximum frequency at multiple operating points
A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity
Model reduction for DC solution of large nonlinear circuits
An algorithm to reduce test application time in full scan designs
Integrated fault diagnosis targeting reduced simulation
Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method
Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished
Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits
Optimal bus sequencing for escape routing in dense PCBs
A delay model for logic synthesis of continuously-sized networks
HERO: hierarchical EMC-constrained routing
Optimal wiresizing for interconnects with multiple sources
MAXCell: PPA-Directed Multi-Height Cell Layout Routing Optimization using Anytime MaXSAT with Constraint Learning
PVT 2 : process, voltage, temperature and time-dependent variability in scaled CMOS process
Parallel domain decomposition for simulation of large-scale power grids
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory
DaDu Series - Fast and Efficient Robot Accelerators
Improving the Proportion of At-Speed Tests in Scan BIST
Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning
HLSPilot: LLM-based High-Level Synthesis
M-trie: an efficient approach to on-chip logic minimization
Voltage island-driven floorplanning
Evaluating RC-Interconnect Using Moment-Matching Approximations
A new method for the efficient state-assignment of PLA-based sequential machines
BISTSYN - A Built-In Self-Test Synthesizer
Impact of Loop Transformations on Software Reliability
Soft-edge flip-flops for improved timing yield: design and optimization
Hessian-Driven Unequal Protection of DNN Parameters for Robust Inference
SparCIM: A Heterogeneous CIM-Based Accelerator for Large Language Models with Contextual and Unstructured Bit Sparsity
Physics-based compact modeling for nonclassical CMOS
Model order reduction of fully parameterized systems by recursive least square optimization
Cube-packing and two-level minimization
Modeling Techniques for Logic Locking
Design dependent process monitoring for back-end manufacturing cost reduction
The feasibility of on-chip interconnection using antennas
From 2D to 3D NoCs: A case study on worst-case communication performance
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs
A high-level design and optimization tool for analog RF receiver front-ends
Design technology for building wireless systems (tutorial)
Clock schedule verification under process variations
Power grid effects and their impact on-die
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults
Deterministic Test Pattern Generation Techniques for Sequential Circuits
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation Approach
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level
Hybrid on-chip communication architectures for heterogeneous manycore systems
SOLE: Hardware-Software Co-design of Softmax and LayerNorm for Efficient Transformer Inference
Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions
A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring
An efficient control variates method for yield estimation of analog circuits based on a local model
ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations
FAME: A Fault-Pattern Based Memory Failure Analysis Framework
Modeling and Mitigation of Extra-SoC Thermal Coupling Effects and Heat Transfer Variations in Mobile Devices
A new tightly-coupled transient electro-thermal simulation method for power electronics
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits
Design of pipeline analog-to-digital converters via geometric programming
Adaptive performance prediction for integrated GPUs
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization
A hardware-based technique for efficient implicit information flow tracking
An iterative gate sizing approach with accurate delay evaluation
Improved Methods for IC Yield and Quality Optimization Using Surface Integrals
Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on Edge
Layer assignment for high-performance multi-chip modules
Combinational equivalence checking through function transformation
Privacy-preserving deep learning and inference
Dynamic Frequency Boosting Beyond Critical Path Delay
Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations
On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications
First steps towards SAT-based formal analog verification
Automating Analog Circuit Design using Constrained Optimization Techniques
Simulated quenching: a new placement method for module generation
A novel cache bank timing attack
Built-in test generation for synchronous sequential circuits
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
Optimal Orientations of Transistor Chains
Voltage island aware floorplanning for power and timing optimization
Optimal shape function for a bi-directional wire under Elmore delay model
Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC
Tiny Deep Ensemble: Uncertainty Estimation in Edge AI Accelerators via Ensembling Normalization Layers with Shared Weights
Online selection of effective functional test programs based on novelty detection
Control synthesis and delay sensor deployment for efficient ASV designs
Efficient techniques for inductance extraction of complex 3-D geometries
Parallel forward and back substitution for efficient power grid simulation
Performance-centering optimization for system-level analog design exploration
Fast algorithms for IR drop analysis in large power grid
Performance optimization under rise and fall parameters
A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter
Unleashing the potential of MLC STT-RAM caches
Tri-state bus conflict checking method for ATPG using BDD
R 2 T-Tiny: Runtime-Reconfigurable Throughput-Optimized TinyML for Hybrid Inference Acceleration on FPGA SoCs
VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory
Generating instruction sets and microarchitectures from applications
A Framework Environment for Logic Design Support System
Bit-flipping BIST
Fast identification of untestable delay faults using implications
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
Power grid analysis with hierarchical support graphs
A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions
Leveraging protocol knowledge in slack matching
ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to Systems
Transaction level modeling in practice: Motivation and introduction
High Performance Global Placement and Legalization Accounting for Fence Regions
Superfast Full-Scale CPU-Accelerated Global Routing
Flexible interpolation with local proof transformations
ModelMap: A Model-Based Multi-Domain Application Framework for Centralized Automotive Systems
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict
A bipartition-codec architecture to reduce power in pipelined circuits
TOGGLE: Temporal Logic-Guided Large Language Model Compression for Edge
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability
Unification of partitioning, placement and floorplanning
Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing
Timing-driven partitioning for two-phase domino and mixed static/domino implementations
Board-level multi-terminal net routing for FPGA-based logic emulation
RC interconnect synthesis-a moment fitting approach
Test pattern generation based on arithmetic operations
McPOWER: a Monte Carlo approach to power estimation
A wide frequency range surface integral formulation for 3-D RLC extraction
Interleaving based variable ordering methods for ordered binary decision diagrams
A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration
LsCMM-H: A TCO-Optimized Hybrid CXL Memory Expansion Architecture with Log Structure
MIRAGE: Microarchitectural Footprints for Detecting Adversarial Attacks in One-Shot Inference
Evolving EDA Beyond its E-Roots: An Overview
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation
Failure diagnosis of asymmetric aging under NBTI
On detecting delay anomalies introduced by hardware trojans
Securing Hardware through Reconfigurable Nano-Structures
A submicron MOSFET model for simulation of analog circuits
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)
ASAP: An Analytical Strategy for AQFP Placement
What can brain researchers learn from computer engineers and vice versa?
Embedded tutorial: Speed - new paradigms in design for performance
Transportation security in the era of autonomous vehicles: Challenges and practice
Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs
Fast Spectral Methods for Ratio Cut Partitioning and Clustering
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics
Modeling and analysis of nonstationary low-frequency noise in circuit simulators: enabling non monte carlo techniques
Fast and Scalable Gate-Level Simulation in Massively Parallel Systems
Design of system interface modules
Fast Boolean optimization by rewiring
Ravel: assigned-delay compiled-code logic simulation
A hardware accelerated multilevel visual classifier for embedded visual-assist systems
Task Mapping-Assisted Laser Power Scaling for Optical Network-on-Chips
Comparing voltage adaptation performance between replica and in-situ timing monitors
CarbonClarity: Understanding and Addressing Uncertainty in Embodied Carbon for Sustainable Computing
Gate matrix partitioning
Co-simulations of electromagnetic and thermal effects in electronic circuits using non-conformal numerical methods
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994
Control-fluidic CoDesign for paper-based digital microfluidic biochips
IntSim: A CAD tool for optimization of multilevel interconnect networks
Performance estimation of embedded software with instruction cache modeling
Feedback control based cache reliability enhancement for emerging multicores
Statistical timing analysis with two-sided constraints
Static Scheduling of Multi-Domain Memories For Functional Verification
Classifying circuit performance using active-learning guided support vector machines
Discriminate Weight Approximation for Efficient DSP Packing in LLM Accelerators
SF-GRASS: Solver-Free Graph Spectral Sparsification
SAMG: Sparsified graph-theoretic algebraic multigrid for solving large symmetric diagonally dominant (SDD) matrices