yusuke1997/dblp-id-title huggingface dataset:
An integrated secured vehicular ad-hoc network leveraging Kerberos authentication and Blockchain technology
Efficient GPU-Accelerated Bulk Evaluation of the Boys Function for Quantum Chemistry
Improving TCP Fairness by Expiring TCP BBR Considering Frequency
An Incremental Algorithm for (2-ε)-Approximate Steiner Tree Requiring O(n) Update Time
Detecting EDoS Attacks in Cloud Environments Using Machine Learning and Metaheuristic Algorithms
Automated Model Generation for Arteriovenous Shunt Stenosis Detection Using Machine Learning Algorithms
Stochastic Resonance Assisted Successive Interference Cancellation Receiver for Multilevel Modulated Signals
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications
Evaluation of QAOA for black-box serializability problem
Single-Hardware Method to Detect Malicious Communications and Malware on Resource-Constrained IoT Devices
A Hybrid Evolutionary Approach for Multi Robot Coordinated Planning at Intersections
Rank Attack Avoidance Method based on Neighbor Node Rank Variation in RPL Network
DRAS-OD: A Reinforcement Learning based Job Scheduler for On-Demand Job Scheduling in High-Performance Computing Systems
Hardware Mechanism for Detecting Malicious Communication in IoT Devices by using Time-Series Processor Information
The Popular Matching Problem in a (3, 3)-Hypergraph with One-sided Preferences
Acceleration of Sociality-Aware Message Routing in Opportunistic Networks
Two-step Contract Signing Protocol
Alter Ego: Identifying Web Server Certificates Containing IP Addresses As Subjects
Stage-Wise and Hierarchical Training of Linked Deep Neural Networks for Large-Scale Multi-Building and Multi-Floor Indoor Localization Based on Wi-Fi Fingerprinting
Multi-Objective Optimization of Controller Placement in Distributed ONOS Networks
Efficient Cryptographic Processing Using On-Chip GPUs in System-on-Chip Architectures
Parallel GPU Computation of Nuclear Attraction Integrals in Quantum Chemistry
Hardware Acceleration of Underwater Image Color Restoration Algorithm
Information Sharing Scheme Using AoI for DTN-based Evacuation Systems and Its Evaluation
Reduction of Agents Based on Appearance Probability for Agent-based Human Tracking System
An Accurate Positioning Geocast Protocol for Safety Message Dissemination in VANETs
Accountable Ring Signatures from Symmetric-Key Primitives
Flexibility and Privacy: A Multi-Head Federated Continual Learning Framework for Dynamic Edge Environments
A Study of Layer-2 Consortium Blockchain with zk-SNARKs for Medical Information Management
A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design
Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints
Solving the N-Queens Puzzle by a QUBO Model with Quadratic Size
Introduction of Finger-softness Feature into Writer Verification Based on Finger-writing of Simple Symbol
Accelerating Key-Value Store with Layer-2 Transparent Proxy Cache Using DPDK
Issuer-Revocable Issuer-Hiding Attribute-Based Credentials Using an Accumulator
Decentralized Attribute-Based Credentials with Short Attribute Proofs from DualRing
Characteristic Analysis of SNS Videos for Detection of Flaming Using Sentiment Analysis and Principal Component Analysis
Recommendation of dinner menu sequences for small groups considering individual preferences and their lunch menu sequences
An asynchronous P system with improved branch and bound for solving the minimum Steiner tree
A Non-stop Fault-Tolerant Real-Time System-on-Chip/System-in-Package
Impact of Anonymity Indicator "PFDOC Entropy l-Diversity" on Medical Data Utility
A self-stabilizing distributed algorithm for the 1-MIS problem under the distance-3 model
Multithreaded Edge-Assisted Visual SLAM with Keyframe Backup Mechanism
Toward Collision-Free LoRaWAN Communication under the Coexistence with Wi-Fi Networks
Semantic Search of Japanese Sentences Using Distributed Representations
A Serverless Signaling Scheme for WebRTC Using Bluetooth LE
eSilo: Making Silo Secure with SGX
Reducing Testing Time in Penetration Test Automation by Using EPSS and Parallelization
Improved Vulnerability Handling Framework to Automatically Fix Vulnerable Web Applications
Sparse Ternary Matrix Multiplication with Tensor Core for Transformer
CodoMo: Python Model Checking to Integrate Agile Verification Process of Computer Vision Systems
Accelerate Inference of CNN Models on CPU via Column Combining Based on Simulated Annealing
Machine learning prediction of drug dynamics in dasatinib
Real-Time Phase Retrieval Using On-the-Fly Training of Sample-Specific Surrogate Models
Implementation of Cryptanalytic Program for ASCON Using ChatGPT
Implementation and Evaluation of LLM on a CGLA
AGV-Assisted Construction of Dynamic Wi-Fi Fingerprint Databases for Indoor Localization
A UDP-based Data Transmission Scheme Considering Transfer Time for Wireless Multihop Networks and Its Evaluation
Multiplication of Local Formulae and Commutativity of CAs with Essentially 3-Neighborhood Local Functions over Monoid N
Quantum Computer Architecture for Quantum Error Correction with Distributing Process to Multiple Temperature Layers
Ransomware detection using write data obtained from I/O Request Packets
Effect of Integrating Variational Autoencoder with SENet on Dimensionality Reduction in Driving Behavior Learning
Fairly Decentralizing a Hybrid Concurrency Control Protocol for Real-time Database Systems
Analyzing the Vectorization Capability of the Java Vector API
A New Approach to Disabling SSL/TLS: Man-in-the-Middle Attacks are still Effective
Dynamic Screening of Two-Electron Repulsion Integrals in GPU Parallelization
Supporting Multiple OS Types on Estimation of System Call Hook Point by Virtual Machine Monitor
Implementation of the Home Automation System by Using FPGA Platform
On the Practical Dependency of Fresh Randomness in AES S-box with Second-Order TI
Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding
Twelfth International Symposium on Computing and Networking, CANDAR 2024 - Workshops, Naha, Japan, November 26-29, 2024
An Implementation of USB-Enabled Network Isolation for Remote IoT Security Exercises
Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals
A Study of Blockchain-Based Metadata Management and Its Use for Data Verification
Zero-Knowledge Proofs of Connectivity for Labeled Directed Graphs Using Bilinear-Map Accumulator
A Comparative Study between FPGA and DSP for the Efficient Implementation of FIR Filters
A System Call Moving Target Defense for Binary Injections
A Deep Neural Network Translator for Edge Site Implementation
Method for Detecting DoH Communications from Non-Encrypted Information at a Middlebox
Reasoning and Justification System for Domestic Hazardous Behaviors Based on Knowledge Graph of Daily Activities and Retrieval-Augmented Generation
Bicycle-based collision prevention system using iPhone with LiDAR
An FPGA-Oriented Quantization Approach for Vision Transformer with LUT-Friendly Operations
Extended VLIW Processor Based on RISC-V Compressed Instruction Set
How to Efficiently Determine the Lattice Scale for Fuzzy Extractors and Fuzzy Signatures
Verification of IoT Malware Match Rate Using Signatures Created Based on Processor Information
Message and Order Flexible Pairing based Multisignature
Surveillance Routing with a Minimum Number of Drones
Design of Decoded Instruction Cache
Evaluation of Effectiveness of MAC Systems Based on LSM for Protecting IoT Devices
Exploiting Unlabeled RSSI Fingerprints in Multi-Building and Multi-Floor Indoor Localization through Deep Semi-Supervised Learning Based on Mean Teacher
GPU Acceleration of Head-Gordon-Pople Algorithm
PTWT: A reduction technique of page table walking
Encryption Invalidation Attacks: Is your Wi-Fi encryption really working?
Satellite Selection Method by Multiple Receivers on Vehicles for Improving Inter-vehicle Distance Estimation with Local DGNSS
FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster
DC-PaDiM: Fast Anomaly Detection based on Effective Feature Dimension-Compression
Isogeny-based Proxy Signature
GPU Acceleration of Synthetic Image Generation Using Multi-temporal and Single-polarized SAR Images
Dimensionality Reduction Methods Using VAE for Deep Reinforcement Learning of Autonomous Driving
SMOG - An Explicitly Composable Memory Benchmark Suite for Heterogeneous Memory
Improving Raft Performance with Bulk Transfers
LoS Trick: Countermeasure against CPA for DNN Models Using Loss of Significance in Multiply-Accumulate Operations
A Method for Automatic Generation of 3D Background Models Using Fractal Models and Genetic Algorithms
Low-cost implementation of a bicycle assistance embedded system using TensorFlow Lite
An Analysis of Relationship Between Social Bots and Echo Chambers on X in Modern Japan
A Study of the Periodic Performance Degradation of Flash Memory Write Operations in Smartphones
Distributed MQTT Brokers Infrastructure with Network Transparent Hardware Broker
Matthiola incana classification using CNN and class activation maps for model understanding
Context Cache for Multicore RISC-V Processor
A case for edge video processing with FPGA SoC: reversi board detection using Hough transform
Random Number Generation Based on Cryptocurrency Prices and Linear Feedback Shift Register
Real-Time Defense System using eBPF for Machine Learning-Based Ransomware Detection Method
Automated Extraction for Vulnerability Management on PSIRT: A Case Study of Automotive Industry
Proposal and Evaluation for Efficient splitfft and mergefft in FALCON
A Dynamic Splitting TCP Using both Packet Loss Rate and Latency
Auto-tuning Mixed-precision Computation by Specifying Multiple Regions
Dimension-Extended Dragonfly: A More Flexible Interconnection Network Aimed at Reducing Hardware Cost
Advanced Encryption Standard - AES, 4th International Conference, AES 2004, Bonn, Germany, May 10-12, 2004, Revised Selected and Invited Papers
Preliminary Cryptanalysis of Reduced-Round Serpent
More Dual Rijndaels
The Boomerang Attack on 5 and 6-Round Reduced AES
Some Algebraic Aspects of the Advanced Encryption Standard
Relationships among Differential, Truncated Differential, Impossible Differential Cryptanalyses against Word-Oriented Block Ciphers like RIJNDAEL, E2
High-Speed MARS Hardware
An Algebraic Interpretation of AES-128
IBM Comments
The Effects of Multiple Algorithms in the Advanced Encryption Standard
NIST Performance Analysis of the Final Round Java TM AES Candidates
Impossible Differential on 8-Round MARS' Core
The Case for Serpent
Representations and Rijndael Descriptions
Speeding up Serpent
An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists
The Third Advanced Encryption Standard Candidate Conference, April 13-14, 2000, New York, New York, USA
The Cryptanalysis of the AES - A Brief Survey
A Three Rounds Property of the AES
Efficient AES Implementations on ASICs and FPGAs
Efficiency Testing of ANSI C Implementations of Round 2 Candidate Algorithms for the Advanced Encryption Standard
DFA on AES
Refined Analysis of Bounds Related to Linear and Differential Cryptanalysis for the AES
Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms
Fast Implementations of AES Candidates
RC6 as the AES
Performance Evaluation of AES Finalists on the High-End Smart Card
Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware
AES and Future Resiliency: More Thoughts and Questions
Rijndael for AES
Hardware Evaluation of the AES Finalists
The Inverse S-Box, Non-linear Polynomial Relations and Cryptanalysis of Block Ciphers
Complementation-Like and Cyclic Properties of AES Round Functions
A Collision Attack on 7 Rounds of Rijndael
Linearity of the AES Key Schedule
A Comparison of AES Candidates on the Alpha 21264
Comments on Twofish as an AES Candidate
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
AES Finalists on PA-RISC and IA-64: Implementations & Performance
A Comparison of the AES Candidates Amenability to FPGA Implementation
A Performance Comparison of the Five AES Finalists
Attacking Seven Rounds of Rijndael under 192-bit and 256-bit Keys
MARS Attacks! Preliminary Cryptanalysis of Reduced-Round MARS Variants
How Well Are High-End DSPs Suited for the AES Algorithms? AES Algorithms on the TMS320C6x DSP
General Principles of Algebraic Attacks and New Design Criteria for Cipher Components
Performance of the AES Candidate Algorithms in Java
A new fuzzy-clustering-based approach for two-way circuit partitioning
A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks
Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks
On the Size and Generation of Minimal N-Detection Tests
Improved Approach for Noise Propagation to Identify Functional Noise Violations
Satisfiability-Based Detailed FPGA Routing
Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering
Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and Classification
Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications
On Unified Delay Fault Testing
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences
On the Synthesis of Gate Matrix Layout
Carbon Nanotube Electronics
Power-efficient Instruction Encoding Optimization for Embedded Processors
Design of Embedded Systems with Novel Applications
HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications
8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
A Novel Approach to Control a DC-DC Converter Using its Empirical Physical Model
RTL-Datapath Verification using Integer Linear Programming
Bitwise Encoding of Finite State Machines
A New Synthesis of Symmetric Functions
Design of Energy Efficient and Low Delay Posit Multiplier
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application
Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler
Invited Talk: IoT Protocols War and the Way Forward
Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory
Programming and Performance Modelling of Automotive ECU Networks
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test
Novel Architecture of EBC for JPEG2000
COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators
Semi-Custom Design of Adiabatic Adder Circuits
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies
Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
Effective Memory Management and Sparse Aware Cache for Row-Wise Sparse CNNs
Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies
VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010
Multiplierless In-filter Computing for tinyML Platforms
MoM - A Process Variation Aware Statistical Capacitance Extractor
Logic locking emulator on FPGA: A conceptual view
Parallel Model Evaluation for Circuit Simulation on the PACE Multiprocessor
VLSI Architecture for HDTV Motion Estimation Based on Block-Matching Algorithm
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm 2 Segmented Current Steering CMOS DAC
Real-Time, Content Aware Camera - Algorithm - Hardware Co-Adaptation for Minimal Power Video Encoding
RF and RFID Based Object Identification and Navigation System for the Visually Impaired
A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits
High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet
Computational Complexity of Test-Point Insertions and Decompositions
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Partial Product Reduction Based on Look-Up Tables
Process Variations and Process-Tolerant Design
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks
Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis
A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference
OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization
Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms
A 0.29ps FOM Fast Transient any Cap Stable LVR in 28FDSOI
FPGA Based High Performance Double-Precision Matrix Multiplication
A Low Voltage Mixed Signal ASIC for Digital Clinical Thermometer
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications
Design and Implementation of Viterbi Decoder Using FPGAs
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
Hardware-based Detection of Malicious Firmware Modification in Microgrids
Characterization and Implicit Identification of Sequential Indistinguishability
Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests
A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS
Linear Approximation and Differential Attacks on Logic Locking Techniques
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems
17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India
Interconnect Optimization for Timing and Power [IOTAP]
On Electrical Modeling of Imperfect Diffusion Patterning
Embedded Tutorial: General Architectural Concepts for IP Core Re-Use
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks
Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices
Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing
DFM: Linking Design and Manufacturing
A Multiple Terminal Net Routing Algorithm Using Failure Prediction
Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor
Optimal Code and Data Layout in Embedded Systems
A highly testable ASIC for telephone signaling
DSP-The Real Time Technology for the New Millennium
Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers
Deriving Signal Constraints to Accelerate Sequential Test Generation
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC
Threshold Voltage Modeling of Negative Capacitance Double Gate TFET
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
Simulation Acceleration with HW Re-Compilation Avoidance
SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks
Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test
Synthesis-driven Exploration of Pipelined Embedded Processors
Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units
Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF
A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems
Estimating Pre-Placement FPGA Interconnection Requirements
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits
Improved Design Methodology for the Development of Electrically Actuated MEMS Structures
A genetic approach to test application time reduction for full scan and partial scan circuits
FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System
Monitoring AMS Simulation: From Assertions to Features
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing
A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation
Zero Cost Test Point Insertion Technique for Structured ASICs
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework
Tutorial T8A: Realization of RF Front-End for a Cognitive Radio
Efficient Scheduling Techniques for ROBDD Construction
Implementation of NOR Logic Based on Material Implication on CMOL FPGA Architecture
Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation
Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs
Solving Thermal Problems of Hot Chips Using Voronoi Diagrams
A tunable gm-C filter with low variation across Process, Voltage and Temperature
Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support
Low-Cost Redundancy Identification for Combinatorial Circuits
Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc
Building Giga-Transistor [Enterprise] Microprocessors
Instruction-Based Delay Fault Self-Testing of Processor Cores
Low Power Design
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS
Precision Clock Generation with Reference Clock Loss Tolerant Dynamic Tuning to Enable Crystal Less SSD
Scan Delay Testing of Nanometer SoCs
Low Power Code Generation of Multiplication-free Linear Transforms
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
Energy Efficient and Congestion-Aware Router Design for Future NoCs
Online Optimization of Energy Consumption and Makespan for Active Replication based Scheduling Approaches for Real-time Systems
C3L: A Chip for Connected Component Labeling
Tamper Resistance Mechanisms for Secure, Embedded Systems
A Narrow Pulse- Suppressing Filter For Input Buffer
An Architectural support for Digital Microfluidic based Hot-Spot free Computing
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
An Operational Amplifier Model for Test Planning at Behavioral Level
Macro Block Based FPGA Floorplanning
Effective Heuristics for Timing Driven Constructive Placement
Where Analog meets Digital and Beyond
Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications