yusuke1997/dblp-id-title huggingface dataset:
Merging the interface: power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal computing system
A distributed timing analysis framework for large designs
Type-matching clock tree for zero skew clock gating
Late Breaking Results: Decentralized Voting-Based Attestation for IoT Devices
An exact jumper insertion algorithm for antenna effect avoidance/fixing
HERO: hessian-enhanced robust optimization for unifying and improving generalization and quantization performance
Edisim and Edicap: Graphical simulator interfaces
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating
Simulation and SAT-based Boolean matching for large Boolean networks
Layout Optimization by Pattern Modification
The three-dimensional graphical input method for architecture
ABM-SpConv: A Novel Approach to FPGA-Based Acceleration of Convolutional Neural Network Inference
An O( n 1.5 log n ) 1-d Compaction Algorithm
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices
Efficient simulation of critical synchronous dataflow graphs
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
A microprogram simulator
New Performance-Driven FPGA Routing Algorithms
LUT-Based Optimization For ASIC Design Flow
Deterministic Crash Recovery for NAND Flash Based Storage Systems
An analytic technique for router comparison
A Module Generator for Optimized CMOS Buffers
Late Breaking Results: Weight Decay is ALL You Need for Neural Network Sparsification
Clearance-Constrained PCB Global Placement with Heterogeneous Components
The wild west: conquest of complex hardware-dependent software design
Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems
Rapid application specific floating-point unit generation with bit-alignment
DFM rules!
Approximate Equivalence Checking of Noisy Quantum Circuits
Invited: Algorithm-Software-Hardware Co-Design for Deep Learning Acceleration
PIMA-LPN: Processing-in-memory Acceleration for Efficient LPN-based Post-Quantum Cryptography
Work or Sleep: Freshness-Aware Energy Scheduling for Wireless Powered Communication Networks with Interference Consideration
Fault-Tolerance-Oriented Physical Design for Fully Programmable Valve Array Biochips
A tourguide to the AEDCAP Roadmap
A retargetable micro-architecture simulator
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Automated timing model generation
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing
ACE: A Hierarchical Graphical Interface for Architectual Synthesis
Current signature compression for IR-drop analysis
A model for university, industry and government cooperation
Automatic component placement in an interactive minicomputer environment
Government interest and involvement in design automation development the VHSIC perspective
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design
An abstract machine data structure for non-procedural functional models
SCAGuard: Detection and Classification of Cache Side-Channel Attacks via Attack Behavior Modeling and Similarity Comparison
Synthesis of optimal clocking schemes
A Design and Validation System for Asynchronous Circuits
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits
Timing analysis of esterel programs on general-purpose multiprocessors
Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study
The excell method for efficient geometric access to data
A digital computer simulation of a class of lumped and/or distributed four ports
Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP Protection
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping
TCAM enabled on-chip logic minimization
Effective use of a computer aided design system
GSP: A logic simulator for LSI
Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors
Behavioral Modeling for System Design (panel)
Model order reduction for strictly passive and causal distributed systems
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings
Optimal design of central processor data paths
Frameworks - User's Perspective (Panel Abstract)
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects
Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling
Statistical design and optimization for adaptive post-silicon tuning of MEMS filters
Modeling Design Tasks and Tools: The Link Between Product and Flow Model
Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing
Rotation Scheduling: A Loop Pipelining Algorithm
Thermal signature: a simple yet accurate thermal index for floorplan optimization
PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs
3DIC benefit estimation and implementation guidance from 2DIC implementation
Interactive Analog Layout Editing with Instant Placement Legalization
A Power Macromodeling Technique Based on Power Sensitivity
Algorithms for Large-Scale Flat Placement
PLL to the rescue: a novel EM fault countermeasure
Design and Integration Services (Panel Abstract)
Improving performance and lifetime of NAND storage systems using relaxed program sequence
A "true" electrical cell model for timing, noise, and power grid verification
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge
Provably good and practically efficient algorithms for CMP dummy fill
Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs
Logic Extraction and Factorization for Low Power
Weaknesses of commercial data base management systems in engineering applications
Instruction scheduling for reliability-aware compilation
Hypnos: Memory Efficient Homomorphic Processing Unit
SUNMAP: a tool for automatic topology selection and generation for NoCs
Libraries: lifejacket or straitjacket
Learning microarchitectural behaviors to improve stimuli generation quality
Practical methods in coverage-oriented verification of the merom microprocessor
Symbolic guided search for CTL model checking
Global Routing with Crosstalk Constraints
Net Partitions Yield Better Module Partitions
Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects
Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary Data
A fast pseudo-boolean constraint solver
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
Processing-in-SRAM acceleration for ultra-low power visual 3D perception
A logic verifier based on Boolean comparison
Survey of analysis, simulation and modeling for large scale logic circuits
PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup
Algorithm for Vectorizing Logic Simulation and Evaluation of "VELVET" Performance
Optimizing parallel PREM compilation over nested loop structures
Intermittent Systems at Small Scale: Execution Model and Design Guidelines
A new heuristic test generation algorithm for sequential circuits
Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing
AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic Biochips
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods
Novel CNTFET-based Reconfigurable Logic Gate Design
An expected hypervolume improvement algorithm for architectural exploration of embedded processors
A method for rapid testing of beam crossover circuits
Clock Period Optimization During Resource Sharing and Assignment
BLASYS: approximate logic synthesis using boolean matrix factorization
Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires
What input-language is the best choice for high level synthesis (HLS)?
Flight test analysis of missile control systems
An algorithm for frequency-domain noise analysis in nonlinear systems
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Current issues in government interest and involvement in CAD
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
Modeling and analysis of regular symmetrically structured power/ground distribution networks
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems
Bridging High-Level Synthesis to RTL Technology Libraries
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs
ICS Protocol Fuzzing: Coverage Guided Packet Crack and Generation
SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM
Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization
Circuit simulation and timing verification based on MOS/LSI mask information
Accelerating and pruning CNNs for semantic segmentation on FPGA
An Efficient Spare-Line Replacement Scheme to Enhance NVM Security
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture
Dynamic Power Management with Hybrid Power Sources
Reliable and energy-efficient digital signal processing
Boolean Matching for Incompletely Specified Functions
A procedure for generating floor plans computer aided design
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Multi-Level Logic Synthesis Using Communication Complexity
HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing
Evolution of the philosophy and capability for the CAD of digital modules
Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems
Traffic analysis for on-chip networks design of multimedia applications
Application of High Level Interface-Based Design to Telecommunications System Hardware
Energy characterization of filesystems for diskless embedded systems
A new channel routing problem
Modeling Safe Operating Area in Hardware Description Languages
QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code
When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
An algebraic multigrid solver for analytical placement with layout based clustering
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference
Stochastic integral equation solver for efficient variation-aware interconnect extraction
CDALGO - a test pattern generation program
Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures
HLock: Locking IPs at the High-Level Language
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory
SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection
Computer aided test pattern generation for digital processors
Data prediction for response flows in packet processing cache
PriSearch: Efficient Search on Private Data
Computer aids for multilayer printed wiring board design
The VLSI Design Automation Assistant: Prototype system
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing
Position paper role of technology design rules in Design Automation
Efficient Coloring of a Large Spectrum of Graphs
Including variability of physical models into the design automation of cyber-physical systems
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications
BUBBLE: Relationship diagrams using iterative vector approximation
Model Checking in Industrial Hardware Design
The structure and operation of a design language compatible simulator
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
Fault detection and diagnosis of memory system faults
An optimal algorithm for finding disjoint rectangles and its application to PCB routing
Effective bounding techniques for solving unate and binate covering problems
A Novel Covert Timing Channel for Cloud FPGAs
Consistent runtime thermal prediction and control through workload phase detection
M32: A Constructive multilevel Logic Synthesis System
Implementing low-power configurable processors: practical options and tradeoffs
Minimum-implant-area-aware detailed placement with spacing constraints
Description and Simulation of Hardware/Software Systems with Java
LIVAK: A High-Performance In-Memory Learned Index for Variable-Length Keys
Synthesis of Pipelined Instruction Set Processors
An IC design station needs a high performance color graphic display
On Yield Consideration for the Design of Redundant Programmable Logic Arrays
Optimization of placement solutions for routability
Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed
Symbolic Model Checking Using SAT Procedures instead of BDDs
Lightning Talk: The Next Wave of High-level Synthesis
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction
EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit
Symbolic RTL Simulation
RAP-Track: Efficient Control Flow Attestation via Parallel Tracking in Commodity MCUs
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression
IODINE: a tool to automatically infer dynamic invariants for hardware designs
ACED: a hardware library for generating DSP systems
Code Mapping in Heterogeneous Platforms Using Deep Learning and LLVM-IR
Primer: Fast Private Transformer Inference on Encrypted Data
Customer-aware task allocation and scheduling for multi-mode MPSoCs
Formal datapath representation and manipulation for implementing DSP transforms
PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing
A Variable Observation Time Method for Testing Delay Faults
STREAMINGGS: Voxel-Based Streaming 3D Gaussian Splatting with Memory Optimization and Architectural Support
A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays
Will Moore's Law rule in the land of analog?
DistHD: A Learner-Aware Dynamic Encoding Method for Hyperdimensional Classification
Exploiting structure in symmetry detection for CNF
Formal Verification in a Commercial Setting
Speculation Techniques for High Level Synthesis of Control Intensive Designs
VARADE: a Variational-based AutoRegressive model for Anomaly Detection on the Edge
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition
Acceleration of DNN Backward Propagation by Selective Computation of Gradients
Power Considerations in the Design of the Alpha 21264 Microprocessor
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers
Proceedings of the 21st Design Automation Conference, DAC '84, Albuquerque, New Mexico, June 25-27, 1984
A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit Interconnect
Dynamic Search-Space Pruning Techniques in Path Sensitization
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers
Gain-based technology mapping for discrete-size cell libraries
INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware
Memory optimization in single chip network switch fabrics
A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem
Partitioning for VLSI placement problems
DeBuMA: Description, Building and Management of Applications
The N.2 System
Template Aware Coverage: Taking Coverage Analysis to the Next Level
Automatic Verification of Pipelined Microprocessors
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
A Note on Clustering Modules for Floorplanning
The DAC 2012 routability-driven placement contest and benchmark suite
What's Between Simulation and Formal Verification? (Extended Abstract)
IDA: Interconnect delay analysis for integrated circuits
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations
A parameter-driven router
Floorplan sizing by linear programming approximation
Functional test selection based on unsupervised support vector analysis
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols
Hierarchical modeling and simulation in VISTA
HyCaMi: High-Level Synthesis for Cache Side-Channel Mitigation
Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty Estimation
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
An expert-system paradigm for design
Monitoring Reliability in Embedded Processors - A Multi-layer View
Design of Rotary Clock Based Circuits
Formal Verification of Restoring Dividers made Fast and Simple
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology
A database interface for an integrated CAD system
Pearl: A CMOS Timing Analyzer
An algorithm to compact a VLSI symbolic layout with mixed constraints
Liveness evaluation of a cyclo-static DataFlow graph
Lumped Interconnect Models Via Gaussian Quadrature
Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation
ApproxLP: Approximate Multiplication with Linearization and Iterative Error Control
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation
Testing for bridging faults (shorts) in CMOS circuits
Hardware that produces bounded rather than exact results
Improvements in functional simulation addressing challenges in large, distributed industry projects
FastPath: A Hybrid Approach for Efficient Hardware Security Verification
Computer aided design of printed circuit boards using remote graphics and TSO
Content Sifting Storage: Achieving Fast Read for Large-scale Image Dataset Analysis
Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm
A bus router for IC layout
Harvesting aware power management for sensor networks
Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks
Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006
STFL: Energy-Efficient Data Movement with Slow Transition Fast Level Signaling
VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices
Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems
Technology Mapping for Electrically Programmable Gate Arrays
Power and signal integrity challenges in 3D systems
SSDM: smart stack data management for software managed multicores (SMMs)
Computer Aided Programming
Systematic and optimized layout of MOS cells
Verifying inevitability of phase-locking in a charge pump phase lock loop using sum of squares programming
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators
System techniques for time-sharing
Run-time power-down strategies for real-time SDRAM memory controllers
A Rule-Based Placement System for Printed Wiring Boards
A Comprehensive Automated Exploration Framework for Systolic Array Designs
On Minimal Closure Constraint Generation for Symbolic Cell Assembly
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
Side-channel security of superscalar CPUs: evaluating the impact of micro-architectural features
InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs
Design-while-verify: correct-by-construction control learning with verification in the loop
4G terminals: how are we going to design them?
Multilevel Circuit Partitioning
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency
Local search algorithms for timing-driven placement under arbitrary delay models
On-chip power supply network optimization using multigrid-based technique
UltraSPARC-I Emulation
ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption
Mixed-cell-height Placement with Minimum-Implant-Area and Drain-to-Drain Abutment Constraints
Functional Abstraction from Structure in VLSI Simulation Models
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
MMDFL: Multi-Model-based Decentralized Federated Learning for Resource-Constrained AIoT Systems
Design automation and VLSI in the 80's (Position Statement)
DMR3D: dynamic memory relocation in 3D multicore systems
Cloning your mind: security challenges in cognitive system designs and their solutions
Differential public physically unclonable functions: architecture and applications
A language for the description of digital computer processors
A codesign virtual machine for hierarchical, balanced hardware/software system modeling
Inductance 101: Analysis and Design Issues
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation
Circuits for energy harvesting sensor signal processing
MAGE: A Multi-Agent Engine for Automated RTL Code Generation
Panel: What is the Proper System on Chip Design Methodology
Configurable cache subsetting for fast cache tuning
STRIVE: Enabling Choke Point Detection and Timing Error Resilience in a Low-Power Tensor Processing Unit
Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
Performance Directed Technology Mapping for Look-Up Table Based FPGAs
Functional testing techniques for digital LSI/VLSI systems
Intermittent-Aware Neural Network Pruning
Learn-by-Compare: Analog Performance Prediction using Contrastive Regression with Design Knowledge
Cost-aware patch generation for multi-target function rectification of engineering change orders
Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning
A field-programmable pin-constrained digital microfluidic biochip
Dynamic abstraction using SAT-based BMC
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Multiple Error Diagnosis Based on Xlists
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs
Randomness meets feedback: stochastic implementation of logistic map dynamical system
SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields
WET: Write Efficient Loop Tiling for Non-Volatile Main Memory
ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy