yusuke1997/dblp-id-title huggingface dataset:
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints
X-SENSE: Sensing in extreme environments
A Linear-Time, Optimization-Free, and Edge Device-Compatible Hypervector Encoding
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Cycle-True Simulation of the ST10 Microcontroller
Specification decomposition for synthesis from libraries of LTL Assume/Guarantee contracts
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial Functions
Application Performance Prediction and Optimization Under Cache Allocation Technology
Throughput oriented FPGA overlays using DSP blocks
Quantitative Comparison of Power Management Algorithms
SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging
Synthesis of low-overhead configurable source routing tables for network interfaces
Reducing Simulation Testing Time by Parallel Execution of Loosely Coupled Segments of a Test Scenario
Partial witnesses from preprocessed quantified Boolean formulas
Acceleration of probabilistic reasoning through custom processor architecture
Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip
Distributed power-management techniques for wireless network video systems
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees
Performance aware secure code partitioning
Compositional, dynamic cache management for embedded chip multiprocessors
ClockPUF: physical unclonable functions based on clock networks
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes
CSLE: A Cost-sensitive Learning Engine for Disk Failure Prediction in Large Data Centers
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs
Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption Computation
Runtime power estimator calibration for high-performance microprocessors
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
The CAMEL approach to stacked sensor smart cameras
Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs
Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing
Rewiring using IRredundancy Removal and Addition
A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input Gate
DE2: SAT-Based Sequential Logic Decryption with a Functional Description
3D-integration of silicon devices: A key technology for sophisticated products
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs
Computing Timed Transition Relations for Sequential Cycle-Based Simulation
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning
A soft-error resilient route computation unit for 3D Networks-on-Chips
Digital Background Gain Error Correction in Pipeline ADCs
Flow-based partitioning and position constraints in VLSI placement
Disjunctive image computation for embedded software verification
XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?
A constraint-based design space exploration framework for real-time applications on MPSoCs
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects
A four-mode model for efficient fault-tolerant mixed-criticality systems
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme
DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors
Core minimization in SAT-based abstraction
Continuous Safety Verification of Neural Networks
Software enabled wear-leveling for hybrid PCM main memory on embedded systems
Communication-efficient View-Pooling for Distributed Multi-View Neural Networks
AttentionLib: A Scalable Optimization Framework for Automated Attention Acceleration on FPGA
Fast and accurate branch predictor simulation
Unified, ultra compact, quadratic power proxies for multi-core processors
Low-power warp processor for power efficient high-performance embedded systems
User-centric design space exploration for heterogeneous Network-on-Chip platforms
Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs
Interactive presentation: Soft-core processor customization using the design of experiments paradigm
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks
A trace-based method for delay fault diagnosis in synchronous sequential circuits
Topologically homogeneous power-performance heterogeneous multicore systems
Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes
On Reducing Transitions Through Data Modifications
Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation
IDF-Autoware: Integrated Development Framework for ROS-Based Self-Driving Systems Using MATLAB/Simulink
Coverage loss by using space compactors in presence of unknown values
Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling
Emulation of a Fast Reactive Embedded System using a Real Time Operating System
Closed-loop Approach to Perception in Autonomous System
Exploiting SysML v2 Modeling for Automatic Smart Factories Configuration
Adaptive on-the-fly application performance modeling for many cores
Priority scheduling in digital microfluidics-based biochips
Improved offset-analysis using multiple timing-references
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition
TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware
Design-synthesis co-optimisation using skewed and tapered gates
Towards Smart Cattle Farms: Automated Inspection of Cattle Health with Real-Life Data
An efficient static algorithm for computing the soft error rates of combinational circuits
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations
S-LGCN: Software-Hardware Co-Design for Accelerating LightGCN
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
A robust ADC code hit counting technique
Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption
IterL2Norm: Fast Iterative L2-Normalization
Timing verification for adaptive integrated circuits
An online thermal-constrained task scheduler for 3D multi-core processors
DSL methods for CPS simulation in the cloud: Experience report
STAxCache: An approximate, energy efficient STT-MRAM cache
Towards performance and reliability-efficient computing in the dark silicon era
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series
A graph grammar based approach to automated multi-objective analog circuit design
Side-Channel Collision Attacks Against ASCON
Single Chip or Hybrid System Integration
Caspar: Hardware patching for multicore processors
High-Integrity GPU Designs for Critical Real-Time Automotive Systems
Nano-Crossbar based Computing: Lessons Learned and Future Directions
Low-cost implementations of on-the-fly tests for random number generators
SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware
A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system
Creating Value Through Test
Anti-counterfeiting with hardware intrinsic security
A time-triggered ethernet (TTE) switch
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Fast simulation of future 128-bit architectures
Static analysis of asynchronous clock domain crossings
Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale Integration
Accelerating arithmetic kernels with coherent attached FPGA coprocessors
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment
Debugging of inconsistent UML/OCL models
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling
Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems
SEAL: Sensing Efficient Active Learning on Wearables through Context-awareness
High Speed Neural Network Chip for Trigger Purposes in High Energy Physics
Dynamic reconfiguration in sensor networks with regenerative energy sources
Scheduling for energy efficiency and fault tolerance in hard real-time systems
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
Future Computing Platform Design: A Cross-Layer Design Approach
HiDP: Hierarchical DNN Partitioning for Distributed Inference on Heterogeneous Edge Platforms
Using emerging technologies for hardware security beyond PUFs
Formal methods for ranking counterexamples through assumption mining
Energy efficient multiprocessor task scheduling under input-dependent variation
An Event-Driven System-Level Noise Analysis Methodology for RF Systems
Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections
Overcoming limitations of the SystemC data introspection
A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems
Transparent offloading of computational hotspots from binary code to Xeon Phi
Smart devices panel session - Integrating the real world interfaces
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits
FPGA-based adaptive computing for correlated multi-stream processing
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections
TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking Models
Error Detection/Correction in DNA Algorithmic Self-Assembly
TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU
MALEC: a multiple access low energy cache
Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators
Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013
A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation
A Low Power Strategy for Future Mobile Terminals
CUBA: Chained Unanimous Byzantine Agreement for Decentralized Platoon Management
Test and reliability challenges in automotive microelectronics
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code
Synthesis of CMOS Analog Cells Using AMIGO
Observable Time Windows: Verifying the Results of High-Level Synthesis
A design method for remote integrity checking of complex PCBs
UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency
Value-based bit ordering for energy optimization of on-chip global signal buses
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI
From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++
An LOCV-based static timing analysis considering spatial correlations of power supply variations
Exploiting more parallelism from write operations on PCM
DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference
Wave pipelining for majority-based beyond-CMOS technologies
A Game Theoretic Approach to Low Energy Wireless Video Streaming
Instruction Set Extension Exploration in Multiple-Issue Architecture
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor
TAPP: temperature-aware application mapping for NoC-based many-core processors
Partial online-synthesis for mixed-grained reconfigurable architectures
SOFIA: Software and control flow integrity architecture
Automatic Verification of Scheduling Results in High-Level Synthesis
Different Approaches to Add Reconfigurability in a SoC Architecture
Accelerators and emulators: Can they become the platform of choice for hardware verification?
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network
A New Embedded Measurement Structure for eDRAM Capacitor
Reusing trace buffers to enhance cache performance
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators
Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology
Protocol Stack-Based Telecom-Emulator
Improvements in Polynomial-Time Feasibility Testing for EDF
RLPlanner: Reinforcement Learning Based Floorplanning for Chiplets with Fast Thermal Analysis
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
Automated system testing using dynamic and resource restricted clients
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits
High-Performance QuIDD-Based Simulation of Quantum Circuits
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing
Technology Mapping for Minimizing Gate and Routing Area
Enabling vertical wormhole switching in 3D NoC-bus hybrid systems
Masking timing errors on speed-paths in logic circuits
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture
Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems
FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs
Correlation manipulating circuits for stochastic computing
SACHa: Self-Attestation of Configurable Hardware
MTTF-balanced pipeline design
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs
An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems
Low power design of the X-GOLD ® SDR 20 baseband processor
A New Approach to Component Testing
T-SKID: Predicting When to Prefetch Separately from Address Prediction
Global Responsibilities in SOC Design
Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits
Dynamic Scheduling on Heterogeneous Multicores
Shared Data Kills Real-Time Cache Analysis. How to Resurrect It?
SEDG: Stitch-Compatible End-to-End Layout Decomposition Based on Graph Neural Network
A high performance split-radix FFT with constant geometry architecture
Accurate Area and Delay Estimators for FPGAs
Out-of-order parallel simulation for ESL design
Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture
Leader: Accelerating ReRAM-based main memory by leveraging access latency discrepancy in crossbar arrays
Adaptable Demonstrator Platform for the Simulation of Distributed Agent-Based Automotive Systems
Identification of process/design issues during 0.18 µm technology qualification for space application
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs
HolyLight: A Nanophotonic Accelerator for Deep Learning in Data Centers
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement
A Memory-based Architecture for MPEG2 System Protocol LSIs
A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy
Sequential analysis driven reset optimization to improve power, area and routability
Improving utilization of reconfigurable resources using two dimensional compaction
COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions
GAN-Sec: Generative Adversarial Network Modeling for the Security Analysis of Cyber-Physical Production Systems
A Generic Architecture for On-Chip Packet-Switched Interconnections
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-Time Memory Diagnostic Data Compression in Automotive SoCs
False-Noise Analysis for Domino Circuits
Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis
Lightweight middleware for seamless HW-SW interoperability, with application to wireless sensor networks
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications
Poros: One-Level Architecture-Mapping Co-Exploration for Tensor Algorithms
A new field programmable system-on-a-chip for mixed signal integration
A Web-Based System for Assessing and Searching for Designs
A real-time smart sensor system for visual motion estimation
BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA
iRw: An Intelligent Rewriting
Impact of resistive-open defects on the heat current of TAS-MRAM architectures
Towards a Kernel Language for Heterogeneous Computing
SafeSU-2: a Safe Statistics Unit for Space MPSoCs
PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation
A Triple-Mode Reconfigurable Sigma-Delta Modulator for Multi-Standard Wireless Applications
Error correcting code analysis for cache memory high reliability and performance
Composition Trees in Finding Best Variable Orderings for ROBDDs
Systemic Embedded Software Generation from SystemC
On refining standard cell placement for self-aligned double patterning
Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits
A flexible floating-point wavelet transform and wavelet packet processor
A new approach for adaptive failure diagnostics based on emulation test
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique
Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis
Improved practical differential fault analysis of grain-128
EMAClave: An Efficient Memory Authentication for RISCV Enclaves
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
Efficient utilization of scratch-pad memory in embedded processor applications
Enabling fine-grain leakage management by voltage anchor insertion
Hidden-Delay-Fault Sensor for Test, Reliability and Security
EGIS: Entropy Guided Image Synthesis for Dataset-Agnostic Testing of RRAM-Based DNNs
Synthesis of system verilog assertions
M2H: Optimizing F2FS via Multi-log Delayed Writing and Modified Segment Cleaning based on Dynamically Identified Hotness
Inexact designs for approximate low power addition by cell replacement
Accurate and scalable reliability analysis of logic circuits
Parametric Fault Simulation and Test Vector Generation
Design Space Exploration for Model-based Communication Systems
KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS
Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate
Communication-Efficient Model Parallelism for Distributed In-Situ Transformer Inference
ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics
Interactive presentation: System level power optimization of Sigma-Delta modulator
Model-Based Specification and Execution of Embedded Real-Time Systems
Adaptively tolerate power-gating-induced power/ground noise under process variations
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6
Hardware aging-based software metering
On the Use of Hackathons to Enhance Collaboration in Large Collaborative Projects : - A Preliminary Case Study of the MegaM@Rt2 EU Project -
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors
Optimization of the PLL configuration in a PLL-based TRNG design
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip
A Log-aware Synergized scheme for page-level FTL design
Optimizing the generation of object-oriented real-time embedded applications based on the real-time specification for Java
GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing
Extending IP-XACT to support an MDE based approach for SoC design
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs
Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices
An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelines
IP Testing - The Future Differentiator?
Minimization of NBTI performance degradation using internal node control
Fault Tolerant Non-Volatile spintronic flip-flop
Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems
Efficient design space exploration of high performance embedded out-of-order processors
Reconfigurable asynchronous pipelines: From formal models to silicon
Secure Cyber-Physical Systems: Current trends, tools and open research problems
Efficient bit-error-rate estimation of multicarrier transceivers
NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems
Thermal-aware memory mapping in 3D designs
Fast and Low-Precision Learning in GPU-Accelerated Spiking Neural Network
Run-time consistency checking in discrete simulation models
Machine learning-based anomaly detection for post-silicon bug diagnosis
Towards parallel execution of IEC 61131 industrial cyber-physical systems applications
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks
Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart
Transformational Placement and Synthesis
Network processors: a perspective on market requirements, processor architectures and embedded S/W tools
Fast statistical analysis of RC nets subject to manufacturing variabilities
Crosstalk avoidance codes for 3D VLSI