yusuke1997/dblp-id-title huggingface dataset:
Using Texture Mapping with Mipmapping to Render a VLSI Layout
Survival strategies for mixed-signal systems-on-chip (panel session)
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
A retrospective on software engineering in design automation
Worst-case circuit delay taking into account power supply variations
A unified treatment of PLA faults by Boolean differences
Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield Evaluation
Component-based design approach for multicore SoCs
LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
Automatic Tub Region Generation for Symbolic Layout Compaction
Introducing Redundant Computations in a Behavior for Reducing BIST Resources
Multilevel k -way Hypergraph Partitioning
Proceedings of the 15th Design Automation Conference, DAC '78, Las Vegas, Nevada, USA, June 19-21, 1978
A multi-pass, multi-algorithm approach to PCB routing
Non-integral event timing for digital logic simulation
Distributed task migration for thermal management in many-core systems
A semiempirical model for wakeup time estimation in power-gated logic clusters
Interconnect Analysis: From 3-D Structures to Circuit Models
Accurate temperature estimation using noisy thermal sensors
Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT
Perform-ML: performance optimized machine learning by platform and content aware customization
GRAFOS - A symbolic routing language
Invited: New Solutions on LLM Acceleration, Optimization, and Application
Toward Synthesis from English Descriptions
Designing High Performance CMOS Microprocessors Using Full Custom Techniques
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
POSE: Power Optimization and Synthesis Environment
An Efficient STT-RAM Last Level Cache Architecture for GPUs
Self-referential verification of gate-level implementations of arithmetic circuits
Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware
Logic design system in Japan
Courteous cache sharing: being nice to others in capacity management
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm
Plug-n-learn: automatic learning of computational algorithms in human-centered internet-of-things applications
Chisel: constructing hardware in a Scala embedded language
STCG: State-Aware Test Case Generation for Simulink Models
A design of and design tools for a novel quantum dot based microprocessor
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization
The semiconductor industry's nanoelectronics research initiative: motivation and challenges
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory
Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
You Can Get There From Here: Connectivity of Random Graphs on Grids
Generic lithography modeling with dual-band optics-inspired neural networks
On the Scheduling of Fault-Tolerant Mixed-Criticality Systems
Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction
FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference
A vertically integrated VLSI design environment
ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models
Event-driven gate-level simulation with GP-GPUs
Plugging versus logging: a new approach to write buffer management for solid-state disks
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints
Flexible on-chip power delivery for energy efficient heterogeneous systems
WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime
A Sparse Image Method for BEM Capacitance Extraction
A production PCB layout system on a minicomputer
AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits
The Impact of NBTI on the Performance of Combinational and Sequential Circuits
Logic simulation and fault analysis of a self-checking switching processor
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays
Nanometer design: place your bets
ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation
HyCiM: A Hybrid Computing-in-Memory QUBO Solver for General Combinatorial Optimization Problems with Inequality Constraints
Robust, stable time-domain methods for solving MPDEs of fast/slow systems
An Efficient Accelerator for Point-based and Voxel-based Point Cloud Neural Networks
Hierarchical circuit extraction with detailed parasitic capacitance
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained Applications
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits
Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures
RedCache: Reduced DRAM Caching
Computation of accurate interconnect process parameter values for performance corners under process variations
Integration of Hardware and Software in Embedded Systems Design (Panel Abstract)
Scalable trajectory methods for on-demand analog macromodel extraction
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000
On routing two-point nets across a channel
Reliable computing with ultra-reduced instruction set co-processors
FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel Attacks
PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance
Custom is from Venus and synthesis from Mars
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
CuMAPz: a tool to analyze memory access patterns in CUDA
Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation
Comprehensive optimization of scan chain timing during late-stage IC implementation
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent
Late Breaking Result: AQFP-aware Binary Neural Network Architecture Search
Computing Signal Delay in General RC Networks by Tree/Link Partitioning
Generalized SAT-sweeping for post-mapping optimization
To DFM or not to DFM?
FlexReduce: Flexible All-reduce for Distributed Deep Learning on Asymmetric Network Topology
Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels
Design challenges for secure implantable medical devices
MPTLsim: a simulator for X86 multicore processors
Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques
A Programmable Hardware Accelerator for Compiled Electrical Simulation
Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference
Leakage power optimization with dual-V th library in high-level synthesis
Word level predicate abstraction and refinement for verifying RTL verilog
Generic Global Placement and Floorplanning
An Object-Oriented Approach to Data Management: Why Design Databases Need It
An algorithmic pretest development for fault identification in analog networks
PDRAM: a hybrid PRAM and DRAM main memory system
Fast, cheap and under control: the next implementation fabric
Specification techniques
Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints
Performance-Driven System Partitioning on Multi-Chip Modules
Designing mega-ASICs in nanogate technologies
Linear Sifting of Decision Diagrams
An algorithm for searching shortest path by propagating wave fronts in four quadrants
An over-the-cell router
HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery
Exploiting design-for-debug for flexible SoC security architecture
Integrated circuit security techniques using variable supply voltage
Hardware Trojan horse detection using gate-level characterization
A two-dimensional placement algorithm for the master slice LSI layout problem
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
Which ASIC Technology Will Dominate the 1990's (Panel Abstract)
A New Area and Shape Function Estimation Technique for VLSI Layouts
A minicomputer based Interactive Graphics System as used for electronic design and automation
The Standard Transistor Array (star) (Part II automatic cell placement techniques)
Effectively Sanitizing Embedded Operating Systems
CIRUS: a scalable modular architecture for reusable drivers
Polyhedral model based mapping optimization of loop nests for CGRAs
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator
A general framework for accurate statistical timing analysis considering correlations
A Web-CAD methodology for IP-core analysis and simulation
Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993
Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate Estimation
Abstraction-based performance verification of NoCs
Security and privacy challenges in industrial internet of things
A Universal Method for Task Allocation on FP-FPS Multiprocessor Systems with Spin Locks
AUTOLOFT: The AUTOLOFT geometric processor
Computer aided design college of architecture University of Kentucky
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits
Computer-aided design and practice in city college school of architecture
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors
Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs
Circuit modeling for practical many-core architecture design exploration
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999
Reconfigurable pipelined coprocessor for multi-mode communication transmission
A layout synthesis system for NMOS gate-cells
MiniBit: bit-width optimization via affine arithmetic
An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits
ARIES: A workstation based, schematic driven system for circuit design
Misuse and limitations of simulation as a business research technique: Some comments
Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections
Smart phone power
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors
Applications of logic simulation in design automation at Texas Instruments
ALLENDE: a procedural language for the hierarchical specification of VLSI layouts
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits
A functional level modelling language for digital simulation
Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic Computing
Mos LSI computer aided design system
Proof-Aided Design of Verified Hardware
Hierarchical dynamic router
Proceedings of the 5th annual Design Automation Workshop, DAC '68, Washington, DC, USA, July 15-18, 1968
An architecture-agnostic integer linear programming approach to CGRA mapping
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Don't Cross Me! Cross-layer System Security
Automated design of tunable impedance matching networks for reconfigurable wireless applications
P-DAC: Power-Efficient Photonic Accelerators for LLM Inference
Finite element mesh generation employing satellite graphics
A watermarking system for IP protection by a post layout incremental router
Reshaping EDA for power
Vanguard: a chip physical design system
Effective model-based mask fracturing for mask cost reduction
Logic Synthesis for Efficient Pseudoexhaustive Testability
RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference
Design Automation in the Soviet Union: History and Status (Abstract)
Physical unclonable functions-based linear encryption against code reuse attacks
Design Methodology for Analog High Frequency ICs
Practical Statistical Design of Complex Integrated Circuit Products
Layout effects in fine grain 3D integrated regular microprocessor blocks
Invited - Ultra low power integrated transceivers for near-field IoT
High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization
Power Distribution Topology Design
LEMAX: learning-based energy consumption minimization in approximate computing with quality guarantee
Reconfigurable multi-function logic based on graphene P-N junctions
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug
Identifying System-on-Chip Security Assets with Structure-Based Analysis
Instruction encoding synthesis for architecture exploration using hierarchical processor models
Branch-Aware Loop Mapping on CGRAs
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture
Cross-Attention for AES Mode Variation in Side-Channel Analysis
Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs
Buffer sizing for clock power minimization subject to general skew constraints
Retargetable profiling for rapid, early system-level design space exploration
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs
N-detection under transparent-scan
RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Performance Evaluation of an Event-Driven Logic Simulation Machine
Efficient reinforcement learning for automating human decision-making in SoC design
Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing
Transformation rules for designing CNOT-based quantum circuits
Routability-Driven Blockage-Aware Macro Placement
PARIS and ELSA: an elastic scheduling algorithm for reconfigurable multi-GPU inference servers
LL-PCM: Low-Latency Phase Change Memory Architecture
On-device Malware Detection using Performance-Aware and Robust Collaborative Learning
Considering diagnosis functionality during automatic system-level design of automotive networks
Optimal cell flipping in placement and floorplanning
Multiple defect diagnosis using no assumptions on failing pattern characteristics
Material implication in CMOS: a new kind of logic
DyGNN: Algorithm and Architecture Support of Dynamic Pruning for Graph Neural Networks
Splicer: A Heuristic Approach to Connectivity Binding
Profile-guided microarchitectural floorplanning for deep submicron processor design
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms
DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel)
Non-Scan Design-for-Testability Techniques for Sequential Circuits
The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut Placement
LiveSynth: Towards an Interactive Synthesis Flow
Theoretical analysis of gate level information flow tracking
Energy optimal speed control of devices with discrete speed sets
Obtaining and reasoning about good enough software
Increasing Soft Error Resilience by Software Transformation
Reduced Offsets for Two-Level Multi-Valued Logic Minimization
PETNet: Polycount and Energy Trade-off Deep Networks for Producing 3D Objects from Images
On the Verification of Sequential Machines at Differing Levels of Abstraction
Satometer: how much have we searched?
Feedback-controlled reliability-aware power management for real-time embedded systems
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics
Functional simulation shortens the development cycle of a new computer
Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract)
Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios
Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
A prototyping and simulation approach to interactive computer system design
Retargetable Self-Test Program Generation Using Constraint Logic Programming
WCET-aware register allocation based on graph coloring
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics
An MPSoC for energy-efficient database query processing
Test generation for designs with multiple clocks
EUV and e-beam manufacturability: challenges and solutions
Integrated placement/routing in sliced layouts
A Practical Repeater Insertion Method in High Speed VLSI Circuits
HARS: a heterogeneity-aware runtime system for self-adaptive multithreaded applications
New Computational Results and Hardware Prototypes for Oscillator-based Ising Machines
Technology rules- the other side of technology dependent code
At-Speed Delay Testing of Synchronous Sequential Circuits
Electrical considerations in the computer aided design of logic circuit interconnections
User Experience with High Level Formal Verification (Panel)
Transmit or Discard: Optimizing Data Freshness in Networked Embedded Systems with Energy Harvesting Sources
Layout aware line-edge roughness modeling and poly optimization for leakage minimization
Automated synthesis of efficient binary decoders for retargetable software toolkits
Diagnosis and Correction of Logic Design Errors in Digital Circuits
Optimization of the influence of problem modifications on given microprogrammed controllers
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network
Switched by input: power efficient structure for RRAM-based convolutional neural network
A fast passivity test for descriptor systems via structure-preserving transformations of Skew-Hamiltonian/Hamiltonian matrix pencils
Ultra-Efficient Processing In-Memory for Data Intensive Applications
Coding for system-on-chip networks: a unified framework
Workshop introduction to gate array placement and routing packages
Multi-objective bayesian optimization for analog/RF circuit synthesis
Non-uniform micro-channel design for stacked 3D-ICs
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing
AccMoS: Accelerating Model Simulation for Simulink via Code Generation
A DVS-based pipelined reconfigurable instruction memory
Design automation algorithms: Research and applications
Self-Attention to Operator Learning-based 3D-IC Thermal Simulation
Methods of modelling digital devices for logic simulation
Rescuing Memristor-based Neuromorphic Design with High Defects
A DFT Method for Time Expansion Model at Register Transfer Level
A data structure for gridless routing
An experimental input system of hand-drawn logic circuit diagram for LSI CAD
Loom: exploiting weight and activation precisions to accelerate convolutional neural networks
SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural Networks
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips
A systolic design rule checker
Fast and scalable human pose estimation using mmWave point cloud
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits
Precise failure localization using automated layout analysis of diagnosis candidates
A 2 BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Resurrecting infeasible clock-gating functions
A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line Interconnections
Architecture-level synthesis for automatic interconnect pipelining
Symbolic Prime Generation for Multiple-Valued Functions
Real time diagnosis using single pin probe
SEALS: sensitivity-driven efficient approximate logic synthesis
Distributed and Parallel Demand Driven Logic Simulation
Plowing: Interactive stretching and compaction in magic
Architecture-aware Precision Tuning with Multiple Number Representation Systems
The three dimensions of architectural design automation
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case
IPR: An Integrated Placement and Routing Algorithm
Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating
FPGA power reduction using configurable dual-Vdd
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations
Incremental Tree Height Reduction for High Level Synthesis
Software Patents and Their Potential Impact on the EDA Community (Panel)
Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs
A new look at test generation and verification
ZeroTetris: A Spacial Feature Similarity-based Sparse MLP Engine for Neural Volume Rendering
Incremental processing applied to Steinberg's placement procedure
Formal verification of module interfaces against real time specifications
AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processors
Design and reliability challenges in nanometer technologies
Switch-level emulation
NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core
Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR
Efficient transistor-level timing yield estimation via line sampling
Cell map representation for hierarchical layout
MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits
Computer aided input/output for use with the finite element method of structural analysis
A scalable software-based self-test methodology for programmable processors
Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis
Competitive strategies for the electronics industry
Effects of FPGA Architecture on FPGA Routing
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
Defect tolerant probabilistic design paradigm for nanotechnologies
Proceedings of the 17th Design Automation Conference, DAC '80, Minneapolis, Minnesota, USA, June 23-25, 1980
Circuit design aids on unix
"An interactive, graphical system for the design of photomasks"
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
Evaluation of functional mock-up interface for vehicle power network modeling
Proceedings of the 29th Design Automation Conference, Anaheim, California, USA, June 8-12, 1992
A case study in process independence
Behavioral Synthesis
An Efficient Delay Test Generation System for Combinational Logic Circuits
PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code
Parallel Logic Simulation of VLSI Systems