yusuke1997/dblp-id-title huggingface dataset:
Umweltinformatik '00, Umweltinformation für Planung, Politik und Öffentlichkeit, 12. Internationales Symposium "Informatik für den Umweltschutz" der Gesellschaft für Informatik (GI), Bonn, 4.-6.10.2000, Band I
On the Suitabilitz of the "Hydrologic Evaluation of Landfill Performance" (HELP) Model of the U.S. Envrionmental Protection Agency for the Simulation of the Water Balance of Landfill Covers
Environment Software Featuring Interactive Interface
Einbettung von Interpolationsverfahren in die Anfragesprache SQL zur Bearbeitung von Umwelt-Meßwerten
User Interface Management in Distributed Systems
Konzeption rechnergestützter Suchhilfen für die Beschaffung von Chemikaliendaten
Entwicklungstendenzen in Waldökosystemen - Ergebnisse der Scannerbildanalyse auf einem Parallelrechner
Zur Rahmenkonzeption des Umweltinformationssystems Banden- Württemberg
Informatik für den Umweltschutz / Computer Science for Environmental Protection, 6. Symposium, München, 4.-6. Dezember 1991, Proceedings
EXCEPT- Ein Expertensystem zur Unterstützung und Dokumentation von Bewerungsvorgägen in der Umweltverträglichkeitsprüfung
Scattered Data Algorithmen zur Umweltdatenvisualisierung
Radioecological Analysis Support System
Stochastische Modelle für den Stofftransport in der wasserungesättigten Bodenzone
Technology for Global and Regional Environmental Decision-Making
Call Control and Routing in SONET Rings
Fast Matching Method for DNA Sequences
On-Line Bin Packing with Arbitrary Release Times
Streaming Algorithms for Data in Motion
CR-precis: A Deterministic Summary Structure for Update Data Streams
A More Effective Linear Kernelization for Cluster Editing
An Effective Refinement Algorithm Based on Swarm Intelligence for Graph Bipartitioning
Optimal Commodity Distribution for a Vehicle with Fixed Capacity Under Vendor Managed Inventory
On the L(h, k)-Labeling of Co-comparability Graphs
An Efficient Algorithm for Solving the Container Loading Problem
Extending the Hardness of RNA Secondary Structure Comparison
Robust Optimization Model for a Class of Uncertain Linear Programs
A New Load Balanced Routing Algorithm for Torus Networks
Constrained Cycle Covers in Halin Graphs
Energy Efficient Heuristic Scheduling Algorithms for Multimedia Service
Phrase-Based Statistical Language Modeling from Bilingual Parallel Corpus
Application of Copula and Copula-CVaR in the Multivariate Portfolio Optimization
On the Complexity and Approximation of the Min-Sum and Min-Max Disjoint Paths Problems
A New (t, n)-Threshold Scheme Based on Difference Equations
All-Pairs Ancestor Problems in Weighted Dags
A Fast Asymptotic Approximation Scheme for Bin Packing with Rejection
The Tight Bound of First Fit Decreasing Bin-Packing Algorithm Is FFD(I) <= 11/9OPT(I) + 6/9
Lagrangian Relaxation and Cutting Planes for the Vertex Separator Problem
On the On-Line Weighted k-Taxi Problem
Inverse Min-Max Spanning Tree Problem Under the Weighted Sum-Type Hamming Distance
On the Complexity of the Max-Edge-Coloring Problem with Its Variants
A New Succinct Representation of RMQ-Information and Improvements in the Enhanced Suffix Array
Heuristic Search for 2D NMR Alignment to Support Metabolite Identification
Combinatorics, Algorithms, Probabilistic and Experimental Methodologies, First International Symposium, ESCAPE 2007, Hangzhou, China, April 7-9, 2007, Revised Selected Papers
Quantitative Analysis of Multi-hop Wireless Networks Using a Novel Paradigm
Finding Pure Nash Equilibrium of Graphical Game Via Constraints Satisfaction Approach
A Digital Watermarking Scheme Based on Singular Value Decomposition
Optimal Semi-online Algorithms for Scheduling with Machine Activation Cost
On the Minimum Risk-Sum Path Problem
Optimal Semi-online Scheduling Algorithms on a Small Number of Machines
Sequential Vector Packing
Clique-Transversal Sets in Cubic Graphs
A Bijective Code for k -Trees with Linear Time Encoding and Decoding
A Tighter Analysis of Set Cover Greedy Algorithm for Test Set
Model Futility and Dynamic Boundaries with Application in Banking Default Risk Modeling
Informative Gene Selection and Tumor Classification by Null Space LDA for Microarray Data
Online Coupon Consumption Problem
Online Capacitated Interval Coloring
Market-Based Service Selection Framework in Grid Computing
Lower Bounds on Edge Searching
A Scheduling Problem with One Producer and the Bargaining Counterpart with Two Producers
An Approximation Algorithm for the General Mixed Packing and Covering Problem
Proceedings of the 2nd International Workshop on LEO Networking and Communication, LEO-NET 2024, Washington, DC, USA, November 18-22, 2024
×Grid: A Location-oriented Topology Design for LEO Satellites
On the Feasibility of Laser Inter-satellite Links for Low-latency High Frequency Trading
Do We Need a Million Satellites in Orbit? Constellation-as-a-Service with Modular Satellites: Challenges and Opportunities
Starlink Performance through the Edge Router Lens
Proceedings of the 1st ACM Workshop on LEO Networking and Communication, LEO-NET 2023, Madrid, Spain, 6 October 2023
A Survey on Direct-to-Device Satellite Communications: Advances, Challenges, and Prospects
An In-Depth Investigation of LEO Satellite Topology Design Parameters
Astrolabe: Modeling RTT Variability in LEO Networks
Multi-Timescale Evaluation of Starlink Throughput
Trajectory-based Serving Satellite Identification with User Terminal's Field-of-View
LEO Satellite Network Resilience Analysis: A Focus on Critical Satellites
Weathering a Solar Superstorm: Starlink Performance during the May 2024 Storm
Exploring Low-Earth Orbit Network Design
Edge Computing in Low-Earth Orbit - What Could Possibly Go Wrong?
Analyzing Source-Routed Approaches for Low Earth Orbit Satellite Constellation Networks
StarQUIC: Tuning Congestion Control Algorithms for QUIC over LEO Satellite Networks
Choosing the Right Spot: How Well Are LEO Satellite Gateways Placed? Starlink Case-Study
Stealthy Signals: Using Ghost Modulation to Watermark Interference
A First Look at Networking-Aware LEO Maneuvers
Observing the Skies - Ground-Based Cloud Detection for Evaluating the Impact of Clouds on LEO Communications
Segment Routing based on Geographic Checkpoints
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
GCStack+GCScaler: Fast and Accurate GPU Performance Analyses Using Fine-Grained Stall Cycle Accounting and Interval Analysis
Constructing Replicated Systems Using Processors with Point-to-Point Communication Links
SigRace: signature-based data race detection
Energy-efficient cache design using variable-strength error-correcting codes
EcoFaaS: Rethinking the Design of Serverless Environments for Energy Efficiency
Robust architectural support for transactional memory in the power architecture
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Architecting a Stochastic Computing Unit with Molecular Optical Devices
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
A State-of-the-Art SIMD Two-Dimensional FFT Array Processor
Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs
Alignment Network Used for Connecting a Prime Number of Memory Blocks with a Power of 2 of Processing Elements
MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata
WindServe: Efficient Phase-Disaggregated LLM Serving with Stream-based Dynamic Scheduling
The Stanford FLASH Multiprocessor
FFCCD: fence-free crash-consistent concurrent defragmentation for persistent memory
Synchronization for Fault-Tolerant Quantum Computers
Improving the Throughput of a Pipeline by Insertion of Delays
A Computer Simulation Facility for Packet Communication Architecture
Analytic Evaluation of Shared-memory Systems with ILP Processors
A Comparative Study of Distributed Resource Sharing on Multiprocessors
EOD: Enabling Low Latency GNN Inference via Near-Memory Concatenate Aggregation
Modular Architecture for High Performance Implementation of FFT Algorithm
HMO, A Hardware Microcode Optimizer
Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995
Emerald: graphics modeling for SoC systems
Design of Instruction Set Architectures for Support of High-Level Languages
Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision
Cost-effective speculative scheduling in high performance processors
Prediction Based Execution on Deep Neural Networks
TRACI: Network Acceleration of Input-Dynamic Communication for Large-Scale Deep Learning Recommendation Model
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor
Difficult-Path Branch Prediction Using Subordinate Microthreads
Hardware-aware Calibration Protocol for Quantum Computers
Avoiding Initialization Misses to the Heap
Adaptive Software Cache Management for Distributed Shared Memory Architectures
Multiple vs. Wide Shared Bus Multiprocessors
Data prefetching by dependence graph precomputation
ZeRØ: Zero-Overhead Resilient Operation Under Pointer Integrity Attacks
Folded Banks: 3D-Stacked HBM Design for Fine-Grained Random-Access Bandwidth
Redundant memory mappings for fast access to large memories
Interconnection Networks for Scalable Quantum Computers
Thread-based Programming for the EM-4 Hybrid Dataflow Machine
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France
VLSI Oriented Asynchronous Architecture
Piecewise Linear Branch Prediction
Reducing memory access latency with asymmetric DRAM bank organizations
Efficient Mapping of Algorthims To Single-Stage Interconnections
Continuous real-world inputs can open up alternative accelerator designs
The Architecure and System Method of DDM1: A Recursively Structured Data Driven Machine
Physical Register Inlining
Reactive NUCA: near-optimal block placement and replication in distributed caches
GPUWattch: enabling energy optimizations in GPGPUs
Parallel Processing as a Language Design Problem
Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration
CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities
The Peripheral Processor PP4 - A Highly Regular VLSI Processor
Buffer-on-board memory systems
Limitations of Cache Prefetching on a Bus-Based Multiprocessor
Interconnecting A Distibuted Processor System for Avionics
Mechanisms for store-wait-free multiprocessors
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
GameStreamSR: Enabling Neural-Augmented Game Streaming on Commodity Mobile Platforms
Navigating the cache hierarchy with a single lookup
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems
Plasticine: A Reconfigurable Architecture For Parallel Paterns
A Virtualization Framework for IOMMU-less Many-Core Accelerators
Using Prediction to Accelerate Coherence Protocols
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Evolution of thread-level parallelism in desktop applications
Concurrent Error Detection in VLSI Interconnection Networks
Integrated computer architecture development system
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques
Resource allocation in rectangular SW banyans
The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine (Extended Abstract)
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Exploring the Design Space for a Shared-Cache Multiprocessor
LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge
31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany
QoS provisioning in clusters: an investigation of Router and NIC design
Tolerating process variations in nanophotonic on-chip networks
The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy
Disaggregated memory for expansion and sharing in blade servers
An Emulator Network for SIMD Machine Interconnection Networks
Aurochs: An Architecture for Dataflow Threads
Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator
VLSI Based Design Principles for MIMD Multiprocessor Computers with Distributed Memory Management
ARM Virtualization: Performance and Architectural Implications
SoPHy: A Software Platform for Hybrid Resource Management of Homogeneous Many-core Accelerators
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, HASP@ISCA 2018, Los Angeles, CA, USA, June 02-02, 2018
Redundant Memory Array Architecture for Efficient Selective Protection
CoNDA: efficient cache coherence support for near-data accelerators
VEAL: Virtualized Execution Accelerator for Loops
The role of optics in future high radix switch design
Flexible Decoupled Transactional Memory Support
Architecture Advances of the Space Shuttle Orbiter Avionics Computer System
A hardware mechanism for dynamic extraction and relayout of program hot spots
Cooperative Caching for Chip Multiprocessors
Managing Multi-Configuration Hardware via Dynamic Working Set Analysis
IVEC: off-chip memory integrity protection for both security and reliability
SIMD divergence optimization through intra-warp compaction
Leveraging control-flow similarity to reduce branch predictor cold effects in microservices
Counter-light Memory Encryption
HAPPE Honeywell Associative Parallel Processing Ensemble
HALO: accelerating flow classification for scalable packet processing in NFV
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering
A synthesis framework for stitching surface code with superconducting quantum devices
MGX: near-zero overhead memory protection for data-intensive accelerators
Mechanisms for bounding vulnerabilities of processor structures
Caravan: A Hardware/Software Co-Design for Efficient SIMD Neighbor Search on Point Clouds
MBus: an ultra-low power interconnect bus for next generation nanopower systems
Position Paper: Challenges Towards Securing Hardware-assisted Execution Environments
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
PPMLAC: high performance chipset architecture for secure multi-party computation
An MLP-aware leakage-free memory controller
RAP.2 - An Associative Processor for Data Bases
Highly Concurrent Scalar Processing
i-NVMM: a secure non-volatile main memory system with incremental encryption
BlissCam: Boosting Eye Tracking Efficiency with Learned In-Sensor Sparse Sampling
RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization
Resource Allocation in Rectangular CC-Banyans
CAMJ: Enabling System-Level Energy Modeling and Architectural Exploration for In-Sensor Visual Computing
A Programmable Galois Field Processor for the Internet of Things
Guided Region Prefetching: A Cooperative Hardware/Software Approach
iSwitch: Coordinating and optimizing renewable energy powered server clusters
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, HASP@ICSA 2016, Seoul, Republic of Korea, June 18, 2016
Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches
The FLEX/32 Multicomputer
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies
Reconfigurable caches and their application to media processing
SPACE: Locality-Aware Processing in Heterogeneous Memory for Personalized Recommendations
FlexiCores: low footprint, high yield, field reprogrammable flexible microprocessors
What Computer Architects Need to Know about Memory Throttling
Single-graph multiple flows: Energy efficient design alternative for GPGPUs
Failure Sentinels: Ubiquitous Just-in-time Intermittent Computation via Low-cost Hardware Support for Voltage Monitoring
PreSto: An In-Storage Data Preprocessing System for Training Recommendation Models
Geyser: a compilation framework for quantum computing with neutral atoms
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Design of Special-Purpose VLSI Chips: Example and Opinions
NMP-PaK: Near-Memory Processing Acceleration of Scalable De Novo Genome Assembly
A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3)
PMNet: In-Network Data Persistence
A defect-tolerant accelerator for emerging high-performance applications
Retrospective: the J-machine
Hierarchical Multiprocessor Organizations
Rumba: an online quality management system for approximate computing
Locality vs. criticality
Multinomial Conjunctoid Statistical Learning Machines
Evolution of the Samsung Exynos CPU Microarchitecture
High Performance Integrated Prolog Processor IPP
Code layout optimizations for transaction processing workloads
Data reorganization in memory using 3D-stacked DRAM
FRED: A Wafer-scale Fabric for 3D Parallel DNN Training
An Empirical Evaluation of Two Memory-Efficient Directory Methods
HLS: combining statistical and symbolic simulation to guide microprocessor designs
Simultaneous Multithreading: Maximizing On-Chip Parallelism
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
Destage Algorithms for Disk Arrays with Non-Volatile Caches
Execution of Logic Programs on a Dataflow Architecture
InfiniMind: A Learning-Optimized Large-Scale Brain-Computer Interface
μManycore: A Cloud-Native CPU for Tail at Scale
SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje
Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors
Analysis and implementation of hybrid switching
The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor
Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs)
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Unified Memory Protection with Multi-granular MAC and Integrity Tree for Heterogeneous Processors
The Serial Microprocessor Array (SMA): Microprogramming and Application Examples
Efficient Interprocessor Communications for MIMD Multiprocessor Systems
A Special Purpose LSI Processor Using the DDA Algorithm for Image Transformation
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
SieveStore: a highly-selective, ensemble-level disk cache for cost-performance
When Mitigations Backfire: Timing Channel Attacks and Defense for PRAC-Based RowHammer Mitigations
With Shared Microexponents, A Little Shifting Goes a Long Way
Branch History Table Prediction of Moving Target Branches due to Subroutine Returns
Detecting Non-Control-Flow Hijacking Attacks Using Contextual Execution Information
Mocktails: Capturing the Memory Behaviour of Proprietary Mobile Architectures
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures
Retrospective: A Preliminary Architecture for a Basic Data Flow Processor
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
A Preliminary Architecture for a Basic Data Flow Processor
The SGI Origin: A ccNUMA Highly Scalable Server
An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
WCRC: An ANSI SPARC Machine Architecture for Data Base Management
A PMS Level Language for Performance Evaluation Modelling (V-PMS)
Suppressing Correlated Noise in Quantum Computers via Context-Aware Compiling
Cascading structured pruning: enabling high data reuse for sparse DNN accelerators
BTS: an accelerator for bootstrappable fully homomorphic encryption
Size, Power, and Speed
Performance Studies of a Parallel Prolog Architecture
ATiM: Autotuning Tensor Programs for Processing-in-DRAM
GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures
A Few Examples of How to Use a Symmetrical Multi-Micro-Processor
Reducing Startup Time in Co-Designed Virtual Machines
CoopRT: Accelerating BVH Traversal for Ray Tracing via Cooperative Threads
Increasing off-chip bandwidth in multi-core processors with switchable pins
Rotary router: an efficient architecture for CMP interconnection networks
Morpheus: Creating Application Objects Efficiently for Heterogeneous Computing
Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987
Directory based cache coherence verification logic in CMPs cache system
NoHype: virtualized cloud infrastructure without the virtualization
Memory Dependence Prediction Using Store Sets
HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing
RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation
Architecture implications of pads as a scarce resource
Research on Synthesis of Concurrent Computing Systems
EOLE: Paving the way for an effective implementation of value prediction
ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis
Price/Performance Comparison of C.mmp and the PDP-10
Building Blocks for Data Flow Prototypes
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
Implementing Streams on a Data Flow Computer System With Paged Memory
Parallel Garbage Collection Without Synchronization Overhead
Lelantus: Fine-Granularity Copy-On-Write Operations for Secure Non-Volatile Memories
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
Nested Enclave: Supporting Fine-grained Hierarchical Isolation with SGX
Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures
Side-channel vulnerability factor: A metric for measuring information leakage
Flagger: Cooperative Acceleration for Large-Scale Cross-Silo Federated Learning Aggregation
Security and Protection of Data in the IBM System/38
Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races
TCP: A Tensor Contraction Processor for AI Workloads Industrial Product
SpecEE: Accelerating Large Language Model Inference with Speculative Early Exiting
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking
Efficient Synchronization: Let Them Eat QOLB
Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency
Switched Multiple Instruction, Multiple Data Stream Processing
Performance evaluation of disk subsystems
Optimized Mesh-Connected Networks for SIMD and MIMD Architectures
Profiling Hyperscale Big Data Processing
Secure TLBs
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing
Independent Forward Progress of Work-groups
EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks
A fully associative software-managed cache design
An Instruction Class for an Extensible Interpreter
Multiscalar Processors
Magellan: A High-Performance Loop-Guided Prefetcher for Indirect Memory Access
Data marshaling for multi-core architectures
IOMMU: Strategies for Mitigating the IOTLB Bottleneck
Light-weight Cache Replacement for Instruction Heavy Workloads
Comparison of Hardware and Software Cache Coherence Schemes
LogCA: A High-Level Performance Model for Hardware Accelerators
Communication Algorithm-Architecture Co-Design for Distributed Deep Learning