yusuke1997/dblp-id-title huggingface dataset:
An implementation of memory-based on-chip analogue test signal generation
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Multilevel full-chip gridless routing considering optical proximity correction
Performance driven multiple-source bus synthesis using buffer insertion
Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair
Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology
Utilizing high level design information to speed up post-silicon debugging
A global interconnect reduction technique during high level synthesis
ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise
Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling
Post silicon skew tuning: Survey and analysis
A wideband hierarchical circuit reduction for massively coupled interconnects
Application of ESL synthesis on GSM edge algorithm for base station
Symmetrical buffered clock-tree synthesis with supply-voltage alignment
Statistical gate delay model for Multiple Input Switching
7.3 Gb/s universal BCH encoder and decoder for SSD controllers
LightCL: Compact Continual Learning with Low Memory Footprint For Edge Device
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise
Netlist reverse engineering for high-level functionality reconstruction
Automatic assertion extraction via sequential data mining of simulation traces
SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity
YoseUe: "trimming" Random Forest's training towards resource-constrained inference
Efficient loop-back testing of on-chip ADCs and DACs
Design automation for integrated continuous-time filters using integrators
ReRAM-based processing-in-memory architecture for blockchain platforms
Power analysis of a 32-bit embedded microcontroller
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers
Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework
A multi-level transmission line network approach for multi-giga hertz clock distribution
Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders
Reuse and protection of intellectual property in the SpecC system
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems
Fast Analytic Placement using Minimum Cost Flow
Dynamic power management in environmentally powered systems
Adaptive models for input data compaction for power simulators
Heterogeneous BISR-approach using System Level Synthesis Flexibility
An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits
Collaborative Coalescing of Redundant Memory Access for GPU System
A perturbation-aware noise convergence methodology for high frequency microprocessors
A datapath synthesis system for the reconfigurable datapath architecture
Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL
Novel task migration framework on configurable heterogeneous MPSoC platforms
A 1.2GHz delayed clock generator for high-speed microprocessors
Hierarchical dummy fill for process uniformity
IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network
PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage : (Invited Paper)
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling
Event-driven observability enhanced coverage analysis of C programs for functional validation
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
On test syndrome merging for reasoning-based board-level functional fault diagnosis
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels
Architectural simulation for a programmable DSP chip set
Approximation-aware testing for approximate circuits
RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power
Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback
Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams
Automatic constraint generation for guided random simulation
Flexible interconnect in 2.5D ICs to minimize the interposer's metal layers
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization
A fast counterexample minimization approach with refutation analysis and incremental SAT
Current consumption model for more efficient side-channel tolerant design at FPGA design stage
Reducing cache engery through dual voltage supply
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code
Software Licensing Models in the EDA Industry
An arbitrary chaos generator core curcuit using PWM/PPM signals
TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks
Statistical power profile correlation for realistic thermal estimation
Single cycle access cache for the misaligned data and instruction prefetch
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme
Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints
A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation
Automated Detection of Spatial Memory Safety Violations for Constrained Devices
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS
TCG-based multi-bend bus driven floorplanning
Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial)
SPADs for quantum random number generators and beyond
Interconnect design methods for memory design
GECOM: Test data compression combined with all unknown response masking
FastRoute 4.0: global router with efficient via minimization
Multi-level timing simulation on GPUs
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
Algorithm for synthesizing design context-aware fast carry-skip adders
DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators
T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fusion
Low-cost hardware architectures for mersenne modulo functional units
A scheduling algorithm for synthesis of bus-partitioned architectures
Scheduling with integer time budgeting for low-power optimization
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks
Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification
SoC HW/SW verification and validation
Polynomial time optimal algorithm for stencil row planning in e-beam lithography
PowerV i P: Soc power estimation framework at transaction level
The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearity
LiteIndex: Memory-Efficient Schema-Agnostic Indexing for JSON documents in SQLite
Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture
High-Level Synthesis of Transactional Memory
Power recduction by gate sizing with path-oriented slack calculation
An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems
Fast large-scale optimal power flow analysis for smart grid through network reduction
A retention-aware test power model for embedded SRAM
An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing
A technique for QoS-based system partitioning
Synthesis of single-output space compactors with application to scan-based IP cores
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation
Accounting for non-linear dependence using function driven component analysis
A low power asynchronous Java processor for contactless smart card
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting
Hybrid analysis of SystemC models for fast and accurate parallel simulation
Automatic timing-coherent transactor generation for mixed-level simulations
Simultaneous data and power transmission using nested clover coils
Algorithm accelerations for luminescent solar concentrator-enhanced reconfigurable onboard photovoltaic system
ARM MPCore; The streamlined and scalable ARM11 processor core
VFCC: A verification framework of cache coherence using parallel simulation
FPGA-based accelerator for long short-term memory recurrent neural networks
MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator
Training itself: Mixed-signal training acceleration for memristor-based neural network
CN-SIM: A cycle-accurate full system power delivery noise simulator
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications
A system-level approach to hardware reconfigurable systems
Checkered white-RGB color LOFIC CMOS image sensor
IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems
An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits
Maximizing return on investment of a grid-connected hybrid electrical energy storage system
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
A low-power wide dynamic-range current readout circuit for biosensors
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages
Noise-aware buffer planning for interconnect-driven floorplanning
Substrate resistance extraction with direct boundary element method
IR to routing challenge and solution for interposer-based design
Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips
Floating-point reconfiguration array processor for 3D graphics physics engine
Statistical design of macro-models for RT-level power evaluation
Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper)
Enabling Scalable AI Computational Lithography with Physics-Inspired Models
A new performance driven placement method with the Elmore delay model for row based VLSIs
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology
FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design
A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower
MUTARCH: Architectural diversity for FPGA device and IP security
Equivalence checking of scheduling with speculative code transformations in high-level synthesis
A local reconfiguration based scalable fault tolerant many-processor array
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application
On compliance test of on-chip bus for SOC
A low-power high-speed accuracy-controllable approximate multiplier design
Towards Finding the Sources of Polymorphism in Polymorphic Gates (Invited)
SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design
A performance enhanced dual-switch Network-on-Chip architecture
PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection
APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning
Improved DD-based Equivalence Checking of Quantum Circuits
A tool for measuring quality of test pattern for LSIs' functional design
Boosting the Profitability of NVRAM-based Storage Devices via the Concept of Dual-Chunking Data Deduplication
On-chip power network optimization with decoupling capacitors and controlled-ESRs
TLM automation for multi-core design
A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing
A high performance low complexity joint transceiver for closed-loop MIMO applications
Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors
Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics
An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system
Exploiting accelerated aging effect for on-line configurability and hardware tracking
Self-aligned double patterning layout decomposition with complementary e-beam lithography
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method
Determination of optimal polynomial regression function to decompose on-die systematic and random variations
A new encoding scheme for rectangle packing problem
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL
An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio
Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks
Memory access aware power gating for MPSoCs
Electromigration-aware redundant via insertion
Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009
An accurate ACOSSO metamodeling technique for processor architecture design space exploration
Voltage island-driven floorplanning considering level shifter placement
A cell synthesis method for salicide process
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber
A heuristic for multi objective software application mappings on heterogeneous MPSoCs
LithoROC: lithography hotspot detection with explicit ROC optimization
Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network
Generalised threshold gate synthesis based on AND/OR/NOT representation of Boolean function
Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk
SEA: fast power estimation for micro-architectures
Object duplication for improving reliability
A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS
High-density integration of functional modules using monolithic 3D-IC technology
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques
Fast multi-domain clock skew scheduling for peak current reduction
A closed caption TV microcontroller
Full-custom vs. standard-cell design flow: an adder case study
An efficient compression scheme for checkpointing of FPGA-based digital mockups
A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy
An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000
V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting
FTT-NAS: Discovering Fault-Tolerant Neural Architecture
Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process
Generating circuit current constraints to guarantee power grid safety
A formal approach to debug polynomial datapath designs
An on-line approach for power minimization in QoS sensitive systems
Balancing resiliency and energy efficiency of functional units in ultra-low power systems
A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array
Towards limiting the impact of timing anomalies in complex real-time processors
A new test and characterization scheme for 10+ GHz low jitter wide band PLL
Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation
Synthesis of false loop free circuits
Simulation of Ideally Switched Circuits in SystemC
An Efficient General-Purpose Optical Accelerator for Neural Networks
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)
Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges
A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration
Automatic partitioning for efficient combinatorial verification
Lithography Hotspot Detection via Heterogeneous Federated Learning with Local Adaptation
A BDD-based fast heuristic algorithm for disjoint decomposition
A flexible hybrid simulation platform targeting multiple configurable processors SoC
Piecewise quadratic waveform matching with successive chord iteration
Efficient synthesis of compressor trees on FPGAs
A retargetable and accurate methodology for logic-IP-internal electromigration assessment
On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors
Defects Mitigation in Resistive Crossbars for Analog Vector Matrix Multiplication
A high efficient hardware architecture for multiview 3DTV
An integrated approach to timing-driven synthesis and placement of arithmetic circuits
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V
On applying erroneous clock gating conditions to further cut down power
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
Open architecture test system: not why but when!
Machine learning for engineering
A wireless real-time on-chip bus trace system
Performance driven multiway partitioning
Analytical placement of mixed-size circuits for better detailed-routability
Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN Implementation
A topology-based ECO routing methodology for mask cost minimization
Invited Paper: Boosting Standard Cell Library Characterization with Machine Learning
From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETs
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Fast Boolean Matching Under Permutation Using Representative
FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers
Design and chip implementation of a heterogeneous multi-core DSP
An On-Chip Automatic Tuning Circuit using Integration Level Approximation
E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean Algorithms
XORiM: A case of in-memory bit-comparator implementation and its performance implications
Design Consideration of 6.25 Gbps Signaling for High-Performance Server
On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping
AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off
Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs
Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption
Equivalence checking of integer multipliers
SYNTHNET: A High-throughput yet Energy-efficient Combinational Logic Neural Network
An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction
In-Memory Computing Accelerators for Emerging Learning Paradigms
Optimization of Reversible Logic Networks with Gate Sharing
EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting Devices
Automated debugging of counterexamples in formal verification of pipelined microprocessors
Temporal floorplanning using 3D-subTCG
A comparative investigation of approximate attacks on logic encryptions
Low area pipelined circuits by multi-clock cycle paths and clock scheduling
Systematic Scan Reconfiguration
Using red-black interval trees in device-level analog placement with symmetry constraints
An optimal algorithm for sizing sequential circuits for industrial library based designs
Mutation-based Compliance Testing for RISC-V
Design for manufacturability and reliability for TSV-based 3D ICs
WUCC: Joint WCET and Update Conscious Compilation for cyber-physical systems
High level event driven thermal estimation for thermal aware task allocation and scheduling
Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSA
A multiple level network approach for clock skew minimization with process variations
Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation
Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning Microprocessor
A read-write aware DRAM scheduling for power reduction in multi-core systems
Reinforcing the Connection between Analog Design and EDA (Invited Paper)
Design of self-timed asynchronous Booth's multiplier
Obstacle-avoiding wind turbine placement for power-loss and wake-effect optimization
The Y-architecture: yet another on-chip interconnect solution
Methodology for hardware/software co-verification in C/C++ (short paper)
Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read
Watermarking Layout Topologies
AQUILA: An equivalence verifier for large sequential circuits
Leakage conscious DVS scheduling for peak temperature minimization
An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines
CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits
EMC-adequate design of printed circuit boards as a part of the system development
Non-scan design for testable data paths using thru operation
3DCoB: A new design approach for Monolithic 3D Integrated circuits
A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators
A racetrack memory based in-memory booth multiplier for cryptography application
Manycore processor for video mining applications
Transduction Method for AIG Minimization
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM
Execution of provably secure assays on MEDA biochips to thwart attacks
Slicing floorplan with clustering constraints
Equivalent lumped element models for various n-port Through Silicon Vias networks
Fast and accurate performance simulation of embedded software for MPSoC
Hardware-dependent software synthesis for many-core embedded systems
Analytical model for the impact of multiple input switching noise on timing
Challenges to covering the high-level to silicon gap
Partial Scan Design Methods Based on Internally Balanced Structure
CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs
An Inductively Coupled Wireless Bus for Chiplet-Based Systems
Statistical time borrowing for pulsed-latch circuit designs
A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder