yusuke1997/dblp-id-title huggingface dataset:
Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems
Enlarging neural class detection capacity in passive sonar systems
Secure the image-based simulated telesurgery system
Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation
Memristor-based 4: 2 compressor cells design
On Compare-and-Swap Optimization for Fully Homomorphic Encrypted Data
Controlling chaos via second-order sliding modes
Event-Driven Local Gain Control on a Spiking Cochlea Sensor
Design of A 128 × 128 CMOS APS with extended noise suppression for high and low light imaging applications
Sonar echo-location in 2-D using mini-microphone array and spatiotemporal frequency filtering
Efficient analog verification against Trojan states using divide and contraction method
Class AB technique for high performance switched-current memory cells
A low-power CMOS front end for particle detection applications
A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth
AI-enabled RF-to-THz IC Design Space Discovery and Inverse Design Flow
Optimization of sequential verification by history-based dynamic minimization of BDDs
A 1-1 MASH 2-D vernier time-to-digital converter with 2 nd -order noise shaping
In pixel VCO-based 5V 58.5μW Capacitance Sensing for Large Area Electrowetting Arrays
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation
Performance estimators for hardware/software co-design
A high gain strategy with positive-feedback gain enhancement technique
ReRAM-based synaptic device for neuromorphic computing
Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters
A 50 Hz SC notch filter for IoT applications
An FPGA-based Real-Time Optical Flow Accelerator for Recurrent All-Pairs Field Transforms
Analog representation and digital implementation of OFDM systems
A New Approach to Bolometric Tomography in Tokamaks
Ultra-low-power, high-density spintronic programmable logic (SPL)
A Low-Power, Single-Chip Electronic Skin Interface for Prosthetic Applications
A Circuit-Generator-Aided Design Methodology for GHz Pipelined SAR ADCs
A successive reoptimization approach for the design of discrete coefficient perfect reconstruction lattice filter bank
Challenges in High Current On-Chip Voltage Stacked Systems
An efficient homotopy method for finding DC operating points of nonlinear circuits
Faster adaptive parallel diagnosis in the presence of intermittent faults (extended abstract)
Structured log-domain synthesis of nonlinear systems
A 50-100 MHz 5 V to -5 V, 1 W Cuk converter using gallium arsenide power switches
On designing FIR filters using windows based on Gegenbauer polynomials
A Robust Variable Forgetting Factor QS-decomposition Algorithm for Subspace Tracking
A control scheme for eliminating garbage collection during highspeed analysis of big-graph data stored in NAND flash memory
Three Dimensional Integer Rotation Transform and Improvement of its Compatibility
Axial Attention Transformer for Fast High-quality Image Style Transfer
Error-energy analysis of hardware logarithmic approximation methods for low power applications
Voltage reference using mutual compensation of mobility and threshold voltage temperature effects
Low-overhead error-resilient bit-plane image coding
A Low Power, High Count Rate Radiation Detection Chip Using A Current Subtraction Technique
Combined image signal processing for CMOS image sensors
Practical solutions for the application of the oscillation-based-test in analog integrated circuits
A Low Power Digital Baseband for Wireless Endoscope Capsule
Printing Sensor on Flexible Substrates for Detection of Volatile Organic Compounds
Noise modeling of Stokes parameters in division of focal plane polarization imagers
Multi-carrier LINC amplifier calibration by min-minimum criterion
K infinity Generalized Functions
A 71-86 GHz Cascaded Harmonic Enhanced Tripler with -69 dBc Fundamental and -66 dBc Second Harmonic Suppression
Passive closed-form expression of RLCG transmission lines
FIR filter with variable fractional delay and phase shift: Efficient realization and design using reweighted l1-norm minimization
Behavioral analysis and dimensioning of UMTS transmitters baseband blocks
A new memory-based FFT processor for VDSL transceivers
Synchronization in Heterogeneous Networks Coupled of LC Oscillators Via Sampled-Data Control
Submission for CAS Transactions Papers: Design Methodology Based on the Inversion Coefficient and its Application to Inductorless LNA Implementations
Address-Event Video Streaming over Wireless Sensor Networks
VLSI architecture for 4×4 16-QAM V-BLAST decoder
Enhancing the performance of output-capacitorless LDO regulators by pass-transistor segmentation
Power Transfer System Combining Wireless Resonators and Wired Three-Coil Repeater
Matching pursuit: Evaluation and implementatio for LTE channel estimation
Configuration self-test in FPGA-based reconfigurable systems
Accelerating Machine Learning with RISC-V Vector Extension and Auto-Vectorization Techniques
A dual-rail static edge-triggered latch
Method for equalizer design based on time-domain symmetry
Spoken Letter Recognition using Deep Convolutional Neural Networks on Sparse and Dissimilar Data
A Minimal Memory Game-Based Distributed Algorithm to Vertex Cover of Networks
A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV
Impulsive noise estimation and cancellation in DSL using compressive sampling
A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR
A Frequency-domain Features Based Clustering Algorithm for Blood Pressure Estimation with Photoplethysmogram Signal
A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter
An improved rate control algorithm for H.264
The chaotic numbers of the bipartite and tripartite graphs
A methodology for constructing two-transistor multistable circuits
Noise-Induced Simultaneous Firing in Uncoupled Leaky Integrate-And-Fire Circuits
A novel 3D model recognition approach using Pitman-Yor process mixtures of Beta-Liouville Distributions
A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage
Global motion estimation from coarsely sampled motion vector field and the applications
Towards Automated Power Gating of Registers using CoDeL
Medical data mining model for oriental medicine via BYY Binary Independent Factor Analysis
Quality control of real-time panoramic views from the smart camera 360SCAN
Robust video segmentation employing variable bandwidth object boundary
KARS: Kernel-Grouping Aided Row-Skipping for SDK-based Weight Compression in PIM Arrays
Necessary and sufficient conditions for LTI systems to preserve signal richness
Stability of interacting grid-connected power converters
CMOS limiting optical preamplifiers using dynamic biasing for wide dynamic range
A general model for differential power analysis attacks to static logic circuits
An unscented-transform-based filtering algorithm for noisy contaminated chaotic signals
Intrinsic Lateral Inhibition Facilitates Winner-Take-All in Domain Wall Racetrack Arrays for Neuromorphic Computing
Improving rate and quality in MPEG 2 sequences using global motion information
Error correction algorithm for high accuracy bio-impedance measurement in wearable healthcare applications
An observer point of view on synchronization of discrete-time systems
On the global robust stability of delayed neural networks
Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic
Software and Hardware Design for Coding Depth Map Sequence with Texture Motion Information
Concept of spectrum-signal transformation
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process
Set-membership affine projection algorithm for echo cancellation
Top-down analog design methodology using Matlab and Simulink
A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers
Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications]
An intelligent framework for designing analog circuits based on hybrid reasoning
C-based design of a real time speech recognition system
Efficient Inter Mode Decision for H.263 to H.264 Video Transcoding using Support Vector Machines
Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension
Low-distortion Continuous-time R-MOSFET-C Filters
A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS
A 28GHz, Asymmetrical, Modified Doherty Power Amplifier, in 22nm FDSOI CMOS
Emergence of Chimera States with Re-Programmable Memristor Crossbar Arrays
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis
A triple 8b, 80MSPS 3.3 V graphics digitizer
Modeling the Substrate Noise Injected by a DC-DC Converter
Content-based adaptive media player for networked video
An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations
Storing and Retrieving Wavefronts with Resistive Temporal Memory
A polynomial-time algorithm for designing digital filters with power-of-two coefficients
New efficient residue-to-binary converters for 4-moduli set {2 n - 1, 2 n , 2 n + 1, 2 n+1 - 1}
Conversion Error in D/A Converters Employing Dynamic Element Matching
Dynamic oversampling ratio sigma-delta modulation for the control of switching power converter
Detecting multi-mode MIMO signals: Algorithm and architecture design
Almost Distortion-Free IIR Subband Filters using a Nested Structure
A 12V-to-1~1.8V Tri-Path Series-Capacitor Converter with Reduced Inductor Current and Full-Range Duty Cycle for Point-of-Loads Application
A novel ultra high-speed flip-flop-based frequency divider
An Adaptive Event-based Data Converter for Always-on Biomedical Applications at the Edge
On-chip jitter tolerance measurement technique for CDR circuits
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor
Approximate BDD Minimization by Weighted A
AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks
Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation
A current-mode CMOS loser-take-all with minimum function for neural computations
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
Infrastructural health monitoring using self-powered Internet-of-Things
Towards a comprehensive and systematic classification of hardware Trojans
A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise
On reducing leakage quantization noise of multistage Sigma-Delta modulator using nonlinear oscillation
Polynomial order algorithms for structural and behavioral analysis of state machine allocatable nets
Design of Low-Cost Approximate CMOS Full Adders
Teaching circuits to new generations of engineers
A high-output-impedance current microstimulator for anatomical rewiring of cortical circuitry
Understanding Wilson current mirror via the negative feedback approach
A Low Power Reconfigurable Heterogeneous Architecture for a Mobile SDR System
A 13.6-17.7 GHz Sub-Harmonic Injection-Locked SSPLL with 74-fs RMS Jitter
Video decoder embedded with temporal LMMSE denoising filter
Beamforming MIMO Receiver with Reduced Hardware Complexity
Analysis of Parasitic Effects on Capacitor-Loaded Broadside-Coupled Split-Ring Resonator RF Filters
A rakeness-based design flow for Analog-to-Information conversion by Compressive Sensing
Scheduling problems for a class of parallel distributed systems
Outdoor Check Stop HAZMAT Placard Detection Using Synthetic Images and YOLOv5-Small
MispredTable: A Side Branch Predictor to TAGE in Multithreading Processors
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer
SuperHCA: A Super-Resolution Accelerator with Sparsity-Aware Heterogeneous Core Architecture
Substrate noise-aware floorplanning for mixed-signal SOCs
A pMOS-based double-ladder integrated charge pump for standard process
An Integrated Modelling Technique for Hardware/Software Systems
A full-range all-pass variable phase shifter for multiple antenna receivers
Multidimensional RD-CNNs: a circuit realization
Time to Digital Converter Based on a Ring Oscillator with Even Number of Non-Inverting Elements
A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI
A Lyapunov function for large scale power systems
Performance analysis of lattice-reduction algorithms for a novel LR-compatible K-Best MIMO detector
High-precision DAC based on a self-calibrated sub-binary radix converter
Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation
Local Approximation of Stability Boundary of a Power System Using the Real Normal Form of Vector Fields
Influence of external input on Oscillatory Cellular Nonlinear Networks dynamics
The time machine: A novel spike-based computation architecture
Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor
Automated test development and test time reduction for RF subsystems
Transient analysis of a CMOS inverter driving resistive interconnect
An energy-efficient ternary interconnection link for asynchronous systems
An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer
Bit-rate transparent electronic data regeneration in repeaters for high speed lightwave communication systems
A custom signal processor based neuroprosthesis intended to recover urinary bladder functions
A 1.8/2.5/3.3V BiCMOS I/O driver with VCC=5V
Theory and applications of complex networks: Advances and challenges
Dynamic threshold based rate adaptation for HTTP live streaming
Reduced Domain Multiplication for Deep Neural Network Acceleration
Design of discrete Fractional Hilbert transformer in time domain
Design and Analysis of Split-Inductor Based Buck-Boost Converters
Analysis of the role played by error correcting coding in robust watermarking
A 0.084% Nonlinearity Open-Loop Capacitive Micro-Accelerometer with On-Chip Digital Nonlinearity Calibration and Embedded EEPROM
An Adaptive Front-end Readout System for Radiation Detection
An interface for the I 2 C protocol in the WaferBoard™
PCI-AER interface for neuro-inspired spiking systems
Bifurcation analysis of delayed bidirectional associative memory neural networks
Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement
A pixel-parallel anisotropic diffusion algorithm for subjective contour generation
An Innovative PUF-based Mutual Authentication Key Exchange Protocol with Biometric Identification
A Low-power Sensorless Inverter Controller of Brushless DC Motors
Low power compact design of ARIA block cipher
A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving
High-bandwidth floating gate CMOS rectifiers with reduced voltage drop
Probabilistic particle modeling of quantum wave propagation with excitation and refraction
Real-Time Speech Recognition for IoT Purpose using a Delta Recurrent Neural Network Accelerator
A semi-custom memory design for an asynchronous 8051 microcontroller
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks
Sound Classification using Summary Statistics and N-Path Filtering
Universal nonlinear phenomena in a class of electronic oscillators
On the synthesis of piecewise affine control laws
An analytical model of multi-sine AC-DC voltage multiplier
A new insertion loss technique for the exact design of elliptic LDI ladder digital filters
Low-complexity general FIR filters based on Winograd's inner product algorithm
Multirate cascaded continuous time Sigma-Delta modulators
A 6.57 mW ZigBee transceiver for 868/915 MHz band
Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO
MASH Sigma-delta Modulators with Reduced Sensitivity to the Circuit Non-idealities
An Indirect Time-of-Flight Sensor with Adaptive Multiple Sampling for High Depth Precision
SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing
Coded modulations based on controlled 1-D and 2-D piecewise linear chaotic maps
Architecture for CORDIC algorithm realization without ROM lookup tables
Hardware-based anti-counterfeiting techniques for safeguarding supply chain integrity
Discrete-time phase-locked loop as a source of random sequences with different distributions
Enhancing robustness of information hiding against interference of communication with turbo code
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model
A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee Standard
An approach to statistical analysis of coarsely time-Markov systems
A quadrature oscillator using simplified phase and amplitude calibration
Transmultiplexers as precoders in modern digital communication: a tutorial review
Live Demonstration: A Single LED PPG-Based Noninvasive Glucose Monitoring Prototype System
Information retrieval from large data sets via multiple-winners-take-all
A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system
Low-power UWB transmitter using a combined mixer and power amplifier
Stable and secure delay-based physical unclonable functions using device aging
High performance clock routing in X-architecture
CMOS Technology and Current-feedback Op-Amps
Low-Power Multiplier Design Using Delayed Evaluation
Improving Deep Features for Image Retrieval Using Multi-Source Spatial Information
Hardware Acceleration of Phase and Gain Control for Analog Beamforming
A current-limiter-based soft-start scheme for linear and low-dropout voltage regulators
A shifted permuted difference coefficient method
Analysis of Crop Dynamics through Close-Range UAS Photogrammetry
A Threshold Voltage Generator Circuit with Automatic Refresh and Dynamic Updating for Ultra-Low-Power Continuous-Time Comparators
A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode
A BJT-based SAR Temperature Sensor with a $5.12\ \text{pJ}\cdot \mathrm{K}^{2}$ Resolution FoM from -40 °C to 125 °C
Spread-spectrum Markovian-code acquisition in asynchronous DS/CDMA systems
Design of an optimized reversible bidirectional barrel shifter
Foundational-circuit-based spice simulation
A low-power low-voltage NMOS bulk-mixer with 20 GHz bandwidth in 90 nm CMOS
Channel estimation for wireless communications using space-time block coding techniques
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset
Eddy-current power loss in laminated iron cores
Hardware Obfuscation of AES through Finite Field Construction Variation
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer
A 450kHz PVT-resilient all-digital BPSK demodulator for energy harvesting sensor nodes
A new ML-based data-aided feedforward symbol synchronizer for burst-mode transmission
Low-power spatial computing using dynamic threshold devices
A Physical Charge-Based Model for the Space Charge Region of Abrupt and Linear Semiconductor Junctions
Dual-loop control of laser drivers for 3.125GHz optical transceivers
Subspace-based estimation method of uplink FIR channel in MC-CDMA system without cyclic prefix over frequency-selective fading channel
Measurement of open-loop small-signal control-to-output transfer function of a PWM boost converter operated in DCM
Adaptive Digital Correction for Dual Quantization Sigma-Delta Modulators
Fast human-animal detection from highly cluttered camera-trap images using joint background modeling and deep learning classification
Error sensitivity testing for the MC-EZBC scalable wavelet video coder
An efficient inverse multiplier/divider architecture for cryptography systems
Monitoring Myocardial Edema Tissue with Electrical Impedance Spectroscopy
PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design
Bifurcation and basin in two coupled parametrically forced logistic maps
Accelerate Neural Image Compression with Channel-Adaptive Arithmetic Coding
Characterisation and Data-driven Modelling of Memimpedance
Cost-effective and low-power memory address bus encodings
Co-evolutionary reliability-oriented high-level synthesis
Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time Convolution
SPIKA: 200-TOPS/W RRAM-based Neural Network Accelerator Chip
A low-power, low-noise CMOS amplifier for neural recording applications
Radar-based georeferencing system for estimation of changing river-shores
An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS
Chaotifing a continuous-time system by time-delay feedback
Space-time codes for high bit rate wireless communications: asymptotic performance of space-time random codes
On the Estimation of Bulk Delay & Length of Dispersive Region in Echo Cancellation
Zero Reversion Loss, High-Efficiency Charge Pump for Wide Output Current Load Range
Biosensor systems and applications in genomics, proteomics and metabolomics: A review
A new block exact affine projection algorithm [acoustic echo cancellation system example]
An integrated current flattening module for embedded cryptosystems
A 3D Descriptor based on Local Height Image
A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching
Multi-user encoding for forward error correction in passive optical networks
Filterbank-based blind signal separation with estimated sound direction
An approach for physical topology exploration in wired bus networks
A 14-bit 6GS/s DAC Achieving >65dBc SFDR with Bilateral Output Impedance Compensation in 22nm CMOS
Cascade-LogoNet: Eliminating Classification Ambiguity with Cascaded Logo Detection
Improved TDOA disambiguation techniques for sound source localization in reverberant environments
A low-cost scalable Voltage-Frequency Adjustor for implementing low-power systems
Accurate Weight Mapping in a Multi-Memristive Synaptic Unit
Inverter Chain Buffer Optimization for N-path Filter Switch Drivers and Validation through Simulations in 22nm FD-SOI Technology
Rate Control with Resolution Changes for VVC
New classes of frequency-response masking FIR filters
Event-based 64-channel binaural silicon cochlea with Q enhancement mechanisms
Protocol-level performance analysis for anti-collision protocols in RFID systems
Robust speaker verification with a two classifier format and feature enhancement
Micro-watt inductorless gm-boost LNA for biomedical implants
A reconfigurable OFDM inner receiver implemented in the CAL dataflow language
All digital FPGA-implementable time-average-frequency direct period synthesis for IoT applications
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology
Novel Methods for EEG Visualization and Visualization
Low-energy and low-latency error-correction for phase change memory
Hardware-friendly Integer Motion Estimation With Weighted Search For AVS3
An MPSoC-based on-line Edge Infrastructure for Embedded Neuromorphic Robotic Controllers
Triplet spike time dependent plasticity in a floating-gate synapse
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation
A Scalable Fully Synthesized Phase-to-Digital Converter for Phase and Duty-Cycle Measurement of High-Speed Clocks
A Comparative Study of Compensation Techniques in Directional DCT's
Pseudo-voltage domain implementation of a 2-dimensional silicon cochlea
A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers