yusuke1997/dblp-id-title huggingface dataset:
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
Simple virtual channel allocation for high throughput and high frequency on-chip routers
Design, integration and implementation of the DySER hardware accelerator into OpenSPARC
AstriFlash A Flash-Based System for Online Services
Static Bubble: A Framework for Deadlock-Free Irregular On-chip Topologies
Supporting Highly-Speculative Execution via Adaptive Branch Trees
ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance
To Cross, or Not to Cross Pages for Prefetching?
A Pulse Generation Framework with Augmented Program-aware Basis Gates and Criticality Analysis
Data Enclave: A Data-Centric Trusted Execution Environment
PEEP: Exploiting predictability of memory dependences in SMT processors
Front-End Policies for Improved Issue Efficiency in SMT Processors
Parabix: Boosting the efficiency of text processing on commodity processors
Duet: Creating Harmony between Processors and Embedded FPGAs
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons
Reducing Load Latency with Cache Level Prediction
Revisiting virtual L1 caches: A practical design using dynamic synonym remapping
Prosper: Program Stack Persistence in Hybrid Memory Systems
Multi-Granularity Shadow Paging with NVM Write Optimization for Crash-Consistent Memory-Mapped I/O
Improving Disk Throughput in Data-Intensive Servers
Storage free confidence estimation for the TAGE branch predictor
Minimal disturbance placement and promotion
High-Bandwidth Low-Latency Approximate Interconnection Networks
Node-Type-Based Load-Balancing Routing for Parallel Generalized Fat-Trees
Communication Lower Bound in Convolution Accelerators
Scheduling Communication on a SMP Node Parallel Machine
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
Reviving In-Storage Hardware Compression on ZNS SSDs through Host-SSD Collaboration
Fault-Tolerance with Multimodule Routers
A Deep Reinforcement Learning Framework for Architectural Exploration: A Routerless NoC Case Study
Opportunities beyond single-core microprocessors
An intelligent IT infrastructure for the future
Experiences with ML-Driven Design: A NoC Case Study
ESESC: A fast multicore simulator using Time-Based Sampling
ACCESS: Smart scheduling for asymmetric cache CMPs
MISE: Providing performance predictability and improving fairness in shared main memory systems
Adaptable Register File Organization for Vector Processors
VQ-LLM: High-performance Code Generation for Vector Quantization Augmented LLM Inference
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
FastTrackNoC: A NoC with FastTrack Router Datapaths
Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability
Secure Dynamic Memory Scheduling Against Timing Channel Attacks
Temporal Exposure Reduction Protection for Persistent Memory
Atomic persistence for SCM with a non-intrusive backend controller
HyGCN: A GCN Accelerator with Hybrid Architecture
A Systematic Study of DDR4 DRAM Faults in the Field
Reducing GPU offload latency via fine-grained CPU-GPU synchronization
Variation-aware dynamic voltage/frequency scaling
Architectural support for synchronization-free deterministic parallel programming
Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators
The Software Industry: Ten Lessons for Long Life
Gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures
Serializing instructions in system-intensive workloads: Amdahl's Law strikes again
Automatic Microprocessor Performance Bug Detection
Partial Row Activation for Low-Power DRAM System
Know Your Enemy To Save Cloud Energy: Energy-Performance Characterization of Machine Learning Serving
M-ANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory Architecture for Accelerating Linear Programming Problems
A Statistically Rigorous Approach for Improving Simulation Methodology
Supporting highly-decoupled thread-level redundancy for parallel programs
Design and implementation of the blue gene/P snoop filter
NVMePass: A Lightweight, High-performance and Scalable NVMe Virtualization Architecture with I/O Queues Passthrough
HARD: Hardware-Assisted Lockset-based Race Detection
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
Knapp: A Packet Processing Framework for Manycore Accelerators
Multi-Range Supported Oblivious RAM for Efficient Block Data Retrieval
Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety
Tensor Casting: Co-Designing Algorithm-Architecture for Personalized Recommendation Training
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Shuffle-Ring: Overcoming the Increasing Degree of Hypercube
Enhancing Collective Communication in MCM Accelerators for Deep Learning Training
Processor Aware Anticipatory Prefetching in Loops
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory
BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
PAISE: PIM-Accelerated Inference Scheduling Engine for Transformer-based LLM
Reliability-Aware Runahead
Statistical performance comparisons of computers
High-speed formal verification of heterogeneous coherence hierarchies
Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup
Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level
SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
Unbounded Transactional Memory
Tiered-latency DRAM: A low latency and low cost DRAM architecture
Talus: A simple way to remove cliffs in cache performance
Power-Efficient DRAM Speculation
Exascale computing: The challenges and opportunities in the next decade
Cooper: Task Colocation with Cooperative Games
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors
TB-STC: Transposable Block-wise N: M Structured Sparse Tensor Core
3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, HiPINEB@HPCA 2017, Austin, TX, USA, February 5, 2017
Fine-Grain Software Distributed Shared Memory on SMP Clusters
Architecting for power management: The IBM POWER7 TM approach
BulletProof: a defect-tolerant CMP switch architecture
A Unified Compressed Memory Hierarchy
Automatically Mapping Code on an Intelligent Memory Architecture
Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation
WEST: Cloning data cache behavior using Stochastic Traces
Pacman: Tolerating asymmetric data races with unintrusive hardware
Differential-Matching Prefetcher for Indirect Memory Access
Octopus-Man: QoS-driven task management for heterogeneous multicores in warehouse-scale computers
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
Hardware/software-based diagnosis of load-store queues using expandable activity logs
Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems
Reliability-Aware Scheduling on Heterogeneous Multicore Processors
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cluster-level feedback power control for performance optimization
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures
Amdahl's Law in Big Data Analytics: Alive and Kicking in TPCx-BB (BigBench)
CAMA: Energy and Memory Efficient Automata Processing in Content-Addressable Memories
Memory System Behavior of Java-Based Middleware
Computational CXL-Memory Solution for Accelerating Memory-Intensive Applications
DAPPER: A Performance-Attack-Resilient Tracker for RowHammer Defense
Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures
Accurate and Complexity-Effective Spatial Pattern Prediction
FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
Efficient Bad Block Management with Cluster Similarity
EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer
Application performance modeling in a virtualized environment
Heat Behind the Meter: A Hidden Threat of Thermal Attacks in Edge Colocation Data Centers
Cost-Sensitive Cache Replacement Algorithms
Design and Performance Evaluation of a Multithreaded Architecture
Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server Platform
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
Mascar: Speeding up GPU warps by reducing memory pitstops
Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses
FTXen: Making hypervisor resilient to hardware faults on relaxed cores
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers
Accordion: Toward soft Near-Threshold Voltage Computing
Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine Learning
KAML: A Flexible, High-Performance Key-Value SSD
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
SupermarQ: A Scalable Quantum Benchmark Suite
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?
Proceedings of the 1998 workshop on Computer architecture education, WCAE@HPCA 1998, Las Vegas, Nevada, USA, February 1998
SkyByte: Architecting an Efficient Memory-Semantic CXL-based SSD with OS and Hardware Co-design
HSMU-SpGEMM: Achieving High Shared Memory Utilization for Parallel Sparse General Matrix-Matrix Multiplication on Modern GPUs
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
Cache-Efficient Matrix Transposition
Speculative Versioning Cache
Amdahl's Law in the multicore era
The Accelerator Wall: Limits of Chip Specialization
Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network
SnakeByte: A TLB Design with Adaptive and Recursive Page Merging in GPUs
AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers
SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training
FPGA Accelerated INDEL Realignment in the Cloud
Register File Design Considerations in Dynamically Scheduled Processors
NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory
Design and implementation of software-managed caches for multicores with local memory
Poseidon: Practical Homomorphic Encryption Accelerator
ACR: Amnesic Checkpointing and Recovery
iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores
Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures
Simultaneous Multikernel GPU: Multi-tasking throughput processors via fine-grained sharing
Grad: Intelligent Microservice Scaling by Harnessing Resource Fungibility
Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems
Multithreaded Vector Architectures
Atomic SC for simple in-order processors
Recovery Oriented Computing: A New Research Agenda for a New Century
MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing
ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems
Operating Liquid-Cooled Large-Scale Systems: Long-Term Monitoring, Reliability Analysis, and Efficiency Measures
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs
Power Issues Related to Branch Prediction
Enabling Large Dynamic Neural Network Training with Learning-based Memory Management
The What's Next Intermittent Computing Architecture
Quantifying Load Stream Behavior
Optimizing Instruction Cache Performance for Operating System Intensive Workloads
Stack Value File: Custom Microarchitecture for the Stack
SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture
FlipBit: Approximate Flash Memory for IoT Devices
Improving multi-core performance using mixed-cell cache architecture
The Effects of STEF in Finely Parallel Multithreaded Processors
Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory
ParallelNN: A Parallel Octree-based Nearest Neighbor Search Accelerator for 3D Point Clouds
Run-time monitoring with adjustable overhead using dataflow-guided filtering
A case for toggle-aware compression for GPU systems
Implications of Device Timing Variability on Full Chip Timing
HiPerRF: A Dual-Bit Dense Storage SFQ Register File
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
A low-power hybrid reconfigurable architecture for resistive random-access memories
BBS: Micro-Architecture Benchmarking Blockchain Systems through Machine Learning and Fuzzy Set
An educational environment for teaching a course in computer architecture and organization
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
Warped-preexecution: A GPU pre-execution approach for improving latency hiding
Non-Vital Loads
19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models
Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement
Express Cube Topologies for on-Chip Interconnects
MemZip: Exploring unconventional benefits from memory compression
TransPIM: A Memory-based Acceleration via Software-Hardware Co-Design for Transformer
FAST: DNN Training Under Variable Precision Block Floating Point with Stochastic Rounding
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution
WASP: Exploiting GPU Pipeline Parallelism with Hardware-Accelerated Automatic Warp Specialization
Fabric convergence implications on systems architecture
Access Ordering and Memory-Conscious Cache Utilization
Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors
MRPB: Memory request prioritization for massively parallel processors
Predictive Sequential Associative Cache
A Case Study on Implementing Virtual 5D Torus Networks Using Network Components of Lower Dimensionality
A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor
Designing a processor from the ground up to allow voltage/reliability tradeoffs
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
Precision-aware soft error protection for GPUs
VIP: A Versatile Inference Processor
Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM
ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator
Selective GPU caches to eliminate CPU-GPU HW cache coherence
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors
Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput
Program Counter Based Techniques for Dynamic Power Management
Secure DIMM: Moving ORAM Primitives Closer to Memory
Software-hardware cooperative memory disambiguation
ANNA: Specialized Architecture for Approximate Nearest Neighbor Search
Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller
XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures
GRIT: Enhancing Multi-GPU Performance with Fine-Grained Dynamic Page Placement
IR-ORAM: Path Access Type Based Memory Intensity Reduction for Path-ORAM
Application Defined On-chip Networks for Heterogeneous Chiplets: An Implementation Perspective
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems
A DSM Architecture for a Parallel Computer Cenju-4
BRAVO: Balanced Reliability-Aware Voltage Optimization
Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip
A Case for Packageless Processors
FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption
Message Proxies for Efficient, Protected Communication on SMP Clusters
Optical Interconnect Opportunities for Future Server Memory Systems
Adrias: Interference-Aware Memory Orchestration for Disaggregated Cloud Infrastructures
CHOPIN: Scalable Graphics Rendering in Multi-GPU Systems via Parallel Image Composition
Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh
Perturbation-based Fault Screening
Efficient complex operators for irregular codes
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs
ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms
Venice: Exploring server architectures for effective resource sharing
Predicting DRAM-Caused Risky VMs in Large-Scale Clouds
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors
RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing Techniques
G-TSC: Timestamp Based Coherence for GPUs
Random Folded Clos Topologies for Datacenter Networks
Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study
Perception-Oriented 3D Rendering Approximation for Modern Graphics Processors
SmartDIMM: In-Memory Acceleration of Upper Layer Protocols
A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments
Skinflint DRAM system: Minimizing DRAM chip writes for low power
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
IEEE International Symposium on High Performance Computer Architecture, HPCA 2025, Las Vegas, NV, USA, March 1-5, 2025
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration
Isolating Jobs for Security on High-Performance Fabrics
Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications
Software Assistance for Data Caches
Ursa: Lightweight Resource Management for Cloud-Native Microservices
AccPar: Tensor Partitioning for Heterogeneous Deep Learning Accelerators
I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators
Architecting Space Microdatacenters: A System-level Approach
LASER: Light, Accurate Sharing dEtection and Repair
LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators
Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002
DPrime+DAbort: A High-Precision and Timer-Free Directory-Based Side-Channel Attack in Non-Inclusive Cache Hierarchies using Intel TSX
A large-scale study of soft-errors on GPUs in the field
WiDir: A Wireless-Enabled Directory Cache Coherence Protocol
Performance and power optimization through data compression in Network-on-Chip architectures
Exploiting Basic Block Value Locality with Block Reuse
MPress: Democratizing Billion-Scale Model Training on Multi-GPU Servers via Memory-Saving Inter-Operator Parallelism
Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance
PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory
Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996
Buffalo: Enabling Large-Scale GNN Training via Memory-Efficient Bucketization
Industrial Perspectives: Platform Design Challenges with Many cores
Effective Mimicry of Belady's MIN Policy
Enabling Transparent Memory-Compression for Commodity Memory Systems
Near-Ideal Networks-on-Chip for Servers
Low-overhead and high coverage run-time race detection through selective meta-data management
The integrated computer engineering design (ICED) curriculum
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
Chimera: An Analytical Optimizing Framework for Effective Compute-intensive Operators Fusion
Offline symbolic analysis to infer Total Store Order
Let's Study Whole-Program Cache Behaviour Analytically
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Safe and efficient supervised memory systems
Synthesizing Representative I/O Workloads for TPC-H
SCsafe: Logging sequential consistency violations continuously and precisely
FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks
Using Multicast and Multithreading to Reduce Communication in Software DSM Systems
ReGNN: A Redundancy-Eliminated Graph Neural Networks Accelerator
NeuroSync: A Scalable and Accurate Brain Simulator Using Safe and Efficient Speculation
Fast complete memory consistency verification
Communication Across Fault-Containment Firewalls on the SGI Origin
A Burst Scheduling Access Reordering Mechanism
A Cache Coherency Protocol for Optically Connected Parallel Computer Systems
High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation
IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023, Montreal, QC, Canada, February 25 - March 1, 2023
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
Exploiting Postdominance for Speculative Parallelization
Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads
Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing
Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor
Multithreaded Value Prediction
Pushing the limits of accelerator efficiency while retaining programmability
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems
ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors
Improving Release-Consistent Shared Virtual Memory Using Automatic Update
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors
Computational sprinting
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
PIXEL: Photonic Neural Network Accelerator
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
Enterprise-Class Cache Compression Design
NearFetch: Saving Inter-Module Bandwidth in Many-Chip-Module GPUs