yusuke1997/dblp-id-title huggingface dataset:
Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects
Fault-tolerant methods for a new lightweight cipher SIMON
Automatic Generation of Translators for Packet-Based and Emerging Protocols
Efficient Closed-Form Crosstalk Delay Metrics
Runtime fault recovery protocol for NoC-based MPSoCs
A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning
Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality Reduction
Interconnect Mode Conversion in High-Speed VLSI Circuits
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures
Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World
EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
Reducing EPL Alignment Errors for Large VLSI Layouts
Reduced-Order Modeling Based on PRONY's and SHANK's Methods via the Bilinear Transformation
TS-EFA: Resource-efficient High-precision Approximation of Exponential Functions Based on Template-scaling Method
Paradigm-Based Automatic HDL Code Generation Using LLMs
VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
Level matrix propagation for reliability analysis of nano-scale circuits based on probabilistic transfer matrix
A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays
Statistical decoupling capacitance allocation by efficient numerical quadrature method
Place and route considerations for voltage interpolated designs
RLCK Extraction and Simulation in High-Speed SoC Designs (Tutorial Abstract)
Near-threshold circuit variability in 14nm FinFETs for ultra-low power applications
Combinational logic SER estimation with the presence of re-convergence
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding
Genetic Algorithm-Assisted Golden-Free Standard Cell Library Extraction from SEM Images
PUF-PassSE: A PUF based Password Strength Enhancer for IoT Applications
High-Frequency-Measurement-Based Frequency-Variant Transmission Line Characterization and Circuit Modeling for Accurate Signal Integrity Verification
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering
Power Delivery System: Sufficiency, Efficiency, and Stability
Delay Fault Diagnosis for Non-Robust Test
Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization
IR-drop management CAD techniques in FPGAs for power grid reliability
A study on NBTI-induced delay degradation considering stress frequency dependence
Accurate Temperature Estimation for Efficient Thermal Management
Concrete Impact of Formal Verification on Quality in IP Design and Implementation
On Accumulator-Based Bit-Serial Test Response Compaction Schemes
Fast variational static IR-drop analysis on the graphical processing unit
1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA
A case for standard-cell based RAMs in highly-ported superscalar processor structures
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells
An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation
Trojan Attacks on Variational Quantum Circuits and Countermeasures
Real-Time CNN Based ST Depression Episode Detection Using Single-Lead ECG
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network
Single-Ferroelectric FET based Associative Memory for Data-Intensive Pattern Matching
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier
Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints
Process variation impact on FPGA configuration memory
Sizing-priority based low-power embedded memory for mobile video applications
Delay Fault Diagnosis Using Timing Information
EasyBand2.0: A Framework with Context-Aware Recommendation Mechanism for Safety-Aware Mobility during Pandemic Outbreaks
Global transaction ordering in Network-on-Chips for post-silicon validation
Cells reconfiguration around defects in CMOS/nanofabric circuits using simulated evolution heuristic
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems
A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits
State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency
HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs
An FPGA-based Max-K-Cut Accelerator Exploiting Oscillator Synchronization Model
Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors
Error Analysis for the Support of Robust Voltage Scaling
An Evaluation of Single-Ended and Differential Impedance in PCBs
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs
Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise
Locality-sensing Fast Neural Network (LFNN): An Efficient Neural Network Acceleration Framework via Locality Sensing for Real-time Videos Queries
MAPIM: Mat Parallelism for High Performance Processing in Non-volatile Memory Architecture
EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates
Optimal Choice of Waveform for Library Characterization for Accurate Delay Calculation
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC
3D-ICs with self-healing capability for thermal effects in RF circuits
Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling
SALAH: Simulation-Assisted LAyout Hierarchy Construction
FastSpot: Host-compiled thermal estimation for early design space exploration
Physical-design-friendly hierarchical logic built-in self-test - A case study
Integrated Sensing and Computing using Energy-Efficient Magnetic Synapses
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
Improving Reliability of Quantum True Random Number Generator using Machine Learning
IP Quality: A Design, Not a Verification Problem
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits
A MATLAB-based technique for defect level estimation using data mining of test fallout data versus fault coverage
Alleviating Bottlenecks for DNN Execution on GPUs via Opportunistic Computing
Hardware Trojans in Quantum Circuits, Their Impacts, and Defense
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning
SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography
Automated Standard Cell Library Analysis for Improved Defect Modeling
Processor Verification with hwBugHunt
GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder
Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT
Hidden Quality, Crouching Customer - How Much Does the Quality of EDA Tools Impact Electronic Design?
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond
An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing
LUPIS: Latch-up based ultra efficient processing in-memory system
Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning Process
Polynomial Formal Verification of a Processor: A RISC-V Case Study
Systematic approximate logic optimization using don't care conditions
An analytical model for interdependent setup/hold-time characterization of flip-flops
Gridless wire ordering, sizing and spacing with critical area minimization
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications
Pareto-Front Computation and Automatic Sizing of CPPLLs
Self-Powered IOT System for Edge Inference
Interconnect Modeling for Timing, Signal Integrity and Reliability
Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited)
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits
Cost-driven 3D design optimization with metal layer reduction technique
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects
Impact of Noise on the Resilience and the Security of Quantum Computing
BIC: Blind Identification Countermeasure for Malicious Thermal Sensor Attacks in Mobile SoCs
Deep Learning Based IoT System for Real-time Traffic Risk Notifications
Fundamental Data Retention Limits in SRAM Standby Experimental Results
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability
pH sensing with temperature compensation in a Molecular Biosensor for drugs detection
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits
CPDI: Cross-power-domain interface circuit design in monolithic 3D technology
Soft-Errors Phenomenon Impacts on Design for Reliability Technologies
Analog placement and global routing considering wiring symmetry
A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays
Sparsely connected neural networks in FPGA for handwritten digit recognition
Discrete Steps towards Approximate Computing
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology
Efficient SAT-based techniques for Design of Experiments by using static variable ordering
SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
Low power latch based design with smart retiming
LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction
Skew analysis and bounded skew constraint methodology for rotary clocking technology
Profiled Power-Analysis Attacks by an Efficient Architectural Extension of a CNN Implementation
A 64-core platform for biomedical signal processing
Pushing Low Power Limits on Multi-Core High Performance SoC
An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design
Effcient approaches to overcome non-convexity issues in analog design automation
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control
Advancing Quality of EDA Software (invited)
Near optimal repair rate built-in redundancy analysis with very small hardware overhead
A new low power test pattern generator using a variable-length ring counter
MACcelerator: Approximate Arithmetic Unit for Computational Acceleration
Variation Impact on SER of Combinational Circuits
Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
Methodology from chaos in IC implementation
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects
ALBORZ: Address Level Bus Power Optimization
Processing Rate Optimization by Sequential System Floorplanning
MambaLiteSR: Image Super-Resolution with Low-Rank Mamba Using Knowledge Distillation
Integrated Power Delivery Methodology for 3D ICs
SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone Design
Energy reduction by built-in body biasing with single supply voltage operation
Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test
A Root-Finding Method for Assessing SRAM Stability
Toward Intelligence in Communication Networks: A Deep Learning Identification Strategy for Radio Frequency Fingerprints
RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate
Coprocessor design space exploration using high level synthesis
Quality-Driven System-on-a-Chip Design
Designing low-VTh STT-RAM for write energy reduction in scaled technologies
Automatic Generation of Standard Cell Library in VDSM Technologies
Analysis and optimization of flip-flops under process and runtime variations
Quantum Technology for Comparator Circuit
SEU hardened clock regeneration circuits
Low power and compact mixed-mode signal processing hardware using spin-neurons
Clock gating effectiveness metrics: Applications to power optimization
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors
Functionally valid gate-level peak power estimation for processors
MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
A case study on system-level modeling by aspect-oriented programming
Self-Adaptive Systems to Drive out the Nano-Scale Devil
Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs
Should Yield be a Design Objective?
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability
Small-Delay Defect Detection in the Presence of Process Variations
Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning
BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency
Yield Enhancement Methodology for CMOS Standard Cells
NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework
A parallel clustering algorithm for placement
Full-chip analysis of unintentional forward biased diodes
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme
Enhancing circuit operation using analog floating gates
Statistical Methods for the Determination of Process Corners
Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators
Low Power 260 k Color TFT LCD One-Chip Driver IC
A technique to aggregate classes of analog fault diagnostic data based on association rule mining
SUB 45nm Low Power Design Challenges
i-Know what you Do: Privacy Evaluation of Apple Smartphones with Remote Acoustic Side-Channels
Task-Based Neuromodulation Architecture for Lifelong Learning
An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs
Analysis and Design of a 5G Multi-Mode Power Amplifier using 130 nm CMOS technology
Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation
Noise Injection and Propagation in High Performance Designs
A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers
A droop measurement built-in self-test circuit for digital low-dropout regulators
Placement aware clock gate cloning and redistribution methodology
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs
Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor
Heterogeneity exploration for peak temperature reduction on multi-core platforms
Interconnect Modeling
Low-Power Design
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
In Search of the Origin of VHDL's Delta Delays
NBTI/HCI Modeling and Full-Chip Analysis in Design Environment
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects
Energy-Efficient QoS-Aware Scheduling for S-NUCA Many-Cores
Advanced Module Packaging Method
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs
Computational Cost Reduction in Extracting Inductance
HiSIM-RP: A reverse-profiling based 1 st principles compact MOSFET model and its application to variability analysis of 90nm and 40nm CMOS
Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs
Transistor Modeling for the VDSM Era
Reliability-constrained die stacking order in 3DICs under manufacturing variability
On application of one-class SVM to reverse engineering-based hardware Trojan detection
TuneLogic: Post-silicon tuning of dual-Vdd designs
Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation
RTL datapath optimization using system-level transformations
Hardware Performance Counter Enhanced Watchdog for Embedded Software Security
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs
System-in-Package Technology: Opportunities and Challenges
Memristor-based Deep Spiking Neural Network with a Computing-In-Memory Architecture
Achieving Wave Pipelining in Spin Wave Technology
XStatic: A Simulation Based ESD Verification and Debug Environment
Network on interconnect fabric
Timing margin recovery with flexible flip-flop timing model
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis
Non-parametric Greedy Optimization of Parametric Quantum Circuits
Cost-quality trade-offs of approximate memory repair mechanisms for image data
Substrate Coupling: Modeling, Simulation and Design Perspectives
Multi-degree smoother for low power consumption in single and multiple scan-chains BIST
Design Based Yield Improvements (DBYI)
Constructing Current-Based Gate Models Based on Existing Timing Library
Two-Graph Approach to Temperature Dependent Skew Scheduling
A New Design Cost Model for the 2001 ITRS (invited)
Instruction Scheduling for Variation-Originated Variable Latencies
Improving Routability Prediction via NAS Using a Smooth One-Shot Augmented Predictor
Case studies of mixed-signal DFT
System-level modelling of dynamic reconfigurable designs using functional programming abstractions
A DyadicCluster method used for nonlinear placement
Efficient Signal Integrity Verification of Multi-Coupled Transmission Lines with Asynchronously Switching Non-Linear Drivers
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures
Modular Approach for Controlling Multi-Agent Systems with Natural Language
Impact of SoC power management techniques on verification and testing
A robust and low power dual data rate (DDR) flip-flop using c-elements
Adversarial Assertions
Regularized logistic regression for fast importance sampling based SRAM yield analysis
A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs
A 90 nm low-power successive approximation register for A/D conversions
Improving timing error tolerance without impact on chip area and power consumption
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver
Self-Time Regenerators for High-Speed and Low-Power Interconnect
Single fault reliability analysis in FPGA implemented circuits
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis
Non-Physical Pseudo-Wave-Based Modal Decoupling Technique of Multi- Coupled Co-Planar Transmission Lines with Homogeneous Dielectric Media
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis
Joint-optimization of Node Placement and UAV's Trajectory for Self-sustaining Air-Ground IoT system
Occurrence probability analysis of a path at the architectural level
A novel probabilistic SET propagation method
A Method of Embedded Memory Access Time Measurement
A design tradeoff study with monolithic 3D integration
Analysis of Attack Surfaces and Practical Attack Examples in Open Source FPGA CAD Tools
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O
Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells
Study of Floating Fill Impact on Interconnect Capacitance
Low latency divider using ensemble of moving average curves
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers
An Interactive IoT-based framework for Resource Management in Assisted living during pandemic
Design challenges and methodologies in 3D integration for neuromorphic computing systems
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC
NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data Applications
High precision yet wide range on-chip oscillator with dual charge-discharge technique
Simulation methodology for timing analysis and design optimization in digital superconducting electronics
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures
An Error Resilient Design Platform for Aggressively Reducing Power, Area and Routing Congestion
Early system level modeling of real-time applications on embedded platforms
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
In-Memory Template Matching with Approximated PCC Computation Leveraging Memristive System
Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson Solver
Issues in Deep Submicron State-of-the-Art ESD Design
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process
Overview and development of EDA tools for integration of DSA into patterning solutions
Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner
Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates
Parallel partitioning based on-chip power distribution network analysis using locality acceleration
Programmable Engines for Embedded Systems: The New Challenges
An effective BIST architecture for power-gating mechanisms in low-power SRAMs
Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
Kriging bootstrapped neural network training for fast and accurate process variation analysis
Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited)
Using Integer Equations for High Level Formal Verification Property Checking
LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection
Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs
Functional test pattern generation for maximizing temperature in 3D IC chip stack
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
Side-Channel-Driven Intrusion Detection System for Mission Critical Unmanned Aerial Vehicles
Resynthesis-based Attacks Against Logic Locking
Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET)
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs
Efficient power network analysis with complete inductive modeling
Making unreliable Chem-FET sensors smart via soft calibration