yusuke1997/dblp-id-title huggingface dataset:
32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2024, Orlando, FL, USA, May 5-8, 2024
Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study
A High-Performance Hardware Architecture for ECC Point Multiplication over Curve25519
Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs
Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors
A parallel hardware evolvable computer POLYP
Linear Placement for Static / Dynamic Reconfiguration in JBits
Memory-Efficient Pipelined Architecture for Large-Scale String Matching
RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs
FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks
System-Level Retiming and Pipelining
AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS
A Sparse Matrix Personality for the Convey HC-1
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs
Mapping the MD5 Hash Algorithm onto the NAPA Architecture
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, New York City, NY, USA, May 15-18, 2022
Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Matched Filter Computation on FPGA, Cell and GPU
Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis Tool
Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform
29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2021, Orlando, FL, USA, May 9-12, 2021
High Level Synthesis Based E-Nose System for Gas Applications
Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA
CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
TFR-GCN: A GCN Accelerator with Tile-Fusing Strategy
RISC-V Barrel Processor for Accelerator Control
Application Composition and Communication Optimization in Iterative Solvers Using FPGAs
Hybrid Data/Configuration Caching for Striped FPGAs
A Fast and Accurate FPGA-Based Fault Injection System
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs
Reconfigurable Computing Cluster Project: Phase I Brief
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
Stay Flexible: A High-Performance FPGA NPU Overlay for Graph Neural Networks
Designing Domain Specific Computing Systems
IceSpy: Reconfigurable Edge Accelerator for Scalable and Private Structural Health Monitoring
Enumeration of Bent Boolean Functions by Reconfigurable Computer
Reconfigurable real-time signal transport system using custom FPGAs
Incremental reconfiguration for pipelined applications
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
High-Level Description and Synthesis of Floating-Point Accumulators on FPGA
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters
Matrix Computations on Heterogeneous Reconfigurable Systems
Efficient Overlay Architecture Based on DSP Blocks
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer
Computing kernels implemented with a wormhole RTR CCM
Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce
Configurable computing solutions for automatic target recognition
Reconfigurable Computing for Space-Time Adaptive Processing
ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects
HLScope: High-Level Performance Debugging for FPGA Designs
Optimizing Technology Mapping for FPGAs Using CAMs
Sparse Graph Processing with Soft-Processors
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design
Design of a JTAG Based Run Time Reconfigurable System
SpCNA: An FPGA-based Accelerator for Point Cloud Convolutional Neural Networks
Microscaling Vision Transformers on FPGAs
LLM-IMC: Automating Analog In-Memory Computing Architecture Generation with Large Language Models
MRH-GCN: An Efficient GCN Accelerator for Multi-Relation Heterogeneous Graph
Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Enabling Elastic Resource Management in Cloud FPGAs via A Multi-layer Collaborative Approach
A case study in porting a production scientific supercomputing application to a reconfigurable computer
On Hard Adders and Carry Chains in FPGAs
FAssem: FPGA Based Acceleration of De Novo Genome Assembly
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System
Etna: MLIR-Based System-Level Design and Optimization for Transparent Application Execution on CPU-FPGA Nodes
C2OPU: Hybrid Compute-in-Memory and Coarse-Grained Reconfigurable Architecture for Overlay Processing of Transformers
Accelerating Apache Spark Big Data Analysis with FPGAs
Design methodologies for partially reconfigured systems
Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding
FPGA-Based Multigrid Computation for Molecular Dynamics Simulations
A Key Size Configurable High Speed RSA Coprocessor
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform
HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory
CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security
The MOLEN Processor Prototype
Preemptive Multitasking on FPGAs
FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case
Using rapid prototyping to teach the design of complete computing solutions
A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device
FPGA-Based Solid-State Drive Prototyping Platform
RENCO: A Reconfigurable Network Computer
On Optimizing the Arithmetic Precision of MCMC Algorithms
Hardware Accelerator for Subgraph Isomorphism Problems
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform
A Heterogeneous Architecture for Evaluating Real-Time One-Dimensional Computational Fluid Dynamics on FPGAs
Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation
Reconfigurable Hardware as Shared Resource for Parallel Threads
Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer
Enabling Automatic Module Generation for FCCM Compilers
Efficient 8-bit Matrix Multiplication on Intel Agilex-5 FPGAs
FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor
Fabric-Based Systems: Model, Tools, Applications
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
EBRAM - Extending the BlockRAMs in FPGAs to Support Caches and Hash Tables in an Efficient Manner
FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method
JBits™ Design Abstractions
Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems
ICARUS: A Dynamically Reconfigurable Computer Architecture
Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures
PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs
A Configurable Architecture for a Visual Saliency System and Its Application in Retail
Reconfigurable Shape-Adaptive Template Matching Architectures
Lava and JBits: From HDL to Bitstream in Seconds
HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
Accelerating an IR Automatic Target Recognition Application with FPGAs
COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking
Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure
Design Patterns for Reconfigurable Computing
An Embedded Reconfigurable Datapath for SoC
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems
The Chimaera reconfigurable functional unit
Astrophysical Hydrodynamics Simulations on a Reconfigurable System
Performance Prediction for Large-Scale Heterogeneous Platforms
A High-Performance Asynchronous FPGA: Test Results
Early Experiences with OpenCL on FPGAs: Convolution Case Study
Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers
A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms
RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations
MPC-Wrapper: Fully Harnessing the Potential of Samsung Aquabolt-XL HBM2-PIM on FPGAs
BoostGCN: A Framework for Optimizing GCN Inference on FPGA
Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices
FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions
PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA
FPGA-accelerated seed generation in Mercury BLASTP
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
High-Level Debugging and Verification for FPGA-Based Multicore Architectures
Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs
Reconfigurable Data Processing for Clouds
A Range and Scaling Study of an FPGA-Based Digital Wireless Channel Emulator
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver
A Signature Match Processor Architecture for Network Intrusion Detection
Function Proxies for Improved Resource Sharing in High Level Synthesis
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing
Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures
An FPGA implementation of pipelined multiplicative division with IEEE Rounding
EM-Aware Memory Mapping Algorithms for SRAM Based FPGA
FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction
Defending Side-Channel Attacks in Convolutional Neural Networks with Channel-Level Parallelization
An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic
A Networked FPGA-Based Hardware Implementation of a Neural Network Application
A Grammar Induction Method for Clustering of Operations in Complex FPGA Designs
A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem
Low-Latency FPGA Based Financial Data Feed Handler
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks
Ph.D. Project: An Efficient NTT Accelerator Supporting Various Lengths for HHE
Accelerating Large Scale GCN Inference on FPGA
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability
Ph.D. Project: A Novel Compilation-Based Approach for Generating Sparse Tensor Accelerators
An FPGA-Optimized Architecture of Real-time Farneback Optical Flow
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results
The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks
Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions
Feature Extraction Accelerator for Streaming Time Series
HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA
FPGA-Based CDMA Switch for Networks-on-Chip
Reconfigurable Computing Application Frameworks
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration
FPGA Side Channel Attacks without Physical Access
Quantifying Effective Memory Bandwidth of Platform FPGAs
Accelerating Scientific Model Optimization with a Pipelined FPGA-Based Differential Evolution Engine
DataMaster: A GNN-based Data Type Optimizer for Dataflow Design in FPGA
Accelerating Deformable Convolution Networks
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia
Centaur: A Framework for Hybrid CPU-FPGA Databases
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Modelling and optimising run-time reconfigurable systems
MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations
FPGAs, GPUs and the PS2 - A Single Programming Methodology
A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops
A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems
Probabilistic Scheduling in High-Level Synthesis
Soaring with TRILLI: An HW/SW Heterogeneous Accelerator for Multi-Modal Image Registration
Specifying and Compiling Applications for RaPiD
Implementation and Evaluation of a Prototype Reconfigurable Router
Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementations
Estimating Soft Processor Soft Error Sensitivity through Fault Injection
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers
Ph.D. Project Hardware-Aware Neural Networks
The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture
A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player
FERMAT: FPGA-Accelerated Heterogeneous Computing Platform Near NVMe Storage
An FPGA Based Hardware Accelerated Framework for Solar Spectra Matching with Parameterized Matched Filter IP Core
Fast Arbitrary Precision Floating Point on FPGA
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs
Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators
An FPGA-based coprocessor for ATM firewalls
An External Memory Interface for FPGA-Based Computing Engines
A Novel 2D Filter Design Methodology for Heterogeneous Devices
Power Management for FPGAs: Power-Driven Design Partitioning
BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs
Control and Configuration Software for a Reconfigurable Networking Hardware Platform
Embedded Compilation for Multimedia Applications
New Protection Mechanisms for Intellectual Property in Reconfigurable Logic
Inheriting Software Security Policies within Hardware IP Components
An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular Dynamics
A Library and Platform for FPGA Bitstream Manipulation
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller
N-TORC: Native Tensor Optimizer for Real-Time Constraints
Specifying Compiler Strategies for FPGA-based Systems
Multi-FPGA Evaluation Platform for Disaggregated Computing
Scalable and Portable Architecture for Probability Density Function Estimation on FPGAs
Technology Scaling in FPGAs: Trends in Applications and Architectures
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
APR-OIS: A Near-Sensor Point Cloud Pre-Processing Accelerator on FPGA
Experiments in Mapping Expressions to DSP Blocks
A Large-Scale Architecture for Restricted Boltzmann Machines
High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined Search
An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology
Time-Critical Software Deceleration in an FCCM
ZUMA: An Open FPGA Overlay Architecture
Communication-Aware MCMC Method for Big Data Applications on FPGAs
FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization
Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA
Decision Forest Training Accelerator Based on Binary Feature Decomposition
The swappable logic unit: a paradigm for virtual hardware
Power-hammering through Glitch Amplification - Attacks and Mitigation
Routability improvement using dynamic interconnect architecture
Ph.D. Project: Systems-on-Chip to Implement Zero-Trust Architectures
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor
Combining Serialization and Reconfiguration for Convolver Designs
Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report
A Memory-Efficient and Modular Approach for String Matching on FPGAs
Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines
Hidden Markov modeling and fuzzy controllers in FPGAs
Hand-based Interface for Augmented Reality
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
Speeding Up FPGA Placement: Parallel Algorithms and Methods
A High I/O Reconfigurable Crossbar Switch
ScalaPipe: A Streaming Application Generator
High-Performance FPGA-Based General Reduction Methods
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes
Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs
Death of the RLOC?
Aizup-a pipelined processor design and implementation on XILINX FPGA chip
Application-Aware Collective Communication (Extended Abstract)
A TDMA Ethernet Switch for Dynamic Real-Time Communication
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013
On Improving the HLS Compatibility of Large C/C++ Code Regions
Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing
MeXT-SE: A System-Level Design Tool to Transparently Generate Secure MPSoC
A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution
Pharos: a Performance Monitor for Multi-FPGA Systems
A Scalable FPGA-based Multiprocessor
An Efficient FPGA-based Architecture for Contractive Autoencoders
Impact of FPGA Architecture on Area and Performance of CGRA Overlays
A programming model for developing Application Specific Dataflow Machines on FPGAs
Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design
Reconfigurable Computing for Augmented Reality
The SMEM Seeding Acceleration for DNA Sequence Alignment
Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks
Sepia: Scalable 3D Compositing Using PCI Pamette
Assisting Network Intrusion Detection with Reconfigurable Hardware
Power2Picture: Using Generative CNNs for Input Recovery of Neural Network Accelerators through Power Side-Channels on FPGAs
Internet Connected FPGAs
Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture
COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors
A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures
Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata
Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation
A Generator of Numerically-Tailored and High-Throughput Accelerators for Batched GEMMs
Energy-Aware Optimisation for Run-Time Reconfiguration
DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAs
From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup
Moth: A Hardware Accelerator for Neural Radiance Field Inference on FPGA
A FeFET-Based Compute-in-Memory Architecture on FPGA for Neural Network Inference
A Field Programmable RFID Tag and Associated Design Flow
Improved Small Multiplier Based Multiplication, Squaring and Division
Mutable Functional Units: Initial Results
Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs
Acceleration of template-based ray casting for volume visualization using FPGAs
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing
Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources
The Development of an Operating System for Reconfigurable Computing
Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics
An FPGA Solution for Radiation Dose Calculation
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA
XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion
Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
Runtime Parameterizable Regular Expression Operators for Databases
FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid Solvers
On Sparse Matrix-Vector Multiplication with FPGA-Based System
An Alternate Wire Database for Xilinx FPGAs
3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA
SparseLUT: Sparse Connectivity Optimization for Lookup Table-Based Deep Neural Networks
Establishing Chain of Trust in Reconfigurable Hardware
Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Reloc - An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles
33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2025, Fayetteville, AR, USA, May 4-7, 2025
A PYNQ-Based Framework for Rapid CNN Prototyping
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm
Map-reduce as a Programming Model for Custom Computing Machines
SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable Hardware