yusuke1997/dblp-id-title huggingface dataset:
Inductive Fault Analysis for Test and Diagnosis of DNA Sensor Arrays
Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density
Learning-Based Secure Spectrum Sharing for Intelligent IoT Networks
CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator
Enhancing performance of wireless NoCs with distributed MAC protocols
Design optimization of sense amplifiers using deeply-scaled FinFET devices
A 5T Half-SRAM Design for Cold CMOS Physical Unclonable Function Applications and Beyond
A 2-layer laser multiplexed photonic network-on-chip
Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding
Energy-Adaptive Checkpoint-Free Intermittent Inference for Low Power Energy Harvesting Systems
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability
Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces
Transition Aware Global Signaling (TAGS)
Clock planning for multi-voltage and multi-mode designs
A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology
Efficient Transfer Learning on Modeling Physical Unclonable Functions
A 1.2 V Double-Tail StrongARM Latch Comparator with 51 fJ/comparison and 380 μV Input Noise in 65 nm CMOS Technology
Comparative analysis of clock distribution networks for TSV-based 3D IC designs
Design issues and insights of multi-fin bulk silicon FinFETs
0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus
Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis
Congestion Driven Buffer Planning for X-Architecture
DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering?
Probabilistic Bottom-Up RTL Power Estimation
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs
Design of radiation hardened wide tuning range CMOS oscillators
An Efficient Deep Reinforcement Learning Framework for UAVs
18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, CA, USA, March 14-15, 2017
QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization
Coping with Uncertainty
An IoT-enabled Electronic Textile-based Flexible Body Sensor Network for Real-time Health Monitoring in Assisted Living during Pandemic
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation
Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms
Inductance Aware Interconnect Scaling
CMP monitoring and prediction based metal fill
Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions
A geometric approach to register transfer level satisfiability
Power efficient router architecture for wireless Network-on-Chip
A Comprehensive Multi-Voltage Design Platform for System-Level Validation of Standard Cell Library
Formal Verification of Pipelined Microprocessors with Delayed Branches
Low Power Testing of VLSI Circuits: Problems and Solutions
A General Framework to Map Neural Networks onto Neuromorphic Processor
Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing
On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis
A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes
Advances in Computation of the Maximum of a Set of Random Variables
Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems
Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies
Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life?
Parametric analysis to determine accurate interconnect extraction corners for design performance
Joint Equalization and Coding for On-Chip Bus Communication
NBTI-aware statistical circuit delay assessment
A Qualification Platform for Design Reuse
The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices
Performance modeling and optimization for on-chip interconnects in 3D memory arrays
Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools
Composite Sub-surface Model for RF GaN-HEMTs
Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs
Diversity Techniques for Concurrent Error Detection
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits
Tracking hardware evolution
A Crosstalk Modelling Method between a Power Supply and a Nearby Signal in High-density Interconnection PCBs
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations
Efficient Object Detection from Fused RGB and IR Aerial Images Enhanced by Token Selection
Temporal-encoded 6T-RRAM with Bidirectional Control for Future Neuromorphic Systems
An Intermittent OTA Approach to Update the DL Weights on Energy Harvesting Devices
Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder
Analysis of setup and hold margins inside silicon for advanced technology nodes
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop
Soft Core Based Model of a Microcomputer Family
Modeling MOS Snapback for Circuit-Level ESD Simulation Using BSIM3 and VBIC Models
IP REUSE QUALITY: "Intellectual Property" or "Intense Pain"?
Leakage temperature dependency modeling in system level analysis
Automated methods for eliminating X bugs
Power prediction of embedded scalar and vector processor: Challenges and solutions
ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes
Enabling DIR(Designing-In-Reliability) through CAD Capabilities
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits
Harvesting-aware adaptive energy management in solar-powered embedded systems
Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation
Learning based DVFS for simultaneous temperature, performance and energy management
Clock buffer and flip-flop co-optimization for reducing peak current noise
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
A new single inductor bipolar multiple output (SIBMO) boost converter using pulse frequency modulation (PFM) control for OLED drivers and optical transducers
hArtes design flow for heterogeneous platforms
Fast Timing Update under the Effect of IR Drop
A low input, low-power dissipation CMOS ADC
A workload-aware-design of 3D-NAND flash memory for enterprise SSDs
First-Order Continuous-Time Sigma-Delta Modulator
A Scalable Communication-Centric SoC Interconnect Architecture
Human Immune System Inspired Architecture for Self-Healing Digital Systems
A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies
Exploring the use of volatile STT-RAM for energy efficient video processing
"Condition-based" dummy fill insertion method based on ECP and CMP predictive models
Efficient Model Update for General Link-Insertion Networks
High-level synthesis of key based obfuscated RTL datapaths
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition
Closing the Verification Gap with Static Sign-off
Designing High Quality, Scaleable SoC??s with Heterogeneous Components
Achieving Zero ADC Production Test Time with Self-calibration and BIST
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm
Vision-inspired global routing for enhanced performance and reliability
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below
On the Use of Windows for Accurate Analysis of Package Interconnects
A 3D IC designs partitioning algorithm with power consideration
Buffered Clock Tree for High Quality IC Design
Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance
Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors
Effectiveness of hybrid recovery techniques on parametric failures
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect
Design of ultra high density and low power computational blocks using nano-magnets
A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits
Dynamic range estimation for systems with control-flow structures
HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec
FinFET Based SRAM Design for Low Standby Power Applications
Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit
An accurate and scalable MOSFET aging model for circuit simulation
Signal Attenuation in Transmission Lines
Integrated Inductors Modeling and Tools for Automatic Selection and Layout Generation
A preliminary study on system-level impact of persistent main memory
How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results
On Structural vs. Functional Testing for Delay Faults
A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes
The low power design of SM4 cipher with resistance to differential power analysis
MErBAG: Mesh Error Based Adaptive Grid Generation in System-Level Thermal Analysis
Low Voltage Buffered Bandgap Reference
A hypervisor approach with real-time support to the MIPS M5150 processor
SOMA: Security Evaluation of Obfuscation Methods via Attack Sequencing
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache
Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
A VLSI System Perspective for Microprocessors Beyond 90nm
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation
True Coverage: A Goal of Verification
Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning
A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs)
NBTI aware workload balancing in multi-core systems
A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers
Automatic die placement and flexible I/O assignment in 2.5D IC design
Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification
Efficient and Scalable Place and Route Methodology for Large-Scale Hierarchical Designs: Achieving Faster Turnaround Time and Predictability
CMP-SiL: Confidential Multi Party Software-in-the-Loop Simulation Frameworks
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
Jitter Decomposition by Time Lag Correlation
The OpenAccess Coalition - The Drive to an Open Industry Standard Information Model, API, and Reference Implementation for IC Design Data (invited)
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects
Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces
Efficient checking of power delivery integrity for power gating
Quality and EDA
Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages
Design for Variability in DSM Technologies
A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects
A Comparative Analysis of Microrings Based Incoherent Photonic GEMM Accelerators
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders
Monolithic 3D IC design: Power, performance, and area impact at 7nm
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations
Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach
Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age
EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation
A complete framework of simultaneous functional unit and register binding with skew scheduling
Fast Boolean Matching with Don't Cares
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs
kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier
Leakage Biased Sleep Switch Domino Logic
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
Determining proximal geolocation of IoT edge devices via covert channel
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators
Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?
Dynamic voltage (IR) drop analysis and design closure: Issues and challenges
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint
Coupled Simulation of Circuit and Piezoelectric Laminates
Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP)
Multi-objective optimization techniques for VLSI circuits
A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits
SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization
Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method
I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os
Why Integrated Yield Management is a Necessity
Chip-package power delivery network resonance analysis and co-design using time and frequency domain analysis techniques
A Power Network Synthesis Method for Industrial Power Gating Designs
Cost-effective optimization of serial link system for Signal Integrity and Power Integrity
Design of ESD Protection Device Using Statistical Methods
Machine Learning-Assisted Website Fingerprinting Attacks with Side-Channel Information: A Comprehensive Analysis and Characterization
Worst case timing jitter and amplitude noise in differential signaling
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology
Harnessing ferroelectrics for non-volatile memories and logic
Assessment of reliability impact on GHz processors with moderate overdrive
Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling
Constructing fast and energy efficient 1TnR based ReRAM crossbar memory
A Low-overhead PUF-based Secure Scan Design
Novel low-power 12-bit SAR ADC for RFID tags
On-Line Adjustable Buffering for Runtime Power Reduction
Error mitigation in digital logic using a feedback equalization with schmitt trigger (FEST) circuit
Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration
Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories
Reproducing Fear Conditioning of Rats with Unmanned Ground Vehicles and Neuromorphic Systems
Economic Analysis of a Stopping-rule in Branch Coverage Testing
Efficient Reachability Analysis Based on Inductive Invariant Using X-value Based Flipflop Selection
Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model
Model Auto Extraction for Gate-All-Around Silicon Nanowire MOSFETs Using A Decomposition-Based Many-Objective Evolutionary Algorithm
An electromagnetic fault injection sensor using Hogge phase-detector
A Novel Test Generation Methodology for Adaptive Diagnosis
Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method
Clock Skew Scheduling Under Process Variations
Full-Chip Signal Interconnect Analysis for Electromigration Reliability
Simultaneous buffer and interlayer via planning for 3D floorplanning
A fault prediction module for a fault tolerant NoC operation
Securing FPGA-based obsolete component replacement for legacy systems
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology
Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors
A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC
LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search
Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network
Plenary Session 2P
Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults
Clock buffer polarity assignment considering capacitive load
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model
Ternary-Valued Associative Processor Design
Power-delay product based resource library construction for effective power optimization in HLS
Benchmarks for Interconnect Parasitic Resistance and Capacitance
An Area Efficient Superconducting Unary CNN Accelerator
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
Redundant via insertion under timing constraints
Thermal-aware lifetime reliability in multicore systems
A novel two-dimensional scan-control scheme for test-cost reduction
A SPICE-based Framework to Emulate Quantum Circuits with classical LC Resonators
A Clustering Based Area I/O Planning for Flip-Chip Technology
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes
Noise Safety Design Methodologies
Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits
Managing Derivative SoC Design Projects to Better Results
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction
Fast synthesis of low power clock trees based on register clustering
An area efficient on-chip hybrid voltage regulator
Welcome Notes
Statistical Modeling for Circuit Simulation
Generation of Hazard Identification Functions
A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architectures
Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations
On-chip DC-DC converters for three-dimensional ICs
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations
CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation
Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
Towards Internet-of-Things for Wearable Neurotechnology
A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality
Accurate Estimation of Circuit Delay Variance with Limited Monte Carlo Simulations Using Bayesian Inference
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node
Transistor Level Budgeting for Power Optimization
Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs
High performance electrical driven hotspot detection solution for full chip design using a novel device parameter matching technique
Aging-aware critical paths for process related validation in the presence of NBTI
Quality on Time
Variation-immune resistive Non-Volatile Memory using self-organized sub-bank circuit designs
Accurate analysis of substrate sensitivity of active transistors in an analog circuit
Shared Scratch-Pad Memory Space Management
Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation
A Simulation-Based Soft Error Estimation Methodology for Computer Systems
Energy efficient design of DVB-T2 constellation demapper
Logic SER Reduction through Flipflop Redesign
Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design
High Resolution Read-Out Circuit for DNA Label-Free Detection System
Efficient Digital Architecture of Spiking Encoders for Neuromorphic Accelerators
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture
Notch filter based Readout Interface for Hall-effect sensors for DC and High-Frequency Currents
Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT
Fast FPGA-based fault injection tool for embedded processors
Leakage optimization using transistor-level dual threshold voltage cell library
Statistical Analysis of Clock Skew Variation in H-Tree Structure
LLM-FIN: Large Language Models Fingerprinting Attack on Edge Devices
Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
Improved path clustering for adaptive path-delay testing
Runtime Validation of Transactional Memory Systems
Automated Supervised Topic Modeling Framework for Hardware Weaknesses
Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer (invited)
DFT and Test: Ensuring Product Quality
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
On temperature planarization effect of copper dummy fills in deep nanometer technology
Three-dimensional Memristive Deep Neural Network with Programmable Attention Mechanism
Analysis of VF-TLP ESD Measurements Using Machine Learning
Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing
Interface Specification Assurance Methods
4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Low Power BIST for Wallace Tree-Based Fast Multipliers
A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning