yusuke1997/dblp-id-title huggingface dataset:
Hardware Software Codesign for a Hybrid Substitution Box
Design Automation Standards: The IP Providers Perspective
Tutorial T8B: Performance Debugging of Complex Embedded Systems
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits
Extensions to Programmable DSP architectures for Reduced Power Dissipation
28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015
Array Index Allocation under Register Constraints in DSP Programs
A Decade of Platform-Based Design: A look backwards, a look forwards
Automated AC (Timing) Characterization for Digital Circuit Testing
Statistical methods for delay fault coverage analysis
Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing Latches
Ultra Low Energy Reduced Switching DAC for SAR ADC
Partitioning VLSI Floorplans by Staircase Channels for Global Routing
Energy Efficient Programmable Computation
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing
CMOSP18 FD-SOI Technology Based MCU Achieving High Performance of 1.2GHz Using High Speed, Optimized Leakage & High Density Tightly Coupled Memory (TCM)
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis
Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis
Improving the Diagnosability of Digital Circuits
Inserting Placeholder Slack to Improve Run-Time Scheduling of Non-preemptible Real-Time Tasks in Heterogeneous Systems
Evolvable Hardware for Fault Mitigation in Control Circuits
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs
An Innovative Solution to Improve Ultra Low Voltage Writability and Leakage in GPU SRAMs
Buffered Routing Tree Construction under Buffer Placement Blockages
Codesign for Broadcast Addressing Biochip Towards Tamper-Resistance and Enhanced Reliability
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips
Computational Lithography - Moore Bang for your Buck
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products
Enhancing Digital Microfluidic Biochip Operations with Scheduling Interval Method
Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design
Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach
Image Completion using a Sparse Probabilistic Spin Logic Network
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block
Efficient Scale Invariant Human Detection Using Histogram of Oriented Gradients for IoT Services
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India
Security Metrics for Power Based SCA Resistant Hardware Implementation
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
Message from the Steering Committee Chair
Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations
Cyber Security of Cyber Physical Systems: Cyber Threats and Defense of Critical Infrastructures
Impact of Partial Reset on Fault Independent Testing and BIST
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space
An Automated Approach for Minimum Jitter Buffered H-Tree Construction
Tutorial T1: Designing Secure SoCs
Design and Analysis of a Minimally Invasive and ECG Controlled Ventricular Assistive Device
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images
A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects
Temperature Minimization Using Power Redistribution in Embedded Systems
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence
ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications
Variable Input Delay CMOS Logic for Low Power Design
DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification
Design for Trust Utilizing Rareness Reduction
A fast-multiplier generator for FPGAs
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
An Accurate Probalistic Model for Error Detection
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer
A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode
Crosstalk Noise Analysis at Multiple Frequencies
Mixed-Signal Test
An Integrated Multipurpose Low-Power Electrochemical Readout Interface with On-Chip Input Waveform Generator
An Algorithm for M Shortest Routes for a Net
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits
Electrical Model For Program Disturb Faults in Non-Volatile Memories
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects
Retargetable Functional Simulator Using High Level Processor Models
AMS-Miner: Mining AMS Assertions Using Interval Arithmetic
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI
Object oriented data modeling for VLSI/CAD
Electronic Industry on Fire: How to Survive and Thrive
A novel CMOS monolithic analog multiplier with wide input dynamic range
SRIL: Securing Registers from Information Leakage at Register Transfer Level
Synchronized Generation of Directed Tests Using Satisfiability Solving
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video
Database Search and ATPG - Interdisciplinary Domains and Algorithms
Incorporating Process Induced Effects into RC Extraction
On-chip networks: A scalable, communication-centric embedded system design paradigm
Reducing the Overhead of Stochastic Number Generators Without Increasing Error
Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample Preparation
A Path Delay Fault Simulator for Sequential Circuits
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control
Efficient Placement of Compressed Code for Parallel Decompression
Application of High-Level Synthesis in an Industrial Project
Evaluating Run-Time Techniques for Leakage Power Reduction
Low-Power Wireless Sensor Networks
Test Transformation to Improve Compaction by Statistical Encoding
Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI
Efficient simulation of interconnect and mixed analog-digital circuits in ACES
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications
A Graph-Theoretic Approach for Register File Based Synthesis
A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA
Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India
A 20MHz CMOS Variable Gain Amplifier
Stochastic Number Generation with Few Inputs
Energy Efficient Scheduling for Datapath Synthesis
Few Good Frequencies for Power-Constrained Test
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits
Real Time Dynamic Voltage Scaling For Embedded Systems
Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection
Testing High-Speed IO Links Using On-Die Circuitry
Model Based Test Generation for Microprocessor Architecture Validation
A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS
Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits
An ASIC for High Performance Stepper Motor Control
N2S: An Automatic Netlist to Schematic generator
T5: Low-Power Design
Sequential Chaotic Annealing and its Application to Multilayer Channel Routing
Multilevel Factorization Technique for Pass Transistor Logic
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit
SANNA: Secure Acceleration of Neural Network Applications
Computing area and wire length efficient routes for channels
Novel Circuit Architecture for configurable eDP and MIPI DPHY IO
A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead
Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments
Keynote talk: Embedded vision systems
Formal Verification of a Public-Domain DDR2 Controller Design
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage
Thermal-Safe Schedule Generation for System-on-Chip Testing
Electrical Modeling of Lithographic Imperfections
Configurable Processor the Building Block for SOC (System-On-a-Chip)
High Level Synthesis from Sim-nML Processor Models
Trimless, PVT Insensitive Voltage Reference Using Compensation of Beta and Thermal Voltage
On Improving Static Test Compaction for Sequential Circuits
Customizing Instruction Set Extensible Reconfigurable Processors Using GPUs
Self-Sleep Buffer for Distributed MTCMOS Design
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis
Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS
Controlling State Explosion in Static Simulation by Selective Composition
Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems
SUBGEN: a genetic approach for subcircuit extraction
Double Pass Transistor Logic for High Performance Wave Pipeline Circuits
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems
Simulation and Modeling of a Multicast ATM Switch
Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains
Mutual Information based Efficient Spike Encoding on FPGA
DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions
Test Cost Reduction Using Partitioned Grid Random Access Scan
Phase Change Memory Faults
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation
A consistent labeling approach to hardware software partitioning
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing Strategy
Resource Allocation and Binding Approach for Low Leakage Power
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)
A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFET
A 160MSPS 8-Bit Pipeline Based ADC
A sub-μW Fully Integrated Compact CMOS Temperature Sensor for Passive RFID Applications
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model
SEVA: Structural Analysis based Security Evaluation of Sequential Locking
An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects
High Performance Integer DCT Architectures for HEVC
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults
Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors
Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low Temperature
Tutorial T6A: Pedagogy of Negative Feedback Circuits
A Global Test Point Placement Algorithm of Combinational Circuits
An Evolutionary Approach to System Redesign
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
Low Power Design Methodologies for Systems-on-Chips
Recent Advances in Verification, Equivalence Checking and SAT-Solvers
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies
VSI Standards, Current Status and Future Work
Design for high-speed testability of stuck-at faults
Zero Steady State Current Power on Reset Circuit with Brown-Out Detector
Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits
Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures
Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects
Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained Scheduling
Interface Synthesis for Embedded Applications in a Co Design Environment
A 2.5 V 10 bit SAR ADC
An Ultra-low Power Symbol Detection Methodology and Its Circuit Implementation for a Wake-up Receiver in Wireless Sensor Nodes
Future FPGA Technologies, in Partnership with Universities
Analog Modeling Using Event-Driven HDL's
Minimizing Total Wire Length By Flipping Modules
An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators
Evaluating the Impact of Transition Delay Faults in GPUs
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
Large Dynamic Range Readout Integrated Circuit for Infrared Detectors
Circuit optimization for minimisation of power consumption under delay constraint
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA
Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design
A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA
Performance Optimization with Scalable Reconfigurable Computing Systems
Boolean Decomposition Using Two-literal Divisors
An Efficient Methodology for Noise Characterization
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range
A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors
New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top Contact
Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates
A 0.009mm 2 , 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs
Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs
Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms
A Novel Reconfigurable Co-Processor Architecture
Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education
Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?
WIB-SAR: Write Intensity Based Selective Address Remapping
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture
Analog Circuit Testing Using Auto Regressive Moving Average Models
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder
FPGA Implementation of Median Filter
A Sea-of-Gates Style FPGA Placement Algorithm
Serialized Control Interface ASIC for Distributed Controllers of Space-Borne RADAR
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits
Robust Verification Methodology for Scan Chain in Memories
Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET
VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests
Partitioned Fair Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded Systems
An Efficient Method For Characterization Of ASIC Compilers
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions
Energy-Efficient Dynamic Data Encoding for Multi-level STT-MRAM
A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization
A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs
Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive
Design Partitioning on Single-Chip Emulation Systems
Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
OPSYN - OASYS Based Pseudosynthesis Tool
Specification Driven Design of Phase Locked Loops
A New Hardware Routing Accelerator for Multi-Terminal Nets
PPA-Aware Power Grid Optimization Techniques for Congested High Frequency Datapath Designs
Overcoming Energy and Reliability Challenges for IoT and Mobile Devices with Data Analytics
A Portable Ultra-low-cost Multi-Gas Sensing System-on-Module for Wireless Air Quality Monitoring Network
Instruction Level Power Analysis and Optimization of Software
Hardware Algorithms for Polygon Matching
Area Efficient VLSI Design with Cells of Controllable Complexity
Single Chip Encryptor/Decryptor Core Implementation of AES Algorithm
Clock Tree Skew Minimization with Structured Routing
VLSI floorplan generation and area optimization using AND-OR graph search
Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror
Early Bug Detector - A Verification Methodology for DFD-SoC RTL Parameters
Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation
Functional Refinement: A Generic Methodology for Managing ESL Abstractions
Variation-Conscious Formal Timing Verification in RTL
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph
A Rapid Methodology for Multi-mode Communication Circuit Generation
Heterogeneous Floorplanning for FPGAs
A SPICE Macromodel for the Analysis of Lossy Dispersive Coupled GaAs Interconnect Line System
Efficient Hierarchical Post-Silicon Validation and Debug
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters
A 3.55 dB NF Ultra-Compact Noise-Optimized LNA for 5G mm-Wave Bands in 65nm CMOS
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits
Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits
Battery Life Estimation of Mobile Embedded Systems
Compiler-Directed Code Restructuring for Operating with Compressed Arrays
OpenSPARC - A Scalable Chip Multi-Threading Design
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects
CM-SIM: A Parallel Circuit Simulator on a Distributed Memory Multiprocessor
An Efficient Method for Clock Skew Scheduling to Reduce Peak Current
Formal Verification of C Language Based VLSI Designs
Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy Flight
Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes
A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node
RTL Test Generation on Multi-core and Many-Core Architectures
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System
TCAD Based Study of String Current Variability in 3D NAND Flash Memory
A Hierarchical Test Generation Using High Level Primitives
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs
A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata
DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements
Topological Routing Amidst Polygonal Obstacles
On Testing of Superscalar Processors in Functional Mode for Delay Faults
MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method
Modeling and Estimation of Leakage in Sub-90nm Devices
Synthesis of Asynchronous Circuits Using Early Data Validity
A study of composition schemes for mixed apply/compose based construction of ROBDDs
A 27S/32S DC-balanced line coding scheme for PAM-4 signaling
Manufacturability and Testability Oriented Synthesis
Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses
Code Transformations for TLB Power Reduction
High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities
Programmable cellular automata based testbed for fault diagnosis in VLSI circuits
Power Efficient Sense Amplifier For Emerging Non Volatile Memories
A VLSI architecture for the computation of NURBS patches
Compact Implementations of FPGA-based PUFs with Enhanced Performance
Silicon Heterostructure Devices for RF Wireless Communication
A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL
A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme
DEFLAN- A delay estimator for floorplanner
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping
Systematic Methodology for High-Level Performance Modeling of Analog Systems
A Hybrid Energy Efficient Digital Comparator
Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation
Controllability-driven Power Virus Generation for Digital Circuits
Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration
Finite Element Analysis of SIGe npn HBT
Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar Arrays
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits
Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs
Efficient MBIST Area and Test Time Estimator Using Machine Learning Technique
T3: Physical Design
Power Reduction Techniques for Portable DSP Applications
Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid
Synthesizing "Verification Aware" Models: Why and How?
Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes
Can SAT be used to Improve Sequential ATPG Methods?
Error Diagnosis of Sequential Circuits Using Region-Based Mode
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
Peripheral Partitioning and Tree Decomposition for Partial Scan
Resource requirements for field programmable interconnection chips
Securing Module-Less Synthesis on Cyberphysical Digital Microfluidic Biochips from Malicious Intrusions
Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip