yusuke1997/dblp-id-title huggingface dataset:
A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip Applications
A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations
Pinpointing Cache Timing Attacks on AES
Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models
An Adaptive Body-Biased Clock Generation System in 28nm CMOS
Svoboda-Tung division with no compensation
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN
A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology
Does retiming affect redundancy in sequential circuits?
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
FinFET SRAM Design
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis
An FPGA Based High throughput Discrete Kalman Filter Architecture for Real-Time Image Denoising
A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity
Lichen: Leveraging Coupled Heterogeneity
Circuit Design using Resonant Tunneling Diodes
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp
Industrial Strength Formal Verification Techniques for Hardware Designs
9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India
Multidimensional Grid Aware Address Prediction for GPGPU
Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs
A High Speed FIR Filter Architecture Based on Novel Higher Radix Algorithm
Advanced LCD Timing Controller IC with Memory-Assisted Response Time Compensation
Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks
Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple
Repeater Insertion To Minimise Delay In Coupled Interconnects
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA
A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in 0.18µ Digital CMOS
FAST: FPGA Targeted RTL Structure Synthesis Technique
Optimization of Sub-Threshold Standard Cells for Energy Efficient Designs
Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules
A 64b/66b Line Encoding for High Speed Serializers
Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits
Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization
NFC for Pervasive Healthcare Monitoring
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology
Personal and Portable: The Evolving Definition
Power Aware Post-Manufacture Tuning of MIMO Receiver Systems
4×2Gbps Source-Synchronous Transmitter in 45nm CMOS
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models
Design Space Exploration for Data Path Synthesis
LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits
FAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits
Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems
CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip
A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip
Design of high performance two stage CMOS cascode op-amps with stable biasing
Solving Physical Design Problems on a Vector Machine
Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems
Parallelization of DC Analysis through Multiport Decomposition
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs
A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals
Ring Oscillator with Improved Design
Efficient multisine testing of analog circuits
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults
Debug Automation for Synchronization Bugs at RTL
Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines
An Efficient Memory Zeroization Technique Under Side-Channel Attacks
Multi-CoDec Configurations for Low Power and High Quality Scan Test
Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model
Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes
Migration Aware Low Overhead ERfair Scheduler
36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023
Electrical Modeling and Characterization of Copper/Carbon Nanotubes in Tapered through Silicon Vias
VLSI Architectures for Jacobi Symbol Computation
On Dependence of Amplitude Noise versus Offset Frequency in LC Oscillators
High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET Technology
Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power Gating
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function
Efficient Implementation of Multiple On-Chip Signature Checking
Power Optimization of LNA for LTE Receiver
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors
An Energy Efficient In-Memory Computing Machine Learning Classifier Scheme
A Force Directed Hill-Climbing Placement Algorithm
A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design
Low Complexity High Speed Deep Neural Network Augmented Wireless Channel Estimation
A micropower analog hearing aid on low voltage CMOS digital process
Efficient RTL Power Estimation for Large Designs
Measuring Area-Complexity Using Boolean Difference
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
A Design Approach for Compressor Based Approximate Multipliers
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming
An Optimal Design for Parallel Test Generation Based on Circuit Partitioning
A novel controlled shutdown scheme for DCDC converters enabling energy recycling
Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications
Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems
Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging
Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator
Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs
Made for India Forum
Energy Model Based Macrocell Placement for Wirelength Minimization
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems
Voting model based diagnosis of bridging faults in combinational circuits
Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons
An Efficient RISC-V Vector Coprocessor for Heart Rate Variability Detection on Edge
Scalable techniques and tools for reliability analysis of large circuits
Programmable Delay Line With Inherent Duty Cycle Correction
Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis
Rescheduling of Power Gating Instructions for Reduction of In-rush Current
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier
Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life
A Low Power 256 KB SRAM Design
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI
Pseudoduplication - An ACOB Technique for Single-Ended Circuits
High-Performance Power Grids For Nanometer Technologies
Reconfigurable Digital Logic Gate Based on Neuromorphic Approach
System Level Specification and Synthesis
Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go?
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities
An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation
Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETs
Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction
Role of Interface Trap Charges in the Performance of Monolayer and Bilayer MoS2-based Field-Effect Transistors
Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to Silicon
Technologies for Safe and Intelligent Transportation Systems
On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control
A New Device Level Digital Simulator for Simulation and Functional Verification of Large Semiconductor Memories
Identifying Combination of Defects and Unknown Defects on Semiconductor Wafers using Deep Learning and Hierarchical Reclustering
Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP
An Efficient Method for Computation of Signatures
Diagnosis of parametric path delay faults
Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things
RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation
An Efficient VLSI Architecture for Convolution Based DWT Using MAC
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter
Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays
Bounding Supply Noise Induced Path Delay Variation Using a Relaxation Approach
VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures
A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process
Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System
SAGA: the first general-purpose on-line arithmetic co-processor
Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling
Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2 m )
Programmable Output Multi-phase Switched Capacitor Step-Up DC-DC Converter with SAR-based Regulation
Circuit Optimization at 22nm Technology Node
The "G-F" 2-Valued Formula Generating Complete Set of Tests to Multiple Faults
Efficient Techniques for Noise Characterization of Sequential Cells and Macros
Emulation - Smart Way of Power Estimation and Power Aware Verfication
Pseudo-Continuous Output Switched-Capacitor Amplifier for Rail-to-Rail Current Sensing Application
An Efficient Method for Bottom-Up Extraction of Analog Behavioral Model Parameters
A Design Technique of TSC Checker for Borden's Code
Video Coding Tools and Their Impact on Compression Engine Architecture
Diagnostic Simulation of Sequential Circuits Using Fault Sampling
A System for Behavior Extraction from FPGA Implementations of Synchronous Designs
A Reconfigurable Processor for Phylogenetic Inference
An Investigation on Inherent Robustness of Posit Data Representation
13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link
SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors
Automated Low-Cost SBST Optimization Techniques for Processor Testing
Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture
Towards Single Pin Scan for Extremely Low Pin Count Test
Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs
Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI
Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction
Retiming of synchronous circuits with variable topology
ISP: An Improved Slicing Pair Code for Skewed Slicing Floorplan
Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS
Design of RF Tuner for Cable Modem Applications
Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993
On Bridging Faults in ECL Circuits
Instruction-Set Modeling for ASIP Code Generation
Analysis and Design Considerations for MASH of Noise Shaped SAR ADCs
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis
12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India
How Good Silicon Oxide-based Memristor Can be?
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping
Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence
Formal Verification of an ARM Processor
Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained Platforms
Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections
Pulse-width Modulation Technique for Generation of Multiple Analog Voltages for On-chip Calibration
GB: A New Grid-Based Binding Approach for High-Level Synthesis
Fast Arithmetic on Xilinx 5200 FPGA
A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
Hardware Software Codesign of DSP System Using Grammar Based Approach
Binary neural network based real time emotion detection on an edge computing device to detect passenger anomaly
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures
Synchronization of communicating modules and processes in high level synthesis
A Carry Select Adder with Conflict Free Bypass Circuit
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates
NSGA-RM: NSGA-II Evolved Performance Optimized Non-Homogeneous Recursive Polynomial Multiplier Architectures
Optimizing Logic Design Using Boolean Transforms
On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
A Technique to Improve Capture Range of a PLL in PRML Read Channel
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling
A Massively Parallel, Micro-Grained VLSI Architecture
Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks
Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling
Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation
On-the-Fly Donut Formation in Compiled Memory
An Introduction to VHDL 2008
Verifying Tomasulo's Algoithm by Refinement
3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Fast and Robust Sense Amplifier for Digital In Memory Computing
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop
Interconnect Process Variations: Theory and Practice
Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters
Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications
Current Mode Ternary D/A Converter
Call for Participation: VLSI Design 2007
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations
A Comparative Study of Pseudo Stuck-At and Leakage Fault Model
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers
Electromigration-Aware Physical Design of Integrated Circuits
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs
Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 Compressor
A Progressive Two-Stage Global Routing for Macro-Cell Based Designs
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
A Bus Encoding Technique for Power and Cross-talk Minimization
Testable Design of Sequential Circuits with Improved Fault Efficiency
Functional clock schedule optimization
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
Package-silicon co-design - Experiment with an SOC design
Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism
A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
Proceedings of the Fifth International Conference on VLSI Design, VLSI Design 1992, Bangalore, India, January 4-7, 1992
Channel Optimization for the Design of High Speed I/O links
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications
Industry Standards from Accellera
Partitioning sequential circuits for low power
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology
Power Optimization Techniques for DDR3 SDRAM
Multilevel Logic Minimization Using Functional Don't Cares
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers
A High Performance Switchable Multiband Inductor Structure for LC-VCOs
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
Assertion-Based Functional Consistency Checking between TLM and RTL Models
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops
Design Optimization at the Fluid-Level Synthesis for Safe and Low-Cost Droplet-Based Microfluidic Biochips
New frontiers for embedded computing
Integrated On-Chip Storage Evaluation in ASIP Synthesis
Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits
Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array
Address Code and Arithmetic Optimizations for Embedded Systems
Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers
An Accurate, Power and Area Efficient 13.33x Charge Pump with Wide-Range Programmability for Biomedical Sensors
A Novel Approach towards Biochemical Synthesis on Cyberphysical Digital Microfluidic Biochip
Designing Reconfigurable Systems in Lava
A Fast Equation Free Iterative Approach to Analog Circuit Sizing
Improved Timing Windows Overlap Check Using Statistical Timing Analysis
An Approach to Software Performance Evaluation on Customized Embedded Processors
Design of AFE and PWM Drive for Lithium-Ion Battery Management System for HEV/EV System
Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors
Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective
Low-Energy BIST Design for Scan-based Logic Circuits
Keynote Talk: A Wireless Sensor a Day Keeps the Doctor Away
A Fast Two-level Logic Minimizer
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips
A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops
A Low Noise, Low Power, Wide Range Programmable Output Reference Buffer for Sensor Applications
Retiming with logic duplication transformation: theory and an application to partial scan
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs
A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation
A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications
SV Based Fast & Accurate Verification Methodology for CTLE Adaptation Algorithm
Manufacturing and Test Considerations in System-On-Chip Designs
Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds
Specification and Design of a Quasi-Delay-Insensitive Java Card
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass
A High Accuracy Bandgap Reference with Chopped Modulator to Compensate MOSFET Mismatch
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop
High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio
Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design
Programmable Digital Frequency Multiplier
A Low Latency Stochastic Square Root Circuit
Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors
Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack
High-Level Synthesis with SIMD Units
Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography
A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs
Use of Storage Elements as Primitives for Modelling Faults in Synchronous Sequential Circuits
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA
Synthesis of Self-Checking Sequential Machines Using Cellular Automata
SHIRT (Self Healing Intelligent Real Time) Scheduling for Secure Embedded Task Processing
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations
A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display Applications
Designing Hash and Encryption Engines using Quantum Computing
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs
Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring
Extending Action Recognition in the Compressed Domain
On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology
A New Approach for CMOS Op-Amp Synthesis
Embedded Tutorial ET2: Digital Subscriber Line
On the Impact of Address Space Assignment on Performance in Systems-on-Chip