yusuke1997/dblp-id-title huggingface dataset:
Embedded processors based on Spin Wave Functions (SPWFs)
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017
Architecting 3-D integrated circuit fabric with intrinsic thermal management features
Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions
Nanowire field-programmable computing platform
Commutative Approximate Adders: Analysis and Evaluation
A hybrid memory cell using Single-Electron transfer
Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells
Analog-to-stochastic converter using magnetic-tunnel junction devices
Ambipolar circuits for analog, mixed-signal, and radio-frequency applications
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
A fast, numerical circuit-level model of carbon nanotube transistor
Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds
CryptoLight: An Electro-Optical Accelerator for Fully Homomorphic Encryption
REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning
Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning
Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arrays
Defect tolerance in QCA-based PLAs
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS)
A memristor-based compressive sensing architecture
Regular 2D NASIC-based architecture and design space exploration
Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Quantum-dot Cellular Automata RAM design using Crossbar Architecture
Design automation for hybrid CMOS-nonoelectronics crossbars
Fast march tests for defects in resistive memory
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Dynamically Configurable Physical Unclonable Function based on RRAM Crossbar
Cryogenic In-MRAM Computing
Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells
Exploiting the Third Dimension: Stackable Quantum-dot Cellular Automata
Novel MTJ-based shift register for non-volatile logic applications
MRAM-based logic array for large-scale non-volatile logic-in-memory applications
Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect
Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars
Stigmergic search with single electron tunneling technology based memory enhanced hubs
3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015
Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric
Spin wave functions nanofabric update
Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS
System-level energy and performance projections for nanomagnet-based logic
Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication
Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories
Hardware Efficiency Stochastic Computing based on Hybrid Spatial Coding
On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Compact modeling and corner analysis of spintronic memristor
A compare-and-select error tolerant scheme for nonvolatile processors
An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
Inexact computing for ultra low-power nanometer digital circuit design
A cellular architecture for self-assembled 3D computational devices
Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
A new Tunnel-FET based RAM concept for ultra-low power applications
Reconfigurable Approximate Multiplication Architecture for CNN-Based Speech Recognition Using Wallace Tree Tensor Multiplier Unit
Post-Layout Optimization for Field-coupled Nanotechnologies
Sleep stage classification with stochastic Bayesian inference
Fault modeling for FinFET circuits
Circuit Optimization Techniques for Efficient Ex-Situ Training of Robust Memristor Based Liquid State Machine
Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme
Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array
HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM
A pseudo-weighted sensing scheme for memristor based cross-point memory
Fine-grained 3-D CMOS concept using stacked horizontal nanowire
Hybrid neural network using binary RRAM devices
Wave-based device scaling concept for brain-like energy efficiency and integration
Hysteresis-free carbon nanotube field-effect transistors without passivation
Impact of PCM resistance-drift in neuromorphic systems and drift-mitigation strategy
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars
Computation-in-memory based parallel adder
Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing
Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing
Design and comparison of NML systolic architectures
A Novel Programmable Variation-Tolerant RRAM-based Delay Element Circuit
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, The Netherlands, July 4-6, 2012
Robust neural logic block (NLB) based on memristor crossbar array
A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor
A tunable cache for approximate computing
Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators
A compact model of stochastic switching in STT magnetic RAM for memory and computing
Computing with nanoscale memory: Model and architecture
Design-for-Test method for high-speed ADCs: Behavioral description and optimization
New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits
A low power input amplifier for bio-signal acquisition in 28 nm FDSOI technology
Self-managing power management unit
Dynamic placement applications into Self Adaptive network on FPGA
Simulation and planning method for on-chip power distribution - An industry perspective
Analyzing and Optimizing the Dummy Rounds Scheme
A software-based self-test and hardware reconfiguration solution for VLIW processors
Behavior of CMOS polymorphic circuits in high temperature environment
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic
A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010
New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams
Direct Test Methodology for HDL Verification
Design of an S-band 0.35 µm AlGaN/GaN LNA using cascode topology
The HDL and FE Thermal Modeling of Heterogeneous Systems
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors
Combining fault tolerance and self repair at minimum cost in power and hardware
Non-disjoint decomposition of logic functions in Reed-Muller spectral domain
Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application
IP Integration Overhead Analysis in System-on-Chip Video Encoder
An on-line testing scheme for repairing purposes in Flash memories
Clockless Implementation of LEON2 for Low-Power Applications
Designing Time-to-Digital Converter for Asynchronous ADCs
Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip
Towards approximation during test of Integrated Circuits
Characterization of digital cells for statistical test
Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing
New Solutions for the Support Region Calculation of Logarithmic Quantizers for the Laplacian Source
Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI's Components using RAD-THERM TCAD Subsystem
Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults
Manifestation of Precharge Faults in High Speed DRAM Devices
Containment of Metastable Voltages in FPGAs
Towards an unified IP verification and robustness analysis platform
A fault injection platform for the analysis of soft error effects in FPGA soft processors
Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair
Future of EDA: Usual suspect or silent hero for successful semiconductor business?
Standard Cell Tuning Enables Data-Independent Static Power Consumption
HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing
Synaptic Control for Hardware Implementation of Spike Timing Dependent Plasticity
On the Use of Information Redundancy When Designing Secure Chips
CAD tool for PLL Design
Open Automation Framework for Complex Parametric Electrical Simulations
Hybrid Mesh-Ring wireless NoC for multi-core system
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults
An Integrated Phase Shifting Frequency Synthesizer for Active Electronically Scanned Arrays
Test data compression based on reuse and bit-flipping of parts of dictionary entries
Modeling and Accelerated Mixed-Signal Simulation of a Control System
Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier
DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development
A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs
A hardware accelerated framework for the generation of design validation programs for SMT processors
Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation
Modeling CMOS Gates Using Equivalent Inverters
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
Built-in self-repair architecture generator for digital cores
FPGA-controlled PCBA power-on self-test using processor's debug features
Wrapper design for a CDMA bus in SOC
An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores
Parts Obsolescence Challenges for the Electronics Industry
Reliability challenges in avionics due to silicon aging
Synthesis of Finite State Machines on Memristor Crossbars
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
Optimization of message encryption for distributed embedded systems with real-time constraints
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories
Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks
Fault injection analysis of transient faults in clustered VLIW processors
Test Scheduling for SoC under Power Constraints
System side-channel leakage emulation for HW/SW security coverification of MPSoCs
Ensuring high testability without degrading security: Embedded tutorial on "test and security"
Precision human body temperature measurement based on thermistor sensor
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells
Correlation Power Analysis of SipHash
FPGA based time-of-flight 3D camera characterization system
A novel architecture for LZSS compression of configuration bitstreams within FPGA
Multiobjective evolution of approximate multiple constant multipliers
Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies
A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters
The Wall Ahead is Made of Rubber
Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design
A System-On-Chip for Wireless Body Area Sensor Network Node
New categories of Safe Faults in a processor-based Embedded System
SHiLA: Synthesizing High-Level Assertions for High-Speed Validation of High-Level Designs
Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators
Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip
Low-Area and High-Speed Approximate Matrix-Vector Multiplier
Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock
Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching
CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution
Modular Data Link Layer Processing for THz communication
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network
Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS
Hardware solution of chaos based image encryption
Debug Patterns for Efficient High-level SystemC Debugging
Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques
Vertical Slit Transistor based Integrated Circuits (VeSTICs)
Network Probe for Flexible Flow Monitoring
Excitation optimization in fault diagnosis of analog electronic circuits
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit
MEMS Testing by Vibrating Capacitor
Optimized embedded memory diagnosis
Layout to Logic Defect Analysis for Hierarchical Test Generation
Functional enhancements of TMR for power efficient and error resilient ASIC designs
Comparing Subtraction-Free and Traditional AMI
Parameterized Critical Path Selection for Delay Fault Testing
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
Accurately Determining Bridging Defects from Layout
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation
Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit
Developing Virtual ADC Testing Environment in MAPLE
LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs
CMOS Testing at the End of the Roadmap: Challenges and Opportunities
27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, DDECS 2024, Kielce, Poland, April 3-5, 2024
Decomposition of Logic Functions in Reed-Muller Spectral Domain
A novel impedance calculation method and its time efficiency evaluation
Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform
FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization
A tunable bandwidth 6th-order active low-pass filter in 0.18 um CMOS technology
Precise IPv4/IPv6 packet generator based on NetCOPE platform
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations
Differential evolutionary optimization algorithm applied to ESD MOSFET model fitting problem
25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022
Energy-Efficient Neural Network Inference through Golomb-Rice Compression of Activations for Edge Devices
Effective hash-based IPv6 longest prefix match
Implementation of Selective Fault Tolerance with conventional synthesis tools
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories
AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages
A Leakage-based Random Bit Generator with On-line Fault Detection
Instruction reliability analysis for embedded processors
Contactless characterization of MEMS devices using optical microscopy
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs
Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology
About the Efficiency of Real Time Sequences FFT Computing
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit
Parity Waterfall method
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC
Verifying robust frequency domain properties of non linear oscillators using SMT
Deep-Submicron MOS Transistor Matching: A Case Study
An evaluation of the application dependent FPGA test method
Test pattern generation for the combinational representation of asynchronous circuits
Stacking order impact on overall 3D die-to-wafer Stacked-IC cost
Modeling and observing the jitter in ring oscillators implemented in FPGAs
Evaluation of the Iddq Signature in devices with Gauss-distributed background current
Hexapod robotic system for indoor neutron and gamma radiation mapping and inspection
A scheme of logic self repair including local interconnects
Low power scan by partitioning and scan hold
From Constraints to Tape-Out: Towards a Continuous AMS Design Flow
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression
A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units
Analysis of the influence of intermittent faults in a microcontroller
High-performance hardware accelerators for sorting and managing priorities
Hardware implementation of a medium access control layer for industrial wireless LAN
LEON-2: General Purpose Processor for a Wireless Engine
An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations
Logic testing with test-per-clock pattern loading and improved diagnostic abilities
A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication
Dual use of power lines for data communications in microprocessors
A chaotically injected timing technique for ring-based oscillators
Comparison of jitter decomposition methods for BER analysis of high-speed serial links
Fast Boolean Minimizer for Completely Specified Functions
A Design of Ring Oscillator Based PUF on FPGA
Stratified sampling: fast estimation of quantization effects on DNN
Structural test of programmed FPGA circuits
Controllability-Based Circuit Similarity Estimation
Effective BIST for crosstalk faults in interconnects
Novel Hardware Implementation of Adaptive Median Filters
Test and diagnosis of power switches
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A fast untestability proof for SAT-based ATPG
Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies
Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language
A study on fast pipelined pseudo-random number generator based on chaotic logistic map
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
PolyAdd: Polynomial Formal Verification of Adder Circuits
SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores
Automated Integration of Dynamic Power Management into FPGA-Based Design
Receiver synchronization in video streaming with short latency over asynchronous networks
A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability
A new method for path criticality calculation
A user-level library for fault tolerance on shared memory multicore systems
A 120V high voltage DAC array for a tunable antenna in communication system
Recognition of DRM Signal in Frequency Domain and Hardware Demands
Generic built-in self-repair architectures for SoC logic cores
Diagnosis of faulty units in regular graphs under the PMC model
Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems
IoT Based Occupancy Detection System with Data Stream Processing and Artificial Neural Networks
Design Flow for Radhard TMR Flip-Flops
Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator
A Switch Supporting Circuit and Packet Switching for On-Chip Networks
Using 3-valued memory representation for state space reduction in embedded assembly code model checking
A Novel Parity Bit Scheme for SBox in AES Circuits
TLM protocol compliance checking at the Electronic System Level
Error resilient OBDDs
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs
Comprehensive bridging fault diagnosis based on the SLAT paradigm
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems
Constant Voltage Maximum Power Point Tracking Method for Fully Integrated Solar-Powered Energy Harvester
An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets
Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology
Programmable logic elements using multigate ambipolar transistors
Challenges for test and design for test
A low-overhead monitoring ring interconnect for MPSoC parameter optimization
The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS
Temperature and on-chip crosstalk measurement using ring oscillators in FPGA
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures
Application of IDDT test towards increasing SRAM reliability in nanometer technologies
Window optimization of reversible and quantum circuits
Automatic property generation for the formal verification of bus bridges
Augmenting All Solution SAT Solving for Circuits with Structural Information
Hardware Acceleration of FHEW
Mont-Blanc 2020: Simulation Efforts Towards Exascale High Performance Computing : Embedded Tutorial on "DDECS-2020"
Low latency book handling in FPGA for high frequency trading
Self-timed thermal sensing and monitoring of multicore systems
High Throughput Floating-Point Dividers Implemented in FPGA
Analysis and comparison of functional verification and ATPG for testing design reliability
Fault Tolerant Synchronous Multi-Channel Buck Converter for Nuclear Inspection Instruments
A Multi-Credit Flow Control scheme for asynchronous NoCs
Current Sensing Completion Detection in deep sub-micron technologies
NAND/NOR gate polymorphism in low temperature environment
Exploiting PUF Variation to Detect Fault Injection Attacks
Heap Queue: A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems
How to Improve a Set of Design Validation Data by Using Mutation-based Test
Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation