yusuke1997/dblp-id-title huggingface dataset:
LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments
Cati - An Open-Source Framework to Evaluate Attacks on Cameras for Autonomous Vehicles
Projected Don't Cares
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation
GCells: A Graph-Search Approach to Design Custom Cells for Computational Subsystems
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits
Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary Translation
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection
Synthesis of Multipurpose Reversible Logic Gates
Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip
ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm
ASAM: Automatic Architecture Synthesis and Application Mapping
SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology
Enhancing the Simulation-Centric Design of Cyber-Physical and Multi-physics Systems through Co-simulation
Modeling RISC-V Processor in IP-XACT
Decoupling of Computation and Communication with a Communication Assist
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications
High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA
Sense and Control of Oscillating MEMS Mirrors
QEMU-Based Fault Injection for a System-Level Analysis of Software Countermeasures Against Fault Attacks
Accelerating Volume Image Registration through Correlation Ratio Based Methods on GPUs
Enabling Smart Urban Mobility with Edge AI
Account for Radiation Effects in Signal Integrity Analysis of PCB Digital Systems
On Projecting Sums of Products
Activity Migration in M-of-N-Systems by Means of Load-Balancing
Data Flow Analysis of Software Executed by Unreliable Hardware
Enhanced Quality Using Intensive Test and Analysis on Simulators
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber
AHEMS: Asynchronous Hardware-Enforced Memory Safety
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards
Dependability Evaluation of Real Railway Interlocking Device
Scene Management Models and Overlap Tests for Tile-Based Rendering
Managing the Resource Continuum in a Real Video Surveillance Scenario
Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources
High Performance Image Processing on a Massively Parallel Processor Array
Optimising Quality-of-Control for Data-Intensive Multiprocessor Image-Based Control Systems Considering Workload Variations
Cone of Influence Analysis at the Electronic System Level Using Machine Learning
Fault Models and Injection Strategies in SystemC Specifications
A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions
Reconfigurable Computing at Xilinx
A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography
An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems
Segmentation of Hyperspectral Images Using Quantized Convolutional Neural Networks
Coded Modulation Simulation Framework for Time-of-Flight Cameras
Constant Coefficient Convolution Implemented in FPGAs
T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties
Layered Decoding of Non-Layered LDPC Codes
The AXIOM Software Layers
A Novel Authenticated Encryption Algorithm for RFID Systems
Design and Implementation of a Low-Power, Embedded CNN Accelerator on a Low-end FPGA
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins
A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems
Toward unsupervised Human Activity Recognition on Microcontroller Units
On-Line Device Replacement Techniques for SSD RAID
Implementation of a Boolean Masking Scheme for the SCREAM Cipher
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits
LEON3 ViP: A Virtual Platform with Fault Injection Capabilities
Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
Low-power Branch Target Buffer for Application-Specific Embedded Processors
Novel Controller for Dummy Rounds Scheme DPA Countermeasure
An Efficient FPGA-Based Architecture of Skein for Simple Hashing and MAC Function
Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS Circuits
Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks
Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia
Automatic and Unsupervised Identification of Specific Biochemical Features from Raman Mapping Data
An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion
Towards Formalization of Enhanced Privacy ID (EPID)-based Remote Attestation in Intel SGX
Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study
Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems
Synchronizing a High-Speed SIMD Processor Array
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
Application of Decision-Making Method for Architecture Selection of ADSL Modem
Hardware Generators with Chisel
Flexible OFDM Waveform for PLC/RF In-Vehicle Communications
Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures
Synchronisation of a Multimodal Sensing Setup for Analysis of Conservatory Pianists
A Hybrid Scheduling Mechanism for Multi-programming in Mixed-Criticality Systems
Development of a Hyperspectral Colposcope for Early Detection and Assessment of Cervical Dysplasia
State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System
Multiprotocol Middleware Translator for IoT
ARTS: An adaptive regularization training schedule for activation sparsity exploration
Faster Processor Allocation Algorithms for Mesh-Connected CMPs
An Efficient Method to Reliable Data Transmission in Network-on-Chips
Streaming Reduction Circuit
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration
HOG Feature Extractor Hardware Accelerator for Real-Time Pedestrian Detection
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
DSEParted: Co-Optimization of Embedded NPU Architectures and Neural Network Partitioning
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC
Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight Cameras
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits
SEAMLESS Project: Development of a Performing Secure Platform for IEEE 802.15.4 WSN Applications
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor
A Probabilistic Context-Free Grammar Based Random Test Program Generation
An Energy-Efficient Reconfigurable NoC Architecture with RF-Interconnects
Intrusion Detection for SOME/IP: Challenges and Opportunities
A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits
Abstract Application Modeling for System Design Space Exploration
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation
LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries
AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs
Multi-sensor Energy Efficient Obstacle Detection
Dataflow-Based Multi-ASIP Platform Approach for Digital Control Applications
Glitch Happens: Attacking the AMD-Xilinx PLL with a Clock Glitch Generator
A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length Partitioning
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation
CoFELS: Conceptual Framework for Electricity Load Shifting System Design
A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms
Suit up! - Made-to-Measure Hardware Implementations of ASCON
Formal Modeling of Multicast Communication in 3D NoCs
11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008
Architecture Exploration of 3D Video Recorder Using Virtual Platform Models
Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
A processor for testing mixed-signal cores in System-on-Chip
An Architecture for Online-Diagnosis Systems Supporting Compressed Communication
A Software Stack for Next-Generation Automotive Systems on Many-Core Heterogeneous Platforms
An Improved Automotive Multiple Target Tracking System Design
Event-Based Vision on FPGAs - a Survey
Device Driver and System Call Isolation in Embedded Devices
Path-Delay Fault Testing in Embedded Content Addressable Memories
Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems
Programmable Systems for Intelligence in Automobiles (PRYSTINE): Technical Progress after Year 2
Synthesizing Reversible Circuits for Irreversible Functions
Long Term Trends for Embedded System Design
Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models
Run-Time Effect by Inserting Hardware Trojans, in Combinational Circuits
Leveraging Domain Knowledge for the Efficient Design-Space Exploration of Advanced Cyber-Physical Systems
Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance
Online Protocol Testing for FPGA Based Fault Tolerant Systems
Many-Core Scheduling of Data Parallel Applications Using SMT Solvers
Timing Driven Wiring on an Advanced Microprocessor
Evaluating the Hardware Performance of a Million-Bit Multiplier
Building Distributed Co-Simulations Using CoHLA
Integrating a Computational Model and a Run Time System for Image Processing on a UAV
REBECCA: Reconfigurable Heterogeneous Highly Parallel Processing Platform for Safe and Secure AI
Leveraging Data Promotion for Low Power D-NUCA Caches
Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments
High-Performance Floating Point Divide
Static Average Case Power Estimation Technique for Block Ciphers
Streaming consistency: a model for efficient MPSoC design
A Fast and Well-Structured Multiplier
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults
Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition
Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes
Multi-granular Arithmetic in a Coarse-Grain Reconfigurable Architecture
The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OS
A Formal Condition to Stop an Incremental Automatic Functional Diagnosis
Intelligent Security Measures for Smart Cyber Physical Systems
Using SystemC Cyber Models in an FMI Co-Simulation Environment: Results and Proposed FMI Enhancements
Hardware Virtual Components Compliant with Communication System Standards
Search Strategy of Large Nonlinear Block Codes
Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
A Common Operator for FFT and Viterbi Algorithms
Algebraic Cryptanalysis of Small-Scale Variants of the Bluetooth Stream Cipher E0
Testing for Intermittent Resistive Faults in CMOS Integrated Systems
Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC
Euromicro Conference on Digital System Design, DSD 2017, Vienna, Austria, August 30 - Sept. 1, 2017
D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop
BIST Technique for GALS Systems
Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors
Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs
Towards Hardware Support for FPGA Resource Elasticity
A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges
Models and Tradeoffs in WSN System-Level Design
FATTY: A Reliable FAT File System
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
Key Enabling Technologies for Drones
Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding
The H2020-ECSEL Project "iRel40" (Intelligent Reliability 4.0)
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm
Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip
GPU4S: Embedded GPUs in Space
Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes
A Variable Length Vector Pipeline Architecture Design Methodology
Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines
X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems
Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC
Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any Overhead
Optimising Self-Timed FPGA Circuits
Enhanced Metastability Characterization Based on AC Analysis
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm
A Case for Hardware Task Management Support for the StarSS Programming Model
Wireless Sensor Systems - Constraints and Opportunities
Radar-Based Human Activity Acquisition, Classification and Recognition Towards Elderly Fall Prediction
Phased Array and Adaptive Antenna Transceivers in Wireless Sensor Networks
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms
Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform
Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism
PtNBridge - A Power-Aware and Trustworthy Near Field Communication Bridge to Embedded Systems
Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri net
Reliable and Continuous Measurement of SET Pulse Widths
Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach
Design Space Exploration in an FPGA-Based Software Defined Radio
The AirSpeck Family of Static and Mobile Wireless Air Quality Monitors
A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits
Identifying NBTI-Critical Paths in Nanoscale Logic
Toggle Equivalence Preserving (TEP) Logic Optimization
An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs
Spatial Correlation in Weak Physical Unclonable Functions: A Comprehensive Overview
PoLibSi: Path Towards Intrinsically Reconfigurable Components
Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques
Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation
Electromagnetic Leakage Assessment of a Proven Higher-Order Masking of AES S-Box
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding
A Novel Real-Time Framework for Embedded Systems Health Monitoring
Designing Energy-Efficient Approximate Circuits for the FPGA Technology
Back-Traced Deductive-Parallel Fault Simulation for Digital Systems
On Modeling and Evaluation of Logic Circuits under Timing Variations
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip
An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design
Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing Units
Automated Design Debugging in a Testbench-Based Verification Environment
Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks
Towards Efficient Field Programmable Pattern Matching Array
An Evaluation of an FPGA Run-Time Support System
Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation
Evaluation of artificial neural networks for the detection of esophagus tumor cells in microscopic hyperspectral images
Fast Heuristics for the Edge Coloring of Large Graphs
Deterministic Search Strategy of Compression Codes
Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers
Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation
A Programmable SoC Implementation of the DGK Cryptosystem for Privacy-Enhancing Technologies
The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data
Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia Application
P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications
A Formal Model for Optimal Autonomous Task Hibernation in Constrained Embedded Systems
Design of Trace-Based Split Array Caches for Embedded Applications
Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18
Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study
HEAP: A Highly Efficient Adaptive Multi-processor Framework
A New High-Level Methodology for Programming FPGA-Based Smart Camera
Assuring the Safety of End-to-End Learning-Based Autonomous Driving through Runtime Monitoring
Efficient and Exact Design Space Exploration for Heterogeneous and Multi-Bus Platforms
Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology
SlideAcross: A Low-Latency Adaptive Router for Chip Multi-processor
Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC
An SoC FPGA-based Integrated Real-time Image Processor for Uncooled Infrared Focal Plane Array
SoC and Board Modeling for Processor-Centric Board Testing
Enabling Fail-Operational Behavior and Degradation for Safety-Critical Automotive 3D Flash LiDAR Systems
Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection
Boolean Difference Based Reliability Evaluation of Fault-Tolerant Circuit Structures on FPGAs
Integration of Instruction Set Simulators into SystemC High Level Models
Automatic Identification of Parallelism in Handel-C
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing
CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores
Stochastic Reconfigurable Hardware for Neural Networks
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables
A Reliable Statistical Analysis of the Best-Fit Distribution for High Execution Times
A Methodology for Designing Communication Architectures for Multiprocessor SoCs
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures
A Method to Construct Efficient Carbon-Nanotube-Based Physical Unclonable Functions and True Random Number Generators
Design and Implementation of a 90nm Low bit-rate Image Compression Core
Understanding Video Pixel Processing Applications for Flexible Implementations
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units
Hybrid Quantum-secure Group-based Communication with PQC and QKD
Hardware-Software Codesign of a CNN Accelerator
Targeting different defect-oriented fault models in IC testing: an experimental approach
Multi-Pipeline Implementations of Real-Time Vector DFT
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems
HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions
Integration of the TPM in the AACKA Protocol
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs
Analysis of Variable Reordering on the QMDD Representation of Quantum Circuits
A Multiuser FBMC Receiver Implementation for Asynchronous Frequency Division Multiple Access
A Configurable Test-Processor for Board-Level Testing
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops
Parallel Deadlock Detection and Recovery for Networks-on-Chip Dedicated to Diffused Computations
High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing
ST-HAR: A Single Stretchable Sensor Dataset for Human Activity Recognition
Quantization of Constrained Processor Data Paths Applied to Convolutional Neural Networks
A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-core Platforms
Eccentric SoC Architectures as the Future Norm
Application Specific Instruction Set Processor for Adaptive Video Motion Estimation
Partial Evaluation in Junction Trees
Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications
Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design
Simulation and SAT Based ATPG for Compressed Test Generation
Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling Techniques
HS2RGB: an Encoder Approach to Transform Hyper-Spectral Images to Enriched RGB Images
Evaluating Convolutional Neural Networks Reliability depending on their Data Representation
An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures
Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy Coder
Hardware Implementation of a Memory Allocator
Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors
Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors
A Novel Intra Prediction Architecture for the Hardware HEVC Encoder
FPGA-Based Real-Time Laser Beam Profiling and Stabilization System for Quantum Simulation Applications
Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGA
Applying Caching to Two-Level Adaptive Branch Prediction
Multiple Bit Error Detection and Correction in Memory
A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing
TraceFormer: A Transformer-Based Method for Weight Extraction from AIMC Tiles
Towards New Real-Time Processor: The Multioperand MSB-First Real-Time Adder
Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks
Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design