yusuke1997/dblp-id-title huggingface dataset:
Chitosan Polymeric Micelles for Prevention of Cisplatin-Induced Nephrotoxicity and Anticancer Activity of Cisplatin
Selection of a Nanobody Specific to Human Interferon-Inducible Protein 10 (IP-10) Using a Combination of Phage Display and the FLI-TRAP Technique
A Finite Element Study of the Universality and Scalability of an Optimized Universal Talus Implant
Fear-related Visual Information Transfer Characteristics of the Lateral Posterior Thalamic Nucleus
Two-Dimensional Simulation of Blood Flow in Thoracic Aorta
Pneumonia Diagnosis Using Chest X-ray Images and Machine Learning
Footprint Biometrics on Person Identification Using CNN Algorithm
Dynamic Blood Oxygen Saturation Monitoring based on a New IPPG Detecting Device
Application of Reflectance Mode Photoplethysmography for Non-Invasive Monitoring of Blood Glucose Level with Moving Average Filter
Study on Stress Resistance of n-Hexadecane Degrading Bacteria under High Salt Stress
Measurement of Specific Gravity, Urobilinogen, Blood, Protein and pH Level of Urine Samples Using Raspberry Pi based Portable Urine Test Strip Analyzer
Detection of Entamoeba Histolytica using Canny Edge Detection and Watershed Transform
Vision-based Pill Blister Package Inspection System using CNN
Biodegradation of n-Hexadecane by P. Aeruginosa with Treatment of Rhamnolipid Bio-Surfactant
A Simulation Study to Locate Cervical Abnormality based on Electrical Impedance Tomography (EIT), using a Planar Nine-Electrode Probe
Portable Nuclear and Cortical Eye Cataract Detection using Image Processing
The Role of Estrogen in Bone Turnover with Aging and Age-related Osteoporosis
Review on Marine Biotoxins Toxicity and Detection Methods
Design of Embedded System for Electrochemical Immunosensor Using NI myRIO
Investigation of Anti Cancer Proliferation Properties of Luffa Acutangula on Ht29 Using Electroporation Method
Planar Electrode Configurations of Electrode Plates for the Localization of Cervical Abnormality based on Electrical Impedance Tomography (EIT) - A Simulation Study
Investigation of In-body to Off-Body Wireless Telemetry Performance Considering Respiration-induced Organ Movements for Transplanted Organ Monitoring
Multi-Layer Dense Attention Decoder for Polyp Segmentation
An Integreated Method for Mass Spectrometry-based proteomics analysis of Single Cell by using online sample preparation on a monolithic column
Microbial Degradation Kinetics of Polyphenanthrene Phenanthrene
Ultrasound Median Nerve Image Instance Segmentation via Nesting Attention and Boundary-guided Segmentation Mechanism
Microscopic Image Analysis and Counting of Red Blood Cells and White Blood Cells in a Urine Sample
Automatic Detection of Circulating Tumor Cells with Very Deep Residual Networks
Determination of Ripening Stages and Nutritional Content of Tomatoes Using Color Space Conversion Algorithm, Processed Through Raspberry Pi
Word Translation of Filipino Sign Language Under Various Backgrounds
Characterizing morphology and membrane proteins on ER and endosomes with cryoET
Session 22 - Oversampling data converters
BAG: A Process-Portable Framework for Generator-based AMS Circuit Design
A 96.1% Efficiency 48V-to-IBV GaN Power Converter with Full-Wave Temperature-Compensated Current Sensing and Adaptive Slope Emulation Achieving 4.3% Full-Temperature Sensing Error for AI Data Center Applications
A compact, high linearity 40GS/s track-and-hold amplifier in 90nm SiGe technology
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS
On-Chip Circuit Harness Enabling Probe-Less, Position-Invariant and Massive Testing of Chiplets via Die Front/Back-Side Capacitive Coupling
Design of low-noise CMOS MEMS accelerometer with techniques for thermal stability and stable DC biasing
An mm-Wave Synthesizer with Low In-Band Noise and Robust Locking Reference-Sampling PLL
High speed pipelined ADCs: Fundamentals and variants
Amorphous silicon 5 bit flash analog to digital converter
An IF CMOS signal component separator chip for LINC transmitters
A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection
Switched-Capacitor Circuits
Heterogeneous multicore SoC for secure multimedia applications
A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A
Multi-functional Monolithic-MEMS Tactile Imager Using Flexible Deformation of Silicon IC
8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3 rd order, 3/5-bit IIR and 3 rd order 3-bit-FIR noise shapers in 90nm CMOS
The architecture of dual-mode FPGA embedded system blocks
Noise and bandwidth performance of single-molecule biosensors
Enhancing Productivity by Continuously Improving Standard Compact Models
A bidirectional lens-free digital-bits-in/-out 0.57mm 2 terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication
Session 17 - Clocking circuits
A dynamic offset control technique for comparator design in scaled CMOS technology
A mm-Wave Blocker-Tolerant Harmonic-Resilient N-Path Mixer-First Receiver with 6.2 dB NF and 5 dBm OOB-B1dB
Quadratic differential and integration technique in V 2 control buck converter with small ESR capacitor
A Low Jitter Multi-Phase PLL with Capacitive Coupling
A 334-to-348-GHz 7×2 Radiator Array with Coupled-Line-Based Mode-Decoupling Harmonic Enhancement and Chip-to-Waveguide Interface Achieving 30-dBm EIRP
Enhanced analytic noise model for RF CMOS design
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS
A low power PSK receiver for space applications in 0.35-μm SOI CMOS
A 65 mW, 0.4-2.3 GHz bandpass filter for satellite receivers
A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs
A new design for complete on-chip ESD protection
A simple algorithm for calculating frequency-dependent inductance bounds
A 28nm 157TOPS/W 446.9Kb/mm 2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs
A voltage doubling passive rectifier/regulator circuit for biomedical implants
A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network
A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvesting
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider
A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique
IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings
A 52-to-73GHz Tri-Coupled Transformer Based Noise Self-Canceling and Gm-Boosting LNA with 3.78dB NF and 22.4dB Gain in 40nm CMOS
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage
An AC-coupled stacked dual active bridge hybrid DC-DC converter for battery-to-processor power delivery with 87.2% peak efficiency and high accuracy loadline regulation
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells
A 11 pA/√Hz TIA with +15dB input OMA Range for 112Gb/s PAM4 Optical Links in 22nm FDSOI
A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC
Analog techniques I
Sub-sampling sigma-delta modulator for baseband processing
A 300 K-gate 0.5 μm CMOS implementation of an 8-VSB receiver IC [for HDTV]
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time
A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation
Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widths
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS
Wireless interconnection within a hybrid engine controller board
Keynote speaker: Massive MIMO active antenna arrays for advanced wireless communications
Leakage power analysis of a 90nm FPGA
A new receiver architecture for multiple-antenna systems
A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization
Session 18 - Millimeter-wave circuit techniques
22-30GHz Quadrature Hybrid SCPA with LO Leakage Self-Suppression and Distributed Parasitic-Cancelling Sub-PA Array for Linearity and Efficiency Enhancement
An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32, 8, 10) LDPC code
Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications
A Low-Power 20Gb/s 196GHz BPSK Wireless Transmitter with Energy Efficiency FoM of 0.15pJ/bit/cm
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS
A 104dB SNDR Transimpedance-based CMOS ASIC for Tuning Fork Microgyroscopes
IC Design After Moore's Law
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology
An integrated four-phase buck converter delivering 1A/mm 2 with 700ps controller delay and network-on-chip load in 45-nm SOI
A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration
A CMOS two-path tree search detector
A Ku-band monolithic tuner-LNB for satellite applications [low noise block down-converter]
MDSP-II: 16-bit DSP with mobile communication accelerator
Varactor-based signal restoration for near-speed-of-light surfing global interconnect
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004
Energy-performance tunable logic
A 2.125 Gbaud 1.6 kΩ transimpedance preamplifier in 0.5 μm CMOS
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS
Shared data line technique for doubling the data transfer rate per pin of differential interfaces
A ROM compression method for continuous data
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking
A new CMOS image sensor readout structure for 3D integrated imagers
A Low-Power and low-noise 21∼29 GHz ultra-wideband receiver front-end in 0.18 µm CMOS technology
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces
Low-Jitter Active Deskewing Through Injection-Locked Resonant Clocking
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS
Modeling of monolithic lumped planar transformers up to 20 GHz
A subharmonically-injected quadrature LO generator for 17GHz WLAN applications
BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS
Noise and reliability containment approaches
A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control
iMCU: A 102-μJ, 61-ms Digital In-Memory Computingbased Microcontroller Unit for Edge TinyML
A Closed-Loop Brain-Machine Interface SoC Featuring a 0.2μJ/class Multiplexer Based Neural Network
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS
A completely integrated 2 GHz VCO with post-processed Cu inductors
Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique
A 6.3pJ/b 30Mbps -30dB SIR-tolerant broadband interference-robust human body communication transceiver using time domain signal-interference separation
A 1.6mm 3 Wirelessly Powered Reconfigurable FDD Radio with On-Chip Antennas Achieving 4.7 pJ/b TX and 1 pJ/b RX Energy Efficiencies for Medical Implants
5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM
Independent N and P process monitors for body bias based process corner correction
A configurable 5.9 μW analog front-end for biosignal acquisition
A XiRisc-based SoC for embedded DSP applications
A capacitor-based AC-DC step-up converter for biomedical implants
Built-in resistance compensation (BRC) technique for fast charging Li-Ion battery charger
Modified mismatch-shaping for continuous-time delta-sigma modulators
A study of injection pulling and locking in oscillators
Watermarking-based copyright protection of sequential functions
Artificial intelligence meets large-scale sensing: Using Large-Area Electronics (LAE) to enable intelligent spaces
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques
A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier
A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control
All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS
A 78%-efficiency li-ion-compatible fully-integrated modified 4-level converter with 0.01-40mW DCM-operation in 28nm FDSOI
High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety
60GHz CMOS/PCB co-design and phased array technology
ST-MRAM fundamentals, challenges, and applications
A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology
Power management
Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor
Testing SerDes beyond 4 Gbps - changing priorities
A 32-Gb/s 9.3-mW CMOS equalizer with 0.73-V supply
A 1V downconversion filter using duty-cycle controlled bandwidth tuning
An Integrated Readout Circuit for a Transcutaneous Oxygen Sensing Wearable Device
A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA
Towards one chip HDTV MPEG2 encoder LSI
CMOS-Based MEMS Mirror Driver for Maskless Lithography Systems
Twisted inductors for low coupling mixed-signal and RF applications
A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systems
Wide Lock-Range, Low Phase-Noise PLL using Interpolative Ring-VCO with Coarse Frequency Tuning and Frequency Linearization
Fast and accurate event-driven simulation of mixed-signal systems with data supplementation
A 69MHz-Bandwidth 40V/μs-Slew-rate 3nV/√Hz-Noises 4.5μV-Offset Chopper Operational Amplifier
Fully Integrated Solutions for High Resolution Terahertz Imaging (Invited)
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs
A 135GHz SiGe transmitter with a dielectric rod antenna-in-package for high EIRP/channel arrays
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory
Specialty Foundry technology and design enablement for RF, high performance analog, and power
A Wireless Subdural Optical Cortical Interface Device with 768 Co-Packaged Micro-LEDs for Fluorescence Imaging and Optogenetic Stimulation
A 4-15-GHz ring oscillator based injection-locked frequency multiplier with built-in harmonic generation
A low-supply PLL with Enhanced Cascode Compensation and a low-supply-sensitivity CCO
Phase noise in multi-gigahertz CMOS ring oscillators
An 81.7M Ω-lnput-lmpedance 179.5dB-FOMSNDR 1.8Vpp-lnput-Range Noise-Shaping-SAR-Based Sensing Frontend with Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping-DEM
Improving embedded software design and integration in SOCs
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm 2 per MB
A Zero-Voltage-Switching Buck Converter with Conduction-Loss-Minimized ZVS Operation and Auxiliary Inductor Transient Reuse Technique Achieving up to 8.3% Efficiency Improvement and 42% Voltage Droop Reduction
Wireless synchronization of mm-wave arrays in 65nm CMOS
A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery
Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface
A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter
Long, Short, Monolithic - The Gate Loop Challenge for GaN Drivers: Invited Paper
A 103.6dB-SNDR 760mVPP-Input-Range 7.8GΩ-Input-Impedance Direct-Digitization Sensor Readout with Pseudo-Differential Transconductors and Dummy DAC
Infrastructure for modular SOC testing
A novel high-performance predictable circuit architecture for the deep sub-micron era
Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform
56G/112G Link Foundations Standards, Link Budgets & Models
Fully-Integrated CMOS Power Regulator for Telemetry-Powered Implantable Biomedical Microsystems
A 1/3" VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervals
MEMS, biomedicals, and sensors
A 256x256 6.3pJ/pixel-event Query-driven Dynamic Vision Sensor with Energy-conserving Row-parallel Event Scanning
A 73.3% Peak Efficiency Isolated DC-DC Converter with Gap-Time Modulation using Pseudo-Hysteresis Control for -12kV/μs Common-Mode Transient Immunity
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
System Aspects of Deploying FPGAs for Cloud Infrastructure
Advanced Design Techniques for Integrated Voltage Controlled LC Oscillators
Implementation of a digital timing recovery circuit for CDMA applications
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS
A 27mW 2.2dB NF GPS receiver using a capacitive cross-coupled structure in 65nm CMOS
Insights into wideband fractional All-Digital PLLs for RF applications
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications
A 3.3 V analog adaptive line-equalizer for fast Ethernet data communication
Implementation of a Hermitian decoder IC in 0.35 μm CMOS
Low power bus coding techniques considering inter-wire capacitances
Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETs
A 4-Channel High-Precision Constant Current Control ASIC for Automotive Transmission Applications
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
A DRAM based physical unclonable function capable of generating >10 32 Challenge Response Pairs per 1Kbit array for secure chip authentication
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology
Per-Pixel Floating-Point ADCs with Electronic Shutters for a High Dynamic Range, High Frame Rate Infrared Focal Plane Array
Session 6 - Advanced SoC/SiP integration & co-design
A 6.8µW AFE for Ear EEG Recording with Simultaneous Impedance Measurement for Motion Artifact Cancellation
A CMOS-Integrated Color Center Pulse-Sequence Control and Detection System
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application
A semi-passive UHF RFID tag with on-chip temperature sensor
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS
A 16×20 electrochemical CMOS biosensor array with in-pixel averaging using polar modulation
Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation
A pipelined SAR ADC reusing the comparator as residue amplifier
Band-gap references for near 1-V operation in standard CMOS technology
A -10.1dBm IIP3, 0.3-40GHz Receiver Using Hybrid-Path Band-Selection with Reduced LO Coverage Bandwidth Supporting 480Mb/s 4096-QAM and 7.2Gb/s 64-QAM Modulation
A 334uW 0.158mm2 Saber Learning with Rounding based Post-Quantum Crypto Accelerator
Mobile Deep Learning Processors on the Edge
Hole filling: a novel delay reduction technique using selector logic
A multiple-probe approach for robust frequency domain ring oscillator simulation
Design for test of a mm-Wave ADPLL-based transmitter
Quad Gate-Driver Controller with Start-Up and Shutdown for Cascaded Resonant Switched-Capacitor Converter
CMOS LC oscillator using variable mean frequency
A novel global interconnect method using nonlinear transmission lines
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories
A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems
Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems
Design in hot-carrier reliability for high performance logic applications
Bipolar pulse width modulation driver for MEMS electrostatic actuator arrays
Autonomy through smart sensors and power electronics
Prospects for High-Efficiency Silicon and lll-V Power Amplifiers and Transmitters in 100-300 GHz Bands
A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques
Sequential synthesizable embedded programmable logic cores for system-on-chip
A phase detector for 12.5Gbps clock and data recovery with optimal detection
Analog sense amplifiers for high density NOR flash memories
A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR
A 14-b 30MS/s 0.75mm 2 Pipelined ADC with On-Chip Digital Self-Calibration
A 105.5 dB, 0.49 mm 2 Audio ΣΔ modulator using chopper stabilization and fully randomized DWA
A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler
Modeling of jitter in bang-bang clock and data recovery circuits
Transceivers for 6G Wireless Communications: Challenges and Design Solutions
Modeling Op Amp Nonlinearity in Switched-Capacitor Sigma-Delta Modulators
A Compact CMOS 363 GHz Autodyne FMCW Radar with 57 GHz Bandwidth for Dental Imaging
A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer
A General-Regression-Neural-Network Based 5V-to-48V Three-Level Buck/Boost Power Converter with 40dB PSRR 90%-Efficiency for SSD Power Loss Protection
Power management circuits for a 15-μA, implantable pressure sensor
A Wideband CMOS Linear Digital Phase Rotator
A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation
A 6.5 GHz wideband CMOS low noise amplifier for multi-band use
A Fully Integrated Adaptive-MPP-Shifting Rectifier for Piezoelectric Energy Harvesting Outputting 580µW at 10V-VOC
A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI
A 2455μm 2 1.7Gbps Side-Channel Attack-Resistant Masked HMAC-SHA256 Accelerator in Intel 4 CMOS
A diode-less compact voltage/frequency reference-in-one
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz
A heterogeneous digital signal processor implementation for dynamically reconfigurable computing
A Monolithic I 2 V 2 -Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting
40V MESFETs fabricated on 32nm SOI CMOS
A 1.3-GHz IF digitizer using a 4 th -order continuous-time bandpass ΔΣ modulator
Scaling beyond the 65 nm node with FinFET-DGCMOS
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling
A compact and programmable high-frequency oscillator based on a MEMS resonator
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications
A 0.0285mm 2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS