yusuke1997/dblp-id-title huggingface dataset:
Digital background auto-calibration of DAC non-linearity in pipelined ADCs
Optimum synchronous phase detection and its application in smart sensor interfaces
A Fully Integrated dToF System-on-Chip with High Precision Using Adaptive Optical Power Control and Shifted Histogram-Bin Binning
Flexible GF(2 m ) Divider Design for Cryptographic Applications
A low-distortion fourth-order bandpass delta-sigma modulator
The Impact of Parallel Programming Interfaces on the Aging of a Multicore Embedded Processor
Evolutionary Biperiodogram
Dictionary-based program compression on transport triggered architectures
Low-voltage Analog CMOS Filter Design
Peak-Contrained WLS Strategy for FIR Digital Filter Design
A New CMOS Broadband, High Impedance LNA for MRI Achieving an Input Referred Voltage Noise Spectral Density of 200pV/Hz√
ATAC: Improving performance and programmability with on-chip optical networks
Programmable spatially variant multiresolution readout capability on a sensor focal plane
Improved Toolchain-Compatible Standard Cells with 5% - 36% Lower EDP for Super Threshold Operation in 65nm Low-Power CMOS Technology
Statistical analysis of chaotic Markov systems with quantised output
Compressive sensing of localized signals: Application to Analog-to-Information conversion
Multilayer graphene nanoribbon floating gate transistor for flash memory
Efficient Probabilistic Optimal Power Flow Assessment Using an Adaptive Stochastic Spectral Embedding Surrogate Model
Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes
Low-band-shift (LBS) motion estimation with symmetric padding in wavelet domain
A Capacitor-less Hybrid LDO for Low Frequency Supply Noise Suppression Achieving 99.87% Efficiency and 3.32ps Response Time in 65nm
A highly-integrated biomedical multiprocessor system for portable brain-heart monitoring
Delay element concept for Continuous Time Digital Signal Processing
Modeling and analysis of PSRR in analog PWM class D amplifiers
A new shared-input amplifier architecture with enhanced noise-power efficiency for parallel biosignal recordings
Sparse component analysis of overcomplete mixtures by improved basis pursuit method
Evaluation of power cut-off techniques in the presence of gate leakage
Design of an ultra-wideband low noise amplifier in 0.13µm CMOS
Design of Reversible Sequential Elements With Feasibility of Transistor Implementation
Phase noise in frequency divider circuits
Effective modelling of large NoCs using SystemC
A low-complexity and high-speed Booth-algorithm FIR architecture
A Stability Condition for Constant-On Time Buck Converters Suitable for Automotive Applications
An End-to-End Deep-Learning-Based Indirect Time-of-Flight Image Signal Processor
Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing
A simple and efficient dithering method for vector quantizer based mismatch-shaped ΔΣ DACs
Brain-on-a chip technologies for investigating neuronal diseases: Toward precision medicine applications
Characteristics of human voice processing
DNA chip image processing via cellular neural networks
Designing DSP-based systems using Multiple Processor Hardware Platforms
Load-Independent Class-E Rectifier with Variable Gain and Fixed Input Reactance
Bit-level pipelined digit serial GF(2m) multiplier
A power management architecture for fast per-core DVFS in heterogeneous MPSoCs
Static Allocation of a Task Tree onto a Linear Array
A 0.5V nanoWatt CMOS voltage reference with two high PSRR outputs
Design of threshold logic gates using emerging devices
Modeling of dynamic errors in algorithmic A/D converters
Agile multi-band delta-sigma frequency synthesizer architecture
DSA-QoE: Quality of Experience Evaluation for Streaming Video Based on Dual-Stage Attention
Finding all elementary circuits exploiting transconductance
A 6-bit low-power compact flash ADC using current-mode threshold logic gates
An Adaptive Neuro/Fuzzy CMOS Chip
A fast depth-map wedgelet partitioning scheme for intra prediction in 3D video coding
A 16-bit Encrypted On-chip Embedded System for Implantable Medical Devices
Hierarchical Reinforcement Learning with Self-Distillation for Resource Scheduling in Complex Resource Networks
Energy Harvesting Circuit for Indoor Light Based on the FOCV and P&O Schemes with an Adaptive Fraction Approach
Cascoded Ring Amplifiers for High Speed and High Accuracy Settling
Transcoder with arbitrarily resizing capability
A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system
45.2% Energy efficiency improvement of UWB IR Tx by use of differential PPM in 180nm CMOS
An overview of design techniques for CMOS phase detectors
A novel finite-wordlength particle swarm optimization technique for FRM IIR digital filters
Fast-scale instability of single-stage power-factor-correction power supplies
A Digital FLL-based Adaptive Binary LDO for Implantable Medical Devices
Energy conservation in a circuit with single electron tunnel junctions
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells
Autonomous robot for a power transmission line inspection
Back-tracing and event-driven techniques in high-level simulation with decision diagrams
On-chip temperature sensor with high tolerance for process and temperature variation
A 276 nW, area-eficient CMOS subbandgap reference circuit
A color frame reproduction technique for IoT-based video surveillance application
No-reference quality assessment of JPEG images by using CBP neural networks
Design of bidirectional associative memories based on the perceptron training technique
Measurement of delay mismatch due to process variations by means of modified ring oscillators
Reduced Complexity Space-Time-Frequency Model for Multi-Channel EEG and Its Applications
Sensitivity of interconnect delay to on-chip inductance
High level spectral-based analysis of power consumption in DSPs systems
Demosaicking of Color Filter Array patterns using Quaternion Fourier Transform and low pass filter
A generalized averaging model for fixed frequency converters
Design of a 1.5 V CMOS integrated 3 GHz LNA
Voltage-clamped class E amplifier with a Zener diode across the switch
A high-speed wide-range low-distortion constant-gm cell design for GHz applications
Stability and linearization: discrete-time systems
A 10 bit, 50 M sample/s, low power pipelined A/D converter for cable modem applications
Solving ability of Hopfield Neural Network with scale-rule noise for QAP
An Auto Loss Compensation System for Non-contact Capacitive Coupled Body Channel Communication
A 3 Gb/s 80 dB CMOS differential transimpedance amplifier for optical communication systems
Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead
Analysis of the convergence behavior of the complex Gaussian kernel LMS algorithm
Segmented channel routing with pin rearrangements via satisfiability
Simple Cell Admission Control and Buffer Management Scheme for Mulitclass Video-On-Demand Service
On unbiased identification of autoregressive signals with noisy measurements
High-precision analog EEPROM with real-time write monitoring
An integrated beamformer for IR-UWB receiver in 0.18-µm CMOS
An In-Situ Technique for Measuring the Individual Contact Resistance between the Pins of an IC Package and the Board of a Flexible Hybrid Electronic System
A low-power gigabit Ethernet analog equalizer
Detection of all low-period windows for the logistic map
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System
Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays
A 100/μA/Ch fully-integrable lock-in multi-channel frontend for infrared spectroscopic gas recognition
Detection of a preseizure state in epilepsy: signal prediction by maximally weakly nonlinear networks?
Complexity reduction for frequency-response masking filters using serial masking
An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers
A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz
A termination technique for the averaging network of flash ADC's
Adaptive identification of sparse systems with variable sparsity
A CMOS on-chip temperature sensor with -0.21°C 0.17 °C inaccuracy from -20 °C to 100 °C
Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding
Enhanced power analysis attack using chosen message against RSA hardware implementations
A micropower vision processor for parallel object positioning and sizing
A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter
Performance enhancement of linear power amplifier employing digital technique
Sequential Node/Link Recovery Strategy of Power Grids Based on Q-Learning Approach
A simple LDO with adaptable bias for internet of things applications
Voltage stability and voltage recovery: effects of electric load dynamics
Energy efficiency optimization in Strong-Arm latch-based dynamic comparator by capacitor distribution
Comparative analysis of information rates of simple amplifier topologies
A fast and precise interconnect capacitive coupling noise model
Application of digital wide band mismatch calibration to an I/Q receiver
A Low-cost and High-performance SoC Design for OMA DRM2 Applications
Improved multirate sigma-delta architecture
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator
A system level description and model of Signaling System No 7
Architecture driven filter transformations
On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters
Analysis of partial constant return map from controlled manifold piecewise linear chaotic circuits
A freshman level module in biometric systems
Design of a Compact Cluster Structure by Using Genetic Algorithms
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop
Dynamic Amplifiers: Settling, Slewing and Power Issues
Efficient subband encoding of magnitude/phase spectra
Fault Detection and Classification of Analog Circuits by Means of Fuzzy Logic-Based Techniques
Scene adaptive video encoding for MPEG and H263+ video
Pipelined analog multi-layer feedforward neural networks
Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI
Sign Haar Transform
Instruction Level Parallelism Optimizations in a High-Performance Dual-Issue RISC-V Processor for Real-Time Control Systems
Process tolerant calibration circuit for PLL applications with BIST
Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications
An efficient pre-traceback approach for Viterbi decoding in wireless communication
Interference severity in nerve cuff recordings due to muscle source relative proximity
A new design for cascaded sigma-delta modulators
Using Machine Learning for Person Identification through Physical Activities
Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply
Implementation of overlapped block filtering using scheduling by edge reversal
A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise
Ultra low-power array processor propagation circuit arrangement
A 1-V 1.1-MHz BW digitally assisted multi-bit multi-rate hybrid CT ΣΔ with 78-dB SFDR
Dual-Path Deep Supervision Network with Self-Attention for Visible-Infrared Person Re-Identification
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer
Infinite Precision Analysis of the Fast QR Decomposition RLS Algorithm
Experimental validation of pinning controllability in networked Chua's circuits
Power-supply-variation-aware timing analysis of synchronous systems
Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique
Optimal Standard Cell Library Composition for 7nm
Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device
Inverting closed-loop amplifier architecture with reduced gain error and high input impedance
Low power LC-VCO design using direct cross-coupled cell biasing
Mapping channel estimation and MIMO detection in LTE-advanced on a reconfigurable cell array
Combined Effect of Loop Delay and Reference Clock Jitter in First-order Digital Bang-bang Phase-locked Loops
Trade-off between Sampling Rate and Resolution: A Time-synchronized Based Multi-resolution Structure for Ultra-fast Acquisition
A 2.5 GHz All-Digital Multiphase DLL and Phase Shifter in 65 nm CMOS using a Scalable Phase-to-Digital Converter
Multiple resonance networks with incomplete energy transfer and operating with zero-state response
A low-voltage high-swing colpitts VCO with Inherent tapped capacitors based dynamic body bias technique
Secure Communication Through Switched-Current Chaotic Circuits
A current mode Palmo cell for programmable analogue signal processing
Sensing Temporal Codes and Probing System Responses with Spikes: An Active Pixel Approach
A Novel Methodology for Processor based PUF in Approximate Computing
A high-bandwidth high-swing CMOS power amplifier for portable audio players
A wide band CMOS radio frequency RMS power detector with 42-dB dynamic range
Cryptographic Hash Function using current-induced magnetization switching in nano-magnetic devices
Linearized CMOS OTA using active-error feedforward technique
Applying CNN to Cheminformatics
Topology design for fast convergence of network consensus algorithms
Wearable RF Device for Monitoring Brain Activities in the Ageing Population
A front-end circuit with active spike and LFP separation via a switched capacitor filter structure for neural recording applications
Configurable Cache Memory Architecture for Low-Energy Motion Estimation
Fast thermopile readout circuit arrangement for array processors
A CMOS imager with pixel prediction for image compression
Bifurcation theory of a class of perturbed mappings
Subband Model and Implementation of 0-QAM System
A low-voltage low-noise digital buffer system
A Multi-Stride Convolution Acceleration Algorithm for CNNs
An Extended Phase Detector 2.56/3.2Gb/s Clock And Data Recovery Design with Digitally Assisted Lock Detector
AER EAR: a matched silicon cochlea pair with address event representation interface
Minimizing coupling jitter by buffer resizing for coupled clock networks
Coupling reduction analysis of bus-invert coding
A block-based adaptive super-exponential deflation algorithm for blind deconvolution of MIMO systems using the matrix pseudo-inversion lemma
Comparator-based switched-capacitor pipelined ADC with background offset calibration
A 2.2mW CMOS LNA for 6-8.5GHz UWB receivers
Leveraging LoRa Spreading Factor Detection to Enhance Transmission Efficiency
Fast image super-resolution via Randomized Multi-split Forests
A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation
Customizable FPGA-based Accelerator for Binarized Graph Neural Networks
AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs
Practical application of transconductance-to-drain-current dependent flicker noise analysis
Tri-FeatureNet: An Adversarial Learning-Based Invariant Feature Extraction for Sleep Staging using Single-Channel EEG
Identification of motor neuron disease using wavelet domain features extracted from EMG signal
An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies
Superpipelined Adder Designs
VLSI considerations in the design of k-ary n-cube interconnection networks
Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
Layout decomposition for hybrid E-beam and DSA double patterning lithography
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection
Semidefinite relaxations of equivalent optimal power flow problems: An illustrative example
Balanced-uncertainty optimized wavelet filters with prescribed regularity
Trellis coded residual vector quantization with application to image coding
Optimal procurement of VAR ancillary service in the electricity market considering voltage security
A straightforward approach of Automatic Parking System - "Training-Recording-Play back"
A Faster DiSH: Hardware Implementation of a Discrete Cell Signaling Network Simulator
Phase amplitude converter with conditional shift operation
A Ring Temperature Sensor for Quantum Applications
Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques
Efficient FPGA implementation of complex multipliers using the logarithmic number system
A power-configurable bus for embedded systems
Scalable high-throughput architecture for H.264/AVC variable block size motion estimation
Synthesis of reconfigurable multiplier blocks: part - II algorithm
A novel CMOS lab-on-a-chip for biomedical applications
The scaled normalized lattice digital filter
Steering with an aVLSI motion detection chip
High-speed link verification based on statistical inference
A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders
A fully-programmable temperature-compensated analogue circuit for Gaussian functions
Passive device modeling methodology using nonlinear optimization
Parameter domain pruning for improving convergence of synthesis algorithms
A low-power, hard-decision analogue convolutional decoder using the modified feedback decoding algorithm
Filter bank based frequency-domain equalizers with diversity combining
d-infinite Criteria for MEG Characterization
On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta Modulators
An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits
Optimization of the DQRUMA MAC protocol for multimedia traffic in an OFDM based W-ATM system
Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction
Approaches to mitigating the impact of DAC mismatch on the performance of continuous-time delta-sigma modulators
On reachability conditions for unrestricted Petri nets
ResDDQN-FPGA: A Reinforcement Learning Framework for Dynamic and Efficient Control in Resonant DC-DC Converters
Design and Analysis of an E-Band Power Detector in 0.13 μm SiGe BiCMOS Technology
An 1.92mW Feature Reuse Engine based on inter-frame similarity for low-power object recognition in video frames
A dual-mode, low-power and low-noise 0.18µm CMOS front-end for optical biosensors
Rule based constraints for the construction of genetic devices
Sleep condition inferencing using simple multimodality sensors
A 240-mV 33.8-μV/°C 1.5-nW Voltage Detector for Energy Harvesting
A Wide-band Low-power ROIC for Optoelectronic mixer-based LiDAR System
Property of rational functions related to band-pass transformation
Analysis and VLSI architecture of update step in motion-compensated temporal filtering
Design of A New Memristive-Based Architecture Using VTM Method
LiteLSTM Architecture for Deep Recurrent Neural Networks
A Real-Time Wearable FPGA-based Seizure Detection Processor Using MCMC
A fifth-order comb decimation filter for multi-standard transceiver applications
Dynamically adaptable NoC router architecture for multiple pixel streams applications
Fractional-Order Differentiators and Integrators with Reduced Circuit Complexity
Fast prototyping of reconfigurable architectures from a C program
Analysis of nonlinear dynamics in delta modulators for PWM control
Multi-band wide tuning range CMOS VCO with Hybrid Inductor for LTE standard
Adaptive CMOS LNAs for Beyond-3G RF Receivers - A Multi-standard GSM/WCDMA/BT/WLAN Case Study
Modeling Symmetry in Analog Electronic Circuits
A New Quadrature LC-Oscillator
Multi-Agent Bipartite Containment over Time-Varying Structurally Balanced Networks
Lagrangian Gradient for Principal Singular Component Analysis
A time-continuous optimization method for automatic adjustment of gain and phase imbalances in feedforward and LINC transmitters
A filtered-X RLS based narrowband active noise control system in the presence of frequency mismatch
Energy Efficient Bio-Feedback Stimulation System with Adaptive Parameters Optimization Closed Loop
A Novel Capacitive-Inductive Channel for Wireless Power and Data Transmission
A maximal entropy digital chaotic circuit
AVX2-Optimized Interpolation Filters for HEVC Inter Encoding
CPG-MTA implementation for locomotion control
Compact hardware architectures for BLAKE and LAKE hash functions
A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area
A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line
A novel technique for DCGA optimization of guaranteed BIBO stable IIR-based FRM digital filters over the CSD multiplier coefficient space
Optimal resource allocation for multimedia application providers in multi-site cloud
Geometric characterization of series-parallel variable resistor networks
A 2.4µW 400nC/s constant charge injector for wirelessly-powered electro-acupuncture
Simulation and Optimization of Class-E Power Amplifiers with Extended Impedance Method
Body-bias regulator for ultra low power multifunction CMOS gates
Fast 32-bit digital multiplier
High Q backside micromachined CMOS inductors
Distortion calculation of an asynchronous switching xDSL line-driver
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs
Multibit Sigma-Delta ADC with mixed-mode DAC error correction
Reliability Analysis of Physiological Phenomena by Cardiac Action Potential Model
A complete receiver solution for a chaotic direct-sequence spread spectrum communication system
FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers
A 0.78 mW Low-Power 4.02 High-Compression Ratio Less than 10 -6 BER Error-Tolerant Lossless Image Compression Hardware for Wireless Capsule Endoscopy System
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT
Design methodology for CMOS distributed amplifiers
Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4
Wearable wireless sensor patch for continuous monitoring of skin temperature, pressure, and relative humidity
Memristive devices fabricated with silicon nanowire schottky barrier transistors
A compound anisotropic diffusion for ultrasonic image denoising and edge enhancement
A Comparative Study of Five Integrator Structures for Monolithic Continuous-time Filters
Semiautomatic video object generation using multivalued watershed and partition lattice operators
Constant and maximum bandwidth feedback amplifier with adaptive frequency compensation
A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding
Bondwire-antenna and Duplexer-less LNA/PA Design for Wireless Transceivers
Joint wavelet transform and vector quantization for speech coding
Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification
A 12.5 Gb/s 1.93 pJ/Bit Optical Receiver Exploiting Silicon Photonic Delay Lines for Clock Phases Generation Replacement
DCHAS: Dual-Channel Heterogeneous Agent System for Optimizing Agricultural Irrigation Decisions
A modular test structure for CMOS mismatch characterization
A fast charge pump PLL using a bang-bang frequency comparator with dead zone
System level power optimizations for EPC RFID tags to improve sensitivity using load power shaping and operation scheduling
A Digital Radio-Frequency Condenser Microphone with Amplitude Modulation
An Automatic Leakage Compensation Technique for Capacitively Coupled Class-AB Operational Amplifiers
A 34.1fps scale-space processor with two-dimensional cache for real-time object recognition
A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder
An OpenCL runtime system for a heterogeneous many-core virtual platform