yusuke1997/dblp-id-title huggingface dataset:
HyperTEE: A Decoupled TEE Architecture with Secure Enclave Management
Sequential Prolog machine: Image and host architectures
Branch Target Buffer Organizations
A computing unit for FFP function evaluation in support of correctness proofs
Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor
ASV: Accelerated Stereo Vision System
The ZCache: Decoupling Ways and Associativity
Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era
LLVA: A Low-level Virtual Instruction Set Architecture
DynaMOS: dynamic schedule migration for heterogeneous cores
Bias-Free Branch Predictor
Look-Up Table based Energy Efficient Processing in Cache Support for Neural Network Acceleration
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Dynamic memory disambiguation for array references
LATCH: A Locality-Aware Taint CHecker
Analysis of the conditional skip instructions of the HP precision architecture
The trap as a control flow mechanism
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994
Algorithms for a self-tuning microprogrammed computer
Featherweight Soft Error Resilience for GPUs
Read-After-Read Memory Dependence Prediction
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
Patchable control store for reduced microcode risk in a VLSI VAX microcomputer
Costs and benefits of flexibility in spatial division circuit switched networks-on-chip
ASDR: An Application-Specific Deadlock-Free Routing for Chiplet-Based Systems
Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
Fairness and Throughput in Switch on Event Multithreading
A comparison of two pipeline organizations
CLIP: Load Criticality based Data Prefetching for Bandwidth-constrained Many-core Systems
Scaling Superconducting Quantum Computers with Chiplet Architectures
Summarizer: trading communication with computing near storage
Dominator-path scheduling: a global scheduling method
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly
Architectural Support for Software Transactional Memory
The implementation of the attributed recursive descent architecture in VAX-11/780 microcode
ASSASIN: Architecture Support for Stream Computing to Accelerate Computational Storage
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips
Design of concurrently testable microprogrammed control units
A VLSI view of microprogrammed system design
ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage
Multiple operation memory structures
FIdelity: Efficient Resilience Analysis Framework for Deep Learning Accelerators
Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation
IvLeague: Side Channel-Resistant Secure Architectures Using Isolated Domains of Dynamic Integrity Trees
Wavelength stealing: an opportunistic approach to channel sharing in multi-chip photonic interconnects
An Analysis of the Information Content of Address Reference Streams
NeSC: Self-virtualizing nested storage controller
Proposal on efficient address allocation algorithm for horizontal microprograms
SOPHIE: A Scalable Recurrent Ising Machine Using Optically Addressed Phase Change Memory
Predicting Performance Impact of DVFS for Realistic Memory Systems
An algorithm for control memory minimization
Path-based, randomized, oblivious, minimal routing
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems
gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling
Microarchitecture Support for Improving the Performance of Load Target Prediction
Memory Controller Optimizations for Web Servers
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
Initialization of microprogrammed machines
Teaching basic computer organization through "microprogramming"
The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings
Microdiagnostics for minicomputers
Hardware Identification of Cache Conflict Misses
Continuous runahead: Transparent hardware acceleration for memory intensive workloads
Design considerations for a QM-1 based multimicroprocessor emulation system
Reducing wire delay penalty through value prediction
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
STAR: Sub-Entry Sharing-Aware TLB for Multi-Instance GPU
Information structures in language directed architectures
Scale-out acceleration for machine learning
WarpPool: sharing requests with inter-warp coalescing for throughput processors
SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989
Analysis Techniques for Predicated Code
A comparative performance evaluation of various state maintenance mechanisms
Modulo scheduling for a fully-distributed clustered VLIW architecture
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense
A technique for micro-simulation the software "machine"
Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores
A microprogrammed implementation of an architecture simulation language
A Case for Speculative Address Translation with Rapid Validation for GPUs
Surf-Deformer: Mitigating Dynamic Defects on Surface Code via Adaptive Deformation
On High-Bandwidth Data Cache Design for Multi-Issue Processors
PACE - a microprogram evaluation system
Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing
Cache-Conscious Wavefront Scheduling
Transactional Memory Architecture and Implementation for IBM System Z
Low-cost router microarchitecture for on-chip networks
On improving operating system efficency through use of a microprogrammed, low-level environment
SquiggleFilter: An Accelerator for Portable Virus Detection
GCD 2 : A Globally Optimizing Compiler for Mapping DNNs to Mobile DSPs
HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, Virtual Event, Greece, 17 October 2020
Looking into the Black Box: Monitoring Computer Architecture Simulations in Real-Time with AkitaRTM
On Improving the Performance of Hybrid Wired-Wireless Network-on-Chip Architectures
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation
Application-aware prioritization mechanisms for on-chip networks
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
A monitoring system for NoCs
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Lightweight Emulation of Virtual Channels using Swaps
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
Shader Performance Analysis on a Modern GPU Architecture
Erasing Core Boundaries for Robust and Configurable Performance
Interactive microprogram validation: A Prime 400 testbed facility
SHARP control: controlled shared cache management in chip multiprocessors
An ultra low-power hardware accelerator for automatic speech recognition
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits
SAGE: self-tuning approximation for graphics engines
Authentication Control Point and Its Implications For Secure Processor Design
Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing
HgPCN: A Heterogeneous Architecture for E2E Embedded Point Cloud Inference
Region-based compilation: an introduction and motivation
Merging Head and Tail Duplication for Convergent Hyperblock Formation
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM
MIDETT: Microprogrammed-system design technique and tools
Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach
Automatic Parallelization in a Binary Rewriter
Design of assembly level language for horizontal encoded microprogrammed control unit
Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection
RIFLE: An Architectural Framework for User-Centric Information-Flow Security
MDM: The GPU Memory Divergence Model
Twig: Profile-Guided BTB Prefetching for Data Center Applications
An instruction reoderer for pipelined computers
ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs
Evaluation of a High Performance Code Compression Method
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Measuring limits of parallelism and characterizing its vulnerability to resource constraints
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture
Memory Allocation Under Hardware Compression
Out-of-Order Vector Architectures
Placement of microinstructions in a two-dimensional address space
On tuning the microarchitecture of an HPS implementation of the VAX
UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition
Time Interpolation: So Many Metrics, So Few Registers
MEGA Evolving Graph Accelerator
Generational Cache Management of Code Traces in Dynamic Optimization Systems
SecureLoop: Design Space Exploration of Secure DNN Accelerators
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
A versatile microprogram sequencer
Affinity Alloc: Taming Not-So Near-Data Computing
Microcode compaction via microblock definition
A scalable architecture for ordered parallelism
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers
COMP: Compiler Optimizations for Manycore Processors
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware
A micro signal processing module
A standardized microprogram sequencing control with a push down storage
Increasing User Interaction During High-Level Synthesis
Supplement to the conference record of the 7th annual workshop on Microprogramming, MICRO 1974, Palo Alto, California, USA, September 30 - October 2, 1974
Criticality Driven Fetch
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations
Correctness and equivalence of straight line microprograms
Dynamic 3D Graphics Workload Characterization and the Architectural Implications
CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units
PHAP: Password based Hardware Authentication using PUFs
Performance evaluation of instruction scheduling on the IBM RISC System/6000
The Reconfigurable Streaming Vector Processor (RSVPTM)
Predictability of load/store instruction latencies
Tolerating Concurrency Bugs Using Transactions as Lifeguards
CLEAN-ECC: high reliability ECC for adaptive granularity memory system
SHIFT: shared history instruction fetch for lean-core server processors
A cloud-scale acceleration architecture
Improving the performance of interpretive hierarchies by the introduction of local hardware
Combating Aging with the Colt Duty Cycle Equalizer
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network
Software pipelining: a comparison and improvement
The BubbleWrap many-core: popping cores for sequential acceleration
Master/slave speculative parallelization
Verification of the FTSC microprogram
Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms
MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product
Hypernode reduction modulo scheduling
Short Paper: A Quantum Circuit Obfuscation Methodology for Security and Privacy
3D MAX: A Maximally Adaptive Routing Method for VC-less 3D Mesh-based Networks-on-Chip
Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing
Direct addressed caches for reduced power consumption
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
EASY - an operating system for the QM-1
A static power model for architects
PRIME - a processor design for character recognition
Insertion and promotion for tree-based PseudoLRU last-level caches
Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002
ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading
Bell Labs microcode for the IBM 360/67
Divergence-aware warp scheduling
Selective Cache Ways: On-Demand Cache Resource Allocation
Efficient Memory Integrity Verification and Encryption for Secure Processors
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
Control flow coalescing on a hybrid dataflow/von Neumann GPGPU
Register Cache System Not for Latency Reduction Purpose
Compiler Synthesized Dynamic Branch Prediction
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996
MicroTAL - a machine-dependent, high-level microprogramming language
Experience with a high level micromachine simulator
Split-path Enhanced Pipeline Scheduling for Loops with Control Flows
Schedtask: a hardware-assisted task scheduler
Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers
Global optimization of microprograms through modular control constructs
Data-centric execution of speculative parallel programs
Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection
COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with Adaptive Spike Speculation
An evaluation of bottom-up and top-down thread generation techniques
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications
SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices
Self-calibrating Online Wearout Detection
The Filter Cache: An Energy Efficient Memory Structure
Bundled execution of recurring traces for energy-efficient general purpose processing
Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults
Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network
Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitectures
EMPROF: Memory Profiling Via EM-Emanation in IoT and Hand-Held Devices
Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects
Neighborhood-Aware Address Translation for Irregular GPU Applications
An application of L systems to local microcode synthesis
Proceedings of the 15th annual workshop on Microprogramming, MICRO 1982, Palo Alto, California, USA, October 5-7, 1982
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
Predicting Coherence Communication by Tracking Synchronization Points at Run Time
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines
Interlock collapsing ALU for increased instruction-level parallelism
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023, Toronto, ON, Canada, 28 October 2023 - 1 November 2023
Microarchitecture in the system-level integration era
Firmware approach to fast Lisp interpreter
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications
Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AI
Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip Architecture
An evaluation of functional unit lengths for single-chip processors
The Design and Performance of a Conflict-Avoiding Cache
A VLIW architecture based on shifting register files
Defensive microprogramming
Organizing computer systems for learnability and useability
Techniques for compressing program address traces
ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration
Towards Efficient NVDIMM-based Heterogeneous Storage Hierarchy Management for Big Data Workloads
Microprogrammed enhancements to higher level languages - an overview
MAVBench: Micro Aerial Vehicle Benchmarking
Techniques for extracting instruction level parallelism on MIMD architectures
A Hardware Accelerator for Protocol Buffers
SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems
DISC: Dynamic Instruction Stream Computer
Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handhelds
A Novel Partitioning Algorithm for Optimizing Neuron-to-Neuron Pathways through NoC in BMI
I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip
Formalization and automated synthesis of microprograms
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Use it or lose it: wear-out and lifetime in future chip multiprocessors
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
Automatic Thread Extraction with Decoupled Software Pipelining
Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors
COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous Persistence
KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity
Formally enhanced runtime verification to ensure NoC functional correctness
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures
Locality-Aware Mapping of Nested Parallel Patterns on GPUs
Estimating and understanding architectural risk
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources
Execution Drafting: Energy Efficiency through Computation Deduplication
PHI: Architectural Support for Synchronization- and Bandwidth-Efficient Commutative Scatter Updates
Efficient exception handling support for GPUs
Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment
Copy or Discard execution model for speculative parallelization on multicores
A high-level microprogrammed processor
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
Branch classification: a new mechanism for improving branch predictor performance
AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime
A first effort for a distributed segment-based approach on self-assembled nano networks
Code Transformations to Improve Memory Parallelism
Principal Kernel Analysis: A Tractable Methodology to Simulate Scaled GPU Workloads
Empirical and theoretical lower bounds on energy consumption for networks on chip
Efficient hardware for multiway jumps and pre-fetches
A data layout optimization framework for NUCA-based multicores
Control Flow Optimization Via Dynamic Reconvergence Prediction
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
Software Pipelining Loops with Conditional Branches
Proceedings of the 11th annual workshop on Microprogramming, MICRO 1978, Asilomar (Pacific Grove), California, USA, November 19-22, 1978
SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations
A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and Defenses
ActiveN: A Scalable and Flexibly-Programmable Event-Driven Neuromorphic Processor
The design of a system for the synthesis of correct microprograms
Improving cache lifetime reliability at ultra-low voltages
Compaction of two-level microprograms for a multiprocessor computer
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator
Unleashing CPU Potential for Executing GPU Programs Through Compiler/Runtime Optimizations
RAHP: A Redundancy-aware Accelerator for High-performance Hypergraph Neural Network
Microarchitecture description techniques
Composable Lightweight Processors
Characterizing and Modeling Non-Volatile Memory Systems
Veiled Pathways: Investigating Covert and Side Channels Within GPU Uncore
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor
The predictability of branches in libraries
Fast Secure Processor for Inhibiting Software Piracy and Tampering
An approach to optimization of horizontal microprograms
TAPAS: Generating Parallel Accelerators from Parallel Programs
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000
Post-Fabrication Microarchitecture
Thermal Modeling, Characterization and Management of On-Chip Networks
The Use of Multithreading for Exception Handling
Calpa: a tool for automating selective dynamic compilation
Minos: Control Data Attack Prevention Orthogonal to Memory Model
NAS-SE: Designing A Highly-Efficient In-Situ Neural Architecture Search Engine for Large-Scale Deployment
PipeRench implementation of the instruction path coprocessor
Relational profiling: enabling thread-level parallelism in virtual machines
A compile-time managed multi-level register file hierarchy
Towards Memory Friendly Long-Short Term Memory Networks (LSTMs) on Mobile GPUs
CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System
Microprogrammed significance arithmetic with tapered floating point representation
DeSC: decoupled supply-compute communication management for heterogeneous architectures
Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993
A microcoded RISC
Emulation of computer networks by microprogrammable microcomputers
SCAR: Scheduling Multi-Model AI Workloads on Heterogeneous Multi-Chiplet Module Accelerators
An efficient retargetable microcode generator
Trace scheduling optimization in a retargetable microcode compiler
POWER7 multi-core processor design
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999
ShapeShifter: Enabling Fine-Grain Data Width Adaptation in Deep Learning
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach