yusuke1997/dblp-id-title huggingface dataset:
Comparison of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs
CMOS Envelope Tracking amplifier IC design for high-efficiency RF polar transmitters
ARC: Adaptive Rounding and Clipping Considering Gradient Distribution for Deep Convolutional Neural Network Training
A multirate approach to multichannel blind deconvolution
Area efficient circuit tuning with floating-gate techniques
A thermal equivalent circuit for PEM fuel cell temperature control design
Low-complexity Carrier Frequency Offset Estimation using Novel Range Pointer Method for OFDM-based WLAN Systems
Techniques for robust energy efficient subthreshold domino CMOS circuits
Trading Off Sspeed Versus Dynamic Range in Switched Current Circuits
Encoding compressive sensing measurements with Golomb-Rice codes
A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays
Quantization noise in filter bank analog-to-digital converters
Sub-threshold Circuit Design with Shrinking CMOS Devices
TDC Sharing in SPAD-Based Direct Time-of-Flight 3D Imaging Applications
Blind deconvolution of linear systems driven by non-stationary source based on almost-symmetrical time-varying ARMA model
Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression
A Semi-digital Interface for Capacitive Sensors
GODPE: Global Optimization in Small Signal Device Model Parameter Extraction
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO
Tight coupling of timing-driven placement and retiming
Power optimization in a parallel multiplier using voltage islands
Mapping DSP applications on processor/coarse-grain reconfigurable array architectures
Introducing IC reliability elements in digital circuits and systems design education
Joint Enhancement and Denoising Method via Sequential Decomposition
A programmable temperature trigger circuit
A low phase-noise class-C VCO using novel 8-shaped transformer
Analysis of Simultaneous Switching Noise
Fast & Efficient Hysteretic Power Supplies for IoT Microsensors: Analysis & Design with Insight
98.9% Efficiency Fully-integrated GaN Driver for Underwater Wireless Charging Application
Intermodulation products in the EER technique applied to class-E amplifiers
A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW
Block-Based Spiking Neural Network Hardware with Deme Genetic Algorithm
Analysis and Design of ULV DIGOTAs in 16 nm CMOS FinFET
Low complexity image rectification for multi-view video coding
Band-stop noise modulated bandpass sigma-delta analog-to-digital converter
Fault Tolerant Adaptive Filter Structure Based on the Generalized Subband Decomposition of FIR Filters
HEAM: High-Efficiency Approximate Multiplier optimization for Deep Neural Networks
A 2 7 -1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS
Scalar quantizer based feedback of the Channel Direction Information in MU-MISO systems
Determining potentially unstable operating points using time-varying root-locus
An Energy-Efficient 13-bit Zero-Crossing ΔΣ Capacitance-to-Digital Converter with 1 pF-to-10 nF Sensing Range
Modeling and analysis of nonlinearities and bandwidth limitations in RF receivers
A new memory reference reduction method for FFT implementation on DSP
Measurement, composition and inversion of orthogonal representations of memoryless nonlinearities
A VLSI System Architecture for Optical Flow Computation
Progressive fine granular scalable (PFGS) video using advance-predicted bitplane coding (APBIC)
System aspects of a bionic eyeglass
Blind equalization by sequential importance sampling
Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits
Neural Precision Polarization: Simplifying Neural Network Inference with Dual-Level Precision
RecogNoise: Machine-Learning-Based Recognition of Noisy Segments in Electrocardiogram Signals
Global scheduling and register allocation based on predicated execution
Unambiguous I-cache testing using software-based self-testing methodology
Exploiting Approximate SRAM for Energy-Efficient Integer Motion Estimation on VVC Encoders
ΣΔ gradient-descent learning for online real-time calibration of digitally-assisted analog circuits
Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models
Efficient VLSI architecture for 2-D inverse discrete wavelet transforms
Fuzzy logic controlled monolithic switching regulator in BCD technology
2-D signal theoretic investigation of background elimination in visual tomographic reconstruction for safety and enabling health applications
Design considerations of bandpass CT ΣΔ modulators for software-defined-radio receivers
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
A Novel Zero Dynamics Design Method and its Application to Hydraulic Turbine Governor
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier
Symbolic Analysis of Large Linear Circuits with the Bilinear-Splitting Transformation
A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages
Switched-current fractional-order filter designs
A Family of Consistent Steiglitz-McBride Algorithms for IIR Adaptive Filtering
Window Size Estimation for Nearest Neighbour Compliant Quantum Circuit Mapping
Mage: a Decoupled Access-Execute CGRA tailored for Static Control Applications
Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect
Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder
Design Methodology of VLSI with Multiple Valued Logic
Effects of quench discretization on superregenerative oscillators
Issues in enhanced narrow-band signal attenuation in DSSS BPSK receiver systems
Practical issues using e-pot circuits
A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation
SMF robust filtering in impulsive noise
Approximate treatment for calculation of the rate-distortion slope in EBCOT
A High-Throughput Design for the H.266/VVC Low-Frequency Non-Separable Transform
A new approach to avoid walk error in pulsed laser rangefinding
High slew rate two stage A/AB and AB/AB op-amps with phase lead compensation at output node and local common mode feedback
Real-time compressed sensing-based electrocardiogram compression on energy-constrained wireless body sensors
An adaptive class-E power amplifier with improvement in efficiency, reliability and process variation tolerance
Cost-effective low-power architectures of video coding systems
67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications
A new recursive algorithm for time-varying autoregressive (TVAR) model estimation and its application to speech analysis
An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal
Optimization of Lookup Table Size in Table-Bound Design of Function Computation
Communication-aware application mapping and scheduling for NoC-based MPSoCs
Multidimensional convolutional code: progresses and bottlenecks
Single-Event Transient Tolerant Optical Receiver Using Triple Modular Redundancy
A 27.5 fJ/step SAR Capacitance-to-Digital Converter Based on Correlated Double Sampling
A low-power fully-integrated SP10T-RF-switch-IC
Power Delivery for Silicon Interconnect Fabric
On the Feasibility of SI for low-Power VLSI Biomedical Signal Processing
A novel approach for K-best MIMO detection and its VLSI implementation
Towards System Level Security Analysis of Artificial Pancreas Via UPPAAL-SMC
A new genetic algorithm for routing the shortest route via several designated points
A 80µW/frame 104×128 CMOS imager front end for JPEG compression
Super resolution of video using key frames
Live Demonstration: Neuromorphic Robotics, from Audio to Locomotion Through Spiking CPG on SpiNNaker
Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array
Direct Sigma Delta GMSK modulator modeling and design for 2.5 G TX applications
On the Design of a Less Jitter Sensitive NTF for NRZ Multi-bit Continuous-time DeltaSigma Modulators
An overview and comparison of analytical TCP models
An efficient greedy approach to PLA folding
IP-cores design for the kNN classifier
DRAM access reduction in GPUs by thread-block scheduling for overlapped data reuse
Continuous User Authentication Using IoT Wearable Sensors
A Novel Non-profiling Side-Channel Attack on Masked Devices with Connectivity Matrix
A pseudo-differential CMOS receiver insensitive to input common mode level
Partitioning graphs of supply and demand
Large-signal and phase noise performance analysis of active inductor tunable oscillators
A digital technique for reducing clock jitter effects in time-interleaved A/D converter
Iterative QR Decomposition Architecture using the Modified Gram-Schmidt Algorithm
Sampling at Minimum Sampling Rate for Signals in Shift Invariant Spaces
Achievement of CV and CC Output Modes on Class-E/F Inverter with One Auxiliary Switch
Analysis of CMS noise reduction for 65 nm CIS
Interlaced Sampling for Noise Reduction
Study of zero-order holder discretization in single input sliding mode control systems
A high-frequency phase-compensation fractional-N frequency synthesizer
VLSI implementation of real-time motion compensated beamforming in synthetic transmit aperture imaging
Event-based Audio Prediction with Spectro-Temporal Event-Graphs
Towards neural network-based design of radiofrequency low-noise amplifiers
Quantization Noise of 1-Bit Double-Loop Sigma-Delta Modulator
An efficient and accurate method for computing the invariant measure of piecewise affine chaotic maps
A novel variation insensitive clock distribution methodology
A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator
Data hiding for bi-level documents using smoothing technique
Unifying past and recent developments in bounded ellipsoid processing
Fractional discrete-time chaotic map
A CMOS imager with real-time frame differencing and centroid computation
Deep Multi-Scale Features Learning for Distorted Image Quality Assessment
A framework for fully automatic moving video-object segmentation based on graph partitioning
Data link design using a time-based approach
Design guidelines for reconfigurable multiplier blocks
Projection Deformation Based Motion Compensation for Panoramic Video
On the use of compressive sensing (CS) for brain dopamine recording with fast-scan cyclic voltammetry (FSCV)
Fully-Integrated Differential RRAM Cell Designs with Multi-Level Capability and Enhanced Read Margin
OBT implementation on Gm-C filters without self-tuning capability
An ultra low-energy DAC for successive approximation ADCs
Chaotic system reconstruction from noisy time series measurements using improved least squares genetic programming
The multi-level paradigm for distributed fault detection in networks with unreliable processors
A 40nm 24.6TOPS/W Scalable EfficientDet Processor for Object Detection
Gain- and offset-compensated non-inverting SC circuits
Chaos in a differential fourth-order log-domain band-pass filter
Finding the minimum sampling frequency of multi-band signals: An efficient iterative algorithm
Crosstalk noise effects of on-chip inductive links on power delivery networks
A 3.1-4.2 GHz automatic amplitude control loop VCO with constant Kvco and <10mV amplitude variation
An SoC Integrating an H.264 Encoder with an ISP
On the modeling of blackouts in power networks
A low-complexity correlation algorithm
A Derivation of System Specifications Based on a Partial Logical Petri Net
Assessment of Perceptual Depth Intensity on Source Stereoscopic Images
A compact dual-band 5dBm RF power amplifier for cellular applications
Robust design of high gain amplifiers using dynamical systems and bifurcation theory
40 Gop/s/mm 2 fixed-point operators for Brain Computer Interface in 65 nm CMOS
An Automated Compiler for RISC-V Based DNN Accelerator
A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends
Live demonstration: Real-time, dynamic visual saliency computation in a VR environment seeing through the eyes of a mobile robot
Recursive Least Squares adaptive filters for ultrasonic signal deconvolution
Optimization of CMOS Voltage reference with Prediction based on Multi-group Hierarchical Collaborative Evolution and GBDT
Position, damping and inertia control of parallel-plate electrostatic actuators
Mixing in a 220MHz CMOS-MEMS
On the Design of a Doubly-matched Diplexer with a Common Junction
An improved scan design for minimization of test power under routing constraint
Memory and computationally efficient psychoacoustic model for MPEG AAC on 16-bit fixed-point processors
An area-efficient maximum/minimum detection circuit for digital and video signal processing
Energy-Efficient Reconfigurable Skyrmion-Based Counter for Nanoscale Applications
A meminductive circuit based on floating memristive emulator
Designing Adaptive Equalizers Based on the Constant Modulus Error Criterion
Associative Memory Function Using Coupled Oscillators with Sparse Coupling
Design and Analysis of GaN Based Isolated Double-Step-Down Converter for High-Step-Down Application
Post-silicon skew tuning algorithm utilizing setup and hold timing tests
Cost Effective Color Filter Array Demosaicking with Chrominance Variance Weighted Interpolation
6-channel CMOS-based instrument for optical absorption spectroscopy and chemical identification
A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application
Design of a high-speed Reed-Solomon decoder
Fast motion estimation using modified circular zonal search
Passive Ladder Synthesis in filtorX
Embedded Jitter Measurement of High-speed I/O Signals
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM
Fault Orientated Test and Fault Simulation of Mixed Signal Integrated Circuits
Embedding of non-contractive systems in lossless realizations
Thresholding based Stochastic Robust Algorithm for Distributed Compressed Sensing
Remote PPG Estimation from RGB-NIR Facial Image Sequence for Heart Rate Estimation
A flexible macroblock ordering with 3D MBAMAP for H.264/AVC
Network theory of information engines
A 64-MHz~1920-MHz programmable spread-spectrum clock generator
Mixed signal and SoC design flow requirements
A new architecture for analog sampled-data neural filters
A technique to design high entropy chaos-based true random bit generators
Implementation of biorthogonal cosine-modulated filter banks with fixed-point arithmetic
VLSI implementation of a real-time video watermark embedder and detector
Power Delivery for Ultra-Large-Scale Applications on Si-IF
Hybrid transform for HEVC-based lossless coding
Digital tuning of analog bandpass filters based on envelope detection
A Novel Compact Current Driver Circuit with Temperature Feedback Control for 2D Nanophotonic Phased Arrays
A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller
Efficient Synchronizer Architecture using Common Autocorrelator for DVB-S2
Code division parallel delta-sigma A/D converter with probabilistic iterative decoding
A Low-Power 65/14nm Stacked CMOS Image Sensor
Curriculum Development for Tapeout-Ready Mixed-Signal System-on-Chip Design and Assembly
Luminance-adaptive smart video storage system
Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network
A low-energy hybrid radix-4/-8 multiplier for portable multimedia applications
Exploring Spiking Neural Networks for Prediction of Traffic Congestion in Networks-on-Chip
Design and Synthesis of a Three Input Flagged Prefix Adder
Digitally Tunable CMOS Mixer Design for Adaptive RF Front-Ends
An analog-to-digital converter with Golomb-Rice output codes
Orthogonal convolutional modulation for UWB impulse radio communications
Hardware-efficient steering matrix computation architecture for MIMO communication systems
BEOL NEM Relay Based Sequential Logic Circuits
A New MRAM-Based Process In-Memory Accelerator for Efficient Neural Network Training with Floating Point Precision
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD
Fully-differential 13 Gbps clock recovery circuit for OC-255 SONET applications
Reordering-based transform for compressing human motion capture data
A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 Video Decoder
A phase model approach for synchronization analysis of coupled nonlinear oscillators
A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture
Bulk Linearization Techniques
Probabilistic Neural Network with Memristive Crossbar Circuits
Distributed evidence filtering: the recursive case
A 96.7% efficient boost converter with a stand-by current of 420 nA for energy harvesting applications
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU
An analog modulator/demodulator using a programmable arbitrary waveform generator
A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application
Novel high-radix residue number system multipliers and adders
Stable output error identification scheme using periodic excitation signals
Emerging resistive switching memory technologies: Overview and current status
An improved test power optimization method by insertion of linear functions
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique
High-Linearity Switched-Capacitor Circuits in Digital CMOS Technology
GNN4HHR: A GNN Based Model for Hybrid Hardware Representation
A modified spiral search motion estimation algorithm and its embedded system implementation
Separation of weak reflection from a single superimposed image using gradient profile sharpness
An Algorithm for Automatic Tuning of PLLs
The current-feedback differential difference amplifier: new CMOS realization with rail to rail class-AB output stage
Arrays of switched Chua's circuits
Simple RC models of distributed RC lines in consideration with the delay time
A Pulse-based Amplifier and Data Converter for Bio-potentials
Power efficient sequential multiplication using pre-computation
Low Power Neuromorphic Analog System Based on Sub-Threshold Current Mode Circuits
The CBP parameter - a useful annotation to aid block-diagram compilers for DSP
High-speed BiCMOS Operational Amplifier for Switched-capacitor Circuits
A two-stage genetic algorithm for the design and optimization of resonator/integrator based sigma-delta A/D and D/A converters
A memristor-CMOS hybrid architecture concept for on-line template matching
A 0.9V 75MHz 2.8mW 4th-order analog filter in CMOS-bulk 28nm technology
Improved structural similarity measurement for vocal signals
An Incremental Σ∆ Current-to-Digital Converter with Dynamically Scalable Power Consumption and No Dead Time
On data address computation for embedded DSP systems
A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology
Towards Built-In-Self-Test for SNR Testing of a Mixed-Signal IC
Statistical Electromigration analysis of a chip with the consideration of a within-die temperature map
A Dual Basis Systolic Divider for GF(2 m )
Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers
Condensed recursive structures for computing multi-dimensional DCT with arbitrary length
High light-load efficiency charge pumps
Chaos control in permanent magnet synchronous motor
I/Q imbalance of two-path ladder filters
On Time-interleaved Analog-to-digital Converters for Digital Transceivers
Multi-scale Attentive Fusion Network for Remote Sensing Image Change Captioning
Linear current mode image sensor with focal plane spatial image processing
A digital centric transmitter architecture with arbitrary ratio baseband-to-LO upsampling
Spectral analysis of multibit VCO-ADCs and PFM-ADCs with sinusoidal inputs
Special singularity integrals encountered in electric circuits [RLC circuit examples]
Neurodynamic interface circuits for a multichannel, wireless sensor IC operating in saltwater
The Evolution of Submissive Strategies on the Clustered Scale-Free Networks
On the Computation of Hetero Clinic Orbits in Dynamical Systems
Small-signal analysis of closed-loop PWM boost converter in CCM with complex impedance load
Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing
ALPACA: An Accelerator Chip for Nested Loop Programs
Powerline Energy Harvesting with Maximum Power Point Tracking for a Wide Current Range
Application of a novel battery charger system to new developed piezoelectric actuator for high speed micropositioning motion
ROI-based scalability for progressive transmission in JPEG2000 coding
Adaptive delay compensation in multi-dithering adaptive control
An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior
Analytical solutions of the Class D inverter
Logarithmic sampling of gain and phase approximation
A Generic Circuit Platform of Covering All Rational Numbers for Determnistic Stochastic Computing in the Time Dimension
Multicast video synchronization via MPEG-4 FGS/XML representation
Time-delay modelling for multi-layer power systems
A countermeasure against differential power analysis based on random delay insertion
A Comparative Study of Advanced Techniques for Wireless Power Transfer to Miniature Medical Implants
Realization of Reading-based Ternary Łukasiewicz Logic using Memristive Devices
Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model
A CMOS Vision Sensor for Background Subtraction
20GHz bandwidth digitizer for single shot analysis
An Improved Biasing Circuit for High Input CMR Op Amps
Bandwidth Limitations in Current Mode and Volage Mode Integrated Feedback Amplifiers
A Self-Reset Transconductance Integrating Leakage Latch (STILL) for Ultra-Low Power Sensor Interfacing
14-bit DR, 20 kHz BW, 2-2 MASH SI-Σ modulator using low-distortion feedforward topology
Application of Adaptive CPWL Filter in Impulsive Noise Removal
Throughput Adaptation for Scalable Video Multicast in Wireless Networks
A deadline-aware virtual contention free EDCA scheme for H.264 video over IEEE 802.11e wireless networks
Synthesis of Dual-Input Single-Output DC/DC Converters
Energy harvesting circuit with input matching in boundary conduction mode for electromagnetic generators
On the baseband hardware complexity of modernized GNSS receivers
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique
Multi-strategy object tracking in complex situation for video surveillance
Recent theory and new applications in chaos communications
A study of digital decoders in flash analog-to-digital converters
The new weighting method of sparse neural network
Lyapunov Function Based Fuzzy State Estimator
A new steady-state analysis method for RF-IC circuits driven by multi-tone signals
Leveraging Open Source IC Design Tools for an Undergraduate Microelectronic Circuit Design Course
Chaotic control of a DC-DC-converter
Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme
Stray Insensitive Implementation of Programmable Switched Capacitor Amplifiers
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians
Load adaptive control scheme to improve converter efficiency and performance
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework
An EFOM for cross-layer optimization towards low-power and high-performance wireless networks
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface
A Real-Time Memory-Less In-Sensor Time-Domain Convolution Processor with Programmable Kernel for Feature Extraction