yusuke1997/dblp-id-title huggingface dataset:
Block time-recursive discrete Gabor transform implemented by unified parallel lattice structures
Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices
A voltage reference generator targeted at extracting the silicon bandgap Vgo from Vbe
Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint
Variable-resolution simulation of nonlinear power circuits
Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era
Single Gauss model set-based data imputation method for complex ASR task
Generalized half-band maximally flat FIR filters
An Improved Random Walk Approach for Yield Optimization
A new searchless fractal image encoding method for a real-time image compression device
Subband stationarity analysis of speech signals
Blind signal separation using fixed overcomplete basis function dictionaries
Sufficient Conditions for Finding Multiple Operating Points for CD Circuits Using Continuation Methods
High-resolution DOA estimation by algebraic phase unwrapping algorithm
An energy-efficient parallel-processing method based on master-hibernating DVFS
Triggers for Irrigation Decision-Making in Greenhouse Horticulture using Internet of Things
A Novel Approach to Detection of Closely Spaced Sinisoids
Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes
Modeling of conduction losses in PWM converters operating in discontinuous conduction mode
A cost effective reconfigurable memory for multimedia multithreading streaming architecture
A CMOS fifth-order low-pass current-mode filter using a linear transconductor
On the Joint Compensation of IQ Imbalances and Phase Noise in MIMO-OFDM Systems
Mixed-mode ESD protection circuit simulation-design methodology
An FPGA-Based Hybrid Neural Network Accelerator for Embedded Satellite Image Classification
Soft-switching boost power factor correction converter with negative slope ramp carrier control
A two-stage digital AGC scheme with diversity selection for frame-based OFDM systems
An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC
Nonlinear dynamics in a graphene nanostructured device for energy harvesting
A Systolic Dataflow Based Accelerator for CNNs
CardioNet: Deep Learning Framework for Prediction of CVD Risk Factors
Winner-take-all neural network with digital frequency-locked loop
Closed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model
Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA
An impedance detection circuit for applications in a portable biosensor system
New FPN correction method for PD-storage dual-capture CMOS image sensor using a nonfully depleted pinned photodiode
Generalized Multiplication Free Arithmetic Codes
Frequency domain limitations of non-negative impulse response non-lowpass filters
Rapid design space exploration of two-level unified caches
Fast compression artifact reduction technique based on nonlinear filtering
A 5-GHz delta-sigma PLL frequency synthesizer for WLAN applications
An area-efficient and protected network interface for processing-in-memory systems
A ±10ppm -40 to 125°C BAW-based frequency reference system for crystal-less wireless sensor nodes
Parallel Digital Signal Filtering on Barrel Shifter Computers
Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications
Pulse Transition Characterization from Electrocardiography and Photoplethysmography for Non-Invasive Blood Pressure Estimation
Inexact Arithmetic Circuits for Energy Efficient IoT Sensors Data Processing
Improved Large-signal Model for Vacuum Triodes
A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation Time
A novel approximate computing based security primitive for the Internet of Things
Digital watermarking using Walsh code sequences with error spreading technique and intra-pixel prediction
On designing linearly-tunable ultra-low voltage CMOS g m -C filters
A multifunctional high-voltage driver chip for low-power mobile display systems
A Matching Technique for Biphasic Stimulation Pulse
Lean angle estimation in two-wheeled vehicles with a reduced sensor configuration
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance
A SAT-based diagnosis pattern generation method for timing faults in scan chains
Adaptive Stereo Direct Visual Odometry with Real-Time Loop Closure Detection and Relocalization
Mapping the wavelet transform onto silicon: the dynamic translinear approach
A reconfigurable channel codec coprocessor for software radio multimedia applications
Spatio-Temporal Δ-Σ N2-Port ADC Noise Shaping for N × N Antenna Arrays
Scale- and rotation- invariant feature detectors on Cellular Processor Arrays
Polynomial implementation structure for lagrange-type variable fractional delay filters
A study of injection locking in ring oscillators
Digital Signal Processing for Multi-Carrier Data Transmission on Phase-Controlled Power Lines with Nonlinearities
Synthetic Image Generation for Gastritis Detection Based on Auxiliary Classifier Generative Adversarial Network
Controlling chaotic systems with disturbance: a new approach based on backstepping design and nonlinear damping
A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing
On the Characterization of GraphML Frameworks: The Case of Semi-Supervised Node Classification
TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference
Design of wide-band amplifiers/filters using Lommel polynomials
Data-Driven Offline Optimization of Deep CNN models for EEG and ECoG Decoding
An 8-bit, 1mW successive approximation ADC in SOI CMOS
Cross-Space Alignment-based Attribute Artifact Removal for V-PCC
A CFAR synchronization scheme for impulse based UWB receiver
Forward error correction with RaptorQ code on GPU
Dynamic jitter accumulation in clock repeaters considering power and ground noise correlations
A Dual-mode Flow Measurement System for Large Sensing Range with High Accuracy
A 1.5 V linear transconductor with wide bandwidth and wide input and output signal swings
Hybrid discretization in power converters' digital controller design
Finite state machine partitioning for low power
CMOS auto-ranging PLL for low-voltage wideband systems
Image super-resolution via dual-dictionary learning and sparse representation
A Stealthy Hardware Trojan Design and Corresponding Detection Method
Fully-integrated Multi-band Tunable Linearized CMOS Active Analog Phase Shifter with Active Loss Compensation for Multiple Antenna Wireless Transceiver Applications
Narrow-band and wide-band single filter frequency masking FIR filters
Millimeter-Wave BPFs Design using Quasi-Lumped Elements in 0.13-μm (Bi)-CMOS Technology
Signal activity and power consumption reduction using the logarithmic number system
Engaging Students in an Introductory Circuits Course
A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration
A precedence effect based far-field DoA estimation algorithm
Formal verification of an SoC platform protocol converter
Equal Phase, Variable Crossover, Ladder Realizable, Diplexers using the Butterworth Polynomial
Capacitively-Biased Floating-Gate CMOS: a New Logic Family
A feedforward timing recovery scheme using two samples per symbol: algorithm, performance and implementation issues
Improving the computer network intrusion detection performance using the relevance vector machine with Chebyshev chaotic map
Optimal Order for Signal and System Modeling
Synthetic Gene Network Computational Design
Current profile of a microcontroller to determine electromagnetic emissions
Continuous-Time Algorithms for Solving Maxwell's Equations using Analog Circuits
A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback
Advances in QoS path(s) selection problem
Towards Wave Digital Memcomputing with Physical Memristor Models
A Fast Low-Power Driver for Long Interconnections in VLSI Systems
A 10GS/s 2V pp emitter follower only track and hold amplifier in SiGe BiCMOS technology
CARE: A dynamic stereo vision sensor system for fall detection
AFSEM: Advanced frequent subcircuit extraction method by graph mining approach for optimized cell library developments
Social learning with bounded confidence and probabilistic neighbors
A novel algorithm for color quantization by 3D diffusion
A novel hybrid neuro-wavelet system for robust speech recognition
Beyond CMOS: Ternary and mixed radix CNTFET circuit design, simulation and verification
Logarithmic number system addition-subtraction using fractional normalization
Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections
The generalized back-propagation algorithm with convergence analysis
Fuzzy Partitioning applied to VLSI-Floorplanning and Placement
Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter
Multi-frequency resonant clocks
Live Demonstration: Deep Learning-Based Visual Tracking of Multiple Objects on a Low-Power Embedded System
A single-stage three-phase high power factor rectifier with high-frequency isolation and regulated DC-bus based on the DCM SEPIC converter
A refinement process for nozzle path planning in 3D printing
Tonal behavior analysis of an adaptive second-order sigma-delta modulator
An integrated countermeasure against differential power analysis for secure smart-cards
A Full-Reference Image Quality Assessment Method with Saliency and Error Feature Fusion
Multiplication by two integers using the minimum number of adders
SUTLAC: A Conceptual Study on VR-Enabled Semantic Dessert Design Utility for Treating Diabetes MeLlitus with Active PartiCipation
Design of Pre-Emphasis Pulses for Large Memory Arrays with Minimal Word-Line Delay Time
Event-Triggered Control and Interactive LQR Tuning for Improved Control Efficiency
Spectral correlation MUSIC algorithm for cyclostationary signals by exploitation of new array configuration
A rotation based multichannel least squares lattice algorithm for adaptive nonlinear filters
Model Predictive Control-Based Reinforcement Learning
Ultra-Low-Power IoT 30nW 474mV 19 ppm/ ° C Voltage Reference and 2 nA 470 ppm/ ° C Current Reference
Localized weighted prediction for video coding
Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System
An FPGA Processor Combining Point Cloud and SNN for DVS-based ADAS Application
CMOS SFFDS PA with Coupled Transformer for High Power RF Applications
Two algorithms for frequency estimation of a real sinusoid from short data records
Bifurcation of modes in three-coupled oscillators with the increase of nonlinearity
Novel asynchronous registers for sequential circuits with quantum-dot cellular automata
Analysis of Time-varying Collusion Attacks in Fingerprinting Systems: Capacity and Throughput
Blind detection of photomontage using higher order statistics
A multipath polyphase digital-to-analog converter for software radio transmission systems
A sub-1µW, 16kHz current-mode SAR-ADC for single-neuron spike recording
New implementation of time domain measurement of quality factor
Study of Performance Impact from Powering RF Receiver Front-End Circuits with a DC-DC Converter
A 0.18 µm implementation of a floating-point unit for a processing-in-memory system
An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC
Recent results for chaotic modulation schemes
Digital post-correction of front-end track-and-hold circuits in ADCs
A circuit that creates a logarithmic response from an integrating CMOS pixel
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter
Settling time of mesochronous clock re-timing circuits in the presence of timing jitter
Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems
Design Limitations in Oxide-Based Memristive Ternary Content Addressable Memories
Low-power adaptive filter based on RNS components
Finite-State-Machine inspired Hardware Watermark using Spin-Orbit Torque operated MTJ
Model compatibility aspects in multilingual simulation environments
Generating multi-scroll chaotic attractors via threshold control
A 40nm Early-Warning AVFS Design with Path Activation-Based Monitoring Point Optimization
Live Demonstration: A Baseband Testbed for Uplink Mobile MIMO WiMAX Communications
High Speed Sphere Decoding Based on Vertically Incremental Computation
Segmentation Guided Fusion Network for Motion Deblurring of Long Exposure Images in Low Light Condition
Circular array based 2D recursive filtering using a spatio-temporal helix transform
Low power techniques for flash memories
A series of exponential step-down switched-capacitor converters and their applications in two-stage converters
CNN models of current mode neuromorphic networks
The extended ear type system and possible applications
A 20 V, 8 MHz resonant DCDC converter with predictive control for 1 ns resolution soft-switching
Real-time speaker identification using the AEREAR2 event-based silicon cochlea
A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder
Workload-Aware Routing (WAR) for Network-on-Chip Lifetime Improvement
A mixed-signal CMOS DTCNN chip for pixel-level snakes
Robust Diffusion Average Strategy Over Distributed Networks with Impulsive Link Noise
CNTFET 8T SRAM cell performance with near-threshold power supply scaling
The VLSI design of de-interlacing with scene change detection
On the optimal transform for vector quantization of images
A mm-Wave Coupler-based Dual-band Power Amplifier for Advanced Driver Assistance Systems
Symmetrical Buffered Clock Tree Synthesis Considering NBTI
Fixed-point analysis of adaptive filters based on the EDS algorithm
Stochastic decoding for LDPC convolutional codes
Reduction on Power Dissipation of Filters Based on Local-Feedback Amplifier
A Current Mirror Cross Bar Based 2.86-TOPS/W Machine Learner and PUF with <2.5% BER in 65nm CMOS for IoT Application
Estimation of MOSFET Channel Noise and Noise Performance of CMOS LNAs at Cryogenic Temperatures
Neural network handoff in shadow-Rayleigh fading
A multistandard FFT processor for wireless system-on-chip implementations
An integrated H.263 video CODEC with protocol processor
A new successive elimination algorithm for fast block matching in motion estimation
An efficient parallelization technique for high throughput FFT-ASIPs
The relationship between music processing and electrocardiogram (ECG) in vegetative state (VS)
A Novel Tri-State Binary Phase Detector
A new approach for weighted least-square design of FIR filters
An advanced contrast enhancement using partially overlapped sub-block histogram equalization
Using invisible watermarks to protect visibly watermarked images
Extended RLS lattice adaptive filters
A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications
A 19.5mW 1.5V 10-bit pipeline ADC for DVB-H systems in 0.35µm CMOS
Incremental Learning Meets Reduced Precision Networks
Optimal user weighting fusion in DWT domain on-line signature verification
Ultra-Low Power Analog Multiplier Based on Translinear Principle
A distributed FIFO scheme for on chip communication
A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discrimination
Deriving optimal silicon neuron circuit specifications using Data Assimilation
Using a Scaling Factor in O(1/N) for the fixed-point implementation of the second-order goertzel filter
A high voltage zero-static current voltage scaling ADC interface circuit for micro-stimulator
Geometric structure of sum-of-rank-1 decompositions for n-dimensional order-p symmetric tensors
Allocating usages of voltage security margin in deregulated electric markets
Feed-forward path and gain-scaling - a swing and distortion reduction scheme for second order sigma-delta modulator
Enhancing industry participation in ISCAS and Circuits and Systems Society
A power constrained simultaneous noise and input matched low noise amplifier design technique
Algorithmic aspects in RF Circuit Simulation
Hardware Security Chip Based on PUF Technology for Real-time Respiratory Disease Diagnosis System Protection
1.3A, -2V Tolerant Solenoid Drivers for Pedestrian Protection in Active Hood Lift Systems
Placement with symmetry constraints for analog layout using red-black trees
Analysis of parallel processor architectures for the solution of the Black-Scholes PDE
Human body channel energy harvesting scheme with -22.5 dBm sensitivity 25.87% efficiency threshold-compensated rectifier
Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators
Minimally invasive pseudo-continuous blood glucose monitoring: Results from in-vitro and in-vivo testing of the e-Mosquito
Equivalent output-filtering using fast QRD-RLS algorithm for burst-type training applications
A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs
Offset-compensated Area-efficient Switched-capacitor Sum-gain Amplifier
A Universal Approach to Developing Fast Algorithm for Simplified Order-16 ICT
A closed form expression for TSV-based on-chip spiral inductor
Efficient power clock generation for adiabatic logic
A five-level neutral-point-clamped H-bridge PWM inverter with superior harmonics suppression: a theoretical analysis
Efficient path metric access for reducing interconnect overhead in Viterbi decoders
A high fill-factor native logarithmic pixel: Simulation, design and layout optimization
The new improved pseudo fractional-N clock generator with 50% duty cycle
Power management system for a capsule endoscope using autofluorescence imaging
On-line learning applied to power system transient stability prediction
Adaptive antenna systems for mobile ad-hoc networks
An accurate statistical yield model for CMOS current-steering D/A converters
A new LMS-based Fourier analyzer in the presence of frequency mismatch
On the effects of timing jitter in charge sampling
A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques
Memristor models for SPICE simulation of extremely large memristive networks
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues
Chaos in Fully Digital Circuits: A Novel Approach to the Design of Entropy Sources
A new concept for flash AD conversion
Experimental validation of a novel adaptive controller for piecewise affine systems
Multilevel PWM for single-phase power factor pre-regulator
An On-Chip Clock Generation Circuit for Smart Catheters
High level specification of embedded listeners for monitoring of Network-on-Chips
Bang-bang phase detector model revisited
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit
Analogue CMOS circuit implementation of a dopamine modulated synapse
Uplink channel estimation for space-time block coded multiple-input multiple-output MC-CDMA systems
Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm
A novel method for detection of aliased frequency components in FFT-based spectrum analysers and digital oscilloscopes
Quadrature VCO based on direct second harmonic locking
A Switched-Photovoltaic Ladder DC-DC Converter for High Harvesting Efficiency under Nonuniform Illumination
Teaching electronic circuits online: Lessons from MITx's 6.002x on edX
A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems
Modified Gilbert transconductance multiplier
Index assignment design for three-description lattice vector quantization
Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip
A parallel fast algorithm of Volterra adaptive filters
Mixed Deterministic and Pseudorandom Test Vector Generator Based on Cellular Automata Structures
An Approximate and Iterative Posit Multiplier Architecture for FPGAs
A neural processing node with on-chip learning
Duty Cycle Shift Keying data transfer technique for bio-implantable devices
A MOSFET bridge fluid biosensor
Optimization method for designing filter bank channelizer of a software defined radio using vertical common subexpression elimination
Encoding and transcoding multiple video objects with variable temporal resolution
A FIR baseband filter for high data rate 60-GHz wireless communications
A 6Gb/s adaptive equalizer using overshoot control in 0.18µm CMOS technology
Hardware-Oriented Dual Stream Object Recognition System using Binarized Neural Networks
Fast Style Transfer with High Shape Retention
A deterministic dynamic element matching approach to ADC testing
Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications
Floorplanning for Low Power Designs
Pinning a Complex Network through the Betweenness Centrality Strategy
CLFusion: 3D Semantic Segmentation Based on Camera and Lidar Fusion
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT
A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA)
Communication-aware design flow for dependable networked embedded systems
Effects of Quantiation noise in Parallel Arrays of Analog-to-Digital Converters
Near-perfect cover image recovery anti-multiple watermark embedding approaches
FCCQA: A High-Performance FPGA-based Accelerator for Approximate Nearest Neighbor Search
Power and area efficient high speed analog adaptive equalization
A circuit-oriented geometrical approach in predicting subharmonic oscillation of dc-dc converters with voltage-mode control
On network-based leader-following consensus of linear multi-agent systems
Chaos from Orbit-Flip Homoclinic Orbits Generated in Real Systems
FPGA-Memory Tradeoff in the High-Level Synthesis of FPGA-Based Reconfigurable Systems
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing
A Scalable Annealing Processing Architecture for Fully-Connected Ising Models
A Hyperstable Adaptive Line Enhancer for Frequency Estimation
Design of an optimal layout RF passive polyphase filter for large image rejection
Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models
Dynamically Adaptive Accumulator for in-sensor ANN Hardware Accelerators
Lossless, near-lossless and lossy adaptive coding based on the lossless DCT
Efficient high-throughput architectures for high-speed parallel scramblers
Design of a generalized phase-controlled class E inverter
Region incrementing visual secret sharing scheme based on random grids
A fast convergent algorithm for identification of noisy autoregressive signals
Cognitive Radio Circuits and Systems - Application to Digitizers
A greedy pursuit algorithm for arbitrary block sparse signal recovery
A Robust Spike-based Gas Identification Technique for SnO2 Gas Sensors
Multi-scale Adaptive Dual Attention for Image Defocus Blur Detection
Modeling all-MOS log filters and its application to Sigma-Delta modulators
Synchronization in Ladder-Coupled Chaotic Circuits Including Ring Structures
A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection
MMSE equalization for bandwidth-efficient multicarrier systems
Low energy register allocation beyond basic blocks
Multi-cycle compress technique for high-speed IP in low-cost environment
A 2 V 0.25µm CMOS 250 MHz fully-differential seventh-order equiripple linear phase LF filter
Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor
A heuristic approach for power system measurement placement design
Performance-driven optimization for video accelerator design [video coding]
Performance analysis of algorithmic noise-tolerance techniques
Improved frame-layer rate control for H.264 using MAD ratio