yusuke1997/dblp-id-title huggingface dataset:
A State-Space Model for the Analysis of VCO-Based Filters using PFM
Simulation and validation of arbitrary ordered VSCP-PLLs using event-driven macromodeling
Tolerance design of DC-DC switching regulators
Convergence analysis of multiple imputations particle filters for dealing with missing data in nonlinear problems
Live demonstration: A highly sensitive and quantitative fluorescence sensing platform, for disease diagnosis
Regression Based Mixed Signal Verification of an Ambient Light Sensor Interface
Spatial error concealment based on directional decision and intra prediction
Stability robustness of interconnected discrete time systems with synchronization errors
Jitter error spectrum for NRZ D/A converters
Power management system for ultra-low power energy harvesting applications
Least-Squares Multiple Frequency Estimation using Recursive Regression Sum of Squares
A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing
An FPGA-based Quantization and Acceleration Framework for Multi-DNN
Optimisation of RO-PUF Design Parameters for Minimising the Effective Area per PUF Bit
2.4 GHz RF down-conversion mixers in standard CMOS technology
An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing
QoS technologies on AV/CE-oriented wireless home network
Integrated near-end acoustic echo and noise reduction systems
A single CMOS chip for biocell trapping, levitation, detection and characterization
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
Social relation-aware SVC-based video streaming system over P2P network
Fast Mode Decision Algorithm for Spatial and SNR Scalable Video Coding
Transient Simulation of Nonuniform Transmission Lines by Asymptotic Waveform Evaluation
Efficient interconnect modeling by Finite Difference Quadrature methods
Analysis of analog to digital converter based on single-electron tunnelling transistors
A Calibration Free 8-to-12 b, 1-to-20 MSPS Reconfigurable SAR ADC with Optimized Window-Switching Scheme
On efficient extraction of partially specified test sets for synchronous sequential circuits
Channel characterization for galvanic coupled in vivo biomedical devices
On use of averaging in FxLMS algorithm for single-channel feedforward ANC systems
Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding
Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 nm CMOS Process
Formulation of INL and DNL yield estimation in current-steering D/A converters
A 230 MHz 8 tap programmable FIR filter using redundant binary number system
A Pipelined A/D Conversion Technique with Low INL and DNL
Quadrature mismatch shaping with a complex, tree structured DAC
Analysis of CORDIC-based triangularization for MIMO MMSE filtering
Analysis of Mean-Square-Error (MSE) for fixed-point FFT units
Restoration of three dimensional microscopic images using the row action projection method
Event-Based Containment Control of Multi-Agent Systems Without Velocity Measurements
Design and implementation of a Radix-100 division unit
Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies
DCT-domain image registration techniques for compressed video
Nonlinear output feedback control of TCP/AQM networks
Fully integrated charge sensitive amplifier for readout of micromechanical capacitive sensors
Highly efficient compact size 0.7W broad bandwidth power amplifier
A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator
An HVDC-based controller design for stabilization of frequency oscillation
A New Approach for Improving the Convergence Performance of Global Optimization Problems
A chip design of radix-4/2 64b/32b signed and unsigned integer divider using Compass cell library
Metalization Enhanced Latch-Based PUF With 1.29% Native Instability
Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers
Improving the performance of deadlock recovery based routing in irregular mesh NoCs using added mesh-like links
Handwritten Numeral Recognition with Multiple Features andd Multistage Classifiers
Multi-Objective Spiking Neural Network for Optimal Wind Power Prediction Interval
Methodology for analog technology porting including performance tuning
An Adaptive Neural Network VQ Algorithm and Its Implementation on the DSP32C Signal Processor
A low store energy and robust ReRAM-based flip-flop for normally off microprocessors
Construction of regular 3D point clouds using octree partitioning and resampling
Single and Sequential Viewports Prediction for 360-Degree Video Streaming
Adaptivity figures of merit and K-rail diagrams - comprehensive performance characterization of low-noise amplifiers and voltage-controlled oscillators
A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration
A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics
Cellular-array power-sum circuits over programmable finite field GF(2''')
Hardware-oriented adaptive multi-resolution motion estimation algorithm and its VLSI architecture
A Unified Analytical Solution for Bipolar, Unipolar, and Multistep SHE Converters
A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design
A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic
On VLSI decompositions for d-ary de Bruijn graphs (extended abstract)
A new reliable supplied gate drive circuit for SCRs with breakover diodes for protection
Wavelet transform to hybrid support vector machine and hidden Markov model for speech recognition
A stimulation platform for optogenetic and bionic vision restoration
Energy reduction of ultra-low voltage VLSI circuits by digit-serial architectures
Tool Management in an Electronic CAD Framework
Design considerations for a 10 GHz CMOS transmit-receive switch
RRAM-Based Analogue Artificial Neuron for Gaussian Activation Function Edge Classifier
Analog signal processing solutions for particle physics detectors: Upgrade of the LHCb calorimeter electronics
Runtime mitigation of illegal packet request attacks in Networks-on-Chip
Analytical design for resonant inductive coupling wireless power transfer system with class-E inverter and class-DE rectifier
Gramian-preserving frequency transformation for linear continuous-time state-space systems
Comparison of synthesized bus and crossbar interconnection architectures
Frame-layer H.264 rate control improvement using Lagrange multiplier and quantizer
An adaptive analog video line driver with impedance matching based on peak detection
Linearization of ADCs via digital post processing
A time-based technique for a resistive detector
Multiple region-of-interest image coding with embedded watermark
Adaptable MOS current mode logic for use in a multi-band RF prescaler
A combinational digital logic approach to STDP
On the Design of Error Cancellation Network for MASH Sigma-Delta-Frequency discriminators
Efficient and Correct Compilation of Quantum Circuits
Parallel Processing of Two-Dimensional Sequences Using 2-D Denominator-Separable digital Filters
Short Floating-Point CNN Accelerator for Brain-Computer Interface to Decode Visual Information
Linear cellular neural networks
Experimental performance evaluation of a low-EMI chaos-based current-programmed DC/DC boost converter
150 µA CMOS Transconductor with 82 dB SFDR
On noisy FIR filtering via total least squares estimation
Design of nonrecursive 2-D digital filters using semidefinite programming
In-pixel generation of gaussian pyramid images by block reusing in 3D-CMOS
Content-aware layered compound video compression
Low complexity parallel Chien search architecture for RS decoder
A New Metric to Find the Most Vulnerable Node in Complex Networks
A 0.816nW 12.3pS Tunable Low-Gm Transconductor for Bio-electrical Signal Acquisition
Discrete space continuous time 2D delay block using 2D all-pass frequency planar networks
All-digital linear regulators with proactive and reactive gain-boosting for supply droop mitigation in digital load circuits
Low-delay View Random Access for Multi-view Video Coding
A 6.86mW 1.5 GS/s 9 b Pipelined SAR ADC with TDC-Assisted Residue Quantization
A Wideband LNA with Active Balun for DVB-T Application
Stochastic model and simulation of a random number generator circuit
Estimation of current density distributions from EEG/MEG data by maximizing sparseness of spatial difference
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model
The Design of Computationally efficient Narrowband and Wideband Sharp FIR Filters
5.2 GHz self-powered lock and roll radio using VCO injection-locking and on-chip antennas
Piecewise BJT process spread compensation exploiting base recombination current
LATextSpotter: Empowering Transformer Decoder with Length Perception Ability
Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits
Digital Twin Assisted Performance Aware Power Management for FPGA MPSoC using High Speed Reinforcement Learning
A wideband down conversion mixer with dual cross-coupled loops for software defined radio
On-Line Histogram Equalization for Flash ADC
Amplitude detection inside CMOS LC oscillators
Neural network stream processing core (NnSP) for embedded systems
Fast implementations of Montgomery's modular multiplication algorithm
Architectural issues in base-station frequency synthesizers
Stereoscopic images generation with directional Gaussian filter
On scalable spiking convnet hardware for cortex-like visual sensory processing systems
Single Processor Design for 2-D Wiener Filter
Run-time SoC memory subsystem mapping of heterogeneous clients
An efficient skipping method of H.264/AVC weighted prediction for various illuminating effects
A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links
eUTDSP: a design study of a new VLIW-based DSP architecture
Memory conflict analysis for a multi-standard, reconfigurable turbo decoder
Performance of an adaptive homodyne receiver in the presence of multipath, Rayleigh-fading and time-varying quadrature errors
An Effective Digital Calibration Method Based on Volterra Neural Network for Pipeline ADCs
Nonlinear dynamics and switching time bifurcations of a thyristor controlled reactor
Self-Tuning RIS Controller for Vehicular Communications: A Hardware Perspective
Chip-interleaved block-spread CDMA for the downlink with inter-cell interference and soft hand-off
Two-tone PLL for on-chip IP3 test
A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS
Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support
Measurement location analysis for information embedded power systems
Reconciliation of methods for bipolar transistor thermal resistance extraction
A novel design of leading zero anticipation circuit with parallel error detection
A Compact GaNFET-Based Power Amplifier for ASIC-Based Miniature NMR Spectrometers
Fully integrated charge pump for high voltage excitation of a bulk micromachined gyroscope
Joint carrier recovery and adaptive equalization for high-order QAM
Modeling a resonant LC tank circuit embedded in a VCO
Design of Approximate Restoring Dividers
A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers
A Two Legs Darlington Based Circuit for on Site Tracing of Solar Panels I-V Curve
Near-carrier oscillator spectrum due to flicker and white noise
A subspace multiuser beamforming algorithm for downlink in mobile communication systems
Accelerating Tiny YOLOv3 using FPGA-Based Hardware/Software Co-Design
Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits
Reducibility of RLC networks over F xi
Accurate modeling of simultaneous switching noise in low voltage digital VLSI
Robust Semantic Communication for UAV Control with Integrated Trajectory Prediction
A novel delta-sigma modulator using resonant-tunneling quantizers
AxRSU: Approximate Radix-4 Squarer Unit
Neural Models of Ferrite Inductors Non-Linear Behavior
Retraining-free Constraint-aware Token Pruning for Vision Transformer on Edge Devices
Prototype filter design for subband adaptive filtering structures with critical sampling
On synthetic AER generation
A novel LNA-mixer design with on-chip balun
GPU based sample adaptive offset parameter decision and perceptual optimization for HEVC
A Gaussian Synapse Circuit for Analog VLSI Neural Networks
A Phase Noise Model Based on Multi-Loop Control System Theory Applied to Feed-Forward Ring Oscillators
Current readout circuit using two-stage amplification method for 64-channel CNT arrays
Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space
A new interpolation technique for TI ΣΔ A/D converters
An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors
Mixed-Order Sturdy MASH Delta-Sigma Modulator
A Paralleled Greedy LLL Algorithm for 16×16 MIMO Detection
A neural network approach to predict the crosstalk in non-uniform multiconductor transmission lines
A heteroclinic point and basin boundaries in a piecewise linear chaotic neuron model
A New Pulse-Compression Circuit With Residual Energy Recovered
Robust digital image-in-image watermarking algorithm using the fast Hadamard transform
An accurate method for fourier synthesis of photoplethysmographic signals
A new concept of continuous-time narrow bandpass Q-varying filter with transient suppression
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors
Design of a third-order ΣΔ modulator with minimum op-amps output swing
Dynamic modelling of analog integrated filters for the stability study of on-chip automatic tuning loops
The minimum number of live minimal structural traps to make an arbitrary minimal structural deadlock lve in general Petri nets
A Low-Power Low-Resistance Switched-Capacitors Bandgap Reference Generator with -40°C to 175°C Operative Range
A new image interpolation method for increasing the frame rate in multimedia and virtual reality applications
A novel approach for high-level power modeling of sequential circuits using recurrent neural networks
MEMS with Σ - Δ type of feedback loop control as an iterative map
Mechanism for taming chaos by weak harmonic perturbations
FPGA implementation of block truncation coding algorithm for gray scale images
Switched-capacitor (SC)/switched inductor (SL) structures for getting hybrid step-down Cuk/Sepic/Zeta converters
HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy
Three-phase high-power-factor rectifier with three AC power switches
Real-time 3D Pose Reconstruction of Human Body from Monocular Video Sequences
A Novel High-Accuracy Inductor-Current Estimator for Digitally-Controlled Synchronous DC-DC Buck Converters
Power supply topologies for biphasic stimulation in inductively powered implants
A 1.4G samples/sec comb filter design for decimation of sigma-delta modulator output
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
Closed-Loop Neuromorphic Deep Brain Stimulation using Deep Spiking Q-Networks
Low voltage class AB output stages for CMOS op-amps using floating capacitors
Intelligent Rapid Antenna Design with Integrated Impedance Matching Network for Wireless Communication System
Near-threshold CNTFET SRAM cell design with removed metallic CNT tolerance
A DC-6 GHz, 50 dB dynamic range, SiGe HBT true logarithmic amplifier
Design and performance analysis of DS-UWB rake receiver
Spike Decoders for Regressing Arm Angle for Autonomous Stroke Rehabilitation System
Two floating resistor circuits and their applications to synaptic weights in analog neural networks
Living and Dealing with RF Impairments in Communication Transceivers
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter
Information capacity and power efficiency in operational transconductance amplifiers
Adaptive L-Filters Based on Fuzzy Rules
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects
A CMOS-Integrated Radar-Assisted Cognitive Sensing Platform for Seamless Human-Robot Interactions
Enhanced line-based intra prediction with fixed interpolation filtering
Proposal & Investigation of Schottky Ring Engineered Reconfigurable Nanowire Transistor
Circuit-Level Evaluation of the Generation of Truly Random Bits with Superparamagnetic Tunnel Junctions
Using Reduced Graphs for Efficient HLS Scheduling
3D Bridge Super-resolution Crossbars
A low-complexity scanned-array 3D IIR frequency-planar filter
Estimation of supply current spectrum for early noise evaluation
An Object-based Approach to Plenoptic Video Processing
Sparse Signal Reconstruction Using Multi-Sequential Lp Optimization
A 2.4 V, 12 mW stereo audio D/A converter with double sampling switching
XML-based customization along the scalability axes of H.264/AVC scalable video coding
A widely tunable balun based on 2-port N-path bandpass filters with embedded phase shifting
Energy efficient SQRD processor for LTE-A using a group-sort update scheme
Magnetizing inrush current of a transformer and a new technique of its computation
Efficient digital self-calibration of video-rate pipeline ADCs using white Gaussian noise
Designing multiplier blocks with low logic depth
Characterization of the residual self-interference power in full-duplex wireless systems
A fully integrated multi-channel impedance extraction circuit for biosensor arrays
Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size
Review of CMOS implementations of the CNN universal machine-type visual microprocessors
Learning-based Image Coding for Machine Intelligence with Variable-Rate
A Fully Integrated Charge Pump with Double-Loop Control and Differentiator-based Transient Enhancer for Neural Stimulation Applications
Optimization of the data rate of an OOK CMOS medical transmitter based on LC oscillators
Fault Tolerant Adaptive Filters based on modified discrete fourier transform architectures
A Low-Noise High-Precision Dual-Mode Offset Calibration for High-Speed Dynamic Comparators
A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications
New CMOS Fully Differential Current Conveyor and its Application in Realizing Sixth Order Complex Filter
A nonlinear technique for image contrast enhancement and sharpening
A purely-VCO-based single-loop high-order continuous-time ΣΔ ADC
Sinusoidal Excitation on the Chua's Circuit Simulation of Limit Cycles and Chaos
An efficient algorithm for simultaneous wire permutation, inversion, and spacing
Signal recovery method for compressive sensing using relaxation and second-order cone programming
A Two-Stage CMOS Amplifier Performing High Degree of Stability for All Capacitive Load
On-the-fly speed and power scaling of an E-TSPC dual modulus prescaler using forward body bias in 0.25 μm CMOS
A field-programmable mixed-signal array architecture using antifuse interconnects
CIPL: A Fast and Low-Power Level Shifter for Wide-Range Voltage Conversion
Dynamic Partitioning for Concurrent Waveform Relaxation-based Circuit Simulation
A parallel/pipelined algorithm for the computation of MDCT and IMDCT
A Tri-Loop Capacitor-Less LDO with Current Feedback Loop and Super Source Follower Achieving 8-mV Undershoot and 99-dB PSR
A 2.1/5.2-NEF/PEF Capacitively Coupled Instrumentation Amplifier with Fast - Settling for Biosensor
Complex dynamics in cellular neural networks
A 4MHz Gm-C filter with on-chip frequency automatic tuning
Analog circuit synthesis using standard EDA tools
Power efficient AES core for IoT constrained devices implemented in 130nm CMOS
A low power UWB very low noise amplifier using an improved noise reduction technique
Faulter tolerant FIR adaptive filters with improved convergence behavior
Simultaneous Minimization of Pole and Zero Sensitivity in Digital Filter Design
Design space exploration on heterogeneous network-on-chip
Robustness of logic gates and reconfigurability of neuromorphic switching networks
A 0.35μm CMOS 200kHz-2GHz Fully-Analogue Closed-Loop Circuit for Continuous-Time Clock Duty-Cycle Correction in Integrated Digital Systems
Hardware implementation of a nonlinear processor
A current-mode interface cascade on COG(CiCC) for TFT-LCD systems
A Non-Intrusive Speech Quality Assessment Method for Low-Rate Communication
Multi-path Filters Robust to Substrate Noise and Nonlinearity
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications
Open source cell library Mono3D to develop large-scale monolithic 3D integrated circuits
Min-max interpolators and Lagrange interpolation formula
Accurate On-Chip Linearity Monitoring With Low-Quality Test Signal Generation
A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks
Sub-THz CMOS Phased-Array Transceiver Design for 6G
An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning
SONET transcoder design for ATM over SONET or directly over fiber
Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs
Synchronization and Control of Chaos by Occasional Linear Connection
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS)
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs
A MEMS micromagnetic actuator for use in a bionic interface
Improve 3D Feature Extraction and Fusion for Stage Diagnosis of Alzheimer's Disease
Hybrid systems view of power system modelling
New design methods of FIR filters with signed power of two coefficients based on a new linear programming relaxation with triangle inequalities
An analytical source-and-drain series resistance model of quarter micron MOSFETs and its influence on circuit simulation
A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS
MAC-DO: DRAM-Based Multi-Bit Analog Accelerator Using Output Stationary
A novel encoding method into sequence-pair
Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme
A CMOS Axon-sharing Neuron Array with Background Calibration
Design and Implementation of Sigma-delta DPWM Controller for Switching Converter
A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC
A 16.4pJ/bit Fully Integrated IR-UWB Transmitter with PSK+PPM Modulation and On-Chip Antenna
Cross-dimensional quality assessment for low bitrate video
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area
Stably-freeness and multidimensional systems with structural stability
The CMOS/nano interface from a circuits perspective
A Semi-Folded Based High-Power-Efficiency FFT for Frequency Offset Estimate
A pseudo-adaptive fuzzy controller using hybrid T-operator concept
Visual-weighted motion compensation frame interpolation with motion vector refinement
Low power digital signal processing scheme via stochastic logic protection
Improving DPA resistance of S-boxes: How far can we go?
A Hardware Architecture for Video Rate Shading of Volume Data
Implementation of space-efficient voltage-insensitive capacitances in integrated circuits
Graph-Based Salient Object Detection using Background and Foreground Connectivity Cues
S-code: new distance-3 MDS array codes
Delay propagation for a High-speed Railway Network with the Consideration of Primary Delay Derivation
Multi-Threaded Processor for Image Generation
On the theoretical lower bound of the multiplicative complexity for DCT
Micromachined microphone with optical interferometric readout
A study of SPT-term distribution of CSD numbers and its application for designing fixed-point linear phase FIR filters
Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology
An efficient architecture of DCTQ module in MPEG-4 video codec
Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers
How many solutions does a SAT instance have?
A WCDMA/HSDPA baseband processor