yusuke1997/dblp-id-title huggingface dataset:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCs
NCUBE: an automatic test generation program for iterative logic arrays
Fast path-based timing analysis for CPPR
Detection Through Deep Neural Networks: A Reservoir Computing Approach for MIMO-OFDM Symbol Detection
On Topological Via Minimization and Routing
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU
Soft error derating computation in sequential circuits
Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning
A vectorless estimation of maximum instantaneous current for sequential circuits
Shielding and securing integrated circuits with sensors
Estimation of power sensitivity in sequential circuits with power macromodeling application
A tool for hierarchical test generation
Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations
Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture Design Optimization?
Accurate power estimation for large sequential circuits
Security engineering of nanostructures and nanomaterials
Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect
Incremental partitioning-based vectorless power grid verification
OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization
Making the Fault-Tolerance of Emerging Neural Network Accelerators Scalable
Variability and yield improvement: rules, models, and characterization
Hardware/software partitioning of software binaries
Estimation of signal arrival times in the presence of delay noise
DisQ: A Novel Quantum Output State Classification Method on IBM Quantum Computers using OpenPulse
Function unit specialization through code analysis
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation
Validating direct memory access interfaces with conformance checking
Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes
BSG-Route: a length-matching router for general topology
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Symbolic model checking of process networks using interval diagram techniques
Towards Assurance Evaluation of Autonomous Systems
The epsilon-approximation to discrete VT assignment for leakage power minimization
Arjun: An Efficient Independent Support Computation Technique and its Applications to Counting and Sampling
A statistical study of the effectiveness of BIST jitter measurement techniques
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects
Squat: Quant Small Language Models on the Edge
TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer Acceleration
SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory Computing
Mixed-cell-height placement considering drain-to-drain abutment
Be careful with don't cares
Reduced-order modelling of linear time-varying systems
Optimizing data locality using array tiling
e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving
Network flow based circuit partitioning for time-multiplexed FPGAs
Overlay aware interconnect and timing variation modeling for double patterning technology
Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning
Extending ML-OARSMT to net open locator with efficient and effective boolean operations
Board driven I/O planning & optimization
The Calculation of Signal Stable Ranges in Combinational Circuits
Using constraint geometry to determine maximum rate pipeline clocking
Design and manufacturing process co-optimization in nano-technology
Cyclist: Accelerating hardware development
Latchup-aware placement and parasitic-bounded routing of custom analog cells
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies
MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNs
A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays
Full State Quantum Circuit Simulation Beyond Memory Limit
An Agile Precision-Tunable CNN Accelerator based on ReRAM
The Impedance Fault Model and Design for Robust Impedance Fault Testability
The Fellowship of the Leak: Power Analysis of a Masked FrodoKEM Hardware Accelerator
Post-placement power optimization with multi-bit flip-flops
Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technology
Wirelength optimization by optimal block orientation
Synthesizing complementary circuits automatically
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines
Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations
A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers
Improving the efficiency of static timing analysis with false paths
SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon
SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning
CREST-a current estimator for CMOS circuits
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers
Record & play: a structural fixed point iteration for sequential circuit verification
An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling
Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)
LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs
Assured deep learning: practical defense against adversarial attacks
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer
Improving the Robustness of Redundant Execution with Register File Randomization
Hardware Acceleration of Robot Scene Perception Algorithms
The impact of the nanoscale on computing systems
Logic synthesis for large pass transistor circuits
A General and Exact Routing Methodology for Digital Microfluidic Biochips
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Generalized constraint generation in the presence of non-deterministic parasitics
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Making the Best Switch: Encoding Strategy Management for Efficient TFHE Circuit Evaluation
Efficient block-based parameterized timing analysis covering all potentially critical paths
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Dynamic Platform Management for Configurable Platform-Based System-on-Chips
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips
A new algorithm for topological routing and via minimization
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning Framework
Re-encoding sequential circuits to reduce power dissipation
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated
Engineering a scalable Boolean matching based on EDA SaaS 2.0
A Statistical Gate-Delay Model Considering Intra-Gate Variability
A methodology for fast and accurate yield factor estimation during global routing
Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
An efficient method for circuit sensitivity calculation using piecewise linear waveform models
Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost
A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement
Dynamic voltage and frequency management based on variable update intervals for frequency setting
COSIME: FeFET Based Associative Memory for In-Memory Cosine Similarity Search
Multi-Threaded Simics SystemC Virtual Platform
Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion
A Hierarchical Approach for Testing Large Circuits
A selective pattern-compression scheme for power and test-data reduction
A Scalable Application-Specific Processor Synthesis Methodology
PROTON: an automatic place-and-route tool for optical networks-on-chip
Scalable-effort ConvNets for multilevel classification
Static Timing Analysis Using Interval Constraints
Partial scan delay fault testing of asynchronous circuits
Associative Memory Based Experience Replay for Deep Reinforcement Learning
Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers
Basic concepts for an HDL reverse engineering tool-set
Pseudo-random testing and signature analysis for mixed-signal circuits
On modeling top-down VLSI design
New ATPG techniques for logic optimization
High-Level Delay Estimation for Technology-Independent Logic Equations
PCBFormer: Understanding 3D Structure of RealWorld PCB Traces for S-Parameter Prediction
Cbase 1.0: a CAD database for VLSI circuits using object oriented technology
SAT-based protein design
GRAFT: Graph-Assisted Reinforcement Learning for Automated SSD Firmware Testing
Protection Against Physical Attacks Through Self-Destructive Polymorphic Latch
A Clock Net Reassignment Algorithm Usign Voronoi Diagram
A Systematic Approach for Designing Testable VLSI Circuits
Design with FinFETs: design rules, patterns, and variability
Inserting active delay elements to achieve wave pipelining
A fast block structure preserving model order reduction for inverse inductance circuits
Methodology for standard cell compliance and detailed placement for triple patterning lithography
Minimum crosstalk switchbox routing
System Specification and Synthesis with the SpecCharts Language
Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC
The disjunctive decomposition of logic functions
Modeling and enhancing virtual memory performance in logic simulation
DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs
Optimal layer assignment for escape routing of buses
Integrating floorplanning in data-transfer based high-level synthesis
Integrating logic retiming and register placement
Nanolithography and CAD challenges for 32nm/22nm and beyond
On accelerating pattern matching for technology mapping
Efficient utilization of adversarial training towards robust machine learners and its analysis
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs
Timing analysis and optimization: from devices to systems (tutorial)
Measuring progress and value of IC implementation technology
Remote activation of ICs for piracy prevention and digital right management
Stick diagram extraction program SKELETON
Exploiting regularity for low-power design
Match and replace - A functional ECO engine for multi-error circuit rectification
DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution
Optimal 2-D cell layout with integrated transistor folding
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics
Enabling Decoder-only Language Model Inference on a CNN Accelerator
Efficient design space exploration for component-based system design
Multi-level logic optimization using binary decision diagrams
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions
Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operation
Invited Paper: Side Channel Vulnerability Analysis of Flexible Neuromorphic Circuits
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Event-EMU: an event driven timing simulator for MOS VLSI circuits
A Single-State-Transition Fault Model for Sequential Machines
Flexible Block-Multiplier Generation
Enabling Robust Inverse Lithography with Rigorous Multi-Objective Optimization
Robust mixed-size placement under tight white-space constraints
Accurate detection for process-hotspots with vias and incomplete specification
Verification of executable pipelined machines with bit-level interfaces
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits
Extending High-Level Synthesis with AI/ML Methods
LMLitho: A Large Vision Model-Driven Lithography Simulation Framework
SPIMA: Scalable and Cost-Efficient Sparse Matrix Multiplication via Processing in DRAM Array
Retiming sequential circuits for low power
Design automation issues for biofluidic microchips
Throughput optimization of general non-linear computations
Dataflow-driven memory allocation for multi-dimensional signal processing systems
Efficient model order reduction via multi-node moment matching
Finding Clusters in VLSI Circuits
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Refinement Strategies for Any-Angle Package Routing with I/O Alignment Consideration
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems
Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization
Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research
Arbitrary rectilinear block packing based on sequence pair
High-quality global routing for multiple dynamic supply voltage designs
Memory access optimization of dynamic binary translation for reconfigurable architectures
Sequential redundancy identification using recursive learning
Energy Efficient Real-Time Scheduling
Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper)
Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis
Background memory management for dynamic data structure intensive processing systems
BoostNoC: power efficient network-on-chip architecture for near threshold computing
Verification of asynchronous interface circuits with bounded wire delays
Binning optimization based on SSTA for transparently-latched circuits
Detailed layer assignment for MCM routing
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network
Risk-Aware and Explainable Framework for Ensuring Guaranteed Coverage in Evolving Hardware Trojan Detection
Verification of analog/mixed-signal circuits using labeled hybrid petri nets
Fast static analysis of power grids: Algorithms and implementations
Equivalent design representations and transformations for interactive scheduling
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration
Timing analysis in high-level synthesis
Efficient construction of binary moment diagrams for verifying arithmetic circuits
An Algorithmic Approach for Generic Parallel Adders
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation
Net characterization based channel router: FT router
Hierarchical partitioning
Interconnect in high speed designs: problems, methodologies and tools
A new high-order absolutely-stable explicit numerical integration algorithm for the time-domain simulation of nonlinear circuits
A robust finite-point based gate model considering process variations
Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
Formal specification and verification of a dataflow processor array
Novel test detection to improve simulation efficiency - A commercial experiment
Comprehensive procedure for fast and accurate coupled oscillator network simulation
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
A Case for CMOS/nano co-design
MASIM: An Energy-Efficient Multi-Array Scheduler for SIMD Logic-in-Memory Architectures
Expanded rectangles: a new VLSI data structure
More effective power-gated circuit optimization with multi-bit retention registers
Bit-level scheduling of heterogeneous behavioural specifications
Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing
iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement
Accurate delay computation for noisy waveform shapes
CAMSHAP: Accelerating Machine Learning Model Explainability with Analog CAM
Battery cell configuration for organic light emitting diode display in modern smartphones and tablet-PCs
A Theory of Non-Deterministic Networks
FastPep: a fast parasitic extraction program for complex three-dimensional geometries
Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applications
A unified approach to simulating electrical and thermal substrate coupling interactions in ICs
Reinforcement learning based power management for hybrid electric vehicles
Complementary use of runtime validation and model checking
Strain-aware performance evaluation and correction for OTFT-based flexible displays
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design
Personalized Heterogeneity-Aware Federated Search Towards Better Accuracy and Energy Efficiency
Congestion-Driven Placement Using a New Multi-Partitioning Heuristic
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs
An optimal algorithm for river routing with crosstalk constraints
Improved heuristics for finite word-length polynomial datapath optimization
Conjugate Direction Waveform Methods for Transient Two-Dimensional Simulation for MOS Devices
Co-manage power delivery and consumption for manycore systems using reinforcement learning
SPECS simulation validation with efficient transient sensitivity computation
Dynamical identification of critical paths for iterative gate sizing
High-level scheduling model and control synthesis for a broad range of design applications
ATPG for Noise-Induced Switch Failures in Domino Logic
Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems
Sparse and passive reduction of massively coupled large multiport interconnects
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
QScale: thermally-efficient QoS management on heterogeneous mobile platforms
Strategies for improving the parametric yield and profits of 3D ICs
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis
Rectilinear Steiner Tree Construction by Local and Global Refinement
Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track
Gate sizing by Lagrangian relaxation revisited
Trace alignment algorithms for offline workload analysis of heterogeneous architectures
Behavioral synthesis for easy testability in data path scheduling
QQ: Is 2-bit Enough? Exploiting Quantization to Enhance Computation and Memory Efficiency in Quantum Simulation
Partitioning around roadblocks: tackling constraints with intermediate relaxations
InterLock: An Intercorrelated Logic and Routing Locking
INA: Incremental Network Approximation Algorithm for Limited Precision Deep Neural Networks
Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks
Test of Future System-on-Chips
Fast and Fair Medical AI on the Edge Through Neural Architecture Search for Hybrid Vision Models
XREF/COUPLING: Capacitive Coupling Error Checker
A Min-Cost Flow Based Detailed Router for FPGAs
Simulation of Noise in Neurons and Neuronal Circuits
Combinational and sequential mapping with priority cuts
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Acceleration of Nested Conditionals on CGRAs via Trigger Scheme
A Contract Design Approach for Colocation Data Center Demand Response
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications
Revisit Choice Network for Synthesis and Technology Mapping
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits
Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning
SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs
False-Noise Analysis using Logic Implications
Optimal Module Implementation and Its Application to Transistor Placement
DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs
ISLU: Indexing-Efficient Sparse LU Factorization for Circuit Simulation on GPUs
Clock buffer polarity assignment for power noise reduction
Online clock skew tuning for timing speculation
Synthesis of address generators
Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells
Clustering-based simultaneous task and voltage scheduling for NoC systems
MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning
Variability in sub-100nm SRAM designs
Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs
IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020
Efficient VCO phase macromodel generation considering statistical parametric variations
A thermal-driven floorplanning algorithm for 3D ICs
TICER: realizable reduction of extracted RC circuits
Identifying the optimal energy-efficient operating points of parallel workloads
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms
GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method
Iterative Abstraction using SAT-based BMC with Proof Analysis
RSizing: Robust Bayesian Optimization for Analog Circuit Sizing Under Process Variations
Reinforcement Learning-Enhanced Cloud-Based Open Source Analog Circuit Generator for Standard and Cryogenic Temperatures in 130-nm and 180-nm OpenPDKs
Timing-aware power noise reduction in layout
Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality
A new heuristic for rectilinear Steiner trees
ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite
NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network
The Hercules CAD Task Management System
On channel segmentation design for row-based FPGAs
Applying GNNs to Timing Estimation at RTL
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill