yusuke1997/dblp-id-title huggingface dataset:
A Measurement and Analysis of Its Performance of Voice Data Transmission Systems with PDA over a Wireless Network
Dynamic Probabilistic Retransmission in Ad Hoc Networks
Modeling Attacks on Wireless Sensor Networks
Wireless Video Sensor Networks over Bluetooth for a Team of Urban Search and Rescue Robots
Wifi Mesh for HandHelds in Linux
Kernel Density Estimation for Wireless Fading Channels Using Slepian Semi-Wavelets
Eurecom IPv6 Soft Handover
Location Management by Sharing Individual Mobility Model Between Mobile Station and Wireless Network
GeoConnect: Geographic and Connectivity-Aware Routing Protocol for Wireless Sensor Network
Evaluate and Improvement of IPv4 to IPv6 Transition Mechanisms
An IV Collision Avoidance Algorithm - Strengthening the WEP
Performance Modeling for Voice over MANET in IEEE802.11b
Mobility in ATM Networks
Secure Routing in Ad Hoc Networks for Reactive Next Hop Routing Protocols
A New Efficient Technique for Network and Cluster Rekeying in Wireless Sensor Network based on Quarantining
QoS Enhancement Scheme for Real-Time Service in Ad Hoc Networks
Energy Efficient Algorithms for Static Ad Hoc Wireless Networks
A Topology Generator and Evolutionary Routing Algorithm for Random Deployment of Wireless Sensor Networks
Wireless Sensor Network for Landslide Detection
PSiS Mobile
Interference Effects on Heterogeneous Networks in the ISM Band
A Defense-In-Depth Approach to Secure Wireless LANs
Proceedings of the International Conference on Wireless Networks, ICWN '03, June 23 - 26, 2003, Las Vegas, Nevada, USA
A Study on Biological Data Transmission Performance of Wireless Sensor Networks for Cattle Feedlot
Routing Method Under Coexistence of Different Types of Multihop Transmissions in MANET
A Survey on Location Services for Position-Based Routing in Mobile Ad Hoc Networks
Performance Analysis of MANET Routing Protocols Using TCP Traffic for Freeway Mobility Model
A Trooper Selection Strategy on a Milepost Network
States-Detection-Based Reducing Power Use Method in Resource Discovery and Interaction
The Election Protocol for Reconfigurable Distributed Systems
Performance Issues for Wireless Web Servers
Optimizing the Location-aided Routing Protocol in Mobile Ad hoc Networks
Mitigating Congestion in Multi-hop Cellular Network with Distributed Routing
HEAPINGS: From Concept To Simulations
LPC Vocoders for Environmental Monitoring Using Wireless Sensor Networks
The WiTAG - a WiFi Sensor TAG
A Mobile IPv6 Study
A Cluster-Based Hybrid Proactive/Reactive Source Routing Protocol for Ad Hoc Wireless Networks
Data Dissemination using Limited Flooding in Wireless Sensor Networks
Performance Analysis of a Novel MAC Protocol For Service Differentiation In Wireless Network
Energy-Efficient Bootstrapping Protocol for Sensor Networks
TAP: Tree Based Code Propogation in Wireless Sensor Networks
An Efficient Data Dissemination Technique based on Squared Trajectory in Sensor Networks
Push-to-talk over Wi-Fi
Scenario-Based Performance Analysis of MAC Protocols for Wireless Sensor Networks
Mobility and Load Analysis of DSDV and DSR Mobile Ad hoc Routing Protocols
A New Lightweight and Scalable Encryption Algorithm for Streaming Video over Wireless Networks
Routing in Fast-Moving Mobile Ad Hoc Networks
Intelligent Pervasive Framework for Consumer-Supplier Interaction
A Bridge-Node Aided Multi-Hop Routing Scheme
Throughput Analysis of High-Speed Downlink Packet Access (HSDPA)
A Survey on Current and Future Pervasive Computing Devices and Applications
The Impact of Reduced Computational Complexity of Multiuser Detectors on the Processing Gain in a Wireless DS-CDMA Multiuser System
Comparison of DTN Routing Protocols and Their Buffer Utilization using ONE Simulator
Evaluating the Efficiency of Clustering on Routing and Network Performance
Enhanced Fixed and Dynamic Code Assignment Policies for OVSF-CDMA Systems
MAC-centric Hierarchical Cross-Layer Fuzzy Control for Video Streaming over the IEEE 802.11e Wireless Networks
A Scalable and Tunable Encryption Key Management Scheme for Mobile Ad Hoc Networks
On Mobility of MANETs-Overlaid P2P Rings
Survey of Vertical Handoff Models in Heterogeneous Wireless Networks
A Low Power Analog Front End Receiver for Wireless Personal Area Network
Performance Evaluation of Location Management Protocols for Mobile Ad Hoc Networks
An Indoor Bluetooth-Based Positioning System: Concept, Implementation and Experimental Evaluation
Cell Phone as a Portable Storage Device And Beyond
A Simple Two-Step Approach for Maximum Likelihood Target Localization Using Binary Data
Handoff Decision and Relative Mobility Estimation of Mobile Station in Dielectric Objects Interfered Environment
Scalable Multicast Location Service in Mobile Ad Hoc Networks
Layered Call Admission Policy for 3G Cellular Data Networks: A CDMA2000 Case Study
Improving New Calls Relative to Handover Calls
Modeling and Analysis of Multi-Hop Wireless Mobile Ad Hoc Networks Using the IEEE 802.11 DCF Protocol
Bitwise Block Acknowledgement Method for Multiple Segments Recovery of TCP on Unreliable Network
Performance Comparision of Ant Colony Algorithm and Approximate Algorithm for Reporting Cell Problem Under Total Signaling Cost
Spider-Net Zone Routing Protocol for Mobile Sink Wireless Sensor Networks
UDP Performance over an Ad Hoc Network for Mobile Robots
A Hybrid Routing Protocol for Wireless Mesh Networks
Performance Evaluation of 802.11b and 802.11g Standards in Ad-hoc Wireless Networks
Voice-Controlled Ubiquitous Computing
Concerns with Time-Space Based Wireless Security
Reduction of Cochannel Interference on the Downlink of a CDMA Cellular Architecture with Directional Antennas
Secure Routing in Wireless Mobile Ad Hoc Networks without the Support of Key Management Infrastructure
Multicast Routing Architecture in Ad-Hoc Network
Effective Bandwidth Allocation with Fairness Guarantee in WiMAX
GPS-less Speed Detection in VANET
Communication in the Smart Grid
A Novel MAC Scheme for Cellular Traffic in Packet CDMA Environment
Performance Analysis of Unified Transport Layer Protocols for Next Generation Wireless Internet
Routing Protocols for Sensor Networks
Detecting Primary Signals Using Time and Space Model
Flooding Features for the AODV Protocol
Estimating Base Station Requirements for 3G UMTS Services
Scaling Laws of Sampled Data and Many-to-One Capacity of Sensor Networks on Closed Surfaces
HEAPINGS: A Secure Counterintuitive Sensor Network Protocol
A bidirectional Bluetooth authentication scheme based on game-theoretic framwork
Efficient radio resource management for future mobile wireless networks using scalable resource allocation algorithm
An Authenicated Short Message Service (SMS)-Based Transactions System without SIM Modification
Effect of Adjacent WCDMA Network to 3G-1X Uplink Capacity in the 850 MHz Bands
A Probabilistic Routing Algorithm for DTNs of Randomly Moving Nodes
A Framework For Policy Based Coordinated Adaptation in Mobile Systems
Women and Technology: The Next Step in Bridging the Divide
Positioning Models for Context-Aware Applications
Analysis of Energy Harvesting for Vibration-Motivated Wireless Sensor Networks
Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications
Dynamic binary code translation for data prefetch optimization
Packing with Boundary Constraints for a Reconfigurable Operating System
Irregular Redistribution Scheduling by Partitioning Messages
Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications
Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings
Evolution of NAND Flash Memory Interface
Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining
A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance
UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems
A New On-the-fly Summation Algorithm
Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination
The Challenges of Massive On-Chip Concurrency
SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator
Multiple-Dimension Scalable Adaptive Stream Architecture
Performance models for Cluster-enabled OpenMP implementations
Architecture Design of a High-Performance 32-Bit Fixed-Point DSP
A Power-Efficient Processor Core for Reactive Embedded Applications
DHCP support for secure automatic detection of host status
The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip
Covert Channel Analysis of the Password-Capability System
Portable desktop applications based on user-level virtualization
An Online Profile Guided Optimization Approach for Speculative Parallel Threading
A Memory Bandwidth Effective Cache Store Miss Policy
Trace-Based Data Cache Leakage Reduction at Link Time
Cost/Performance Tradeoff of n-Select Square Root Implementations
Bipartition Architecture for Low Power JPEG Huffman Decoder
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization
Impact of Register-Cache Bandwidth Variation on Processor Performance
Performance Impact of Different Data Value Predictors
A study of integrating digital health network with UPnP in an elderly nursing home
A gather/scatter hardware support for efficient Fast Fourier Transform
A Router Architecture for QoS Capable Clusters
Building a Terabit Router with XD Networks
Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance
Streaming Networks for Coordinating Data-Parallel Programs (Position Statement)
Live Range Aware Cache Architecture
D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters
A New Hierarchy Cache Scheme Using RAM and Pagefile
Reconfigurable Instruction-Level Parallel Processor Architecture
Micro-Threading: A New Approach to Future RISC
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
A Novel Processor Architecture for Real-Time Control
Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures
Multi-threaded Microprocessors - Evolution or Revolution
Performance of the Achilles Router
Some Real Observations on Virtual Machines
An Auto-adaptative Reconfigurable Architecture for the Control
Quality improvement of sequential steady-state simulations for telecommunication networks
muTC - An Intermediate Language for Programming Chip Multiprocessors
A Bypass Mechanism to Enhance Branch Predictor for SMT Processors
Resource sharing control in Simultaneous MultiThreading microarchitectures
A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory
Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy
An Object-Oriented Data Storage System on Network-Attached Object Devices
Reducing Access Count to Register-Files through Operand Reuse
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures
Performance of Keyword Connection Algorithm in Nested Mobility Networks
Exploring Design Space Using Transaction Level Models
The Channel Assignment Algorithm on RP(k) Networks
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Issues and Support for Dynamic Register Allocation
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA
DSTRIDE: Data-Cache Miss-Address-Based Stride Prefetching Scheme for Multimedia Processors
Unbiased Branches: An Open Problem
A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels
Scientific Computing Applications on the Imagine Stream Processor
Pre-virtualization: Soft layering for virtual machines
The Development of System Software for Parallel Supercomputers
Make Computers Cheaper and Simpler
Choice Predictor for Free
An Integrated Partitioning and Scheduling Based Branch Decoupling
Heterogeneous Networks of Workstations
Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research
A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations
Quiz-based trust model with optimized resource management in grid
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy
Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability
Architectural Enhancements for Color Image and Video Processing on Embedded Systems
A multiple simple regular expression matching architecture and coprocessor for deep packet inspection
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture
Initial Evaluation of a User-Level Device Driver Framework
A DDL-Based Software Architecture Model
Understanding Prediction Limits Through Unbiased Branches
Diva: A dataflow programming model and its runtime support in Java virtual machine
Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor
Embedded Intelligent Imaging On-Board Small Satellites
Retargetable Cache Simulation Using High Level Processor Models
Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor
A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems
A Cost-Effective Supersampling for Full Scene AntiAliasing
A novel spatio-temporal adaptive bus encoding for reducing crosstalk interferences with trade-offs between performance and reliability
Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP
Dynamic Fetch Engine for Simultaneous Multithreaded Processors
Synchronization Mechanisms on Modern Multi-core Architectures
An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems
The First Real Operating System for Reconfigurable Computers
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
FPGA-Accelerated Active Shape Model for Real-Time People Tracking
Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform
Debugging of assembly library functions without target debugging tools
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications
Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems
FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit
Hamiltonian-cycle-based multicasting on wormhole-routed torus networks
A Study of the Performance Potential for Dynamic Instruction Hints Selection
WAN services lookup protocol
Runtime Performance Projection Model for Dynamic Power Management
Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures
A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs
An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips
Adaptive Interfacing with Reconfigurable Computers
A Register Allocation Framework for Banked Register Files with Access Constraints
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC
Implementations of Square-Root and Exponential Functions for Large FPGAs
Continuous Adaptive Object-Code Re-optimization Framework
Parallelization of spectral clustering algorithm on multi-core processors and GPGPU
Static Scheduling for Out-of-order Instruction Issue Processors
Investigating Enhanced Route Optimization for Mobile IPv6
Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems
5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia
Making Power-Efficient Data Value Predictions
Computation rotating for data reuse
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor
Arithmetic Circuits Combining Residue and Signed-Digit Representations
Analysis of Real-Time Communication System with Queuing Priority
dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization
Order Independent Transparency for Image Composition Parallel Rendering Machines
Mapping Applications to a Coarse Grain Reconfigurable System
Real-Time Three Dimensional Vision
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks
Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures
Legba: Fast Hardware Support for Fine-Grained Protection
Towards an Asynchronous MIPS Processor
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution
Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols
Branch Behavior Characterization for Multimedia Applications
A Novel Architecture for Genomic Sequence Searching and Alignment
Design and Implementation of Java Processors
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories
A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions
Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor
Targeted Data Prefetching
Automated Component Adaptation by Forced Simulation
Processor Directed Dynamic Page Policy
A Fault-Tolerant Single-Chip Multiprocessor
Entropy-Based Profile Characterization and Classification for Automatic Profile Management
Embedding of Cycles in the Faulty Hypercube
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors
The Circuit Object Organization Library
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA
Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm
Analyzing the impact of data prefetching on Chip MultiProcessors
An Innovative Instruction Cache for Embedded Processors
Mechanism for return stack and branch history corrections under misprediction in deep pipeline design
Concurrency engineering
PMPS(3): A Performance Model of Parallel Systems
A Novel Rename Register Architecture and Performance Analysis
On energy-efficient semi-asynchronous MAC protocols for multi-hop ad-hoc networks
A Power-Aware Alternative for the Perceptron Branch Predictor
Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation
Comparing Low-Level Behavior of SPEC CPU and Java Workloads
Tandem virtual machine - An efficient execution platform for GALS language SystemJ
Password-Capabilities: Their Evolution from the Password-Capability System into Walnut and Beyond
Latency Improvement in Virtual Multicasting
Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs
Speculative Issue Logic
Register Allocation on Stream Processor with Local Register File
Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors
Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors
Modularized Redundant Parallel Virtual File System
MediaMem: A dynamically adjustable memory subsystem for high-bandwidth required multimedia SoC systems
Improving the Performance of GCC by Exploiting IA-64 Architectural Features
User-Level Management of Kernel Memory
Overload Protection for Commodity Network Appliances
Using Branch Prediction Information for Near-Optimal I-Cache Leakage
Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling
How Can the Earth Simulator Impact on Human Activities
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs
Dataflow Java: Implicitly Parallel Java
An Anticipative Recursively-Adjusting Mechanism for redundant parallel file transfer in data grids
Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction
Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings
Increasing Embedding Probabilities of RPRPs in RIN Based BIST
Acceleration Techniques for Chip-Multiprocessor Simulator Debug
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures
A Two-Level On-Chip Bus System Based on Multiplexers
Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory
A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling
On the Feasibility of Fixed-Length Block Structured Architectures
An ALU cluster with floating point unit for media streaming architecture with homogeneous processor cores
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision
Designing Ultra-large Instruction Issue Windows
Design of an Efficient Flexible Architecture for Color Image Enhancement
Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor
Components + Security = OS Extensibility
Reorganizing UNIX for Reliability
MOOSS: CPU Architecture with Memory Protection and Support for OOP
Implementation of a Hybrid TCP/IP Offload Engine Prototype
Optimal Placement of Frequently Accessed IPs in Mesh NoCs
Reliable Systolic Computing Through Redundancy
Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings
Design of a Reconfigurable Cryptographic Engine
6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland, Australia
Constructing Node-Disjoint Paths in Enhanced Pyramid Networks
Open Issues in MPI Implementation
Morphable Structures for Reconfigurable Instruction Set Processors
A partial memory protection scheme for higher effective yield of embedded memory for video data
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures
Desktop search in the intranet with integrated desktop search engines
The Era of Multi-core Chips -A Fresh Look on Software Challenges
A Low Power Branch Predictor to Selectively Access the BTB
DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques
A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks
A Hybrid protocol for Cluster-based wireless sensor networks
Enhancing robustness of an iSCSI-based file system in wireless networks
A Simulator for High Speed Digital Communications
StarDBT: An Efficient Multi-platform Dynamic Binary Translation System
A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time
A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling
Architectural Solution to Object-Oriented Programming
Adaptive Middleware for Heterogeneous Defense Networks-An Exploratory Simulation Study
Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control
Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks
Performance Evaluation of a Partial Retraining Scheme for Defective Multi-Layer Neural Networks
Combining Wireless Sensor Network with Grid for Intelligent City Traffic
A Stream Architecture Supporting Multiple Stream Execution Models
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks
A study on periodic shutdown for adaptive CMPs in handheld devices
LogSPoTM: a scalable thread level speculation model based on transactional memory
Cycle Period Analysis and Optimization of Timed Circuits
Saving register-file static power by monitoring short-lived temporary-values in ROB
A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To?