yusuke1997/dblp-id-title huggingface dataset:
2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme
20.1 A light-load-efficient 11/1 switched-capacitor DC-DC converter with 94.7% efficiency while delivering 100mW at 3.3V
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS
6.2 A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power Back-Off Operating in the 5GHz Band
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections
23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications
27.1 A 3-Axis MEMS Gyroscope with 2.8ms Wake-Up Time Enabled by a 1.5µW Always-on Drive Loop
Student research preview
Cascading Techniques for a High-Speed Memory Interface
184QPS/W 64Mb/mm 2 3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System
Session 2 overview: Power amplifiers
3.3 A Passive Switched-Capacitor-Based Multimode Amplifier with a Logarithmic Conformity Error of 0.75 % from -25 to 200°C
A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna
A 90%-Efficiency 40.68MHz Single-Stage Dual-Output Regulating Rectifier with ZVS and Synchronous PFM Control for Wireless Powering
A 3.47 NEF 175.2dB FOMs Direct Digitization Front-End Featuring Delta Amplification for Enhanced Dynamic Range and Energy Efficiency in Bio-Signal Acquisition
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector
19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology
A Triturated Sensing System
Session 6 overview: Image sensors
A 28nm Multimode Multiband RF Transceiver with Harmonic-Rejection TX and Spur-Avoidance RX Supporting LTE Cat1bis
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS
An 8.6GHz 42ps pulse-width electrical mode-locked oscillator
28.4 A CMOS Multimodality In-Pixel Electrochemical and Impedance Cellular Sensing Array for Massively Paralleled Synthetic Exoelectrogen Characterization
22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS
Session 10 overview: Advanced wireline transceivers and PLLs
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS
25.5 A 320GHz subharmonic-mixing coherent imager in 0.13µm SiGe BiCMOS
5.5GHz system z microprocessor and multi-chip module
A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput
12.6 Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimization
15.4 A Neuroprosthetic SoC with Sensory Feedback Featuring Frequency-Splitting-Based Wireless Power Transfer with 200Mb/s 0.67pJ/b Backscatter Data Uplink and Unsupervised Multi-Class Spike Sorting
11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links
23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor
A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1%
28.5 A 0.6V 0.015mm2 time-based biomedical readout for ambulatory applications in 40nm CMOS
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS
A mixed-signal 32-coefficient RX-FFE 100-coefficient DFE for an 8Gb/s 60GHz receiver in 65nm LP CMOS
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm
20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers
A 250µW 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers
13.3 A Cryo-BiCMOS Controller for 9 Be + -Trapped-Ion-Based Quantum Computers
A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces
13.3 A 10mW Bluetooth Low-Energy transceiver with on-chip matching
2.9 A 29dBm 18.5% peak PAE mm-Wave digital power amplifier with dynamic load modulation
3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
A Broadband Distributed Amplifier with Internal Feedback Providing 660GHz GBW in 90nm CMOS
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee
22.6 A 22V compliant 56µW active charge balancer enabling 100% charge compensation even in monophasic and 36% amplitude correction in biphasic neural stimulators
A Mechanically Flexible Implantable Neural Interface for Computational Imaging and Optogenetic Stimulation over 5.4 × 5.4 mm 2 FoV
AI x Robotics: Technology Challenges and Opportunities in Sensors, Actuators, and Integrated Circuits
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS
A 19nm 112.8mm 2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration
27.7 A 30.5mm 3 fully packaged implantable device with duplex ultrasonic data and power links achieving 95kb/s with <10 -4 BER at 8.5cm depth
A 1V-Supply $1.85\mathrm{V}_{\text{PP}}$ -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2 nd -Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS
14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC
29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC
25.4 Liquid Metal - Polymer Composites for Stretchable Circuits, Soft Machines, and Thermal Management
Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS
A 769μW Battery-Powered Single-Chip SoC With BLE for Multi-Modal Vital Sign Health Patches
Integrated neural interfaces
A mm-wave CMOS multimode frequency divider
100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier
A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor
A Broadband Mm-Wave VSWR-Resilient Joint True-Power Detector and Impedance Sensor Supporting Single-Ended Antenna Interfaces
An 8.3MHz GaN Power Converter Using Markov Continuous RSSM for 35dBμV Conducted EMI Attenuation and One-Cycle TON Rebalancing for 27.6dB VO Jittering Suppression
A leakage-suppression technique for phase-locked systems in 65nm CMOS
33.8 A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation
A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy
A 0.46mm 2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy
A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOS
Session 8 overview: Digital PLLs and security circuits
A Cryogenic ADC operating Down to 4.2K
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme
A dividerless reference-sampling RF PLL with -253.5dB jitter FOM and <-67dBc Reference Spurs
An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolution
32.1 A 13.56MHz Current-Mode Wireless Power and Data Receiver with Efficient Power Extracting Controller and Energy-Shift Keying Technique for Loosely Coupled Implantable Devices
A 94GHz Locking Hysteresis-Assisted and Tunable CML Static Divider in 65nm SOI CMOS
Session 23 Overview: THz Circuits and Front-Ends Rf Subcommittee
A 4-tap 3.5 μm 1.2 Mpixel Indirect Time-of-Flight CMOS Image Sensor with Peak Current Mitigation and Multi-User Interference Cancellation
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme
17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems
A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS
A 128 X 128 120db 30mw asynchronous vision sensor that responds to relative intensity change
12.3 Exploring PUF-Controlled PA Spectral Regrowth for Physical-Layer Identification of IoT Nodes
F6: Circuit, systems and data processing for next-generation wearable and implantable medical devices
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis
5.1 POWER8 TM : A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS
An integrated organic circuit array for flexible large-area temperature sensing
A GaN Gate Driver with On-chip Adaptive On-time Controller and Negative Current Slope Detector
A wideband IM3 cancellation technique for CMOS attenuators
A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS
2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012
5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs
A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput
23.2 A 1.1nW energy harvesting system with 544pW quiescent power for next-generation implants
12.1 A 0.518mm 2 quasi-current-mode hysteretic buck DC-DC converter with 3μs load transient response in 0.35μm BCDMOS
9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm
An isolator-less CMOS RF front-end for UHF mobile RFID reader
A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS
19.4 A 0.07 mm 2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS
A High-Conversion-Ratio and 97.4% Peak-Efficiency 3-Switch Boost Converter with Duty-Dependent Charge Topology for 1.2A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Applications
A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converter
Eco-friendly semiconductor technologies for healthy living
12.1 3D ultrasonic gesture recognition
A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing
A 110-to-130GHz SiGe BiCMOS Doherty Power Amplifier With Slotline-Based Power-Combining Technique Achieving >22dBm Saturated Output Power and >10% Power Back-off Efficiency
Analog Matrix Processor for Edge AI Real-Time Video Analytics
A 40Gb/s full-rate 2: 1 MUX in 0.18µm CMOS
A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications
A Receiver with Start-up Initialization and Programmable Delays for Wireless Clock Distribution
Is RF doomed to digitization? What shall RF circuit designers do?
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits
Baseband Signal Processing
8.2 Fully integrated low-drop-out regulator based on event-driven PI control
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage
5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4: 1-VSWR-Resilient Operations in Large-Scale Phased Arrays
A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/s
25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100 % Solvability and 31.7μs Solution Time
EE4: Figures-of-merit on trial
IBM Telum: a 16-Core 5+ GHz DCM
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects
SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light
F6: Energy-efficient I/O design for next-generation systems
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS
A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications
2.2 A scalable 28GHz coupled-PLL in 65nm CMOS with single-wire synchronization for large-scale 5G mm-wave arrays
A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS
21.3 A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate During Load Transients
Session 19 overview: Advanced wireless techniques: Wireless subcommittee
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS
A 200 x 256 Image Sensor Heterogeneously Integrating a 2D Nanomaterial-Based Photo-FET Array and CMOS Time-to-Digital Converters
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS
A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology
A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC
A -76dBm 7.4nW wakeup radio with automatic offset compensation
A Digitally Modulated Polar CMOS PA with 20MHz Signal BW
Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants
A 14-band Frequency Synthesizer for MB-OFDM UWB Application
ATAC: High-speed interfaces
31.5 A 750mW, 37% Peak Efficiency Isolated DC-DC Converter with 54/18Mb/s Full-Duplex Communication Using a Single Pair of Transformers
A 26-to-39GHz Broadband Ultra-Compact High-Linearity Switchless Hybrid N/PMOS Bi-Directional PA/LNA Front-End for Multi-Band 5G Large-Scaled MIMO System
26.2 Design Considerations for Superconducting Quantum Systems
21.1 A single-cycle MPPT charge-pump energy harvester using a thyristor-based VCO without storage capacitor
A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique
CMOS Image Sensor with integrated 4Gb/s Camera Link Transmitter
Panel-Sized TFT-LCD Column Driver
12.2 3D gesture-sensing system for interactive displays based on extended-range capacitive sensing
A Single-Link Multi-Domain-Output (SLiMDO) Isolated DC-DC Converter with Passive Magnetic Flux Sharing for Local Energy Distribution and Rx Behavior Sensing-Based Global Power Modulation
A 4.1mW 79dB-DR 4th-order Source-FollowerBased Continuous-Time Filter for WLAN Receivers
A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem
A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications
6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications
A 2.7Gb/s/mm 2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC
A Highly Linear Direct-Conversion Transmit Mixer Transconductance Stage with Local Oscillation Feedthrough and I/Q Imbalance Cancellation Scheme
Signal-Margin-Screening for Multi-Mb MRAM
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
Circuit design issues in multi-gate FET CMOS technologies
A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During Startup
IBM z14™: 14nm microprocessor for the next-generation mainframe
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter
29.2 A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW
A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits
Delay reduction in real-time recognition of human activity for stroke rehabilitation
GMM-based speaker gender and age classification after voice conversion
Towards biometrie features for 2D/3D sensoring of forensic handwriting
Cancelable biometrics for finger vein recognition
Image pre-processing detection: Evaluation of Benford's law, spatial and frequency domain feature performance
Employing speech and location information for automatic assessment of child language environments
Towards neural art-based face de-identification in video data
Kernel subclass support vector description for face and human action recognition
Improving the convergence of co-training for audio-visual person identification
Visually evoked potentials for EEG biometrie recognition
User intention understanding from scratch
First International Workshop on Sensing, Processing and Learning for Intelligent Machines, SPLINE 2016, Aalborg, Denmark, July 6-8, 2016
Robust community detection on dynamic graph
Background subtraction for patterns of activities in cities
Projecting emotional speech into arousal-valence space using pairwise preference learning
Two-stage cascade model for unconstrained face detection
Deep learning architectures for tattoo detection and de-identification
Underwater acoustic sensor fault detection for passive sonar systems
Effect of multi-condition training and speech enhancement methods on spoofing detection
Unsupervised representation learning of structured radio communication signals
Convolutional Neural Network for 3D object recognition using volumetric representation
Efficient fingerprint image protection principles using selective JPEG2000 encryption
Piecewise linear definition of transformation functions for speaker de-identification
Cycled merging registration of point clouds for 3D human body modeling
A visual analysis system for metabolomics data
Visual exploration of microbial populations
neuroMAP - Interactive graph-visualization of the fruit fly's neural circuit
MaTSE: The microarray time-series explorer
Keynote address
Hummod browser: An exploratory visualization tool for the analysis of whole-body physiology simulation data
Gene-RiViT: A visualization tool for comparative analysis of gene neighborhoods in prokaryotes
Visualization of anisotropic contact potentials within protein structures
Keynote address: Scientific publishing in a technological age
Implicit surfaces for interactive graph based cavity analysis of molecular simulations
Semantically steered visual analysis of highly detailed morphometric shape spaces
Modeling and visualization of receptor clustering on the cellular membrane
The Molecular Control Toolkit: Controlling 3D molecular graphics via gesture and voice
Visualizing cells and their connectivity graphs for CompuCell3D
IEEE Symposium on Biological Data Visualization, BioVis 2013, Atlanta, GA, USA, October 13-14, 2013
The Galaxy Track Browser: Transforming the genome browser from visualization tool to analysis tool
Robust detection and visualization of cytoskeletal structures in fibrillar scaffolds from 3-dimensional confocal image
EVEVis: A multi-scale visualization system for dense evolutionary data
VisNEST - Interactive analysis of neural activity data
Challenge session speakers: Engaging today's genomics resources
GenAMap: Visualization strategies for structured association mapping
Parallel Contour-Buildup algorithm for the molecular surface
Epithelial cell reconstruction and visualization of the developing Drosophila wing imaginal disc
Fiber stippling: An illustrative rendering for probabilistic diffusion tractography
Evaluating the VIPER pedigree visualisation: Detecting inheritance inconsistencies in genotyped pedigrees
Heterogeneity-based guidance for exploring multiscale data in systems biology
Leveraging wall-sized high-resolution displays for comparative genomics analyses of copy number variation
Quick2Insight: A user-friendly framework for interactive rendering of biological image volumes
MDMap: A system for data-driven layout and exploration of molecular dynamics simulations
Keynote address: Translating the cancer genomes
2011 IEEE Symposium on Biological Data Visualization, BioVis 2011, Providence, RI, USA, October 23-24, 2011
invis: Exploring high-dimensional RNA sequences from in vitro selection
HiTSEE: A visualization tool for hit selection and analysis in high-throughput screening experiments
COMBat: Visualizing co-occurrence of annotation terms
From biochemical reaction networks to 3D dynamics in the cell: The ZigCell3D modeling, simulation and visualisation framework
TIALA - Time series alignment analysis
mzRepeat: Visual analysis of lipids in mass spectrometry
RuleBender: Integrated visualization for biochemical rule-based modeling
ADVISe: Visualizing the dynamics of enzyme annotations in UniProt/Swiss-Prot
Visual cleaning of genotype data
Metrics for comparing explicit representations of interconnected biological networks
Large-scale multiple sequence alignment visualization through gradient vector flow analysis
Uncertainty-aware visual analysis of biochemical reaction networks
Towards real-time visualization of detailed neural tissue models: View frustum culling for parallel rendering
Similarity analysis of cell movements in video microscopy
Dynamic channels in biomolecular systems: Path analysis and visualization
iHAT: Interactive hierarchical aggregation table
Volume visualization in serial electron microscopy using local variance
MoClo planner: Interactive visualization for Modular Cloning bio-design
Interactive extraction of neural structures with user-guided morphological diffusion
enRoute: Dynamic path extraction from biological pathway maps for in-depth experimental data analysis