yusuke1997/dblp-id-title huggingface dataset:
A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits
A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots
Designing scratchpad memory architecture with emerging STT-RAM memory technologies
Interconnect design and limitations in nanoscale technologies
On Switched-Current Delta-Sigma A/D Converters
Self-Tuned Series Resonant Power Oscillator with Load-independent Operation
Generic face recognition, feature extraction and edge detection using optimal DSNR expansion matching
Lost solution and chaos
F-Domain Analysis of Linear Circuits with Time-Varying Parameters via Integral Equations
A 4D frequency-planar IIR filter and its application to light field processing
Real-time streaming challenges in Internet of Video Things (IoVT)
A low frequency-dependence, energy-efficient switching technique for bottom-plate sampled SAR ADC
A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses
Adaptive baseband fre-equalization for RF impedance matching correction
A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform
Classification of Human Activities Based on Radar Signals using 1D-CNN and LSTM
An adaptive microphone preamplifier for low power applications
Compensation of errors generated by an analog 2D DCT
Supersystolic arrays on large-scale FPGA structures
Adaptive system modeling with critically decimated multirate filters
EEG-based cognitive state monitoring and predition by using the self-constructing neural fuzzy system
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Sub-Hz self-powered sensing based on mechanical-buckling driven hot-electron injection
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique
An Overview of Quantum Algorithms: From Quantum Supremacy to Shor Factorization
Spectrogram-Based Spectrum Prediction for AI-managed Cognitive-Radio Edge Devices
A Compact and Low-Power Column Readout Circuit based on Digital Delay Chain
High-Fidelity, Low-Latency State Detection for 300 Trapped Ion Qubits
Efficient Floorplan Enumeration Using Dynamic Programming
Implementation of the conscience mechanism using single-electron transfer in competitive learning
New Power Index Model for Switching Power Analysis from Adder Graph of FIR filter
Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis
Adaptive watermarking technique based on human visual system and fuzzy inference system
SLAP: a system for the detection and correction of pronunciation for second language acquisition
A design-oriented approach for modeling integrators non-idealities in discrete-time sigma-delta modulators
Filament behaviour and stability in ECM memristive devices studied by electrochemical impedance spectroscopy
Texture segregation employing orientation-selective analog multi-chip vision system
High speed single-ended pseudo differential current sense amplifier for SRAM cell
Efficient transient analysis of nonlinear circuits using Volterra series and piecewise constant interpolation
A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems
A design for test perspective on memory synthesis
A 12-bit current steering DAC for cryogenic applications
Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory
Waveguide QED Analysis of Quantum-Coherent Links for Modular Quantum Computing
High dynamic range double-balanced active mixers using lossless feedback
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS
ARMA processes in sub-bands with application to audio restoration
Live Demonstration: A Scalable CNN Accelerator SoC With a Cost-Effective Chip-to-Chip Adapter
Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning
Analysis on the Low-Frequency Bifurcation Phenomena of Weak-Grid-Tied VSCs
A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS
Area-time efficient realization of multiple constant multiplication
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers
A Current-mode Conductance-based Silicon Neuron for Address-event Neuromorphic Systems
Orthogonal time-varying filter banks and wavelets
Real-Time Seizure Detection in Microelectrode Array based on Z-Test Spike Detection for Hardware Implementation
A Nanowatt Temperature-Independent Tunable Active Capacitance Multiplier with DC Compensation in $0.13-\mu\mathrm{m}$ CMOS
Reduced latency arithmetic decoder for JPEG2000 block decoding
A Deep Cascade Framework for Non-Intrusive Power Disaggregation in Solar-Powered Households
FPGA Implementation of SFO for OFDM-based Network Enabled Li-Fi System
Principles of nonlinearity Cancellation in Linear MOS Systems using MRC Circuits
Power-aware topology optimization for networks-on-chips
A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation
Optimum sizing of power grids for IR drop
A versatile low-dropout voltage regulator for automotive applications
Tile-based GPU optimizations through ESL full system simulation
Self-adjustable feed-forward control and auto-tracking off-time control techniques for 95% accuracy and 95% efficiency AC-DC non-isolated LED driver
Low-latency area-delay-efficient systolic multiplier over GF(2 m ) for a wider class of trinomials using parallel register sharing
Improved building blocks for log-domain linear transformation filters
Improving verification coverage of analog circuit blocks by state space-guided transient simulation
A fast global motion estimation for moving objects segmentation using moment-preserving technique
Andronov-Hopf bifurcation of sinusoidal oscillators under the influence of noise
Parameter optimization tool for enhancing on-chip network performance
A Stacked MOSFET-Based RF Switch with Inductive Biasing Network
Toward Analog Implementation of Recurrent Neural Networks in the RF Domain for Proactive Anomaly Detection in B5G Wireless Networks
A close-loop time-mode temperature sensor with inaccuracy of -0.6°C/0.5°C from -40°C to 120°C
30-39GHz 2Gbit/s ring oscillator based OOK-modulator for chip-to-chip communications
Symbolic techniques applied to switched-current ADCs synthesis
Physical Design-Aware Power Side-Channel Leakage Assessment Framework using Deep Learning
Wave computer core using fixed-point arithmetic
Design Considerations for Analog LCMOS Harvest-Use Integrated Signal Processing
A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration
On Steiner Tree Problem with 45 Degree Routing
Low-power transimpedance amplifier for near infrared spectroscopy
Switched-capacitor dc-dc converters with output inductive filter
Vision chip for navigating and controlling Micro Unmanned Aerial Vehicles
Deterministic Finite State Machines for Stochastic Division in Unipolar Format
Decoding of directional DCT-coded images: A total variational approach with directionality
Towards Gb/s turbo decoding of product code onto an FPGA device
Neural detectors with variable threshold
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS
A low-complexity iterative interference suppressor for coded aperiodic spreading CDMA systems
Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000
Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence
A triple-band flexible low-noise transmitter with linearity enhancement
Analysis of Magnetic Field Emissions in Inductive Power Transfer EV Chargers Following Reference Designs in SAE J2954/2019
High speed Dual Mode Logic Carry Look Ahead Adder
Consensus-based distributed droop control of VSGs for isolated AC micro-grids by ADMMs
Communication Characterization of AI Workloads for Large-scale Multi-chiplet Accelerators
Using the Miller Theorem in LPTV Networks to Analyze Miller N-Path Filters
Comparison of Instructor and Professionals Assessment in Project-Based Learning
Power Efficient Wireless Sensor Node through Edge Intelligence
Consensus-based distributed droop control of synchronverters for isolated micro-grids
A Cost-Effective Self-Healing Approach for Reliable Hardware Systems
Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators
A new structure for capacitor-mismatch-insensitive multiply-by-two amplification
A temperature compensated array of CMOS floating-gate analog memory
Area-power-time efficient pipeline-interleaved architectures for wave digital filters
A lattice structure for linear-phase perfect reconstruction filter banks with mirror image symmetric frequency response
Parametric model for 2D real scattering Schur polynomials
A reconfigurable FIR filter design using dynamic partial reconfiguration
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay
High current CMOS operational amplifier
Volterra Analysis Using Chebyshev Series
Optimal frame synchronization for DVB-S2
Two-stage series-based neural network approach to nonlinear independent component analysis
Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment
A low power asynchronous GF(2 173 ) ALU for elliptic curve crypto-processor
Multi-level Order Reduction with Nonlinear Port Constraints
Cross-layer optimization for wireless streaming via adaptive MIMO OFDM
A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis
Fast ICA for noisy data using Gaussian moments
Successive packing based interleaver design for turbo codes
Optimizing deep neural network structure for face recognition
On the compression of ECG records employing triangular elements and analysis-by-synthesis modeling
Asychnronous sampling based hybrid equalizer
SiGe IC- based mm-wave imager
A charge-pump-controlled MOSFET-C single-amplifier biquad
A sparse representation of physical activity video in the study of obesity
High Voltage Transformer Condition Monitoring Using Memristive Echo State Networks
Markovian SS codes imply inversion-free code acquisition in asynchronous DS/CDMA systems
A 94-dB SFDR multi-bit audio-band delta-sigma converter with DAC nonlinearity suppression
A 10-bit 100MS/s subrange SAR ADC with time-domain quantization
A programmable charge-balanced current stimulation circuit for implantable medical devices
Memristor-based synapses and neurons for neuromorphic computing
Fabrication and Characterization of Emerging Nanoscale Memory
A Novel Pseudo-Differential Integer/ Fractional-Order Voltage-Mode All-Pass Filter
Nanoliter array advances: miniaturized, high-speed PCR sensing & control
Learning-Based Human Detection via Radar for Dynamic and Cluttered Indoor Environments
Source-degenerated CMOS Transconductor with Auxiliary Linearization
A dual-mode neural stimulator capable of delivering constant current in current-mode and high stimulus charge in semi-voltage-mode
A real-time systolic array processor implementation of two-dimensional IIR filters for radio-frequency smart antenna applications
Improve accuracy of delay element by filtering false path for low power desychronized circuits
S4oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats - A Network Theoretic, Learning Approach
A Complex Bandpass Delta-Sigma Converter for Digital Radio
The Multiple Input Floating Gate MOS Differential Amplifier An Analog Computational Building Block
A heuristic approach to synthesize Boolean functions using TANT network
Closed-form spectral analysis of pulse-width modulation
New viewpoint of bit-serial/parallel normal basis multipliers using irreducible all-one polynomial
A nonlinearity-corrected CMOS time digitizer IC with 20 ps single-shot precision
A real-time VLSI median filter employing two-dimensional bit-propagating architecture
On partially blind learning complexity
CMOS Implementation of Low-Frequency Pattern Generator for Electrochemical Sensing
An Ultra Compact Neural Front-End with CT-NEO Based Spike Detection for Implantable Applications
A new packet detection algorithm for IEEE 802.15.4a DBO-CSS in AWGN channel
Optimal Distribution of High-Speed Clocks on Transceiver Chips
Study of the compatibility of 1-D and 2-D bounded real functions
Design and comparison of CMOS Current Mode Logic latches
A 60-GHz rectenna for monolithic wireless sensor tags
An 81.92Gpixels/s Fast Reconstruction of Images from Compressively Sensed Measurements
Analog cellular neural network for application in physical unclonable functions
An Integrated Circuit for Decoupling and Tuning of Inverted-F Antennas in Cellular User Equipment
Low-Cost Photoacoustic Tomography System Enabled by Frequency-Division Multiplexing
QoS-driven optimization for video streaming using layer-aligned multipriority rateless codes
An approach for joint blind space-time equalization and DOA estimation
IIR filter design with novel stability condition
Classification of ECG Anomaly with Dynamically-biased LSTM for Continuous Cardiac Monitoring
Hybrid cascode compensation for two-stage CMOS operational amplifiers
Self-organization and emergent models in bacterial adhesion on engineered polymer surfaces
A comparison approach of lowpass type wave active filter using unified circuit block
Data acquisition for wearables and in-patient monitoring
CNN-Based Bi-Directional Motion Compensation for High Efficiency Video Coding
Q-enhancement of a low-power gm-C bandpass filter for closed-loop sensor readout applications
A 4×4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps
Unit resistor characterization for matching-critical circuit design
Low-complexity Reed-Solomon decoder for optical communications
An overview on computer-aided analysis techniques for sigma-delta modulators
Image processing by three-layer cellular neural networks with a new layer arrangement
Control of autonomous continuous systems using parametric perturbations
Energy Reduction in Turbo Decoding through Dynamically Varying Bit-Widths
Design Techniques of High Speed PHY using Highly compact FOVEROS Through Silicon Via
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Highly Linear VHF Current-Mode Miller Integrator with 900 dB DC Gain
A High-Gain Three-Stage Auto-Zeroing Residual Amplifier for High-Precision Pipelined SAR ADC
Design of a super-pipelined Viterbi decoder
Application of Genetic Algorithm for Response Surface Modeling in Optimal Statistical Design
FAST: A simulation framework for solving large-scale probabilistic inverse problems in nano-biomolecular circuits
Logic gate for sequenced data with nonlinear nanomechanical resonator driven by weak signals
1.25/2.5-Gb/s burst-mode clock recovery circuit with a novel dual bit-rate structure in 0.18µm CMOS
Nonlinear Energy-Efficient Noise-Aware Design of CMOS LC Tank Oscillators
A 0.58mW dB-Linear Time Gain Compensation Amplifier with ±0.5-dB Gain Error for Imaging Applications
Fast hard multiple generators for radix-8 Booth encoded modulo 2 n -1 and modulo 2 n +1 multipliers
Novel Time-Based Sensing Scheme for STT-MRAMs
Two-Dimensional Optimal Algorithms for Image Compression using ARMA predictors
Turbo coded multiple symbol differential detection for correlated Rayleigh fading channel
A Wide-Load-Range Tri-Mode Buck Converter with Seamless Mode Transition
Distortion Contribution Analysis by combining the Best Linear Approximation and noise analysis
Image denoising utilizing the scale-dependency in the contourlet domain
Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits
Adjustable input Self-Strobed Delay Line ADC intended to implantable devices
A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design
Analysis techniques for obtaining the steady-state solution of MOS LC oscillators
An optical CNN implementation with stored programmability
Simulated annealing search through general structure floorplans using sequence-pair
Lower-bits cache for low power STT-RAM caches
A neuromorphic cross-correlation chip
Digital jitter-cancellation for narrowband signals
Voltage domain correction technique for timing skew errors in time interleaved ADCs
A least squares algorithm for efficient context-based adaptive arithmetic coding
Security of neuromorphic systems: Challenges and solutions
Visual saliency model based on minimum description length
A Convolutional Neural Network Accelerator Architecture with Fine-Granular Mixed Precision Configurability
Capacitively-coupled current conveyer second-order section for continuous-time bandpass filtering and cochlea modeling
An ultra low power, low voltage CMOS squarer circuit for non-coherent IR-UWB receivers
A high performance architecture of EBCOT encoder in JPEG 2000
Injection Locked Oscillators with Current Reuse
PVT-Insensitive Time-Domain-based In-Memory Computation with Improved Linearity for Binary Neural Networks
Analysis of the Influence of Component Mismatch on Integrated Passive Polyphase Filters
An Intrinsic Method for Fast Parameter Update on the SpiNNaker Platform
A new fully integrated CMOS interface for a dielectrophoretic lab-on-a-chip device
Teaching introductory circuits and systems: Enhancing learning experience via iterative design process and pre-/post-project learning activities
Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications
Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications
Test Generation for BiCMOS Circuits
Performance of chaotic switching noise injected to Hopfield NN for quadratic assignment problem
A transform-domain G-PrOBE algorithm
Model of Capacitive Micromechanical Accelerometer Including Effect of Squeezed Gas Film
Security using Shannon-Fano-Elias Codes
SimParallel: A high performance parallel SystemC simulator using hierarchical multi-threading
Method to update the feedback control filter coefficients under active noise control
Register allocation for hybrid register architecture in nonvolatile processors
Analysis of the LMS Algorithm with Delayed Coefficient Update
A gradient-based approach for interference cancelation in systems with multiple Kinect cameras
FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond
A 10-transistor low-power high-speed full adder cell
Histogram-Equalized Quantization for logic-gated Residual Neural Networks
The Hierarchical Ensemble Model for Network Intrusion Detection in the Real-world Dataset
Generation of embedding watermark signals from reference watermark of the detector
Challenges in designing trustworthy cryptographic co-processors
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
Flexible PVDF-ZnO Composite Sensor with High Sensitivity and Piezoelectric Response for Enhanced Acoustic Emission Detection
Challenge to off-roadmap silicon devices
Entropy-based Thermal Sensor Allocation for Temperature-aware Multi-core Platforms
Mitigation of Vertical Fixed Pattern Noise in CMOS Image Sensors through Analog Offset Dithering and Dynamic Clock Adjustment
Enhancing the Unified Logical Effort algorithm for branching and load distribution
A design methodology for active-bootstrapped Miller-amplifiers
Structured stochastic optimization strategies for problems with ill-conditioned error surfaces
LLC Resonant Inverter for Induction Heating with Asymmetrical Voltage-cancellation Control
DNA: DC Nodal Analysis Attack for Analog Circuits
CMOS Body-enhanced Cascode Current Mirror
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver
ML frame synchronization for IEEE 802.11a WLANs on multipath Rayleigh fading channels
The design of an audio power amplifier as a class project for undergraduate students
Data-retention flip-flops for power-down applications
Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks
An end-to-end rate control protocol for multimedia streaming in wired-cum-wireless environments
Sub-pixel downsampling of video with matching highly data re-use hardware architecture
Form specifies function: robust spike-based computation in analog VLSI without precise synaptic weights
A Wireless Power Transfer System with Regulated Receiver Based on LCC-S Compensation and Global Control
The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance
New LS and SVD based methods for estimating frequencies of complex sinusoids
Is the road towards "Zero-Energy" paved with NEMFET-based power management?
A novel floating-gate multiple-valued CMOS full-adder
A 3.125 GHz four stage voltage controlled ring oscillator in 0.18 CMOS
The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System
Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application
High Speed 1-bit Bypass Adder Design for Low Precision Additions
Learning and Feature Extraction Based Fundamental Frequency Determination Algorithm in Very Low SNR Scenario
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection
BiCMOS Active-Pull-Down Non-Threshold Logic Cicuits for High-Speed Low-Power Applications
Improved SVD-Based Technique for Enhancing the Time-Frequency Representation of Signals
Compact Temperature Sensor with Voltage-Ratio Current-Independent Output for Reference Independent Data Conversion
Real-time acquisition and tracking for GPS receivers
A varactorless technique for tuning LC oscillators based on loop gain adjustment
125ppm resolution and 120dB dynamic range nanoparticle chemiresistor array readout circuit
Novel Floating Point A/D- and D/A-Conversion Methods
Multi-Partitioned Software Defined Radio Transceiver Based on Dynamic Partial Reconfiguration
Framework to Benchmark CNNs (FaBCNN) for Processing Real-Time HD Video Streams on FPGAs
CASCADE - configurable and scalable DSP environment
Effective capacitance of RLC loads for estimating short-circuit power
A Convolutional Neural Network for Classification of Nerve Activity Based on Action Potential Induced Neurochemical Signatures
Realization of high accuracy 2-D variable IIR digital filters based on the reduced-dimensional decomposition form
Simulation model of switching power circuits
A New Tuning Technique for Implementing Very High Q, Continuous-Time, Bandpass Filters in Radio Receiver Applications
An On-line, Multi-Parametric, Multi-Channel Physicochemical Monitoring Platform for Stem Cell Culture Bioprocessing
Class-E MOSFET low-voltage power oscillator
Thin film PIN photodiodes for optoelectronic silicon on sapphire CMOS
Electronic packaging of SiC MOSFET-based devices for reliable high temperature operation
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework
MBDS: A MultiBody Dynamics Simulation Dataset for Graph Networks Simulators
A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS
Practical homomorphic encryption: A survey
Modulo (2 p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic
A compact factored form for a Boolean function
The integrate-and-fire sampler: A special type of asynchronous Σ - Δ modulator
Advancing Autonomous Vehicle ITS with V2X and V2I Periodic Calibration
Beyond spike-timing dependent plasticity in memristor crossbar arrays
Defects detection and characterization by using cellular neural networks
Integrated multi-tap transformer for reconfigurable multimode matching networks
Enhanced Steiglitz-McBride Procedure for Minimax IIR Digital Filters
Compensation of IQ imbalance and transmitter nonlinearities in broadband MIMO-OFDM
Synthesis of static multiple input multiple output MITE networks
MetaplasticNet: Architecture with Probabilistic Metaplastic Synapses for Continual Learning