yusuke1997/dblp-id-title huggingface dataset:
An overview of hardware intellectual property protection
An energy-efficient 1MSps 7µW 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm
Ultra low voltage design considerations of SOI SRAM memory cells
Overlapped list successive cancellation approach for hardware efficient polar code decoder
High quality MPEG-audio layer III algorithm for a 16-bit DSP
A digital background calibration method for mash Σ-Δ modulators by using coefficient estimation
Design of STR level converters for SoCs using the multi-island dual-VDD design technique
An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates
Multirate Operations for Exact Interpolation and Iterative Subdivision Schemes
Use of concatenated FEC coding for real-time packet video over heterogeneous wired-to-wireless IP networks
SNN Modeling of Cricket Auditory Network with Izhikevich Model Optimized by PSO
The parametric filter of signal constant component
Nonlinear image restoration using recurrent radial basis function network
Experimental results on wideband spectrum sensing using random sampling ADC in 90nm CMOS
A collusion-free key assignment scheme for hierarchical access control using recursive hash chains
Sliding window integrator approximations for multichannel autocorrelation UWB receivers
A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance
Two-dimensional vector modeling of image random field using aritficial neural networks
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit
A complex texture classification algorithm based on Gabor-type filtering cellular neural networks and self-organized fuzzy inference neural networks
Generalized quadrature bandpass sampling with FIR filtering
Accumulator-based output selection for test response compaction
Inter-screen interaction for session recognition and transfer based on cloud centric media network
Response Characteristic from an Artificial Hysteresis Neuron
Millimeter-Wave CMOS Transceiver Toward 1Tbps Wireless Communication
Space Efficient CMOS Nonlinear Transmission Lines
Optimal use of 2-phase transparent latches in buffered maze routing
A SPARC-compatible general purpose address-event processor with 20-bit l0ns-resolution asynchronous sensor data interface in 0.18μm CMOS
Simplified input current waveshaping technique by using inductor voltage sensing for power factor correction isolated Sepic rectifier
On optimum placement of sectionalizing switches in radial distribution networks
Adaptive packet encapsulation of Scalable Video Coding bitstream
Local affine motion prediction for H.264 without extra overhead
Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing
Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators
Performance Analysis of Phoneme Based Voice Recognition System on Different Accents
Nonlinear control evaluation of two-stage matrix converter using ideal and non-ideal IGBT Models
2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers
Fully Integrated Tunable Wideband True Time Delay for Wireless Sensor Networks
A dynamic-translinear fully-integrated highly-directional hearing aid adapter
Joint bit-allocation for MPEG encoding of multiple video sequences with minimum quality-variation
SEVDA: Singular Value Decomposition Based Parallel Write Scheme for Memristive CNN Accelerators
A 2.7μW 10b 640kS/s time-based A/D converter for implantable neural recording interface
Automatic tuning of high frequency, high Q, multiple loop feedback bandpass filters
A Hybrid All-NMOS Rectifier With Gate-Biasing Techniques Achieving a 22.3 dB Power Dynamic Range
A split-radix algorithm for 2-D DFT
RNN-Based Detection of Fault Attacks on RSA
Efficient Check Node Processing for Min-Max NB-LDPC Decoding over Lower-Order Finite Fields
A CMOS companding-based third order Chebyshev filter
A low-latency transmission scheme for interactive screen sharing
Bandwidth-enhanced Feed-forward Amplifier with Shared Class-AB Gain and Compensation Paths
Geometric-mean based current-mode CMOS multiplier/divider
A flexible hardware implementation of SHA-1 and SHA-2 Hash Functions
A single-chip FPGA design for real-time ICA-based blind source separation algorithm
A low-phase-noise LC QVCO with bottom-series coupling and capacitor tapping
The impact of analog computational error on an analog boolean satisfiability solver
Feasibility of UWB radio: Impulse radio versus chaos-based approach
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices
FPGA Implementation of Pulse-Coupled Phase Oscillators working as a Reservoir at the Edge of Chaos
Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting
Chaotic p-ary sequences with exponential auto-correlation properties based on piecewise linear maps
Smart Watchdog Mechanism for Fault Detection in RISC-V
A SoC for an active implantable microsystem for closed-loop optogenetic neuromodulation
Live Demonstration: A Dry electrode-based Brain Computer Interface for P300-based Car Driving
Signal processing and climate understanding
A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function
A Data-Traffic Aware Dynamic Power Management for General-Purpose Graphics Processing Units
CMOS inverter analytical delay model considering all operating regions
Live demonstration: A 64×64 pixels UWB wireless temporal-difference digital image sensor
A Mixed Electrical-Functional Model Strategy to Investigate the Nonlinear Behaviors of an Experimental Flyback Converter
Fault Tolerance in Programmable Metasurfaces: The Beam Steering Case
Method for designing multi-channel RNS architectures to prevent power analysis SCA
An oversampling 2D sigma-delta converter by cellular neural networks
Live demonstration: Mixed-signal network analysis characterization and modeling platform
N × 16 cellular test chips for low-pass filtering large images
Toward a Low Power E-Skin Interface System on a Chip for Taxel Arrays
Combined GMSK and 8PSK modulator for GSM and EDGE
Simplified algorithm to determine break point realys and relay coordination based on network topology [for realys read relays]
Design of FIR filter over a discrete coefficient space with applications to HDTV signal processing
Live Demonstration: A Cloud-Based Cell-Free Distributed Massive MIMO System
Design and implementation of an RSA public-key cryptosystem
A 32nm tunnel FET SRAM for ultra low leakage
Synchronization of Chaotic Systems Through Parameter Adaptation
Fractional biorthogonal partners and application in signal interpolation
A One-Point Exponential Trimming Technique for an Effective Suppression of Process Spread in BJT-based Temperature Processing Circuits
Frame-level dependent bit allocation via geometric programming
Low-noise readout IC with integrated analog-to-digital conversion for radiation detection system
Ascend: automatic bottom-up behavioral modeling tool for analog circuits
Novel Design for Binary to RNS Converters
Analysis of nonlinear residual echo suppressors for telecommunications [voice communication applications]
A simplicial CNN visual processor in 3D SOI-CMOS
A New Floorplan Simultaneously Placing Blocks over Two Logic Layers for Sea-of-gate Gate Arrays
The VLSI implementation of a baseband receiver for DECT-based portable applications
Nonsymmetric PDF approximation by artificial neurons: application to statistical characterization of reinforced composites
A mutual information approach to articulated object tracking
Comparative analysis of double-edge versus single-edge triggered clocked storage elements
Decoder-side Block Motion Estimation for H.264 / MPEG-4 AVC based Video Coding
Floorplanning for 2.5-D system integration using multi-layer-BSG structure
Rate Control for Slimmable Video Codec using Multilayer Perceptron
A Wideband 24-29 GHz Differential All-Pass Filter in 65-nm CMOS
A low power 1.1 MHz CMOS continuous-time delta-sigma modulator with active-passive loop filters
Analysis and Design of Concurrent Dual-band Distributed Baluns
Complex network topologies and synchronization
A Unified FFT/NTT Design for Efficient NTRU Equation Solving in FALCON Cryptography
A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm
A Micropower Cochlear Prosthesis System Demonstrator
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation
Memory efficient column-layered decoder design for non-binary LDPC codes
A fast compact CMOS feedforward automatic gain control circuit
Adaptive fault tolerant digital filters with single and multiple bit errors in floating-point arithmetic
Towards a neuromorphic implementation of hierarchical temporal memory on SpiNNaker
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors
Mel-frequency cepstrum encoding in analog floating-gate circuitry
Optimization of FIR filters using the frequency-response masking approach
A class of two-channel approximately perfect reconstruction hybrid analog/digital filter banks
Tile-graph-based power planning
PSRR enhancement based on QFG techniques for low-voltage low-power design
A new gain controllable on-chip active balun for 5 GHz direct conversion receiver
A closed-form delay formula for on-chip RLC interconnects in current-mode signaling
An Instrumentation Amplifier with High-Flexibility, High-CMRR and Low-Power Consumption for Electrical Impedance Tomography Applications
DC and AC analysis of buck PWM DC-DC converter with peak-voltage-modulation feedforward control
Current Averaging Networks Based on Transmission Lines
Live Demonstration: Real-time neuro-inspired sound source localization and tracking architecture applied to a robotic platform
Performance analysis of online dual slope delta modulated PWM inverter
Varactor-driven temperature compensation of CMOS floating-gate current memory
Mixed-signal PI controller in current-mode DC-DC buck converter for automotive applications
A neurofuzzy selfmade network with output dependable on a single parameter
Teaching freshmen VHDL-based digital design
A dynamic address decode circuit for implementing range addressable look-up tables
7-decades tunable translinear SiGe BiCMOS 3-phase sinusoidal oscillator
Estimating spatial spectrum with generalized spectral-correlation signal subspace fitting
Equivalence classes of clone circuits for physical-design benchmarking
Integrated 64-state parallel analog Viterbi decoder
In-package spiral inductor characterization for high efficiency buck converters
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility
Towards systems integration in a virtual environment: small steps, big results, and complications to come for embedded systems engineering in the next millennium
A chaos tracker applied to non-coherent detection in chaos-based digital communication systems
On-chip compensation of dark current in infrared focal plane arrays
An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies
Process-variation tolerant flexible circuit for wearable electronics
Neural network system for face recognition
A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs
A Linear CMOS OTA for VHF Applications
2-D Tridiagonal IIR Filters/Systems: State Space and Circuit Realizations
Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration
An area- and power-efficient half-rate clock and data recovery circuit
A Nanowatt Comparator with Feedforward Slew Rate Enhancement and PVT-Insensitive Bias for Always-on MEMS Switch Wake-up Sensor
High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder
Low Computational Sensing with Goertzel Filtering for Mobile Industrial IoT Devices
A new approach to the computation of reduced order models for one-port and two-port RC circuits
SDEX: Monte Carlo Simulation of Stochastic Differential Equations on Memristor Crossbars
Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors
Design and Optimization of a 71 Gb/s Injection-locked CDR
Enhanced Thermal-Resistant Fingerprint Model for Device Identification in OWC System
A Nonlinear Optimization Algorithm for Asymmetric FIR Digital Filters
Use of noise shaping for rate conversion in oversampled video signals
A 2.5 kHz 50.57 dB Linearized VCO ADC Using 6 µm LTPS TFTs
A Parallel SONET Scrambler/Descrambler Architecture
sWMF: Separable weighted median filter for efficient large-disparity stereo matching
A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency
Transistor-Level Consideration of an RC Current-Mode Oscillator using Unity-Gain Current-Mirrors
Design of high-performance CMOS charge pumps in phase-locked loops
High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter
An ABCD parameter based modeling and analysis of crosstalk induced effects in Multilayer Graphene Nano Ribbon interconnects
Semi-blind CFO, channel estimation and data detection for OFDM systems over doubly selective channels
ADC Required Resolution for Correct Demodulation of an Intra-Quantum Signal
Simulink based model realization for CDMA communication over power lines
Intermediate view synthesis from binocular images for stereoscopic applications
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores
A Convolutional Accelerator for Neural Networks With Binary Weights
Validation of and delay variation in total ionizing dose hardened standard cell libraries
Tuning Elliptic Filters with a 'Tuning Biquad'
Hardware Implementation of Stochastic Computing-based Morphological Neural Systems
Evaluation of Dual Mode Logic Under Cryogenic Temperatures
Comparison of time and frequency domain interpolation implementations for MB-OFDM UWB transmitters
Minimax Design of IIR Digital Filters using SDP Relaxation Technique
A low distortion high frequency transconductor structure
Towards a fully parallel stochastic Hopfield neural network
Parameter-free view synthesis distortion model with application to depth video coding
Content-based video retrieval using motion descriptors extracted from compressed domain
A fully-programmable neural interface for multi-polar, multi-channel stimulation strategies
Floating-gate techniques for assessing mismatch
A Novel Sub-1V Bandgap Reference with 17.1 ppm/ 0 C Temperature coefficient in 28nm CMOS
FPGA-Based Wordlength Optimization for DSP
A new rail-to-rail driving scheme and a low-power high-speed output buffer amplifier for AMLCD column driver application
Extending the dynamic range of implantable real-time neurochemical monitoring systems
A USB3.0 FPGA event-based filtering and tracking framework for dynamic vision sensors
Adaptive depth map filter for blocking artifacts removal and edge preserving
Design of Systems with Prescribed Impulse Response Based on Second-Order Cone Programming
Practical stability assessement of distributed synchronous generators under load variations
Frequency synthesizer for on-chip testing and automated tuning
Reconfigurable Voltage/Current Readout Instrumentation Amplifier for Cardiovascular Health Monitoring
An On-Chip Static and Dynamic DAC Error Correction Technique for High Speed Multibit Delta-Sigma Modulators
A robust H.264 video streaming scheme for portable devices
Self-assembled multiferroic magnetic QCA structures for low power systems
A Multiple Exchange Remez Algorithm for Complex FIR Filter Design in the Chebyshev Sense
Early case splitting and false path detection to improve high level ATPG techniques
Decomposed piecewise-linear models by hyperplanes unbending
Design of multiplier-free state-space digital filters
Reconfigurable Low-noise Multichannel Amplifier for Neurochemical Recording
A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture
A Framework for Automatic Synthesis of Neuromorphic Architectures with Heterogeneous Integration of CMOS and Memristors
Behavioral Models for the Analysis of Dynamic Wireless Charging Systems for Electrical Vehicles
Investigation of different frequency estimation techniques using the phase vocoder
The System of Personalized Learning Resource Recommendation and Experimental Teaching Based on Collaborative Filtering
CMOS interface circuits for reading and writing memristor crossbar array
A hybrid delta-sigma modulator with adaptive calibration
Optimum biasing and design of high performance double gate MOSFET RF mixers
The Fisher information matrix for two-dimensional separable-denominator continuous systems
Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers
Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution
A square root unscented Kalman filter for estimating DAC and loopfilter nonidealities in continuous-time sigma-delta modulators
Robust encoding by collective bursting in biologically plausible neural networks
Live Demonstration of an Asynchronous Integrate-and-fire Pixel-event Vision Sensor
Observing test response of embedded cores through surrounding logic
Digital enhancement of frequency synthesizers
Analysis of coexisting solutions and control of their bifurcations in a parallel LC resonant inverter
Analysis of a circuit exhibiting ferroresonance
On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters
Hardware Implementation of High Throughput RC4 algorithm
Clockless continuous-time neural spike sorting: Method, implementation and evaluation
Improved dynamic range, digitally-controlled linear-in-dB CMOS variable gain amplifier
An efficient ECG data compression technique based on predefined signature and envelope vector banks
Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering
Input-adaptive Mixed-Precision Framework for Efficient Object Detection
Hierarchical Placement Algorithm for Analog Circuit With Polygonal Modules
250Mb/s to 3Gb/s unilateral continuous rate CDR using precise frequency detector and 1/5-rate linear phase detector
Advanced real time fire detection in video surveillance system
Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT
Emulation of Salamander Retina with Multilayer Neural Network
LSMaker: A robotic platform for Engineering Education
Measuring Cohesion of Software Systems Using Weighted Directed Complex Networks
IDVP (Intra-Die Variation Probe) for System-On-Chip (SoC) Infant Mortality screen
Novel integration technologies for improving reliability in NAND flash memory
Encoder architecture with throughput over 10 Gbit/sec for quasi-cyclic LDPC codes
A Sub-μVRms Chopper Front-End for ECoG Recording
Time-Encoded Mostly Digital Feature Extraction for Voice Activity Detection Tasks
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC
A Current-Mode Analog Circuit for Reinforcement Learning Problems
Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC
JPEG 2000 encryption enabling fine granularity scalability without decryption
Improvement of the Mu-law Proportionate NLMS Algorithm
EDGE data receiver design
High speed multistage CMOS clock buffers with pulse width control loop
HTChecker: Detecting hardware trojans based on static characteristics
Singular value decomposition in sensitivity minimisation for digital filters
Analysis and Improvement of an Algorithm for the Online Inertia Estimation in Power Grids with RES
Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique
An Adaptive Quality-Factor Bandpass Filter
High linear voltage references for on-chip CMOS smart temperature sensor from -60degreeC to 140degreeC
Hardware Trojans Detection at Register Transfer Level Based on Machine Learning
On the performance of CNNs for associative memories in robot vision systems
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
A novel self conjugate halftone image watermarking technique
Single-Axis Capacitive Accelerometer Chip with AC Offset Suppression Loop
Integrated Circuit Innovative Talents Training under the Background of New Engineering
Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm
Low-power partial-parallel Chien search architecture with polynomial degree reduction
Spike response properties of an AER EAR
High-Frequency Component Restoration for Kalman Filter Based Speech Enhancement
Live demonstration: A TiO2 ReRAM parameter extraction method
A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators
An Optimized FPGA-Based Hardware Accelerator for Physics-Based EKF for Battery Cell Management
Recursive algorithm for the realization of the discrete cosine transform
An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network
Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling
A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN
Determination of installation location of SMES for power system stabilization
High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction
2-D zero-phase IIR notch filters design based on state-space representation of 2-D frequency transformation
Modified RF in -RF out broadband predistorter for 5G communication system
A high-quality spatial-temporal content-adaptive deinterlacing algorithm
A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS
Cryptanalysis of a multistage encryption system
A 275 MHz quadrature modulator in 0.18-µm CMOS
Incremental ∆Σ ADCs without Periodic Reset
A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate
Mixed signal phase sensitive detection
A ΔΣ ADC using an LSB-first SAR quantizer
Wavelet-based spatially adaptive method for despeckling SAR images
Balanced Inter-Layer Prediction for Combined Coarse Granular Scalability and Spatial Scalability
An Auto-Polarity Thermoelectric Energy Harvesting Interface Based on a Boost/Buck-Boost Converter
A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer
Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic
A 32.65µm 2 Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array
Partitioning Scheme and Performance Analysis of Distributed Digital Low-Dropout Regulators in SoC
A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation
Behavioral modeling simulation and high-level synthesis of pipeline A/D converters
Improving the coverage of ultra wideband impulse radio by pulse compression
FPGA-based digit-serial complex number multiplier-accumulator
Autonomous Memory Block for reconfigurable computing
Examination of the Relationship between Feature Extraction by Kernels and CNN Performance
Real-time blind spectrum sensing using USRP
A Modular Current-Mode High-Precision Winner-Take-All Circuit
A Fast Modular Inversion FPGA Implementation over GF(2 m ) using Modified x 2n Unit
Kyber-KEM-Ascon: Benchmarking a Lightweight Post-quantum KEM on IoT Devices
CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay
A two-stator MEMS power generator for cardiac pacemakers
A multiresolution algorithm for focal-plane compression
A Low THD Analog Class D Amplifier based on Self-oscillating Modulation with Complete Feedback Network
A low-voltage sinc 2 decimator implemented by a new circuit technique using floating-gate MOS transistors
Perturbation-based digital background calibration technique for pipelined ADCs
A BiCMOs Current-Feedback Operational Amplifier with a 60 dB Constant Bandwidth Range
A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology
Mutual relations and properties of symmetric functions in Walsh spectral domain
Cascode transconductance amplifiers for HF switched-capacitor applications
A Consensus Policy for Heterogeneous Opinion Dynamics
Nonlinear quantizer design in data conversion systems using the unscented transform