yusuke1997/dblp-id-title huggingface dataset:
Keynote: Systems management in the age of cloud
Storage I/O generation and replay for datacenter applications
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
AIBench Training: Balanced Industry-Standard AI Training Benchmarking
Memphis: Finding and fixing NUMA-related performance problems on multi-core platforms
Low-Overhead Dynamic Instruction Mix Generation Using Hybrid Basic Block Profiling
WARP: Enabling fast CPU scheduler development and evaluation
GenomicsBench: A Benchmark Suite for Genomics
A Loop-Aware Autotuner for High-Precision Floating-Point Applications
Power measurement techniques on standard compute nodes: A quantitative comparison
MLC PCM main memory with accelerated read
RPU: The Ring Processing Unit
Architecture-Level Energy Estimation for Heterogeneous Computing Systems
On latency in GPU throughput microarchitectures
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks
The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-Cores
Profiling Intel Graphics Architecture with Long Instruction Traces
Scalability comparison of commodity operating systems on multi-cores
ASLink: Modeling Multi-GPU Execution in Accel-Sim
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Extending statistical cache models to support detailed pipeline simulators
Probing Weaknesses in GPU Reliability Assessment: A Cross-Layer Approach
Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly
Racing to Hardware-Validated Simulation
Evaluating the efficacy of statistical simulation for design space exploration
Advancing computer systems without technology progress
SimPoint-Based Microarchitectural Hotspot & Energy-Efficiency Analysis of RISC-V OoO CPUs
Hardware prediction of OS run-length for fine-grained resource customization
Demystifying Crypto-Mining: Analysis and Optimizations of Memory-Hard PoW Algorithms
Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications
Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms
A survey and comparison of consistent hashing algorithms
Architectures and compilers for multimedia
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture
Distributed Training of Neural Radiance Fields: A Performance Characterization
Deconstructing commit
Full-System Critical Path Analysis
FireMarshal: Making HW/SW Co-Design Reproducible and Reliable
Dynamic program analysis of Microsoft Windows applications
Prometheus: scalable and accurate emulation of task-based applications on many-core systems
Non-volatile memory host controller interface performance analysis in high-performance I/O systems
Leveraging Memory Expansion to Accelerate Large-Scale DL Training
Simulation environment for studying overlap of communication and computation
PAPI 5: Measuring power, energy, and the cloud
A dynamic energy management scheme for multi-tier data centers
Quantitative system design
A Flexible and Accurate Circuit-Level Substrate for Future DRAM Design and Analysis
The Impact of SoC Integration and OS Deployment on the Reliability of Arm Processors
Address Translation Conscious Caching and Prefetching for High Performance Cache Hierarchy
LoopIn: A Loop-Based Simulation Sampling Mechanism
GaaS workload characterization under NUMA architecture for virtualized GPU
Performance analysis and optimization of a distributed Video on Demand service
gpuFI-4: A Microarchitecture-Level Framework for Assessing the Cross-Layer Resilience of Nvidia GPUs
Design alternatives for scalable Web server accelerators
Mosaic: cross-platform user-interaction record and replay for the fragmented android ecosystem
RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform
Minimizing interference through application mapping in multi-level buffer caches
A new synthetic web server trace generation methodology
A study of mobile device utilization
Performance Characterisation and Simulation of Intel's Integrated GPU Architecture
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures
PIM-BEACON: A Benchmarking and Emulation Framework Supporting Adaptive CONfigurations in DRAM-Based Processing-in-Memory Systems
Analyzing Secure Memory Architecture for GPUs
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
1D performance analysis and tracing of technical and Java applications on the Itanium2 processor
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation
GARNET: A detailed on-chip network model inside a full-system simulator
StressRight: Finding the right stress for accurate in-development system evaluation
XAMP: An eXtensible Analytical Model Platform
Characterization of Unnecessary Computations in Web Applications
Mathematical modelling of adaptive wormhole routing in the presence of self-similar traffic
Analysis of Factors Affecting Power Consumption and Energy Efficiency of SGEMM on the Low-Power Myriad-2 VPU
A Profiling-Based Benchmark Suite for Warehouse-Scale Computers
MIAMI: A framework for application performance diagnosis
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020
MEGsim: A Novel Methodology for Efficient Simulation of Graphics Workloads in GPUs
Modeling TCAM power for next generation network devices
2016 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2016, Uppsala, Sweden, April 17-19, 2016
Bandwidth Characterization of DeepSpeed on Distributed Large Language Model Training
TCP performance re-visited
Measuring Performance Overheads of Software Memory Management Using Functional-First Simulators
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs
Phase-Guided Small-Sample Simulation
Integrating complete-system and user-level performance/power simulators: the SimWattch approach
Understanding control flow transfer and its predictability in java processing
Spatiotemporal Strategies for Long-Term FPGA Resource Management
An analytical framework for estimating TCO and exploring data center design space
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications
Flexible Binary Instrumentation Framework to Profile Code Running on Intel GPUs
A Regression-based Model for End-to-End Latency Prediction for DNN Execution on GPUs
Rapid Memory Footprint Access Diagnostics
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2018, Belfast, United Kingdom, April 2-4, 2018
Analyzing the impact of on-chip network traffic on program phases for CMPs
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
Performance competitiveness of a statically compiled language for server-side Web applications
La Superba: Leveraging a Self-Comparison Method to Understand the Performance Benefits of Sparse Acceleration Optimizations
Virtual Power Management simulation framework for computer systems
COCOSSim: A Cycle-Accurate Simulator for Heterogeneous Systolic Array Architectures
Independent Component Analysis and Evolutionary Algorithms for Building Representative Benchmark Subsets
RTHpower: Accurate fine-grained power models for predicting race-to-halt effect on ultra-low power embedded systems
ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale
NoMali: Simulating a realistic graphics driver stack using a stub GPU
Re-establishing Fetch-Directed Instruction Prefetching: An Industry Perspective
StatCache: a probabilistic approach to efficient and accurate data locality analysis
Branch trace compression for snapshot-based simulation
Non-determinism and overcount on modern hardware performance counter implementations
Behavior and performance of interactive multi-player game servers
Simulation Differences Between Academia and Industry: A Branch Prediction Case Study
Is the Future Cold or Tall? Design Space Exploration of Cryogenic and 3D Embedded Cache Memory
Shifting the Barrier: Extending the Boundaries of the BarrierPoint Methodology
Observations and opportunities in architecting shared virtual memory for heterogeneous systems
PowerSensor 2: A Fast Power Measurement Tool
Understanding transactional memory performance
Cross-Level Characterization of Program Behavior : (Extended Poster Abstract)
BigHouse: A simulation infrastructure for data center systems
Where is the data? Why you cannot debate CPU vs. GPU performance without the answer
VMAD: A virtual machine for advanced dynamic analysis of programs
LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators
Performance Analysis of GEMM Workloads on the AMD Versal Platform
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2011, 10-12 April, 2011, Austin, TX, USA
Vision Transformer Computation and Resilience for Dynamic Inference
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models
Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA
Generative AI in Embodied Systems: System-Level Analysis of Performance, Efficiency and Scalability
Beyond the Numbers: Measuring Android Performance Through User Perception
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings
Scaling Down to Scale Up: A Cost-Benefit Analysis of Replacing OpenAI's LLM with Open Source SLMs in Production
GUFI: A framework for GPUs reliability assessment
Simulating DRAM controllers for future system architecture exploration
Sampled simulation of multi-threaded applications
Characterization of SPEC CPU2006 and SPEC OMP2001: Regression Models and their Transferability
HMCSP: Reducing Transaction Latency of CSR-based SPMV in Hybrid Memory Cube
Estimation-based profiling for code placement optimization in sensor network programs
Quantifying instruction-level parallelism limits on an EPIC architecture
Efficient memory tracing by program skeletonization
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator
Orpheus: A New Deep Learning Framework for Easy Deployment and Evaluation of Edge Inference
Characterization and bottleneck analysis of a 64-bit ARMv8 platform
The Alberta Workloads for the SPEC CPU 2017 Benchmark Suite
Interplay of energy and performance for disk arrays running transaction processing workloads
SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities
Performance analysis through synthetic trace generation
Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters
One Size Does Not Fit All: Quantifying and Exposing the Accuracy-Latency Trade-Off in Machine Learning Cloud Service APIs via Tolerance Tiers
Workload characterization and optimization of TPC-H queries on Apache Spark
Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations
A Novel Simulation Methodology for Silicon Photonic Switching Fabrics
WiLIS: Architectural modeling of wireless systems
Web applications and dynamic reconfiguration in UNIX servers
Multi-Core Aware Evaluation of Prefetchers
AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores
Cycle accurate thread timer for linux environment
mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator
Accelerating architecture research
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2019, Madison, WI, USA, March 24-26, 2019
Generative AI Beyond LLMs: System Implications of Multi-Modal Generation
2014 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2014, Monterey, CA, USA, March 23-25, 2014
TPUPoint: Automatic Characterization of Hardware-Accelerated Machine-Learning Behavior for Cloud Computing
Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks
Performance Analysis of 5G NR vRAN Platform and its Implications on Edge Computing
Compositional model of coherence and NUMA effects for optimizing thread and data placement
Enabling Reproducible and Agile Full-System Simulation
The future of simulation: A field of dreams
QUICK: A flexible full-system functional model
BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass
The POP Detector: A Lightweight Online Program Phase Detection Framework
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison
Using utility prediction models to dynamically choose program thread counts
Stargazer: Automated regression-based GPU design space exploration
Workload characterization of multithreaded java servers
Characterizing the branch misprediction penalty
2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings
Performance potentials of compiler-directed data speculation
Memory reference reuse latency: Accelerated warmup for sampled microarchitecture simulation
2001 IEEE International Symposium on Performance Analysis of Systems and Software, November 4-6,2001, Tucson, Arizona, USA, Proceedings
MASE: a novel infrastructure for detailed microarchitectural modeling
Communication breakdown: analyzing CPU usage in commercial Web workloads
Hierarchical Traversal Stack Design Using Shared Memory for GPU Ray Tracing
A server performance model for static Web workloads
VIPP: Validation-Included Precision-Parametric N-Body Benchmark Suite
SimTrace: Capturing over Time Program Phase Behavior
ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas
An analytical model for loop tiling and its solution
Analyzing the scalability of managed language applications with speedup stacks
Revisiting the performance impact of branch predictor latencies
Dynamic pretenuring schemes for generational garbage collection
Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models
Parallel simulation of multiprocessor execution: implementation and results for simplescalar
Pairminer: mining for paired functions in Kernel extensions
Performance Characterization of .NET Benchmarks
Evaluating GPUs for network packet signature matching
Understanding the communication characteristics in HBase: What are the fundamental bottlenecks?
Hierarchical Page Eviction Policy for Unified Memory in GPUs
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI
Message from the Program Chairs; ISPASS 2024
Assessing the Effects of Low Voltage in Branch Prediction Units
Evaluating cache coherent shared virtual memory for heterogeneous multicore chips
On the provision of prioritization and soft qos in dynamically reconfigurable shared data-centers over infiniband
Using program and user information to improve file prediction performance
Issues in the design of store buffers in dynamically scheduled processors
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Hardware-Validated CPU Performance and Energy Modelling
Benchmarking 3D Gaussian Splatting Rendering
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures
APGPM: Automated PMC-Based Power Modeling Methodology for Modern Mobile GPUs
Scientific Computing Applications on a Stream Processor
CETUS: Towards Proportional Capacity Provisioning and Cost-Effectiveness in Frontend Servers
Automatic Extraction of Network Configurations for Realistic Simulation and Validation
Performance Characterization of Java Applications on SMT Processors
Specializing Coherence, Consistency, and Push/Pull for GPU Graph Analytics
A Benchmark Suite for Improving Performance Portability of the SYCL Programming Model
Clone morphing: Creating new workload behavior from existing applications
BarrierPoint: Sampled simulation of multi-threaded applications
Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs
Finding cool code: An analysis of source-level causes of temperature effects
Understanding the Characteristics of Mobile Augmented Reality Applications
Interactive visualization of cross-layer performance anomalies in dynamic task-parallel applications and systems
Bandwidth bandit: Understanding memory contention
Use Equal-Work or Equal-Time Speedup, Not Geomean Speedup
Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation
Characterization and dynamic mitigation of intra-application cache interference
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications
PES: An Energy and Throughput Model for Energy Harvesting IoT Systems
AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
Performance scalability in multiprocessor systems with resource contention
Moby: A mobile benchmark suite for architectural simulators
CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices
PEBIL: Efficient static binary instrumentation for Linux
An MPEG-4 performance study for non-SIMD, general purpose architectures
The design space of ultra-low energy asymmetric cryptography
Micro-architecture independent branch behavior characterization
A detailed and flexible cycle-accurate Network-on-Chip simulator
Demystifying GPU microarchitecture through microbenchmarking
Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures
AMPeD: An Analytical Model for Performance in Distributed Training of Transformers
Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks
EMERALD: Characterization of emerging applications and algorithms for low-power devices
Modeling load address behaviour through recurrences
Metrics for Architecture-Level Lifetime Reliability Analysis
An evaluation of search tree techniques in the presence of caches
Implementation and evaluation of a best-effort scheduling algorithm in an embedded real-time system
MBPlib: Modular Branch Prediction Library
Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA
QTrace: a framework for customizable full system instrumentation
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings
PyTFHE: An End-to-End Compilation and Execution Framework for Fully Homomorphic Encryption Applications
Some observations based on simple models of MP scaling
Building a Performance Model for Deep Learning Recommendation Model Training on GPUs
BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling
Luthier: A Dynamic Binary Instrumentation Framework Targeting AMD GPUs
Analyzing Machine Learning Workloads Using a Detailed GPU Simulator
A hybrid allocator
Emulating cache organizations on real hardware using performance cloning
Eccentric and fragile benchmarks
Enabling Design Space Exploration of DRAM Caches for Emerging Memory Systems
How to compare the performance of two SMT microarchitectures
LagAlyzer: A latency profile analysis and visualization tool
Modeling Deep Learning Accelerator Enabled GPUs
Universal rules guided design parameter selection for soft error resilient processors
Performance modeling and characterization of large last level caches
Nyami: a synthesizable GPU architectural model for general-purpose and graphics-specific workloads
Power/performance evaluation of energy efficient Ethernet (EEE) for High Performance Computing
KORDI: A Framework for Real-Time Performance and Cost Optimization of Apache Spark Streaming
Analyzing Energy Efficiency of a Server with a SmartNIC under SLO Constraints
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
Beethoven: A Heterogeneous Multi-Core Accelerator System Composer
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective
SAGA: A Surrogate Assisted Genetic Algorithm for Fast CPU Power Virus Generation
Peta Thread Computing [Keynote I]
Analyzing graphics processor unit (GPU) instruction set architectures
A quantitative simulator for dynamic memory managers
MARTA: Multi-configuration Assembly pRofiler and Toolkit for performance Analysis
Effectiveness of simple memory models for performance prediction
FIDESlib: A Fully-Fledged Open-Source FHE Library for Efficient CKKS on GPUs
Micro-architecture independent analytical processor performance and power modeling
Visualizing complex dynamics in many-core accelerator architectures
Modeling memory concurrency for multi-socket multi-core systems
Full-System Simulation of Mobile CPU/GPU Platforms
Demystifying the MLPerf Training Benchmark Suite
Compiler-based adaptive fetch throttling for energy-efficiency
A comprehensive performance analysis of HSA and OpenCL 2.0
Performance Analysis and Optimization with Little's Law
2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings
Architecturally-Independent and Time-Based Characterization of SPEC CPU 2017
Invocation profile characterization of Java applications
Studying Thermal Management for Graphics-Processor Architectures
Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware
Graph Processing Platforms at Scale: Practices and Experiences
Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility
Boreas: A Cost-Effective Mitigation Method for Advanced Hotspots using Machine Learning and Hardware Telemetry
Bifrost: End-to-End Evaluation and optimization of Reconfigurable DNN Accelerators
Characterizing Sources of Ineffectual Computations in Deep Learning Networks
Dataflow: A Complement to Superscalar
Evaluating STT-RAM as an energy-efficient main memory alternative
Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators
Splash-4: Improving Scalability with Lock-Free Constructs
Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
How Do Graph Relabeling Algorithms Improve Memory Locality?
A practitioner report on the evaluation of the performance of the C, C++ and Java compilers on the OS/390 platform
Extracting fine-grain profiles of in-order executions of instruction level parallel programs
Performance evaluation of exclusive cache hierarchies
Insight, not (random) numbers
Understanding Capacity-Driven Scale-Out Neural Recommendation Inference
Performance evaluation of adaptivity in software transactional memory
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2008, April 20-22, 2008, Austin, Texas, USA, Proceedings
Performance analysis of CNN frameworks for GPUs
Improved stride prefetching using extrinsic stream characteristics
Accurate address streams for LLC and beyond (SLAB): A methodology to enable system exploration
MAPS: Understanding Metadata Access Patterns in Secure Memory
The Hadoop distributed filesystem: Balancing portability and performance
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators
Where does the time go? characterizing tail latency in memcached
Characterizing In-Kernel Observability of Latency-Sensitive Request-Level Metrics with eBPF
RTune: Towards Automated and Coordinated Optimization of Computing and Computational Objectives of Parallel Iterative Applications
MeMo: Enhancing Representative Sampling via Mechanistic Micro-Model Signatures
Demystifying cloud benchmarking
Evaluating asymmetric multiprocessing for mobile applications