yusuke1997/dblp-id-title huggingface dataset:
A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator
Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching
Series Resonant Tunneling Diodes as a Two-Dimensional Memory Cell
Decomposition of Multiple-Valued Relations
Two-Stage Exact Detection of Symmetrics
Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of Algebras
Representations of Elementary Functions Using Edge-Valued MDDs
Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits
Computation Time Reduction to Speed-up the Database Searching Process
Minimal Coverings of Maximal Partial Clones
Some I2L circuits for multiple-valued logic
New Logical and Complexity Results for Signed-SAT
Contextuality Supplies the Magic for Quantum Computation
On Set-Valued Functions and Boolean Collections
Properties and Relations of Quaternary Linearly Independent Helix Transformations
Bounded Bases of Strong Partial Clones
Lazy Clones and Essentially Minimal Groupoids
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
Theory and Uses of Post Algebras of Order \omega+\omega\ast. Part II
Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization
Remarks on Gibbs Permutation Matrices for Ternary Bent Functions
Many Valued Probability Theory
Logic Synthesis for Quantum State Generation
An Epistemic Logic without K/B Operators
Centralizing Monoids on a Three-Element Set
Multi-Source Training Deep-Learning Side-Channel Attacks
A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion
Characterization of Partial Sheffer Functions in 3-Valued Logic
Redundant Complex Number Systems
Non-convex Fuzzy Truth Values and De Morgan Bisemilattices
Synthesis of Permutative Quantum Circuits with Toffoli and TISC Gates
From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway
Logic Synthesis from Polynomials with Coefficients in the Field of Rationals
31st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2001, Warsaw, Poland, May 22-24, 2001, Proceedings
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals
Optimization of multivalued decision algorithms
Interpreting Propositional Fuzzy Logics via Imperfect Information Games
Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams
Fundamental Properties of Kleene-Stone Logic Functions
On the Fault Tolerance of Stochastic Decoders
On the Maximum Size of the Terms in the Realization of Symmetric Functions
Natural Deduction with Explosion and Excluded Middle
On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions
Quantum Algorithm for Machine Learning and Circuit Design Based on Optimization of Ternary - Input, Binary-Output Kronecker-Reed-Muller Forms
Some Classes of Centralizing Monoids on a Three-Element Set
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices
A simulataneous analog/ternary converter
A Tableau Calculus for Non-Clausal Regular MaxSAT
A Method of Uncertainty Reasoning by Using Information
A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices
Approximate memory-based logic synthesis of index generation functions using linear decomposition
A Canonical Disjunctive Form of Extended Kleene-Stone Logic Functions
An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Paraconsistent Disjunctive Deductive Databases
Note: Towards a Formalization of Guessing
Non-Deterministic Matrices in Action: Expansions, Refinements, and Rexpansions
Betweenness, Metrics and Entropies in Lattices
Intuitionistic Counterparts of Finitely-Valued Logics
Greedy Algorithms, Ordering of Variables, and d-degenerate Instances
Modeling Multi-Valued Circuits in SystemC
Classifying Functions with Exact Synthesis
Counterexample Sufficiency in Modifications to Strict-Tolerant Logics
Representing Fuzzy Structures in Quantum Computation with Mixed States
Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier Expressions
Kleene Algebra With Tests for Weighted Programs
Highly Testable Boolean Ring Logic Circuits
On the Mutual Definability of Classes of Generalized Fuzzy Implications and of Classes of Generalized NegationsandS-Norms
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions
Partial Clones and their Generating Sets
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals
Commutation for Functions of Small Arity Over a Finite Set
Benchmarking Łukasiewicz Logic Solvers with Properties of Neural Networks
Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I)
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection
The B-ternary logic and its applications to the detection of hazards in combinational switching circuits
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels
Test Generation and Fault Localization for Quantum Circuits
Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions
A Synthesis Method for MVL Reversible Logi
28th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1998, Fukuoka, Japan, May 27-29, 1998, Proceedings
A Frontier Algorithm for Optimization of Multiple-Valued Logic Functions
Algorithms for Taylor Expansion Diagrams
Data Mining Using Multi-Valued Logic Minimization
Bent-based Realization of a Class of Ternary Plateaued Functions
Web-Based Nursing Care Quality Improvement System with Fuzzy Recommendation System
A High-Speed Interconnect Network Using Ternary Logic
Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits
A ternary J - K memory
Parallel Processing of Fuzzy Inferences
Novel Fractional-N All Digital Frequency Locked Loop with Robustness for PVT variation
Non-disjoint functional decomposition of index generation functions
Contributions of Arto Salomaa to Multiple-Valued Logic
Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation
Dynamic Reliability Indices for Multi-State System
Learning with Permutably Homogenous Multiple-Valued Multiple-Threshold Perceptrons
Monomial Clones: Local Results and Global Properties
Complete and Independent Sets of Axioms of Boolean Algebra
On the Performance of Multivalued Integrated Circuits: Past, Present and Future
Quantum Phase Estimation Using Multivalued Logic
Joint Position Registration between OpenPose and Motion Analysis for Rehabilitation
A behavioral model and triggering modes for MVL R-flops
On new Properties of the Maiorana-McFarland Ternary Bent Functions
On Scheduling in Multiprocessor Systems Using Fuzzy Logic
Descending Order Transformation-based Synthesis of MVL Reversible Circuits
Toffoli Gate Implementation Using the Billiard Ball Model
The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons
Concrete Dualities and Essential Arities
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures
A Method To Generate Rules From Examples
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions
Searching for Complete Functions over E(3) with Small Radii
Centralising monoids with conservative majority operations as witnesses
Computational Neuroscience and Multiple-Valued Logic
Physical Unclonable Functions Based on Carbon Nanotube FETs
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems
Application of Resonant-Tunneling Quaternary Quantizer to Ultrahigh-Speed A/D Converter
SPRUCE, an Embedded Compact Stack Machine for IGBT Power Modules
On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams
Noise Convolutional Neural Networks and FPGA Implementation
Analysis of computing protection structures by means of multi-valued logic systems
Multiple-Valued Constant-Power Adder for Cryptographic Processors
Multi-Peak Resonant Tunneling Diodes Based Fuzzifiers
Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits
Skipping Embedding in the Design of Reversible Circuits
Information Theory Method for Flexible Network Synthesis
De Morgan Algebras - completeness and recursion
On Partial Clones Containing All Idempotent Partial Operations
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition
Default Reasoning with Imperfect Information in Multivalued Logics
An Exact Method to Enumerate Decomposition Charts for Index Generation Functions
Constructions of Kleene lattices
Edge-Valued Decision Diagrams for Multiple-Valued Functions
Untruth, falsity and non-deterministic semantics
A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks
A New CMOS Gate - The Balanced Gate - For Detecting Physical Failures
Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links
All minimal clones generated by {0, 1}-valued majority operations on a five-element set
Maximal Chains of Partial Clones Containing All Idempotent Partial Functions
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter
An Approach Toward Classification of Minimal Groupoids on a Finite Set
A Galois Field Approach to Modelling Gene Expression Regulation
Remarks on Shapes of Decision Diagrams and Classes of Multiple-Valued Functions
Multiple-Valued Dynamic Source-Coupled Logic
Semirigid Equivalence Relations on a Finite Set
Multi-Valued Data Transmission System Using Mild Waveform Shaping Based on Multi-Dimensional Symbol Mapping
A Set Theory within Fuzzy Logic
Defaults as First-Class Citizens
Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions
Three-Valued Constructive Logic and Logic Programs
Issues in Multi-valued Multi-modal Sensor Fusion
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition
Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5)
The Interface between P and NP in Signed CNF Formulas
Study Support System of Character Drawing Considering Feeling Evaluation
Not Finitely Definable Partial Clones on a Finite Set
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation
Finitary Approximations and Metric Structure of the Space of Clones
Down Literal Circuit with Neuron-MOS Transistors and Its Applications
Answer Set Programming: A Declarative Approach to Solving Challenging Search Problems
A Representation Theorem for Quantale Valued sup-algebras
Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams
Automated Reasoning in Some Local Extensions of Ordered Structures
New Information on the Effectiveness of Different Reed-Muller Algebras on the Representation of Quaternary Functions
GAP vs. PAG
Differential-Time and Pulse-Amplitude Modulation Signaling for Serial Link Transceivers
Minimal Unsatisfiability: Models, Algorithms and Applications (Invited Paper)
Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms
Non-Deterministic Many-Valued Modal Logic
Augmented Sifting of Multiple-Valued Decision Diagrams
From Intuitionistic Logic to Gödel-Dummett Logic via Parallel Dialogue Games
Algebras and Algorithms
Analog Soft Decoding for Multi-Level Memories
Approximative Conjunctions Processing by Multi-Valued Logic
Extending Multiple-Valued Clausal Forms with Linear Integer Arithmetic
Realizing all Index Generation Functions by the Row-Shift Method
Gray-Scale Morphology Based Image Segmentation and Character Extraction Using SVM
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices
ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan
Cut-Elimination in a Sequents-of-Relations Calculus for Gödel Logic
Semantic Games with Backtracking for Fuzzy Logics
Algebraic and Combinatorial Methods for Reducing the Number of Variables of Partially Defined Discrete Functions
A Fuzzy Human Detection for Security System Using Infrared Laser Camera
On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones
Propositional Skew Boolean Logic
Completeness Criteria in Many-Valued Set Logic under Compositions with Boolean Functions
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon
Quasi-Postan Logic Hazard of Postan Signals
On Prior's Three-Valued Modal Logic Q
A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation
Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms
Fleischer po-semigroups and quantum B-algebras
Weak Bases for All Maximal Clones
Finitely Generated Maximal Partial Clones and Their Intersections
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
Search for Some Majority Operation and Studies of its Centralizing Monoid
VLSI Fuzzy Chip and Inference Accelerator Board Systems
PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits
Automated Reasoning with Ordinary Assertions and Default Assumptions
Constructing an MVL Patterned after Boolean Logic using a Practical Approach
On the Definition of Modal Operators in Fuzzy Logic
A Note on Minimal Partial Clones
A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic
Fuzzy Logic Assisted Quantification of Gyral Deformation Index Using Magnetic Resonance Images for the Infantile Brain
On Concurrent Tests of Fuzzy Controllers
Set-Valued Functions and Regularity
Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design
Signal Processing Algorithms and Multiple-Valued Logic Design Methods
Current Challenges in Infinite-Domain Constraint Satisfaction: Dilemmas of the Infinite Sheep
Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
Logical Not Polynomial Forms to Represent Multiple-Valued Functions
Increasing Degree of Ternary Bent Functions
On Universality of General Reversible Multiple-Valued Logic Gates
Automata over MV-Algebra
Remarks on Applicability of Spectral Representations on Finite Non-Abelian Groups in the Design for Regularity
A New Class of Fuzzy Modifiers
Decompressing Dilithium's Public Key with Fewer Signatures Using Side Channel Analysis
Three Classes of Closed Sets of Monomials
Chaining Techniques for Automated Theorem Proving in Many-Valued Logics
Minimal Weighted Clones with Boolean Support
A Modular Reduction of Regular Logic to Classical Logic
Monoids whose Centralizer is the Least Clone
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC
On Logic of Paradox
Addition in signed digit number systems
Development of Quantum Functional Devices for Multiple-Valued Logic Circuits
A Characterization of Antisymmetry in Boolean and Multi-Valued Functions
A Ternary Analog-to-Digital Converter System
Logics of Reasonable Information Sources
Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic Systems
On Optimum Linear Decomposition of Symmetric Index Generation Functions
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables
Spectral Invariant Operations in the p-valued Spectral Domain
Neural Spike Compression Using Feature Extraction and a Fuzzy C-Means Codebook
Kalmbach implication in orthomodular posets
Join Operations on Commutative BCK-Algebras with Condition (S)
Track-Down Operations on Bilattices
Representations of Logic Functions Using QRMDDs
Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics
Fuzzy Damage Extraction Method for Ultrasonic Nondestructive Testing Images
A New Algorithm to Compute Quaternary Reed-Muller Expansions
Planarity in ROMDD's of Multiple-Valued Symmetric Functions
An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions
Easily Testable Multiple-Valued Cellular Arrays
Random Forest and K-Means Clustering Algorithms to Classify of 18 F-Florbetapir Brain PET
Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991
A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number Systems
The Arity Gap of Polynomial Functions over Bounded Distributive Lattices
Semirigid Sets of Quasilinear Clones
Non-Archimedean Models of Lukasiewicz Logic
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic
36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore
Number of Maximal Partial Clones
Decomposition of Multi-Valued Functions into Min- and Max-Gates
Boolean Max-Co-Clones
Some Continuous Maps on the Space of Clones in Multiple-Valued Logic
Uniqueness of Partially Specified Multiple-Valued Kleenean Function
Non-Binary Approaches for Classification of Amyloid Brain PET
Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop
Design of Interconnection-Free Biomolecular Computing System
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions
CMOS Implementation and Fabrication of the Pseudo Analog Neuron
Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams
Analysis of Multi-state Systems with Multi-state Components Using EVMDDs
Computation of Spectral Information from Logic Netlists
Evaluation and Comparison of Threshold Logic Gates
Several Remarks on Index Generation Functions
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions
Towards the Gibbs Characterization of a Class of Quaternary Bent Functions
Many-Valued Logics and Plausible Reasoning
A Three-Valued Approach to the Master Argument
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences
Some Spectral Invariant Operations for Multiple-Valued Functions with Homogeneous Disjoint Products in the Polynomial Form
Multiple-Valued Logic Operations with Universal Literals
A Bit-Vector Approach to Satisfiability Testing in Finitely-Valued Logics
Generalizing the Concept of Scalable Reversible Circuit Synthesis for Multiple-Valued Logic
Multiple-Valued Generalized Reed-Muller Forms
Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution
Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic
A Representation of Approximate Reasoning with Analogy
Simulation and Evaluation of Asynchronous Circuits in Extreme Edge Environments
Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram
Handwritten Digit Recognition Based on Classification Functions
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
The Radii of Sheffer Functions Over E(3)
Set-Valued Logic Networks Based on Optical Wavelength Multiplexing
Classification of Fastest Quaternary Linearly Independent Arithmetic Transforms
A New Characterization of Restriction-Closed Hyperclones
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
Bi-Decompositions of Multi-Valued Functions for Circuit Design and Data Mining Applications
On the Ranges of Algebraic Functions in Lattices - A Preliminary Report
Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta
38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA
Centralizing Monoids and the Arity of Witnesses
Detection of osteochondritis dissecans using convolutional neural networks for computer-aided diagnosis of baseball elbow
Calculation of Ternary Mixed Polarity Function Vector
Design of One-Vector Testable Binary Systems Based on Ternary Logic
Exploiting Polarity in Multiple-Valued Inference Systems
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing
Lukasiewicz Negation and Many-Valued Extensions of Constructive Logics
MUSIC Spectra Using Cayley Graphs of Multiple-Valued Signals
EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions
27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings
Reducing Reversible Circuit Cost by Adding Lines
Construction of Ternary Bent Functions by FFT-like Permutation Algorithms
Multiple-Valued Galois Field S/D Trees for GFSOP Minimization and Their Complexity
Majority and Other Polynomials in Minimal Clones
Ternary Function Classification Using Machine Learning
On a Memory-Based Realization of Sparse Multiple-Valued Functions
Design of Ratioless Ternary Inverter Using Graphene Barristor
Quantum Computing, Cryptography and Compilers
Construction of Ternary Plateaued Functions from Quadratic Forms for Ternary Bent Functions
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model
Towards Fuzzy Partial Logic
Some Remarks on Fourier Transform and Differential Operators for Digital Functions
Current-Mode CMOS Galois Field Circuits
Construction of Ternary Bent Functions From Ternary Linear Functions
The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits
47th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2017, Novi Sad, Serbia, May 22-24, 2017
Multi-Valued Neural Logic Networks
Complexity of Decision Trees for Boolean Functions
Redundant Complex Arithmetic and Its Application to Complex Multiplier Design
Multi-valued Quantum Cascade Realization with Group Decomposition
CNOT-Measure Quantum Neural Networks
The Number of Cascade Functions
Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions
A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms
Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms
Design of Set-Valued Logic Networks for Wave-Parallel Computing
Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups
Comparison of Spectrally Efficient Coding Techniques for High-Speed Serial Links
Equivalence between varieties of Post algebras with a distinguished automorphism and pth root rings
Partially Ordered Set with Residuated t-norm
A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic
Hintikka Style Game Rules for Semi-Fuzzy Quantifiers
Many-Valued and Annotated Modal Logics
2 n +1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle
Chaotic Time Series Prediction Using Neuro-Fuzzy Systems with Cluster-Based Tribes Optimization Algorithm
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions