yusuke1997/dblp-id-title huggingface dataset:
On the Usage of Programming Languages in the iOS Ecosystem
12th IEEE International Working Conference on Source Code Analysis and Manipulation, SCAM 2012, Riva del Garda, Italy, September 23-24, 2012
Techniques for Efficient Automated Elimination of False Positives
Does code review really remove coding convention violations?
An Exploratory Study of Functional Redundancy in Code Repositories
CharmFL: A Fault Localization Tool for Python
A Case Study in Detecting Software Security Vulnerabilities Using Constraint Optimization
Concepts as Syntactic Sugar
Evaluating Clone Detection Tools for Use during Preventative Maintenance
An Empirical Study of Code Smells in Transformer-based Code Generation Techniques
Using Data Flow Analysis to Infer Type Information in Java Bytecode
Identifying 'Linchpin Vertices' That Cause Large Dependence Clusters
[Research Paper] Periodic Developer Metrics in Software Defect Prediction
The Java System Dependence Graph
Infant mortality tests for analog and mixed-signal circuits
Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking
An optimized testable architecture for finite state machines
Instruction-Based Self-Testing of Processor Cores
A novel method for fast identification of peak current during test
Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit
In-depth soft error vulnerability analysis using synthetic benchmarks
13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA
Improved Handling of False and Multicycle Paths in ATPG
Innovative practices session 2C: Advanced in yield learning
Fast WAT test structure for measuring Vt variance based on latch-based comparators
Pseudo-Functional Scan-based BIST for Delay Fault
Silicon-on-Insulator Technology Impacts on SRAM Testing
Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os
Knob non-idealities in learning-based post-production tuning of analog/RF ICs: Impact & remedies
28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA
Innovative Test Practices in Japan
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs
Compression Technique for Interactive BIST Application
Low-power test planning for arbitrary at-speed delay-test clock schemes
Low cost high frequency signal synthesis: Application to RF channel interference testing
Architectural Radiation Hardening of CMOS Power Management Circuits through Bias Tuning
BIST: Advantages or Limitations?
Combinational circuit ATPG using binary decision diagrams
Quality versus cost analysis for 3D Stacked ICs
Session Abstract
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?
Testing MEMS
Test Economics for Multi-site Test with Modern Cost Reduction Techniques
Test implications and challenges in near threshold computing special session
Statistical techniques for predicting system-level failure using stress-test data
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron
Enhanced Wear-Out Sensor Design in a 12nm Process for Separable Stress Regime Monitoring
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects
Structural constraints for circular self-test paths
Test preparation for high coverage of physical defects in CMOS digital ICs
Special session 8B: Embedded tutorial challenges in SSD
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients
A software system architecture for testing multiple part number wafers
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set
Power Dissipation During Testing: Should We Worry About it?
Reliability enhancement using in-field monitoring and recovery for RF circuits
A novel built-in current sensor for I DDQ testing of deep submicron CMOS ICs
22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA
Thermal Testing: Fault Location Strategies
Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators
An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs
On the Reliability of In-Memory Computing: Impact of Temperature on Ferroelectric TCAM
Mitigating Read Failures in STT-MRAM
A definition of the number of detections for faults with single tests in a compact scan-based test set
Asymmetric sizing: An effective design approach for SRAM cells against BTI aging
Test Resource Partitioning and Optimization for SOC Designs
Testing Systems Wirelessly
Beyond CMOS
Optimizing Test Length for Soft Faults in DRAM Devices
Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs)
Bridges in sequential CMOS circuits: current-voltage signatur
Innovate Practices on CyberSecurity of Hardware Semiconductor Devices
Special session on early life failures
An IDDQ BIST approach to characterize phase-locked loop parameters
Changing the Scan Enable during Shift
Efficient Monte Carlo-based analog parametric fault modelling
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure
Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOS
Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits
Millimeter-wave and THz Measurement Practices
Impact of crosstalk and process variation on capture power reduction for at-speed test
On Using Efficient Test Sequences for BIST
Soft-Error Hardening Designs of Nanoscale CMOS Latches
Special session 11B: ITRS adaptive test update
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation
SDRAM Delay Fault Modeling and Performance Testing
Diagnosis of interconnects and FPICs using a structured walking-1 approach
Signature Rollback - A Technique for Testing Robust Circuits
Generation of testable designs from behavioral descriptions using high level synthesis tools
Low Power BIST via Non-Linear Hybrid Cellular Automata
Diagnosis of Delay Defects Using Statistical Timing Models
Production Test Methods for Measuring 'Out-of-Band' Interference of Ultra Wide Band (UWB) Devices
Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis
SCT: An Approach For Testing and Configuring Nanoscale Devices
Test response compaction using arithmetic functions
DfT for the Reuse of Networks-on-Chip as Test Access Mechanism
Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile Sets
Test Vector Compression Using EDA-ATE Synergies
The Impact of NoC Reuse on the Testing of Core-based Systems
On-the-fly variation tolerant mapping in crossbar nano-architectures
Power Characterization of Embedded SRAMs for Power Binning
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
Session 4B - Panel data analytics in semiconductor manufacturing
Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum
Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection
New topic session 2B: Co-design and reliability of power electronic modules - Current status and future challenges
Error Sequence Analysis
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling
A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips
Neural models for transistor and mixed-level test generation
A partial scan methodology for testing self-timed circuits
Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime
Special Session: Fault Criticality Assessment in AI Accelerators
Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency
GATPS: An attention-based graph neural network for predicting SDC-causing instructions
MINVDD Testing for Weak CMOS ICs
Arithmetic built-in self test for high-level synthesis
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk
Machine Learning-Based Overkill Reduction through Inter-Test Correlation
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation
Innovations in Test Automation
Determination of coherence errors in ADC spectral domain testing
Multi-core Vmin and Worst-core Vmin Prediction using SOMAC
Deterministic Test Vector Decompression in Software Using Linear Operations
Designing self-exercising analogue checkers
ATPG for scan chain latches and flip-flops
A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis
Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions
DC Stimulus Electrical Calibration of MEMS Accelerometers
Special Session: Approximation and Fault Resiliency of DNN Accelerators
A Low-Speed BIST Framework for High-Performance Circuit Testing
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor
Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing
March LR: a test for realistic linked faults
Silicon Evaluation of Logic Proximity Bridge Patterns
Multi-Level Reference for Test Coverage Enhancement of Resistive-Based NVM
Panel: Is design-for-security the new DFT?
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators
Current signatures [VLSI circuit testing]
Opportunities for Built-In Self-Test Within Emerging mm-Wave Phased-Array and MIMO Architectures
Functional Test of Field Programmable Analog Arrays
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations
Hardware Security and Test for AMS Circuits
Panel 4A: Apprentice - VTS edition: Season 3
Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques
A low cost 100 MHz analog test bus
The multi-configuration: A DFT technique for analog circuits
Hierarchical fault modeling for analog and mixed-signal circuits
CURRENT: a test generation system for I DDQ testing
Embedded two-rail checkers with on-line testing ability
Testing of Dynamic Logic Circuits Based on Charge Sharing
Special Session: Photonic IC Testing - Challenges and Opportunities
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers
Innovative practices on design & test for flexible hybrid electronics
Challenges in Nanometric Technology Scaling: Trends and Projections
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions
A methodolgy for characterizing cell testability
A Novel Solution for Chip-Level Functional Timing Verification
Low Coverage Analysis using dynamic un-testability debug in ATPG
Novel architectures for TSC/CD and SFS/SCD synchronous controllers
Testing of flow-based microfluidic biochips
Innovative Practice on Wafer Test Innovations
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling
Innovative practices session 9C: Implications of power delivery network for validation and testing
Predictive Test Technique for Diagnosis of RF CMOS Receivers
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging
Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures
An analysis and testing of operation induced faults in MOS VLSI
Special Session: A Testability Practitioner's Guide to Chiplets
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification
Analog circuit observer blocks
At-speed testing of ASICs
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography
Maintaining Accuracy of Test Compaction through Adaptive Re-learning
Development of test programs in a virtual test environment
Enabling ECC and Repair Features in an eFuse Box for Memory Repair Applications
IR drop prediction of ECO-revised circuits using machine learning
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST
Transition Tests for High Performance Microprocessors
3D microelectronic with BEOL compatible devices
ExTest scheduling for 2.5D system-on-chip integrated circuits
An approach for system tests design and its application
An analytical model for predicting the residual life of an IC and design of residual-life meter
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes
Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips
A new digital test approach for analog-to-digital converter testing
Developments in delay testing
SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks
On the use of multi-cycle tests for storage of two-cycle broadside tests
An Efficient BIST Method for Small Buffers
Special session 6C: New topic mixed-signal test impact to SoC commercialization
Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs
Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level
Learning the process for correlation analysis
Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop Testing
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies
Parallelization methods for circuit partitioning based parallel automatic test pattern generation
Memristor-Specific Failures: New Verification Methods and Emerging Test Problems
LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware
Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan
Performance Comparison of VLV, ULV, and ECR Tests
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors
Reliability Challenges for Advanced Packaging
Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links
A Successful DFT Tester: What Will It Look Like? Is Revolution in Test Approaches Required?
Yield improvement of an EEPROM for automotive applications while maintaining high reliability
Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits
A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units
Reliability evaluation of combinational logic circuits by symbolic simulation
Case Study: Soft Error Rate Analysis in Storage Systems
On Low-Capture-Power Test Generation for Scan Testing
Design for Bit Error Rate estimation of high speed serial links
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits
Testing trees for multiple faults
Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test
An oscillation-based test technique for on-chip testing of mm-wave phase shifters
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST
Simulation of at-speed tests for stuck-at faults
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding
A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays
Testable design for BiCMOS stuck-open fault detection
A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing
The MCM's thermal testing
Test challenges and solutions for emerging non-volatile memories
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing
Defect-Aware SOC Test Scheduling
42nd IEEE VLSI Test Symposium, VTS 2024, Tempe, AZ, USA, April 22-24, 2024
Industrial practices of test cost reduction: Perspective, current design practices
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety
Special session 12A: Hot topic counterfeit IC identification: How can test help?
Fault modeling and testing of 1T1R memristor memories
HLSIM-a new hierarchical logic simulator in APL
Smart selection of indirect parameters for DC-based alternate RF IC testing
Detection and location of faults and defects using digital signal processing
A novel hybrid method for SDD pattern grading and selection
Impact of multiple input switching on delay test under process variation
Design of low cost ROM based test generators
Refreshing the JTAG Family
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses
Delay fault testing of iterative arithmetic arrays
Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages
An optimized delay testing technique for LSSD-based VLSI logic circuits
Empirical bounds on fault coverage loss due to LFSR aliasing
Design of Test Access Mechanism for AMBA-Based System-on-a-Chip
40th IEEE VLSI Test Symposium, VTS 2022, San Diego, CA, USA, April 25-27, 2022
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division
A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing [of SRAMs]
APT: Optimal Tree for Diagnosis Simulation
Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test Sequences
Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation
Innovative Practices Track: Silent Data Errors
39th IEEE VLSI Test Symposium, VTS 2021, San Diego, CA, USA, April 25-28, 2021
Efficient Array Characterization in the UltraSPARC T2
A Self Calibrated ADC BIST Methodology
Innovative practices session 2C: Memory test
SOC test compression scheme using sequential linear decompressors with retained free variables
Explorations of sequential ATPG using Boolean satisfiability
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data
Coverage metrics for functional tests
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
Flexible scan interface architecture for complex SoCs
Methodology of generating dual-cell-aware tests
All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and Diagnosis
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test
From Signals to Features to Insights: Multi-Level Novelty Detection for Fast Scientific Discovery
Special Session: Noisy Intermediate-Scale Quantum (NISQ) Computers - How They Work, How They Fail, How to Test Them?
Selection of tests for outlier detection
Fiscal: Firmware identification using side-channel power analysis
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector
On broad-side delay test
Unsupervised Root-Cause Analysis with Transfer Learning for Integrated Systems
Special Session: Test Challenges in a Chiplet Marketplace
On-line delay testing of digital circuits
Concurrent error correction in iterative circuits by recomputing with partitioning and voting
Test Technology Educational Program: Overview of Tutorials
LFSROM an algorithm for automatic design synthesis of hardware test pattern generator
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency
Aliasing error for a mask ROM built-in self-test
Enhanced hotspot detection through synthetic pattern generation and design of experiments
Effectiveness of I-V Testing in Comparison to IDDq Tests
Special session on intelligent sensor nodes
Modular TSC Checkers for Bose-Lin and Bose Codes
Scan Tests with Multiple Fault Activation Cycles for Delay Faults
Very Low Voltage Testing of SOI Integrated Circuits
On diagnosis of faults in a scan-chain
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models
Maintaining NIST-Traceability for MEMS Sensors via In-Field Electrical Recalibration
Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing
Test Compaction Using (k, 1)-Cycle Tests
Static logic implication with application to redundancy identification
Analyzing the Need for ATPG Targeting GOS Defects
Design for Testability and Testing of IEEE 1149.1 Tap Controller
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults
Hybrid Methodology for Verification of SW Safety Mechanisms
Calibrated high-efficiency testing and modelling methodologies for concentrated multi-junction solar cells
A distributed BIST control scheme for complex VLSI devices
Reusing NoC-infrastructure for test data compression
Test Methods for TID Effects on Capacitors
Special session: Hot topics: Statistical test methods
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor
Design of Phase Shifters for BIST Applications
A new built-in self-test method based on prestored testing
A Novel mechanism for speed characterization during delay test
CED-HDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional Computing
Effect of Noise on Analog Circuit Testing
Analysis and Design of Optimal Combinational Compactors
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks
Minimal hardware multiple signature analysis for BIST
On-line testing of switched-capacitor filters
Securing IJTAG against data-integrity attacks
Layered Approach to Designing System Test Interfaces
Multiple Coupling Effects Oriented Path Delay Test Generation
A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection
Zero cost testing of check bits in RAMs with on-chip ECC
Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs
At-speed capture global noise reduction & low-power memory test architecture
A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester Resources
Innovative practices session 5C: Advancements in test -keeping moore moving!
Highly testable and compact single output comparator
Active polymers for bio medical microdevices and microfluidic systems
Structural tests of slave clock gating in low-power flip-flop
Innovative practices session 4A variation-tolerant design of circuits/systems
A multi-faceted approach to FPGA-based Trojan circuit detection
A Statistical Approach to Characterizing and Testing Functionalized Nanowires
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
Test Data Compression for System-on-a-Chip Using Golomb Codes
A convergent procedure for partially-reachable states
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment
Synthesis of X-Tolerant Convolutional Compactors
Hidden Markov and Independence Models with Patterns for Sequential BIST
A Technique for Logic Fault Diagnosis of Interconnect Open Defects
Test and diagnosis of paper-based microfluidic biochips
Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling
Towards an Understanding of No Trouble Found Devices
Test pattern generation for current testable faults in static CMOS circuits
Low-Cost Alternate EVM Test for Wireless Receiver Systems
Linear finite state machine for lD ILAs
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost