yusuke1997/dblp-id-title huggingface dataset:
An Area Effective Programmable Front-end Amplifier for Neural Signal Acquisition
An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder
A Survey of Recent Attacks and Mitigation on FPGA Systems
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices
Digital Right Management for IP Protection
Dynamic Phase-Based Optimization of Embedded Systems
A Scalable Design Approach to Efficiently Map Applications on CGRAs
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
Profile-Driven Power Optimizations for AAL Robots: Maximizing Robots Idle Time by Offloading Monitoring Workload to Dedicated Hardware Components
Reliability-Aware SOC Voltage Islands Partition and Floorplan
QCA Systolic Matrix Multiplier
Tile Architecture and Hardware Implementation for Computation-in-Memory
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier
Intelligent NOC Hotspot Prediction
TDC: Tagless DRAM Cache
LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits
Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks
Area Efficient NMOS Based Positive and Negative Voltage Multiplier
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability
DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT
Titan II : An IPComp Processor for 10Gbit/sec networks
Guessing Your PIN Right: Unlocking Smartphones with Publicly Available Sensor Data
Efficient Majority Logic Modulo 2 n -1 Adder Design
Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETs
A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test
Enhancing PRESENT-80 and Substitution-Permutation Network Cipher Security with Dynamic "Keyed" Permutation Networks
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs
Concurrent Pseudo-Exhaustive Testing of Combinational VLSI Circuits
Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs
RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonics
MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications
Designing Memory Subsystems Resilient to Process Variations
Clock Tree Synthesis with XOR Gates for Polarity Assignment
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA
A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline
Evaluation of Compilers Effects on OpenMP Soft Error Resiliency
A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator
NoC Power Optimization Using a Reconfigurable Router
On-the-Fly Evaluation of FPGA-Based True Random Number Generator
A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management
Enhancing Performance of Floating Point Units Using Parallel Prefix Adders
Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning
Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET
Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool
A Transient-Enhanced Capacitorless LDO Regulator with improved Error Amplifier
Finding the Best Compromise in Compiling Compound Loops to Verilog
Tunable Approximate Booth Multiplier
Design and Analysis of Low Power Dynamic Bus Based on RLC simulation
Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors
An Analytical Drain Current Model for Short-Channel Triple-Material Double-Gate MOSFETs
Mapping Data and Code into Scratchpads from Relocatable Binaries
Centrality Indicators for Efficient and Scalable Logic Masking
Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead
An Optimized Architecture For Decomposed Convolutional Neural Networks
Analog Circuit Implementation of Neural Networks for In-Sensor Computing
Efficient Implementation of RISC-V Vector Permutation Instructions
Regulating Degree of Adaptiveness for Performance-Centric NoC Routing
Investigating Fairness in Disaggregated Non-Volatile Memories
3DPlace: Timing-driven Detailed Placement for Monolithic 3D ICs
Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures
2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015
A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes
Computational Architectures Based on Coupled Oscillators
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation
A High-accuracy Time-efficient Error Metric Model for Approximate Computing Circuits
Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs
Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies
Variation Aware Placement for FPGAs
Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows
Vector Processing Support for FPGA-Oriented High Performance Applications
Can ML-Based Reliability Models Span Quantum Hardware Boundaries?
Improved Yield in Nanotechnology Circuits Using Non-square Meshes
Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges
2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA
Floorplanning Based on Particle Swarm Optimization
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation
LISA: LLM Informed Systemverilog Assertion generation with RAG and Chain-of-Thought
A Reconfigurable Array Architecture for NML
Reconfigurable Support Vector Machine Classifier with Approximate Computing
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs
CMOS Gates with Second Function
AIFSP: An Adaptive Instruction Flow Stream Processor
CCATDC: A Configurable Compact Algorithmic Time-to-Digital Converter
Custom enhancements to networked processor templates
Control and Data Flow Graph Extraction for High-Level Synthesis
Precise Duty Cycle Variation Detection and Self-Calibration System for High-Speed Data Links
An IoT Enabled Real-Time Communication and Location Tracking System for Vehicular Emergency
A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures
The Road to Widely Deploying Processing-in-Memory: Challenges and Opportunities
Decoding of Stochastically Assembled Nanoarrays
Nanowire Addressing in the Face of Uncertainty
Optimization and Evaluation of Energy-Efficient Mixed-Signal MFCC Feature Extraction Architecture
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM
Design of an Asynchronous Detector with Priority Encoding Technique
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd
An Inkjet-Printed Flexible Memristor Device for Echo State Networks
A Survey of Side-Channel Attacks in Superconducting Quantum Computers
Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN
Low Power Single Electron Or/Nor Gate Operating at 10GHz
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Towards Supporting Fault-Tolerance in FPGAs
Regular Routing Architecture for a LUT-based MPGA
Neural Networks as a Side-Channel Countermeasure: Challenges and Opportunities
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era
Configurable Multiprocessors for High-Performance MPEG-4 Video Coding
Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints
Design and Hardware Implementation of a PRNG-CS for Embedded Security Applications
Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks
Feature Based Coverage Analysis of AMS Circuits
DERauth: A Battery-Based Authentication Scheme for Distributed Energy Resources
Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading
X4-RARE: Revisiting the X4CP32 Coarse-Grained Reconfigurable Architecture Model
Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey
Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design
New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui
Sparse-Aware NTT: Accelerating Lattice-Based Cryptography on FPGAs
Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough
Linear Optimization for Memristive Device in Neuromorphic Hardware
Application-Specific Energy Optimization of General-Purpose Datapath Interconnect
Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level
High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit
DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC
A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface
A Family of Area-Time Efficient Modulo 2n+1 Adders
Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFET
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths
Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection
HDXplore: Automated Blackbox Testing of Brain-Inspired Hyperdimensional Computing
A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI
Performance Enhancement of Split Length Compensated Operational Amplifiers
Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution
Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling
Design & implementation of software defined radios on a homogeneous multi-processor architecture
2-Output Spin Wave Programmable Logic Gate
Speedup of Self-Timed Digital Systems Using Early Completion
A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC
Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices
Unobtrusive Wearable Health Monitoring System
Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications
Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips
An Architectural Leakage Power Simulator for VHDL Structural Datapaths
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs
System Design and Power Optimization for Mobile Computers
Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions
Long-Term Predictive Analytics of Continuous Glucose Sensing for Enhanced Glycemic Control
Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy
Exploiting Software Pipelining for Network-on-Chip architectures
Compiler-Directed Data Cache Leakage Reduction
Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support
Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level Synthesis
An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard
Automated Dynamic Memory Data Type Implementation Exploration and Optimization
Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks
A Survey of Microarchitecture Support for Embedded Processor Security
Performance Analysis of 3D NoCs Partitioning Methods
Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes
FastNTT: Design and Evaluation of Modular-Reduction Based Fast NTT Design on FPGA
Carbon-Efficient 3D DNN Acceleration: Optimizing Performance and Sustainability
Logic Locking Induced Fault Attacks
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors
A Novel Low Power Multilevel Current Mode Interconnect System
High-Performance Noise-Robust Asynchronous Circuits
A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET
A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction
A Receiver Circuit for Low-Swing Interconnect Schemes
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
A DNN Protection Solution for PIM accelerators with Model Compression
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries
An Accurate All CMOS Temperature Sensor for IoT Applications
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis
A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions
Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design
Homomorphic Data Isolation for Hardware Trojan Protection
Quasi-Exact BDD Minimization Using Relaxed Best-First Search
Logical Core Algorithm: Improving Global Placement
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing
Towards a Faster Simulation of SystemC Designs
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits
A Novel Low-Power Clock Skew Compensation Circuit
Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems
Self-HWDebug: Automation of LLM Self-Instructing for Hardware Security Verification
Self-Timed Design with Dynamic Domino Circuits
Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache
Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization
Reduction of Current Mismatch in PLL Charge Pump
An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs
Lemma Exchange in a Microcontroller Based Parallel SAT Solver
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference
Dynamic Mitigation of Hardware Trojan Induced Black Hole Router Attack in Network-on-Chip
Equivalence Checking Using Trace Partitioning
Symbolic verification of timed asynchronous hardware protocols
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate
Efficient Deployment of Very Wide and Very Deep Hypersparse FFNs on FPGA
Sub-Micron Binary HyperPixel Sensor Circuit: In-Pixel Binarization with Variable Thresholding
Regulator-Gating Methodology with Distributed Switched Capacitor Voltage Converters
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power
Static Compaction by Merging of Seeds for LFSR-Based Test Generation
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs
Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits
Optimizing LU Decomposition with RISC-V Based Hardware Acceleration
Routing-Aware Incremental Timing-Driven Placement
PUF-ML: Machine Learning - Based Physical Unclonable Functions For Cost Effective Integration In Smart Healthcare
Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip
Metal Fix and Power Network Repair for SOC
Aging-Aware Instruction Cache Design by Duty Cycle Balancing
Exploration of 2D Cellular Automata as Binary Sequence Generators
A Prefix Based Reconfigurable Adder
A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing
A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular Automata
FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes
AI-enabled Application Process Interface for On-device Personalized Blood Pressure Monitoring
A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications
LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support
Handling Data Streams while Compiling C Programs onto Hardware
A PUF Based CAN Security Framework
A Multi-Scale Lightweight 1D-CNN for Efficient CAN Intrusion Detection
Voice Based User-Device Physical Unclonable Functions for Mobile Device Authentication
Design of An Approximate FFT Processor Based on Approximate Complex Multipliers
Enhancing Graph Execution for Performance and Energy Efficiency on NUMA Machines
A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG)
Dynamic encryption key design and management for memory data encryption in embedded systems
BLAS Comparison on FPGA, CPU and GPU
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits
On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012
On the Compressibility of Power Grid Models
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
The Impact of Process Faults on Specific Parameters of a 1.9GHz CMOS Mixer
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation
PRIVATEER: Secure FPGA Acceleration for 6G AI Edge Analytics
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems
Performance of Graceful Degradation for Cache Faults
On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors
Dynamic Coding Technique For Low-Power Data Bus
On Leveraging Multi-threshold FinFETs for Design Obfuscation
A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays
An Efficient Algorithm for the Analysis of Cyclic Circuits
Dual-Sum Single-Carry Self-Timed Adder Designs
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks
Development of a Layout-Level Hardware Obfuscation Tool
Message from the Technical Program Chair
Distributed Kriging-Bootstrapped DNN Model for Fast, Accurate Seizure Detection from EEG Signals
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation
A Modified Cascaded Sigma-Delta Modulator with Improved Linearity
A Hardware Monitor to Protect Linux System Calls
A Flexible Datapath Interconnect for Embedded Applications
A Robust Synchronizer
On Protecting IJTAG from Data Sniffing and Alteration Attacks
CellFlow: Automated Standard Cell Design Flow
Reducing the Storage Requirements of a Set of Functional Test Sequences by Using a Background Sequence
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins
Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design
Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis
Efficient Metastability-Containing Multiplexers
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators
A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications
Hardware-Optimized RNN Detection for Insertion/Deletion Channels in Wireless Communication
Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy Consumption
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Detection of Sequential Trojans in Embedded System Designs Without Scan Chains
PTL: PCM Translation Layer
Crosstalk Logic Circuits with Built-in Memory
A Hierachical Method for Wiring and Congestion Prediction
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression
Symposium Committees
A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors
Memory Power Modeling - A Novel Approach
Treating Quantifiers in Database Semantics
Transforming Concept D Schema into Relational Database Schema
Information Modelling and Knowledge Bases XXII, 20th European-Japanese Conference on Information Modelling and Knowledge Bases (EJC 2010), Jyväskylä, Finland, 31 May - 4 June 2010
Converting Ordinary Rules into Default Rules Based on Contradiction of Knowledge Base
Metadata as Support for Data Provenance
Inductive Inference of Regular Term Free Languages and Its Application to Knowledge Discovery
A Description-based Approach to Mashup of Web Applications, Web Services and Mobile Phone Applications
A New Partial Information Extraction Method for Personal Mashup Construction
Information Modelling for Preference Analysis of Musical Instrument Sounds
Q-Learning as Failure
Modelling Knowledge Logistics for Knowledge Management
Prototype Systems of Life Support Network for Rural Living People
Inferencing in Database Semantics
Intelligent software support of the SCRUM process
The Discourse Tool: A Support Environment for Collaborative Modeling Efforts
A Proposal for a User Oriented Language Based on the Lyee Theory
A Mutual Resource Exchanging Model in Mobile Computing and its Applications to Universal Battery and Bandwidth Sharing
Performance Forecasting for Performance Critical Huge Databases
A Dengue Location-Contraction Risk Calculation Method for Analyzing Disease-Spread
The 4D World Map System with Semantic Spatiotemporal Analyzers
Concepts and Ontologies
Opportunities and Pitfalls of IT Architectures for Edge Computing
Optimization of Processes in Multimedia Content Publishing: A Proposal for Architecture Design
Estimating Actual Evapotranspiration from NDVI Using Landsat 8 and Sentinel-2 Imagery
Concept Theory vs. Set Theory
A Case-Based Analysis of Process Modeling for Public Administration System Design
Visual Programming for Artificial Intelligent and Robotic Application (VPAR) Framework
Semiotic Aspects of Generalized Bases of Data
An Analysis Method for Heating Network Leaks Monitoring
Challenge in Urban Flood Mitigating System: Decision Support based on Cyber-Physical-Human Infrastructure
Manufacturing Roadmaps as Information Modelling Tools in the Knowledge Economy
Discussion Session on Concept Theory and Conceptual Modelling
On the Construction of Ontologies based on Natural Language Semantic
Logic of Dynamic Discourse; Anaphora Resolution
Forecasting Industrial Wastes to Wastes Disposal Management by Using Box-Jenkins Autoregressive Integrated Moving Average Models and Excel Application: Case Study on Opthalmic Plastic Lens Production of Company A in Thailand
Context-Sensitive Framework for Visual Analytics in Energy Production from Biomass
A Conceptual Space Logic
Process and Logic Approaches in the Intelligent Agents Behavior