yusuke1997/dblp-id-title huggingface dataset:
A data structure for a computer aided design system
An automated, reconfigurable, low-power RFID tag
Design through transformation
Precon: A Precision-Convertible Architecture for Accelerating Quantized Deep Learning Models across Various Domains Including LLMs
Lightning Talk 21: EDA with ML, Rule-Based, or Both?
Instruction Splitting for Efficient Code Compression
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling
Distance driven finite state machine traversal
HH-PIM: Dynamic Optimization of Power and Performance with Heterogeneous-Hybrid PIM for Edge AI Devices
Power management through DVFS and dynamic body biasing in FD-SOI circuits
An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices
Static leakage reduction through simultaneous threshold voltage and state assignment
AL-PA: cross-device profiled side-channel attack using adversarial learning
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem
Detecting tangled logic structures in VLSI netlists
A module level simulation technique for systems composed of LSI's and MSI's
Simulating pass transistor circuits using logic simulation machines
Structured design methodologies
EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs
Sign bit is enough: a learning synchronization framework for multi-hop all-reduce with ultimate compression
RuleBase: An Industry-Oriented Formal Verification Tool
On Static Compaction of Test Sequences for Synchronous Sequential Circuits
Retention Trimming for Wear Reduction of Flash Memory Storage Systems
Aw expanded logic equation list for checkout
Robust partitioning for hardware-accelerated functional verification
Automated Design Decision Support System
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing
Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation
An integrated algorithm for memory allocation and assignment in high-level synthesis
Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries
A simple computer-aided artwork system that works
Efficient code synthesis from extended dataflow graphs for multimedia applications
From Network to Artwork
Garrison: A High-Performance GPU-Accelerated Inference System for Adversarial Ensemble Defense
Modeling and analysis of circuit performance of ballistic CNFET
Layla: a VLSI layout language
GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian Splatting
Optimized selection of wireless network topologies and components via efficient pruning of feasible paths
Hypernel: a hardware-assisted framework for kernel protection without nested paging
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead
Formal Verification of FIRE: A Case Study
Some consideration on the data model of geometric data bases
An Empirical Study of On-chip Parallelism
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses
Model Development and Verification for High Level Analog Blocks
Panel: When Will the Analog Design Flow Catch Up with Digital Methodology?
Partitioning of VLSI Circuits and Systems
Automatic optical design with accos v program
COSAIM: Counter-based Stochastic-behaving Approximate Integer Multiplier for Deep Neural Networks
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs
Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks
Differentiable-timing-driven global placement
Workload and user experience-aware dynamic reliability management in multicore processors
Verification for Field-coupled Nanocomputing Circuits
An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form
Two New Techniques for Compiled Multi-Delay Logic Simulation
Design-for-testability of PLA's using statistical cooling
Module Compaction in FPGA-based Regular Datapaths
On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation
Formal Techniques for Effective Co-verification of Hardware/Software Co-designs
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture
System-Level Design for Test of Fully Differential Analog Circuits
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding
Standard cell characterization considering lithography induced variations
"A user's experience in Computer Aided Manufacturing" or "CAM" at GTE - Automatic Electric
Microprocessor Based Testing for Core-Based System on Chip
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming
Behavioral modeling of (coupled) harmonic oscillators
A multiple delay simulator for MOS LSI circuits
The Role of Timing Verification in Layout Synthesis
Technology tracking for VLSI layout design tools
Variations-aware low-power design with voltage scaling
Solution-processed infrared photovoltaic devices
Exact Required Time Analysis via False Path Detection
Human emotion based real-time memory and computation management on resource-limited edge devices
Space frame analysis and applications to other types of structures
Observational wear leveling: an efficient algorithm for flash memory management
Code Generation and Analysis for the Functional Verification of Microprocessors
Accelerating Switch-Level Simulation by Function Caching
Charge recycling in MTCMOS circuits: concept and analysis
Ragnar: Exploring Volatile-Channel Vulnerabilities on RDMA NIC
Algorithms for global routing
Non-volatile FPGAs based on spintronic devices
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective
Use of Change Coordination in an Information-rich Design Environment
An efficient algorithm for statistical timing yield optimization
The relational data model for CAD(Tutorial/Panel/Workshop): Close encounters of the third normal form
A Comparison of Four Two-dimensional Gate Matrix Layout Tools
History-based VLSI legalization using network flow
Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach
Symbolic analysis of analog circuits with hard nonlinearity
A moment-based effective characterization waveform for static timing analysis
Assertion-based verification of a 32 thread SPARC TM CMT microprocessor
Wafer Map Defect Patterns Classification using Deep Selective Learning
Power grid reduction based on algebraic multigrid principles
Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons
Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction
Macro-driven circuit design methodology for high-performance datapaths
An over-cell gate array channel router
Layout Driven Selecting and Chaining of Partial Scan
Optimal placement of power supply pads and pins
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation
A method for the best geometric placement of units on a plane
Tumbler: Energy Efficient Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes
A Computer Oriented Mechanical Design System
A helper thread based dynamic cache partitioning scheme for multithreaded applications
ReCG: ReRAM-Accelerated Sparse Conjugate Gradient
Function Search from Behavioral Description of a Digital System
Design tools for VLSI (Position Statement)
FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar Cores
A parallel integer programming approach to global routing
A simple, efficient design automation processor
Embedded intelligent SRAM
Validation with Guided Search of the State Space
A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix
A multilevel technique for robust and efficient extraction of phase macromodels of digitally controlled oscillators
Static Timing Analysis of Dynamically Sensitizable Paths
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
The case for elastic operating system services in fos
Ink: Efficient Incremental k-Critical Path Generation
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling
An Automated Design of Minimum-Area IC Power/Ground Nets
A novel wavelet transform based transient current analysis for fault detection and localization
UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification
Implementing the Vision: Electronic Design in the 1990's (Panel Abstract)
Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET Cells
Beyond safety: customized SAT-based model checking
Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems
Justification and financial analysis for CAD
CND-IDS: Continual Novelty Detection for Intrusion Detection Systems
Verification of asynchronous circuits using Time Petri Net unfolding
A design automation system for telephone electronic switching system
Compilation and virtualization in the HiPEAC vision
Guidelines to design parity protected write-back L1 data cache
Technology Summit - A View from the Top (Panel)
Dynamic Voltage Scaling and Power Management for Portable Systems
Electromigration Reliability Enhancement via Bus Activity Distribution
A model for hardware description and verification
The ITT VLSI design system: CAD integration in a multi-national environment
A symbolic design system for integrated circuits
An integrated CAD data base system
Techniques of gate assignment
Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes
An algorithm for integrated pin assignment and buffer planning
A Unified Approach to Input-Output Encoding for FSM State Assignment
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options
PACO: fast average-performance estimation for time-randomized caches
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model
The Princeton University Behavioral Synthesis System
HARPA: A hierarchical multi-level hardware description language
New Ideas for Solving Covering Problems
The Key to EDA Results: Component & Library Management (Panel Abstract)
E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system
InterConFuzz: A Fuzzing-based Comprehensive NoC Verification Framework
Program function test definition using a three-value simulator
A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential Circuits
A Programming Environment for the Design of Complex High Speed ASICs
Application mapping for chip multiprocessors
Automatic synthesis of clock gating logic with controlled netlist perturbation
Maximizing Energy Efficiency in Spiking Neural Networks: A Dynamic Joint Pruning Framework
HaVOC : a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories
Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters
A fast maze router with iterative use of variable search space restriction
Concepts in CAD data base structures
Employing classification-based algorithms for general-purpose approximate computing
Optimum Functional Decomposition Using Encoding
SAGA: A Memory-Efficient Accelerator for GANN Construction via Harnessing Vertex Similarity
Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation
Computer-aided space planning
Module Selection for Pipelined Synthesis
Precise and scalable shared cache contention analysis for WCET estimation
Variation aware cross-talk aggressor alignment by mixed integer linear programming
Communication-efficient hardware acceleration for fast functional simulation
A tool for computer design
Dataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUs
A 2-dimensional placement algorithm for the layout of electrical circuits
EDGE: Efficient DAG-based Global Routing Engine
ACTAS: an accurate timing analysis system for VLSI
Misleading performance claims in parallel computations
High-throughput TSV testing and characterization for 3D integration using thermal mapping
Area-Efficient Event Stream Ordering for Runtime Observability of Embedded Systems
The "PI" (placement and interconnect) system
Designing application versatility into a software package for numerically controlled drafting machines
Why Partial Design Verification Works Better Than It Should
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
Acquiring and Maintaining State-of-the-Art DA Systems
Data communication estimation and reduction for reconfigurable systems
Constraint-driven floorplan repair
A knowledge based system for selecting a test methodology for a PLA
DDRoute: a Novel Depth-Driven Approach to the Qubit Routing Problem
Optimization of Primitive Gate Networks Using Multiple Output Two-Level Minimization
A Simple Cache Coherence Scheme for Integrated CPU-GPU Systems
Computer aided design system for logic equipment applied to design of electronic switching equipment
The modeling and synthesis of bus systems
TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis
A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods
A chip-package-board co-design methodology
VISION: VHDL Induced Schematic Imaging on Net-Lists
Improving GNN-based accelerator design automation with meta learning
Low-energy encryption for medical devices: security adds an extra design dimension
BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network Acceleration
Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography
Automatic stability checking for large linear analog integrated circuits
A topologically based non-minimum distance routing algorithm
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
A Practical Online Design Rule Checking System
62nd ACM/IEEE Design Automation Conference, DAC 2025, San Francisco, CA, USA, June 22-25, 2025
Global Stratgies for Electronic Design (Panel Abstract)
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Frequency domain decomposition of layouts for double dipole lithography
DuQTTA: Dual Quantized Tensor-Train Adaptation with Decoupling Magnitude-Direction for Efficient Fine-Tuning of LLMs
Multiple patterning layout decomposition considering complex coloring rules
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores
Invited: Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
Placement of circuit modules using a graph space approach
User-perceived latency driven voltage scaling for interactive applications
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
Me-MPK: Accelerating Krylov Subspace Solvers via Memory-efficient Matrix-Power Kernel
Accurate Estimation of Program Error Rate for Timing-Speculative Processors
Design for testability in a silicon compilation environment
Invited: Waving the Double-Edged Sword: Building Resilient CAVs with Edge and Cloud Computing
Timing optimization of FPGA placements by logic replication
Graph in the Vault: Protecting Edge GNN Inference with Trusted Execution Environment
Language Extensions to SystemC: Process Control Constructs
Is statistical timing statistically significant?
(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs
A Parallel PLA Minimization Program
Block description language (BDL): A structural description language
Handling complexities in modern large-scale mixed-size placement
An extensible object-oriented mixed-mod functional simulation system
NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal Simulation
System Level Fixed-Point Design Based on an Interpolative Approach
A hardware assisted design rule check architecture
Lightning Talk: Unlocking the Potential of the Analog Domain: Exploring the Next Frontier in Hardware Security
Power minimization using control generated clocks
GNNIE: GNN inference engine with load-balancing and graph-specific caching
A network security processor design based on an integrated SOC design and test platform
Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision
Scalable specification mining for verification and diagnosis
Joint DAC/IWBDA special session engineering biology: fundamentals and applications
Dynamic Management of Scratch-Pad Memory Space
Placement feedback: a concept and method for better min-cut placements
An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration
Logic Optimization of MOS Networks
A class of min-cut placement algorithms
An adaptive FPGA architecture with process variation compensation and reduced leakage
Exploiting Computation Reuse for Stencil Accelerators
A module for improving data access and management in an integrated CAD environment
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures
Logic Synthesis for Engineering Change
Increasing Design Quality and Engineering Productivity through Design Reuse
An optimum layer assignment for routing in ICs and PCBs
Techniques for Effective Distributed Physical Synthesis
Probabilistic Analysis of Large Finite State Machines
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis
A Method of Delay Fault Test Generation
Estimation of the likelihood of capacitive coupling noise
SODA: Sensitivity Based Optimization of Disk Architecture
Computer aided schematics
Tutorial: The relational data model for Design Automation
HCI-tolerant NoC router microarchitecture
Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip
Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach
Self-test methodology for at-speed test of crosstalk in chip interconnects
Adaptive Granularity Encoding for Energy-efficient Non-Volatile Main Memory
LOTUS: learning-based online thermal and latency variation management for two-stage detectors on edge devices
Improving a PLA Area by Pull-Up Transistor Folding
Improving the Efficiency of Power Simulators by Input Vector Compaction
Enabling Low Latency for ECQF based Flow Aggregation Scheduling in Time-Sensitive Networking
A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision
Virtual channels vs. multiple physical networks: a comparative analysis
ThermalScope: A Practical Interrupt Side Channel Attack Based on Thermal Event Interrupts
CGaAs PowerPC FXU
Optimizing Recovery Logic in Speculative High-Level Synthesis
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Rethinking key-value store for byte-addressable optane persistent memory
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement
Integrated VLSI CAD systems at Digital Equipment Corporation
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule
Steep Slope Devices: Enabling New Architectural Paradigms
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Extended statistical element selection: a calibration method for high resolution in analog/RF designs
PICK: An SRAM-based Processing-in-Memory Accelerator for K-Nearest-Neighbor Search in Point Clouds
Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002
Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation
Efficient program scheduling for heterogeneous multi-core processors
Linking TCAD to EDA - Benefits and Issues
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications
Building a verification test plan: trading brute force for finesse
Typical Worst Case Response-Time Analysis and its Use in Automotive Network Design
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Graphic applications to aerospace structural design problems
ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method
Computer aided ship design at MarAd
A symbolic functional description language
A Layout Estimation Algorithm for RTL Datapaths
The concurrent simulation of nearly identical digital networks
File format for data exchange between graphic data bases
Post-route gate sizing for crosstalk noise reduction
An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology
River PLAs: a regular circuit structure
Protecting RISC-V against Side-Channel Attacks
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories
E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
SSIM: A Software Levelized Compiled-Code Simulator
Parameterized random testing
Framework Encapsulations: A New Approach to CAD Tool Interoperability
Simulator-oriented fault test generator
A Framework for Low Complexity Static Learning
INVITED: Computational Methods of Biological Exploration
Important criteria in selecting engineering work stations
Hardware Logic Simulation by Compilation
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs
Tools to Aid in Wiring Rule Generation for High Speed Interconnects
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
Post-silicon validation challenges: how EDA and academia can help
A compiler and runtime for heterogeneous computing
What's cool for the future of ultra low power designs?
Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Floorplan-aware automated synthesis of bus-based communication architectures
An efficient retiming algorithm under setup and hold constraints
MOS circuit models in Network C
Timing Optimization for Multi-Level Combinational Networks
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment
A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints
Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber
A Multi-Layer Channel Router with New Style of Over-the-Cell Routing
IGES as an interchange format for integrated circuit design
Standard cell sizing for subthreshold operation
The automatic printed wire routing system of BACKIS
Construction of concrete verification models from C++
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors