yusuke1997/dblp-id-title huggingface dataset:
Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs
Investigation of Communication Overhead of SoC Lookaside Accelerators
RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration
Multi-objective optimization of a low-noise antenna amplifier for multi-constellation satellite-navigation receivers
Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology
Experience Migrating OpenCL to SYCL: A Case Study on Searches for Potential Off-Target Sites of Cas9 RNA-Guided Endonucleases on AMD GPUs
Implementation of a network flow lookup circuit for next-generation packet classifiers
An Ultra-Low-Voltage Sub-Threshold Pseudo-Differential CMOS Schmitt Trigger
Simultaneous escape routing based on routability-driven net ordering
Low Power 20.625 Gbps Type-C USB3.2/DPl.4/ Thunderbolt3 Combo Linear Redriver in 0.25 μm BiCMOS Technology
A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications
A low supply voltage mixed-signal maximum power point tracking controller for photovoltaic power system
RoadRunner: A Modularized Design and Tool Manager for Hardware Projects
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO
kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation
Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique
High-purity 56-66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applications
Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO
MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices
A leakage-tolerant low-leakage register file with conditional sleep transistor
Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication
Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA
A low-power pairing-based cryptographic accelerator for embedded security applications
A novel fault-tolerant router architecture for network-on-chip reconfiguration
A Quantitative Approach to SoC Functional Safety Analysis
Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem
Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware
A low clock load conditional flip-flop
A single-phase energy metering SoC with IAS-DSP and ultra low power metering mode
A band-switching wide-band CMOS LC QVCO for multi-standard applications
Automatic debugging of System-on-a-Chip designs
On Efficient Crosstalk Predictability for Fanout Package Designs
Predictable system interconnects through accurate early wire characterization
Accurate power estimation of hardware co-processors using system level simulation
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS
Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits
Implementation of an SoC architecture with built-in safety features
Security challenges in mobile and IoT systems
"Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore's law"
What You Need to Know About Patent Litigation
A filter design to increase accuracy of Lucy-Richardson deconvolution for analyzing RTN mixtures effects on VLSI reliability margin
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies
Covert Communication Attacks in Chiplet-based 2.5-D Integration Systems
An early global routing framework for uniform wire distribution in SoCs
A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration
Adaptive multicast routing method for 3D mesh-based Networks-on-Chip
Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling
Bandgap yield loss due to dislocations on RFSiGe transceiver ICs: failure analysis, design
Tutorial 4A: Supply voltage noise and mitigation for real world SoCs
High-gain high-speed operational amplifier in digital 120nm CMOS
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding
Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation
A hardware acceleration scheme for memory-efficient flow processing
A multi-mode sphere detector architecture for WLAN applications
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards
A novel 5.46 mW H.264/AVC video stream parser IC
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s
Effective signal region based analog mixed signal design considering variations and applications
Efficient Hardware Acceleration of Convolutional Neural Networks
On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems
Material Intelligence: Exploiting Intrinsic Learning and Optimization Capabilities for Intelligent Systems
Designing multi-processor Systems-on-Chip
Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings
RF-MEMS resonator design for parameter characterization
Hardware Specification Aware Timing Side Channel Security Analysis
Hardware-Software Co-Design for Efficient LLM Inference on PCIe-Based FPGAs Using Coarse-Grained Systolic Arrays
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities
Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration
Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors
Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy
A synchronous interface for SoCs with multiple clock domains
Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency
Robust throughput boosting for low latency dynamic partial reconfiguration
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks
Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding
Reconfiguralbe multimedia accelerator for mobile systems
On the stability, transient and quiescent current control of one low-voltage class-AB op-amp architecture
Combined simulator statistics and block code sampling to study performance enhancement of microarchitecture
Low power repeaters driving RC interconnects with delay and bandwidth constraints
Probabilistic Computing for Sustainable Edge Devices Using Organic Electronics
A Low Latency Spiking Neural Network with Improved Temporal Dynamics
Clock buffer with duty cycle corrector
Energy-Efficient Black Hole Router Detection in Network-on-Chip
Integrated assignment of registers and functional units for heterogeneous vliw-architectures
An independent-gate FinFET SRAM cell for high data stability and enhanced integration density
MTNET: Design and Optimization of a Wireless SOC Test Framework
A massive parallel neuromorphic computing model for intelligent text recognition
T4A: System-on-chip design using Tri-gate technology
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping
HARDY: Hardware based Analysis for malwaRe Detection in embedded sYstems
Supercapacitor-based embedded hybrid solar/wind harvesting system architectures
Design Study on Impact of Memory Access Parallelism for Cloud FPGAs
Cache Organization for Embeded Processors: CAM-vs-SRAM
LIGHTER-R: Optimized Reversible Circuit Implementation For SBoxes
Design-for-testability automation of mixed-signal integrated circuits
LHF-NTT: Local Horizontal Folding Number Theoretic Transform Hardware Accelerator
A Hybrid and Distributed Access Integration for SMR Disks
An Efficient FPGA Accelerator for Point Cloud
An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform
ASIC Power Estimation Across Revisions using Machine Learning
A 1 ppm/°C bandgap voltage reference with new second-order Taylor curvature compensation
DeepShield: Lightweight Privacy-Preserving Inference for Real-Time IoT Botnet Detection
Introduction to the SystemC AMS DRAFT standard
Interrupt Communication on the SegBus platform
On-chip network based embedded core testing
Time sensitive networks for industry 4.0
One Time Programmable Memory for Light Powered ASICs
Numerical Analysis of Double-Gate OTFTs Using TCAD: Influence of Structural Parameters on Device Performance Flexible and Printable Electronics Applications
A high throughput router with a novel switch allocator for network on chip
A generic, scalable reconfiguration infrastructure for sensor networks functionality adaption
Programmable Voltage Reference Circuit Using an Analog Floating Gate Device
A 45 Gb/s, 98 fJ/bit, 0.02 mm 2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS
A digital-control sensorless current-mode boost converter with non-zero error bin compensation and seamless mode transition
A flexible two-layer external memory management for H.264/AVC decoder
An Efficient Hybrid Pseudo-Random Number Generator Based on CNTFET
Design of a low power CMOS 10bit flash-SAR ADC
An Investigation of Machine Learning Algorithms for High-bandwidth SQL Injection Detection Utilising BlueField-3 DPU Technology
Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch
A silicon core for an acoustic archival tag
A New Circuit Topology for High-Performance Pulsed Time-of- Flight Laser Radar Receivers
Accelerating Binary-Matrix Multiplication on FPGA
EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT using Stationary Neuromorphic Vision Sensors
Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits
A framework for specifying, modeling, implementation and verification of SOC protocols
2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006
A prototype platform for system-on-chip ADC test and measurement
An incremental floorplanning algorithm for temperature reduction
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video
Application specific instruction memory transformations for power efficient, fault resilient embedded processors
Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations
Robust Learning-to-Rank Algorithm for Bug Discovery in Hardware Verification
IP watermark verification based on power consumption analysis
Cluster Tool Performance Analysis using Graph Database
A tunable inverter-based, low-voltage OTA for continuous-time ΣΔ ADC
Wednesday Keynote: The Memory Wall: Challenges and Solutions
Approximate compressed sensing for hardware-efficient image compression
Unification of obstacle-avoiding rectilinear Steiner tree construction
DE-C3: Dynamic Energy-Aware Compression for Computing-In-Memory-Based Convolutional Neural Network Acceleration
Intra-die process parameter variation and leakage analysis of cache at the microarchitectural level
Design of low flicker noise active CMOS mixer
Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs
FPGA-efficient phase-to-I/Q architecture
Noisy neuromorphic circuit modeling Obsessive Compulsive Disorder
Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems
Efficient hardware architecture of softmax layer in deep neural network
Performance evaluation of High Bandwidth Memory for HPC Workloads
A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts
3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling Performance
Continuous Conduction Mode in Digital Control Loop of DC-DC
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip
Energy-Efficient FlashAttention Acceleration on CGLA
Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM
A 65nm low power 2T1D embedded DRAM with leakage current reduction
Transport Layer Assisted Routing for Non-Stationary Irregular mesh of thermal-aware 3D Network-on-Chip systems
Downlink-Centric User Scheduling for Full-Duplex MU-MIMO Systems
Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies
A comparative study of multi-GHz LCVCOs designed in 28nm CMOS technology
A Duty Cycle Error Reduction with 1-point Calibration achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores
Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communications
Towards More Secure PUF Applications: A Low-Area Polar Decoder Implementation
Compensating imperfections in RF-DAC based transmitters using LUT-based predistortion
Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels
Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator
Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors
21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings
A fully parallel content addressable memory design using multi-bank structure
Low power design under parameter variations
Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming
TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures
A stochastic learning algorithm for neuromemristive systems
Circuit level modeling and simulation of mixed-technology systems
HM2GP: A Multi-Version Task Scheduler with Extended Precedence Constraints on COTS SoCs
A weighted fair queuing finishing tag computation architecture and implementation
Applying ESL in A Dual-Core SoC Platform Designing
Dual-band CDR using a half-rate linear phase detector
Quantum Implementation of Linear and Non-Linear Layers
A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing
LinkBo: A Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications
Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications
Dynamic Power Analysis of Standard-Cell FPGA Fabrics
MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA
Analysis and design of monolithic, high PSR, linear regulators for SoC applications
A fast pull-in scheme of plls using a triple path nonlinear phase frequency detector
Configurable error correction for multi-wire errors in switch-to-switch SOC links
A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure
Fault-resilient routing unit in NoCs
Virtual Platform Acceleration through Userspace Host Execution
ML-Assisted Error-Tolerant Inexact Multiplier Allocation for Energy-Efficient Systolic Arrays
Zigzag Dataflow Architecture for Convolutional Neural Network
An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI
Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN
A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS
CoDe-CS: A CNN Accelerator with Co-Designed Compute and Storage for Edge Efficiency
Effects of Interconnect Process Variations on Signal Integrity
Simultaneous memory and bus partitioning for SoC architectures
Pvalite CLN: Lightweight Object Detection with Classfication and Localization Network
All-digital deskew buffer using a hybrid control scheme
System-level exploration of mesh-based NoC architectures for multimedia applications
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017
Performance Impact of Caches, Interrupt Strategies and Communication on SoC Lookaside Acceleration
Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator
A new design for built-in self-test of 5GHz low noise amplifiers
A low complexity multi standard dual band CMOS polar transmitter for smart utility networks
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design
Evaluating Deep Neural Network Performance on Edge Accelerators: A Roofline Model Adopted Benchmarking Approach
"Venice: A cost-effective architecture for datacenter servers"
AutoML for Multilayer Perceptron and FPGA Co-design
Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits
High Performance Flip-Flop Design Using a New Output Latch Scheme in Samsung 2nm GAA Process
A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHz
A virtual channel router for on-chip networks
Surveillance camera SOC architecture using one-bit motion detection for portable applications
A wide range programmable duty cycle corrector
An analog gamma correction method for high dynamic range applications
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs
Co-Optimizing CPUs and Accelerators in Constrained Systems
Generative adversarial network based scalable on-chip noise sensor placement
On-Chip Distributed Architectures
High throughput architecture for CLICHÉ Network on Chip
Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS
A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature Compensation
Power-aware design technique for PAC Duo based embedded system
A low cost method to tolerate soft errors in the NoC router control plane
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM
A Glitch Key-Gate for Logic Locking
BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT
Comparison between optimal interconnection network in different 2D and 3D NoC structures
A novel architectural approach for control architectures in RF transceivers
Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC
Design and Implementation of Stochastic Neural Networks Using Superconductor Quantum-Flux-Parametron Devices
Performance Investigation for IEEE 802.15.4z-compliant SiP-assisted Ranging
Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression
Sparse Attention: A Co-Design Approach for Efficient Transformer Execution on Tensor Cores
New power budgeting and thermal management scheme for multi-core systems in dark silicon
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration
Using power gating techniques in area-array SoC floorplan design
Loop acceleration and instruction repeat support for application specific instruction-set processors
Ultra low power QC-LDPC decoder with high parallelism
Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs
A new design methodology for Voltage-to-Time Converters (VTCs) circuits suitable for Time-based Analog-to-Digital Converters (T-ADC)
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design
Symbolic verification and error prediction methodology
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems
A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology
In-Network Accumulation: Extending the Role of NoC for DNN Acceleration
Dynamic fraction control bus: new SOC on-chip communication architecture design
A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization
A scan segmentation architecture for power controllability and reduction
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers
Multilevel routing with jumper insertion for antenna avoidance
Precharged SRAM cell for ultra low-power on-chip cache
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors
A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18 μm SiGe BiCMOS Technology
Reactive and Proactive Threat Detection and Prevention for the Internet of Things
A DSL for the SegBus platform
A reconfigurable 0-L1-L2 S-MASH 2 modulator with high-level sizing and power estimation
RECS: A Scalable Platform for Heterogeneous Computing
Device allocation on the SegBus platform based on communication scheduling cost minimization
Implementation of a hardware-efficient EEG processor for brain monitoring systems
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists
Reliability-aware floorplanning for 3D circuits
SPICE versus STA tools: Challenges and tips for better correlation
Can We Trust Machine Learning for Electronic Design Automation?
A multi-format floating-point multiplier for power-efficient operations
An instruction set architecture independent design method for embedded OFDM-based software defined transmitter
Dual-Band GSM Energy Harvester for a Duty-Cycle Approach in 180nm CMOS Technology
Programmable RFSoC-Based Antenna Emulator for MIMO System Prototyping
Analysis and Modeling of Passive LC Filters Using Node Elimination Technique
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
NBTI-aware statistical timing analysis framework
Exploiting memristive device behavior for emerging digital logic and memory applications
A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC
A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF)
High reliability built-in self-detection and self-correction design for DCT/IDCT application
Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing
Accurate Estimation of the CNN Inference Cost for TinyML Devices
A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter
A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control
Plenary: Boosting performance efficiency in multiprocessor systems through multi-threading
Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability
An Efficient Implementation of Arbiter PUF on FPGA for IoT Application
CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 cores
Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI
EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems
High speed mixed analog/digital PRML architecture for optical data storage system
Fair rate packet arbitration in Network-on-Chip
An FPGA implementation for a high-speed optical link with a PCIe interface
Microwave IC design for broadband receivers
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems