yusuke1997/dblp-id-title huggingface dataset:
Time-Triggered Conversion of Guards for Reachability Analysis of Hybrid Automata
Analyzing Real-Time Event-Driven Programs
Tropical Abstractions of Max-Plus Linear Systems
On Timed Simulation Relations for Hybrid Systems and Compositionality
Tapas: Theory Combinations and Practical Applications
Formal Modeling and Analysis of Timed Systems - 16th International Conference, FORMATS 2018, Beijing, China, September 4-6, 2018, Proceedings
A Local-Time Semantics for Negotiations
On the Expressiveness of MTL with Past Operators
Time-Optimal Test Cases for Real-Time Systems
Automatic Dynamic Parallelotope Bundles for Reachability Analysis of Nonlinear Systems
Nested Timed Automata
Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation
Confluence Reduction for Markov Automata
Formal Methods for Robot Motion Planning with Time and Space Constraints (Extended Abstract)
On Optimal Control of Stochastic Linear Hybrid Systems
Quantitative Analysis of Concurrent Reversible Computations
Refinements and Abstractions of Signal-Event (Timed) Languages
A Mechanized Semantic Framework for Real-Time Systems
Formal Modeling and Analysis of Timed Systems - 9th International Conference, FORMATS 2011, Aalborg, Denmark, September 21-23, 2011. Proceedings
Property-Driven Timestamps Encoding for Timeprints-Based Tracing and Monitoring
Robust Specification of Real Time Components
Contracts for Schedulability Analysis
Analysis of Real Time Operating System Based Applications
Formal Modeling and Analysis of Timed Systems, Third International Conference, FORMATS 2005, Uppsala, Sweden, September 26-28, 2005, Proceedings
CSL Model Checking Algorithms for Infinite-State Structured Markov Chains
Comparison of the Expressiveness of Timed Automata and Time Petri Nets
ParetoLib: A Python Library for Parameter Synthesis
Computing Equilibria in Two-Player Timed Games via Turn-Based Finite Games
Discrete-Time Rewards Model-Checked
Multi-core Reachability for Timed Automata
Translating Timed I/O Automata Specifications for Theorem Proving in PVS
Undecidable Problems About Timed Automata
Explaining Safety Violations in Real-Time Systems
A Framework for Verification of Software with Time and Probabilities
A Novel WCET Semantics of Synchronous Programs
Reducing Quasi-Equal Clocks in Networks of Timed Automata
Designing Consistent Multimedia Documents: The RT-LOTOS Methodology
Active Learning of Timed Automata with Unobservable Resets
Expected Reachability-Time Games
Algebraic Model Checking for Discrete Linear Dynamical Systems
Timed Parity Games: Complexity and Robustness
Formal Modeling and Analysis of Timed Systems - 17th International Conference, FORMATS 2019, Amsterdam, The Netherlands, August 27-29, 2019, Proceedings
Compositional Abstraction in Real-Time Model Checking
Intersection of Regular Signal-Event (Timed) Languages
Formal Modeling and Analysis of Timed Systems - 12th International Conference, FORMATS 2014, Florence, Italy, September 8-10, 2014. Proceedings
Online Quantitative Timed Pattern Matching with Semiring-Valued Weighted Automata
Stability and Performance Bounds in Cyclic Networks Using Network Calculus
A State Class Construction for Computing the Intersection of Time Petri Nets Languages
Counter-Free Input-Determined Timed Automata
Abstraction of Probabilistic Systems
Mcta: Heuristics and Search for Timed Systems
Symbolic Dependency Graphs for $$\text {PCTL}^{>}_{\le }$$ Model-Checking
Model Checking HML on Piecewise-Constant Inhomogeneous Markov Chains
Detecting Quasi-equal Clocks in Timed Automata
Stochastic Games for Verification of Probabilistic Timed Automata
Computing the Price of Anarchy in Atomic Network Congestion Games (Invited Talk)
Safraless Procedures for Timed Specifications
Real-Time Testing with Timed Automata Testers and Coverage Criteria
Checking ACTL * Properties of Discrete Timed Automata via Bounded Model Checking
Formal Modeling and Analysis of Timed Systems, 5th International Conference, FORMATS 2007, Salzburg, Austria, October 3-5, 2007, Proceedings
Verification and Control of Probabilistic Rectangular Hybrid Automata
Frequencies in Forgetful Timed Automata
Automata with Timers
Speeding Up Model Checking of Timed-Models by Combining Scenario Specialization and Live Component Analysis
Models of Timed Systems
Relevant Timed Schedules / Clock Valuations for Constructing Time Petri Net Reachability Graphs
Model-Based Dependability Analysis of Programmable Drug Infusion Pumps
Weak Singular Hybrid Automata
Modeling and Verification of a Fault-Tolerant Real-Time Startup Protocol Using Calendar Automata
Non-convex Invariants and Urgency Conditions on Linear Hybrid Automata
Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling
Simulator for Real-Time Abstract State Machines
Symbolic Simulation-Checking of Dense-Time Automata
Adding Symmetry Reduction to Uppaal
Infinite Runs in Weighted Timed Automata with Energy Constraints
Timed Non-interference Under Partial Observability and Bounded Memory
Delay-Dependent Partial Order Reduction Technique for Time Petri Nets
Reachability Analysis for High-Index Linear Differential Algebraic Equations
Neural Network Repair with Reachability Analysis
Time-Bounded Reachability for Initialized Hybrid Automata with Linear Differential Inclusions and Rectangular Constraints
An STL-Based Formulation of Resilience in Cyber-Physical Systems
Non-bisimulation Based Behavioral Relations for Markov Automata
Piecewise Robust Barrier Tubes for Nonlinear Hybrid Systems with Uncertainty
Control Synthesis for a Smart Card Personalization System Using Symbolic Model Checking
A Dose of Timed Logic, in Guarded Measure
A Nonarchimedian Discretization for Timed Languages
Confidence Bounds for Statistical Model Checking of Probabilistic Hybrid Systems
Duality-Based Nested Controller Synthesis from STL Specifications for Stochastic Linear Systems
Structured Modeling of Concurrent Stochastic Hybrid Systems
Unambiguity in Timed Regular Languages: Automata and Logics
Formal Modeling and Analysis of Timed Systems, 7th International Conference, FORMATS 2009, Budapest, Hungary, September 14-16, 2009. Proceedings
Back in Time Petri Nets
Simulation Based Computation of Certificates for Safety of Dynamical Systems
On Timed Automata with Input-Determined Guards
On MITL and Alternating Timed Automata over Infinite Words
Model Checking Logic WCTL with Multi Constrained Modalities on One Clock Priced Timed Automata
Data-Driven Statistical Learning of Temporal Logic Properties
Event Clock Automata: From Theory to Practice
Efficient Convex Zone Merging in Parametric Timed Automata
Perfect Timed Communication Is Hard
From Analysis to Design
The Power of Proofs: New Algorithms for Timed Automata Model Checking
Time Petri Nets with Dynamic Firing Dates: Semantics and Applications
Coping with the Parallelism of BitTorrent: Conversion of PEPA to ODEs in Dealing with State Space Explosion
Online Timed Pattern Matching Using Automata
Compositional Abstraction for Stochastic Systems
Reconciling Urgency and Variable Abstraction in a Hybrid Compositional Setting
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Verification of Parameterized Timed Systems
Model Checking for Entanglement Swapping
Formal Modeling and Analysis of Timed Systems, 4th International Conference, FORMATS 2006, Paris, France, September 25-27, 2006, Proceedings
Combining the Temporal and Epistemic Dimensions for MTL Monitoring
Reachability Analysis of a General Class of Neural Ordinary Differential Equations
Time to Learn - Learning Timed Automata from Tests
Combined Global and Local Search for the Falsification of Hybrid Systems
More or Less True DCTL for Continuous-Time MDPs
A New Verification Procedure for Partially Clairvoyant Scheduling
Reactive Synthesis for Robotic Swarms
Automatic Abstraction Refinement for Timed Automata
Diagnosis Using Unfoldings of Parametric Time Petri Nets
Formal Modeling and Analysis of Timed Systems, 6th International Conference, FORMATS 2008, Saint Malo, France, September 15-17, 2008. Proceedings
Multi-processor Schedulability Analysis of Preemptive Real-Time Tasks with Variable Execution Times
Specification and Refinement of Soft Real-Time Requirements Using Sequence Diagrams
Language Preservation Problems in Parametric Timed Automata
Mixed-Time Signal Temporal Logic
Removing All Silent Transitions from Timed Automata
Learning Specifications for Labelled Patterns
Monitoring Temporal Logic with Clock Variables
Quantitative Model Checking Revisited: Neither Decidable Nor Approximable
Quantitative Analysis of Communication Scenarios
Formal Modeling and Analysis of Timed Systems - 15th International Conference, FORMATS 2017, Berlin, Germany, September 5-7, 2017, Proceedings
Static Fault-Tolerant Real-Time Scheduling with "Pseudo-topological" Orders
Virtual Integration of Real-Time Systems Based on Resource Segregation Abstraction
Real Time Temporal Logic: Past, Present, Future
Static Detection of Zeno Runs in UPPAAL Networks Based on Synchronization Matrices and Two Data-Variable Heuristics
Synthesis of Non-Interferent Timed Systems
Timed Alternating-Time Temporal Logic
On Global Scheduling Independency in Networks of Timed Automata
Adding Invariants to Event Zone Automata
Efficient Online Timed Pattern Matching by Automata-Based Skipping
Maximum Satisfiability of Mission-Time Linear Temporal Logic
Thin and Thick Timed Regular Languages
Closing the Gap Between Discrete Abstractions and Continuous Control: Completeness via Robustness and Controllability
A Characterization of Meaningful Schedulers for Continuous-Time Markov Decision Processes
Backward Symbolic Optimal Reachability in Weighted Timed Automata
Convergence Verification: From Shared Memory to Partially Synchronous Systems
Augmented Complex Zonotopes for Computing Invariants of Affine Hybrid Systems
From Mtl to Deterministic Timed Automata
Safe Over- and Under-Approximation of Reachable Sets for Delay Differential Equations
Safe Runtime Verification of Real-Time Properties
Verification and Performance Evaluation of Timed Game Strategies
Incremental Language Inclusion Checking for Networks of Timed Automata
Matching Scenarios with Timing Constraints
Revisiting Timed Specification Theories: A Linear-Time Perspective
Proportional Lumpability
On Timed Models of Gene Networks
SMT-Based Induction Methods for Timed Systems
Optimal Reachability in Cost Time Petri Nets
Extended Directed Search for Probabilistic Timed Reachability
Checking Timed Büchi Automata Emptiness Using LU-Abstractions
Performance of Pipelined Asynchronous Systems
Formal Modeling and Analysis of Timed Systems - 13th International Conference, FORMATS 2015, Madrid, Spain, September 2-4, 2015, Proceedings
TCTL Model Checking Lower/Upper-Bound Parametric Timed Automata Without Invariants
On Optimal Timed Strategies
Dynamic Causes for the Violation of Timed Reachability Properties
Formal Modeling and Analysis of Timed Systems: First International Workshop, FORMATS 2003, Marseille, France, September 6-7, 2003. Revised Papers
A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface
Hypervolume Approximation in Timed Automata Model Checking
Guarded Autonomous Transitions Increase Conciseness and Expressiveness of Timed Automata
Usage-and Risk-Aware Falsification Testing for Cyber-Physical Systems
MITL Verification Under Timing Uncertainty
Computing Schedules for Multithreaded Real-Time Programs Using Geometry
Modeling Bitcoin Contracts by Timed Automata
Forward Reachability Analysis of Timed Petri Nets
Bounded Delay Timed Channel Coding
Modular Performance Analysis of Distributed Embedded Systems
Real-Time Synthesis is Hard!
Zone-Based Verification of Timed Automata: Extrapolations, Simulations and What Next?
Weakness Monitors for Fail-Aware Systems
DiffRNN: Differential Verification of Recurrent Neural Networks
Synchrony and Time in Fault-Tolerant Distributed Algorithms - (Invited Tutorial)
Critical Paths in the Partial Order Unfolding of a Stochastic Petri Net
The Complexity of Bounded Synthesis for Timed Control with Partial Observability
Realizability of Real-Time Logics
Bounded Model Checking of Max-Plus Linear Systems via Predicate Abstractions
On the Expressiveness of Parametric Timed Automata
On the Verification of Timed Ad Hoc Networks
Symbolic Reachability Analysis of Lazy Linear Hybrid Automata
Causal Time Calculus
Decomposing Verification of Timed I/O Automata
Craig Interpolation in the Presence of Non-linear Constraints
Reachability Analysis of Nonlinear Systems Using Hybridization and Dynamics Scaling
Precise Robustness Analysis of Time Petri Nets with Inhibitor Arcs
Lazy Approximation for Dense Real-Time Systems
On Conformance Testing for Timed Systems
Interdisciplinary Foundations for Open Cyber-Physical Systems - (Invited Talk)
Munta: A Verified Model Checker for Timed Automata
On the Verification of Timed Discrete-Event Models
Learning that Grid-Convenience Does Not Hurt Resilience in the Presence of Uncertainty
On the Complexity of Timed Pattern Matching
PARS: A Process Algebra with Resources and Schedulers
Classification of Driving Behaviors Using STL Formulas: A Comparative Study
Formal Modeling and Analysis of Timed Systems - 10th International Conference, FORMATS 2012, London, UK, September 18-20, 2012. Proceedings
Symbolic Robustness Analysis of Timed Automata
Parametric Model-Checking of Time Petri Nets with Stopwatches Using the State-Class Graph
Revisiting Decidability and Optimum Reachability for Multi-Priced Timed Automata
A Conformance Testing Relation for Symbolic Timed Automata
Model Predictive Runtime Verification for Cyber-Physical Systems with Real-Time Deadlines
HW/SW approaches to accelerate GRAPES in an FU array
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation
Template-Based Automatic Library Function Generation with Halide for Compute-Intensive Simulink Models
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR
Branch Divergence-Aware Flexible Approximating Technique on GPUs
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board
Message from the Advisory Committee Chair
A low power DRAM refresh control scheme for 3D memory cube
DXT501: An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication
Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?"
A power-efficient FPGA accelerator: Systolic array with cache-coherent interface for pair-HMM algorithm
Body bias control for renewable energy source with a high inner resistance
UniCrypt: Universal Crypto Engine with Optimized Resource Sharing for Security Applications
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management
Multi-Level Packet Processing Caches
Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications
Kernel data race detection using debug register in Linux
An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection
Encoder-based Many-Pattern Matching on FPGAs
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K
A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology
A 22 nm 10 TOPS Mixed-Precision Neural Network SoC for Image Processing with Energy-Efficient Dilated Convolution Support
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory
Trade-off analysis of fine-grained power gating methods for functional units in a CPU
Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC
IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2024, Tokyo, Japan, April 17-19, 2024
A High-Performance Hardware Design for Polynomial Multiplication in the CRYSTALS-Kyber Algorithm
IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2022, Tokyo, Japan, April 20-22, 2022
IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
Parallel design of control systems utilizing dead time for embedded multicore processors
A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling
The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller
In Search of the Performance- and Energy-Efficient CNN Accelerators
Message from the program committee chairs
Reinforcement Learning Hardware Accelerator using Cache-Based Memoization for Optimized Q-Table Selection
Dual Vector Load for Improved Pipelining in Vector Processors
A low-power sync processor with a floating-point timer and universal edge tracer for 3DTV active shutter glasses
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler
A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system
A Metadata Prefetching Mechanism for Hybrid Memory Architectures
A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training
Proposal for Non-Volatilization of eFPGA Core
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit
Blackghost: An ultra-low-power all-in-one 28nm CMOS SoC for Internet-of-Things
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control
Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors
Message from the advisory committee chair
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator
Thermal safety through Limp Home Mode for intelligent Rear View Camera Systems
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation
Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory System
A 2.41-μW/MHz, 437-PE/mm 2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation
Hope: An Efficient Accelerator With Head-Wise Overlap Processing for Sparse Attention in Vision Transformer
2013 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVI, Yokohama, Japan, April 17-19, 2013
Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-Scalar Multiplication
LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture
Language runtime support for NVM/DRAM hybrid main memory
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2025, Tokyo, Japan, April 16-18, 2025
Automatic parallelization, performance predictability and power control for mobile-applications
Statistical Access Interval Prediction for Tightly Coupled Memory Systems
Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor
Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing
Reinforcement Learning based Efficient Mapping of DNN Models onto Accelerators
A Compute-in-Memory Ascon Implementation Based on a Novel 11T SRAM Processing Macro
Subthreshold logic for low-area and energy efficient true random number generator
IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023
A Microservice Scheduler for Heterogeneous Resources on Edge-Cloud Computing Continuum
FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System
ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions
An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application
An energy-efficient dynamic memory address mapping mechanism
Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control
SPARC64TM XII: Fujitsu's latest 12 core processor for mission critical servers
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links
Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications
FPGA-based Low Power Acceleration of HARK Sound Source Localization
A media-oriented vector architectural extension with a high bandwidth cache system
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator
EMAXVR: A programmable accelerator employing near ALU utilization to DSA
Panel discussions: "Cool chips for the next decade"
Panel Discussions: "Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing"
A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices
Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays
2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020
A flexible insertion policy for dynamic cache resizing mechanisms
2016 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XIX, Yokohama, Japan, April 20-22, 2016
Establishing a standard interface between multi-manycore and software tools - SHIM
A Lightweight Transformer Model with Dynamic Sparse Mask for Neural Machine Translation
Panel discussions: Impact on society by fusion and harmony of mobile devices, servers, and networks - Their direction of evolutions and optimal roles
Keynote & invited speaker's biography [7 biographies]
Perceptron-based Cache Bypassing for Way-Adaptable Caches
Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve?
2018 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2018, Yokohama, Japan, April 18-20, 2018
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud
Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation Configuration
Key-value Store Chip Design for Low Power Consumption
Body Bias Control on a CGRA based on Convex Optimization
MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture
2011 IEEE Symposium on Low-Power and High-Speed Chips, Cool Chips XIV, Yokohama, Japan, 20-22 April, 2011
MIAOW - An open source RTL implementation of a GPGPU
An application-adaptive data allocation method for multi-channel memory
A Low-power and Real-time Neural-Rendering Dense SLAM Processor with 3-Level Hierarchical Sparsity Exploitation
XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks
Power performance analysis of ARM scalable vector extension