yusuke1997/dblp-id-title huggingface dataset:
On Solving Stack-Based Incremental Satisfiability Problems
Two-phase Logic Design by Hardware Flowcharts
Methods for analysing and improving the fault resilience of delay-insensitive codes
Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression
Clustering and Load Balancing for Buffered Clock Tree Synthesis
The CydraTM 5 computer system architecture
Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems
Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands
FAGR: An Efficient File-aware Graph Recovery Scheme for Erasure Coded Cloud Storage Systems
AOME: Autonomous Optimal Mapping Exploration Using Reinforcement Learning for NoC-based Accelerators Running Neural Networks
GRPU: An Efficient Graph-based Cross-Rack Parallel Update Scheme for Cloud Storage Systems
A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems
Reconfiguration strategies in VLSI processor arrays
Routed Inter-ALU Networks for ILP Scalability and Performance
Approaching a nanosecond: a 32 bit adder
Memory coherence in the age of multicores
Redundancy Identification and Removal Based on Implicit State Enumeration
AMULET3: a high-performance self-timed ARM microprocessor
Array Tracking Prefetcher for Indirect Accesses
On the Manisfestation of Faults to Errors in Signature Analysis
A System-Level Solution to Domino Synthesis with 2 GHz Application
Scaling Up the Sustainability of Photonic Tensor Cores With Device-Circuit-Signaling Co-Design
An integrated microspacecraft avionics architecture using 3D multichip module building blocks
BlzFS: Crash Consistent Log-structured File System Based on Byte-loggable Zone for ZNS SSD
Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs)
IBM AS/400 Processor Architecture and Design Methodology
Fault Tolerant Processor Arrays for Nonlinear Shortest Path Problem
Bounded model checking of embedded software in wireless cognitive radio systems
Template Attack Based Deobfuscation of Integrated Circuits
A Banked-Promotion TLB for High Performance and Low Power
IBM Single Chip RISC Processor (RSC)
Clustering-Based Microcode Compression
A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors
Accelerating Hybrid Quantized Neural Networks on Multi-tenant Cloud FPGA
Three-Level Decomposition with Application to PLDs
Enhancing Virtual Distillation with Circuit Cutting for Quantum Error Mitigation
Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design
Representation of control and timing behavior with applications to interface synthesis
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
Integrating Branching and Pruning for Efficient Hyperdimensional Computing
A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect
Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization
A VLSI chip for image compression using variable block size segmentation
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds
Distributed Reorder Buffer Schemes for Low Power
A power gating scheme for ground bounce reduction during mode transition
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs
Rearranging Random Issue Queue with High IPC and Short Delay
Safe Speculation for Cheri
Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor
Low-cost open-page prefetch scheduling in chip multiprocessors
Accurate prediction of physical design characteristics for random logic
Adaptive and flexible key-value stores through soft data partitioning
Engineering crossbar based emerging memory technologies
Gate planning during placement for gated clock network
Exploit asymmetric error rates of cell states to improve the performance of flash memory storage systems
BiCMOS Futurebus transceiver
Differential Testing of x86 Instruction Decoders with Instruction Operand Inferring Algorithm
NeuroFabric: Hardware and ML Model Co-Design for A Priori Sparse Neural Network Training
Embedded Protocol Processor for Fast and Efficient Packet Reception
Representing and Scheduling Looping Behavior Symbolically
An Efficient, Scalable Hardware Engine for Boolean SATisfiability
Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field
Architectural Verification of Processors Using Symbolic Instruction Graphs
Hardware-Based Probabilistic Threat Detection and Estimation for Embedded Systems
A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer
Special Session: Noise Characterization and Error Mitigation in Near-Term Quantum Computers
Low-current probabilistic writes for power-efficient STT-RAM caches
Efficient testability enhancement for combinational circuit
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis
A New Development Tool with the IEEE-ISTO
Exploiting multi-level scratchpad memories for time-predictable multicore computing
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model
Reconfigurable Array for Analog Applications
Improving Power and Data Efficiency with Threaded Memory Modules
Machine Learning for Quantum Hardware Performance Assessment
First 32-bit SPARC-based processors implemented in high-speed CMOS
Contention Tracking in GPU Last-Level Cache
Energy Considerations in Multichip-Module Based Multiprocessors
HElix: Genome Similarity Detection in the Encrypted Domain
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability
A Photonic Accelerator for Deep Learning Training
High-performance digit-serial complex-number multiplier-accumulator
Buffer size driven partitioning for HW/SW co-design
The M·CORE TM M340 Unified Cache Architecture
Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systems
Optimizing post-silicon conformance checking
An Efficient Algorithm for Reconfiguring Shared Spare RRAM
Concurrent checking in dedicated controllers
Delay Prediction for Technology-Independent Logic Equations
A dynamic accuracy-refinement approach to timing-driven technology mapping
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem
CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash
SRAM memory margin probability failure estimation using Gaussian Process regression
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design
VLSI design of densely-connected array processors
A systolic approach to multistage interconnection network design
Watts-inside: A hardware-software cooperative approach for Multicore Power Debugging
Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system
DFGC: DFG-aware NoC Control based on Time Stamp Prediction for Dataflow Architecture
A Trace Based Evaluation of Speculative Branch Decoupling
Hyperdimensional Hybrid Learning on End-Edge-Cloud Networks
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power-Down Structures for BIST
Three Dimensional Circuit Oriented Electromagnetic Modeling for VLSI Interconnects
A High Performance Sub-Pipelined Architecture for AES
Data-driven logic synthesizer for acceleration of Forward propagation in artificial neural networks
Analysis of Multiprocessor Memory Refernce Behavior
Priority-monotonic energy management for real-time systems with reliability requirements
FPGA routing architecture analysis under variations
Fast boolean logic mapped on memristor crossbar
Topology-driven cell layout migration with collinear constraints
Fidelity and Near-Optimality of Elmore-Based Routing Constructions
Multi-Level Logic Minimization through Fault Dictionary Analysis
PA-8000: A Case Study of Static and Dynamic Branch Prediction
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis
An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT
Two dimensional highly associative level-two cache design
FPGA Trust Zone: Incorporating trust and reliability into FPGA designs
HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA
Design of a custom processing unit based on Intel i486 architectures and performances trade-offs
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing
A Superassociative Tagged Cache Coherence Directory
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Global Mobility Based Scheduling
HAL III: function level hardware logic simulation
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors
Design of repairable and fully testable folded PLAs
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study
Resource allocation algorithms for guaranteed service in application-specific NoCs
The MIPS M2000 system
Modeling soft error effects considering process variations
XMAX: X-Tolerant Architecture for MAXimal Test Compression
Improving the Performance of NVM Crash Consistency under Multicore
Reducing the Energy of Speculative Instruction Schedulers
CMC: Compound Memory-Computing Architecture for Energy-Efficient CNN Accelerators
A tool set for the design of asynchronous circuits with bundled-data implementation
An Application of Genetic Algorithms and BDDs to Functional Testing
An improved algorithm for the minimization of mixed polarity Reed-Muller representations
Model Checking TileLink Cache Coherence Protocols By Murphi
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines
33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015
The design and implementation of a multi-queue buffer for VLSI communication switches
QoS management on heterogeneous architecture for parallel applications
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels
A prototype router for the massively parallel computer RWC-1
Exploring the viability of stochastic computing
An area-efficient reconfigurable binary tree architecture
Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic
Taming Sparse Giants: Deploying Mixture-of-Experts on 3D Heterogeneous Compute-in-Memory Systems
SSM-MP: more scalability in shared-memory multi-processor
Compilation of communicating processes into delay-insensitive circuits
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects
Towards Sparsification of Graph Neural Networks
Recommendation-Expert Framework for Fast and Adaptive Scheduling in Computing Power Network
Using stochastic computing to implement digital image processing algorithms
Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA
A Dynamic Virtual Memory Management System for LLMs on AI Chips
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition
Formal semantics of UDL/I and its applications to CAD/DA tools
Exploiting Online Locality and Reduction Parallelism for Sampled Dense Matrix Multiplication on GPUs
Model Checking C Programs Using F-SOFT
Input-Aware Flow-Based In-Memory Computing
A CMOS wave-pipelined image processor for real-time morphology
Code coalescing unit: a mechanism to facilitate load store data communication
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem
A global chip test implementation including built-in self-test
A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors
A fine-grained link-level fault-tolerant mechanism for networks-on-chip
Application Specific Embedded Processors for Next Generation Communication Systems
Physical Design of the "2.5D" Stacked System
Testing of VLSI regular arrays
TriMedia CPU64 Application Domain and Benchmark Suite
Attacking Trivium at the Bitstream Level
Write buffer design for cache-coherent shared-memory multiprocessors
Path Prefetching: Accelerating Index Searches for In-Memory Databases
Non-enumerative correlation-aware path selection
A GaAs vector memory system for signal processing
A morphable phase change memory architecture considering frequent zero values
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes
A polynomial time flow for implementing free-choice Petri-nets
Stafan Algorithms for MOS Circuits
Placement with Alignment and Performance Constraints Using the B*-Tree Representation
21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings
A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor
A Multi-Factor Adaptive Multi-Level Cooperative Replacement Policy in Block Storage Systems
Scale in Chip Interconnect requires Network Technology
Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis
A test generation system for path delay faults
Magnitude classes in switch-level modeling
Non-Crossing OBDDs for Mapping to Regular Circuit Structures
Efficient binary translation system with low hardware cost
SaberX4: High-Throughput Software Implementation of Saber Key Encapsulation Mechanism
Synthesis from VHDL
Static window addition: A new paradigm for the design of variable latency adders
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor
Tree structured analysis on GPU power study
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings
A Single-Multiplier Quadratic Interpolator for LNS Arithmetic
Optimizing Quantum Circuit Synthesis with Dominator Analysis
Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution
Implications of Distributed On-Chip Power Delivery on EM Side-Channel Attacks
Built-in self-test with weighted random pattern hardware
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation
Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors
3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores
Runtime Deep Model Multiplexing for Reduced Latency and Energy Consumption Inference
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits
Special Session: Noninvasive Sensor-Spoofing Attacks on Embedded and Cyber-Physical Systems
Comparing Layouts with HDL Models: A Formal Verification Technique
Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory
DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits
Thermal placement for high-performance multichip modules
Effective Dynamic Thermal Management for MPEG-4 decoding
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learning
On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs
A fine-grain dynamic sleep control scheme in MIPS R3000
Quick Scan Chain Diagnosis Using Signal Profiling
Driving Scenario Perception-Aware Computing System Design in Autonomous Vehicles
Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer
NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping
Design Methodology for the High-Performance G4 S/390
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems
Interpretable Risk-aware Access Control for Spark: Blocking Attack Purpose Behind Actions
Side-Channel Attack on STTRAM Based Cache for Cryptographic Application
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm
An Efficient VLIW DSP Architecture for Baseband Processing
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime
Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams
Convolutional Neural Networks on Dataflow Engines
SOLE: Speculative one-cycle load execution with scalability, high-performance and energy-efficiency
Classical fault analysis for MOS VLSI circuits
Statistical timing analysis based on simulation of lithographic process
An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device
LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs
CoNA: Dynamic application mapping for congestion reduction in many-core systems
A multiseed counter TPG with performance guarantee
ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory Applications
Archimedes: An Approach to Architecutre-Independent Modeling for High-Level Simulation
A trace-driven analysis of the 'wrap-around' network
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches
Improving the reliability of on-chip data caches under process variations
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
An orchestrated approach to efficiently manage resources in heterogeneous system architectures
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
A technique for selecting CMOS transistor orders
FPGA Module Minimization
Improving the interface performance of synthesized structural FAME simulators through scheduling
Timing-Driven Global Placement with Entropy-Mobility Guided Pin-to-Pin Weighting
Tutorial: Software-defined radio technology
Proof and synthesis
AC++ Based Environment for Analog Circuit Simulation
A Mechanism for Efficient Context Switching
ResCheck: Resilient Checkpointing for Energy Harvesting Systems
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
A New Weight Set Generation Algorithm for Weighted Random Pattern Generation
A Simulator for General Purpose Optical Arrays
Design of an Embedded Video Compression System - A Quantitative Approach
Parallel-Array Implementations of a Non-Restoring Square Root Algorithm
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers
Tera-Hertz study of normal and superconducting transmission lines
Leveraging speculative architectures for run-time program validation
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm
RWORT: A Read and Write Optimized Radix Tree for Persistent Memory
Design Tradeoffs and Experience with Motorola PowerPC? Migration Tool
Issues in Multi-Level Cache Designs
Precise exception handling for a self-timed processor
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights
DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications
A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap
Frequency and voltage planning for multi-core processors under thermal constraints
Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation
A co-processor approach for accelerating data-structure intensive algorithms
Reduced Hamming Count and Its Aliasing Probability
BiCMOS, a technology for high-speed/high-density ICs
LDPC-Based Adaptive Multi-Error Correction for 3D Memories
Empirical evaluation of randomly-wire multistage networks
NTTFusion: Efficient Number Theoretic Transform Acceleration on GPUs
Desktop Wars - The PC Versus the Workstation
Revitalizing Buffered I/O: Optimizing Page Reclaim and I/O Throttling
Implementing a STARI chip
DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation
IBM RISC chip design methodology
Fast Cache Access with Full-Map Block Directory
Architectural impact of secure socket layer on Internet servers
Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks
A 32-bit microprocessor with high performance bit-map manipulation instructions
Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design
Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time Multicores
An approach to 150 K gate low power ECL cell based integrated circuits
68040 integer module
A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing
MILES: a mixed level simulator for analog/digital design
Boolean Decomposition Based on Cyclic Chains
FreshCache: Statically and dynamically exploiting dataless ways
Super computer technology at Convex
FPGA-based Internet Protocol Version 6 router
CyHOP: A generic framework for real-time power-performance optimization in networked wearable motion sensors
Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance
Efficient architectures for elliptic curve cryptography processors for RFID
A Timing Side-Channel Attack on a Mobile GPU
SLAM: a smart analog module layout generator for mixed analog-digital VLSI design
Voltage Scaling for Energy Minimization with QoS Constraints
Yield Optimization by Design Centering and Worst-Case Distance Analysis
Wireless Network-on-Chip analysis of propagation technique for on-chip communication
Simple tree-construction heuristics for the fanout problem
Stochastic neuromorphic learning machines for weakly labeled data
VGTA: Variation Aware Gate Timing Analysis
Clear and Present Tensions in Microprocessor Design
Verifying the performance of the PCI local bus using symbolic techniques
Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72
Automatic layout and optimization of static CMOS cells
BioChipWork: Reverse Engineering of Microfluidic Biochips
Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage
Distributed automatic test pattern generation with a parallel FAN algorithm
Design methodology for sample preparation on digital microfluidic biochips
MDP Design Tools and Methods
A higher level hardware design verification
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations
Dynamic test scheduling for analog circuits for improved test quality
Fine-Grained Parallel Routing for FPGAs with Selective Expansion
ALPHA: A Scalable Lock-Free Partitioned Hash Index for Persistent Memory on NUMA Architectures
Transient Analysis of VLSI Interconnects with Arbitrary Initial Distributions and Nonlinear Terminations
A Hybrid Spin-CMOS Flash ADC based on Spin Hall Effect and Spin Transfer Torque
VLSI implementation of GSC architecture with a new ripple carry adder
Feasibility study of dynamic Trusted Platform Module
Design for testability of integrated operational amplifiers using oscillation-test strategy
Optimized bit level architectures for IIR filtering