yusuke1997/dblp-id-title huggingface dataset:
Tensor-Based Hybrid Precoding Processor for 8 × 8 × 8 mmWave 3D-MIMO Systems
Online multiclass passive-aggressive learning on a fixed budget
Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering
Flexible high-accuracy wide-range gas sensor interface for portable environmental nosing purpose
Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques
Low-cost trimmable manufacturing methods for printable electronics
A formal approach to slack-driven high-level synthesis
Wavelet compression of 3D medical images using conditional arithmetic coding
A 400Mbps CMOS spatially-modulated photoreceiver for optical storage
Architectures for IIR digital filters using stochastic computing
On-chip ESD protection for RF I/Os: devices, circuits and models
File Classification Based on Spiking Neural Networks
A Simplicial PWL Integrated Circuit Realization
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications
A Wide Input Power Line Energy Harvesting Circuit for Wireless Sensor Nodes
A Hybrid Memristor/CMOS SNN for Implementing One-Shot Winner-Takes-All Training
The low-power and low-area PWM by light intensity for photoflash in 0.35-µm CMOS
A Study of Three-Phase DC-DC Boost Converters
A temperature independent trimmable current source
Big data requirements in current and next fusion research experiments
Logic Implementation Based on Double Memristors
Lossless multi-channel EEG compression
Low-complexity Adaptive Channel Estimation for OFDM System in Fast-fading Channel
Acoustic Source Localization using LS-SVMs without Calibration of Microphone Arrays
A 12GS/s 6-bit DAC with 4-2 Segmentation in 40nm CMOS
A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors
Congruence Synchronous Mirror Delay
A 200GΩ-ZIN, <0.2%-THD CT-△Σ-Based ADC-Direct Artifact-Tolerant Neural Recording Circuit
Reinforcement-Learning-Based Successive Approximation Algorithm
Semi-formal verification of VHDL-AMS descriptions
Live Demonstration: Smart Watchdog Mechanism for Real-time Fault Detection in RISC-V
A low-power low-voltage MOSFET-only voltage reference
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells
A new parameterization method for all stabilizing controllers of nD systems without coprime factorizability
A 2+1 multi-bit incremental architecture using Smart-DEM algorithm
Fast adaptive inter-prediction mode decision method for H.264 based on spatial correlation
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis
A CMOS field programmable analog array and its application in continuous-time OTA-C filter design
Live Demonstration: End-to-End Real-Time ROI-based Encryption in HEVC Videos
Disparity vector based advanced inter-view prediction in 3D-HEVC
Tightly-coupled MPEG-4 video encoder framework on asymmetric dual-core platforms
Analog Implementation of SNR based Gain Adaptation for Denoising
A dual-core programmable decoder for LDPC convolutional codes
Time Domain Analysis of Secondary Stage With Series Resonance Driving Rectifier Load
On a novel Hybrid LQ-MCS control strategy and its application to a DC motor
Low Peak Power ATPG for n-Detection Test
Event-driven body motion analysis for real-time gesture recognition
Optimal chaos shift keying communications with correlation decoding
Gigahertz-range MCML multiplier architectures
A 10-mW 435-MHz differential CMOS LNA for low-IF receivers in space applications
Second order statistics based blind channel equalization with correlated sources
Receiver Driven Overlap FEC for Scalable Video Coding Extension of the H.264/AVC
Allpass structures for multiplierless realization of recursive digital filters
Optimization-based calibration of a static timing analyzer to path delay measurements
A 9.2b 47fJ/conversion-step asynchronous SAR ADC with input range prediction DAC switching
State trajectory prediction control for boost converters
DNNMapper: An Elastic Framework for Mapping DNNs to Multi-die FPGAs
Time Step Impact on Performance and Accuracy of Izhikevich Neuron: Software Simulation and Hardware Implementation
A 95 dB dynamic range automatic gain control circuits and systems for Multi-standard Digital TV tuner
On two-directional orthogonal ray graphs
Generalized buffering of PTL logic stages using Boolean division
Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator
On the Resetability of Synchronous Sequential Circuits
An Online SVM Based VVC Intra Fast Partition Algorithm With Pre-Scene-cut Detection
A low complexity speech coder for binaural communication in hearing aids
Data adaptive analysis of ECG signals for cardiovascular disease diagnosis
Coherer is the elusive memristor
Musical instrument classification using non-negative matrix factorization algorithms
Portable photoacoustic system for noninvasive blood temperature measurement
Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits
Seeking low-power synchronous/asynchronous systems: A FIR implementation case study
Pulse mode multilayer neural network based on floating point number representation
A transformation for computational latency reduction in turbo-MAP decoding
A Wearable EEG Acquisition Device With Flexible Silver Ink Screen Printed Dry Sensors
DeepRS: Deep-Learning Based Network-Adaptive FEC for Real-Time Video Communications
Optimum scaling of stages in a frequency divider chain for best jitter FoM
A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range
Coefficient extraction for MPM using LSE, ORLS and SLS applied to RF-PA modeling
Temporal processing with volatile memristors
Simulated Isobaric Annealing
Dynamic nets-to-TSVs assignment in 3D floorplanning
Active Charge Balancer with 6.6 to 40 V Quad-Rail Power Supply Compliance for Neural Stimulators
Implementation of a CNN-based perceptual framework on a roving robot
A High Performance FPGA with Hierarchical Interconnection Structure
An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement
A low-power ΣΔ modulator with low capacitor spread for multi-standard receiver applications
Phase-jitter dynamics in second-order DPLLs with irrational and integer input frequencies
Frame-skipping transcoding with motion change consideration
Repeater insertion in RLC lines for minimum propagation delay
A floating-gate DAC array
Performance and routability improvements for routability-driven FPGA routers
A Comprehensive Method to Taxonomize Mechanical Energy Harvesting Technologies
A digital tuning algorithm for on-chip resistors
A two-time scale framework for stability analysis of electrical power system
An IIP2 calibration technique for direct conversion receivers
Universal Portable SDE Platform for Teaching the Theory and Practice of ICT Systems
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis
A decision feedback equalizer utilizing higher-order correlation
A 128×128 Current-Mode Ultra-High Frame Rate ISFET Array for Ion Imaging
RDLNET: Residual Dense Block based Lightweight Network for Video Super-Resolution
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band
A Real-Time Machine Learning Module for Motion Artifact Detection in fNIRS
Group Event Detection for Video Surveillance
On the time-frequency content of Weyl-Heisenberg frames generated from odd and even functions [signal representation applications]
On two approaches to analyzing consensus in complex networks
Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters
Live demonstration: Inductive power and telemetry for micro-implant
Fully Integrated Dynamic Power Cell Allocation SIDO SC DC-DC Converter with a 263.8mV/ns DVS Speed and a 19.8ns Transient Recovery Time
Towards the development of next-generation remote healthcare system: Some practical considerations
A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation
A new adaptive harmonic extraction scheme for single-phase active power filters
Analysis and test of electromigration failures in FPGAs
Fault and simple power attack resistant RSA using Montgomery modular multiplication
Voltage Controlled Pulse Skipping Modulation: Extension towards the Ultra Light Load
CMOS integrated MEMS resonator for RF applications
Efficient Lossless Compression with Distribution Quantized Finite-State Autoregressive Model
A switched-capacitor interface circuit for integrated sensor applications
Intra mode power saving methodology for CGRA-based reconfigurable processor architectures
A novel high rate transmission scheme for space time coding with low decoding complexity
An energy-based attack flow for temporal misalignment coutermeasures on cryptosystems
Performance analysis of low complexity solutions for UWB low data rate impulse radio
Efficient FPGA implementation of a wireless communication system using Bluetooth connectivity
Source-follower-based bi-quad cell for continuous-time zero-pole type filters
Improving Digital MOS Macromodel Accuracy
A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal
A charge pump-based direct frequency modulator
Symbol-Based Algorithms for Decoding Binary LDPC Codes with Higher-Order Modulations
Cross Technology Prediction for SRAM Stability Analysis
A 15.9 mW 96.5 fps Memory-Efficient 3D Reconstruction Processor with Dilation-based TSDF Fusion and Block-Projection Cache System
Efficient Variable Rate Vector Quantization Using Quadtree Segmentation
Hybrid Event-Frame Neural Spike Detector for Neuromorphic Implantable BMI
Comparative investigations of substrate noise caused by voltage-mode and current-mode gates
Reverse engineering resistant ROM design using transformable via-programming structure
Investigation of single-event upsets in dynamic logic based flip-flops
Automatic generation of moment invariants and the use of higher order moments for character recognition
Redundant linear coding for accelerating counting and comparison operations
An efficient routing algorithm for irregular mesh NoCs
Whitespace insertion for through-silicon via planning on 3-D SoCs
New method for tailoring ripple and spectral properties of chaotic DC-DC converters
Hardware Trojan Design on Neural Networks
Multispectral and Multimodal Image Registration Based on a Dynamic Fusion Index
A partitioned linear minimum mean square estimator for error concealment [video decoder error concealment]
Performance evaluation of multithreaded architectures for media processing applications
A 2-GHz CMOS variable gain amplifier optimized for low noise
Shared memory switching + virtual output queuing: A robust and scalable switch
Subband Coding of Color Images Using Multiplierless Encoders and Decoders
Fixed-Throughput GRAND with FIFO Scheduling
Gate Level Optimisation of Primitive Operator Digital Filters using a Carry Save Decomposition
Concurrent optimization of process dependent variations in different circuit performance measures
Multimodal Fusion for Dementia Detection using Voice and Facial Features
Parallel FFT computation with a CDMA-based network-on-chip
An Efficient Hardware Accelerator for Sparse Transformer Neural Networks
SoC design integration by using automatic interconnection rectification
A 2.4 GHz low-power low-phase-noise CMOS VCO using spiral inductors and junction varactors
A 128 channel 290 GMACs/W machine learning based co-processor for intention decoding in brain machine interfaces
Carrier-Auxiliary IF Feedback Crystal-Less LO Generator and Approximate Low-If Receiver Architecture for Energy-Efficient Radio
A Fast-locking and Wide-range Reversible SAR DLL
Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels
A 45V 10-b electrode monitoring analog-to-digital converter
A Novel Approach to Noise Shaping in Digital Pixels for Infrared Imagers using Over-Integration
A Dempster-Shafer theory of evidence approach for combining trained neural networks
Hybrid-DPLL-based constant-envelope modulator for Internet-of-Things chipsets
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay
Power saving technique for MOS differential amplifiers
A CMOS charge pump for low voltage operation
Electronically Controllable Audio Equalizers Based on Bilinear Immittances Utilizing CMOS Voltage Differencing Current Conveyor
A 83dB SNDR low power readout ASIC for piezoresistive nanogauge based gyroscopes
An analog VLSI model of muscle sarcomeres
A Low Complexity Radioisotope Identification System using an Integrated Multichannel Analyzer and Embedded Neural Network
Large-signal stability-oriented design of boost-type regulators in discontinuous conduction mode
A novel optimization method for CT sigma-delta-modulators using a switched system model
State-dependent changeable scan architecture against scan-based side channel attacks
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model
Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees
High throughput and resource efficient AES encryption/decryption for SANs
Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications
Multiple voltage-based scheduling methodology for low power in the high level synthesis
Effects of numerical noise floor on the accuracy of time domain noise analysis in circuit simulators
Fast analytical approach to finding steady-state waveforms for power electronics circuits using orthogonal polynomial basis functions
Low Voltage Current Mirrors for Built-in Current Sensors
Stability analysis of the second-order lossless digital integrator allpass filter
Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations
Live demo of a vibration-powered Bluetooth sensor with running PFC power conditioning
High-speed pipelined A/D converter using time-shifted CDS technique
Noise analysis of correlated double sampling SC-integrators
A New Learning Algorithm for RBF Neural Networks with Applications to Nonlinear System Identification
An effective algorithm for delay constrained least cost unicast routing
A Dual-Band Vector-Sum Phase Shifter for 28-GHz and 60-GHz Phased Arrays in 65-nm CMOS
A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12µm standard CMOS
Analog Synthesis from Behavioural Descriptions
Linear echo cancellation using optimized recursive prefiltering
Analysis of a MEMS-based ring oscillator
GPU-Acceleration of Affine Prediction in the Versatile Video Coding
Fast selective-intra mode search algorithm based on macro-block tracking for inter-frames in the H.264/AVC video standard
Fault tolerant bit parallel finite field multipliers using LDPC codes
A programmable continuous-time analog Fourier processor based on floating-gate devices
On some recent advances in synchronization and control of Complex Networks
Detailed frequency analysis of power supply rejection in Brokaw bandgap
On the three-dimensional channel routing
Wideband Power-Line Decoupling Technique for Millimeter-Wave CMOS Integrated Circuits
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs
Programming interface requirements for an AMS simulator
A Novel System and Statistical Analysis for Predicting Defibrillation Timing During Ventricular Fibrillation
A 40-nm 640-µm 2 45-dB opampless all-digital second-order MASH ΔΣ ADC
pyNeurode: a real-time neural signal processing framework
Electrostatically Adaptable Current Mirror based on Germanium Field-Effect Transistors
A model for predicting sampler RF bandwidth and conversion loss
Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons
SEE Sensitivity of a 16GHz LC-Tank VCO in a 22nm FinFET Technology
Ladder realizations of fast subband/VQ coders with diamond support for color images
Area-efficient scaling-free DFT/FFT design using stochastic computing
A new architecture for computationally adaptive full-search block-matching motion estimation
Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits
A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA
Class DE Inverter with Asymmetric Shunt Capacitors
Sensitivity analysis of nonlinear circuits using Volterra series
Enhanced Programmability of Reconfigurable Intelligent Surfaces for Smart Cities using Application-Specific Integrated Circuits
Distributed meta-heuristic method for network optimization problems in information network
Effective tunneling capacitance: a new metric to quantify transient gate leakage current
Food Traceability in Fruit and Vegetables Supply Chain
A single SAR ADC converting multi-channel sparse signals
A pipelined dual-channel switched capacitor programmable gain amplifier
An on-line unsupervised learning machine for adaptive feature extraction
A Low-Power Spike Detector Using In-Memory Computing for Event-based Neural Frontend
On the secrecy of compressive cryptosystems under finite-precision representation of sensing matrices
Impulsive synchronization on complex networks of nonlinear dynamical systems
High-throughput packet aggregator for the back-end DAQ of CERN CMS HGCAL detector
Energy Scaling with Control Distance in Complex Networks
An Efficient Oscillator Design Based on OTA Nonlinearity
A 0.4 V 180 nm CMOS Sub-μW Ultra-Compact and Low-Effort Design PWM-Based ADC
Electrical connectivity analysis of a MEMS micropackage
FPGA implementation of a spiking neural network for pattern matching
A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic
Closed-Form Solution of Granular Quantization Error for a Class of Sigma-Delta Modulators
Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio
Network science meets circuit theory: Kirchhoff index of a graph and the power of node-to-datum resistance matrix
Exploiting the non-linear current-voltage characteristics for resistive memory readout
A methodology for MOS transistor mismatch parameter extraction and mismatch simulation
Towards an H.264/AVC full encoder on chip: an efficient real-time VBSME ASIC chip
Implementation of hybrid version management in hardware transactional memory
A 3.3 µW dual-modulus frequency divider with 189% locking range for MICS band applications
Cost-Effective Reconfigurable MCM with Common-Value Elimination and Alignment
A High Dynamic Range Feedback Compensation Front-End for Unlimited Sampling ASDM ADC
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-µm CMOS [convereter read converter]
Design and analysis of class DE amplifier with any output Q, any duty ratio and switch on resistance
3D Oncological PET volume analysis using CNN and LVQNN
A 120μW 240×110@25fps vision chip with ROI detection SIMD processing unit
Analysis of in-band Spurious Tones of VCO-based Analog Filters and Mitigation Techniques
Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation
Walsh-domain Neural Network for Power Amplifier Behavioral Modelling and Digital Predistortion
A wide dynamic range low power 2× time amplifier using current subtraction scheme
Dynamic voltage and frequency scaling for neuromorphic many-core systems
Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs
Scalable behavior modeling for SCR based ESD protection structures for circuit simulation
An on-chip combinational decompressor for reducing test data volume
Simple switched-capacitor-boost converter with large DC gain and low voltage stress on switches
A low-power 3-phase half rail pass-gate differential logic
Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter
Design of electro-optical demodulating pixel in CMOS technology
Wireless Power Transfer H-Bridge design with serial resonance and varying supply voltage
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms
Part 1 - Electronics in Transition, The Tools and Technologies for 2000 AD
Finite Precision Analysis of the Fast QRD-RLS Lattice Algorithm
A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS
Robust encoding of 3D mesh using data partitioning
Statistical Constrained Optimization of Analog CMOS Circuits using Empirical Performance Models
Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs
A Practical Second-Order Delta-Digma Frequency-to-Digital Converter
Very high speed Viterbi decoder with circularly connected analog CNN cell array
The new CMOS 2 V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers
Interleaving Active Feedback in Inverter-Based Optical Receivers for Bandwidth Extension and Linearity Improvement
A simple high-speed low current comparator
3D scheduling based on code space exploration for dynamically reconfigurable systems
A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter
A compact adaptive slope compensation circuit for Current-Mode DC-DC converter
Image sensor with focal plane change event driven video compression
Full chip ESD design rule checking
Hardware implementation of the SUMIS detector using high-level synthesis
A high-performance, low-voltage, body-driven CMOS current mirror
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency
Muliplierless Realization Structure of Adaptive Filters by Nonuniform Quantization of Input Signal
Design of fractional delay FIR filter using discrete Fourier transform interpolation method
Optimized multi-path routing using dual decomposition for wireless video streaming
Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V
Forward body biased keeper for enhanced noise immunity in domino logic circuits
Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node
Selective Multi-pulse Pulse Position Modulation for Lighting Constrained Visible Light Communications
Inverter-based switched current circuit for very low-voltage and low-power applications
A Utilization Aware Robust Channel Access Mechanism for Wireless NoCs
New method for weighted low-rank approximation of complex-valued matrices and its application for the design of 2-D digital filters
Closed-form design of maximally flat FIR fractional delay filters
Bidirectional conversion to minimum signed-digit representation
Low-cost and ultra-sensitive poly-Si nanowire biosensor for Hepatitis B Virus (HBV) DNA detection
An implementation of numerical inversion of Laplace transforms on FPGA
Logic Reduction in Timed Asynchronous Circuits
A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity
A CMOS high-speed multistage preamplifier for comparator design
A Fast-switching Current-pulse Driver for LED Backlight
A Region Based Motion Compensated Video Codec for Very Low Bitrate Applications
MIRROR: an interactive content based image retrieval system
Comparison of digital linearization methods for embedded sensor interfaces
Statistical detector for wavelet-based image watermarking using modified GH PDF
Iterative Waveform Relaxation Bounds for General RC Circuits
Analysis and design of MCML gates with hysteresis
Use of granular method to design centering
A Probability Method to Estimate the State of a Digital Resonate-And-Fire Neuron without Running a Simulation
Realization of the NLMS based transversal adaptive filter using block floating point arithmetic
Reconstructing the Model of a Nonlinear MEMS Structure by the Example of a Piezoelectric Resonant Energy Harvester
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity
Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations
A spur cancellation technique for MDLL-based frequency synthesizers