yusuke1997/dblp-id-title huggingface dataset:
A low-jitter self-biased phase-locked loop for SerDes
A synchronous boost converter with high speed and high accuracy peak current control unit
High Detection Rate BCH Code with CRC Code for Memory Application
Mixture of Deterministic and Stochastic Quantization Schemes for Lightweight CNN
Performance Comparison of Soiling Detection Using Anomaly Detection Methodology
A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 Signaling
A host-accelerator communication architecture design for efficient binary acceleration
Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter
An Efficient FPGA Implementation of Izhikevich Neuron Model
Electromagnetic Shielding Effectiveness of Sputtered Non-woven Noise Suppression Sheet with Varied Air Gap
MTCMOS-based Ternary to Binary Converter
Fast Automatic Circuit Optimization Using Deep Learning
A Compact Design of SPAD Detector with Quenching Circuit for Reduced Dark Count Rate
A Top-Down Approach for Low Noise Amplifier Design using Verilog-A
Embedded Solutions for IoT Based Automated Drug Infusion Device
Wafer-level Packaging Platform for MEMS Sensor Applications
A CMOS Rectifier with 72.3% RF-to-DC Conversion Efficiency Employing Tunable Impedance Matching Network for Ambient RF Energy Harvesting
Integrated circuits design using carbon nanotube field effect transistor
BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning Acceleration
Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM Architecture
HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier
CMOS low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applications
Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology
A Robust DT ∆Σ Modulator for High-Resolution Sensor Against Temperature Variations
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications
A Design and Implementation of MIPI A-PHY RTS Layer
The hardware implementation of QARMA-64 with RoCC on FPGA for memory encryption
A 94.3 % Peak Power Efficiency Time-Based Buck Converter Using Pulse-Phase-Shift Modes with An Intrinsic Window for Transient Enhancement
Two-step local dimming for image quality preservation in LCD displays
Design of a Multilingual Translation System with Personalized Voice Characteristics
Time-domain temperature sensor based on interlaced hysteresis delay cells
Introduce reward-based intelligent vehicles communication using blockchain
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology
A design of real time detection IP with color detection for surveillance
Design of hand skeleton extraction accelerator for a real-time hand gesture recognition
A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit
Peak Current Control Boost Converter with Time-Multiplex
A Study of Changes in Prediction Performance Influenced by Attractor State in Oscillator Reservoir Computing
Design of a Low-Power Complex Baseband Filter with Tunable Gain and Bandwidth in 65nm CMOS
A dynamic fixed-point representation for neuromorphic computing systems
Temperature Independent Subthreshold Circuits Design
Image interpolation based on Hessian analysis
TSV fault-tolerant mechanisms with application to 3D clock networks
Wide center-tape balun for 60 GHz silicon RF ICs
Detecting LED Chip Surface Defects with Modified Faster R-CNN
D-band Low Noise Amplifier with Improved Linearity in 90-nm BiCMOS9HP Process
A study of low jitter phase locked loop for SPDIF
ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing
Towards Automatic Property Generation for SoC Security Verification
Secure Scan Design through Pseudo Fault Injection
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors
Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications
A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links
A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method
Implementation of RF frequency synthesizer for smart utility network system
Body-coupled wireless power transfer and energy harvesting for wearables
Designs of Dual-band Metamaterials for Near-field Wireless Power Transmission
Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis
Synchronization Phenomena of Coupled Oscillators with Node and Edge Weights in Two-Dimensional Complex Networks
A high-efficiency active rectifier by using zero current sensing and deglitch circuit for inductive coupling receiver
Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure
Dual Path Binary Neural Network
A 60 GHz CMOS OOK Receiver with 7.7 GHz Bandwidth for Wireless Proximity Communication
A Multi-precision Multiply-Accumulation Array
A decouple structured gyroscope with integrated readout circuit on standard 0.18pm 1P6M CMOS technology
Flexible and efficient FEC decoders supporting multiple transmission standards
Adaptive Battery State-of-Charge Estimation Method for Electric Vehicle Battery Management System
Low phase noise pulse rotary wave voltage controlled oscillator
Linearity Characterization of Hybrid Driving Scheme for Spatial Light Modulator System
Design of AdaBoost classifier circuit using Haar-like features for automobile applications
A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation
Current equalization scheme for parallel low-dropout regulators
A 1.6mW 320×240 pixel vision sensor for event detection
A fully integrable RF energy harvester with dynamic efficiency tuning
Automatic image deviation detection for AVM auto-calibration
An efficient design of split-radix FFT pruning for OFDM based Cognitive Radio system
Trend of Emerging Non-Volatile Memory for AI Processor
An efficient convolutional neural networks design with heterogeneous SRAM cell sizing
Triple module redundancy scheme on an optically reconfigure gate array
1.6-ppm/°C Reference Voltage Generator with PSRR of -93dB based on Threshold Voltage Difference of LVT and SVT Devices
A Current Feedback Instrumentation Amplifier with Current Reuse and Power Line Interference Mitigation Technique for ECG Recording
Reconfigurable Stochastic Computing Architecture for Computationally Intensive Applications
A COT-based Highly Efficient Hybrid 3-Level Buck Converter for Next-Generation Memory Module Designs
On-chip CMOS Corner Detector Design for Panel Drivers
21st International SoC Design Conference, ISOCC 2024, Sapporo, Japan, August 19-22, 2024
Two Stage CMOS Bio-medical Amplifier Based on a highly Linear TΩ Pseudo-Resistor
Synchoronization Penomena of Coupled Oscillators in Weighted Three-Dimensional Complex Networks
FPGA-based Optical Character Recognition for Handwritten Mathematical Expressions
A survey and perspective on electronic design automation tools for ensuring SoC security
A Hybrid Precision Network with Efficient Processing Elements for 3D Hand Pose Estimation
Novel In-memory Computing Circuit using Muller C-element
Instruction set extension and hardware acceleration for SVM application toward a vector processor
A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA
Analog front-end for EMG acquisition system
SCC: Efficient Error Correction Codes for MLC PCM
Artificial synaptic behavior and its improvement of RRAM device with stacked solution-processed MXene layers
FB-SKP: Front-Back Structured Kernel Pruning via Group Convolution without Increasing Memory
A Baseband Analog Spectrum Sensing Unit Employing Super Source Follower-Based Channel Selection Filters
SoC Design for Mobile Real-time Badminton Stroke Classification Design
19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022
6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer
Enhancing Efficiency in Computational Intensive Domains via Redundant Residue Number Systems
Circuit design for carbon nanotube field effect transistors
18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021
Design Optimization for Decimation Filter for High Performance Sigma-Delta ADC
Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter
Design on Smart Grid and Irrigation Management: based on Information Sharing
A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion
FPGA implementation of sequence-to-sequence predicting spiking neural networks
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology
A 400MHz 3-10Mbps transceiver IC with ∼0.3 nJ/bit TX/RX energy efficiency for body area applications
Design of a Low-Cost Approximate Adder with a Zero Truncation
Efficient Power Control Using Variable Resolution Algorithm for LiDAR Sensor-based Autonomous Vehicle
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization
Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65nm CMOS Technology
Rank Reversal Avoiding Algorithm for Modern Cooperative Spectrum Sensing
Data Randomization for Multi-Variant Execution Environment
An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery
A background calibration method for DAC mismatch correction in multibit sigma-delta modulators
A study on river water level monitoring method in a debris barrier
Capless Low-Dropout Regulator with a Dual Feedback Loop and Voltage Dampers
Fast and Accurate Curvilinear OPC with ML-Guided Curve Correction
Variable bit truncation technique for approximate stochastic computing (ASC)
11-Bit 1.8uW 40KS/s segmented SAR ADC for sensor applications
A Design of SIDITO Buck-Boost Converter with Real Time Maximum Power Point Tracking for RF Energy Harvesting System
A fully-digital phase modulator with phase calibration loop for high data-rate systems
Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems
Assuring system reliability in wireless sensor networks via verification and validation
Lifetime Improvement Method using Threshold-based Partial Data Compression in NoC
Tunable pre-emphasis architecture for downstream data in long-haul PON systems
Design of 3D Inductors for IoT Security
Low Power - High Speed Magnitude Comparator Circuit Using 12 CNFETs
K-means Clustering-specific Lightweight RISC-V processor
Automatic Speech Recognition Techniques for Transcription of Thai Traditional Medicine Texts
An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism
Compact thermal models: Assessment and pitfalls
A hardware-efficient wireless functional electrical stimulation system based on ergodic cellular automaton dynamics
An optimum RF link for implantable devices with rectification of transmission errors
SiGe BiCMOS power amplifiers for 60GHz ISM band applications
A novel charge sharing charge pump for energy harvesting application
An Energy Efficient Finite State Machine Algorithm for Real-Time Asset Monitoring and Tracking System
A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-Kelvin
A WDR method with low noise in digital circuit
Percentile Clipping based Low Bit-Precision Quantization for Depth Estimation Network
Enhancing Embedded Super-Resolution Accelerators: Techniques for Hardware Performance Improvement
Improvements in parallel SIMD implementation of single image defogging
Frequency Discriminator Using a Simple AD Converter for Interface Systems
Chaotic True Random Number Generator for Secure Communication Applications
A Radiation Hardened SRAM with Self-refresh and Compact Error Correction
Design of a Low-Power BLE5-Based Wearable Device for Tracking Movements of Football Players
LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator
A double-quadrature down-conversion mixer in 0.18 μm SiGe BiCMOS process
A dual-retention time architecture towards secure and high performance STT-RAM main memory subsystem
Uncompensated Robust Rail-to-Rail New Amplifier Structure Compatible with Drivers of LCD Panels
A web service for automated IP/SoC verification using computers on network
Development of burst error effect reduction algorithm for CAN using interleaver method
ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator
A study of the referenceless CDR based on PLL
Leakage current modeling for GPGPU systems
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS
A Smith-Waterman Hardware Accelerator Design using Sliding Window for Genomic Sequence Alignment
A Low-Power Counter-based Digital CDR
Noise reduction scheme of temporal and spatial filter for 3D video real-time processing
Characterizing convolutional neural network workloads on a detailed GPU simulator
Designing a Class E Power Amplifier through Modeling in Verilog-A
Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell
A DLL-Based Three-Step Time-to-Digital Converter for Time-of-Flight Applications
Implementation of RF narrow band frequency synthesizer for LoRaWAN system
An Improved Early Termination Methodology Using Convolutional Neural Network
An Area-Efficient Column Driver with Fully Nonlinear Gamma Scale for Mobile AMOLEDs
Millions to thousands issues through knowledge based SoC CDC verification
Transition-delay Test Methodology for Designs with Self-gating
A High-Speed HBM Receiver Design for High-Performance Computing Systems
Preliminary Study on Reducing Memory Overhead in Accelerating Quantum Computer Simulations Using PIM Technology
On-chip Interconnect Optimization and Validation using Virtual Platform
A Hybrid Execution Approach to Improve the Performance of Dataflow Applications
A High Efficient RF-DC Converter for RF Energy Harvesting Applications
Design of an Area-Efficient and Error-Reduced CMOS Approximate Adder
A 38-GHz Stacked-FET Linear Power Amplifier with Novel Phase Linearizer Circuit in 45-nm CMOS SOI
Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB
Implementation of Aurora Interface using SFP+ Transceiver
STT-MRAM Read and Write Circuit for High Reliability and Power Efficiency
Distance Searching-based Hyperparameter Optimization for Restricted Coulomb Energy-based Neural Network
A study on wide-band frequency synthesizer for advanced wireless communication
Alleviating the Impact of Fingerprint Operations on NAND Flash Memory Storage Performance
A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-l Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural Networks
A 2-GHz Reconfigurable Transmitter Using A Class-D PA and A Multi-Tapped Transformer
Calibrating the Dark Count Rate of Single Photon Avalanche Diodes Using Linear Regression
An inductive-coupling link for 3-D Network-on-Chips
Accelerating Transformers with Fourier-Based Attention for Efficient On-Device Inference
Device Parameter Extraction Method for Training Performance Predicting Models
A low-power low-noise ultrasonic receiver front-end IC for medical imaging systems
Time Series Analysis with Three Types of Noise-Mixing Effects by Neural Network
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification
Logic and Reduction Operation based Hardware Trojans in Digital Design
Ka-band RF Front-End with 5dB NF and 16dB conversion gain in 45nm CMOS technology
Sequential Compression Using Efficient LUT Correlation for Display Defect Compensation
Design of logic-compatible embedded DRAM using gain memory cell
Design and Dataflow for Multibit SRAM-Based MAC Operations
A 28GHz-band integrated GaAs Power Amplifier for 5G Mobile Communications
Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits
NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells
Low-dropout regulator with low output peak voltage with soft-start added to bandgap reference output
Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine
Accelerating SoC Security Verification and Vulnerability Detection Through Symbolic Execution
A Time-Domain Computing-In-Memory Micro using Ring Oscillator
Development of Propeller LED Transmitter for High-Speed Image Sensor Communication
INC: In channel Crossing ECC for LPDDR Compression Attached Memory Module
Low Power Gate Diffusion Input Full Adder using Floating Body
Clipped Quantization Aware Training for Hardware Friendly Implementation of Image Classification Networks
Terahertz image sensors using CMOS Schottky barrier diodes
Wideband LC VCO with 39.3 % Frequency Tuning Range for Dielectric Spectroscopy System
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS
Hybrid Test Access Mechanism for Multiple Identical Cores
Energy-based iterative cost aggregation in depth estimation with a stereo camera
High-speed Serial Interface using PWAM Signaling Scheme
An FPGA Implementation of CNN-based Compression Artifact Reduction
Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative Values
Effective Data-Width Aware ECC Scheme for HBM
Real time High Accuracy Phase Difference Measurement for Parallel Multi-Channel Sensors
A 34 dBm IP0.1dB SOI SP3T switch with an integrated negative-bias switch controller at 2.4 GHz
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS)
A 12-bit 5MS/s Synchronous SAR ADC With Comparator Using High Gain Pre-amplifier
Convolutional Neural Network-based Keyword Classification for Mixer Control
Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes
A linear InGaP/GaAs HBT power amplifier for LTE B7 applications
Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design
A high-sensitivity signal conditioning interface for capacitive touch key using ΔΣ modulation
Hardware-friendly Activation Functions for HybridViT Models
Design of 36 dB IRR baseband analog for Bluetooth low energy 5.0 application in 55 nm CMOS
Image Radar-based Traffic Surveillance System: An all-weather sensor as intelligent transportation infrastructure component
eFuse based IC authentication architecture
Speed-adaptive ratio-based lane detection algorithm for self-driving vehicles
Design and Validation of a Blocker Rejection LNA with On-Chip Dual-Notch Filters
Effect of Mutual Information on Chaotic Attractor Classification Accuracy Using Neural Network
Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture
MTJ based non-volatile flip-flop in deep submicron technology
Reliability Optimization of ReRAM Architecture using Heterogeneous Error Correcting Code Scheme
Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS
A simplified, high-speed, Error-tolerant Adder using Zero Padding Method
Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping
Optimizing Image Classification with Inverse Depthwise Separable Convolution for Edge Devices
DNN-based Cancer Recurrence Predictor using FPGA
ASK Modulator Spur reduction using Sigma Delta Modulator and Oscillator
A smart low power R-R-I heartbeat monitor system with contactless UWB sensor
Hardware/software model of DCO-OFDM based visible light communication SoC using DMA
A low power 2.4 GHz quadrature local oscillator buffer for Bluetooth low energy applications
Low Noise Analog Front End for IoT Sensor
Roadmap for Ferroelectric Memory: Challenges and Opportunities for IMC Applications
A highly linear DPOTA-based configurable analog front-end for EXG (EEG, ECG, and EMG)
How to design hardware prime field multipliers for bilinear pairing
Fusing Infrared and Visible Images for DNN-based Nighttime Human Detection
Parallelization of Local Path Planning for High Reliable Autonomous Drones
Chattering phenomenon in a high-side gate driver circuit using MOSFET equivalent circuit
Precision Exploration of Floating-Point Arithmetic for Spiking Neural Networks
A Low-Noise Capacitively-Coupled Chopper Instrumentation Amplifier with SAR-Assisted Low Current Ripple Reduction Technique
Performance hotspot based CUDA acceleration
Enhancing Stochastic Computing using a Novel Hybrid Random Number Generator Integrating LFSR and Halton Sequence
A 1.92 μA Always-on ECG Monitoring Mixed-Signal SoC for Implantable Medical Application
Nano-ampere Current Sensing Technique for OLED Mobile Displays
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process
Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits
Multiple output variable overdrive voltage CMOS current mirror
Low Power High Performance Match Line Design of Content Addressable Memory
Experimental Verification of Slow-Scale Oscillation in DC-DC Converter with Photovoltaic Module
Exploiting Configurability for Correct Sign Calculation in an Approximate Adder
Variation-Tolerant Separated Pre-Charge Sense Amplifier for Resistive Non-Volatile logic circuit
High-throughput HW-SW implementation for MV-HEVC decoder
Automated Reverse Engineering Tools for FPGA Bitstream Extraction and Logic Estimation
Low-power and real-time computer vision on-chip
An ultra-low power AES encryption core in 65nm SOTB CMOS process
Pedestrian Detection in Infrared Thermal Images Based on Raised Cosine Distribution
A high CMRR, high input impedance current-feedback instrumentation amplifier (CFIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors
Efficient IFFT architecture design for OFDM applications
Image compression based on MR-CNN (Modified Region Convolutional Neural Network)
SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation
Lower-part Stochastic Unipolar Adder to Improve Computation Accuracy
Deep Learning Hardware/Software Co-Design for Heart Sound Classification
Deep Neural Network Training Accelerator Designs in ASIC and FPGA
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface
Design of a Generic Security Interface for RISC-V Processors and its Applications
Synchronizations in Three Coupled Oscillators with Memristor Synapses as Ring Structure
Binary Content-Addressable Memory System using Nanoelectromechanical Memory Switch
A 22.8-to-32.4 GHz Injection-locked Frequency Tripler with Source Degeneration
A SoC platform for emerging technologies
A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC
A RAM cache approach using host memory buffer of the NVMe interface
A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS
A Cost-efficient FPGA-based Embedded System for Biosensor Platform
Quantum Battery Optimization through Quantum Machine Learning Techniques
A multiband fully integrated high-linearity power amplifier using a 0.18-μm CMOS process for LTE applications
A low-power and performance-efficient SAR ADC design
A 5.8GHz 9.5 dBm Class-E Power Amplifier for DSRC Applications
An inter-frame macroblock schedule for memory access reduction in H.264/AVC bi-directional prediction
Enabling cell selection optimization for non-traditional CMOS topologies
Design and Automatic Generation of High-Speed Circuits for Wireline Communications
PSO-based Design Procedure for Class-DE Inverter
An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor
Application on Demodulation of FBG Sensing Signals using Phase Detection Algorithm of Intake and Exhaust
Robust optical fingerprint sensor to moisture fingerprints
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction
3T1R Memristor Crossbar Architecture for Diverse Logic Implementation