yusuke1997/dblp-id-title huggingface dataset:
A 2-path bandpass sigma-delta modulator utilizing blue-noise path selection
An Efficient Task Mapping for Manycore Systems
Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops
Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting
CNN-based local motion estimation chip for image stabilization processing
Design of a configurable neural Data compression system for intra-cortical implants
Clustering in globally coupled system of chaotic circuits
A novel microstrip bandpass filter design using asymmetric parallel coupled-line
A Transceiver for NMR Field Probes Integrated in a Low-Power CMOS Process
Set-valued Derivative and Lyapunov Method for Full-range Cellular Neural Networks
A 10-bit fast lock all-digital data recovery with CR oscillator reference for automotive network
Data hiding for digital video with phase of motion vector
A highly scalable 3D chip for binary neural network classification applications
Attack-Resilient Temperature Sensor Design
A Real-time Image Feature Vector Generator Employing Functional Cache Memory for Edge Flags
A novel RTD-HEMT-RTD structure based on simulations
Post linearization of CMOS LNA using double cascade FETs
Inter-layer intra mode coding for the scalable extension of HEVC
A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation in 65 nm CMOS
NESP: An Analog Neural Signal Processor
A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS
Systematic synthesis method for analogue circuits. Part III. All-transistor circuit synthesis
Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control
A W-Band 6.8 mW Low-Noise Amplifier in 90 nm CMOS Technology using Noise Measure
A Battery-free Pavement Roughness Estimation System Based on Kinetic Energy Harvesting
What PNN Says About Spur Rolloff Rates in MASH-Based CP-PLLs With Polynomial Distortion
A Low-Cost Instrument for Estimating the Starch Content of Cassava Roots Based on the Measurement of RF Return Loss
A 0.8V Delta-Sigma modulator using DTMOS technique
Time- and Order-recursive Estimation of Higher Order Moments in a Linear Array
A novel code acquisition algorithm and its application to Markov spreading codes
A CMOS-Based Capacitive Sensor for Laboratory-On-Chips: Design and Experimental Results
TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs
Designing Operational Transconductance Amplifiers for Low Voltage Operation
Dependability-increasing technique for a multi-context optically reconfigurable gate array
Mermite-like Reduction Method for Design of Perfect Reconstruction Multiband Linear Phase Filter Banks
Transaction level modeling of IEEE 802.11 system
Memristor-based LSTM neuromorphic circuits for offshore wind turbine blade fault detection
A CMOS OTA free from second order effects with a high input resistance Gm control terminal
Full parallel process for multidimensional wave digital filtering via multidimensional retiming technique
Advanced IC technology - opportunities and challenges
High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes
Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing
Improvements in biasing and compensation of CMOS opamps
Live Demonstration: A Frame-Based CMOS Vision Sensor with High Dynamic Range for Events Generation
A simple digital architecture for a harmonic-cancelling sine-wave synthesizer
An alternative strategy for reducing mode transitions in a four-switch buck-boost converter
A new approach for non-uniform subband adaptive filtering
CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric
A low power third order delta-sigma modulator for digital audio applications
Phase difference and frequency offset estimation for collaborative beamforming in sensor networks
Automated state-variable formulation for power electronic circuits and systems
Direct digital synthesizer with tunable delta sigma modulator
Design and parallel implementation of an adaptive baseline wander compensator for high-speed optical coherent receivers
Charge recovery logic for thermal harvesting applications
Network condition detection for video transport over wireless Internet
High-Speed VGSOT-MRAM Design for Non-Volatile Cache Memories
Design of a Multi-Sensor Framework for the Real-time Monitoring of Social Interactions
Cycle-true leakage current modeling for CMOS gates
Multidimensional stability test using sum-of-squares decomposition
An inertial sensor based balance and gait analysis system
FPGA demonstration of spiking support vector networks based on growth transform neurons
A new blind wavelet domain watermark detector using hidden Markov model
Decoders for low-density parity-check convolutional codes with large memory
Simultaneous Series-Parallel High-Speed and Accurate Active Cell Balancing for Improved Battery Life
Synchronization and Bifurcations in Networks of Coupled Hindmarsh-Rose Neurons
Towards low-power wearable wireless sensors for molecular biomarker and physiological signal monitoring
A novel intra-rate estimation method for H.264 rate control
Improved roundoff noise performance in a direct-form IIR filter using a modified delta operator
Estimating the HEVC decoding energy using the decoder processing time
Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards
Comparative Analysis of AI-driven Feature Selection and Machine Learning Framework for Efficient Radar Fall Detection
An FPGA Accelerator for Spiking Neural Network Simulation and Training
A Temperature Compensated Variable Gain Phase Shifter Based on GaN HEMTs
C-NMT: A Collaborative Inference Framework for Neural Machine Translation
Fast classification using sparsely active spiking networks
Mixed-precision architecture based on computational memory for training deep neural networks
An Improved Tuning Technique for Switched Capacitor Filters
Design of low-leakage multi-port SRAM for register file in graphics processing unit
Dynamically Reconfigurable Resource Efficient AES Implementation for IoT Applications
A robust and efficient scale-space based metric for the evaluation of MPEG-4 VOPs
A Battery Management System with Charge Balancing and Aging Detection Based on ANN
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio
System-on-chip ultrasonic transducer for dental tissue formation and stem cell growth and differentiation
Sub-50-mV Charge Pump and its Driver for Extremely Low-Voltage Thermal Energy Harvesting
Analysis of hybrid systems by means of embedded return maps
New approaches to constrained optimization of digital filters
Speeding Design Centering By Reusing Simulated Data
A low cost method for testing offset and gain error for ADC BIST
Inferring spatial transmission of epidemics in networked metapopulations
Gaussian Process for Nonlinear Regression via Memristive Crossbars
An enhanced switching policy for buck-derived multi-level switching power amplifiers
Multi-layer floorplanning for reliable system-on-package
Analyzing Cooperation Dynamics of Group Interaction on Two Kinds of Scale-Free Networks
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture
A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform
MPEG-4 video codec IP design with a configurable embedded processor
A Sliding Mode-based Filter for Non-stationary Signals
Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners
Graphene nanoribbon field-effect transistors
Output-pattern directed decomposition for low power design
Introduction to the Discrete Shapelet Transform and a new paradigm: Joint time-frequency-shape analysis
Harmonic Characteristics of LCC-HVDC under Unbalanced Conditions
International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil
On the Angular Decomposition Technique for Computing the Discrete Fractional Fourier Transform
A Comprehensive Tapered buffer optimization algorithm for unified design metrics
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference
Twiddle factor memory switching activity analysis of radix-2 2 and equivalent FFT algorithms
Cascode buffer for monolithic voltage conversion operating at high input supply voltages
Dual-edge triggered level converting flip-flops
Hardware implementation of a CNN for analog simulation of reaction-diffusion equations
Address Code Optimization Exploiting Code Scheduling in DSP Applications
A placement algorithm for implementation of analog LSI/VLSI systems
Modified Layered Message Passing Decoding with Dynamic Scheduling and Early Termination for QC-LDPC Codes
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
Enhanced Student-graph Representation for At-risk Student Detection
Accelerated frequency domain adaptive filter using modified DFT pair and its application to noise canceling
Deep Learning for Block-Level Compressive Video Sensing
A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization
Hybrid image interpolation with soft-decision kernel regression
VLSI implementation of incremental fixed-complexity LLL lattice reduction for MIMO detection
Molecular building blocks for non-linear circuits
Robust pole location for a DC-DC converter through parameter dependent control
Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit
A pulse-shaped power amplifier with dynamic bias switching for IR-UWB transmitters
A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays
An improved method of power control with CMOS class-E power amplifiers
Low-dropout voltage reference: An approach to buffered architectures with low sensitivity
An Accurate dB-Linear Programmable-Gain Amplifier with Temperature-Robust Characteristic
Offset correction of low power, high precision op amp using digital assist for biomedical applications
Emulator Design and Generation of Synthetic Dataset in Multi-Ion Sensing
Design of a low-cost low-power baseband-processor for UHF RFID tag with asynchronous design technique
A very high performance address BUS encoder
Multi-Channel FFT Architectures Designed via Folding and Interleaving
Toward 1000-ch electrode array based on distributed microchip architecture for retinal prosthesis
The theoretical efficiency in digital envelope power amplifiers for WLAN OFDM polar transmitters
Power losses and efficiency of class E RF power amplifiers at any duty cycle
Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs
Steady-state analysis of a subband adaptive algorithm with critical sampling
Studies on the Stability of Two Dimsensional Analog Nonlinear Circuits
Perceptual image compression via adaptive block- based super-resolution directed down-sampling
A background calibration technique for multibit delta-sigma modulators
Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers
A switched-mode multichannel neural stimulator with a minimum number of external components
On the Use of a UML-Based HW/SW Co-Design Platform for Reconfigurable Cryptographic Systems
Obsolete integrated circuit replacement methodology using advanced electronic design automation technology
Robust wide range of supply-voltage operation using continuous adaptive size-ratio gates
A Master-slave Scheme to Tune Gain of Transconductance Amplifiers with High Accuracy
Unified lossless and near-lossless color image coding based on adaptive quantization
Mutual Synchronization with 24 GHz Oscillators
A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs
Properties of RF bandpass amplifier topology with Q-enhancing
A new method for implementing gate operations in a quantum factoring algorithm
The extraction of transistor mismatch parameters: the CMOS current-steering D/A converter as a test structure
A search algorithm for the design of multinested cellular neural networks
A Wireless Wearable Sensor for Pointing and Arm-Gesture Recognition
A High Accuracy Approximate Multiplier with Error Correction
Lov-Voltage (3.3V) / Low-Power (100muW), 2MHZ CMOS Comparator for 12-BIT ADCS
A novel structure for portable digitally controlled oscillator
Approaching the limits of piezoelectricity driven hot-electron injection for self-powered in vivo monitoring of micro-strain variations
Ratio Based Analog Design and Transistor Distortion Characteristics
Gain/phase imbalance and DC offset compensation in quadrature modulators
Noisy Component Extraction (Noice)
Linearity, Accuracy and Bandwidth Considerations in Wideband CMOS Voltage Amplifiers
Multi-parameter homotopy methods for finding DC operating points of nonlinear circuits
Implementation of encryption algorithms on transport triggered architectures
Event-based color change pixel in standard CMOS
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology
State-Space Analysis of Power Complementary Analog Filters
An architecture for best-basis algorithm using threshold cost function for images
Floorplanning with Datapath Optimization
Weighted prediction in the H.264/MPEG AVC video coding standard
Gradient-based depth estimation from 4D light fields
Wavelet domain one-bit transform for low-complexity motion estimation
An Optically-Programmable Absorbing Metasurface
Metal-over-gate MOSFET modeling for radio frequency IC applications
Dynamic characterization of building electrical loads by equivalent energy circuit analysis
A switch mode resonating H-Bridge polar transmitter using RF ΣΔ modulation
Multi-channel Medium Access Control Protocols for Wireless Networks within Computing Packages
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations
A subspace-based method for DOA estimation of uniform linear array in the presence of mutual coupling
Recursive patching for video-on-demand (VOD) systems with limited client buffer constraint
Switched-capacitor integrator design optimizing for power and process variations
Adaptive LMS processing architectures employing frequency domain sub-convolution
Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs
A portable multi-channel potentiostat for real-time amperometric measurement of multi-electrode sensor arrays
Automatic verification of transition systems with unspecified components
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
A Novel Method for the Realization of Complex Logic Functions using Switching Lattices
Filter-Bank Interpretation and Fixed-Point Numerical Accuracy of Subband FFT
A new L1-regularized time-varying autoregressive model for brain connectivity estimation: A study using visual task-related fMRI data
A highly linear front-end based on a logarithmic multiplier-filter
PIN count prediction in ratio cut partitioning for VLSI and ULSI
An unlimited lock range DLL for clock generator
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator
A low-cost CMOS time interval measurement core
SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation
ADHD Classification with Robust Biomarker Detection Using Knowledge Distillation
Impedance Model and Stability Analysis of Offshore Wind Farm via AC Submarine Cable
Blind separation and filtering using state space models
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique
A sub-1V BJT-based CMOS temperature sensor from -55 °C to 125 °C
Impedance Modeling of Switched-Inductor Bias-Flip Piezoelectric Energy Harvesting Circuits
Optimal weight adaptation for multilayer neural networks
Design of a multidimensional split vector-radix decimation-in-frequency FFT algorithm
Dependant distance potential source algorithm for optimal path finding with the analogic CNN
On instantaneous vs. syllabic companding in log domain filters
A Low-Power Cyclic ADC with Capacitive Degeneration Amplifier and Charge Mode Operation
Multivalued Neural Associative Memory
A V-Band Low-Phase-Noise VCO with Transformer-Based Gm-Boosting Technique
Design of multidimensional filter banks using Grobner bases: a survey
A High Throughput-Rate Architecture for 8*8 2-D DCT
Subspace learning in the presence of sparse structured outliers and noise
Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity
International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan
A Multimodal Impedance and Optical CMOS Sensor with Integrated On-Chip Energy Harvesting
Balancing Adder for error tolerant applications
Multi-window real-valued discrete Gabor transform for long and infinite sequences
Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization
Wideband noise cancelling balun LNA with feedback biasing
Prediction of subharmonic oscillation in switching regulators with integrative feedback loops
Complete characterization of channel independent general DMT systems with cyclic prefix
Identifation for robust control design: A comparison of set-membership and statistical methods
Design of a step-up dc-dc converter with on-chip coupled inductors
Extensional design for noise-tolerate MRF standard cells via global mapping
A floating-gate programmable array of silicon neurons for central pattern generating networks
Live demonstration: The self-tuned regenerative electromechanical parametric amplifier
A low-complexity ICI mitigation method for high-speed mobile OFDM systems
Reconfigurable Precision SRAM-based Analog In-memory-compute Macro Design
GENHOP: An Image Generation Method Based on Successive Subspace Learning
A 7ms Speed Automatic Driving Current Signal Cancellation Technique for Bio-Impedance Measurement
A Neural Network for Blind Signal Separation
Low cost and energy, thermal noise driven, probability modulated random number generator
REGAL: Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM
Reverse-Time Chaos from a Randomly Driven Filter
A low-power, ultra low-offset, 16.5-bit, ΣΔ ADC for coulomb counting and fuel gauge applications
Asynchronous consensus of second-order multi-agent systems with aperiodic sampled-data
System-on-Chip design using intellectual properties with imprecise design costs
A novel current-conveyor-based switched-capacitor integrator
A 1.8V low-jitter CMOS ring oscillator with supply regulation
Calculation of the cycle length in a HK-MASH DDSM with multilevel quantizers
The design of a 1 V, 40 MHz, current-mode sample-and-hold circuit with 10-bit linearity
Energy model of CMOS gates using a piecewise linear model
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT
Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time
On-the-fly tests for non-ideal true random number generators
A BDD Based Algorithm for Detecting Difficult Faults
Transmitter utilising bandpass delta-sigma modulator and switching mode power amplifier
HermesC: RF wireless low-power neural recording system for freely behaving primates
A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision
Notes on representation theorems for linear discrete-space systems
Efficient stack filter implementations of rank order filters
EFFRBNet: A Deep Super Resolution Network using Edge-Assisted Feature Fusion Residual Blocks
A General Purpose Discrete-Time Multiplexing Neuron-Array Architecture
Design of a MIMO OFDM baseband transceiver for cognitive radio system
Area-efficient digital baseband module for Bluetooth wireless communications
RM3 based logic synthesis (Special session paper)
FPGA-based machine vision implementation for Lab-on-Chip flow detection
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup
Evaluation of neural network architectures for embedded systems
Cell spreading optimization for force-directed global placers
Comparative Study of Amplifiers with High-Frequency and Low-Frequency Chopping
Audio event classification using binary hierarchical classifiers with feature selection for healthcare applications
A Low-Power and Area-Efficient Analog Duty Cycle Corrector for ADC's External Clocks
A lateral-BJT-biased CMOS voltage-controlled oscillator
Search space reduction for the non-exact projective NPNP Boolean matching problem
Frequency-domain design of 2-D digital filters using the Fornasini-Marchesini second model
Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems
Three-layer bidirectional asymmetrical associative memory
Speed Imagery EEG Classification with Spatial-temporal Feature Attention Deep Neural Networks
Fast and Accurate Event Driven Simulation of Partly Analog Phase-Locked Loops
Step-response-based characterization of nonuniform perfect-reconstruction filter banks
A low-power, 10 GHz back-gated tuned voltage controlled oscillator with automatic amplitude and temperature compensation
30-fps SNR equalized electrical impedance tomography IC with fast-settle filter and adaptive current control for lung monitoring
Modeling power amplifiers with antenna mismatch
Proportional Source Transconductances Integrator for CMOS Analog Filtering with Calibration
A matrix transform imager allowing high-fill factor
A 2.5-V Sigma-Delta modulator in 0.25-µm CMOS for ADSL
A 40-nm 6.75 TOPS/W Quantization-Aware NN Processor for High-Energy-Efficiency Image Recognition
A Reconfigurable Arbiter PUF Based on STT-MRAM
Organic memristors : Basic principles
A Low Phase Noise Dual Core Colpitts Push-Push type VCO at 78 GHz in 90 nm SiGe BiCMOS Technology
Parametrical modeling and identification of a class of hybrid systems under persistent excitation of the input
Architecture and implementation of an associative memory using sparse clustered networks
An adaptive bandwidth reduction scheme for video coding
Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs
Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array
Automated Penetration Testing for Industrial IoT Systems: Enhancing Efficiency and Reducing Reliance on Human Expertise
A CMOS low-power, high-speed, asynchronous comparator for synchronous rectification applications
Asynchronous Adiabatic Logic
Robust super-exponential methods for blind equalization of SISO systems with additive Gaussian noise
Transmission mechanisms with variable tissue properties in a paired electrode system for transcutaneous power
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects
Address-event image sensor network
Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access Memories
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion
A Novel Cross-layer Data Aggregation Approach for Extreme Values in Wireless Sensor Networks
A low-complexity high-performance noncoherent receiver for GFSK signals
Adaptive intra-frame quantization for very low bit rate video coding
High-selectivity SC filters with continuous digital Q-factor programmability
Fast rate distortion optimization with adaptive context group modeling for HEVC
Ultra Low Power Video Understanding Smart Vision SoC with On-Chip Sensing and Hybrid Similarity-Aware SRAM/ROM CIM Macro
A parallel CAVLC design for 4096×2160p encoder
Bandwidth limits in PWM switching amplifiers
An NS-SAR ADC with Full-bit High-order Mismatch Shaped CDAC
Large-signal S-parameters CAD technique applied to power amplifier design
A New Approach to Nonlinear Digital Signal Processing