yusuke1997/dblp-id-title huggingface dataset:
On Correction of A Delay Value Using Ring-Oscillators for Aging Detection and Prediction
At-Speed Testing with Timing Exceptions and Constraints-Case Studies
30th IEEE Asian Test Symposium, ATS 2021, Matsuyama, Ehime, Japan, November 22-25, 2021
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control
Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data
Targeting Leakage Constraints during ATPG
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing
A Region-Based Framework for Design Feature Identification of Systematic Process Variations
An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors
An ADC Test Technique With Dual-Path/Multi-Functional Fine Pattern Generator Realizing High Accuracy Measurement for CMOS Image Sensor
A Class of Linear Space Compactors for Enhanced Diagnostic
Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE
High Performance/Delay Testing
March Based Memory Core Test Scheduling for SOC
Pattern Encodability Enhancements for Test Stimulus Decompressors
Two-Dimensional Test Generation Objective
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
A Jitter Characterizing BIST with Pulse-Amplifying Technique
A 5 Gbps Wafer-Level Tester
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs
A concurrent fault-detection scheme for FFT processors
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating
An Effective Design for Hierarchical Test Generation Based on Strong Testability
High-Speed Interface Testing
SoC Testing and P1500 Standard
Best Paper Awards (2002 and 2003)
Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated Stimulus
Multi-cycle Test with Partial Observation on Scan-Based BIST Structure
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior
Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes
A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter
IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy
Test Time Minimization for Hybrid BIST of Core-Based Systems
Carbon Quantum Dot Fluorescent Stickers for Biochip Authentication
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator
Validating GCSE in the scheduling of high-level synthesis
Power Supply Droop and Its Impacts on Structural At-Speed Testing
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs
Study of N-Detectability in QCA Designs
An Algorithm for All-du-path Testing Coverage of Shared Memory Parallel Programs
Transaction Level Modeling and Design Space Exploration for SOC Test Architectures
On-the-Fly Reduction of Stimuli for Functional Verification
A Covert Attack Method Against FPGA Clouds
Defect-Oriented Test for Ultra-Low DPM
Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits
Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest Factor
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
A parallel sequential test generation system DESCARTES based on real-valued logic simulation
Automatic Testability Analysis of Boards and MCMs at Chip Level
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits
An Efficient Compact Test Generator for IDDQ Testing
Flip-flop chaining architecture for power-efficient scan during test application
Session Summary II: Dependable VLSI for Product Reliability
Tree-Based Logic Encryption for Resisting SAT Attack
Testability of Cryptographic Hardware and Detection of Hardware Trojans
A Partially-Exhaustive Gate Transition Fault Model
A Survey on Fault-Tolerance Methods for SRAM-Based FPGAs in Radiation Environments
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability
A programmable multiple-sequence generator for BIST applications
HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC
The Region-Exhaustive Fault Model
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories
An effective fault simulation method for core based LSI
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing
A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits
Challenges for the Academic Test Community
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs
A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume
On the feasibility of fault simulation using partial circuit descriptions
Adaptive Low Shift Power Test Pattern Generator for Logic BIST
DFT closure
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip
Opportunities and Verification Challenges of Run-Time Performance Adaptation
Optimized Assignment Coverage Computation in Formal Verification of Digital Systems
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
Test Generation of Path Delay Faults Induced by Defects in Power TSV
On the Switching Activity in Faulty Circuits During Test Application
A SmartBIST Variant with Guaranteed Encoding
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults
Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing
Novel techniques for improving testability analysis
Low Power Reduced Pin Count Test Methodology
The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time
On the Use of Scan Chain to Improve Physical Attacks (Extended Abstract)
A Low Overhead On-Chip Path Delay Measurement Circuit
LBIST/ATPG Technologies for On-Demand Digital Logic Testing in Automotive Circuits
Calibration as a Functional Test: An ADC Case Study
An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test
A Design of Approximate Voting Schemes for Fail-Operational Systems
Scan Chain Diagnosis Using IDDQ Current Measurement
A Structured Testing Approach for DSP Software
Analysis and Attenuation Proposal in Ground Bounce
Low-cost Production Test of BER for Wireless Receivers
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults
Tx7901 Dft
Two-Step Dynamic Encoding for Linear Decompressors
A Partial Scan Design Method Based on n-Fold Line-up Structures
A Review of Power Strategies for DFT and ATPG
Power-Aware Test Data Compression for Embedded IP Cores
A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features
Design for Testability of Software-Based Self-Test for Processors
Security Implications of Cyberphysical Flow-Based Microfluidic Biochips
PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment
Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain Faults
Formal Verification Of Self-Testing Properties Of Combinational Circuits
Production Test of High Volume Commercial RFIC
EMI characterization for power conversion circuit with SiC power devices
High Precision Measurement of Sub-Nano Ampere Current in ATE Environment
Improving Output Compaction Efficiency with High Observability Scan Chains
How to Secure Scan Design Against Scan-Based Side-Channel Attacks?
Coverage Directed Test Generation: Godson Experience
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch
Potentiality of Data Fusion in Analog Circuit Fault Diagnosis
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages
Sequential Test Generation Based on Circuit Pseudo-Transformation
A New Technique to Ensure Quality of Test Patterns
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling
Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs
DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity
Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of Dependability
An Adaptive Test for Parametric Faults Based on Statistical Timing Information
A new method for testing mixed analog and digital circuits
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
Test Data Volume Reduction by Test Data Realignment
An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI
Defect Level Prediction Using Multi-Model Fault Coverage
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults
Defect Diagnosis - Reasoning Methodology
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs
A Case Study on Formally Verifying an Open-source Deep Learning Accelerator Design
Delay Testing with Double Observations
A Probabilistic Model for Path Delay Faults
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
Circuit-Width Based Heuristic for Boolean Reasoning
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC
Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test
Side-Channel Attack on Flipped Scan Chains
Efficient Use of Unused Spare Columns to Improve Memory Error Correcting Rate
A Probabilistic and Constraint Based Approach for Low Power Test Generation
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths
Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits
IDDQ Test Methodology and Tradeoffs for Scan/Non-Scan Designs
TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs
3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter
An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits
An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs
High-Throughput Transistor-Level Fault Simulation on GPUs
An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation
GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators
Testing CPU Based Boards for Functionality Using Bus Cycle Signature System
An Innovative Methodology for Scan Chain Insertion and Analysis at RTL
Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators
Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods
Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems
Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity
Advisory Board and Organizing Committee
A Process Monitor Based Speed Binning and Die Matching Algorithm
Test Cycle Count Reduction in a Parallel Scan BIST Environment
A Unified Approach to Partial Scan Design using Genetic Algorithm
A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips
Unexpected Error Explosion in NAND Flash Memory: Observations and Prediction Scheme
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Alleviating DFT Cost Using Testability Driven HLS
On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits
An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing
Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains
Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's
Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs
On Improving Defect Coverage of Stuck-at Fault Tests
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation
TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm
Power Supply Noise Sensor Based on Timing Uncertainty Measurements
Survey: Hardware Trojan Detection for Netlist
Software-Based Delay Fault Testing of Processor Cores
Random Pattern Testable Design with Partial Circuit Duplication
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs
Emerging Techniques for Test Data Compression
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies
An On-Chip Digital Environment Monitor for Field Test
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits
A Test Methodology for Interconnect Structures of LUT-based FPGAs
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
An Efficient Random-like Testing
FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code
Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces
Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path
Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing
Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip
Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault Analysis
Defect Coverage-Driven Window-Based Test Compression
Programmable Leakage Test and Binning for TSVs
Testing Inter-Word Coupling Faults of Wide I/O DRAMs
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework
A Study on Software Reliability Prediction Based on Transduction Inference
Analog Metrology and Stimulus Selection in a Noisy Environment
To Overtest Or Not To Overtest - More Questions Than Answers
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure
Scan-Puf: Puf Elements Selection Methods for Viable IC Identification
Challenges in High Speed Interface Testing
Artificial Neuron Hardware IP Verification
Template-Based and Coverage-Guided Verification Instruction Set Automatic Generation Method for DSP Chip
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester
DFT Aware Layout - Layout Aware DFT
Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC
Robust Space Compaction of Test Responses
Model-Free Testing of Analog Circuits
Accelerated test pattern generators for mixed-mode BIST environments
A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design
Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs
CPU Utilization Micro-Benchmarking for RealTime Workload Modeling
A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family
A New Model with Time Constraints for Conformance Testing of Communication Protocols
On the Compaction of Test Sets Produced by Genetic Optimization
Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost
Accurate Multi-cycle ATPG in Presence of X-Values
On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests
Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults
Scenario Based Integration Testing for Object-Oriented Software Development
A Sigma-Delta Modulation Based BIST Scheme for A/D Converters
On Detecting and Defending AdvDrop Adversarial Attacks by Image Blurring and Adaptive Noising
Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket
Fast Window Test Method of Hysteresis Test
At-Speed Built-in Test for Logic Circuits with Multiple Clocks
The Ultimate Chase
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
A Stochastic Model for NBTI-Induced LSI Degradation in Field
Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors
LLM vs HLS for RTL Code Generation: Friend or Foe?
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
Side-channel Attacks on Memristive Circuits Under External Disturbances
Robust Self Concurrent Test of Linear Digital Systems
Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis
A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic
Progressive ECC Techniques for Phase Change Memory
Test and Reliability of Emerging Non-volatile Memories
Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories
On the Adders with Minimum Tests
Delta-IDDQ Testing of Resistive Short Defects
Non-Intrusive Testing of High-Speed CML Circuits
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays
Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators
An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System
Post-Silicon Test Flow for Aging Prediction
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test
Soft Error Issues with Scaling Technologies
Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs
Power Conscious BIST Design for Sequential Circuits Using ghost-FSM
Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems
Session Summary IV: Post-Silicon Measurements and Tests: Analog Test and High-Speed I/O Test II
Bridge Defect Diagnosis with Physical Information
An Object-Oriented Program Automatic Execute Model and the Research of Algorithm
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs
Effective Automated Testing: A Solution of Graphical Object Verification
Parallel LFSR Reseeding with Selection Register for Mixed-Mode BIST
Efficient Test Methodologies for Conditional Sum Adders
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology
Practical Needs and Wants for Silicon Debug and Diagnosis
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs
XOR-Based Response Compactor Adaptive to X-Density Variation
Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation
Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics
Low Power Test Compression Technique for Designs with Multiple Scan Chain
On Decomposition of Kleene TDDs
Note on CapsNet-Based Wafer Map Defect Pattern Classification
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs
Test Pattern Generation for Column Compression Multiplier
Static Testing of ADCs Using Wavelet Transforms
An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume Production
High Level Test Generation for Custom Hardware: An Industrial Perspective
BIST Diagnostics, Part 1: Simulation Models
Automated System for Testing and Result Analysis for Payload Controller
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis
Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST
Classification of Sequential Circuits Based on ?k Notation
A Testable/Fault Tolerant FFT Processor Design
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design
Guaranteeing Testability in Re-encoding for Low Power
TI-BIST: a temperature independent analog BIST for switched-capacitor filters
22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013
Cloud-Based PVT Monitoring System for IoT Devices
Test Generation for Multiple-Threshold Gate-Delay Fault Model
Optimized Statistical Analog Fault Simulation
Error Resilient Real-Time State Variable Systems for Signal Processing and Control
New Class of Tests for Open Faults with Considering Adjacent Lines
Test Scheduling for Memory Cores with Built-In Self-Repair
Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs
An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing Solution
A Novel TSV Repair Framework for 3-D Stacked ICs
Addressing Test Challenges in Advanced Technology Nodes
An Efficient Diagnosis Scheme for Random Access Memories
An Optimization Problem for Topological Quantum Computation
Combined Impact of BTI and Temperature Effect Inversion on Circuit Performance
Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
A Quasi-best Random Testing
Tolerance DC bands of CMOS operational amplifier
An effective BIST scheme for carry-save and carry-propagate array multipliers
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates
Highly Dependable Multi-processor SoCs Employing Lifetime Prediction Based on Health Monitors
Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking
Post-Silicon Jitter Measurements
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures
Foreword: ATS 2022
Vector Memory Expansion System For T33xx Logic Tester
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model
Comparison Diagnosis in Large Multiprocessor Systems
Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2)