yusuke1997/dblp-id-title huggingface dataset:
Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders
A Programming Model and a NoC-Based Architecture for Streaming Applications
FPGA based 77GHz RADAR processing with novel linearisation
Emulation-Based Fault Effect Analysis for Resource Constrained, Secure, and Dependable Systems
Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing
V2I Cooperation for Traffic Management with SafeCop
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
A High Performance Java Card Virtual Machine Interpreter Based on an Application Specific Instruction-Set Processor
Abeto framework: a Solution for Heterogeneous IP Management
Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs
Design of a Redundant FPGA-Based Safety System for Railroad Vehicles
Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware
MEDA Biochip based Single- Target Fluidic Mixture Preparation with Minimum Wastage
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card
Portable Simulation Models for Energy Aspects of IoT Devices in the LoLiPoP-IoT Project
Functional Validation of Programmable Architectures
Capacitive Sensors Matrix for Interface Pressure Measurement in Clinical, Ergonomic and Automotive Environments
Designing Approximate Arithmetic Circuits with Combined Error Constraints
Temperature Dependence of ROPUF on FPGA
Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core System
Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based Design
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications
RSM Protection of the PRESENT Lightweight Cipher as a RISC-V Extension
Accurate Inexact Calculations of Non-Homogeneous Markov Chains
A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors
Estimation of Blood Pressure and Pulse Transit Time Using Your Smartphone
Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology
A Fault Attack Emulation Environment to Evaluate Java Card Virtual-Machine Security
Opportunistic Pervasive Computing with Domain-Oriented Virtual Machines
Latency-Optimized Hardware Acceleration of Multilayer Perceptron Inference
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher
ADONN: Adaptive Design of Optimized Deep Neural Networks for Embedded Systems
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit
FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems
Towards Reversed Approximate Hardware Design
High Availability Fault Tolerant Architectures Implemented into FPGAs
Efficient Construction of Global Time in SoCs Despite Arbitrary Faults
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration
Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip
Adaptive High-End Microprocessor for Power-Performance Efficiency
Embedded System for Camera-Based TV Power Reduction
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits
A Serial Logarithmic Number System ALU
Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip Multiprocessors
Low-Power Implementation of a U-Net-based Model for Heart Sound Segmentation on a Low-Cost FPGA
On a Security-oriented Design Framework for Medical IoT Devices: The Hardware Security Perspective
Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey
Hardware-level Access Control and Scheduling of Shared Hardware Accelerators
NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables
The Challenges for High Performance Embedded Systems
Live State-of-Health Safety Monitoring for Safety-Critical Automotive Systems
SAT-Based Generation of Optimum Function Implementations with XOR Gates
SimIoT: A Simulator for Verification and Profiling of Complex IoT Deployments
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping
Circadia: Checkpointing for Intermittent Computing in AI Driven Applications
High-Throughput BitPacking Compression
Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip
An Embedded Implementation of the Microsoft Common Language Infrastructure
RobuCheck: A Robustness Checker for Digital Circuits
Autonomous Power Management for Embedded Systems Using a Non-linear Power Predictor
Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots
Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing
Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor
Trojan Immune Circuits Using Duality
Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics
A Latency-Efficient Router Architecture for CMP Systems
Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection
An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems
CART: Communication-Aware Routing Technique for Application-Specific NoCs
A Packet Classifier Using a Parallel Branching Program Machine
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing
An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images
2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015
Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Low Power Strategy for a TFT Controller
Power Spectral Density Side Channel Attack Overlapping Window Method
Design of an On-chip System for the SET Pulse Width Measurement
Trends in On-chip Dynamic Resource Management
Global Analysis of Resource Arbitration for MPSoC
Resource-Aware Decentralization of a UKF-Based Cooperative Localization for Networked Mobile Robots
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
Design of a Highly Dependable Beamforming Chip
A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC
PRYSTINE - PRogrammable sYSTems for INtelligence in AutomobilEs
Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems
Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction
reMORPH: A Runtime Reconfigurable Architecture
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies
Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution
Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures
Enhancing Battery Pack Capacity Utilization in Electric Vehicle Fleets via SoC-Preconditioning
2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey
Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs
Best Polarity for Low Power XOR Gate Decomposition
Auto-DOK: Compiler-Assisted Automatic Detection of Offload Kernels for FPGA-HBM Architectures
Minimal Stimuli Generation in Simulation-Based Verification
Design of Fault Tolerant Network Interfaces for NoCs
A Field Programmable Gate Array-Based Digital Temperature Sensor with Improved Immunity to Static Supply Shift
Combined SD-RNS Constant Multiplication
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
Parallel Multimedia Processor Using Customised Infineon TriCores
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes
From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs
Compression of Lookup Table for Piecewise Polynomial Function Evaluation
A High Level Power Model for the Nostrum NoC
Internet-Based IC Technology Design and Simulation
Co-Optimization of DNN and Hardware Configurations on Edge GPUs
User Flexibility Aware Price Policy Synthesis for Smart Grids
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units
Causality Constraints for Processor Architectures with Sub-Word Parallelism
Robustness in SOC Design
Power-of- Two Quantized YOLO Network for Pedestrian Detection with Dynamic Vision Sensor
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip
Prospeckz-5 - A Wireless Sensor Platform for Tracking and Monitoring of Wild Horses
RISC++: Towards an HLS Defined RISC-V SoC
MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip
Modeling and Scheduling of Composable Instruction Set
Traffic Scheduling Coprocessor with Schedulability Analysis Capability
Towards Post-Quantum Enhanced Identity-Based Encryption
Architecture of a Small Low-Cost Satellite
A Design Methodology for High Performance IC's: Wireless Broadband Radio Baseband Case Study
Off-Line Testing of Delay Faults in NoC Interconnects
A Comparison of Five Different Multiprocessor SoC Bus Architectures
Power Minimisation for Real-Time Dataflow Applications
Configurable Memory Organisation for Communication Applications
Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules
Alleviating Attack Data Scarcity: SCANIA's Experience Towards Enhancing In-Vehicle Cyber Security Measures
Improving Latency of Quantum Circuits by Gate Exchanging
Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration
ALOE-Based Flexible LDPC Decoder
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
FPGA-Based Encryption System for Cloud Security
RNS Arithmetic Units for Modulo {2^n+-k}
Network-Aware Virtual Platform for the Verification of Embedded Software for Communications
RDSP: A RISC DSP based on Residue Number System
Quantum-Dot Cellular Automata Serial Comparator
Power Consumption Modeling for DVFS Exploitation
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
Variations on Truncated Multiplication
Circumventing Uniqueness of XOR Arbiter PUFs
Fault Injection Techniques and their Accelerated Simulation in SystemC
Code Generation from Statecharts: Simulation of Wireless Sensor Networks
A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction
A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks
Co-designing Intelligent Control of Building HVACs and Microgrids
Evaluation of an FPGA-based Reconfigurable SoC for All-Digital Flexible RF Transmitters
Filtering Directory Lookups in CMPs
An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior
A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction Applications
Design of an Embedded Health Monitoring Infrastructure for Accessing Multi-processor SoC Degradation
LiteInjector: A LiteX Extension for Fault Injection
Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques
Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA
Majority Logic Synthesis for Spin Wave Technology
The Application of Formal Verification to SPW Designs
Real-Time Emulation of Multiple NAND Flash Channels by Exploiting the DRAM Memory of High-end Servers
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms
A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition
Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm
Generating On-Chip Heterogeneous Systems from High-Level Parallel Code
Generated Cycle-Accurate Profiler for C Language
A Majority-based Approximate Adder for FPGAs
Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis
GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
Preliminary findings on tools for the analysis of mental activity of programmers using EEG data from portable devices
Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes
Fault-Tolerant Deployment of Dataflow Applications Using Virtual Processors
Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks
A Multicore Embedded Processor for Fingerprint Recognition
Eliminating Write-After-Write Hazards to Improve Performance in Embedded Processors
Automatic Interface Generation for Component Reuse in HW-SW Partitioning
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration
Circuit Inspired Modeling Method for Irrigation
Verification-Driven Design Across Abstraction Levels: A Case Study
A Run-Time Support Environment for Reconfigurable Systems
A PQC and QKD Hybridization for Quantum-Secure Communications
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?
FPGA Design of Digital Circuits for Phonocardiogram Pre-Processing Enabling Real-Time and Low-Power AI Processing
Hybrid Post-Quantum Enhanced TLS 1.3 on Embedded Devices
Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks
A Distributed NUCA Architecture Using an Efficient NoC Multicasting Support
Yield-aware Floorplanning
Virtual TMR Schemes Combining Fault Tolerance and Self Repair
Evaluation of RTD-CMOS Logic Gates
An Efficient Hardware Implementation of a SAT Problem Solver on FPGA
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis
Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods
A Hybrid Timestamping Approach for Multi-Sensor Perception Systems
Hardware Strengthening a Distributed Logging Scheme
Formulating MITF for a Multicore Processor with SEU Tolerance
Energy Profiling of DNN Accelerators
Optimal Dependability and Fine Granular Error Resilience Methodology for Reconfigurable Systems
SystemC Model Generation for Realistic Simulation of Networked Embedded Systems
Passivity-Based Control over Differentiated-Services Packet Networks
Information-driven Library-based Circuit Synthesis
PRYSTINE - Technical Progress After Year 1
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
A Long-term Wearable Vital Signs Monitoring System using BSN
Effective Online Power Management with Adaptive Interplay of DVS and DPM for Embedded Real-Time System
Validation of Embedded Systems Using Formal Method Aided Simulation
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder
TERO-Based Detection of Hardware Trojans on FPGA Implementation of the AES Algorithm
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication
Are ring oscillators without a combinatorial loop good enough for Hardware Trojan detection?
Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*
Exploration of Custom Floating-Point Formats: A Systematic Approach
Analyzing the Impact of Probabilistic Estimates on Communication Reliability at Intelligent Crossroads
Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns
Compact Quantum Circuits for Dimension Reducible Functions
Self-Aware Wearable Systems in Epileptic Seizure Detection
Towards Fine-grained Side-Channel Instruction Disassembly on a System-on-Chip
Non-Profiled Semi-Supervised Horizontal Attack Against Elliptic Curve Scalar Multiplication Using Support Vector Machines
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs
Distributed Parallel Computing with Low Cost Microcontrollers for High Performance Electric Vehicles
Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance
A Virtual Platform for Performance Estimation of Many-core Implementations
RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip
Implementation of the Rainbow signature scheme on SoC FPGA
EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoC
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy
Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators
On Robustness of EDA Tools
An Approach to Minimization of Decision Diagrams
Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution
Efficient CRT RSA with SCA Countermeasures
PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC
An Asynchronous PLA with Improved Security Characteristics
Buffer Allocation for Dynamic Real-Time Streaming Applications Running on a Multi-processor without Back-Pressure
Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout
Exploring the Usage of Time-of-Flight Cameras for Contact and Remote Photoplethysmography
A VLIW Architecture for Logarithmic Arithmetic
Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis
Visualization of Memory Map Information in Embedded System Design
Influence of Structural Units on Vulnerability of Systems with Distinct Protection Approaches
Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling
Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs
Disparity Refinement Processor Architecture Utilizing Horizontal and Vertical Characteristics for Stereo Vision Systems
AUTOSAR AP and ROS 2 Collaboration Framework
SplitMS: Split Modulo-Scheduling for Accelerating Loops Onto CGRAs
Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework
On-Hardware Resilience Analysis of DPUAccelerated CNNs on FPGA-Based Systems
Enabling TDMA Arbitration in the Context of MBPTA
Predictive Analysis of Mission Critical Systems Dependability
Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation Specifications
How to Prove that a Circuit is Fault-Free?
Dummy Rounds as a DPA Countermeasure in Hardware
Enhancing the Availability of Web Services in the IoT-to-Edge-to-Cloud Compute Continuum: A WordPress Case Study
Towards Deploying Highly Quantized Neural Networks on FPGA Using Chisel
Functional Test Generation Remote Tool
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences
The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform
Nonlinear Compression Block Codes Search Strategy
Luminous Tiles: A New Smart Device for Buildings and Architectures
Industrial Application of IEEE P1687 for an Automotive Product
Implementing Modular FFTs in FPGAs - A Basic Block for Lattice-Based Cryptography
A Novel Hardware-Accelerated Priority Queue for Real-Time Systems
The Next Generation of Exascale-Class Systems: The ExaNeSt Project
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems
Implantable MEMS Pressure Sensors Modelling Tool
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors
Creation of Partial FPGA Configurations at Run-Time
Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code
Protecting an Asynchronous NoC against Transient Channel Faults
Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation
Experimental SEU Impact on Digital Design Implemented in FPGAs
Critical Path Tracing Based Simulation of Transition Delay Faults
Pre-Emptive Garbage Collection for SSD RAID
On Complexity of Internal and External Equivalence Checking
CoNNA - Compressed CNN Hardware Accelerator
A Unified Architecture for BCD and Binary Adder/Subtractor
A Connected Component Labelling algorithm for a multi-pixel per clock cycle video stream
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
Distributed Runtime Computation of Constraints for Multiple Inner Loops
Architectures for Fast Modular Multiplication
Cylindrical Reconvergence Physical Unclonable Function
PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
Evaluation of Fault Tolerant Online Scheduling Algorithms for CubeSats
Test scheduling for embedded systems
Confidaent: Control FLow protection with Instruction and Data Authenticated Encryption
An Efficient FPGA Implementation of Versatile Video Coding Intra Prediction
On the Complexity of Error Detection Functions for Redundant Residue Number Systems
An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices
Acceleration of a CNN-based Heart Sound Segmenter: Implementation on Different Platforms Targeting a Wearable Device
Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
On the Characterization of Jitter in Ring Oscillators using Allan variance for True Random Number Generator Applications
Fast Multiprocessor Scheduling with Fixed Task Binding of Large Scale Industrial Cyber Physical Systems
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application
Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
Novel FPGA-Based Low-Cost Hardware Architecture for the PRESENT Block Cipher
Low Power FPGA Implementations of JH and Fugue Hash Functions
Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing
OOCE: Object-Oriented Communication Engine for SoC Design
Digital RF
Scheduling Persistent and Fully Cooperative Instructions
Active Redundant Hardware Architecture for Increased Reliability in FPGA-Based Nuclear Reactors Critical Systems
A Testbed for Evaluating LTE in High-Speed Trains
Towards the Use of Pairing-Based Cryptography for Resource-Constrained Home Area Networks
15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, Turkey, September 5-8, 2012
The HELICoiD Project: Parallel SVM for Brain Cancer Classification
Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture
Level Assignment for Displaying Combinational Logic
A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic Systems
Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs
Persistence Management Model for Dynamically Reconfigurable Hardware
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code
Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile
Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling
Power and Thermal Fault Effect Exploration Framework for Reader/Smart Card Designs
Design and Implementation of a 50MHZ DXT CoProcessor
An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures
Reliability Analysis and Improvement of FPGA-Based Robot Controller