yusuke1997/dblp-id-title huggingface dataset:
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs
Trends in functional verification: a 2014 industry study
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction
DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Behavioral consistency of C and verilog programs using bounded model checking
Statistical Delay Modeling in Logic Design and Synthesis
Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC
How to determine the necessity for emerging solutions
A General Cache Framework for Efficient Generation of Timing Critical Paths
EM attack sensor: concept, circuit, and design-automation methodology
Multilevel Hypergraph Partitioning: Application in VLSI Domain
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
Who solves the variability problem?
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures
Ambient energy harvesting nonvolatile processors: from circuit to system
Gate Sizing For Cell Library-Based Designs
CMU-CAM system
Networked architecture for hybrid electrical energy storage systems
Simplification of CNC programming for PWB routing
An Effective Guidance Strategy for Abstraction-Guided Simulation
Platform based design: does it answer the entire SoC challenge?
Interprocedural optimizations for improving data cache performance of array-intensive embedded applications
Pushing multiple patterning in sub-10nm: are we ready?
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation
ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility
A survey of transient circuit analysis programs
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory
NN-AdderNet: Nonnegative and Sparse Weight Optimization Towards Ultra-Low Bitwidth AdderNet Quantization and Compression
Proceedings of the SHARE design automation project, DAC '66, New Orleans, Louisiana, USA, May 16-19, 1966
Computer-aided design of nonlinear dynamic systems
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications
Partitioning-based approach to fast on-chip decap budgeting and minimization
CASE: An Integrated Design Environment for Algorithm-Driven Architectures
Towards acceleration of fault simulation using graphics processing units
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells
A New Paradigm for Synthesis of Linear Decompressors
A Multiscale Method for Fast Capacitance Extraction
An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers
Efficient Rectification Signal Validation for Optimal Functional ECO Patch Generation
Designing approximate circuits using clock overgating
HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures
Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback
Minimizing the Routing Cost During Logic Extraction
Designing guardbands for instantaneous aging effects
Seamless multi-radio integration challenges
A technology independent block extraction algorithm
Factoring and Recognition of Read-Once Functions using Cographs and Normality
Cost-effective computer-aided manufacturing of prototype parts
Hierarchical hyperdimensional computing for energy efficient classification
Maintaining integrity in complex shape definitions
Buffer Insertion for Noise and Delay Optimization
Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms
Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking
Coupling-Driven Bus Design for Low-Power Application-Specific Systems
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors
A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation
MIME: adapting a single neural network for multi-task inference with memory-efficient dynamic pruning
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Measurements of a VLSI design
ASSURE: Automated Design for Dependability
The VLSI design automation assistant: what's in a knowledge base
A delay test system for high speed logic LSI's
A spiking neuromorphic design with resistive crossbar
HEAT: Hierarchical Energy Analysis Tool
A novel approach for flexible and consistent ADL-driven ASIP design
XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method
SHARPS: A hierarchical layout system for VLSI
A tutorial introduction to the electronic design interchange format (tutorial session)
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA
Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification
Developments in logic network path delay analysis
ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression
CAD Directions for High Performance Asynchronous Circuits
Automatic generation of microprocessor test programs
Specification Partitioning for System Design
An O(n) Algorithm for Transistor Stacking with Performance Constraints
Rule agnostic routing by using design fabrics
DmTSAR-ILP: Allocating a Unified Domain Platform for Streaming Applications
Technology-independent circuit layout
System simulation from operational data
(Bio)-behavioral CAD
Enabling On-Tiny-Device Model Personalization via Gradient Condensing and Alternant Partial Update
On-Chip Measurements Complementary to Design Flow for Integrity in SoCs
Power benefit study for ultra-high density transistor-level monolithic 3D ICs
State-based power analysis for systems-on-chip
A Context Mechanism to Control Sharing in a Design Database
STARBIST: Scan Autocorrelated Random Pattern Generation
The Unwritten Contract of Cloud-based Elastic Solid-State Drives
Functional Verification of MOS Circuits
An Object Oriented Approach to CAD Tool Control within a Design Framework
LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM
Finite State Machine Decomposition For Low Power
Symbolic Analysis of Dataflow Applications Mapped onto Shared Heterogeneous Resources
Cost value of design automation
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks
Interconnects in the Third Dimension: Design Challenges for 3D ICs
Design for Testability for Path Delay faults in Sequential Circuits
Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue
A non-parametric approach for dynamic range estimation of nonlinear systems
Transmission gate modeling in an existing three-value simulator
High Performance Graph Convolutional Networks with Applications in Testability Analysis
IBM FSD VLSI chip design methodology
Fault-tolerant Routing for On-chip Network Without Using Virtual Channels
Cell compilation with constraints
How to make efficient communication, collaboration, and optimization from system to chip
Basic Gate Implementation of Speed-Independent Circuits
Critical Path Selection for Performance Optimization
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs
An Intermediate Representation for Behavioral Synthesis
Area-efficient pipelining for FPGA-targeted high-level synthesis
Fast methods for extraction and sparsification of substrate coupling
Power grid verification using node and branch dominance
Automated Specification and Verification of Functional Safety in Heavy-Vehicles: the VeriSpec Approach
Trace-driven HW/SW cosimulation using virtual synchronization technique
Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator
Extracting design information from natural language specifications
Defining and implementing a multilevel design representation with simulation applications
Relax: A new circuit for large scale MOS integrated circuits
A New Viewpoint on Two-Level Logic Minimization
Formal description of processes - the first step in design automation
Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems
Minimum-energy state guided physical design for nanomagnet logic
Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce
Floor planning systems (panel session)
TrafficHD: Efficient Hyperdimensional Computing for Real-Time Network Traffic Analytics
Effectiveness of heuristics measures for automatic test pattern generation
Structure-aware placement for datapath-intensive circuit designs
On systematic illegal state identification for pseudo-functional testing
Partnering with EDA Vendors: Tips, Techniques, and the Role of Standards
A formal method for the specification, analysis, and design of register-transfer level digital logic
Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited
Deepsecure: scalable provably-secure deep learning
A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries
GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs
Proceedings of the 7th Design Automation Workshop, DAC '70, San Francisco, California, USA, June 22-25, 1970
Test challenges for deep sub-micron technologies
A high-resolution side-channel attack on last-level cache
Communication latency aware low power NoC synthesis
A standard test language - GOAL (Ground Operations Aerospace Language)
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
On diagnosis of pattern-dependent delay faults
Routing L-Shaped Channels in Nonslicing-Structure Placement
OmniBoost: Boosting Throughput of Heterogeneous Embedded Devices under Multi-DNN Workload
RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration
A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices
BDS: a BDD-based logic optimization system
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead
Flexible ASIC: shared masking for multiple media processors
IMAGE: An interactive computer system for multi-constrained spatial synthesis
Age-based PCM wear leveling with nearly zero search cost
An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis
A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures
Coverage Learned Targeted Validation for Incremental HW Changes
Synthesis of Application Specific Programmable Processors
MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers
Integrated computer aided design, documentation and manufacturing system for PCB electronics
Designing critical systems with iterative automated safety analysis
Blocking unsafe behaviors in control systems through static and dynamic policy enforcement
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map
Efficient model order reduction including skin effect
Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals
MONSTR: A Complete Thermal Simulator of Electronic Systems
Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization
Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation
Design exploration of energy-performance trade-offs for wireless sensor networks
Enhancing 3-D Random Walk Capacitance Solver with Analytic Surface Green's Functions of Transition Cubes
Adoption of OPC and the Impact on Design and Layout
Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics
An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits
Verification Coverage: When is Enough, Enough?
Parallel circuit simulation using the direct method on a heterogeneous cloud
An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip
From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy Trees
Timed pattern generation for noise-on-delay calculation
A combined feasibility and performance macromodel for analog circuits
QoS-aware stochastic power management for many-cores
Bottom Up Synthesis Based on Fuzzy Schedules
MASKER: Adaptive Mobile Security Enhancement against Automatic Speech Recognition in Eavesdropping
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits
Stacking SRAM banks for ultra low power standby mode operation
Hierarchical power distribution and power management scheme for a single chip mobile processor
Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms
An iterative technique for printed wire routing
Minimum Length Synchronizing Sequences of Finite State Machine
A practical and efficient method for compare-point matching
Incorrect systems: it's not the problem, it's the solution
Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited
Hierarchical analysis of power distribution networks
Testability Solutions: Who Really Wants Them? (Panel Abstract)
PTStore: Lightweight Architectural Support for Page Table Isolation
Cross-layer dependency analysis with timing dependence graphs
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse
Row Based Dual-VDD Island Generation and Placement
Standard cell routing via boolean satisfiability
Achieving maximum performance: a method for the verification of interlocked pipeline control logic
FT-MUX: A Fault-Tolerant Microfluidic Multiplexer Design
A Time Abstraction Method for Efficient Verification of Communicating Systems
Pareto sampling: choosing the right weights by derivative pursuit
Exploring technology alternatives for nano-scale FPGA interconnects
On Routability Prediction for Field-Programmable Gate Arrays
Experiments with the SLIM Circuit Compactor
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture
LASSIE: Structure to Layout for Behavioral Synthesis Tools
Shatter: efficient symmetry-breaking for boolean satisfiability
Customized Instruction-Sets for Embedded Processors
CUDA Quantum: The Platform for Integrated Quantum-Classical Computing
Late Breaking Results: Evaluation of Human Action Quality with Linear Recurrent Units and Graph Attention Networks on Embedded Systems
Ontology-guided Conceptual Analysis of Design Specifications
Network Partitioning into Tree Hierarchies
High-level synthesis for micro-electrode-dot-array digital microfluidic biochips
Lightning Talk: A Perspective on Neuromorphic Computing
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems
Shared Resource Access Attributes for High-Level Contention Models
Hardware/software IP protection
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems
Faster and Stronger Lossless Compression with Optimized Autoregressive Framework
Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation
What Is a Design Automation Framework, Anyway? (panel)
RISPP: Rotating Instruction Set Processing Platform
An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator
Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging
Complexity theory and design automation
Self-correcting STTRAM under magnetic field attacks
Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC's
New Predictor-Based Attacks in Processors
A timing-driven module-based chip design flow
Interfacing Incompatible Protocols Using Interface Process Generation
A Dynamic and Efficient Representation of Building-Block Layout
Power reduction via separate synthesis and physical libraries
Accelerating neuromorphic vision algorithms for recognition
Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI
Interconnection fabric design for tracing signals in post-silicon validation
EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at Edge
ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs
SysCOLA: a framework for co-development of automotive software and system platform
Concurrent Pin Access Optimization for Unidirectional Routing
Verification testing
Memory Segmentation to Exploit Sleep Mode Operation
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits
FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDA
FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive Parallelism
Automated building design
Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism
A symbolic-interconnect router for custom IC design
Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
Waveform-based performance analysis of RISC-V processors: late breaking results
ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems
Mixed-level fault coverage estimation
Criticality-dependency-aware timing characterization and analysis
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping
SOI Digital CMOS VLSI - a Design Perspective
Orchestrated Scheduling and Partitioning for Improved Address Translation in GPUs
An accurate semi-analytical framework for full-chip TSV-induced stress modeling
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC
Diagnosis of transition fault clusters
A parallel bit map processor architecture for DA algorithms
LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices
A computer simulation approach to elevator system design
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
The Role of VHDL in the MCC CAD System
Leakage power reduction using stress-enhanced layouts
G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis
Formal verification - prove it or pitch it
Automatic generation of self-test programs - a new feature of the MIMOLA design system
Towards Cost-Effective Real-Time High-Throughput End Station Design for Time-Sensitive Networking (TSN)
Power Estimation of Cell-Based CMOS Circuits
Improving Symbolic Traversals by Means of Activity Profiles
Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools
Prerouting analysis programs
MAPS: an integrated framework for MPSoC application parallelization
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans
TailCut: improving performance and lifetime of SSDs using pattern-aware state encoding
RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Quality-driven synthesis of embedded multi-mode control systems
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis
Direct matrix solution of linear complexity for surface integral-equation based impedance extraction of high bandwidth interconnects
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers
ORACLE: optimization with recourse of analog circuits including layout extraction
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick
MetaCores: Design and Optimization Techniques
Data Flow Partitioning for Clock Period and Latency Minimization
Analyzing Parallel Real-Time Tasks Implemented with Thread Pools
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits
ASIP Instruction Encoding for Energy and Area Reduction
Cost effective layout digitizing and mask pen plotting of custom microelectronic devices
Architectural Partitioning for System Level Design
OFTL: ordering-aware FTL for maximizing performance of the journaling file system
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling
Speedpath prediction based on learning from a small set of examples
ISIS: A System for Performance Driven Resource Sharing
An SDRAM-aware router for Networks-on-Chip
Line-End Shortening is Not Always a Failure
Practical automated design of LSI for large computers
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits
Designing time partitions for real-time hypervisor with sufficient temporal independence
Hardware-Software Co-Design and ESDA
VDHL Development System and Coding Standard
An evaluation of the N. mPc design environment
An implementation of a saturated zone multi-layer printed circuit board router
Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability
Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions
GraphRing: an HMC-ring based graph processing framework with optimized data movement
Early Power Exploration - A World Wide Web Application
Dynamically adaptive scrubbing mechanism for improved reliability in reconfigurable embedded systems
Fast multipole method on GPU: tackling 3-D capacitance extraction on massively parallel SIMD platforms
Analog and RF circuit macromodels for system-level analysis
Predicting Area-Time Tradeoffs for Pipelined Design
Rethinking AIG Resynthesis in Parallel
A false-path aware formal static timing analyzer considering simultaneous input transitions
Columba: co-layout synthesis for continuous-flow microfluidic biochips
Timing driven power gating
Watermarking while preserving the critical path
Sequential Circuit Test Generation in a Genetic Algorithm Framework
The interchange algorithms for circuit placement problems
Diagrammatic function description of microprocessor and data-flow processor