yusuke1997/dblp-id-title huggingface dataset:
Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine
Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits
High Throughput CNN Inference and Training with In-Cache Computation
Associative and data processing Mbit-DRAM
Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage Systems
A lightweight run-time scheduler for multitasking multicore stream applications
Jenga: Efficient Fault Tolerance for Stacked DRAM
A physical unclonable function based on setup time violation
Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
A pipelined microprocessor for logic programming languages
A highly parallel processor with an instruction set including relational algebra
Circuit design techniques for a gigahertz integer microprocessor
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles
Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination
Tailoring CUTLASS GEMM using Supervised Learning
Generic ASIC architecture for digital signal processing
Threshold Voltage Tuning Technique for Leakage Power Recovery
Software Metrics for Object-Oriented Designs
PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time Systems
PACA: A Page Type Aware Read Cache Scheme in QLC Flash-based SSDs
Combining cluster sampling with single pass methods for efficient sampling regimen design
The Astronautics ZS-1 processor
Compositional Software Synthesis of Communicating Processes
Routable Technologie Mapping for LUT FPGAs
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits
Formal Hardware Verification based on Signal Correlation Properties
An IEEE 1149.1 Compliant Testability Architecture with Internal Scan
Sleipnir - An Instruction-Level Simulator Generator
A readback based general debugging framework for soft-core processors
Multi-Stage Dynamic Cuckoo Filters
Energy-aware and quality-scalable data placement and retrieval for disks in video server environments
Timing analysis of combinational circuits containing complex gates
FDRAM: DRAM architecture flexible in successive row and column accesses
ReMAP: Reuse and memory access cost aware eviction policy for last level cache management
Keynote talk I: Ending the Tyranny of Amdahl's Law
Area & Time Limitations of FPGA-based Virtual Hardware
Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation
Energy-aware scheduling of conditional task graphs with deadlines on MPSoCs
Exposing vulnerabilities of untrusted computing platforms
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design
Fast Capacitance Extraction of General Three-Dimensional Structures
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
SSM-RDU: A Reconfigurable Dataflow Unit for Long-Sequence State-Space Models
Dark silicon aware power management for manycore systems under dynamic workloads
DDLM: Demand-Aware Dynamic Link Width Management for Energy-Efficient CXL Memory
FloatMax: An Efficient Accelerator for Transformer-Based Models Exploiting Tensor-Wise Adaptive Floating-Point Quantization
PUF-RLA: A PUF-Based Reliable and Lightweight Authentication Protocol Employing Binary String Shuffling
Heart: a Scalable, High-performance ART for Persistent Memory
Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism
Interface design for synthesized structural hybrid microarchitectural simulators
Enhanced symbolic simulation of a round-robin arbiter
Combining technology mapping with post-placement resynthesis for performance optimization
Incorporating timing constraints in the efficient memory model for symbolic ternary simulation
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits
Dual Dictionary Compression for the Last Level Cache
OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite
Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks
An exact solution to the minimum size test pattern problem
Hippogriff: Efficiently moving data in heterogeneous computing systems
BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed!
A Soft Error Monitor Using Switching Current Detection
A cost function based optimization technique for scheduling in data path synthesis
At-Speed Logic BIST Architecture for Multi-Clock Designs
PMA: A Persistent Memory Allocator with High Efficiency and Crash Consistency Guarantee
Cost-Aware TVM (CAT) Tensorization for Modern Deep Learning Accelerators
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
Towards a VLSI packaging design support environment (PDSE); concepts and implementation
Evaluation of high speed LAN protocols as multimedia carriers
Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels
Design and Synthesis of Self-Checking VLSI Circuits and Systems
Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors
Load-Balancing Branch Target Cache and Prefetch Buffer
Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips
Model Synthesis for Communication Traces of System Designs
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems
Adaptive Write Interference Management with Efficient Mapping for Shingled Recording Disks
Data Cache Design Considerations for the Itanium ® 2 Processor
Partitioning Sequential Circuits for Logic Optimization
Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994
Reducing the Cost of Test Pattern Generation by Information Reusing
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction
Precomputation-based Guarding for Dynamic and Leakage Power Reduction
An FPGA-Based Coprocessor for Hash Unit Acceleration
Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration
On-chip bidirectional wiring for heavily pipelined systems using network coding
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques
Mesh Routing Topologies for Multi-FPGA Systems
Analysis of on-chip interconnection network interface reliability in multicore systems
Fault Tolerant VLSI Design with Functional Block Redundancy
HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing from Embedded to High-Performance Systems
Novel Simulation of Deep-Submicron MOSFET Circuits
Independent Test Sequence Compaction through Integer Programming
N-way ring and square arbiters
Locating faults in application-dependent interconnects of SRAM based FPGAs
Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks
Profiling for input predictable threads
VLSI asynchronous sequential circuit design
PRISC Software Acceleration Techniques
VLSI Design and Verification of the Imagine Processor
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current
MNHOKA - PPA Efficient M-Term Non-Homogeneous Hybrid Overlap-free Karatsuba Multiplier for GF (2 n ) Polynomial Multiplier
Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach
Chain-Based Fixed-Priority Scheduling of Loosely-Dependent Tasks
WiNN: Wireless Interconnect based Neural Network Accelerator
Task model suitable for dynamic load balancing of real-time applications in NoC-based MPSoCs
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD
Delay-Verifiability of Combinational Circuits Based on Primitive Faults
CalmRISC TM : A Low Power Microcontroller with Efficient Coprocessor Interface
Defining Wakeup Width for Efficient Dynamic Scheduling
Addressing Multicore Communication Challenges Using NoC Technology
Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapid Prototyping Framework
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
Persimmon: an append-only ZNS-first filesystem
Hybrid-Rewrite: A Rewriting Framework for Hybrid Deduplication and Delta Compression
Static Energy Reduction Techniques for Microprocessor Caches
SPF: Selective Pipeline Flush
MindCrypt: The Brain as a Random Number Generator for SoC-Based Brain-Computer Interfaces
Protocol Verification as a Hardware Design Aid
A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations
A fast, fully verifiable, and hardware predictable ASIC design methodology
Interconnect-centric Array Architectures for Minimum SRAM Access Time
CADedup: High-performance Consistency-aware Deduplication Based on Persistent Memory
×86 computer architecture simulators: A comparative study
HaLSM: A Hotspot-aware LSM-tree based Key-Value Storage Engine
A High-Frequency Custom CMOS S/390 Microprocessor
Behavioral Synthesis for low Power
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs
Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization
Repo: Proactive Swapping Exploiting Loop Patterns in Modern Applications
Full Stack Parallel Online Hyperdimensional Regression on FPGA
Parallel LU factorization for circuit simulation on an MIMD computer
Incremental gate sizing for late process changes
A Robust Solution to the Timing Convergence Problem in High-Performance Design
Checking Formal Specifications under Simulation
A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis
In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips
Embedded Operating System Energy Analysis and Macro-Modeling
Efficient Testing of RF MIMO Transceivers Used in WLAN Applications
A New Non-Restoring Square Root Algorithm and its VLSI Implementation
An octagonal geometry compactor
Locality-aware Speculative Cache for Fast Partial Updates in Erasure-Coded Cloud Clusters
H2ORAM: Low Response Latency Optimized ORAM for Hybrid Memory Systems
Architectural Contracts for Safe Speculation
Pseudo pin assignment for single-layer over-the-cell routing
Formal verification of cache systems using refinement relations
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow
The design of the VLSI image-generator ZaP
Synthesis of testable PLAs using adaptive heuristics for efficiency
Declarative Synthesis and Multi-Objective Optimization of Stripboard Circuit Layouts Using Answer Set Programming
2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013
Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search
HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted Prefetching
An output-shared buffer ATM switch
Asymptotic Limits of Video Signal Processing Architectures
Optimized local control strategy for voice-based interaction-tracking badges for social applications
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture
Direct synthesis of mapping circuits
The complexity of adaptive annealing
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems
TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches
Estimation of area and performance overheads for testable VLSI circuits
Improving CMOS Speed at Low Supply Voltages
Verifying pipelined hardware using symbolic logic simulation
Implementing hardware Trojans: Experiences from a hardware Trojan challenge
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz
Integrated design and test synthesis
MH-SpGEMM: Efficient Sparse General Matrix-Matrix Multiplication on Modern GPUs via Masking and Hashing Cooperative Optimization
K8sES: Optimizing Kubernetes with Enhanced Storage Service-Level Objectives
Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989
The Formal Definition of a Synchronous Hardware-Description Language in Higher Order Logic
Dual Global Flow
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling
Delay test quality maximization through process-aware selection of test set size
Seqver : A Sequential Equivalence Verifier for Hardware Designs
Cache Optimization for Memory-Resident Decision Support Commercial Workloads
Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture
Operation Method in Fuzzy Set Operation Processor
Design of robustly testable static CMOS parity trees derived from binary decision diagrams
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation
Integrating Cyber-Attack Defense Techniques into Real-Time Cyber-Physical Systems
A high performance router with dynamic buffer allocation for on-chip interconnect networks
A New O(n log n) Scheduling Heuristic for Parallel Decomposition of Sparce Matrices
Design and Performance Evaluation of a Cache Assist to implement Selective Caching
Fast low-power shared division and square-root architecture
Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips
PrSpMV: An Efficient Predictable Kernel for SpMV
On Relationship Between ITE and BDD
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture
An energy efficient column-major backend for FPGA SpMV accelerators
DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time
Iterative built-in testing and tuning of mixed-signal/RF systems
High Speed Video Board as a Case Study for Hardware-Software Co-Design
VEGA: a verification tool based on genetic algorithms
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
68040 memory modules and bus controller
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits
Write Buffer Design for On-Chip Cache
Code density concerns for new architectures
Incremental methods for FSM traversal
Bit-Splitting for Testability Enhancement in Scan-Based Design
ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories
Instruction reorganization for a variable-length pipelined microprocessor
EPNR: an energy-efficient automated layout synthesis package
Binary decision diagrams on network of workstation
VLSI Implementation of a New Block Cipher
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
A simple pipelined squaring circuit for DSP
Efficient Logic Optimization Using Regularity Extraction
A temperature-aware synthesis approach for simultaneous delay and leakage optimization
Pipelined computation of LNS addition/subtraction with very small lookup tables
POS: A Popularity-based Online Scaling scheme for RAID-structured storage systems
Energy Prediction for Cache Tuning in Embedded Systems
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan
An Application Specific Processor for a Multi-System Navigation Receiver
Methods for calculating coupling noise in early design: a comparative analysis
Short Destabilizing Paths in Timing Verification
SOP based logic synthesis for memristive IMPLY stateful logic
Side-channel power analysis of a GPU AES implementation
PCC: An End-to-End Compilation Framework for Neural Networks on Photonic-Electronic Accelerators
A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators
A pair selection algorithm for robust RO-PUF against environmental variations and aging
Design for routability of a high-density gate array
Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits
Hardware-based Pointer Data Prefetcher
Practical design assistance at register transfer level using a data path verifier
Crosstalk Noise Estimation for Generic RC Trees
Application Specific Instruction set processor specialized for block motion estimation
Terascale Computing and BlueGene
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
HyperMetric: Robust Hyperdimensional Computing on Error-prone Memories using Metric Learning
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
More Moore landscape for system readiness - ITRS2.0 requirements
Adaptive synchronization
Floating Point Square Root under HUB Format
Training Neural Networks with Low Precision Dynamic Fixed-Point
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations
LBZ: A Lightweight Block Device for Supporting F2FS on ZNS SSD
An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications
A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits
Software Timing Analysis for Complex Hardware with Survivability and Risk Analysis
Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems
Specifying System Behavior in CPA
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
A dynamic cache sub-block design to reduce false sharing
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy
Adaptive techniques for leakage power management in L2 cache peripheral circuits
Transformer-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DTQN
Design space exploration of an NVM-based memory hierarchy
MARVLE: A VLSI Chip for Variable Length Encoding and Decoding
The heterogeneous block architecture
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
VLSI Design of Modulo Adders/Subtractors
Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking
On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors
A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems
Media Processing Applications on the Imagine Stream Processor
Mutable Functional Units and Their Applications on Microprocessors
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan
Leveraging torus topology with deadlock recovery for cost-efficient on-chip network
Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write Amplification
A Co-Design Framework for Graph Processing on CPU-GPU Heterogeneous Platforms
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis
Empirical Guide to Use of Persistent Memory for Large-Scale In-Memory Graph Analysis
Register binding guided by the size of variables
An Improved Approach for AlternativeWires Identi.cation
Optimization of back pressure and throughput for latency insensitive systems
Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing
Flow-Based Cell Moving Algorithm for Desired Cell Distribution
Yesterday and Tomorrow: A View on Progress in Computer Design
ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process Learning
A linear time algorithm for optimal CMOS functional cell layouts
NVAX and NVAX + Single-Chip CMOS VAX Microprocessors
QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin
Design of a Self-Testing Checker for Borden Code
Asynchronous Scan-Latch controller for Low Area Overhead DFT
Concurrent Error Detection in Array Dividers by Alternating Input Data
A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits
Structural Detection of Symmetries in Boolean Functions
Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation
NatSep: Little-to-No Overhead Data Separation for Log-Structured Storage Using Native Information
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework
Row buffer locality aware caching policies for hybrid memories
Pin assignment for improved performance in standard cell design
On Valid Clocking for Combinational Circuits
An efficient approach to pseudo-exhaustive test generation for BIST design
Logic minimization for factored forms
A pre-search assisted ILP approach to analog integrated circuit routing
A novel SoC architecture on FPGA for ultra fast face detection
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Resonance-Based Power-Efficient Pulse Generator Design with Corresponding Distribution Network
Automatic classification of node types in switch-level descriptions
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
Out-of-order retirement of instructions in sequentially consistent multiprocessors
SuperCDC: A Hybrid Design of High-Performance Content-Defined Chunking for Fast Deduplication
UQ-VarQA: Benchmarking and Characterizing NISQ Computers Through Uncertainty Quantification of Variational Quantum Algorithms
Memos: A full hierarchy hybrid memory management framework
On-chip high performance signaling using passive compensation
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter
Automatic generation of control circuits in pipelined DSP architectures
Cache Array Architecture Optimization at Deep Submicron Technologies
A multicore vacation scheme for thermal-aware packet processing
A Thread-Aware Adaptive Data Prefetcher
Decomposition Attack on Structural Logic Locking of Reversible Circuits
On-Line Integrity Monitoring of Microprocessor Control Logic
A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage
Design issues for distributed shared-memory systems
Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem
State Assignment for Power and Area Minimization
A high speed static CMOS PLA architecture
CSM-NN: Current Source Model Based Logic Circuit Simulation - A Neural Network Approach
Shift-aware racetrack memory
Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor
MIST: Efficient Mixed-Precision Preconditioning Through Iterative Sparse- Triangular Solver Design
An Efficient External-Memory Implementation of Region Query with Application to Area Routing
Performance and Reliability Verification of C6201/C6701 Digital Signal Processors
PRATHAM: A power delivery-aware and thermal-aware mapping framework for parallel embedded applications on 3D MPSoCs
43rd IEEE International Conference on Computer Design, ICCD 2025, Richardson, TX, USA, November 10-12, 2025
Power/ground supply network optimization for power-gating
Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications
Functional Fmax test-time reduction using novel DFTs for circuit initialization
Are Today's Verification Tools Able to Handle Current Design Challenges?
Isolation-based decorrelation of stochastic circuits
The system design of a Windows CE ARM based micro-controller
High Performance Packaged Electronics for the IBM ES9000 TM Mainframe
Cluster-Oriented Scheduling in Pipelined Data Path Syntesis
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing