yusuke1997/dblp-id-title huggingface dataset:
Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization
VAE-HDC: Efficient and Secure Hyper-dimensional Encoder Leveraging Variation Analog Entropy
Verification of configurable processor cores
Towards scalable system-level reliability analysis
A Holistic Functionalization Approach to Optimizing Imperative Tensor Programs in Deep Learning
Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis
Enabling Data-Deduplication-Assisted Data Relocation for Interlaced Magnetic Recording
A Unified Data Exchange Environment Based on EDIF
ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation
Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse
VTIcompose - a powerful graphical chip assembly tool
A Parallel Branch and Bound Algorithm for Test Generation
PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis
Transfer Learning-Based Microfluidic Design System for Concentration Generation∗
Hierarchical Design Based on a Calculus of Nets
QuiltNet: efficient deep learning inference on multi-chip accelerators using model partitioning
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor
BPUFuzzer: Effective Fuzz Testing for Branching Transient Execution Vulnerabilities of RISC-V CPU
Computervision's direction in workstation technology
VLSI test expertise system using a control flow model
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
Accurate simulation of high speed computer logic
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog
3-D semiconductor's: more from Moore
Fitting Formal Methods into the Design Cycle
An implementation of a state assignment heuristic
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
An Efficient Zero-Skew Routing Algorithm
Memory-efficient training of binarized neural networks on the edge
Towards Aging-Induced Approximations
Energy reduction techniques for multimedia applications with tolerance to deadline misses
Generation of layouts from MOS circuit schematics: a graph theoretic approach
Constraint improvements for MILP-based hardware synthesis
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
Incremental-in-time Algorithm for Digital Simulation
Present and future on P.C.B. layout design automation system at SIT-Siemens
Fortifying analog models with equivalence checking and coverage analysis
Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing
Detecting bridging and stuck-at faults at input and output pins of standard digital components
SpaHet: A Software/Hardware Co-design for Accelerating Heterogeneous-Sparsity based Sparse Matrix Multiplication
Automatic invariant strengthening to prove properties in bounded model checking
Representation of Function Variants for Embedded System Optimization and Synthesis
Task scheduling and voltage selection for energy minimization
RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming
Improving Virtual-Grid Compaction Through Grouping
Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems
Efficient timing closure without timing driven placement and routing
Low voltage swing logic circuits for a Pentium 4 processor integer core
Schedulability-driven performance analysis of multiple mode embedded real-time systems
Behavioral Fault Simulation in VHDL
Winograd convolution: a perspective from fault tolerance
Efficient Final Placement Based on Nets-as-Points
Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias
The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint
UNIGRAFIX
Technology Retargeting for IC Layout
Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach
Functional testing A user looks at logic simulation
A Mixed-Signal Photonic SRAM-based High-Speed Energy-Efficient Photonic Tensor Core with Novel Electro-Optic ADC
Using satisfiability in application-dependent testing of FPGA interconnects
Tradeoffs between date oxide leakage and delay for dual T ox circuits
AdaGL: Adaptive Learning for Agile Distributed Training of Gigantic GNNs
SCEMIT: a systemc error and mutation injection tool
Rigorous model-based design & verification flow for in-vehicle software
An automated micro measurement system for integrated circuit masks
Stealing Your Data from Compressed Machine Learning Models
Efficient ILT via Multigrid-Schwartz Method
Built-In Self-Test for Signal Integrity
Placement and routing program for master-slice LSI's
Design and verification for transportation system security
DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing
Concurrent Analysis Techniques for Data Path Timing Optimization
Stannis: Low-Power Acceleration of DNN Training Using Computational Storage Devices
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs
Metronome: operating system level performance management via self-adaptive computing
Demand Driven Simulation: BACKSIM
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
QOC: quantum on-chip training with parameter shift and gradient pruning
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU
Efficient Multi-Grained Wear Leveling for Inodes of Persistent Memory File Systems
Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective
An Efficient Compactor for 45° Layout
Synthesis Using Path-Based scheduling: algorithms and Exercises
A combinatorial programming approach to the joint optimization of land use and transportation
A Computer-Aided Design data base
Zeus: A hardware description language for VLSI
3D CNN Acceleration on FPGA using Hardware-Aware Pruning
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems
The State of CAD and VLSI in Russia
DyREM: Dynamically Mitigating Quantum Readout Error with Embedded Accelerator
Microelectronics and printed circuits: Problems and their solutions
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits
LHNN: lattice hypergraph neural network for VLSI congestion prediction
PAMS: An Expert System for Parameterized Module Synthesis
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators
Megatrends and EDA 2017
Logic Synthesis for Programmable Gate Arrays
CDA-GNN: A Chain-driven Accelerator for Efficient Asynchronous Graph Neural Network
DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory Architecture
Rapid and low-cost context-switch through embedded processor customization for real-time and control applications
Reliability modeling and management in dynamic microprocessor-based systems
A Memory-Conscious Code Parallelization Scheme
Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis
Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units
Stitch-aware routing for multiple e-beam lithography
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs
Computing with Hybrid CMOS/STO Circuits
Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery
Phoenix system overview
Present and future in design automation systems
Structural search for RTL with predicate learning
Fundamentals of parallel logic simulation
Circuit Learning for Logic Regression on High Dimensional Boolean Space
Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives
Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract)
High-Performance Routing Trees With Identified Critical Sinks
SWAP - a programming system for automatic simulation, wiring and placement of logical equations
Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor
Master slice LSI Computer Aided Design system
Hierarchical top-down layout design method for VLSI chip
DTM: dynamic tone mapping for backlight scaling
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations
Statistical gate delay model considering multiple input switching
Partitioned Scheduling and Parallelism Assignment for Real-Time DNN Inference Tasks on Multi-TPU
John Hancock's experience with productivity techniques
Invited - Heterogeneous datacenters: options and opportunities
Optimal Wire-Sizing Function with Fringing Capacitance Consideration
State of the art and trends in Design Automation in Italy
Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT
Resistance Extraction using a Routing Algorithm
Double patterning lithography friendly detailed routing with redundant via consideration
Late Breaking Results: Physical Adversarial Attacks of Diffractive Deep Neural Networks
An Automatic Test Generation Algorithm for Hardware Description Languages
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
Networks on Chips: from research to products
SoftSNN: low-cost fault tolerance for spiking neural network accelerators under soft errors
Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming
Boolean Matching Reversible Circuits: Algorithm and Complexity
A novel framework for passive macro-modeling
The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013
Hardware support for automatic routing
Alembic: An Efficient Algorithm for CNF Preprocessing
Design and integration challenges of building security hardware IP
Enabling system-level modeling of variation-induced faults in networks-on-chips
Digital System Simulation: Methodologies and Examples
SCA: A Secure CNN Accelerator for Both Training and Inference
Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator
Adversarial Attack on Microarchitectural Events based Malware Detectors
Graph Representation Learning for Microarchitecture Design Space Exploration
Integrating Design Information for IC Diagnosis
The integration of an advanced gate array router into a fully automated design system
Global resource sharing for synthesis of control data flow graphs on FPGAs
Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange
Recurrence Equations and the Optimization of Synchronous Logic Circuits
Simultaneous multithreading support in embedded distributed memory MPSoCs
Deep Learning Multi-Channel Fusion Attack Against Side-Channel Protected Hardware
An optimal algorithm for layer assignment of bus escape routing on PCBs
PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra
PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays
Design and analysis of electronic circuits
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications
DFT for controlled-impedance I/O buffers
Multilevel Synthesis Minimizing the Routing Factor
Beyond innovation: dealing with the risks and complexity of processor design in 22nm
Impeccable Circuits II
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements
A behavioral modeling system for cell compilers
Parallel Placement on Reduced Array Architecture
Software engineering applied to computer-aided design (CAD) software development
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification
Deriving a simulation input generator and a coverage metric from a formal specification
Achieving defect-free multilevel 3D flash memories with one-shot program design
Defending against Adversarial Patches using Dimensionality Reduction
A Reconfigurable Logic Machine for Fast Event-Driven Simulation
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
VLSI Design Synthesis with Testability
PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines
Optimizing stream program performance on CGRA-based systems
Timing-driven optimization using lookahead logic circuits
Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989
RegVault: hardware assisted selective data randomization for operating system kernels
Addressing design margins through error-tolerant circuits
Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations
Automated rip-up and reroute techniques
PEARL: an expert system for power supply layout
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation
Analog placement based on hierarchical module clustering
Challenges in gate level modeling for delay and SI at 65nm and below
Static dataflow with access patterns: semantics and analysis
Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout
Energy-efficient communication protocols
Optimization and Resynthesis of Complex Data-Paths
Position statement - tools for design automation from a university point of view
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction
Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract)
Constrained Register Allocation in Bus Architectures
A "gridless" Variable-Width Channel Router for Marco Cell Design
Invited: Automatic Hardware/Software Design for High-Speed Autonomous Unmanned Aerial Vehicles Guided by a Flight Model
A generic representation of CCSL time constraints for UML/MARTE models
Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time
UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs
Computer aided design of industrial control systems
DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow Accelerators
Sehwa: a program for synthesis of pipelines
BERRY: Bit Error Robustness for Energy-Efficient Reinforcement Learning-Based Autonomous Systems
A linear algorithm to find a rectangular dual of a planar triangulated graph
Bayesian Inference Based Robust Computing on Memristor Crossbar
Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis
HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Software Environment for a Multiprocessor DSP
Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems
Lift: Exploiting Hybrid Stacked Memory for Energy-Efficient Processing of Graph Convolutional Networks
Late Breaking Results: LDFSM: A Low-Cost Bit-Stream Generator for Low-Discrepancy Stochastic Computing
A new uncertainty budgeting based method for robust analog/mixed-signal design
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems
Run-time adaptive energy-aware motion and disparity estimation in multiview video coding
DuraCache: a durable SSD cache using MLC NAND flash
IPDA: Interconnect Performance Design Assistant
Emerging companies - acquiring minds want to know (panel session)
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks
The Simulation and Design of Integrated Inductors
Comparison of CMOS PLA and polycell representations of control logic
A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber
High-performance timing simulation of embedded software
GRAPHSPY: Fused Program Semantic Embedding through Graph Neural Networks for Memory Efficiency
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography
A model-driven approach to warp/thread-block level GPU cache bypassing
Parameter sensitivity studies for internal combustion engine control and design purposes
Silicon carrier for computer systems
Efficient Recycling Subspace Truncation Method for Periodic Small-Signal Analysis
Boolean Comparison by Simulation
Hardware synthesis of recursive functions through partial stream rewriting
Performance driven multi-level and multiway partitioning with retiming
Don't open row: rethinking row buffer policy for improving performance of non-volatile memories
Non-iterative switching window computation for delay-noise
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Improving mobile gaming performance through cooperative CPU-GPU thermal management
A new routing algorithm for two-sided boards with floating vias
Inducing local timing fault through EM injection
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization
Virtual Platforms and Timing Analysis: Status, Challenges and Future Directions
A State Traversal Algorithm Using a State Covariance Matrix
Detailed Placement for Two-Dimensional Directed Self-Assembly Technology
Partial Scan with Retiming
ICAD/PCB: Integrated computer aided design system for printed circuit boards
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST
Fast Statistical Timing Analysis By Probabilistic Event Propagation
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking
Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited
A perspective view of the MODCON system
EDA: this is serious business
Design of a 17-million gate network processor using a design factory
Closing the gap between analog and digital
Human computation
Emerging Trends in Multi-Accelerator and Distributed System for ML: Devices, Architectures, Tools and Applications
A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited
Fort-NoCs: Mitigating the Threat of a Compromised NoC
Plug-in timing models for an abstract timing verifier
A VLSI design methodology based on parametric macro cells
PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN Accelerators
Symbolic noise analysis approach to computational hardware optimization
Low-cost sequential ATPG with clock-control DFT
Post-placement voltage island generation for timing-speculative circuits
TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks
Binary Decision Diagrams: From abstract representations to physical implementations
Late Breaking Results: Extracting QNNs from NISQ Computers via Ensemble Learning
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers
Integration of solid modeling and data base management for CAD/CAM
Recovery-driven design: a power minimization methodology for error-tolerant processor modules
The construction of minimal area power and ground nets for VLSI circuits
An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules
Optimization by Simulated Evolution with Applications to Standard Cell Placement
SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture
An SoC design methodology using FPGAs and embedded microprocessors
APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-Design
Timing-constrained and voltage-island-aware voltage assignment
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware
A model of design representation and synthesis
A new test pattern generation system
Sketch pad a man-machine graphical communication system
Reliability challenges for 45nm and beyond
Symbolic Computer Algebra and SAT Based Information Forwarding for Fully Automatic Divider Verification
Mamba: closing the performance gap in productive hardware development frameworks
Challenges and Advances in Electrical Interconnect Analysis
A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC Circuits
A Notation for Describing Multiple Views of VLSI Circuits
Improving java virtual machine reliability for memory-constrained embedded systems
Design verification and performance analysis
Functional verification of memory circuits from mask artwork data
Design sensitivity of single event transients in scaled logic circuits
HAL II: a mixed level hardware logic simulation system
IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction
Synthesis of trustable ICs using untrusted CAD tools
Training Acceleration for Deep Neural Networks: A Hybrid Parallelization Strategy
A Graph-Based Synthesis Algorithm for AND/XOR Networks
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture
A multiprocessor raster display for interactive graphics system design
LifeGuard: A Reinforcement Learning-Based Task Mapping Strategy for Performance-Centric Aging Management
WB-trees: a meshed tree representation for FinFET analog layout designs
Design/synthesis workshop session
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
Arithmetic Optimization Using Carry-Save-Adders
An integrated system for computer design
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement
Cost-driven 3D integration with interconnect layers
Memory aware compilation through accurate timing extraction
Fast State Verification
Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems
Automated sign design and stencil cutting system
A statistical model for net length estimation
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor
An information system in architectural practices
A design platform for 90-nm leakage reduction techniques
The icewater language and interpreter
Integrated Designer's Activity Support System for Architecture
Formal analysis of hardware requirements
Formally Verifying a Microprocessor Using a Simulation Methodology
An efficient variable-cost maze router
Nanometer Device Scaling in Subthreshold Circuits
Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs
PC board layout techniques
MADS - a machine aided drafting system
A novel technique to improve noise immunity of CMOS dynamic logic circuits
Secure Logic Locking with Strain-Protected Nanomagnet Logic
System-on-chip beyond the nanometer wall
The KILL Rule for Multicore
Physical design methodology of power gating circuits for standard-cell-based design
On the General False Path Problem in Timing Analysis
Leanor: A Learning-Based Accelerator for Efficient Approximate Nearest Neighbor Search via Reduced Memory Access
Portability in silicon CAE
Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators