yusuke1997/dblp-id-title huggingface dataset:
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing
Application of Multi-Zero Artificial Neural Network to the Design of an M-Valued Digital Multiplier
Counting Predicates, Subset Surjective Functions, and Counting CSPs
Arithmetic Circuits for Analog Digits
An Error Correction Method for Binary and Multiple-Valued Logic
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System
Easily Reconstructable Logic Functions
On Selection of Intraocular Power Formula Using Support Vector Machines and Genetic Algorithm
Memories of K. C. Smith: Analog Computing, Multiple-Valued Logic and Machine Learning
A Broken Line Classification Method of Mathematical Graphs for Automating Translation into Scalable Vector Graphic
Weierstrass Approximations by Lukasiewicz Formulas with One Quantified Variable
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models
State Assignment Techniques in Multiple-Valued Logic
The Groupoid-Based Logic for Lattice Effect Algebras
Mapping Binary Functions to a Practical Adiabatic Quantum Computer
Optimization of GF(4) Expressions Using the Extended Dual Polarity Property
Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure
On Low Cost Realization of Multiple-Valued Logic Functions
Performance of CMOS Current Mode Full Adders
A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation
On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals
A Two-Pronged Approach of Power-Aware Voltage Scheduling for Real-Time Task Graphs in Multi-processor Systems
The Lattice of the Clones of Self-Dual Functions in Three-Valued Logic
New Fastest Linearly Independent Transforms over GF(3)
On NP-Complete Search Problems on Finite Algebras
MVL circuit design and characterization at the transistor level using SUS-LOC
The Pascal Triangle (1654), the Reed-Muller-Fourier Transform (1992), and the Discrete Pascal Transform (2005)
A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices
Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic
Theoretical Basis of Commutation Theory for Partial Clones
Classifications and Enumeration of Bases in P_{3}(2)
Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic Network Realization
A Six-Valued Logic for Representing Incomplete Knowledge
A Synthesis Method of the Approximate Reasoning Engine by means of Genetic Algorithm
Properties of Lindenmayer Fuzzy Languages and a-Driven Lindenmayer Languages
Algorithm and Implementation of a Learning Multiple-Valued Logic Network
Fuzzy four-valued logic for inconsistency and uncertainty
Lukasiewicz' Insect: The Role of Continuous-Valued Logic in a Mobile Robot's Sensors, Control, and Locomotion
A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC
Extensions to the Reversible Hardware Description Language SyReC
Reversible Logic Synthesis via Biconditional Binary Decision Diagrams
ESOP-Based Toffoli Network Generation with Transformations
Some Consistency Criteria for Many-Valued Judgment Aggregation
New Insights into Encodings from MaxCSP into Partial MaxSAT
Representation of Multiple-Valued Bent Functions Using Vilenkin-Chrestenson Decision Diagrams
Classification of Ternary Logic Functions by Self-Dual Equivalence Classes
Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors
Encoding Max-CSP into Partial Max-SAT
Comparing Performance of a Multiple-Valued Time-Based Serial Data Link with Other Serial Links
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks
From Ramon Llull To Lov Grover: Towards A Universal Logic Machine
On the Diagnosability of Systems with Three Valued Test Results: Diagnosis by Comparison Strategy
Evaluation of Cardinality Constraints on SMT-Based Debugging
Induction of Fuzzy Production Rules
(n+1)-Valued Modal Implicative Semilattices
A Photonic Physically Unclonable Function's Resilience to Multiple-Valued Machine Learning Attacks
Generalized Complex Spectral Decision Diagrams Using Unified Complex Hadamard Transform
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables
On the Reed-Muller-Fourier Spectrum of Multiple-Valued Rotation Symmetric Functions
A Classification of Partial Boolean Clones
Towards Fuzzy Type Theory
Design Methodologies for Ternary Logic Circuits
Banzhaf Index and Boolean Difference
Design of Dynamic Reliability Indices
Differential Multiple-Valued Logic Using Resonant Tunneling Diodes
Polynomial Completeness Criteria in Finite Boolean Algebras
Towards First-Order Symbolic Trajectory Evaluation
A Four-Valued Logic B(4) of E(9) for Modeling Human Communication
Ultrafast Ternary Quantizer using Resonant Tunneling Devices
A Super Switch Algebra for Quantum Device Based Systems
On T-Quantifiers and S-Quantifiers
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects
Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions
Classical Gentzen-Type Methods in Propositional Many-Valued Logics
Realization of Arithmetic Operators Based on Stochastic Number Frequency Signal Representation
Optimizations of Ternary Generative Adversarial Networks
Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits
Normal Forms for the One-Variable Fragment of Hájek's Basic Logic
On the Use of VHDL as a Multi-Valued Logic Simulator
Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test
Synthesis of Small Reversible and Pseudo-Reversible Circuits Using Y-Gates and Inverse Y-Gates
On Decision Diagrams for Maximally Asymmetric Functions
Post Relation Algebras and Their Proof System
Single-Chip Realization of a Fuzzy Logic Controller with Neural Network Structure (NNFLC)
Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades
Contribution to the Study of Ternary Functions with a Bent Reed-Muller Spectrum
The MacLaurin's and Taylor's Series Expansions of the Symbolic Multiple Valued Logic Functions
3D Shape Understanding for the Visually Impaired by using Virtual Haptic Senses based on Fuzzy Logic
Spectral Analysis of Special Properties of Ternary Functions
Four-valued threshold logic full adder circuit implementations
A Multiple-Valued Ferroelectric Content-Addressable Memory
Index Generation Functions: Minimization Methods
Haack meets Herzberger and Priest
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits
Universes of Fuzzy Sets - A Short Survey
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits
Multi-Valued Models for Intuitionistic Logic
Multiple-Valued Product-of-Sums Expression with Truncated Sum
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts
Set-Valued Logic Circuits for Next Generation VLSI Architectures
2 k -ary Cyclic AN Codes for Burst Error Correction
Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits
Knot Automata
A Three-Valued Semantics for Discourse Representations
Quaternary Universal-Literal CAM for Cellular Logic Image Processing
Valuations in Nilpotent Minimum Logic
Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware
An Algebraic Approach to Reducing the Number of Variables of Incompletely Defined Discrete Functions
Quantum Motions and Emotions for a Humanoid Robot Actor
A Comparison of Architectures for Various Decision Diagram Machines
Many-Valued Generalizations of Two Finite Intervals in Post's Lattice
Comparative Study by Solving the Test Compaction Problem
Bringing Resources into Logic
de Morgan Bisemilattice of Fuzzy Truth Value
The Minimal Covering of Maximal Partial Clones in 4-valued Logic
Technique of Computing Logic Derivatives for MVL-Functions
2015 IEEE International Symposium on Multiple-Valued Logic, Waterloo, ON, Canada, May 18-20, 2015
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
Proposal of Four-Valued MRAM based on MTJ/RTD Structure
Special-purpose ternary computer for digital filtering
Quantum Multiple Valued Kernel Circuits
Multiple-Valued Caches for Power-Efficient Embedded Systems
Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued Framework
Novel VLSI Architectures for Real-World Intelligent Systems
Partial Clones Determined by Concatenated Relations
Power Indexes in Voting Systems and Multiple-Valued Logic
On Composition-Closed Classes of Boolean Functions
Extremely Complex 4-Colored Rectangle-Free Grids: Solution of Open Multiple-Valued Problems
The Decomposition of U(n) into XU(n) and ZU(n)
Fuzzy Logic and the Calculus of Fuzzy If-Then Rules
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form
A Generalization of Shestakov's Function Decomposition Method
The 2-SAT Problem of Regular Signed CNF Formulas
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits
33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan
Modeling and Simulation of Multiple-Valued and Nonlinear Quantum Photonic Components
Online Testing for Three Fault Models in Reversible Circuits
Silicon Single-Electron Devices and Their Applications
Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals
Vector representation of switching and three-valued functions
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits
Image Segmentation Based on Kleene Algebra
Probabilistic Verification of Multiple-Valued Functions
Experimental Studies on SAT-Based ATPG for Gate Delay Faults
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation
On the Synthesis of MVL Functions Using Input and Output Phase Assignments
On the Contributions of Helena Rasiowa to Mathematical Logic
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System
A Superconducting Ternary Systolic Array Processor
Rosenberg-Type Completeness Criteria for Subclones of Slupecki's Clone
On the Semigroup of Equational Classes of Finite Functions
Systematic Construction of Natural Deduction Systems for Many-Valued Logics
Possibility theory: As a means for modeling computer security and protection
Join-Irreducible Clones of Multiple-Valued Logic Algebra
Reducing the Cost of Clifford+T Quantum Gates
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
Semirigid Problems in k-Valued Logic
Two new classification theorems on residuated monoids
A Study on Realizing Awareness Using 3VL-MLP
Infectious semantics and analytic calculi for even more inclusion logics
A Decade of Spectral Techniques
Lukasiewicz Logic Arrays
Binarization and Classification of RGB Images
Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5)
Remarks on Applications of Shapes of Decision Diagrams in Classification of Multiple-Valued Logic Functions
Multi-Valued Functional Decomposition as a Machine Learning Method
A Novel Nonlinear Synapse Neuron Model Guaranteeing a Global Minimum - Wavelet Neuron
Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams
Quaternary Debiasing for Physically Unclonable Functions
Tunnelling Diode Technology
A Literal Gate Using Resonant-Tunneling Devices
Efficient Implementation of Controlled Operations for Multivalued Quantum Logic
An Analog-to-Digital Converter Using Delta-Sigma Modulator Network
Quaternary Coded Genetic Algorithms
Embedding-Based Methods for Trilattice Logic
Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams
Random Multiple-Valued Networks: Theory and Applications
Several Remarks on Algebraic Entropy
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations
Maximal Centralizing Monoids and their Relation to Minimal Clones
Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode Fuzzy State Memory
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams
Data Envelopment Analysis using Fuzzy Concept
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves
Associative Memories Based on Multiple-Valued Sparse Clustered Networks
Application of Multiple-Valued Logic in Importance Analysis of k-out-of-n Multi-state Systems
The Deepest Repetition-Free Decompositions of Non-Singular Functions of Finite-Valued Logics
Classical vs Quantum Fingerprinting
From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators
A Neighborhood Decoupling Algorithm for Truncated Sum Minimization
Polynomials as Generators of Minimal Clones
"New lamps for old!" (Generalized Multiple-valued Neurons)
Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input
Completeness of Subtrilattice Logic
Theory of Plausible Reasoning - Foundations and Methodology
Novel CMOS Scan Design for VLSI Testability
Structural and Behavioral Modeling with Monadic Logics
Clones of Pivotally Decomposable Functions
Quantification in Non-Deterministic Multi-Valued Structures
Information Relationships and Measures in Application to Logic Design
Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation
Spectral Techniques for Multiple-Valued Logic Circuits
Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency
On a Kleenean Extension of Fuzzy Measure
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing
Two-Dimensional Symbol Mapping for Evaluating Multi-Valued Data Transmission Quality
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor
A Spectral Algorithm for Ternary Function Classification
Efficient Deduction in Many-Valued Logics
Index Generation Functions Based on Linear and Polynomial Transformations
Theory and design of multivalued memory elements
Median Based Calculus for Lattice Polynomials and Monotone Boolean Functions
Intersections with Slupecki Partial Clones on a Finite Set
Hierarchical Subspace Learning for Dimensionality Reduction to Improve Classification Accuracy in Large Data Sets
Methods to Generate Multiple-valued Bent Functions of an odd Number of Variables
Computational Medical and Health Care Technology
Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks
Systems Health Care: Health Management Technology
Alternative Proof of Mulholland's Theorem and New Solutions to Mulholland Inequality
Fast Multi-Polarity Complex Hadamard Transform for Logic Functions
The Design of Current Mode CMOS Multiple-Valued Circuits
On the Minimization of Variables to Represent Partially Defined Classification Functions
Dynamic Re-Encoding During MDD Minimization
OR-Inverter Graphs for the Synthesis of Optical Circuits
Quantum Mechanical Model of Emotional Robot Behaviors
Optimization of Fuzzy If-Then Rule Bases by Evolutionary Tuning of the Operations
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs
A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm
Exact Template Matching Using Boolean Satisfiability
Quantum Algorithm for Maximum Satisfiability
Tableaux for Maximum Satisfiability in Łukasiewicz Logic
Fault Detection in Multiple Valued Logic Circuits
Clones of Partial Cofunctions
Two Many Values: An Algorithmic Outlook on Suszko's Thesis
The mathematics of Ivo Rosenberg
Natural Deduction for Connexive Paraconsistent Quantum Logic
Orderly Majority Functions with their Relation to Minimal Clones
Biometric System by Foot Pressure Change Based on Neural Network
An application of multiple-valued logic to a design of programmable logic arrays
A Multiple-Valued Logic Synthesis Using the Kleenean Coefficients
On Intervals of Partial Clones of Boolean Partial Functions
The new architecture of radix-4 Chinese abacus adder
Variable Reordering and Sifting for QMDD
Weak bases for Boolean relational clones revisited
Quantum Robots for Teenagers
Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990
Multiple-Valued Immune Network Model and Its Simulations
Lattices of Resolution Logics
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
Equalization Techniques for Multiple-Valued Data Transmission and Their Application
Quantum Communication Complexity: A Survey
On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach
A Method for Approximate Equivalence Checking
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic
Fully Source-Coupled Logic Based Multiple-Valued VLSI
Associativity Test in Hypergroupoids
A Completeness Criterion for Semi-Affine Algebras
Conditional Event Algebras and Logic, Part I: Motivation and History of the Problem
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions
On the Number of Multilinear Partitions and the Computing Capacity of Multiple-Valued Multiple-Threshold Perceptrons
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm
Bio-Algebras
Relation Graphs and Partial Clones on a 2-Element Set
Multiple-Valued Current-Mode Arithmetic Circuits Based on Redundant Positive-Digit Number Representations
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions
Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-Based Bounded Model Checking
Multi-Valued Decision Diagrams in Importance Analysis Based on Minimal Cut Vectors
Semirigid Equivalence Relations - A New Proof Method
On Multiple-Valued Separable Unordered Codes
On Submodular and Supermodular Functions on Lattices and Related Structures
A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit
Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms
Paradigms for Non-classical Substitutions
MTMR-SNQM: Multi-Tunnel Magnetoresistance Spintronic Non-volatile Quaternary Memory
PAM-4 Eye-Opening Monitoring Techniques Using Gaussian Mixture Model
Quaternion Groups versus Dyadic Groups in Representations and Processing of Switching Functions
Multiple-Valued-Input TANT Networks
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities
Multi-valued Decision Diagrams in Reliability Analysis of Consecutive k-out-of-(2k-1) Systems
An Efficient Approach to Verifying Galois-Field Arithmetic Circuits of Higher Degrees and Its Application to ECC Decoders
Inversion/Division in Galois Field Using Multiple-Valued Logic
Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams
uMemristorToolbox: Open source framework to control memristors in Unity for ternary applications
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation
Design Methods for Multiple-Valued Input Address Generators
A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus
A High-Throughput Detection Circuit based on 2 q +1-Valued Deep Neural Networks
42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012, Victoria, BC, Canada, May 14-16, 2012
Three-Valued Nonmonotonic Logic
Design of an Asynchronous Digital System with B-Ternary Logic
Multivalued Binary Relations and Post Algebras
Synthesis of Current-Mode Pass Transistor Networks
A Complete Resolution Calculus for Signed Max-SAT
Foundations of Higher Radix Numeric Computation
Proceedings of the 21st International Symposium on Multiple-Valued Logic, ISMVL 1991, Victoria, BC, Canada, May 26-29, 1991
Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems
Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme
Multiple-Valued Random Digit Extraction
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM
Lower Bound Sifting for MDDs
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit
TTL circuits for a 4-valued bus a way to reduce package and interconnections
Normal Forms for Fuzzy Logic Functions
A General Fuzzy Logical Operator Set
A Study on Operations in Interval and Paired Probabilities
Specialized Waveform Equalization Techniques for Multi-Valued Data Transmission
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language
A Functional Manipulation for Improving Tolerance against Multiple-Valued Weight Faults of Feedforward Neural Networks
A Four-Valued Logic and Switch-Level Differences
Non-Deterministic Matrices
On axiomatic characterisations of fuzzy approximation operators II. The rough fuzzy set based case
Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic Functions
Area-Efficient Implication Circuits for Very Dense Lukasiewicz Logic Arrays
The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its Applications
Efficient Algorithm for the Generation of Fixed Polarity Quaternary Reed-Muller Expansions
Theory and Uses of Post Algebras of Order omega+omegaw\ast.I
Quatemary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits
Maximal Hyperclones Determined by Monotone Operations
Finite-Valued Approximations of Product Logic
Spectral Techniques in Binary and Multiple-Valued Switching Theory
A Quaternary Decision Diagram Machine and the Optimization of its Code
Semigrid Sets of Central Relations Over a Finite Domain
Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits
Straight Construction of Non-Interactive Quantum Bit Commitment Schemes from Indistinguishable Quantum State Ensembles
ABCD: Analogy-Based Controllable Data Augmentation
Real Time Traffic Intersection Management Using Multi-objective Evolutionary Algorithm
On the Transfer Learning of Genetic Programming Classification Algorithms
Networks of Polarized Splicing Processors
Nature-Inspired Algorithms Applied to an Efficient and Self-adaptive Resources Selection Model for Grid Applications
Vehicle Routing in a Forestry Commissioning Operation Using Ant Colony Optimisation
Boosting Interactive Evolution Using Human Computation Markets
Quantum Candies and Quantum Cryptography
A Statistical Approach to the Identification of Diploid Cellular Automata
Realization of Periodic Functions by Self-stabilizing Population Protocols with Synchronous Handshakes
SemVec: Semantic Features Word Vectors Based Deep Learning for Improved Text Classification
Improving MLP Neural Network Performance by Noise Reduction
Theory and Practice of Natural Computing - 10th International Conference, TPNC 2021, Tsukuba, Japan, December 7-10, 2021, Proceedings