yusuke1997/dblp-id-title huggingface dataset:
Improving FPGA Reliability with Wear-Levelling
A Reconfigurable Platform for Real-Time Embedded Video Image Processing
Factors Influencing the Performance of a CPU-RFU Hybrid Architecture
An FPGA Implementation of the Linear Cryptanalysis
FPGA implementation of a multi-algorithm parallel FEC for SDR platforms
FPGA Based High Density Spiking Neural Network Array
Degradation Analysis and Mitigation in FPGAs
Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs
High-Level Design Tools for FPGA-Based Combinatorial Accelerators
Automated framework for FPGA-based parallel genetic algorithms
Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures
Improving logic density through synthesis-inspired architecture
Hardware implementation of stereo correspondence algorithm for the ExoMars mission
Extracting INT8 Multipliers from INT18 Multipliers
FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex
RAM-based hardware accelerator for network data anonymization
Architectural exploration and implementation of an image processing chain with SpaceStudio ™
Parallel dot-products for deep learning on FPGA
A hardware/software partitioning algorithm for custom computing machines
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators
An efficient sparse conjugate gradient solver using a Beneš permutation network
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver
Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs
A survey of open source processors for FPGAs
Challenges and Successes in Space Based Reconfigurable Computing
Real-Time Face Detection on a Configurable Hardware System
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems
VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic
Optimum Functional Decomposition for LUT-Based FPGA Synthesis
Dynamic query switching for complex event processing on FPGAs
FPGA-Implementation of Signal Processing Algorithms for Video Based Industrial Safety Applications
Efficient Pattern Recognition Algorithm Including a Fast Retina Keypoint FPGA Implementation
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
FPGA Implementation of an Augmented Reality Application for Visually Impaired People
A New Scalable Hardware Architecture for RSA Algorithm
An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications
Preemptive Hardware Task Management
Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings
Finding a Needle in the Haystack of Hardened Interconnect Patterns
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach
A Run-time Reconfigurable Processor for Video Motion Estimation
Efficient 3D triangulation in hardware for dense structure-from-motion in low-speed automotive scenarios
Area estimation and optimisation of FPGA routing fabrics
A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer
A Hardwar Operating System for Dynamic Reconfiguration of FPGAs
RIC Fast Adder and its Set Tolerant Implementation in FPGAs
Hardware Design with a Scripting Language
Building heterogeneous reconfigurable systems using threads
The LEAP FPGA operating system
Accelerating HMMER search using FPGA
Noise impact of single-event upsets on an FPGA-based digital filter
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
Greedy approach based heuristics for partitioning SpMxV on FPGAs
Recursive pipelined genetic propagation for bilevel optimisation
Tinsel: A Manythread Overlay for FPGA Clusters
PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems
FPGA Based Architectures for H. 264/AVC Video Compression Standard
Development of an FPGA-based real-time P300 speller
FPGA implementation of a digital IQ demodulator using VHDL
Reusable DSP Functions in FPGAs
A Service-Oriented Memory Architecture for FPGA Computing
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques
A Tool for Activity Estimation in FPGAs
Comparative Study of SRT-Dividers in FPGA
SOPC-based Embedded Smart Strain Gage Sensor
Computing Goldbach Partitions Using Pseudo-random Bit Generator Operators on a FPFA Systolic Array
The PowerPC Backend Molen Compiler
Perspectives of Reconfigurable Computing in Research, Industry and Education
A Reconfigurable Perfect-Hashing Scheme for Packet Inspection
Towards an all-digital antenna array transmitter
Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
The Impact of Aging on an FPGA-Based Physical Unclonable Function
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms
Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets
Fast FPGA Placement using Space-filling Curve
Building Asynchronous Circuits with JBits
HyperGRAF: Hyperdimensional Graph-Based Reasoning Acceleration on FPGA
Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine
Simulation of ATM Switches Using Dynamically Reconfigurable FPGAs
Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures
Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench
Hierarchical Interactive Approach to Partition Large Designs into FPGAs
A rate-based prefiltering approach to blast acceleration
XVDPU: A High Performance CNN Accelerator on the Versal Platform Powered by the AI Engine
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection
A link removal methodology for Networks-on-Chip on reconfigurable systems
In pursuit of instant gratification for FPGA design
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories
Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA
A technique for minimizing power during FPGA placement
GICS: Generic interconnection system
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures
Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design
Hardware compilation, configurable platforms and ASICs for self-validating sensors
Detecting power attacks on reconfigurable hardware
Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis
Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers
High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
Synthia : Synthesis of Interacting Automata Targeting LUT-based FPGAs
Power Analysis of FPGAs: How Practical is the Attack?
Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements
Unifying Finite Difference Option-Pricing for Hardware Acceleration
SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip
Wirelength Prediction for FPGAs
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays
Multiplicative Square Root Algorithms for FPGAs
CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs
Clock-Aware Placement for FPGAs
Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis
High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems
On Identifying Segments of Traces for Dynamic Compilation
Comparing and combining GPU and FPGA accelerators in an image processing context
A high performance, open source SATA2 core
Sharf: An FPGA-based customizable processor architecture
The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]
Timing-constrained minimum area/power FPGA memory mapping
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array
FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms
Enhancing security of ring oscillator-based trng implemented in FPGA
CREMA: A coarse-grain reconfigurable array with mapping adaptiveness
Hybrid FPGA debug approach
Design and simulation tools for Embedded NOCs on FPGAs
Power-Aware Real-Time Operating Systems on Reconfigurable Architectures
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies
Digital Pre-distortion Implemented Using FPGA
Multiple Stereo Matching Using an Extended Architecture
A flexible hash table design for 10GBPS key-value stores on FPGAS
Accelerating LSTM-Based High-Rate Dynamic System Models
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs
LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project
Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs
Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration
Ziggurat-based Hardware Gaussian Random Number Generator
SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs
FPGA Implementation of the Adpaptive Lattice Filter
A reconfigurable approach to low cost media processing
Static Profile-Driven Compilation for FPGAs
EasyNet: 100 Gbps Network for HLS
JHDLBits: The Merging of Two Worlds
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor
Efficient floating-point polynomial evaluation on FPGAS
Exploring Potential Benefits of 3D FPGA Integration
An event-based middleware for the remote management of runtime hardware reconfiguration
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area
Clock gating architectures for FPGA power reduction
Three-Dimensional Dynamic Programming for Homology Search
Binarization based implementation for real-time human detection
FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot
Programmable Numerical Function Generators: Architectures and Synthesis Method
Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays
Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation
Processing Models for the Next Generation Network [Abstract]
Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study
A variation-adaptive retiming method exploiting reconfigurability
Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques
DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot
The Teramac Configurable Computer Engine
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling
ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing
Large multipliers with fewer DSP blocks
Virtex-6 and Spartan-6, plus a look into the future
Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing
Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations
Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs
Fast Reconfigurable Crossbar Switching in FPGAs
DynaRapid: Fast-Tracking from C to Routed Circuits
Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models
A Model for Matrix Multiplication Performance on FPGAs
Reconfigurable Architectures for Real-Time Network Anomaly Detection
A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars
Supporting High Level Language Semantics Within Hardware Resident Threads
An Efficient Implementation of a 2D DWT on FPGA
Quantifying observability for in-system debug of high-level synthesis circuits
FPLD Implementation of Computation over Finite Fields GF(2 m ) with Applications to Error Control Coding
Optimizing packet lookup in time and space on FPGA
A secure coprocessor for database applications
MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA
Automated Design of FPGAs Facilitated by Cycle-Free Routing
A Self-Calibrating True Random Number Generator
A Flexible Real-Time Stereo Vision Architecture for Multiple Data Streams with Runtime Configurable Parameters
A Key Management Architecture for Securing Off-Chip Data Transfers
HashCache: High-Performance State Tracking for Resilient FPGA-Based Packet Processing
Data scheduling to increase performance of parallel accelerators
A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware
Effective FPGA debug for high-level synthesis generated circuits
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry
Field-Programmable Analog Arrays: A Floating-Gate Approach
Comparing fine-grained performance on the Ambric MPPA against an FPGA
Power Analysis Attacks Against FPGA Implementations of the DES
FPGA Custom DSP for ECG Signal Analysis and Compression
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis
Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction
Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node
STRIPE: Signal selection for runtime power estimation
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS
Voltage drop-based fault attacks on FPGAs using valid bitstreams
FPGA Implementation of the Ridge Line Following Fingerprint Algorithm
Hardware accelerated novel optical de novo assembly for large-scale genomes
A Real-Time Visualization System for PIV
An FPGA-based implementation of the MINRES algorithm
Aging-based leakage energy reduction in FPGAs
FPL Curriculum at Tallinn Technical University
Reconfigurable Multiplier for Virtex FPGA Family
A Reconfigurable Embedded Input Device for Kinetically Challenged Persons
A generalized and unified SPFD-based rewiring technique
Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
Loop Tiling for Reconfigurable Accelerators
Criticality-based routing for FPGAS with reverse body bias switch box architectures
An FPFA Based Object Recognition Machine
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers
Multi-directional error correction schemes for SRAM-based FPGAs
25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015
An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals
High speed ECC implementation on FPGA over GF(2 m )
DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator
On the difficulty of pin-to-wire routing in FPGAs
Everyone's a Critic: A Tool for Exploring RISC-V Projects
A Concept for an Evaluation Framework for Reconfigurable Systems
A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform
Reconfigurable Logic Based Fibre Channel Network Card With Sub 2 Micro-Second Raw Latency
Ultra-Flow: An Ultra-fast and High-quality Optical Flow Accelerator with Deep Feature Matching on FPGA
An open-source design and validation platform for reconfigurable systems
Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo
FPGA-Based Computation of Free-Form Deformations
A Key Agile 17.4 Gbit/sec Camellia Implementation
An Interactive Datasheet for the Xilinx XC6200
Heterogeneous virtualized network function framework for the data center
A configurable and programmable motion estimation processor for the H.264 video codec
CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems
Reconfigurable Computing Systems as Component-oriented Designs for Robotics
On reconfigurable fabrics and generic side-channel countermeasures
A Dynamic Memory Allocation Library for High-Level Synthesis
A hardware/software codesign framework for vision-based ADAS
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
Redefining the FPGA for the Next Generation
Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator
A space/time tradeoff methodology using higher-order functions
High performance FPGA object detector: Hardware prototype
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
The Design of a New FPGA Architecture
An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms
Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings
FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors
FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture
FPGAS in high energy physics experiments at CERN
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center
Performance Estimation and Prototyping of Reconfigurable Near-Memory Computing Systems
Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp
Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2
An acceleration of a graph cut segmentation with FPGA
SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture
The Fastest Multiplier on FPGAs with Redundant Binary Representation
Hoplite: Building austere overlay NoCs for FPGAs
Defect-Tolerant FPGA Architecture Exploration
A Music Synthesizer on FPGA
Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree
An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture
MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping
Creating a World of Smart Re-configurable Devices
Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions
FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm
FPGA accelerating three QR decomposition algorithms in the unified pipelined framework
Software Decelerators
Real-time Handel-C Based Implementation of DV Decoder
A Global Routing Heuristic for FPGAs Based on Mean Field Annealing
Three-stage pipeline implementation for SHA2 using data forwarding
Performance Modeling of 2D Cellular Automata on FPGA
Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip
Shielding non-trusted IPs in SoCs
Reduction of Bitstream Size for Low-Cost iCE40 FPGAs
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes
Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs
FPL Demo: SERVE: Agile Hardware Development Platform with Cloud IDE and Cloud FPGAs
An Emulator for Exploring RaPiD Configurable Computing Architectures
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators
Implementing Kak Neural Networks on a Reconfigurable Computing Platform
Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware
Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers
TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations
Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core
Secure partial dynamic reconfiguration with unsecured external memory
LYNX: CAD for FPGA-based networks-on-chip
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs
High Density Asynchronous LUT Based on Non-volatile MRAM Technology
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip
GPU Versus FPGA for High Productivity Computing
High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures
Synthesizing Tiled Matrix Decomposition on FPGAs
Secure FPGA technologies and techniques
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip
Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks
Virtualization of Reconfigurable Mixed-Criticality Systems
Emulating Spiking Neural Networks for edge detection on FPGA hardware
A dataflow-inspired CGRA for streaming applications
Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES
Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics
Should FPGAS abandon the pass-gate?
A VHDL Generator for Elliptic Curve Cryptography
Context Saving and Restoring for Multitasking in Reconfigurable Systems
A High-Speed Rotation Processor
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow
On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips
SystemC for the Design and Modeling of Programmable Systems
Designing, Scheduling, and Allocating Flexible Arithmetic Components
Bayesian Optimization for Efficient Heterogeneous MPSoC Based DNN Accelerator Runtime Tuning
An FPGA design for evaluating score function in protein energy calculation
A Programmable I/O System for Real-Time AC Drive Control Applications
Compiled hardware acceleration of Molecular Dynamics code
FPGA Implementation of a Maze Routing Accelerator
High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
An Automatic Technique for Realising User Interaction Processing in PLD Based Systems
Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA
Reconfigurable PCI-Bus Interface (RPCI)
The PLD-Implementation of Boolean Function Characterized by Minimum Delay
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Disruptive Trends by Data-Stream-Based Computing
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices
Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling
Towards benchmarking energy efficiency of reconfigurable architectures
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing
High-speed and Memory Efficient TCP Stream Scanning using FPGA
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs
An Easily Testable Routing Architecture and Efficient Test Technique