yusuke1997/dblp-id-title huggingface dataset:
Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems
A Novel Frequency-Spatial Domain Aware Network for Fast Thermal Prediction in 2.5D ICs
Analysis and Optimization of the Recessed Probe Launch for High Frequency Measurements of PCB Interconnects
Enhancing Reliability of Operational Interconnections in FPGAs
Formal Methods for Integration of Automotive Software
Visualizing Decision Diagrams for Quantum Computing (Special Session Summary)
ManiHD: Efficient Hyper-Dimensional Learning Using Manifold Trainable Encoder
Register allocation for simultaneous reduction of energy and peak temperature on registers
Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning
Towards High-Level Synthesis of Quantum Circuits
Design challenges of high speed ATM communication ASICs
Performance - Manufacturability Tradeoffs in IC Design
GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks
A low-area flexible MIMO detector for WiFi/WiMAX standards
Real-time analysis of engine control applications with speed estimation
Closed-Form Crosstalk Noise Metrics for Physical Design Applications
Dynamic construction of circuits for reactive traffic in homogeneous CMPs
Model-based synthesis and optimization of static multi-rate image processing algorithms
Optimisation opportunities and evaluation for GPGPU applications on low-end mobile GPUs
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor
Design Refinement for Efficient Cluste ing of Objects in Embedded Systems
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding
Latch Modeling for Statistical Timing Analysis
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
Hardware-based on-line intrusion detection via system call routine fingerprinting
A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time
Towards Fast Automatic Design of Silicon Dangling Bond Logic
EffiCSense: an Architectural Pathfinding Framework for Energy-Constrained Sensor Applications
Circuits in a Box: Computing High-Dimensional Performance Spaces for Analog Integrated Circuits
A Step Toward Safe Unattended Train Operations: A Pioneer Vital Control Module
Correlating inline data with final test outcomes in analog/RF devices
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications
Cyborg insects, neural interfaces and other things: building interfaces between the synthetic and the multicellular
All-digital embedded meters for on-line power estimation
Fault Tolerance of Programmable Switch Blocks
Exploiting resource-constrained parallelism in hard real-time streaming applications
Temperature-aware NBTI modeling and the impact of input vector control on performance degradation
PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor
Is Register Transfer Level Locking Secure?
Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory Management
HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars
Generalized Data Placement Strategies for Racetrack Memories
System Design for DSP Applications Using the MASIC Methodology
A universal telephone audio circuit with loudhearing and handsfree operation in CMOS technology
DHD: Double Hard Decision Decoding Scheme for NAND Flash Memory
Design Kit for Microsystems Design for an Enhanced CMOS Process
Hybrid BIST Based on Repeating Sequences and Cluster Analysis
AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics
Model-Order Reduction Based on PRONY's Method
Probabilistic timing analysis on conventional cache designs
Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based Test Generation
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs
A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process
Automotive semi-conductor trend & challenges
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology
ARO-PUF: An aging-resistant ring oscillator PUF design
Reliable Edge Intelligence in Unreliable Environment
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding
Hardware Efficient Weight-Binarized Spiking Neural Networks
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip
Cross-correlation of specification and RTL for soft IP analysis
Communication Analysis for System-On-Chip Design
Linear Model-Based Error Identification and Calibration for Data Converters
Subpage programming for extending the lifetime of NAND flash memory
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
Hardware trojan detection by delay and electromagnetic measurements
Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories
Depth-directed hardware object detection
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra
Design enablement of CFET devices for sub-2nm CMOS nodes
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs
Simulation-based verification of the MOST NetInterface specification revision 3.0
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints
DEAR: Dependable 3D Architecture for Robust DNN Training
PHYLAX: Snapshot-based profiling of real-time embedded devices via JTAG interface
VW-SDK: Efficient Convolutional Weight Mapping Using Variable Windows for Processing-In-Memory Architectures
Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement
Interactive presentation: PowerQuest: trace driven data mining for power optimization
Improved Visibility in One-to-Many Trace Concretization
Methods and tools for systems engineering of automotive electronic architectures
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver
An Experimental Study of Satisfiability Search Heuristics
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
Scheduling and Module Assignment for Reducing Bist Resources
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
Multirate controller design for resource- and schedule-constrained automotive ECUs
Improved diagnosis of realistic interconnect shorts
Virtual Components Application and Customization
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs
A Framework for Designing Scalable Gaussian Belief Propagation Accelerators for use in SLAM
RunAssert: A non-intrusive run-time assertion for parallel programs debugging
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications
A dual grain hit-miss detector for large die-stacked DRAM caches
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost
CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults
Area versus detection latency trade-offs in self-checking memory design
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis
Design Optimization of Frame Preemption in Real-Time Switched Ethernet
Reconfigurable Elliptic Curve Cryptosystems on a Chip
RetroDMR: Troubleshooting non-deterministic faults with retrospective DMR
A ultra-low-power FPGA based on monolithically integrated RRAMs
Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points
Reverse engineering digital circuits using functional analysis
Write-Optimized Persistent Hash Index for Non-Volatile Memory
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits
FUSIS: Fusing Surrogate Models and Importance Sampling for Efficient Yield Estimation
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration
Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks
An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security
Towards a meta-language for the concurrency concern in DSLs
Sanctorum: A lightweight security monitor for secure enclaves
Strengthening properties using abstraction refinement
UML design for dynamically reconfigurable multiprocessor embedded systems
A Comprehensive Solution for Securing Connected and Autonomous Vehicles
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit
GCS: High-performance gate-level simulation with GPGPUs
Power-efficient calibration and reconfiguration for on-chip optical communication
Energy-Aware Error Correction Method for Indoor Positioning and Tracking
A regularity-based hierarchical symbolic analysis method for large-scale analog networks
FastTree: a hardware KD-tree construction acceleration engine for real-time ray tracing
REALM: Reduced-Error Approximate Log-based Integer Multiplier
Adaptive Deep Learning for Efficient Visual Pose Estimation Aboard Ultra-Low-Power Nano-Drones
Ageing simulation of analogue circuits and systems using adaptive transient evaluation
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization
Exploring parallelizations of applications for MPSoC platforms using MPA
Memory bank aware dynamic loop scheduling
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
Efficient wear leveling for inodes of file systems on persistent memories
Improving efficiency of extensible processors by using approximate custom instructions
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns
Multi-bit non-volatile spintronic flip-flop
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity
Digital Memcomputing Machines
CARS: A Multi-layer Conflict-Aware Request Scheduler for NVMe SSDs
2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France
Evaluating energy consumption of homogeneous MPSoCs using spare tiles
Test Structures on MCM Active Substrate: Is it worthwhile?
DSP based programmable FHD HEVC decoder
Improving compressed test pattern generation for multiple scan chain failure diagnosis
Towards inter-vendor compatibility of true random number generators for FPGAs
Bluetooth Transceiver Design with VHDL-AMS
Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology
Isochronous networks by construction
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage
CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation
SCFI: State Machine Control-Flow Hardening Against Fault Attacks
Symmetric Transparent BIST for RAMs
A case study in distributed deployment of embedded software for camera networks
Refinement of Mixed-Signal Systems with Affine Arithmetic
GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters
I 2 SR: Immediate Interrupt Service Routine on RISC-V MCU to Control mmWave RF Transceivers
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM
DeepSeq: Deep Sequential Circuit Learning
Ageing Impact on a High Speed Voltage Comparator with Hysteresis
Data-flow transformations using Taylor expansion diagrams
Property-specific witness graph generation for guided simulation
A Case Study for the Verification of Complex Timed Circuits: IPCMOS
A practical method to estimate interconnect responses to variabilities
Signal Probability Based Statistical Timing Analysis
PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems
Axilog: language support for approximate hardware design
Microwatt end-to-End digital neural signal processing systems for motor intention decoding
CMOS Implementation of Switching Lattices
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer
Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage
Statistical Time-based Intrusion Detection in Embedded Systems
Sufficient response time analysis considering dependencies between rate-dependent tasks
Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform
Multi-Partner Project: Resilient Time-Sensitive Networks (ResTSN)
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays
Early chip planning cockpit
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities
An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms
An AI-Enabled Framework for Smart Semiconductor Manufacturing
Parallel code generation of synchronous programs for a many-core architecture
MLP aware heterogeneous memory system
Characterizing display QoS based on frame dropping for power management of interactive applications on smartphones
System-level energy-efficient scheduling for hard real-time embedded systems
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping
Achieving composability in NoC-based MPSoCs through QoS management at software level
A Write-Efficient Cache Algorithm based on Macroscopic Trend for NVM-based Read Cache
OS Debugging Method Using a Lightweight Virtual Machine Monitor
Optical Receiver IC for CD/DVD/Blue-Laser Application
A VHDL Error Simulator for Functional Test Generation
SoftmAP: Software-Hardware Co-Design for Integer-Only Softmax on Associative Processors
A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices
Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set
Goal-Driven Autonomy for Efficient On-chip Resource Management: Transforming Objectives to Goals
A Deep Learning Approach to Sensor Fusion Inference at the Edge
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures
Checking signal transition graph implementability by symbolic BDD traversal
Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators
Host-compiled multicore RTOS simulator for embedded real-time software development
Incorporating Multi-Chip Module Packaging Constraints into System Design
Verification and synthesis of counters based on symbolic techniques
Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD framework
1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany
Low-Latency Asynchronous Logic Design for Inference at the Edge
The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical Systems
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays
Solid state photodetectors for nuclear medical imaging applications
Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction
Evaluation of a Refinement-Driven SystemC'-Based Design Flow
Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
An improved hierarchical classification algorithm for structural analysis of integrated circuits
A New Self-Checking Sum-Bit Duplicated Carry-Select Adder
Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
An efficient on-line task allocation algorithm for QoS and energy efficiency in multicore multimedia platforms
Towards verified programming of embedded devices
Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency
Worst-case design and margin for embedded SRAM
Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs
The simulation semantics of systemC
Non-Enumerative Path Delay Fault Diagnosis
On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures
On-device objective-C application optimization framework for high-performance mobile processors
Advance Virtual Channel Reservation
OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric Vehicles
Performance analysis of HPC applications on low-power embedded platforms
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems
Malicious Routing: Circumventing Bitstream-level Verification for FPGAs
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs
Methods and tools for component-based system design
Towards a Model-based Multi-Objective Optimization Approach For Safety-Critical Real-Time Systems
CATS: cycle accurate transaction-driven simulation with multiple processor simulators
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures
A new SBST algorithm for testing the register file of VLIW processors
Retiming Sequential Circuits with Multiple Register Classes
Utilization of SECDED for soft error and variation-induced defect tolerance in caches
Timing-reasoning-based delay fault diagnosis
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems
A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems
A methodology for automated design of hard-real-time embedded streaming systems
Fixed points for multi-cycle path detection
Wear-out analysis of Error Correction Techniques in Phase-Change Memory
Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communications
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis
A packet-switched interconnect for many-core systems with BE and RT service
A Deep-Learning-Based Statistical Timing Prediction Method for Sub-16nm Technologies
Random Stimulus Generation using Entropy and XOR Constraints
An automated parallel simulation flow for heterogeneous embedded systems
Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage Optimization
Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation
MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis
Generic design flows for project management in a framework environment
Automatic abstraction of multi-discipline analog models for efficient functional simulation
Entering the path towards terabit/s wireless links
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
IFFSET: In-Field Fuzzing of Industrial Control Systems using System Emulation
An out-of-order superscalar processor on FPGA: The ReOrder Buffer design
ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing
Full custom chip set for high speed serial communications up to 2.48 Gbit/s
Exploiting local logic structures to optimize multi-core SoC floorplanning
Accurate Dynamic Modelling of Hydraulic Servomechanisms
A Container-based DoS Attack-Resilient Control Framework for Real-Time UAV Systems
Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs
Measurement and validation of energy harvesting IoT devices
A methodology for mapping multiple use-cases onto networks on chips
SCI-FI: Control Signal, Code, and Control Flow Integrity against Fault Injection Attacks
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives
RAG: An efficient reliability analysis of logic circuits on graphics processing units
Securing ISW Masking Scheme Against Glitches
Embedded DRAM Architectural Trade-Offs
Impact of interconnect multiple-patterning variability on SRAMs
Toward virtualizing branch direction prediction
Adaptive Learning Based Building Load Prediction for Microgrid Economic Dispatch
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
Planning with Real-Time Collision Avoidance for Cooperating Agents under Rigid Body Constraints
MARS: A flexible real-time streaming platform for testing automation systems
FPGA latency optimization using system-level transformations and DFG restructuring
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs
Tactile prosthetics in WiseSkin
A guiding coverage metric for formal verification
Thermomechanical stress-aware management for 3D IC designs
Checking and deriving module paths in Verilog cell library descriptions
BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking
Workload-Aware Approximate Computing Configuration
An energy-efficient stochastic computational deep belief network
Characterizing the performance benefits of fused CPU/GPU systems using FusionSim
Constructive Library-Aware Synthesis Using Symmetries
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults
SRAM Design Exploration with Integrated Application-Aware Aging Analysis
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
A Combined Fault Detection and Discrimination Strategy for Resource-Sensitive Platforms
Efficient and Effective Redundancy Removal for Million-Gate Circuits
3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory
CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking
Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions
A satisfiability approach to speed assignment for distributed real-time systems
pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems
Energy Bounds for Fault-Tolerant Nanoscale Designs
Study on the Compensation of Silicon Photonics-Based Modulators in DCI Applications
Reducing code management overhead in software-managed multicores
Process Variation Resilient Current-Domain Analog In Memory Computing
Transfer and Online Reinforcement Learning in STT-MRAM Based Embedded Systems for Autonomous Drones