yusuke1997/dblp-id-title huggingface dataset:
CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity
Pixel-Parallel Architecture for Neuromorphic Smart Image Sensor with Visual Attention
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
On-chip clock error characterization for clock distribution system
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints
EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance
Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs
Hybrid QoS Method for Networks-on-Chip
Persistently-Secure Processors: Challenges and Opportunities for Securing Non-Volatile Memories
Near-Chip Dynamic Vision Filtering for Low-Bandwidth Pedestrian Detection
Toward Holistic Modeling, Margining and Tolerance of IC Variability
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques
Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators
Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
Decentralized Framework for Teleportation in Quantum Core Interconnects
On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM
Determining the Optimal Number of Islands in Power Islands Synthesis
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders
Maximizing Efficiency of SNN-Based Reservoir Computing via NoC-Assisted Dimensionality Reduction
High Performance Ternary Multiplier Using CNTFET
Countering PUF Modeling Attacks through Adversarial Machine Learning
SegmentAI: A Neural Net Framework for Optimized Multiclass Image Segmentation via FPGA
A Global Optimization for Scan Chain Insertion at the RT-level
A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy
Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device Heterogeneity
Watermarking Edge Neural Network for Object Detection
Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM
Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models
Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip Technology
Secured-by-Design FPGA against Early Evaluation
Tournament Cache Decay: Tight Control of Leakage Power for Last-Level Caches
Inference and Energy Efficient Design of Deep Neural Networks for Embedded Devices
Binary Difference Based Test Data Compression for NoC Based SoCs
Study and Analysis of Power Optimization Techniques for Embedded Systems
VegeCare: An IoT Framework To Monitor and Maintain Vegetable Quality
Blockchain Based Distributed Key Provisioning and Secure Communication over CAN FD
Parallel Programmable Finite Field GF(2m) Multipliers
Do we need wide flits in Networks-on-Chip?
Countering Botnet of Things using Blockchain-Based Authenticity Framework
An Open-Source Area-Optimized ECEG Cryptosystem in Hardware
MCTS-based Synthesis Towards Efficient Approximate Accelerators
Importance of Diagonal Gates in Tensor Network Simulations
Leveraging 3D Vertical RRAM to Developing Neuromorphic Architecture for Pattern Classification
Backlog Bound Analysis for Virtual-Channel Routers
A Versatile Linear Insertion Sorter Based on a FIFO Scheme
Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach
A Theoretical Framework For Modeling Cache-based Side-Channel Attacks and Countermeasures
Hardware Module Design for Ensuring Trust
High Throughput Floating Point Exponential Function Implemented in FPGA
LiteViT: Leveraging the Power of Transformers for Edge AI in Crop Disease Classification
Jitter in Deep Sub-Micron Interconnect
Reverse Engineering of RTL Controllers from Look-Up Table Netlists
Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test
A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications
Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction
Requirement Evolution Management: A Systematic Approach
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s
On analyzing and mitigating SRAM BER due to random thermal noise
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip
The Impact of Heterogeneity on a Reconfigurable Multicore System
Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization
Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
Exploiting Configurability as a Defense against Cache Side Channel Attacks
Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D Converters
A MCU-robust Interleaved Data/Detection SRAM for Space Environments
Trust Management Through Hardware Means: Design Concerns and Optimizations
A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs
A 64-bit Decimal Floating-Point Adder
FPGA Placement and Routing Using Particle Swarm Optimization
Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing
Testing Circuit-Partitioned 3D IC Designs
Polynomial Formal Verification of Approximate Functions
JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization
Synthesis-Aware Area Optimization for Safety Registers in Automotive SoCs
A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter
Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic Computing
RITC: Repeater Insertion with Timing Target Compensation
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability
A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor Circuits
SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits
Low-power and Computing-free Privacy Design for IoT Systems
Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree
Real-Time Automatic Music Transcription (AMT) with Zync FPGA
Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems
Formal Verification Using Don't-Care and Vanishing Polynomials
Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells library
Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures
Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies
SanaSolo 3.0: A Low-Ground, IoT-Based Rover for In-Situ Soil Fertility Monitoring
Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms
MASH Digital Delta-Sigma Modulators for the CMOS Qubit Controller
Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)
Behavioural Scheduling to Balance the Bit-Level Computational Effort
Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks
ChatTCAD: Leveraging Large Language Models for Automated TCAD Simulation File Generation
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology
Breaking power delivery walls using voltage stacking
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph
Physically Unclonable and Reconfigurable Circuits for IP Protection: Opportunities and Challenges
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells
An Improved Automatic Hardware Trojan Generation Platform
Logic Synthesis for In-memory Computing Using Resistive Memories
Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs
ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA
Q-Fusion: Diffusing Quantum Circuits
A 1.7 GHz Tuning Range LC-VCO with Varactors Array and Switched Cross-Coupled Core
Generation and Exploration of Layouts for Area-Efficient Barrel Shifters
A Variation-Aware and Energy-Efficient Spintronic True Random Number Generator
The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies
A Width-Configurable Hardware Approach for Accelerating Fixed-Point Simulation
MC- PUF: A Robust Lightweight Controlled Physical Unclonable Function for Resource Constrained Environments
Reducing the Model Order of Deep Neural Networks Using Information Theory
Wire Length Distribution Model Considering Core Utilization for System on Chip
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator
Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures
Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware Accelerators
Real-Time IC Aging Prediction via On-Chip Sensors
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations
Aging Analysis of Low Dropout Regulator for Universal Recycled IC Detection
SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect
RRAM Reliability/Performance Characterization through Array Architectures Investigations
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC
Communication-Aware Parallelization Strategies for High Performance Applications
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis
Security Challenges in CPS and IoT: From End-Node to the System
High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links
Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs
Testing of Trusted CMOS Data Converters
Next Generation Smart Home Systems Using Hardware Acceleration Techniques
Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier
An Effective Power Grid Optimization Approach for the Electromigration Reliability
Reconfigurable Architectures for Bioinformatics Applications
Balancing System Level Pipelines with Stage Voltage Scaling
An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform
TrustFlow: A Trusted Memory Support for Data Flow Integrity
Logic synthesis for manufacturability considering regularity and lithography printability
Recent advances and challenges in physical design automation
A Scalable Bandwidth Aware Architecture for Connected Component Labeling
Performance Evaluation of Video Analytics Workloads on Emerging Processing-In-Memory Architectures
Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support
Power Comparison of Throughput Optimized IC Busses
Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCs
Scalable Integer DCT Architecture for HEVC Encoder
Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs
Statistical Gate Sizing for Yield Enhancement at Post Layout Level
A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity
NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors
Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing Platform
Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures
Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis
Decoder-Based Multi-Context Interconnect Architecture
Cohesive Coverage Management for Simulation and Formal Property Verification
Grep: Performance Enhancement in MultiCore Processors using an Adaptive Graph Prefetcher
Program phase duration prediction and its application to fine-grain power management
Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing
XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation
Synthesis of Multithreshold Threshold Gates
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal, Brazil, August 5-7, 2013
Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion
Bistable All-Josephson Junction SQUID with Dual Φ-Junctions for State-Controlled Superconducting Circuits
Functional Broadside Test Generation Using a Commercial ATPG Tool
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators
Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint Architecture
Power Efficient Multiplexer Using DLDFF Synchronous Counter
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters
A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants
A High Speed Reconfigurable Gate Array for Gigahertz Applications
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach
Distributed Classification with Dynamic Communication for Air Quality Sensing
Understanding the Switching Mechanism in Transition Metal Oxide Based ReRAM Devices
Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoT
A Spiking Recurrent Neural Network
High Speed Ultra Low Voltage CMOS inverter
Toward Design Technology in 2020: Trends, Issues, and Challenges
A Graph-Based 3D IC Partitioning Technique
A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification
Boundary-Power Overlapped Design for Sub-3nm Standard Cell Placement
A New High Performance VLSI Architecture for LMS Adaptive Filter Using Distributed Arithmetic
Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA
Combined TDM and SDM Circuit Switching NoCs with Dedicated Connection Allocator
SecCheck: A Trustworthy System with Untrusted Components
Toward Memory-efficient Design of Video Encoders for Multimedia Applications
Energy-Efficient Near-Sensor Event Detector Based on Multilevel Ga2O3 RRAM
A Configurable and Lightweight Timing Monitor for Fault Attack Detection
Soft-Error Probability Due to SET in Clock Tree Networks
Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics
Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded Architectures
A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling
An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff
Efficient Realization of Strongly Indicating Function Blocks
Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores
Analyzing the Sensitivity of GPU Pipeline Registers to Single Events Upsets
New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach
New non-volatile FPGA concept using Magnetic Tunneling Junction
Architecting SOT-RAM Based GPU Register File
Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures
Efficient Rerouting Algorithms for Congestion Mitigation
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect
A New Test Data Compression Scheme for Multi-scan Designs
Intelligent On/Off Link Management for On-chip Networks
Multi-SP: A Representation with United Rectangles for Analog Placement and Routing
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws
Leakage-Aware SPM Management
Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach
LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches
A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation
Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain
Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs
Processor Design with Asymmetric Reliability
Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing
A Low Power High Performance Distributed DCT Architecture
CMOS Control Enabled Single-Type FET NASIC
A Sampling-based Method for Output Safety Verification of Spiking Neural Networks
On the Reduction of Simultaneous Switching in SoCs
Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis
Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device
Enhancing Supply Chain Security: ML Assisted Manufacturer Identification of SRAM PUFs
Equalizing Filter Design for Crosstalk Cancellation
A Comparative Study of Specification Mining Methods for SoC Communication Traces
TEPS: Transient Error Protection Utilizing Sub-word Parallelism
On Analysis of On-chip DC-DC Converters for Power Delivery Networks
A 0.3V Low Cost Low Power 24 GHz Low Noise Amplifier with Body Bias Technology
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection
Compact Model Parameter Extraction using Bayesian Machine Learning
Lightweight and Trust-Aware Routing in NoC-Based SoCs
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy
Possible Reductions to Generate circuits from BDDs
Efficient Multi-Cycle Folded Integer Multipliers
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems
A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters
Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offs
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC)
n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator
Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation
On-Chip Instrumentation for Runtime Verification in Deeply Embedded Processors
Extended Abstract: Quantum-Accelerated Transient Stability Assessment for Power Systems
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures
CMP-aware Maze Routing Algorithm for Yield Enhancement
91dB Dynamic Range 9.5nW Low Pass Filter for Bio-Medical Applications
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage
Integration of Memristive Encoders for On-Device Automation of Low-Power Wearable Energy Management Systems
Phase-Based Dynamic Instruction Window Optimization for Embedded Systems
Improving GA-Based NoC Mapping Algorithms Using a Formal Model
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA
Timing Macro Modeling for Efficient Hierarchical Timing Analysis
Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder
Adaptive and Energy-Efficient Architectures for Machine Learning: Challenges, Opportunities, and Research Roadmap
Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems
Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25 µm, PD SOI Process
A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans
A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm
Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs
SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies
Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs
VLSI Systems for Embedded Video
Design and Performance Evaluation of Approximate Floating-Point Multipliers
Temperature Variable Supply Voltage for Power Reduction
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025, Kalamata, Greece, July 6-9, 2025
Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding
Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair
Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display
Designing and Benchmarking of Double-Row Height Standard Cells
Exploiting Near-Data Processing to Accelerate Time Series Analysis
Let's Think Analog
Pattern-Driven Clock Tree Routing with Via Minimization
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits
Enhanced Architecture for Computing Polynomials Using Unipolar Stochastic Logic
Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation
Scaling Analog Photonic Accelerators for Byte-Size, Integer General Matrix Multiply (GEMM) Kernels
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design
Versatile Signal Distribution Networks for Scalable Placement and Routing of Field-coupled Nanocomputing Technologies
Message from the General Chairs; ISVLSI 2024
Can Soft Errors be Handled Securely?
Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology