yusuke1997/dblp-id-title huggingface dataset:
A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applications
Ultra-low power multi-channel data conversion with a single SAR ADC for mobile sensing applications
A 14-bit 0.17mm 2 SAR ADC in 0.13μm CMOS for high precision nerve recording
Distributed clock generator for synchronous SoC using ADPLL network
A 90-240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking
Recording Front-End Electronics for Large-Scale Implantable Brain-Computer Interfaces: A Design Perspective
Width Quantization Aware FinFET Circuit Design
A 28GHz Hybrid-Beamforming Transmitter Array Supporting Concurrent Dual Data Steams and Spatial Notch Steering for 5G MIMO
A fast method for identifying matching-relevant transistor pairs
A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme
A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA
A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes
The role of translational circuits in RF receiver design
A fast-locking digital DLL with a high resolution time-to-digital converter
The past present and future of design-technology co-optimization
Silicon-on-organic integration of a 2.4GHz VCO using high Q copper inductors and solder-bumped flip chip technology
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems
A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna
Multi-aggressor relative window method for timing analysis including crosstalk delay degradation
Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning
Sandblaster low power DSP [parallel DSP arithmetic microarchitecture]
WiCkeD: analog circuit synthesis incorporating mismatch
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems
A/D converter trends: Power dissipation, scaling and digitally assisted architectures
A high-speed, low-power 3D-SRAM architecture
A Power-Efficient Hybrid Single-Inductor Bipolar-Output DC-DC Converter with Floating Negative Output for AMOLED Displays
Analysis and modeling of on-chip power combiners and their losses in LINC transmitters
Fast, accurate prediction of PLL jitter induced by power grid noise
Analog Front-End Circuits for MEMS Microphones
A 3-V high-bandwidth integrator for magnetic disk read channel continuous-time filtering applications
A discrete-time charge-domain filter with bandwidth calibration for LTE application
A 0.4V∼1V 0.2A/mm 2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2 nd -order ΔΣ linearization
A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching
Characterization and simulation methodology for time-dependent variability in advanced technologies
A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO
High-performance and low-power challenges for sub-70 nm microprocessor circuits
A 0.3V, 35% Tuning-Range, 60kHz 1/f 3 -Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS
Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs
Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems
A 93.7 % -Efficiency 5-Ratio Switched-Photovoltaic DC-DC Converter
A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS
A 65-dB DR 1-MHz BW 110-MHz IF bandpass ΣΔ modulator employing electromechanical loop filter
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode
A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration
Pure CMOS one-time programmable memory using gate-ox anti-fuse
Mixed-swing methodology for domino logic circuits
Circuit-aware on-chip inductance extraction
Time-based ΑΣADCs
Physics-based compact models for insulated-gate field-effect biosensors, landau-transistors, and thin-film solar cells
Monolithic very high frequency GaN switched-mode power converters
Session 20 - Advanced wireline techniques
Ultra low-power CMOS IC using partially-depleted SOI technology
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire
A 2.4mW, 111dB SNR continuous-time ΣΔ ADC with a three-level DEM technique
A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement
Session 4 - High-speed test, characterization, and debug
An open-loop full CMOS 103 MHz -61 dB THD S/H circuit
A Low-Power Unified Arithmetic Unit for Programmable Handheld 3-D Graphics Systems
An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories
A 6μm-Precision Pulsed-Coherent Lidar with a 40-dB Tuning Range Inverter-Based Phase-Invariant PGA
Reducing power in flexible a-Si digital circuits while preserving state
A Highly Linear Broadband Variable Gain LNA for TV Applications
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis
Crosstalk coupling effects of CMOS co-planar spiral inductors
A 48x OSR 105.4-dB SNDR 24-kHz BW CT Zoom ADC with Reset Tri-level DWA and On-chip Negative-R Calibration
The Advanced Compact MOSFET (ACM) Model for Circuit Analysis and Design
A silicon efficient FLEX 6000 programmable logic architecture
Frequency reference challenges - a systemic view
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device
An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS
Modeling of integrated RF passive devices
Sub-sampling PLL techniques
Modeling and simulation for low power in mixed-signal integrated systems
A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP
A CMOS Low-Noise Fast-Settling BM-TIA with CM-Post-Amplifier Chip Connectivity for 50G-PON
A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs
Analytical modeling of MOSFET noise parameters for analog and RF applications
MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros
Understanding Body Channel Communication : A review: from history to the future applications
Direct digital frequency synthesis of low-jitter clocks
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores
An integrated capacitively coupled transformer and its application for RF IC's
Speed-power-accuracy trade-off in high-speed ADCs: what about nano-electronics?
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC
A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction
A 0.5V 0.55mm 2 Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT applications
Virtual de-embedding study for the accurate extraction of Fin FET gate resistance
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR
A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction
Programmable logic IP cores in SoC design: opportunities and challenges
A Cartesian feedback-feedforward transmitter IC in 130nm CMOS
A 2λ×100 Gb/s Optical Receiver with Si-Photonic Micro-Ring Resonator and Photo-Detector for DWDM Optical-IO
A dual-speed 125 Mbaud/10 Mbaud CMOS transmitter for Fast Ethernet
Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions
A transformer-based broadband I/O matching-balun-T/R switch front-end combo scheme in standard CMOS
Multi-thread VLIW processor architecture for HDTV decoding
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O
Super-resolution: Imaging beyond the pixel size limit
Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End
Phase-locked frequency synthesis and modulation for modern wireless transceivers
A 49.8mm 2 Fully Integrated, 1.5m Transmission-Range, High-Data-Rate IR-UWB Transmitter for Brain Implants
When do we need non-quasistatic CMOS RF-models?
A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES
600 MHz DSP for baseband processing in 3G base stations
A fully-integrated, 90% peak efficiency, 0.99 power factor, AC-DC LED Driver with on-chip direct-AC-connect series startup pre-regulator
45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]
Ferroelectric nonvolatile memories for embedded applications
A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection
A universal quad AFE with integrated filters for VDSL, ADSL, and G.SHDSL
A 750Mb/s 12pJ/b 6-to-10GHz Digital UWB Transmitter
Design and Optimization of Low Power and Low Light Sensor: (Invited)
Microsystems for biomedical and sensing applications
Analyzing the impact of supply and substrate noise on jitter in Gb/s serial links
Shared fuse macro for multiple embedded memory devices with redundancy
Low power cryogenic RF ASICs for quantum computing
SP: an advanced surface-potential-based compact MOSFET model
3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%
A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations
470 MHz digital filter on delta-sigma modulated signals
A 14.08 -Gb/s 256 -QAM 60 GHz Phased-Array Transceiver with Switchable Tertiary-Coil Transformer T/R Switch and Customizable-Sized Cascade Phase-Invariant VGAs
A low-power and low-noise CMOS prescaler for 900 MHz to 1.9 GHz wireless applications
An Interference-Resilient 120-Degree-Apart Pseudo-I/Q BLE-Compliant Wake-Up Receiver Achieving -21dB SIR, -94dBm Sensitivity, and 4-D Wake-Up Signature
A dynamically reconfigurable ECG analog front-end with a 2.5 × data-dependent power reduction
A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS
Clock-gated harmonic rejection mixers
Incremental Delta-Sigma Structures for DC Measurement: an Overview
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory
A fully synthesized 0.4V 77dB SFDR reprogrammable SRMC filter using digital standard cells
Digital detection of parametric faults in data converters
A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS
A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012
High performance RF-filters suitable for above IC integration: film bulk-acoustic- resonators (FBAR) on silicon
A 2.4-GHz low-power all-digital phase-locked loop
A Closed-Loop EMI Regulated GaN Power Converter with 500MHz-Sampling-Bandwidth In-Situ EMI Sensing and 9kHz-Resolution Global Excess-Spectrum Modulation
A Low Cost 100 MHz 2-Stage PSiP and Evolution to a Co-Packaged/Fully-Integrated Voltage Regulator for SoC Power Delivery
A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz
1/5 power reduction by global optimization based on fine-grained body biasing
Session 19 - High performance and low power frequency generation
A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3 rd -order Multi-Input Filter and a PVT-Robust Ratio-Based FIA
An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects
A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration
A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture
Design of low power CMOS ultra-wideband 3.1-10.6 GHz pulse-based transmitters
A 1.5mW 16b ADC with improved segmentation and centroiding algorithms and litho-friendly physical design (LFD) used in space telescope imaging applications
32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL
A 1 V, 8 GHz CMOS integrated phase shifted transmitter for wideband and varying envelope communication systems
The virtual chip set: a parametric IP library for system-on-a-chip design
Technology Scaling of ESD Devices in State of the Art FinFET Technologies
A 610-MHz FIR Filter Using Rotary Clock Technique
Overview of low-power wake-up radio design insights
A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs
Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS
A 3.9 mW, 35-44/41-59.5 GHz distributed injection locked frequency divider
Emerging technologies for unique applications
A 2.5 Gbps CMOS optical receiver analog front-end
A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET
CAD Techniques for Power Optimization in Virtex-5 FPGAs
Advances in 3D design and optimization
Complete mixed-signal building blocks for single-chip GSM baseband processing
A 2-24GHz 360° full-span differential vector modulator phase rotator with transformer-based poly-phase quadrature network
25-nA Modified Hybrid Ladder Converter with Efficient Output-Capacitor Charge Recycling and 90% Battery Lifetime Extension
A 1-V Diode-Based Temperature Sensor with a Resolution FoM of 3.1pJ•K 2 in 55nm CMOS
Introduction to Compute-in-Memory
The μPP ASIC: design, methodologies and tools for a pay phone system-on-a-chip based on an ARM core and design reuse
On-chip transformer design and application to RF and mm-wave front-ends
FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit
Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era
A 0.14mW/Gbps high-density capacitive interface for 3D system integration
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
A Real-Time Feedback Controlled Hearing Aid Chip with Reference Ear Model
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology
Statistical modeling and post manufacturing configuration for scaled analog CMOS
Energy-efficient wireless front-end concepts for ultra lower power radio
Split capacitor DAC mismatch calibration in successive approximation ADC
A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors
A CMOS 22k-pixel single-cell resolution multi-modality real-time cellular sensing array
Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors
Advanced MOS modeling techniques
Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video
Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces
3D ICs and 3D systems
Factors influencing the design of microsystems
A Phase-Locked Minimum-Energy-Point-Tracking Enabled by Unified-Clock-Power-and-Body-Bias Slack Regulation and PI-Ratio Based In-Situ Loop Gain Optimization with 97.4% Supply Voltage Margin Recovery at Minimum-Energy-Point in 28nm FDSOI
GHz Serial Passive Clock Distribution in VLSI Using Bidirectional Signaling
A 9V-Tolerant 71.4%-Efficiency Stacked-Switched-Capacitor Stimulation System with Level-Adaptive Switching Control and Rapid Stimulus-Synchronized Charge Balancing
A heterogeneous functional verification platform
Embedding DRAM in single chip MPEG1 codec LSI
A 28nm 1.07TFLOPS/mm 2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing
10-b 100-MS/s Two-Channel Time-Interleaved Pipelined ADC
Time-Variant Characterization and Compensation of Wideband Circuits
Structuring residuals by faults structural decoupling from bicausal diagnostic bond graph
Multi-class SVMs analysis of side-channel information of elliptic curve cryptosystem
Vertical scalability benchmarking in three-dimensional virtual world simulation
Self-learning adaptive algorithm for maritime traffic abnormal movement detection based on virtual pheromone method
Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems, Chicago, IL, USA, July 26-29, 2015
CAEDISI: a cellular automata editor and simulator for network decontamination
An architecture to support integrated manikin-based simulations
The reference model uses object oriented population generation
Building the virtual product with big models
Implementation and simulation of dynamic models: a concise reading of the relationships bond graphs - block diagrams
Low latency network traffic processing with commodity hardware
Efficient network level beamforming training for IEEE 802.11ad WLANs
Intelligent simulation models based on business rules approach in banking sector (WIP)
Emerging modeling and simulation technologies needed to implement cultural familiarization training in virtual environments (WIP)
Solving the problem of efficient gas delivery with aid of decision support system: BPsim.DSS based on simulation modeling
Multi-objective optimization and analysis of the inventory management model
Histogram cloning and CuSum: an experimental comparison between different approaches to anomaly detection
Cyber modeling & simulation for cyber-range events
An analysis on the metrics for dynamic process scheduling on distributed simulation using optimistic protocols
New insights on river crossing operation using rafts by modeling and simulation (WIP)
An agent based exploration of a relationship between daily routines and convenience store footfalls
The impact of climate condition on the optimal size of direct coupled photovoltaic-electrolyzer systems
Management of non-conformant traffic in OpenFlow environments
Healthcare system process improvement: a systems engineering approach (WIP)
Video-guided versus direct laryngoscopy: considerations for using simulation to teach inexperienced medical students
The comparison of high definition versus stereoscopic display on standardized fundamental laparoscopic skill procedures
Towards visulations of astrophysical accretion disk on HPC clusters with AccretionSim
Movement analysis in laparoscopic surgery training
Modeling cognitive radio networks in NetLogo
A novel augmented reality simulator for minimally invasive spine surgery
Nonlinear modeling and analysis of electromechanical actuator
Transient analysis of railway tracks for low frequency vibrations: the bridge end problem (work in progress version)
New caching algorithms performance evaluation
The optimal cloud services portfolio simulation in matlab environment
Development of the energy hub networks based on distributed energy technologies
Harnessing emergence: the control and design of emergent behavior in system of systems engineering
Computational modeling of the effects of counterfeit components
Effect of thermal sintering and poisoning on light-off performance of zoned Pt-Pd/ diesel oxidation catalysts
Production control and optimization
An optimization model for assessing multi-products productions from biomass: a case of renewable Malaysian oil palm empty fruit bunch (EFB)
Thermography for in-vivo wound healing models
Applications of angiosome classification model for monitoring disease progression in the diabetic feet
Development and application of system complexity measures for use in modeling and simulation
The computer assisted surgical trainer: design, models, and implementation
Proceedings of the International Conference on Bond Graph Modeling and Simulation, ICBGM@SummerSim, Montreal, QC, Canada, July 24 - 27, 2016
MOKA: an object-oriented framework for FMI co-simulation
Variable intensity RCPSP approach to a case study flow shop
Adaptive particle filtering in data assimilation of wildfire spread simulation
An accurate, nonlinear model and control of hybrid actuation system (WIP)
Exploring norm establishment in organizations using an extended axelrod model and with two new metanorms
Virtual enterprise synthesis by web services composition with HTN-like parsing algorithm (WIP)
A physically intuitive yaw-plane bond graph model for vehicle active safety system design
Load balancing probabilistic spectrum handoff for cognitive radio networks
A predictive analytics toolbox for medical applications
SIFT's scale-space extrema detection on GPU for real-time applications (WIP)
Simulation experiments: better insights by design
A study on software reliability prediction based on triple exponential smoothing method (WIP)
Agent-based modeling and simulation of the emotional experiences of employees within organizations
Extension of Lagrangian-Hamiltonian mechanics: Umbra Poisson bracket using bond graphs
Definition of essential order on descriptor systems and its bond graph determination
Fiber tractography for finite-element modeling of transversely isotropic biological tissues of arbitrary shape using computational fluid dynamics
Optimal porosity design for gas diffusion layers of hydrogen fuel cells
Incorporating reflection for real-time multi-configuration haptic-interactive virtual environments
Developing a low-cost multi-modal simulator for ultrasonography training
Bio-inspired exploring and recruiting tasks in a team of distributed robots over mined regions
Executable models of fissile reactor systems for hardware simulation and design
Dynamic structural analysis for DAEs
Bond graphs aided development of mechanical power transmission for aerospace electromechanical actuators
Multi-layer sociality in opportunistic networks: an extensive analysis of online and offline node social behaviors
Agent-based modeling and simulation of pooled warehouse intelligent management
Towards sonic urban morphologies: a modeling Nexus (WIP)
Energy-efficient optical HPC and datacenter networks using optimized wavelength channel allocation
The next generation of modeling & simulation: integrating big data and deep learning
Using sectioning to construct confidence intervals for quantiles when applying antithetic variates
Simulation for higher education sustainability
Shared-files parallel simulation framework for dynamic multi-domains networks using OMNeT++ (WIP)
Simulation validation using metamorphic testing (WIP)
OpenMalaria and EMOD: a case study on model alignment
Human modeling for multi coalition joint operations
Using cadaver simulation to improve communication and economy of movement as evidence of progress with the trans-catheter aortic valve implantation (TAVI) learning curve
OpenCounter: counting unknown flows in software defined networks
On estimation of optical properties in near infrared spectroscopy with use of cumulative distributions of times of flight of photons
The SILAS model: sexual infections as large-scale agent-based simulation
Multi-body dynamics modeling & control of quadrotor helicopter using bond graph
Robust fault tolerant control of wind turbine benchmark model
Simulation of OpenFlow scenarios based on NSDL and NS-3
Efficient broadcasting for route discovery in mobile ad-hoc networks
Service-oriented model composition
A driving simulator for discovering requirements in complex systems
Linear dynamic adaptation of the BW granularity allocation for elastic optical OFDM networks
Two bare-bones simulations of human-controlled systems
Co-simulating event-B and continuous models via FMI