ABSTRACT Given a fixed CPU architecture and a fixed DRAM timing specifica- As many recent studies have shown, the memory system is one of the primary bottlenecks in current systems. Further, a number of studies show that, within the memory system, the memory bus accounts for a substantial portion of the primary memory's overhead. For example, Schumann reports that, in Alpha workstations, 30-60% of primary memory latency is attributable to system overhead rather than to latency of DRAM components [22] . Brown and Seltzer cite memory-bus turnaround as responsible for a factor-oftwo difference between predicted execution time and actual measured execution time on a Pentium There are a number of paths developers and researchers have taken to reducing the overhead of the primary memory system. These have largely been divided into approaches that are focussed on the DRAM component and those that are focussed on the system or bus component. For example, a simple DRAM-oriented approach has been to increase DRAM bandwidth. This is the tack taken by the PC industry recently, with the widespread shift from 800 MB/s PC100 SDRAM systems to 1.1 GB/s PC133, 1.6 GB/s Direct Rambus, and 2.1 GB/s DDR266 SDRAM systems. This brings the memory bandwidth of the PC up to that of traditional RISC workstations, such as several UltraSPARC and Alpha models, and to within an order of magnitude of many server-class machines. Another approach is to reduce DRAM latency. DRAM vendors have recently announced numerous core variations that improve access time. For example, Enhanced Memory System's ESDRAM improves performance over regular SDRAM by adding an SRAM cache for the full row buffer, thereby allowing precharge to begin immediately after an access and DRAM writes to go directly to the core without destroying read locality [5, 7, 6 ]. Fujitsu's FCRAM subdivides each internal bank by activating only a portion of each word line, thereby reducing capacitance on the word access and improving access time over that of standard SDRAM to roughly 30ns [9, 10] . MoSys takes this a step further and subdivides the onchip storage into a large number of very small banks (on the order of 32KB each), reducing the access time of the DRAM core to nearly that of SRAM [39, 19, 10] . Several vendors have placed large amounts of SRAM onto the DRAM die, in addition to the row buffers, in an attempt to reduce latency. For example, NEC'S VCDRAM places a set-associative SRAM buffer on the die that holds an implementation-defined number of sub-page (typically 10-100), where a sub-page is a subset of the bits activated by a column access and is on the order of 16-32 bytes [6, 10] . Recent studies show that these DRAM-oriented approaches do reduce application execution time [5, 7] . However, focussing on the DRAM alone is not enough; we note that, even with zero-latency DRAM access, the overhead of the primary memory system would not reduce to zero, because bus transactions still require time. To begin with, there is the obvious time to transfer addresses and data over the bus to and from the DRAM subsystem. In addition, factors such as turnaround time, queueing delays, and inefficiencies due to asymmetric read/write request shapes on an in-order bus all add together to produce a sizable overhead. In multiprocessor systems, the overhead is even larger, due to arbitration and cache coherency protocols-moreover, many uniprocessor systems share the memory bus with graphics chips in an organization that effectively makes the uniprocessor system behave like a multiprocessor. In addition to efforts aimed at improving DRAM devices, we must also improve the connection between the CPU and the DRAM devices-we must improve the overhead of the memory bus. There are a number of approaches one can take, including changing the
Cupu and Jacob REF have investigated mechanisms to reduce request latency and the portion of the main memory systems overhead that is not due to DRAM latency, but rather to other factors.
Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance?
Proceedings 28th Annual International Symposium on Computer Architecture
Proceedings 28th Annual International Symposium on Computer Architecture
Computer Science