Abstract-In this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. We compare the performance of our proposal with a vector system without PVMC as well as a scalar only system. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 2.2x to 14.9x faster, achieves between 2.16x to 3.18x of speedup for 5 applications and consumes 2.56 to 4.04 times less energy.
Hussain et al. proposed a vector architecture called programmable vector memory controller (PVMC) REF and its implementation on an Altera Stratix IV 230 FPGA device.
PVMC: Programmable Vector Memory Controller
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors
Computer Science