Abstract-In this paper, we present a partitioning, mapping, routing and interface optimization framework for energy-efficient voltage-frequency island (VFI) based networks-on-chip. Unlike the recent work that performs tile partitioning only with voltage-frequency assignment for a given mesh network layout, our framework consists of three key VFI-aware components, i.e., VFI-aware core partitioning with voltage and frequency assignment, VFI-aware mapping, and VFI-aware routing path allocation. In addition, we develop a VFI interface and its insertion algorithm to easily satisfy performance constraints. Our methodology makes cores using the same voltage and frequency unified to single VFI. Thus, our technique considerably reduces VFI overheads such as a mixed clock first input, first output buffer and a voltage level converter up to 82% and energy consumption up to 10% compared with the state-of-the-art work. It proves that our global energy optimization framework achieves better power-performance trade-offs. Index Terms-Network-on-chip (NoC), system-on-chip (SoC), voltage-frequency island (VFI).
In REF , Jang et al. construct the framework for energy-efficient VFI-aware partitioning, mapping and routing.
A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Computer Science