Abstract. We present an approach to designing veri ed digital systems by a sequence of small local re nements. Re nements in this approach are not limited to a library of prede ned transformations for which theorems have been previously established. Rather, the approach relies on localizing the re nement steps in such a way that they can be veri ed e ciently by model checking. Toward this end, a compositional rule is proposed by which each design re nement may be veri ed independently, in an abstract environment. This rule supports the use of downward re nement maps, which translate abstract behavior detailed behavior. These maps may involve temporal transformations, including delay. The approach is supported by a veri cation tool based on symbolic model checking.
McMillan REF proposes a compositional rule for hardware verification based on local refinements which can be efficiently model checked.
A Compositional Rule for Hardware Design Refinement
CAV
Computer Science