Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, system decomposition, communication and MAC protocols, and low power short range networks. Keywords: low power, system architecture, mobile computing, wireless communication. The requirement of portability of hand-held computers and portable devices places severe restrictions on size and power consumption. Even though battery technology is improving continuously and processors and displays are rapidly improving in terms of power consumption, battery life and battery weight are issues that will have a marked influence on how hand-held computers can be used. These devices often require real-time processing capabilities, and thus demand high throughput. Power consumption is becoming the limiting factor in the amount of functionality that can be placed in these devices. More extensive and continuous use of network services will only aggravate this problem since communication consumes relatively much energy. Research is needed to provide intelligent policies for careful management of the power consumption while still providing the appearance of continuous connections to system services and applications. Over the past two decades the semiconductor technology has been continuously improved and has lead to ever smaller dimensions of transistors, higher packaging density, faster circuits, and lower power dissipation. The trend is expected to continue beyond the year 2000. Over the past five years, feature sizes have dropped from about f=0.8µ to about f=0.35µ. Semiconductor Industry Associates (SIA) have developed a road map for the next few years (see figure 1 ). It is expected that a feature size of f=0.1µ will be reached in 2007 within the context of our current CMOS technology. Such advances provide an effective area increase of about an order of magnitude. To avoid the effect of high electric fields which would be present in very small devices, and to avoid the overheating of the devices, power supply must be scaled down. The power supply voltage is expected to be as low as 1.2 V in 2007. This rapid advance in technology can be used for several goals. It can be used to increase performance, to add functionality, but also to reduce energy consumption. The current trend is to focus on high performance processors as this is the area in which a semiconductor vendor can enhance its status [5] . Therefore, the architecture of a general purpose processor is most 2 widely studied, and optimizations for processor performance is the main goal. The advance in technology has lead to a number of processor improvements like superscalar technology, reduction in cycle time, large on-chip caches, etc. However, another environment that will rapidly become more important in the near future is that of application specific or embedded processors. The goal of these processors is to optimize the overall cost-performance of the system, and not performance alone. The modern application specific processors can use the same technology to increase functionality to provide services such as compression and decompression, network access, and security functions. For example, instead of the compromise of including 'main memory' on the chip, one could explicitly include dedicated memory space for the functional units. This memory can be used locally for network buffers, video buffers, etc. In this way the data flow in the system is reduced and a bottleneck (access to main memory) is avoided. This is also a good example of how area space can be used to decrease energy consumption as by exploiting this locality of reference, the energy consumption of the system is reduced as well. In fact, many energy reduction techniques will show to have the trade-off between chip area and energy consumption.
Low-power electronics, power-down modes, and energy efficient modulation are examples of work in this category REF .
Design techniques for low-power systems
Journal of Systems Architecture
Computer Science