Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardware to form a two-dimensional (2D) page walk, which reduces the need for hypervisor intervention in guest page table management. However, the extra dimension also increases the maximum number of architecturally-required page table references. This paper presents an in-depth examination of the 2D page table walk overhead and options for decreasing it. These options include using the AMD Opteron TM processor's page walk cache to exploit the strong reuse of page entry references. For a mix of server and SPEC R benchmarks, the presented results show a 15%-38% improvement in guest performance by extending the existing page walk cache to also store the nested dimension of the 2D page walk. Caching nested page table translations and skipping multiple page entry references produce an additional 3%-7% improvement. Much of the remaining 2D page walk overhead is due to lowlocality nested page entry references, which result in additional memory hierarchy misses. By using large pages, the hypervisor can eliminate many of these long-latency accesses and further improve the guest performance by 3%-22%.
To reduce these overheads AMD REF proposed accelerating 2D page walks using nested page walk caches which cache frequently used levels of the page walk in hardware, greatly reducing the overheads of TLB miss.
Accelerating two-dimensional page walks for virtualized systems
ASPLOS
Computer Science