Abstruct-Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the U 0 little has been specifically done for decreasing the U 0 power dissipation. We propose the Bus-Znvert method of coding the U 0 which lowers the bus activity and thus decreases the U 0 peak power dissipation by 50% and the U 0 average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power.
In REF , Limited Weight Coding for low-power bus was proposed which limits the number of transitions in the bus and hence reduce the dynamic power dissipation caused by these transitions.
Bus-Invert Coding for Low-Power I/O
IEEE Transactions on VLSI systems
Computer Science