Abstract| Memory hierarchies have long been studied b y many means: system building, trace-driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly size the di erent levels in a memory hierarchy to a rst-order approximation. In this paper, we present a simple analysis for providing this practical help and some unexpected r esults and intuition that come out of the analysis. By applying a speci c, parameterized m o del of workload locality, we are able to derive a closed-form solution for the optimal size of each hierarchy level. We verify the accuracy of this solution against exhaustive simulation with two case studies: a three-level I O storage hierarchy and a three-level processor-cache hierarchy. In all but one case, the con guration recommended by the model performs within 5 of optimal. One result of our analysis is that the rst place t o s p end money is the cheapest rather than the fastest cache level, particularly with small system budgets. Another is that money spent on an n-level hierarchy is spent in a xed p r oportion until another level is added. Keywords| c ache, memory, and storage hierarchies; tracedriven simulations; optimization of cache con gurations.
Jacob et al . developed a closed form solution for optimal size of each cache level and suggested that the cheapest memory level be increased in the first place REF .
An Analytical Model for Designing Memory Hierarchies
IEEE Transactions on Computers
Computer Science