There exists a huge market for application specific processors used within embedded systems. This market is driven by consumer requirements (e.g., new products, more functionality and flexibility, product digitalization, better performance-cost ratio, portability) and processor design capabilities (i.e., what can we offer). Being successful within this market requires a short time-to-market; this necessitates usage of automated design tools. These tools should not only assist in the quick generation of a specific processor, but also enable the designer to investigate quickly, and quantitatively, a large set of alternative solutions. Therefore, these tools should be based on a flexible and programmable processor template. In this paper we propose the usage of Transport Triggered Architectures (TTAs) for such a processor template. TTAs can be compared to VLIWs; both can exploit the compile-time available instruction level parallelism. However, TTAs are programmed differently. TTAs combine a set of interesting features; apart from being fully programmable, they have favorable scaling characteristics, they easily incorporate arbitrary functionality, and their organization is well structured, allowing simple and automatic design. The paper explains these features. Based on this template a set of design tools has been developed; they include a parallelizing C/C++ compiler which exploits the available processor and application concurrency, a processor generator, simulators, profilers, and a tool for architecture exploration; these tools are integrated within a graphical user interface. Within the paper we shortly describe these tools and demonstrate how they can be applied to a particular application. This example application is taken from the image processing area. It will be shown how the tools assist in exploring many solutions, including those which incorporate application specific functionality.
Another architecture that exposes more details of the datapath to the compiler is the Transport-Triggered Architecture (TTA) REF .
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Computer Science