Abstract -This paper proposes a novel technique for powerperformance trade-off based on profile-driven code execution. Specijkally, we show that there is an optimal level of parallelism for energy consumption and propose a compiler-assisted technique for code annotation that can be used at run-time to adaptively trade-off ower and performance. As shown by experimental results, our approach is up to 23% better than clock throttling and is as efficient as voltage scaling (up to 10% better in some cases). The technique proposed in this paper can be used by an ACPI-compliant power manager for prolonging battery lfe or as a passive cooling feature for thermal management. Power dissipation has become a critical design concem in recent years, driven by the increased levels of complexity and emergence of mobile applications. While it is generally agreed that tools for power estimation and optimization do exist for hardware specifications at different levels (circuit, gate, register-transfer or behavioral), more work is needed in the area of power analysis or optimization at microarchitecture, architecture or system level [I]. Having tools that are able to quantify the effect of different performance or power optimization schemes for a piece of code running on a given processor is of extreme importance for computer architects and compiler engineers who can characterize different architecture styles not only in terms of their performance, but also in terms of the corresponding energy efficiency. In the area of power modeling for embedded software, [2] proposes a per-instruction base power model that can be used to find an aggregate power estimate for a sequence of instructions. In [3], the case of DSP applications is addressed. There, the inter-instruction effects tum out to be significant, thus making possible to develop instruction scheduling techniques that target power minimization. The authors of [4] present an architectural enhancement to reduce the extra work or energy due to mispredicted branches, without significant loss in performance. In [5] a technique for reducing the average power consumption for the pipeline structure is presented. Other approaches target techniques for energy efficient memory systems [6, 7] . From a different perspective, the aspect of thermal management has been addressed in [8] where a hardwaredriven technique for instruction cache throttling has been proposed. In this paper we address the problem of energy optimization in modem processors by using compiler-assisted code annotation for variable fetch or execution rate. We improve the state-of-the-art by proposing a novel technique forfine-grain energy characterization based on aprofile-driven code execution methodology. Specifically, we show analytically and experimentally that there exists an optimal level of parallelism for energy consumption (which may not be the same as the one for performance) and propose a compiler-assisted technique for code annotation that adaptively selects at run-time the optimal number of instructions to be fetched or executed in parallel as far as energy is concemed. Energy, as opposed to performance, is a much more data-dependent parameter. As it will be shown subsequently, it is indeed possible to use less than the maximum number of functional units available, and achieve less energy consumption. We study this effect for the execution stage, as well as for the entire processor. For the first time to our knowledge, we show that there exists an inherent trade-off between performance and energy consumption, due to the data-dependency effect, but, most importantly, due to speculative execution and the inherent level of parallelism exhibited by common applications. To validate our results, we use a microarchitecture-level power simulator developed in industry [9]. As shown subsequently, significant savings can be obtained in both energy and power consumption, at the expense of some decrease in performance. The techniques described in this paper can be used as a means for prolonging the battery lfe, but most importantly, for thermal management [IO] by achieving significant average power reductions in the execution stage or throughout the chip. Such an approach could be used in the context of power management schemes using the Advanced Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. lSLPEI) '00, Rapallo, Italy. Copyright 2000 ACM 1-581 13-190-9/00/0007 ... $5.00. . Thermal management in ACPI is achieved via average power reduction through "clock throttling" in the case ofpassive cooling, or by tuming on the on-chip fan in the case of active cooling. However, both techniques are likely to actually decrease the battery life by consuming more energy, although the average power per cycle is decreased. Our proposed technique is up to 20% more efficient than the classic clock throttling technique and also reduces the total energy consumed, being in some cases 10% better than voltage scaling. Also, as opposed to the instruction cache throttling technique presented in [8], our characterization is sofiware-driven and provides a fine grain energy characterization on aper basic block, per process basis. The paper is organized as follows: Section 2 presents the rationale for profile-driven code execution. In Section 3, we present our methodology for code-annotation for low energy. Section 4 shows our experimental results and we conclude in Section 5 with some final remarks. In superscalar processors, the hardware may execute from one to eight instructions per cycle. Usually, these instructions must be independent and satisfy some constraints. If a certain instruction is dependent or doesn't meet the constraints, only the instructions preceding it in the sequence are issued, hence the variability in issue rate. If, in addition, out-of-order execution of instructions is permitted, any of the succeeding instructions may be executed if there are no data dependencies present. Let us consider the case of an in-order execution of a computationintensive piece of code. We show subsequently how the total energy per operation is decreased by trading-off performance for power. Example 1. Consider the computation of the product of two input streams (ffom a real DSP application) and the availability of up to four Idbit multipliers able to perform the multiplication. We consider four possible scenarios corresponding to using one, two, three or all of the functional units. The four scenarios, labeled with the corresponding total energyper operation, are depicted in Fig.1 . (It is assumed that the input stream x, includes both operands.) As it can be seen, the energy consumption per operation varies significantly among the four scenarios. This is mainly due to the very different profile of the data that is sent to each of the available functional units. Also, when comparing the performance, we can see that using four multipliers gives the largest performance (4 computations per clock cycle), but using two multipliers reduces the total energy by more than 32% and average power by 65%, when compared to the worst case. Fig.1 Four ways of computing a series of multiplications This type of behavior is actually found very eequently in practice, especially in computation intensive applications. These effects become even more important in the case of DSP processors where most of the power consumption is due to the datapath performing additions or multiplications. Another scenario where this effect may become prevalent is the one of a mix of loadktore and arithmetic instructions that alternatively use the same functional units for computing effective addresses and output values. Typically, memory addresses look much more "different" than the operands of arithmetic instructions and thus, a behavior similar to the one shown above will arise. However, in superscalar processors, the contribution of the datapath to the total energy consumption may not be impressive. More precisely, the fetch and issue stages which actually schedule and dispatch instructions to the execution stage have a significant contribution to the total energy consumption.
Marculescu proposes a mechanism to dynamically adapt the fetch and execution bandwidth based on a profiling at the basic-block level REF .
Profile-driven code execution for low power dissipation
ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)
ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)
Computer Science