Branch prediction is the predominant approach for minimizing the pipeline breaks caused by branch instructions. Traditionally, branch prediction is accomplished in one of two ways, static prediction at compile-time via compiler analysis or dynamic prediction at run-time via special hardware structures. In this paper, we propose a novel technique that aims to combine the strengths of the two approaches -the lower cost of compile-time analysis with the eflectiveness of d y m i c prediction. Specifically, we propose that the compiler use projile feedback to dejine a prediction function for each branch and insert a f a v explicit instructions per branch into the compiled code to compute the prediction function. These instructions are carefully selected to predict the direction of the branch using any information available during run-time. A strength of this approach is that information beyond branch history can be used to make predictions, such as the contents of the architectural registers. To substantiate our proposal, we present an algorithm for selecting the prediction instructions, and demonstrate the pegormance of the approach against contemporary static and dynamic branch prediction strategies.
In REF , compiler defines a prediction function for each branch, and inserts instructions for computing prediction function.
Compiler synthesized dynamic branch prediction
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
Computer Science