Abstract: The possibility of using flexible and cost-efficient commodity hardware instead of expensive custom hardware has triggered wide interest in software routers. Performance measurement and simulation are important approaches for identifying bottlenecks of such systems to predict and improve the performance. We measure the performance of software routers using current multi-core hardware architectures. We introduce an innovative and validated node model for intra-node resource contention and realized a resource management extension for the widely-used network simulator ns-3 which allows to evaluate and predict the performance of current and future software router architectures.  The performance of commodity PC hardware has increased rapidly. Therefore, it becomes feasible to use off-the-shelf systems as servers or routers. For instance all Unix-based systems are capable of basic routing functionality. Every PC can be transformed into a software router with the aid of special software or by selecting an appropriate operating system (OS). Thereby commodity hardware is more cost-efficient than specialized hardware solutions and network components. Leveraged by high flexibility and low costs of software developments in comparison with hardware developments, software solutions are preferred in many scenarios. While this advantage may be counterbalanced by the higher performance and lower energy consumption of specialized hardware, the arguments of higher flexibility and better cost-efficiency still remain. Software routers allow rapid deployment of new features that require a considerably more expensive and timeconsuming development cycle when implemented by dedicated hardware. For instance, the IETF NETCONF WG or the Open Networking Foundation implemented new approaches for the configuration of network devices in software, whereas hardware implementations were not available in the early stage. Nevertheless the benefits of software routers come with the drawback of smaller number of ports and lower performance. Approaches like RouteFlow [1] combine the flexibility and routing functionality of software routers with the forwarding performance of hardware OpenFlow switches. Thereby the best of both worlds can be achieved in one system: a comparatively cheap routing system with the performance and scalability of dedicated networking hardware that has the flexibility of software routers. Researches have shown that the performance of specialized routing hardware is within the reach of software routers [2], [3] . For the use of computer systems in high-speed networks the traffic of 1 Gbps, 10 Gbps, and higher speed networks has to be managed. Systems have to be able to cope and handle this traffic without loss of data. Bus systems must guarantee the required data rates between the hardware components. Depending on the type of routing tasks, the OS has to do diverse complex treatments per packet. In order to improve the performance it is necessary to understand packet processing limitations in PC systems in detail. Achieved performance gains can indeed be explained qualitatively on the basis of the hardware architecture and the processes in the OS, but there is a lack of models that could explain the results quantitatively or even predict them. A good model provides a simple way to gain insight into complex packet processing tasks. This model should be scalable and applicable for manifold simulation scenarios which cannot be provided in real testbeds. In this paper, we measure and simulate the performance of software routers based on current multi-core systems. Hence, we apply our general concept for realistic modeling of resource contention in resource-constrained nodes. Our modeling approach is implemented as a resource management module for the network simulator ns-3. After calibrating and validating our model based on our testbed measurements, we evaluate and predict the performance of existing and future software router architectures. This paper is an extended and revised version of [4] .
We also studied the performance of software routers to show the linear scaling of packet processing performance with multi-core CPUs REF .
Validated Model-Based Performance Prediction of Multi-Core Software Routers
PIK - Praxis der Informationsverarbeitung und Kommunikation
Computer Science