We implement and experimentally evaluate the timeliness and energy consumption behaviors of fourteen Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) schedulers on two hardware platforms. The schedulers include CC-EDF, LA-EDF, REUA, DRA, and AGR1, among others, and the hardware platforms include the Intel i5 processor and the AMD Zacate processor. Our studies reveal that measuring the CPU power consumption as the cube of CPU frequency -as often done in the simulation-based RT-DVFS literature -ignores the idle state CPU power consumption, which is significantly smaller than the active power consumption. Consequently, power savings obtained by optimizing active power (i.e., RT-DVFS) is offset by completing tasks sooner by running at high frequency and quickly transitioning to the idle state (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniques' revealed by our measurements are significantly smaller than their simulation-based savings reported in the literature.
Saha and Ravindran REF have implemented fourteen DVS algorithms in the ChronOS real time Linux kernel and evaluated their energy efficiency on two hardware platforms, including an Intel i5 processor and an AMD Zacate processor.
An experimental evaluation of real-time DVFS scheduling algorithms
SYSTOR '12
Computer Science