This paper explores area parallelism tradeo s in the design of distributed shared-memory DSM multiprocessors built out of large single-chip computing nodes. In this context, area-e ciency arguments motivate a heterogeneous organization consisting of few nodes with large caches designed for single-thread parallelism, and a larger number of nodes with smaller caches designed for multi-thread parallelism. Quantitative performance of such organization is reported for a set of homogeneous multiprocessor programs from the SPLASH-2 benchmark suite. These programs are mapped onto the heterogeneous processors without source c ode modi cations via static thread assignment policies. Simulationbased analysis is used t o c ompare the performance o f heterogeneous and homogeneous DSMs that occupy the same silicon area. The analysis shows that a 4-node heterogeneous DSM with 21 processors outperforms its homogeneous counterpart with 4 processors by an average of 36 for the studied multiprocessor workload, while having the same performance for sequential codes. A sensitivity analysis based on a factorial design experiment is used to study the implications of processor, memory, and network heterogeneity on overall cost and performance of a heterogeneous DSM. The studied benchmarks are a ected, on average, primarily by heterogeneity in processor performance 59.3, followed by cache sizes 18.2, memory latency 14.6, and network latency 5.6.
In REF the authors address the impact of heterogeneity on distributed shared memory systems, and assume the presence of few nodes with large caches for supporting single-thread parallelism, and many nodes with smaller caches for multi-thread parallelism.
Impact of heterogeneity on DSM performance
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)
Computer Science