The vector-thread (VT) architectural paradigm unifies the vector and multithreaded compute models. The VT abstraction provides the programmer with a control processor and a vector of virtual processors (VPs). The control processor can use vector-fetch commands to broadcast instructions to all the VPs or each VP can use thread-fetches to direct its own control flow. A seamless intermixing of the vector and threaded control mechanisms allows a VT architecture to flexibly and compactly encode application parallelism and locality, and a VT machine exploits these to improve performance and efficiency. We present SCALE, an instantiation of the VT architecture designed for low-power and high-performance embedded systems. We evaluate the SCALE prototype design using detailed simulation of a broad range of embedded applications and show that its performance is competitive with larger and more complex processors.
REF propose the vector-thread architecture exposing two instruction fetch mechanism in the ISA: vector-fetch and thread-fetch.
The vector-thread architecture
Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.
Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.
Computer Science