In this paper we evaluate the trade-offs between various lowleakage design techniques for field programmable gate arrays (FGPAs) in deep sub-micron technologies. Since multiplexers are widely used in FPGAs for implementing look up tables (LUTs) and connection and routing switches, several low-leakage implementations of pass transistor based multiplexers and routing switches are proposed and their design trade-offs are presented based on transistor-level simulation, physical design, and impact on overall system performance. We find that gate biasing, the use of redundant SRAM cells, and integration of multi-Vt technology are ideal for FPGAs, and they can reduce leakage current by 2X-4X compared to an implementation without any leakage reduction technique. For some of the potential low-leakage design techniques being evaluated in our study, the impact on chip area is very minimal to an increase of 15% − 30%. FPGA, leakage power, and multiplexer.
REF evaluate several low-leakage design techniques for FPGAs and show that using multiple Vt switch blocks reduces leakage significantly.
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04
Computer Science