In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, tc. 7st access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the ,same time, which were traditionally dealt with as separate problems. Experimental results shows the efJiciency and the usefulness of the proposed technique.
Larsson and Peng propose in REF a framework for SOC testing which considers test time minimization, TAM optimization, test set selection and test resource placement, along with test resources and power consumption constraints.
An integrated system-on-chip test framework
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
Computer Science