Abstract-This paper presents an FPGA emulation-based fast Network on Chip (NoC) prototyping framework, called Dynamic Reconfigurable NoC (DRNoC) Emulation Platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown.
An FPGA emulation-based NoC prototyping framework is presented, where the main goal is to speed up the synthesis process by partial reconfiguration of hard cores REF .
A Fast Emulation-Based NoC Prototyping Framework
2008 International Conference on Reconfigurable Computing and FPGAs
2008 International Conference on Reconfigurable Computing and FPGAs
Computer Science