Static power dissipation due to transistor leakage constitutes an increasing paction of the total power in modem semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level:
Butts and Sohi REF introduce a static energy model for estimating static power consumption early in the design process at the architectural level.
A static power model for architects