Abstract: Reducing the design complexity of switches is essential for cost reduction and power saving in on-chip networks. In wormhole-switched networks, packets are split into flits which are then admitted into and delivered in the network. When reaching destinations, flits are ejected from the network. Since flit admission, flit delivery and flit ejection interfere with each other directly and indirectly, techniques for admitting and ejecting flits exert a significant impact on network performance and switch cost. Different flit-admission and flit-ejection microarchitectures are investigated. In particular, for flit admission, a novel coupling scheme which binds a flit-admission queue with a physical channel (PC) is presented. This scheme simplifies the switch crossbar from 2p Â p to ( p þ 1) Â p, where p is the number of PCs per switch. For flit ejection, a p-sink model that uses only p flit sinks to eject flits is proposed. In contrast to an ideal ejection model which requires p . v flit sinks (v is the number of virtual channels per PC), the buffering cost of flit sinks becomes independent of v. The proposed flit-admission and flit-ejection schemes are evaluated with both uniform and locality traffic in a 2D 4 Â 4 mesh network. The results show that both schemes do not degrade network performance in terms of average packet latency and throughput if the flit injection rate is slower than 0.57 flit/cycle/node.
Cost-effective flit admission and ejection blocks were presented in REF .
Admitting and ejecting flits in wormhole-switched networks on chip
IET Computers & Digital Techniques
IET Computers & Digital Techniques
Computer Science