Current network processors (NPs) are being successfully deployed in networking systems and a host of other surprising application areas. This broad deployment is at once strengthened by the high computational throughput of these devices and hindered by program size limitations in the embedded processors providing that throughput. In this paper, we propose the use of segmented instruction caches to remove program size restrictions for those programs that do not have realtime requirements without sacrificing the ability to provide guaranteed instruction delivery. In a segmented instruction cache, each thread is allocated a cache segment, or region, and any conflicts are restricted to within that segment. Several segment sizing strategies are introduced and evaluated, and profile-driven code scheduling is shown to often be effective at reducing miss rates for non-real-time code by between 10% and 60% over a set of benchmark programs.
Patrick Crowley has proposed a segmented instruction cache for network processors to meet its real-time requirement REF .
Supporting Mixed Real-Time Workloads in Multithreaded Processors with Segmented Instruction Caches
Network Processor Design
Network Processor Design
Computer Science