Abstract-The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video. Index Terms-Computer architecture, digital signal processors, very-large-scale integration, video signal processing.
al. REF describes the implementation of an optimized software MPEG-4 decoder on a programmable multi-core system-on-chip architecture, based on a detailed analysis of the bit-stream statistics.
Multicore system-on-chip architecture for MPEG-4 streaming video
IEEE Trans. Circuits Syst. Video Techn.
IEEE Trans. Circuits Syst. Video Techn.
Computer Science