Adding a small loop cache to a microprocessor has been shown to reduce .overage instruction fetch energy for various sets of embedded system applications. With the advent of core-based design, embedded system designers con now tune a loop cache architecture to best match a specipc application. We developed an automated simulation environment to find the best loop cache architecture for a given application and technology. Using this environment, we show significant variation in the best architecture for different examples. The results support the need for futurefast synthesis oftuned loop cache architectures.
Cotterell and Vahid REF develop an automated simulation environment to find the best loop cache architecture for a given application and technology.
Tuning of loop cache architectures to programs in embedded system design
15th International Symposium on System Synthesis, 2002.
15th International Symposium on System Synthesis, 2002.
Computer Science