Abstract I Tester The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In this paper, we introduce a novel and very efJicient lossless compression technique for testing systems-on-a-chip based on geometric shapes. The technique exploits reordering of test vectors to minimize the number of shapes needed to encode the test data. The effectiveness of the technique in achieving high compression ratio is demonstrated on the largest ISCAS85 and full-scanned versions of ISCAS89 benchmark circuits. In this paper, it is assumed that an embedded core will be used to execute the decompression algorithm and decompress the test data.
In REF , a test vector compression technique based on geometric primitives is proposed.
A geometric-primitives-based compression scheme for testing systems-on-a-chip
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001
Computer Science