Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error corrected description from a higher level quantum circuit for state of the art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that converts high level quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for fault-tolerant error correction. We call this form the (I)initialisation, (C)NOT, (M)measurement form (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive, deterministic array of CNOT operations and a series of time ordered X-or Z-basis measurements. The form allows a more flexbile approach towards circuit optimisation. At the same time, the package outputs a standard circuit or a canonical geometric description which is a necessity for operating current state-of-the-art hardware architectures using topological quantum codes. The construction and compilation of quantum algorithms has long been an active area of research [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] . Since the first work on designing circuits from abstract quantum algorithms [11] [12] [13] [14] [15] [16] [17] [18] , research has been centred on many different aspects of compilation and optimisation. These techniques have focused on aspects such as minimising the total number of qubits [19] [20] [21] [22] , the depth of quantum circuits [23] [24] [25] [26] , constraints related to hardware [21, [27] [28] [29] [30] [31] [32] and the minimisation of certain quantum gates that are resource intensive when implemented in error corrected hardware [33] [34] [35] [36] [37] [38] . However, despite the significant quantity of research in this area, much of the early work omitted details of fault-tolerant error correction protocols. These protocols are not only instrumental in implementing any quantum algorithm, beyond a handful of qubits, but place constraints on the cost metrics used when assessing optimal circuit constructions for a higher level algorithm [39] . In recent years, theoretical research has begun to take into account the considerations of error corrected computation. Both high level quantum programming languages and efforts in optimisation have attempted to re-engineer circuits under more appropriate constraints. Most notably is the increased number of papers recognising that in fault-tolerant quantum computation a Clifford + T universal gate set is generally used and the resource penalty associated with the single qubit T = |0 0| + e iπ/4 |1 1| gate requires the minimisation of both the number of such gates and the corresponding T -depth (the number of sequential applications of T -gates in a circuit) [33] [34] [35] [36] [37] [38] . However, much of this work still abstracts out concrete choices of quantum error correction (QEC) coding and/or specific hardware implementations when compiling and optimising quantum circuits. From a hardware perspective, topological codes have emerged as the preferred method for achieving a scalable design. The majority of scalable architectures proposed either use the 2-dimensional surface code [40] [41] [42] , or the 3-dimensional Raussendorf model [43, 44] as the underlying error correction method. These models are preferred as they can be defined on a 2-or 3-dimensional nearest neighbour array of qubits, facilitating experimental fabrication, and have one of the highest fault-tolerant thresholds of any error correction scheme (approaching 1% under certain circuit assumptions) [45, 46] . Additionally, realisation of error corrected algorithms is a function of how the array of qubits is measured, rather than how it is constructed (i.e. the actual choice of algorithm only dictates the physical size of the lattice needed at the hardware level, nothing more) [39, 47, 48] , with error correction decoding and correction occurring concurrently with algorithmic implementation [49, 50] . In recent years numerous results have been published demonstrating hardware accuracy sufficient for this coding model in both ion traps and superconducting systems [51] [52] [53] [54] [55] . These topological codes also have the property, along with more traditional concatenated CSS codes, that a universal, error corrected gate set is built using the Clifford + T library. The inherent fault-tolerant operations allowed in these models are initialisations/measurements in the Z-and X-bases and a two qubit CNOT gate. Hadamard (H = (X + Z)/ √ 2) and Phase (P = √ Z) gates can be realised in multiple ways [56] [57] [58] [59] , to complete the Clifford set, while the T -gate is realised through state injection, purification protocols and teleportations [56] . State distillation protocols, necessary for the T gate and some realisations of the H-and P -gates, dominate the resources required for a large scale computation [39, 42] .
A framework to the study the compilation and description of fault-tolerant, high level quantum circuits is proposed in REF .
Fault-Tolerant High Level Quantum Circuits: Form, Compilation and Description
Quantum Science and Technology, 2, 025003 (2017)
Mathematics Physics