A new format for storing sparse matrices is proposed for efficient sparse matrix-vector (SpMV) product calculation on modern graphics processing units (GPUs). This format extends the standard compressed row storage (CRS) format and can be quickly converted to and from it. Computational performance of two SpMV kernels for the new format is determined for over 130 sparse matrices on Fermi-class and Kepler-class GPUs and compared with that of five existing generic algorithms and industrial implementations, including Nvidia cuSparse CSR and HYB kernels. We found the speedup of up to ≈ 60% over the best of the five alternative kernels. Key words. SpMV, CRS format, CSR format, CUDA, hardware accelerators AMS subject classifications. 65F50, 65Y10 1. Introduction. The sparse matrix-vector (SpMV) multiplication is one of the most important kernels in scientific computing with numerous applications ranging from sparse linear solvers to the PageRank algorithm used by Google in its Web search engine. However, its high memory bandwidth requirements combined with the poor data locality exhibited by typical sparse matrices result in poor performance on general purpose processors which usually attain only a small fraction of their peak performance in this kernel. The literature devoted to SpMV optimization techniques on traditional, cache-based processor designs is ample (see [26] for an extensive overview), and currently one of the major issues is how to exploit new features available in multicore hardware. Several SpMV optimization strategies were already proposed for various designs of chip multiprocessors, including multicore central processing units (CPUs) from Intel and AMD [27], single-and dual-socket STI Cell [27], Sun UltraSPARC T2 [27], field programmable gate arrays (FPGAs) [7, 8] , Intel Xeon Phi coprocessors [14, 20] , and graphics processing units (GPUs) [1, 2, 4, 9, 11, 15, 17, 18, 23, 24, 28] . In just a few years GPUs have evolved from fixed-pipeline application-specific integrated circuits into highly programmable, versatile computing devices with peak computational performance matching that of the most powerful supercomputers of only a decade ago. These devices can be programmed in high-level programming languages, e.g. Nvidia's C++ for CUDA (proprietary) or OpenCL (open standard). The major problem in their usage is software: any new hardware architecture will succeed only if appropriate software can be developed to exploit the parallelism in the hardware efficiently. However, the current multicore architectures are so diverse and are subject to so frequent changes that to exploit their potential the applications must be highly specialized and use architecture-specific optimization strategies. Moreover, massively parallel architectures, like the one utilized in modern GPUs, require to use a new programming paradigm, which in turn requires radical rethinking of how numerical computations should be performed. Since the vast majority of the existing scientific software adheres to "old" programming paradigms, and since development
Other methods for storing sparse data are the compressed row storage (CRS) or compressed sparse row (CSR) patterns REF .
Compressed Multi-Row Storage Format for Sparse Matrices on Graphics Processing Units
SIAM J. Sci. Comput. 36-2 (2014), pp. C219-C239
Computer Science Physics