In this paper, we present a simultaneous resource allocation and binding algorithm for FPGA power minimization. To fully validate our methodology and result, our work targets a real FPGA (320So) with better circuit speed (1600) compared to a traditional resource allocation and binding algorithm.
In REF , a low-power, simultaneous resource allocation and binding algorithm for FPGAs was presented, and included a high-level power estimator.
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs
2007 Asia and South Pacific Design Automation Conference
2007 Asia and South Pacific Design Automation Conference
Computer Science