With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleaved distribution of the address space. Although such an organization is effective for avoiding access hot-spots, it can cause a significant number of non-local L2 accesses for many commonly occurring regular data access patterns. In this paper we develop a compile-time framework for data locality optimization via data layout transformation. Using a polyhedral model, the program's localizability is determined by analysis of its index set and array reference functions, followed by non-canonical data layout transformation to reduce non-local accesses for localizable computations. Simulation-based results on a 16-core 2D tiled CMP demonstrate the effectiveness of the approach. The developed program transformation technique is also useful in several other data layout transformation contexts. Layout Optimization, Polyhedral Model, NUCA Cache N: number of L2 cache banks L: bank offset size, some power of 2 between cache line and page size Physical Address Bank # Log 2 N bits Log 2 L bits Offset (b) Figure 1. (a) Tiled CMP architecture. (b) Mapping a physical address to a cache bank on a tiled CMP.
The work in REF develops a compiletime framework for data locality optimization via data layout transformation targeting NUCA chip multiprocessors.
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
2009 18th International Conference on Parallel Architectures and Compilation Techniques
2009 18th International Conference on Parallel Architectures and Compilation Techniques
Computer Science