Abstract-The performance and power efficiency of multi-core processors are attractive features for safety-critical applications, as in avionics. But increased integration and average-case performance optimisations pose challenges when deploying them for such domains. In this paper we propose a novel approach to compute an interference-sensitive Worst-Case Execution Time (isWCET) considering variable access delays due to the concurrent use of shared resources in multi-core processors, particularly focusing on shared interconnects and main memory. Thereby we tackle the problem of temporal partitioning as required by safety-critical applications. In particular, we introduce additional phases to state-of-the-art timing analysis techniques to analyse an application's resource usage and compute an interference delay. We further complement the offline analysis with a runtime monitoring concept to enforce resource usage guarantees. The concepts are evaluated on Freescale's P4080 multi-core processor in combination with SYSGO's commercial real-time operating system PikeOS and AbsInt's timing analysis framework aiT. We abstract real applications' behaviour using a representative task set of the EEMBC Autobench benchmark suite. Our results show a reduction of up to 53% of the multi-core Worst-Case Execution Time (WCET), while implementing full transparency to the temporal and functional behaviour of applications, enabling the seamless integration of legacy applications.
In REF , an approach for WCET computation considering variable access delay due to shared resources is proposed.
Multi-core Interference-Sensitive WCET Analysis Leveraging Runtime Resource Capacity Enforcement
2014 26th Euromicro Conference on Real-Time Systems
2014 26th Euromicro Conference on Real-Time Systems
Computer Science