Temporal logic model checking involves checking the state-space of a model of a system to determine whether errors can occur in the system. Often this involves checking symmetrically equivalent areas of the state-space. The use of symmetry reduction to increase the efficiency of model checking has inspired a wealth of activity in the area of model checking research. We provide a survey of the associated literature.
A survey of symmetry reductions in temporal logic model checking is given in REF .
Symmetry in temporal logic model checking
CSUR
Computer Science