Heterogeneous multi-processors are designed to bridge the gap between performance and energy efficiency in modern embedded systems. This is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best setting for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance. We develop a simulation methodology that can 1) isolate the hardware effects of migrations from the software, 2) directly compare the performance of different core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with little performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside buffer that matches performance and efficiency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance benefits without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without affecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or better system operation without having to aggressively share the entire memory system or to revert to migration periods finer than 100k instructions. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org.  In today's embedded devices, performance is always tied to power constraints and energy efficiency. This happens because, while process technology scaling is enabling larger transistor densities, power per area has shown to increase beyond a certain threshold in transistor size. This latter effect is commonly referred to as the breakdown of Dennard's scaling, which forces designs to operate only a fraction of the whole system, leaving the remaining design in a dark silicon state [8, 10] . To address this, heterogeneous multiprocessors (HMPs) have emerged over other designs, especially in mobile devices [17, 33] , where keeping within a strict energy envelope while still being able to deliver performance on demand is crucial. To be able to deliver high performance through Memory Level Parallelism (MLP) and instruction level parallelism (ILP), an Out-of-Order (OoO) core is commonly used that has large caches, does aggressive speculation (branch predictors, prefetchers) and masks memory latency at the cost of significantly increased design complexity, area and power requirements. On the other hand, InOrder (InO) cores aim at conserving energy through a simpler and smaller design, at the expense of performance and lower operating frequency. A characteristic implementation of an HMP architecture is, for example, ARM's big.LITTLE [1], which uses two types of cores that share the same instruction set. Workloads can be broken down into phases, some of which show high ILP potential and can therefore yield high performance while others heavily access memory and therefore deliver lower instructions per cycle (IPC). Choosing the most suitable core leads to an optimal performance and energy profile, while making a wrong decision can lead to unnecessary slowdown or energy waste. Recent studies claim that micro-phases in the order of thousands of instructions exist [12, 30] , as seen in Figure 1 , and can be exploited to reduce energy consumption and boost performance through fine-grained migrations. In theory, perfect core matching should lead to optimal behaviour, however every time a migration is performed the working state needs to be transferred to the operating core, adding both a software and hardware execution overhead. From the software side the operating system (OS) handles the scheduling to the appropriate core and sends the required signals to perform the migration. The complexity of the scheduler and the software context switch significantly affects the amount of overhead added to a system, which is on the order of ten million instructions [7, 19, 32, 35] . From a hardware perspective, the overheads depend on how much of the state needs to be transferred and how much is shared between the two migrating cores. The more state shared and preserved, the less warm-up time required, which is the period necessary to achieve maximum performance. Unlike software, hardware overheads can be significantly smaller, as low as thousands of instructions, depending on the amount of resources shared. To reduce overall system slowdown when migrating, several studies propose the implementation of dedicated hardware to efficiently handle the transfer without any software intervention [12, 13, 18, 21, 26] and also fusing cores to share the front-end [20, 22, 24] . However, as hybrid designs are too complex to implement, it is worth investigating a simpler approach determining which components contribute most to the benefits and sharing only those. The questions we aim to answer therefore are:
Other work, namely REF shows that even when applications have all of their data in the caches, the performance hit caused by the branch predictor can be as much as 20% for 100k instruction switching frequencies for Out-of-Order cores while In-Order cores show little degradation.
Nucleus: Finding the Sharing Limit of Heterogeneous Cores
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Computer Science