Abstract-Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering of operating voltages. It is important for designers to be able to validate whether the Soft Error Rate (SER) targets of their design have been met, and help end users select the processor best suited to their reliability goals. The knowledge of the observable worst-case SER allows designers to select their design point, and bound the worst-case vulnerability at that design point. We highlight the lack of a methodology for evaluation of the overall observable worst-case SER. Hence, there is a clear need for a so called stressmark that can demonstrably approach the observable worst-case SER. The worst-case thus obtained can be used to identify reliability bottlenecks, validate safety margins used for reliability design and identify inadequacies in benchmark suites used to evaluate SER. Starting from a comprehensive study about how microarchitecture-dependent program characteristics affect soft errors, we derive the insights needed to develop an automated and flexible methodology for generating a stressmark that approaches the maximum SER of an out-of-order processor. We demonstrate how our methodology enables architects to quantify the impact of SERmitigation mechanisms on the worst-case SER of the processor. The stressmark achieves 1.4× higher SER in the core, 2.5× higher SER in DL1 and DTLB, and 1.5× higher SER in L2 as compared to the highest SER induced by SPEC CPU2006 and MiBench programs.
Since the vulnerability of the processor depends on the application, REF focuses on meeting the need for a stressmark that can measure the observable worst-case soft error rate (SER).
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Computer Science