Abstract-This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design. Index Terms-Extended Min Sum algorithm, FPGA synthesis, low-complexity architecture, non-binary low-density parity-check decoders.
The serial GF (64)-LDPC decoder proposed by Boutillon et al. REF was based on Extended Min-Sum algorithm.
Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers
Mathematics Computer Science