We present a novel, compile-time method for determining the cache performance of the loop nests in a program. The cache-miss rates are produced by applying the program's reference string of a loop nest, determined during compilation, to an architecturally parameterized cache simulator. The obtained cache-miss rates correlate well with the performance of the loop nests on actual target machines. We describe also a heuristic that uses this method for compile-time optimization of loop ranges in iterationspace blocking. The results of the loop program optimizations are presented for di erent processor architectures, namely IBM SP1 RS/6000, the SuperSPARC, and the Intel i860.
In REF W. Kaplow et al. present a compile-time method for determining the cache performance of the loop nests in a program and a heuristic that uses this method for compile-time optimization of loop ranges in iteration-space blocking.
Program Optimization Based on Compile-Time Cache Performance Prediction
Parallel Processing Letters
Computer Science