Abstract| This paper presents systematic techniques to nd low-power, high-performance superscalar processors tailored to speci c user applications. The model of power is novel because it separates power into architectural and technology components. The architectural component i s found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: decreasing power consumption in a superscalar processor without greatly impacting performance. Results are presented from runs using simulated annealing to reduce power consumption subject to performance reduction bounds. The major contributions of this paper are the separation of architectural and technology components of dynamic power, the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark.
al. REF separated architectural and technology components of dynamic power, and used a near-optimal search to tailor a processor design to different benchmarks.
System-Level Power Consumption Modeling and Tradeo Analysis Techniques for Superscalar Processor Design
IEEE Trans. Very Large Scale Integr. Syst.
IEEE Trans. Very Large Scale Integr. Syst.
Computer Science