Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement lowdiameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.
Joshi et al. REF build a nanophotonics clos network, which provides uniform latency and throughput with low power.
Silicon-photonic clos networks for global on-chip communication
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Computer Science