The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-o made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-ampli er through a wire called a bitline. These bitlines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater senseampli er area overhead. In this work, we introduce TieredLatency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-e ciency for both single-core and multi-programmed workloads.
Based on the key observation that long internal wires (bitlines) are the dominant source of DRAM latency, our HPCA 2013 paper REF proposes a new DRAM architecture called Tiered-Latency DRAM (TL-DRAM).
Tiered-latency DRAM: A low latency and low cost DRAM architecture
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Computer Science