Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-level parallelism and improve performance. The techniques include reordering to reduce cache misses originally due to Das et al., blocking to reduce load instructions, and prefetching to prevent multiple load-store units from stalling simultaneously. The techniques improve performance from about 40 Mflops (on a well-ordered matrix) to over 100 Mflops on a 266 Mflops machine.
Toledo REF enhanced sparse matrix multiplication on a superscalar RISC processor by improving instructionlevel parallelism and reducing cache miss rate.
Improving the memory-system performance of sparse-matrix vector multiplication
IBM J Res Dev
Computer Science