Abstract The Compaan framework [8] automatically transforms digital signal processing applications, written in a subset of Matlab, into Kahn Process Networks. These KPNs express the signal processing applications in a parallel distributed way making them more suitable for mapping onto parallel architectures. These networks can be converted to VHDL and quickly synthesized to FPGAs [5] or mapped onto some parallel signal processing architectures [9] at a high level of abstraction to obtain first-order performance numbers. The simplest instance of a Kahn Process Network is a Producer process that communicates with a Consumer process over an unbounded FIFO channel in which the Consumer reads data from the FIFO using a blocking read. A problem emerges if the order data is produced is different from the order data is consumed. Such situation leads to functional incorrect evaluation of the network and moreover it may lead to dead-lock. To avoid such situation, it is necessary to introduce a reordering mechanism that allows the Consumer to consume the data in the correct way. This paper presents a compile time approach to determine for a derived process network whether FIFOs are sufficient or additional reordering mechanisms are needed. For the case when a reordering mechanism is required, we also provide its model. We assume that the process networks are derived using the Compaan toolset from nested loop programs written in Matlab. The toolset consists of three tools. The first tool transforms the initial 1
In Compaan, compile time tests determine whether the FIFO sizes are sufficient or additional memory needs to be allocated to the consumer process to buffer out-of-order data REF .
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks
In IEEE 13th International Conference on Aplication-specific Systems, Architectures and Processors (ASAP’2002
Computer Science