Abstract. Recently, there has been a lot of interest on cryptographic applications based on fields GF (p m ), for p > 2. This contribution presents GF (p m ) multipliers architectures, where p is odd. We present designs which trade area for performance based on the number of coefficients that the multiplier processes at one time. Families of irreducible polynomials are introduced to reduce the complexity of the modulo reduction operation and, thus, improved the efficiency of the multiplier. We, then, specialize to fields GF (3 m ) and provide the first cubing architecture presented in the literature. We synthesize our architectures for the special case of GF (3 97 ) on the XCV1000-8-FG1156 and XC2VP20-7-FF1156 FPGAs and provide area/performance numbers and comparisons to previous GF (3 m ) and GF (2 m ) implementations. Finally, we provide tables of irreducible polynomials over GF (3) of degree m with 2 ≤ m ≤ 255.
In REF a digit serial multiplier over GF (3 m ) is described.
Efficient GF(p m) Arithmetic Architectures for Cryptographic Applications
IN TOPICS IN CRYPTOLOGY - CT RSA 2003
Mathematics Computer Science