Abstract-Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (V th ) due to NBTI is further affected by the initial value of V th from fabricationinduced process variation (PV). Addressing these challenges in embedded FPGA designs is possible, as FPGA reconfigurablility can be exploited to measure the exact timing degradation of an FPGA due to the joint effect of NBTI and PV at run time with low overhead. The gathered information can then be used to improve the run-time performance and reliability of FPGA designs without targeting the pessimistic worst case. In this paper, we present joint NBTI/PV-aware placement techniques for FPGAs, including NBTI/PV-aware timing analysis, region-based delay estimation, and a new move-acceptance procedure. To evaluate the proposed techniques, we combine PV measurements from 15 Xilinx Virtex-II Pro FPGAs with a model of NBTI. The proposed techniques reduce the effect of NBTI/PV by more than 60% for over 60% of the 15 FPGA chips used in the experiments, with a typical run-time overhead of 1.4-1.8X. The standalone move-acceptance procedure also produces good results with negligible run-time overhead, making it suitable for online FPGA compilation and optimization flows. Negative bias temperature instability (NBTI) is a leading reliability challenge at the nano-scale level that causes degradation in the threshold voltage (V th ) of a PMOS transistor, which gradually increases delay. NBTI occurs when a PMOS transistor is stressed under high temperatures with V gs = −V dd , causing high oxide electric field (E ox ); this stress causes some Si-H bonds on the Si-SiO 2 interface to break, leaving unpaired valence electron in Si atoms. These broken bonds are called interface traps. The existence of such traps increases the absolute value of V th in PMOS transistors. NBTI degradation is further affected by the initial value of V th that may deviate from the nominal value due to process variation (PV). The initial value of V th determines the amount of E ox ; the smaller its initial value, the higher E ox , which increases NBTI degradation. However, the joint NBTI/PV effect, i.e., combining initial V th with the expected degradation due to NBTI, shows that variation in V th is always the dominating factor, which means that transistors with smaller initial V th will have smaller V th even after NBTI degradation.Variations in V th are expected to further increase according to the ITRS [1] . Addressing the joint NBTI/PV effect becomes increasingly critical. The regular structure of FPGAs and their reconfigurability can be exploited to measure the joint effect of PV and NBTI at run time. The results can be used to optimize circuit placement and routing with awareness of NBTI and PV effects to improve
A process variation and NBTI-aware placement strategy for FPGAs is introduced in REF .
Reliability- and process variation-aware placement for FPGAs
DATE '10
Computer Science