Abstract-Efficiency a n d flexibility are critical, but often conflicting, deaign goals in embedded system design. The resent emerg8ence of extensible processors promises a favorable tradeoff between emcieney and flexibility, while b p i n g design turnaround times short. Current extensible p r o e e s s~r deaign R o w s automate -vera1 tedious tasks, but typically require designers to manually select t h e parts of t h e program t h a t are to he implemented -custom instructions. In this work, we describe an automatic methodology t o eelact custom instructions t o augment an extensible PTOC~SIIOI, in order to maximize ita efflcieney for a given application program. W e dsmonstrate t h a t t h e number of custom instruction candidates grows rapidly with program ~i s e , leading t o e large design mpace, and t h a t t h e quality (speedup) of custom instructions varies signiflcantly across this space, motivating t h e need for t h e proposed flow. Our methodology features cost funotions t o puide t h e custom inatrustion selection process, * weii M static and dynamic pruning techniques t o eliminate inferior parts of t h e design apace from considerstion. Further, we employ a twostage process, wherein a limited numher of promising instruction candidates are first selected, and then evaluated in more detail through cycleaccurate instruction met aimd a t i o n and synthesb o f t h e corresponding hardware, t o identify t h e custom instruction combinations t h a t resuit in t h e highest program speedup or maximize speedup under a given area constraint. W e have evaluated t h e proposed techniques using a a t a t e o f -t h e art extensible processor platform, In t h e context of L. commercial design flow. Experiments with several benchmark programs indicate t h a t custom processors synthesized using automatic custom. instruction aeiection can result in large improvements in p e r f o r manee (upto 5.4X, average of S.4X), energy (upto 4.5X, average of S.ZX), and energy-delay product (upto 24.ZX, average of lZ.eX), while speeding up t h e design process eignifleantiy. Efficiency and flexibility are two of the most important driving factors in embedded system design. Efficient implementations are required t o meet the tight cost, timing and power constraints present in embedded system. Flexibility, albeit tough to quantify, is equally important -it allows system designs to be easily modified or enhanced in response t o bugs, evolution of standards, market shifts, or user requirements, during the design cycle and even after production. Various implementation alternatives for a given function, ranging from custom-designed hardware t o software running on embedded processors, provide a system designer with differing degrees of efficiency and flexibility. Unfortunately, it is often the case that these are conflicting design goals. While efficiency is obtained through custom hardwired implementations, flexibility is best provided through programmable implementations. Hardwarelsoftware partitioning -separating a system's functionality into embedded software (running on programmable processors), and custom hardware (implemented as cc-processors or peripheral units) -is one approach to achieve a good balance between flexibility and efficiency 111. However, the increasing scale and complexity of embedded Systems-on-Chips (SOCs), together Acknowled-ems: This work w~ supported io part by DARPA under contr-t no. DAABO7-OO-C-LSIB snd in part by ths NJCST Center on Embedded Systemon-*-Chip Daaizn. with decreasing market cycles, provide a constant pusbtowards ' increasing embedded software content. While it is known that application-speciflc instruction set processors (ASIPs) provide a good tradeoff between efficiency ana flexibility, their relatively large design turnaround times ( pared t o software implemented on pre-designed and prRve, embedded processors) have, in part, prevented their wid&&' + SOCs. The recent availability of configurable and extensible pi$.$$:-I cessors ' promises a favorable tradeoff between efficiency and flex-*: ' . , ibility, while keeping design turnaround times short. The emir-., gence and success of companies that offer configurable and extensible embedded microprocessor and DSP cores as a primary product . , etc.) testifies to the beneflts a f t 1s approarb. ' Flealhiug the potential of extensible processors requires the,d+. velopment of supporting tools and methodologies that enable &?.-tem designers t o achieve design turnaround times that are +my parable t o all-software solutions. State-of-the-art extensible pi* !'' cessor design flows automate several tedious tasks and aid the design process by providing a high-level interface to perform processor customhatian, automatic generation of register-transfer level (RTL) hardware descriptions, a retargetable software tool chain for the customized processor (including compilers, assemblers, debuggers, and binary utilities), and design automation scripts t o support verification, logic synthesis, and physical design. However, they require designers to manually select parts of the pmgmm and design the custom instructions that implement them. As . shorn in thG paper, these are daunting tasks f o r large pmpms, and are further complicated when performance improvements need to be attained subject to other considerations. such as constmints on hadware are0 overheads and clock period. Our work addresses the above need by providing a systematic methodology and automation algorithms for the application-specific customization of extensible processors. We briefly trace related research work along the lines of ASIP architectures and overall design methodologies, application-specific instruction set selection, compilation techniques for ASIPs, and . low power ASlP design. A good overview of the benefits and challenges involved in ASIP design is contained in [SI. Early works on architectural synthesis for ASIPs are contained in [9], [lo]. In 1111, a design system for synthesizing simple pipelined ASIPs is described. The work in 1121 deals with the selection of intellectual property (IP) surrounding an ASIP core t o accelerate application programs. A method to design parallel and scalable ASIP architectures, suitable for reactive systems, is presented in 1131. In 1141, an early design space exploration methodology is given for clustered very long instruction word (VLIW) data paths in the context of specific target appli-'Follauing the terminology "sed in 121, a configursble proseaaor offar. the daaibncr the po~sibility to c u s t a m i~~ the basis procenror architestura. while m exten#ibis proseoror allow the designor to extend the baric instruction set throush the
In REF the design flow consists of generating instructions automatically, inserting instructions, and performing a heuristic design space exploration.
Synthesis of custom processors based on extensible platforms
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.
IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.
Computer Science