We present a compiler that takes high level signal and image processing algurithms described in MATUB und generates an optimized hardware,for an FPGA with external memury. We propose a precision unulysis ulgorithm tu determine the minimum number of bits required by an integer variable and a combined precision and errur analysis algorithm to infer the minimum number of bits required by afloating point variable. Our results show that on an average, our algorithms generate hardware requiring u Jucmr of 5 less FPGA resources in terms of the Configurable Logic Blocks (CLBs) consumed as compared to the hardware generated without these uprimizations. We show that our analysis results in the reduction in the size oflookup tables furfunctions like sin, cos, sqrt, exp etc. Our precision unalysis ulso enables us to pack various array elements into a single memory location tu reduce the number cfexternal memory accesses. We show that such a technique improves the performance uf the generated hardware by un overage of 35%.
Nayak et al. in REF presented a compiler that takes highlevel signal processing algorithms described in MATLAB and generates optimized hardware.
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
Computer Science