Multiprocessing architectures provide hardware for executing multiple tasks simultaneously via techniques such as simultaneous multithreading and symmetric multiprocessing. The problem addressed by this paper is that even when tasks that are executing concurrently do not communicate, they may interfere by affecting each others' timing. For cyberphysical system applications, such interference can nullify many of the advantages offered by parallel hardware and can enormously complicate synthesis of software from models. This paper examines what changes need to be made at lower levels of abstraction to support temporal isolation for effective software synthesis. We discuss techniques at the microarchitecture level, in the memory hierarchy, in on-chip communication, and in the instruction-set architecture that can facilitate temporal isolation. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC '11 June 5-10, 2011, San Diego, California, USA Copyright 2011 ACM 978-1-4503-0636-2/11/06 ...$10.00. Categories and Subject Descriptors General Terms Design Precision-timed architectures, PRET machines, microarchitecture, pipelines, memory hierarchy, network on chip, instruction set architecture A cyber-physical system (CPS) uses embedded computers to monitor and control physical processes [8] . These systems are typically in feedback loops such that the physical processes affect the behavior of the computation, and vice versa. Note two important aspects of physical processes: they are inherently concurrent, and time in physical processes progresses at its own pace; time is uncontrollable. Therefore, to control physical processes, embedded computers need to provide support for concurrent behaviors and timely reactions. Modern embedded computing architectures are becoming increasingly parallel by using multiprocessing techniques such as multicores and simultaneous multithreading (SMT). These parallel architectures deliver higher performance and also address the need for concurrency. However, ensuring that real-time requirements are met is a challenge in such architectures. A major problem is that multiprocessing techniques can introduce temporal interference even between logically independent behaviors. For example, in a multicore machine with shared caches, the processes running on one core can affect the timing of processes on another core even when there is no communication between these processes. Similarly, SMT [4] shares a wide-issue superscalar pipeline across multiple hardware threads with instructions dispatched using scoreboaring mechanisms. This allows threads to occupy more pipeline resources when other threads are idle or stalled for long latency operations. This results in temporal interference between the threads because of the contention for pipeline resources. 1 In addition, symmetric multiprocessing (SMP) techniques use multiple processing units connected with an 1 Several research groups have introduced ways to mitigate the temporal interference in SMTs by allocating a real-time thread with the highest priority [2], time-sharing the realtime thread [12] , and partitioning the instruction cache [11] .
Specifically, the precision timed (PRET) architecture REF introduces task runtime control and deadline enforcement at the instruction set (ISA) level.
Temporal isolation on multiprocessing architectures
DAC '11
Computer Science