We propose a memory-model-aware static program analysis method for accurately analyzing the behavior of concurrent software running on processors with weak consistency models such as x86-TSO, SPARC-PSO, and SPARC-RMO. At the center of our method is a uni ed framework for deciding the feasibility of inter-thread interferences to avoid propagating spurious data ows during static analysis and thus boost the performance of the static analyzer. We formulate the checking of interference feasibility as a set of Datalog rules which are both e ciently solvable and general enough to capture a range of hardware-level memory models. Compared to existing techniques, our method can signi cantly reduce the number of bogus alarms as well as unsound proofs. We implemented the method and evaluated it on a large set of multithreaded C programs. Our experiments show the method signi cantly outperforms state-of-the-art techniques in terms of accuracy with only moderate runtime overhead. • Software and its engineering → Automated static analysis; Formal software veri cation;
Kusano et al. REF propose an abstract interpretationbased static analysis of concurrent programs under relaxed memory models (TSO, PSO, RMO); their thread interference feasibility model is formulated as a constraint problem, expressed as a set of Datalog rules.
Thread-modular static analysis for relaxed memory models
ESEC/FSE 2017
Computer Science