Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.
Seiculescu et al. REF proposed a design tool to synthesize application-specific 3-D NoC topology, which assigns the network components on to the 3-D tiers and performs a placement of them in each tier, while considering power and latency cost.
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
2009 Design, Automation & Test in Europe Conference & Exhibition
2009 Design, Automation & Test in Europe Conference & Exhibition
Computer Science