Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical Ll cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over a conventional design.
In the arena of power efficiency, filter caches REF are able to reduce power consumption, but suffer from a significant decrease in performance.
The filter cache: an energy efficient memory structure
Proceedings of 30th Annual International Symposium on Microarchitecture
Proceedings of 30th Annual International Symposium on Microarchitecture
Computer Science