The emergence of power efficiency as a primary constraint in processor and system design poses new challenges concerning power and energy awareness for numerical libraries and scientific applications. Power consumption also plays a major role in the design of data centers, which may house petascale or exascale-level computing systems. At these extreme scales, understanding and improving the energy efficiency of numerical libraries and their related applications becomes a crucial part of the successful implementation and operation of the computing system. In this paper, we study and investigate the practice of controlling a compute system's power usage, and we explore how different power caps affect the performance of numerical algorithms with different computational intensities. Further, we determine the impact, in terms of performance and energy usage, that these caps have on a system running scientific applications. This analysis will enable us to characterize the types of algorithms that benefit most from these power management schemes. Our experiments are performed using a set of representative kernels and several popular scientific benchmarks. We quantify a number of power and performance measurements and draw observations and conclusions that can be viewed as a roadmap to achieving energy efficiency in the design and execution of scientific algorithms. energy efficiency, high performance computing, Intel Xeon Phi, Knights landing, PAPI, performance analysis, performance counters, power efficiency A fundamental challenge in the effort to reach exascale performance levels is striking the right balance between performance and power efficiency at the appropriate software and hardware levels. In this paper, we discuss strategies for power measurement and power control to offer scientific application developers the basic building blocks required to develop dynamic optimization strategies while working within the power constraints of modern and future high-performance computing (HPC) systems. Applications with high data bandwidth requirements, commonly referred to as "memory-bound" applications, have very different implications for power consumption compared to "compute-bound" problems that require heavy CPU throughput. From an energy perspective, compute-bound workloads result in high CPU power consumption, while memory-bound workloads primarily consume power through the main dynamic random-access memory (DRAM). In the latter case, the CPU may not need to consume power at peak levels because the main DRAM's latency and bandwidth serve as a bottleneck. This dynamic suggests that small decrements to the CPU power limit may reduce power consumption over time with minimal-to-no performance degradation, which ultimately results in significant energy savings. To investigate potential power savings, a power management framework must be used for dynamic power monitoring and power capping. Analyzing how hardware components consume power at run time is key in determining which of the aforementioned categories an application fits into. As the computing landscape evolved, hardware vendors began offering access to their energy monitoring capabilities. For example, beginning with the introduction of the Sandy Bridge architecture, Intel incorporates the running average power limit (RAPL) model in their CPU design to provide
Azzam et al. REF analyzed the performance of many kernels and the power consumption of various hardware components in terms of power capping.
Investigating power capping toward energy-efficient scientific applications
Concurr. Comput. Pract. Exp.
Concurr. Comput. Pract. Exp.
Computer Science