Abstract-A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.
REF is an attempt on deriving the energy model of NoC based multicore chips and made comparison to a traditional bus.
Energy Model of Networks-on-Chip and a Bus
2005 International Symposium on System-on-Chip
2005 International Symposium on System-on-Chip
Computer Science