Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. We propose in this article a methodology based on measurements which allows to model the application power consumption with architectural and algorithmic parameters. So, the modeled applications can be added in a library in order to help the system designer to determine early in the design flow the best adequacy between high performances and low power consumption.
In the work of REF , a methodology was proposed, based on real measurements, which allows to model power consumption with architectural and algorithmic parameters.
A high level SoC power estimation based on IP modeling
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
Computer Science