In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, k m flow, for this new type of architecture. The experiment results show our algorithm can achieve depthoptimality in practically all cases. Furthermore it is shown that the k/m-macrocell based FPGAs are practically equivalent to the traditional k-LUT based FPGAs with only a relatively small number of product terms (m~+3). We also investigate the total area and delay of k/m-macrocell based FPGAs on various benchmarks to compare it with commonly used 4-LUT based FPGAs. The experimental result shows k/m-macrocell based FPGAs can outperform 4-LUT based FPGAs in terms of both delay and area after placement and routing by VPR.
In REF , a technology mapping algorithm for devices with -input, single-output macrocells was presented.
Technology mapping for k/m-macrocell based FPGAs
FPGA '00
Computer Science