Abstract-We consider complex embedded systems, where large, heterogeneous sets of communicating tasks are executed on heterogeneous multi-processor / multi-bus architectures with RTOSes and bus-arbitration. Examples include systems-on-chip for mobile communication, multimedia platforms or distributed automotive control systems. In such systems, data-dependent task execution times and preemption lead to data jitter and bursts, and consequently to sophisticated run-time interdependencies between tasks. Reliable validation of timing constraints in such systems can no longer be achieved through simulation due to incomplete corner-case coverage, but instead requires formal performance analysis. Existing system-level performance analysis techniques assume that the completion of one task immediately leads to the activation of a dependent task. However, activation dependencies in realistic embedded applications are often more complex, including multirate data dependencies, multiple activating inputs, cyclic dependencies or conditional communication. In these cases, existing performance analysis techniques are not directly applicable. In this paper, we focus on the calculation of activation timing in the presence of complex task dependencies. These calculations are then integrated into a system-level performance analysis framework for heterogeneous architectures. Using a larger example, we demonstrate how performance analysis allows rapid design-space exploration to optimize the implementation of realistic embedded applications while satisfying all critical timing constraints. Index Terms-performance analysis, reactive multiprocessor systems, complex applications I. EMBEDDED MULTIPROCESSOR SYSTEMS Modern embedded systems are designed to execute large, heterogeneous sets of applications, many of them under hard real-time constraints. Applications are structured into communicating tasks. A task is usually activated when predecessors have produced output data on which the task can operate. Such a task is called a reactive task. Activating events may be sporadic by nature, e. g. alarm signals or user input, or basically periodic, e. g. a stream of sensor data or packets in a communication protocol. Even strictly periodic task activation can be viewed as event-driven, since it is the result of the expiration of a timer. Activation dependencies in realistic embedded applications can be rather complex. A consumer task may require a different amount of data per execution than produced by a producer task, leading to multi-rate systems. Task activation may also be conditional, leading to execution-rate intervals. Furthermore, a task may consume data from multiple task inputs. Then, task activation is determined by a boolean function over the available input data. The behavior of tasks may also heavily depend on the type and value of received data. Any useful system-level performance analysis framework must be able to handle the complexity of real-world applications. The ever increasing number of complex embedded applications can only be implemented efficiently on heterogeneous, programmable multiprocessor systems. Multiprocessor system-on-chip (MpSoC) designs use on-chip buses or networks to integrate multiple different programmable processor cores, specialized memories, and other intellectual property (IP) components on a single chip. MpSoCs have become the architecture of choice in network processing, mobile communication and consumer electronics. In the automotive domain, a trend can be seen towards distributed embedded systems. Systems integration is becoming the major challenge in embedded system design. Complex hardware and software component interactions pose a serious performance threat, including transient overloads, memory overflow, data loss, and missed deadlines. The International Technology Roadmap for Semiconductors names system-level performance verification as one of the top three co-design issues [1]. Simulation and test are state of the art in embedded system performance verification. Tools such as Mentor Graphics' Seamless-CVE [2] or Axys Design Automation's MaxSim [3] support cycle-accurate co-simulation of a complete MpSoC. In the automotive domain, sophisticated hardware-setups such as ETAS LabCar [4] or dSPACE AutoBox [5] allow rapid test of software prototypes. However, for complex systems it becomes increasingly difficult to cover all corner cases. A corner case describes a critical execution scenario. For each corner case, the designer must provide a simulation pattern that reaches that corner case during simulation. Essentially, if all corner cases satisfy the given performance constraints, then the system will satisfy its constraints. However, such corner cases are extremely difficult to find and debug, and it is even more difficult to find simulation patterns to cover them all. To limit complexity, an industrial trend can be observed towards conservative but easily predictable communication protocols like time-division multiple access that minimize nonfunctional component dependencies. The Sonics SiliconBackplane Micronetwork [6] is an example of these protocols, which make communication timing straightforward and predictable. Distributed systems exhibit a similar trend toward conservative protocols, such as the time-triggered protocol [7] in automotive and aerospace electronics. However, this integration simplicity comes at a significant performance price -a price that increases with system complexity, since such protocols are inefficient in dynamically changing load situations that are typical for reactive embedded systems.
Jersak et al. REF also focus on the task interaction.
Performance analysis for complex embedded applications
IJES
IJES
Computer Science