As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor per$ormance. Compiler techniques have been used to improve instruction and data cache performance for virtually indexed caches by mapping code and data with temporal locality to d.@erent cache blocks. In thispaper we examine the petiormance of compiler and hardware approaches for reordering pages in physically addressed caches to eliminate cache misses. The software approach provides a color mapping at compile-time for code and data pages, which can then be used by the operating system to guide its allocation of physical pages. The hardware approach works by adding a page remap field to the TLB, which is used to allow a page to be remapped to a d@erent color in the physically indexed cache while keeping the samephysicalpage in memory. The results show that softwarepage placement provided a 28% speedup and hardware page placement provided a 21% speedup on average for a superscalar pnxessol: For a 4 processor single-chip multiprocessor the miss rate was reducedfrom 8.7% down to 7.2% on average.
Sherwood, et al. REF add a page remap field to the TLB which allows a page to be remapped to a different color in the physically indexed cache while keeping the same physical page in memory.
Reducing cache misses using hardware and software page placement
ICS '99
Computer Science