Abstract-Distributed shared-memory (DSM) multiprocessors provide a scalable hardware platform, but lack the necessary redundancy for mainframe-level reliability and availability. Chip-level redundancy in a DSM server faces a key challenge: the increased latency to check results among redundant components. To address performance overheads, we propose a checking filter that reduces the number of checking operations impeding the critical path of execution. Furthermore, we propose to decouple checking operations from the coherence protocol, which simplifies the implementation and permits reuse of existing coherence controller hardware. Our simulation results of commercial workloads indicate average performance overhead is within 4% (9% maximum) of tightly coupled DMR solutions.
Another proposal, which filters checks from the critical path when possible and decouples checking from coherence, addresses these challenges REF .
Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors
2009 15th IEEE Pacific Rim International Symposium on Dependable Computing
2009 15th IEEE Pacific Rim International Symposium on Dependable Computing
Computer Science