Abstract We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field As technological trends continue to lead toward smaller device and wire dimensions in integrated circuits, the probability of hard (permanent) faults in microprocessors increases. These faults may be introduced during fabrication, as defects, or they may occur during the operational lifetime of the microprocessor. Well-known physical phenomena that lead to operational hard faults are gate oxide breakdown, electromigration, and thermal cycling. Microprocessors become more susceptible to all of these phenomena as device dimensions shrink [28] , and the semiconductor industry's roadmap has identified both operational hard faults and fabrication defects (which we will collectively refer to as "hard faults") as critical challenges [13] . In the near future, it may no longer be a cost-effective strategy to discard a microprocessor with one or more hard faults, which is what, for the most part, we do today. Traditional approaches to tolerating hard faults have masked them using macro-scale redundancy, such as triple modular redundancy (TMR). TMR is an effective approach, but it incurs a 200% overhead in terms of hardware and power consumption. There are some other, lightweight approaches that use marginal amounts of redundancy to protect specific portions of the microprocessor, such as the cache [36, 18] or buffers [5] , but none of these are comprehensive. Our goal in this work is to create a microprocessor design that can tolerate hard faults without adding significant redundancy. The key observation, made also by previous research [25, 27, 29] , is that modern superscalar microprocessors, particularly simultaneously multithreaded (SMT) microprocessors [32] , already contain significant amounts of redundancy for purposes of exploiting ILP and enhancing performance. We want to use this redundancy to mask hard faults, at the cost of a graceful degradation in performance for microprocessors with hard faults. In this paper, we do not consider adding extra redundancy strictly for fault tolerance, because cost is such an important factor for commodity microprocessors. The viability of our approach depends only on whether, given a faulty microprocessor, being able to use it with somewhat degraded performance provides any utility over having to discard it. To achieve our goal, the microprocessor must be able to do three things while it is running. • It must detect and correct errors caused by faults (both hard and transient). • It must diagnose where a hard fault is, at the granularity of the field deconfigurable unit (FDU). • It must deconfigure a faulty FDU in order to prevent its fault from being exercised. While previous work in this area has explored aspects of this problem, none has developed an integrated solution. Some work has used deconfiguration to tolerate strictly fabrication defects and thus assumed pre-shipment testing instead of online error detection and diagnosis [25] . Other work has explored deconfiguration and has left detection and diagnosis as open problems [29] . In this paper, we discuss integrated design options for microprocessors that achieve all three of these goals, and we present one particular microprocessor in this design space. First, our microprocessor detects and corrects errors, due to both transient faults and hard faults, using previously developed DIVA-style [2] dynamic verification. Second, it uses a newly developed mechanism to diagnose hard faults as the system is running. Third, after diagnosing a hard fault, the microprocessor deconfigures the faulty FDU in an FDU-specific fashion. In this paper, we present and evaluate previously developed deconfiguration schemes for functional units and portions of array structures (e.g., reorder buffer, load/store queue, etc.), and we show that our integrated approach also enables the microprocessor to deconfigure faulty DIVA checkers. Our experimental results show that our new diagnosis mechanism quickly and accurately diagnoses hard faults. Moreover, our reliable microprocessor can function quite capably in the presence of hard faults, despite not using redundancy beyond that which is already available in a modern microprocessor. This technique can turn otherwise useless microprocessors into microprocessors that can function at a gracefully degraded level of performance. This capability can improve reliability by tolerating operational hard faults. We can improve yield by shipping microprocessors with defects that we have tolerated-it is as if they are regular microprocessors that will get "binned" into a lower performance bin. Although binning is typically by clock frequency, recent proposals have suggested more general performance binning [25] . As long as these bins are not so low-performing as to be useless, then our improvement in yield is a benefit. Our scheme also vastly outperforms a system with only DIVA or a comparable recovery-based scheme, since the performance cost of recoveries is quite high for hard faults that get exercised frequently; moreover, our scheme can tolerate a hard fault in a DIVA checker. The contributions of this work are: • A dynamic, comprehensive hardware mechanism for diagnosing hard faults in microprocessors, including faults in DIVA checkers. • A microprocessor design that integrates our new hard fault diagnosis mechanism with DIVA error detection and a mix of pre-existing and new deconfiguration schemes. • An experimental evaluation that demonstrates that a microprocessor with our enhancements can tolerate hard faults with a graceful degradation in performance. In Section 2, we discuss hard faults and why they concern microarchitects. In Sections 3, 4, and 5, we describe error detection and correction, hard fault diagnosis, and deconfiguration of faulty components, respectively. Section 6 discusses the costs and limitations of our particular implementation. Section 7 presents our experimental evaluation. We discuss related work in Section 8 and conclude in Section 9. In this section, we discuss the hard faults that motivate this work. In particular, we focus on the technological trends that are leading towards greater incidences of these faults. With increasingly smaller device and wire dimensions and higher temperatures, these trends lead us to conclude that hard fault rates will increase. There have been several recent studies of operational hard faults [28, 14] , that is, hard faults that occur over the lifetime of the microprocessor. Srinivasan et al. [28] determine that electromigration [31, 3] and gate oxide breakdown [10] are likely to be the two dominant phenomena that cause operational hard faults. Electromigration results in highly resistive interconnects or contacts and eventually leads to open circuits. Electromigration increases as wire dimensions shrink and as temperatures increase. Gate oxide breakdown (OBD) results in the malfunction of a single transistor due to the creation of a highly conductive path between its gate and its bulk. A newly manufactured oxide contains inherent electron traps due to imperfections in the fabrication process. Over the lifetime of the device, the number of such traps increases due to electric field stress and electron tunneling. At some point, the electron traps may line up and constitute a conductive path between the gate and the bulk of the device, eventually leading to OBD. OBD rates increase as oxide thicknesses shrink and temperatures increase. Since OBD increases switching delay, it can lead to delay faults that manifest themselves as bit flips [6] . Defects introduced during chip fabrication are another source of hard faults. Their causes differ from those of operational hard faults, but they often manifest themselves in a similar fashion. For example, a fabrication defect could result in a discontinuity in a wire,
REF proposes a microprocessor design integrated with a dynamic verification based error detection mechanism to diagnose hard faults in FUs.
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)
38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)
Computer Science