Energy consumption has become a major design constraint in modern computing systems. With the advent of petaflops architectures, power-efficient software stacks have become imperative for scalability. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause significant performance loss due to the system overhead. Typically, these techniques are used by constraining a priori the application performance loss, under which the energy savings are sought. This paper discusses potential drawbacks of such usage and proposes an energy-saving scheme that takes into account the instantaneous processor power consumption as presented by the "running average power limit" (RAPL) technology from Intel. Thus, the need for the user to predefine a performance loss tolerance is avoided. Experiments, performed on NAS benchmarks, show that the proposed scheme saves more energy than the approaches based on the predefined performance loss.
Sundriyal et al. REF present an energy management approach, relying on the Intel Running Average Power Limit (RAPL).
Runtime power-aware energy-saving scheme for parallel applications
Int. J. High Perform. Syst. Archit.
Int. J. High Perform. Syst. Archit.
Computer Science