Security is becoming the primary concern in today's embedded systems. Network-on-Chip (NoC) based communication architectures have emerged as an alternative to shared bus mechanism in multi-core SoC devices and the increasing number and functionality of processing cores has made such systems vulnerable to security attacks. In this paper a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in a NoC-based multi-core shared memory architecture. Our IAV module is implemented on a FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyse the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.
In our previous work REF , we have presented an identity and address verification-based security module for multi-core systems in order to detect security attacks and stop illegal accesses to the memory.
Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems
Journal of Circuits, Systems, and Computers
Journal of Circuits, Systems, and Computers
Computer Science