Abstract. This paper presents the derivation of a denotational semantics from an operational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build an equivalence between the operational and denotational semantics. We propose a discrete time semantic model for Verilog. Algebraic laws are also investigated in this paper, with the ultimate aim of providing a unified set of semantic views for Verilog.
Zhu et al. REF derived a denotational semantics from the proposed operational semantics for the hardware description language Verilog.
From Operational Semantics to Denotational Semantics for Verilog
CHARME
Computer Science