Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the signijicant byte positions. This significance compression method is integrated into a 5-stage pipeline, with the extension bitsflowing down the pipeline to enable pipeline operations only for the signijicant bytes. Consequently registel; logic, and cache activity (and dynamic power) are substantially reduced. An initial trace-driven stud.y shows reduction in activity of approximately 30-40% for each pipeline stage. Several pipeline organizations are studied. A byte serial pipeline is the simplest implementation, but suffers a CPI (cycles per instruction) increase of 79% compared with a conventional 32-bit pipeline. Widening certain pipeline stages in order to balance processing bandwidth leads to an implementation with a CPI 24% higher than the baseline 32-bit design. Finally, full-width pipeline stages with operand gating achieve a CPI within 2-6% of the baseline 32-bit pipeline.
A technique to compress data addresses and instructions by maintaining only significant bytes with two or three extension bits appended to indicate significant byte positions was proposed in REF .
Very low power pipelines using significance compression