can be imdemented in hardware and software bv using a dedicated Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SOC.
As an example, a state-based power modelling technique for a System on Chip (SoC) is presented in REF .
State-based power analysis for systems-on-chip
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)
Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)
Computer Science