This paper describes an analytical model that relates the architectural parameters of an FPGA to the average prerouting wirelength of an FPGA implementation. Both homogeneous and heterogeneous FPGAs are considered. For homogeneous FPGAs, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the expected wirelength. For heterogeneous FPGAs, the number and positioning of the embedded blocks, as well as the number of pins on each embedded block is considered. Two applications of the model to FPGA architectural design are also presented.
Smith et al. presents a model to estimate post-placement wirelength for both homogeneous and hetergenous FPGA architectures REF .
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development
FPGA '09
Computer Science