Video Coding (HEVC) standard has very high computational complexity. In this paper, an efficient FPGA implementation of HEVC intra prediction is proposed for 4x4, 8x8, 16x16 and 32x32 angular prediction modes. In the proposed FPGA implementation, one intra angular prediction equation is implemented using one DSP block in FPGA. The proposed FPGA implementation, in the worst case, can process 55 Full HD (1920x1080) video frames per second. It has up to 34.66% less energy consumption than the original FPGA implementation of HEVC intra prediction. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.
An energy consumption reduction of 34.66% compared to the original HEVC intra prediction is reported in REF .
An efficient FPGA implementation of HEVC intra prediction
2018 IEEE International Conference on Consumer Electronics (ICCE)
2018 IEEE International Conference on Consumer Electronics (ICCE)
Computer Science