ABSTRACT | This comprehensive review summarizes state of the art, challenges, and prospects of the neuro-inspired computing with emerging nonvolatile memory devices. First, we discuss the demand for developing neuro-inspired architecture beyond today's von-Neumann architecture. Second, we summarize the various approaches to designing the neuromorphic hardware (digital versus analog, spiking versus nonspiking, online training versus offline training) and discuss why emerging nonvolatile memory is attractive for implementing the synapses in the neural network. Then, we discuss the desired device characteristics of the synaptic devices (e.g., multilevel states, weight update nonlinearity/ asymmetry, variation/noise), and survey a few representative material systems and device prototypes reported in the literature that show the analog conductance tuning. These candidates include phase change memory, resistive memory, ferroelectric memory, floating-gate transistors, etc. Next, we introduce the crossbar array architecture to accelerate the weighted sum and weight update operations that are commonly used in the neuroinspired machine learning algorithms, and review the recent progresses of array-level experimental demonstrations for pattern recognition tasks. In addition, we discuss the peripheral neuron circuit design issues and present a device-circuit-algorithm codesign methodology to evaluate the impact of nonideal device effects on the system-level performance (e.g., learning accuracy).  Artificial intelligence (AI) that allows machines to think and act like human beings is reviving, which is a hot topic today not only in academia but also having a remarkable social impact (e.g., Google's AlphaGo [1]). In recent years, artificial neural networks (i.e., machine/deep learning) have shown significantly improved accuracy in large-scale visual/auditory recognition and classification tasks, some even surpassing human-level accuracy [2] . In particular, convolutional neural network (CNN) [3] and recurrent neural network (RNN) [4] algorithms and their variants have proved their efficacy in a wide range of image, video, speech, and biomedical applications. To achieve incremental accuracy improvement, state-of-the-art deep learning algorithms tend to aggressively increases the depth and size of the neural network. For example, Microsoft's Res-Net (which won the ImageNet 2015 image classification competition [5] ) has more than 100 of layers [6] . This poses significant challenges for hardware implementations in terms of computation, memory, and communication resources. For example, Google's stacked autoencoder algorithm was able to successfully identify faces of cats from ten million random images taken from YouTube videos [7] . Yet this task was accomplished on a cluster of 16 000 processor cores consuming ~ 100 kW of power and used three days to train the network. Today's deep learning is typically trained with graphic processing unit (GPU) accelerators on the data center or the cloud side. Specific designed accelerators such as Manchester's SpiNNaker [8], Heidelberger's BrainScaleS [9] , and Google's tensor processing unit (TPU) [10] have been developed to run large-scale neuromorphic and/or deep learning algorithms. On the embedded system or Internet of Things (IoT) edge computing side, such as autonomous driving, smart sensors, and wearable devices, severe design constraints exist in performance, power, and  This article offers a timely review of the state of the art, challenges, and prospects of neuro-inspired computing with such emerging nonvolatile memory devices.
A review of neuro-inspired computing on non-volatile memories is provided in Reference REF .
Neuro-Inspired Computing With Emerging Nonvolatile Memorys
Proceedings of the IEEE
Proceedings of the IEEE
Computer Science