ABSTRACT In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate the power consumption and performance of wireless communication base-band systems implemented in field-programmable gate arrays (FPGAs). As the complexity of such systems is still growing, being able to estimate both power and performance of a design has become a major issue. FPGA devices constitute a promising technology in this highly constrained context. However, to respect their power budget, designers need to explore the design space very soon in the design process. This is performed prior to any implementation. Based on the innovative definition of a scenario, which enables comparison among wireless communication applications in a formal manner, each parameter can be evaluated to meet the power-performance tradeoff. In this paper, the proposed methodology is realized in two steps using a low-level characterization process and high-level system modeling. Another major contribution consists in considering components' time activity to refine power estimations results. We demonstrate the effectiveness of the proposed methodology throughout several domain-specific use cases, with a focus on hardware base-band processing in the wireless communication domain. As compared with current low-level FPGAs vendor tools, an important speedup factor is obtained, and a maximal relative error lower than 5% is reached. INDEX TERMS Wireless communication, field programmable gate array, power consumption, system modelling, SystemC.
A System-level power estimation model was proposed in REF for the wireless communication systems, implemented on the FPGA.
Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems
IEEE Access
IEEE Access
Computer Science