Abstract Dynamic reconfiguration of FPGAs has recently become viable with the introduction of devices that allow high speed partial reconfiguration, e.g., the Xilinx XC6200 series [ 141. Dynamic reconfiguration is usually performed by a software system that decides when to reprogram part of the FPGA and with what. The simplest kind of run-time software simply selects a precompiled circuit and transmits the programming data directly to the FPGA. At the University of Glasgow's Department of Computing Science, the Reconfigurable Architecture Group (RAGE) has a number of projects examining applications of dynamic reconfiguration. These applications have highlighted the need for a more complex run-time system. Rather than developing different run-time systems for each application, as is common, we have extracted a set of common requirements from several applications. This has formed the basis of the design of a proposed, core, run-time system, able to support all of these applications. There are many parallels that can be drawn between this design and conventional operating system design-as the techniques used to manage conventional resources, such as memory and the CPU, are also applicable to the management of FPGAs. The next section of this paper describes three applications of dynamic reconfiguration and their requirements, and draws from these a set of core requirements. We follow this with an overview of the proposed system, and more detailed discussions of the r6les of the identified system components. We close with a discussion of how our system might support other applications in the field. Case Studies The FPGAPS project aims to exploit the dynamic reconfigurability of FPGAs to accelerate PostScript@ rendering.  A collection of pre-routed and placed circuits reside in the main memory of the host system, ready for rapid download onto the FPGA over a PCI bus. The FPGA is housed on the board shown in Figure 1 . At pre-defined intervals during PostScript60 rendering, data and operation codes are passed as parameters to the virtual hardware run-time system. The system then swaps an appropriate circuit onto the P G A and also preioads circuit input registers with values passed from the application. As results are generated by the circuit, the application is interrupted allowing it to fetch the relevant data from some known memory location. Only one working circuit is resident on the chip at any time. Unlike other similar reconfigurable systems. our proposed system aims to factor out such common run-time support operations rather than hard-coding them into the application. To ease memory mapping between the FPGA, the RAGE system, and the FPGA/PS application, circuits can be organised in the following ways: 1. Some circuitry is held static on the P G A and serves as input and output ports for the dynamic circuitry. For instance, a circle rendering circuit needs (x, y ) coordinates for the centre and a radius value. These static input registers would be reused when the next rendering circuit is swapped in. This policy reduces the number of cells to be configured, but makes circuit placing less flexible. 2. The input and output ports of the circuit representation are tied to the working circuit itself, and the circuit is swapped onto a pre-determined location on the FPGA. 3. The circuits are able to be placed anywhere (within known boundaries) and the RAGE system organises the mapping of circuit registers into host memory transparently. To the application, these registers are at a well known address. Circuits which need no run-time place and route can be represented very simply, as addressldata pairs which form the P G A programming information. There is no need to have an internal representation of the FPGA itself, because no place and route need take place. If, however, more complex swapping is required (cases 2 and 3 above) some run-time place and route is required. A full representation of all the muxes and configuration memory on the chip is maintained by the run-time system. The internal representation of circuits needs to be richer too, encompassing knowledge of ports, hierarchical circuit blocks, etc. The circuit swapper has access to a library of circuits, and passes the programming data to the device driver. When a circuit is being swapped, it is important that the behaviour of the system is predictable. The circuit swapping mechanism should either isolate the on-chip static circuitry, or be aware that spurious results may be produced whilst swapping is in progress.
Burns et al. made one of the first efforts in the creation of an operating system (OS) inhabited in a partially reconfigurable device REF , where, based on three different applications, they extracted a set of common requirements, and designed a runtime system for managing the dynamic reconfiguration of FPGAs.
A dynamic reconfiguration run-time system
Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)
Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)
Computer Science