Abstract-A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an addressevent-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F (x; y) as long as it is decomposable into x-axis and y-axis components, i.e., F (x; y) = H (x)V (y), for some rotated coordinate system fx; yg and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations.
An alternative approach to event-based, 2D image filtering is the VLSI architecture proposed in REF , capable of implementing any convolutional kernel that is decomposable into x and y components.
AER Image Filtering Architecture for Vision-Processing Systems
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl
Computer Science