The use of caches poses a difficult rradeoff for architects of real-time systems. While caches provide signifreant performance advantages, they have also been viewed as inherently unpredictable since the behavior of a cache reference depends upon the history of the previous references. The use of caches will only be suitable for realtime systems i f a reasonably tight bound on the performance of programs using cache nzemory can be predirterl. This paper describes an approach for bounding the worstcase instruction cache performanre of large code segments. First, a new method called Static Cache Sitnulation is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. A timing analyzer, which uses the Categorization information, then estimates the worst-case instruction cache performance for each loop and function in the program.
The program control-flow graph is then analyzed and a caching categorization for each instruction in the program is produced REF .
Bounding worst-case instruction cache performance
1994 Proceedings Real-Time Systems Symposium
1994 Proceedings Real-Time Systems Symposium
Computer Science