Abstract-We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated FPGA hardware. Using a HLS tool implemented within the state-of-theart LLVM [1] compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, Fmax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality. Moreover, we show that hardware quality is also affected by the order in which optimizations are applied. We then present a new HLS-directed approach to compiler optimizations, wherein we execute partial HLS and profiling at intermittent points in the optimization process and use the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality. Results show that our approach produces circuits with 16% better speed performance, on average, versus using the standard -O3 optimization level.
The effect of standard LLVM optimizations on the QoR is explored in REF , where a 16% average improvement is reported.
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines
Computer Science