Specialized clustered VLIW processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work we propose a methodology to support early design space exploration of clustered VLIW datapaths, in the context of a specific target application. We argue that, due to the large size and complexity of the design space, the early design space exploration phase should consider only design space parameters that have a first-order impact on two key physical figures of merit: clock rate and power dissipation. These parameters were found to be: maximum cluster capacity, number of clusters, and bus (interconnect) capacity. Experimental validation of our design space exploration algorithm shows that a thorough exploration of the complex design space can be performed very efficiently in this abstract, parameterized design space. Moreover, an empirical study carried out on a representative set of computation-intensive benchmarks suggests that "penalties" of clustered versus centralized datapaths are often minimal and that clustering indeed unlocks a variety of valuable design tradeoffs.
REF present a kernel-specific and technologyindependent methodology for exploration of the design space of clustered VLIW ASIP data paths.
Application-Specific Clustered VLIW Datapaths: Early Exploration on a Parameterized Design Space
IEEE Transactions on Computer
Computer Science