user: Demonstrate the C code that generates the assembly output below:

```asm
<FS460_set_input_mode>:
  endbr64
  push   %rbp
  push   %rbx
  sub    $0x28,%rsp
  mov    %fs:0x28,%rax
  mov    %rax,0x18(%rsp)
  xor    %eax,%eax
  lea    -0x1(%rdi),%edx
  mov    $0x1000,%eax
  cmp    $0x1,%edx
  ja     L65
  mov    %edi,%ebx
  mov    %esi,%ebp
  lea    0x8(%rsp),%rsi
  mov    $0x3c,%edi
  call   <sio_read_reg@plt>
  test   %eax,%eax
  je     L118
L65:
  mov    0x18(%rsp),%rdx
  sub    %fs:0x28,%rdx
  jne    L174
  add    $0x28,%rsp
  pop    %rbx
  pop    %rbp
  ret
L118:
  lea    0x10(%rsp),%rsi
  mov    $0x3e,%edi
  call   <sio_read_reg@plt>
  test   %eax,%eax
  jne    L65
  cmp    $0x2,%ebp
  je     L24
  jg     L210
  test   %ebp,%ebp
  je     L163
  cmp    $0x1,%ebp
  jne    L161
  cmp    $0x1,%ebx
  je     L133
  andq   $0xfffffffffffff7ff,0x8(%rsp)
  mov    0x10(%rsp),%rax
  and    $0xfffffffffffff7fb,%rax
  or     $0x2020,%rax
  mov    %rax,0x10(%rsp)
  jmp    L161
L210:
  cmp    $0x3,%ebp
  jne    L161
  cmp    $0x1,%ebx
  je     L41
  andq   $0xfffffffffffff7ff,0x8(%rsp)
  orq    $0x2825,0x10(%rsp)
  jmp    L161
L163:
  cmp    $0x1,%ebx
  je     L107
  andq   $0xfffffffffffff7ff,0x8(%rsp)
  andq   $0xffffffffffffd7ff,0x10(%rsp)
  jmp    L161
L107:
  andq   $0xfffffffffffffbff,0x8(%rsp)
  andq   $0xffffffffffffebff,0x10(%rsp)
L161:
  mov    0x8(%rsp),%rsi
  mov    $0x3c,%edi
  call   <sio_write_reg@plt>
  test   %eax,%eax
  jne    L65
  mov    0x10(%rsp),%rsi
  mov    $0x3e,%edi
  call   <sio_write_reg@plt>
  jmp    L65
L133:
  andq   $0xfffffffffffffbff,0x8(%rsp)
  mov    0x10(%rsp),%rax
  and    $0xfffffffffffffbf7,%rax
  or     $0x1010,%rax
  mov    %rax,0x10(%rsp)
  jmp    L161
L24:
  cmp    $0x1,%ebx
  je     L53
  lea    0x4(%rsp),%rsi
  mov    $0x1,%edi
  call   <FS460_get_input_mode@plt>
  test   %eax,%eax
  jne    L65
  mov    $0x1125,%eax
  cmpl   $0x2,0x4(%rsp)
  je     L65
  orq    $0x800,0x8(%rsp)
  mov    0x10(%rsp),%rax
  and    $0xffffffffffffffde,%rax
  or     $0x28,%ah
  mov    %rax,0x10(%rsp)
  jmp    L161
L53:
  lea    0x4(%rsp),%rsi
  mov    $0x2,%edi
  call   <FS460_get_input_mode@plt>
  test   %eax,%eax
  jne    L65
  mov    $0x1125,%eax
  cmpl   $0x2,0x4(%rsp)
  je     L65
  orq    $0x400,0x8(%rsp)
  mov    0x10(%rsp),%rax
  and    $0xffffffffffffffee,%rax
  or     $0x14,%ah
  mov    %rax,0x10(%rsp)
  jmp    L161
L41:
  andq   $0xfffffffffffffbff,0x8(%rsp)
  orq    $0x1419,0x10(%rsp)
  jmp    L161
L174:
  call   <__stack_chk_fail@plt>
```

assistant: ```c
int FS460_set_input_mode(int input, int mode) {
  int err;
  unsigned long mux1, mux2;
  if ((1 != input) && (2 != input))
    return 0x1000;
  err = sio_read_reg(0x3C, &mux1);
  if (err)
    return err;
  err = sio_read_reg(0x3E, &mux2);
  if (err)
    return err;
  switch (mode) {
  case 0: {
    switch (input) {
    case 1: {
      mux1 &= ~(1 << 10);
      mux2 &= ~(1 << 10);
      mux2 &= ~(1 << 12);
    } break;
    case 2: {
      mux1 &= ~(1 << 11);
      mux2 &= ~(1 << 11);
      mux2 &= ~(1 << 13);
    }
    }
  } break;
  case 1: {
    switch (input) {
    case 1: {
      mux1 &= ~(1 << 10);
      mux2 &= ~(1 << 3);
      mux2 |= (1 << 4);
      mux2 &= ~(1 << 10);
      mux2 |= (1 << 12);
    } break;
    case 2: {
      mux1 &= ~(1 << 11);
      mux2 &= ~(1 << 2);
      mux2 |= (1 << 5);
      mux2 &= ~(1 << 11);
      mux2 |= (1 << 13);
    }
    }
  } break;
  case 2: {
    int i;
    switch (input) {
    case 1: {
      err = FS460_get_input_mode(2, &i);
      if (err)
        return err;
      if (2 == i)
        return 0x1125;
      mux1 |= (1 << 10);
      mux2 &= ~(1 << 0);
      mux2 &= ~(1 << 4);
      mux2 |= (1 << 10);
      mux2 |= (1 << 12);
    } break;
    case 2: {
      err = FS460_get_input_mode(1, &i);
      if (err)
        return err;
      if (2 == i)
        return 0x1125;
      mux1 |= (1 << 11);
      mux2 &= ~(1 << 0);
      mux2 &= ~(1 << 5);
      mux2 |= (1 << 11);
      mux2 |= (1 << 13);
    } break;
    }
  } break;
  case 3: {
    switch (input) {
    case 1: {
      mux1 &= ~(1 << 10);
      mux2 |= (1 << 0);
      mux2 |= (1 << 3);
      mux2 |= (1 << 4);
      mux2 |= (1 << 10);
      mux2 |= (1 << 12);
    } break;
    case 2: {
      mux1 &= ~(1 << 11);
      mux2 |= (1 << 0);
      mux2 |= (1 << 2);
      mux2 |= (1 << 5);
      mux2 |= (1 << 11);
      mux2 |= (1 << 13);
    } break;
    }
  } break;
  }
  err = sio_write_reg(0x3C, mux1);
  if (err)
    return err;
  err = sio_write_reg(0x3E, mux2);
  if (err)
    return err;
  return 0;
}
```