user: What would the C source look like for the assembly code provided here:

```asm
<bn_mul_comba4>:
  endbr64
  mov    %rdi,%r9
  mov    %rsi,%r8
  mov    %rdx,%rdi
  mov    (%rsi),%rax
  mulq   (%rdx)
  mov    $0x0,%r10d
  mov    %r10,%r11
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r10,%rcx
  mov    %r10,%rsi
  add    %rdx,%rcx
  adc    $0x0,%rsi
  mov    %r11,(%r9)
  mov    (%r8),%rax
  mulq   0x8(%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  mov    %r10,%r11
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    0x8(%r8),%rax
  mulq   (%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    %rcx,0x8(%r9)
  mov    0x10(%r8),%rax
  mulq   (%rdi)
  add    %rax,%rsi
  adc    $0x0,%rdx
  mov    %r10,%rcx
  add    %rdx,%r11
  adc    $0x0,%rcx
  mov    0x8(%r8),%rax
  mulq   0x8(%rdi)
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%r11
  adc    $0x0,%rcx
  mov    (%r8),%rax
  mulq   0x10(%rdi)
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%r11
  adc    $0x0,%rcx
  mov    %rsi,0x10(%r9)
  mov    (%r8),%rax
  mulq   0x18(%rdi)
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r10,%rsi
  add    %rdx,%rcx
  adc    $0x0,%rsi
  mov    0x8(%r8),%rax
  mulq   0x10(%rdi)
  add    %rax,%r11
  adc    $0x0,%rdx
  add    %rdx,%rcx
  adc    $0x0,%rsi
  mov    0x10(%r8),%rax
  mulq   0x8(%rdi)
  add    %rax,%r11
  adc    $0x0,%rdx
  add    %rdx,%rcx
  adc    $0x0,%rsi
  mov    0x18(%r8),%rax
  mulq   (%rdi)
  add    %rax,%r11
  adc    $0x0,%rdx
  add    %rdx,%rcx
  adc    $0x0,%rsi
  mov    %r11,0x18(%r9)
  mov    0x18(%r8),%rax
  mulq   0x8(%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  mov    %r10,%r11
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    0x10(%r8),%rax
  mulq   0x10(%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    0x8(%r8),%rax
  mulq   0x18(%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    %rcx,0x20(%r9)
  mov    0x10(%r8),%rax
  mulq   0x18(%rdi)
  mov    %rsi,%rcx
  add    %rax,%rcx
  adc    $0x0,%rdx
  mov    %r11,%rsi
  mov    %r10,%r11
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    0x18(%r8),%rax
  mulq   0x10(%rdi)
  add    %rax,%rcx
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r11
  mov    %rcx,0x28(%r9)
  mov    0x18(%r8),%rax
  mulq   0x18(%rdi)
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%r11
  adc    $0x0,%r10
  mov    %rsi,0x30(%r9)
  mov    %r11,0x38(%r9)
  ret
```

assistant: ```c
void bn_mul_comba4(unsigned long *r, unsigned long *a, unsigned long *b) {
  unsigned long t1, t2;
  unsigned long c1, c2, c3;
  c1 = 0;
  c2 = 0;
  c3 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[0]), "m"(b[0]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[0] = c1;
  c1 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[0]), "m"(b[1]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[1]), "m"(b[0]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[1] = c2;
  c2 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[2]), "m"(b[0]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[1]), "m"(b[1]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[0]), "m"(b[2]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[2] = c3;
  c3 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[0]), "m"(b[3]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[1]), "m"(b[2]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[2]), "m"(b[1]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[3]), "m"(b[0]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[3] = c1;
  c1 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[3]), "m"(b[1]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[2]), "m"(b[2]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[1]), "m"(b[3]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[4] = c2;
  c2 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[2]), "m"(b[3]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[3]), "m"(b[2]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[5] = c3;
  c3 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"(a[3]), "m"(b[3]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[6] = c1;
  r[7] = c2;
}
```