user: Demonstrate the C code that generates the assembly output below:

```asm
<bn_sqr_comba8>:
  endbr64
  mov    %rdi,%r9
  mov    %rsi,%rcx
  mov    (%rsi),%rax
  mul    %rax
  mov    $0x0,%r10d
  mov    %r10,%r8
  add    %rax,%r8
  adc    $0x0,%rdx
  mov    %r10,%rsi
  mov    %r10,%rdi
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    %r8,(%r9)
  mov    0x8(%rcx),%rax
  mulq   (%rcx)
  mov    %r10,%r8
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    %rsi,0x8(%r9)
  mov    0x8(%rcx),%rax
  mul    %rax
  add    %rax,%rdi
  adc    $0x0,%rdx
  mov    %r10,%rsi
  add    %rdx,%r8
  adc    $0x0,%rsi
  mov    0x10(%rcx),%rax
  mulq   (%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rsi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%r8
  adc    $0x0,%rsi
  mov    %rdi,0x10(%r9)
  mov    0x18(%rcx),%rax
  mulq   (%rcx)
  mov    %r10,%rdi
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    0x10(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    %r8,0x18(%r9)
  mov    0x10(%rcx),%rax
  mul    %rax
  add    %rax,%rsi
  adc    $0x0,%rdx
  mov    %r10,%r8
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x18(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x20(%rcx),%rax
  mulq   (%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    %rsi,0x20(%r9)
  mov    0x28(%rcx),%rax
  mulq   (%rcx)
  mov    %r10,%rsi
  add    %rdx,%rdx
  adc    $0x0,%rsi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%r8
  adc    $0x0,%rsi
  mov    0x20(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rsi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%r8
  adc    $0x0,%rsi
  mov    0x18(%rcx),%rax
  mulq   0x10(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rsi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%r8
  adc    $0x0,%rsi
  mov    %rdi,0x28(%r9)
  mov    0x18(%rcx),%rax
  mul    %rax
  add    %rax,%r8
  adc    $0x0,%rdx
  mov    %r10,%rdi
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    0x20(%rcx),%rax
  mulq   0x10(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    0x28(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    0x30(%rcx),%rax
  mulq   (%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    %r8,0x30(%r9)
  mov    0x38(%rcx),%rax
  mulq   (%rcx)
  mov    %r10,%r8
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x30(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x28(%rcx),%rax
  mulq   0x10(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  mov    %rsi,%r11
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r8,%rsi
  add    %rdx,%rdi
  adc    $0x0,%rsi
  mov    0x20(%rcx),%rax
  mulq   0x18(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rsi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r11
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%rsi
  mov    %r11,0x38(%r9)
  mov    0x20(%rcx),%rax
  mul    %rax
  add    %rax,%rdi
  adc    $0x0,%rdx
  mov    %r10,%r8
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    0x28(%rcx),%rax
  mulq   0x18(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    0x30(%rcx),%rax
  mulq   0x10(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  mov    %rdi,%r11
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r8,%rdi
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    0x38(%rcx),%rax
  mulq   0x8(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%r11
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    %r11,0x40(%r9)
  mov    0x38(%rcx),%rax
  mulq   0x10(%rcx)
  mov    %r10,%r8
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x30(%rcx),%rax
  mulq   0x18(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x28(%rcx),%rax
  mulq   0x20(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    %rsi,0x48(%r9)
  mov    0x28(%rcx),%rax
  mul    %rax
  add    %rax,%rdi
  adc    $0x0,%rdx
  mov    %r8,%rsi
  mov    %r10,%r8
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    0x30(%rcx),%rax
  mulq   0x20(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    0x38(%rcx),%rax
  mulq   0x18(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  mov    %rdi,%r11
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r8,%rdi
  add    %rdx,%rsi
  adc    $0x0,%rdi
  mov    %r11,0x50(%r9)
  mov    0x38(%rcx),%rax
  mulq   0x20(%rcx)
  mov    %r10,%r8
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r8
  mov    0x30(%rcx),%rax
  mulq   0x28(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  mov    %rsi,%r11
  add    %rax,%r11
  adc    $0x0,%rdx
  mov    %r8,%rsi
  add    %rdx,%rdi
  adc    $0x0,%rsi
  mov    %r11,0x58(%r9)
  mov    0x30(%rcx),%rax
  mul    %rax
  add    %rax,%rdi
  adc    $0x0,%rdx
  mov    %r10,%r8
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    0x38(%rcx),%rax
  mulq   0x28(%rcx)
  add    %rdx,%rdx
  adc    $0x0,%r8
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rdi
  adc    $0x0,%rdx
  add    %rdx,%rsi
  adc    $0x0,%r8
  mov    %rdi,0x60(%r9)
  mov    0x38(%rcx),%rax
  mulq   0x30(%rcx)
  mov    %r10,%rdi
  add    %rdx,%rdx
  adc    $0x0,%rdi
  add    %rax,%rax
  adc    $0x0,%rdx
  add    %rax,%rsi
  adc    $0x0,%rdx
  add    %rdx,%r8
  adc    $0x0,%rdi
  mov    %rsi,0x68(%r9)
  mov    0x38(%rcx),%rax
  mul    %rax
  add    %rax,%r8
  adc    $0x0,%rdx
  add    %rdx,%rdi
  adc    $0x0,%r10
  mov    %r8,0x70(%r9)
  mov    %rdi,0x78(%r9)
  ret
```

assistant: ```c
void bn_sqr_comba8(unsigned long *r, unsigned long *a) {
  unsigned long t1, t2;
  unsigned long c1, c2, c3;
  c1 = 0;
  c2 = 0;
  c3 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[0]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[0] = c1;
  c1 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[1]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[1] = c2;
  c2 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[1]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[2]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[2] = c3;
  c3 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[3]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[2]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[3] = c1;
  c1 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[2]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[3]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[4]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[4] = c2;
  c2 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[5]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[4]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[3]), "m"((a)[2]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[5] = c3;
  c3 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[3]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[4]), "m"((a)[2]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[5]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[6] = c1;
  c1 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[0]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[5]), "m"((a)[2]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[4]), "m"((a)[3]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[7] = c2;
  c2 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[4]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[5]), "m"((a)[3]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[2]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[1]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[8] = c3;
  c3 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[2]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[3]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[5]), "m"((a)[4]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[9] = c1;
  c1 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[5]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[4]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[3]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[10] = c2;
  c2 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[4]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[6]), "m"((a)[5]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c2) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[11] = c3;
  c3 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[6]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[5]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c3) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+r"(c3) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[12] = c1;
  c1 = 0;
  do {
    asm("mulq %3" : "=a"(t1), "=d"(t2) : "a"((a)[7]), "m"((a)[6]) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+d"(t2), "+r"(c1) : "g"(0) : "cc");
    asm("addq %0,%0; adcq %2,%1" : "+a"(t1), "+d"(t2) : "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c2), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+r"(c1) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[13] = c2;
  c2 = 0;
  do {
    asm("mulq %2" : "=a"(t1), "=d"(t2) : "a"(a[7]) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c3), "+d"(t2) : "a"(t1), "g"(0) : "cc");
    asm("addq %2,%0; adcq %3,%1" : "+r"(c1), "+r"(c2) : "d"(t2), "g"(0) : "cc");
  } while (0);
  r[14] = c3;
  r[15] = c1;
}
```