ASIC RTL Design Engineer, Machine Learning Accelerators at Google

info_outline X Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Madison, WI, USA . Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. 2 years of experience in Digital design using SystemVerilog RTL. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. 4 years of experience in digital…