[Fascinate Android Development] Agenthex:
I removed the link as well as the kernel images. You would be better off running a kernel found in ROM manager. That being said, I would like to leave this along with a link to the Samsung S5PC110 technical document: http://dl.dropbox.com/u/13699504/S5PC110_EVT1_UM10.pdf

For those brave enough to tweak their own, I present to you the locations of things to change.

PART 1: CPU AND OTHER ARM SUBSYSTEM FREQUENCIES

First off, there are three files you will want to look at and become familiar with: s5pc110-clock.c is the code that will control the CPU frequency. s5pc11x-dvfs.c controls the throttling thresholds for switching from one mode to another. max8998_consumer.c controls voltage levels for the Maxim 8998 voltage regulator. Although it doesn't state granulatrity, I've assumed it to be 25-unit increments measured in mV.

s5pc110-clock.c:

/*APLL_FOUT, MPLL_FOUT, ARMCLK, HCLK_DSYS*/
static const u32 s5p_sysout_clk_tab_1GHZ[][4] = {
// APLL:1000,ARMCLK:1000,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{1066* MHZ, 667 *MHZ, 1066 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:800,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{800* MHZ, 667 *MHZ, 800 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:400,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{400* MHZ, 667 *MHZ, 400 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{200* MHZ, 667 *MHZ, 200 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:100,HCLK_MSYS:100,MPLL:667,HCLK_DSYS:83,HCLK_PSYS:66,PCLK_MSYS:50,PCLK_DSYS:66,PCLK_PSYS:66
{100* MHZ, 667 *MHZ, 100 *MHZ, 133 *MHZ},
};

#define DIV_TAB_MAX_FIELD 12

//yhkim hack from TR note. We got TechnicalReport-S5PC110_Android_DRAMin_DVFSlevel4.doc.
//please check it. we change last value to 7. original val is 4 in s5p_sys_clk_div0_tab_1GHZ.
/*div0 ratio table*/
/*apll, a2m, HCLK_MSYS, PCLK_MSYS, HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, MFC_DIV, G3D_DIV, MSYS source(2D, 3D, MFC)(0->apll,1->mpll), DMC0 div*/
static const u32 s5p_sys_clk_div0_tab_1GHZ[][DIV_TAB_MAX_FIELD] = {
{0, 4, 4, 1, 3, 1, 4, 1, 3, 3, 0, 3},
{0, 3, 3, 1, 3, 1, 4, 1, 3, 3, 0, 3},
{1, 3, 1, 1, 3, 1, 4, 1, 3, 3, 0, 3},
{3, 3, 0, 1, 3, 1, 4, 1, 3, 3, 0, 3},
{7, 7, 0, 0, 7, 0, 9, 0, 3, 3, 1, 7},
};

/*pms value table*/
/*APLL(m, p, s), MPLL(m, p, s)*/
static const u32 s5p_sys_clk_mps_tab_1GHZ[][6] = {
{266, 6, 1, 667, 12, 1},
{200, 6, 1, 667, 12, 1},
{200, 6, 1, 667, 12, 1},
{200, 6, 1, 667, 12, 1},
{200, 6, 1, 667, 12, 1},
};

PART 2: VOLTAGES

The only things I've found worthy of noting about how to enter values in here are:

1) The clock speed can be anything you want it to be.

2) The voltage in frequency_match_1GHZ (same line as frequency) might not be used to set the voltage gates. It may be used only to report to /proc/cpuinfo or other monitoring systems (SetCPU).

3) The third column is either 1100 or 1000. So far, it's always 1100 when not in the lowest power configuration. At that point, it's 1000. I think this has to do with the system-wide power configuration (not the CPU/GPU), and you may be able to increase it, but I have not tried. Please be very careful with this, as CPUs are generally more robust in terms of thermal compensation than other components.

4) dvs_volt_table_1GHZ is where you set the voltages (dvs_volt_table_800MHZ for boot mode). You set them by linking DVSARM# (1-5, 1GHZ / 1-4, 800MHz boot) and DVSINT# (1/2 for 1100/1000).

/* frequency voltage matching table */
static const unsigned int frequency_match_1GHZ[][4] = {
/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/
{1066000, 1175, 1100, 0}, // Mine tested stable at 1175. Your mileage may vary.
{800000, 1075, 1100, 1}, // Stable at 1075. YMMV.
{400000, 950, 1100, 2}, // Stable at 950. YMMV.
{200000, 950, 1000, 4}, // Stable at 950. YMMV.
{100000, 950, 1000, 5}, // Stable at 950. YMMV.
};

static const unsigned int frequency_match_800MHZ[][4] = {
/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/
{800000, 1100, 1100, 0},
{400000, 1050, 1100, 1},
{200000, 950, 1100, 3},
{100000, 950, 1000, 4},
};
const unsigned int (*frequency_match[2])[4] = {
frequency_match_1GHZ,
frequency_match_800MHZ,
};

/* voltage table */
static const unsigned int voltage_table[16] = {
750, 800, 850, 900, 950, 1000, 1050,
1100, 1150, 1200, 1250, 1300, 1350,
1400, 1450, 1500
};

extern unsigned int S5PC11X_FREQ_TAB;
//extern const unsigned int (*frequency_match[2])[4];

static struct regulator *Reg_Arm = NULL, *Reg_Int = NULL;

static unsigned int s_arm_voltage=0, s_int_voltage=0;
unsigned long set1_gpio;
unsigned long set2_gpio;
unsigned long set3_gpio;

/*only 4 Arm voltages and 2 internal voltages possible*/
static const unsigned int dvs_volt_table_800MHZ[][3] = {
{L0, DVSARM2, DVSINT1},
{L1, DVSARM3, DVSINT1},
//266 {L2, DVSARM3, DVSINT1},
{L2, DVSARM4, DVSINT1},
{L3, DVSARM4, DVSINT2},
// {L4, DVSARM4, DVSINT2},
// {L5, DVSARM4, DVSINT2},
};

static const unsigned int dvs_volt_table_1GHZ[][3] = {
{L0, DVSARM1, DVSINT1},//DVSINT0
{L1, DVSARM2, DVSINT1},
{L2, DVSARM3, DVSINT1},
//266 {L3, DVSARM3, DVSINT1},
{L3, DVSARM4, DVSINT2},
{L4, DVSARM4, DVSINT2},
// {L5, DVSARM4, DVSINT2},
// {L6, DVSARM4, DVSINT2},
};

const unsigned int (*dvs_volt_table[2])[3] = {
dvs_volt_table_1GHZ,
dvs_volt_table_800MHZ,
};

static const unsigned int dvs_arm_voltage_set[][2] = {
{DVSARM1, 1275},
{DVSARM2, 1100},
{DVSARM3, 1050},
{DVSARM4, 950},
{DVSINT1, 1100},
{DVSINT2, 1000},
};

That about concludes what I know about this. Thank you for the discussion, and happy hacking.