[G1 Android Development] scholbert:
prepare for MSM7200 OpenOCD NAND acccess

Hi,

today i started playing around with the NAND registers using OpenOCD on the Dream in blue led mode. ARM9 has to be set in halt mode first.

Consider this to be a proof of concept, before i'll start to integrate some rudimentary MSM NAND interface to openOCD.

As already stated i'm a lousy programmer, but it seems that some parts could be implemented quite easily.

If i just would have the time to do....

So here are some commented lines from my session:

mwb 0xA0A00000 0x01	Soft reset NAND controller
mdw 0xA0A0000C => 0x00000004	Read status of NAND_FLASH_CHIP_SELECT
mwb 0xA0A00000 0x0B	Write command 0x0B (fetch ID) NAND_FLASH_CMD
mwb 0xA0A00010 0x01	Send execute 0x1 to NANDC_EXEC_CMD
mdw 0xA0A00040 => 0x5510baad	Read ID from NAND_FLASH_READ_ID

mww 0xA0A00004 0x00000000	Write address to NAND_ADDR0 (send in four cycles to NAND, LSB first)
mww 0xA0A00008 0x00000000	Write page address to NAND_ADDR1
mwb 0xA0A00000 0x32	Write command 0x32 to NAND_FLASH_CMD (enable page commands, page read)
mwb 0xA0A00010 0x01	Send execute 0x1 to NANDC_EXEC_CMD

mdw 0xA0A00100 0x84	Read data from buffer (132 words)
0xa0a00100: 83838383 73d71034 00000001 00000a8c 00000280 8000e000 0001018c 0001018c
0xa0a00120: 8001e18c 00000000 8001e18c 00000000 00000000 00000000 000000af 80ff0000
0xa0a00140: 00000016 00000002 00000151 00000002 00000152 00000000 00000153 0000000d
0xa0a00160: 00000158 00000040 00000159 00000400 0000015a 00000014 0000015c 00000005
0xa0a00180: 00000022 00e00480 00000023 45f04d99 00000024 85e08580 00000025 ....

Result is the content of page0 (MIBIB area) in the NAND buffer at 0xA0A00100.

The flash buffer size is 132x32Bit = 528 bytes (512 bytes data + 16 bytes spare)

To get an idea of the dedicated registers, here's msm_nand.h from android legacy bootloader:

#ifndef __ASM_ARCH_MSM7200_NAND_H
#define __ASM_ARCH_MSM7200_NAND_H

#define MSM_NAND_BASE 0xA0A00000

#define NAND_REG(off) (MSM_NAND_BASE + (off))

#define NAND_FLASH_CMD NAND_REG(0x0000)
#define NAND_ADDR0 NAND_REG(0x0004)
#define NAND_ADDR1 NAND_REG(0x0008)
#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
#define NAND_EXEC_CMD NAND_REG(0x0010)
#define NAND_FLASH_STATUS NAND_REG(0x0014)
#define NAND_BUFFER_STATUS NAND_REG(0x0018)
#define NAND_DEV0_CFG0 NAND_REG(0x0020)
#define NAND_DEV0_CFG1 NAND_REG(0x0024)
#define NAND_DEV1_CFG0 NAND_REG(0x0030)
#define NAND_DEV1_CFG1 NAND_REG(0x0034)
#define NAND_READ_ID NAND_REG(0x0040)
#define NAND_READ_STATUS NAND_REG(0x0044)
#define NAND_CONFIG_DATA NAND_REG(0x0050)
#define NAND_CONFIG NAND_REG(0x0054)
#define NAND_CONFIG_MODE NAND_REG(0x0058)
#define NAND_CONFIG_STATUS NAND_REG(0x0060)
#define NAND_MACRO1_REG NAND_REG(0x0064)
#define NAND_XFR_STEP1 NAND_REG(0x0070)
#define NAND_XFR_STEP2 NAND_REG(0x0074)
#define NAND_XFR_STEP3 NAND_REG(0x0078)
#define NAND_XFR_STEP4 NAND_REG(0x007C)
#define NAND_XFR_STEP5 NAND_REG(0x0080)
#define NAND_XFR_STEP6 NAND_REG(0x0084)
#define NAND_XFR_STEP7 NAND_REG(0x0088)
#define NAND_DEV_CMD0 NAND_REG(0x00A0)
#define NAND_DEV_CMD1 NAND_REG(0x00A4)
#define NAND_DEV_CMD2 NAND_REG(0x00A8)
#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
#define NAND_FLASH_BUFFER NAND_REG(0x0100)

/* device commands */

#define NAND_CMD_SOFT_RESET 0x01
#define NAND_CMD_PAGE_READ 0x32
#define NAND_CMD_PAGE_READ_ECC 0x33
#define NAND_CMD_PAGE_READ_ALL 0x34
#define NAND_CMD_SEQ_PAGE_READ 0x15
#define NAND_CMD_PRG_PAGE 0x36
#define NAND_CMD_PRG_PAGE_ECC 0x37
#define NAND_CMD_PRG_PAGE_ALL 0x39
#define NAND_CMD_BLOCK_ERASE 0x3A
#define NAND_CMD_FETCH_ID 0x0B
#define NAND_CMD_STATUS 0x0C
#define NAND_CMD_RESET 0x0D

#endif

You might have noticed that this had already been posted here, i just wanted to put it down again for completeness :rolleyes:

Best regards,

scholbert