[Samsung Galaxy S9 & S9+ Cross Device Development] murtzsch:
Thanks for the msg, but the kernel I've compiled is already based on this tree, the commit is about removing debug messages.

The info/warn/err messages I was constantly getting are more like these :

06-23 20:48:15.922 0 0 W [3:dhd_rpm_state_t: 2833] dhd_runtimepm_state: DHD Idle state!! - idletime :11, wdtick :100
06-23 20:48:15.922 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_bus_suspend: Entering suspend state
06-23 20:48:15.922 0 0 W [3:dhd_rpm_state_t: 2833] __dhd_txflowcontrol: Netif Queue has already stopped
06-23 20:48:15.922 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_send_mb_data: H2D_MB_DATA: 0x00000001
06-23 20:48:15.925 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_send_mb_data: send H2D_HOST_D3_INFORM to dongle
06-23 20:48:15.937 0 0 W I[4: swapper/4: 0] D2H_MB_DATA: D3 ACK
06-23 20:48:15.937 0 0 W I[4: swapper/4: 0] dhd_bus_handle_d3_ack: D3_ACK Recieved
06-23 20:48:15.937 0 0 W I[4: swapper/4: 0] dhdpci_bus_read_frames: Bus is in power save state (2). Skip processing rest of ring buffers.
06-23 20:48:15.938 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_bus_suspend: Got D3 Ack
06-23 20:48:15.938 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_dump_resource: BAR0(VA): 0x0000000000000000, BAR0(PA): 0x0000000011c00000, SIZE: 32768
06-23 20:48:15.938 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_dump_resource: BAR1(VA): 0x0000000000000000, BAR1(PA): 0x0000000011800000, SIZE: 4194304
06-23 20:48:15.938 0 0 W [3:dhd_rpm_state_t: 2833] dhdpcie_suspend_dev: Enter
06-23 20:48:15.939 0 0 W [3:dhd_rpm_state_t: 2833] BEFORE_EP_SUSPEND: BaseAddress0(0x10)=0x11c00004, BaseAddress1(0x18)=0x11800004 PCIE_CFG_PMCSR(0x4c)=0x4108
06-23 20:48:15.964 0 0 W [3:dhd_rpm_state_t: 2833] AFTER_EP_SUSPEND: BaseAddress0(0x10)=0x11c00004, BaseAddress1(0x18)=0x11800004 PCIE_CFG_PMCSR(0x4c)=0x410b
06-23 20:48:15.965 0 0 I : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_poweroff, start of poweroff, pcie state: 2
06-23 20:48:15.965 0 0 I : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_send_pme_turn_off: link state:d
06-23 20:48:15.965 0 0 E : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: Current LTSSM State is 0xd with retry_cnt =0.
06-23 20:48:15.965 0 0 E : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: ack message is ok
06-23 20:48:15.965 0 0 E : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: received Enter_L23_READY DLLP packet
06-23 20:48:15.965 0 0 I : [3:dhd_rpm_state_t: 2833] SysMMU alloc num : 1092(Max:1130), lv2_alloc : 52, fault : 0
06-23 20:48:15.965 0 0 I : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_poweroff: Set PERST to LOW, gpio val = 0
06-23 20:48:15.965 0 0 I : [3:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_poweroff, end of poweroff, pcie state: 0

06-23 20:48:18.957 0 0 W [0:dhd_rpm_state_t: 2833] dhdpcie_bus_suspend: Entering resume state
06-23 20:48:18.957 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_poweron, start of poweron, pcie state: 0
06-23 20:48:18.957 0 0 E : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: pcie clk enable, ret value = 0
06-23 20:48:18.957 0 0 I : [0:dhd_rpm_state_t: 2833] Set TLB MATCH address for TLB1 Pinning : 0x9_7cc00000 ~ 0x9_7ce00000
06-23 20:48:18.957 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_establish_link: Set PERST to HIGH, gpio val = 1
06-23 20:48:18.978 0 0 E : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: phy clk enable, ret value = 0
06-23 20:48:18.978 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: Set I/A for CDR reset.
06-23 20:48:18.978 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: D state: 0, 47b100
06-23 20:48:18.978 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_establish_link: Link up:1dd8411
06-23 20:48:18.979 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: Current Link Speed is GEN1 (MAX GEN2)
06-23 20:48:18.979 0 0 E : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: l1ss enabled(0x0)
06-23 20:48:18.979 0 0 I : [0:dhd_rpm_state_t: 2833] exynos-pcie 116a0000.pcie0: exynos_pcie_poweron, end of poweron, pcie state: 3
06-23 20:48:18.979 0 0 W [0:dhd_rpm_state_t: 2833] dhdpcie_resume_dev: Enter
06-23 20:48:18.981 0 0 W [0:dhd_rpm_state_t: 2833] AFTER_EP_RESUME: BaseAddress0(0x10)=0x11c00004, BaseAddress1(0x18)=0x11800004 PCIE_CFG_PMCSR(0x4c)=0x4108
06-23 20:48:18.982 0 0 W [0:dhd_rpm_state_t: 2833] dhdpcie_dump_resource: BAR0(VA): 0x0000000000000000, BAR0(PA): 0x0000000011c00000, SIZE: 32768
06-23 20:48:18.982 0 0 W [0:dhd_rpm_state_t: 2833] dhdpcie_dump_resource: BAR1(VA): 0x0000000000000000, BAR1(PA): 0x0000000011800000, SIZE: 4194304
06-23 20:48:18.982 0 0 W [0:dhd_rpm_state_t: 2833] dhd_bus_hostready: Read PCICMD Reg: 0x00100006
06-23 20:48:18.983 0 0 W [0:dhd_rpm_state_t: 2833] dhd_bus_dump_dar_registers: DAR not supported for corerev(23) < 24
06-23 20:48:18.983 0 0 W [0:dhd_rpm_state_t: 2833] dhd_bus_hostready: Ring Hostready:244
06-23 20:48:18.983 0 0 W [0:dhd_rpm_state_t: 2833] __dhd_txflowcontrol: Netif Queue has already started
06-23 20:48:18.983 0 0 W [0:dhd_rpm_state_t: 2833] __dhd_txflowcontrol: Netif Queue has already started
06-23 20:48:18.983 0 0 W [0:dhd_rpm_state_t: 2833] dhd_runtimepm_state: runtime resume ended