[Sony Xperia XZ1 Compact ROMs, Kernels, Recoveries,] munjeni:
[MENTION=4418980]j4nn[/MENTION] are you able to extract section0 from xbl.mbn? Seems section0.guid is obfuscated? Or I misunderstand tool. Only which I can extract from xbl is section0.ui which contain text uefiplat.cfg and another file section1.raw with context:

[Config]
Version = 3
MaxMemoryRegions = 72

[MemoryMap]
# EFI_RESOURCE_ EFI_RESOURCE_ATTRIBUTE_ EFI_MEMORY_TYPE ARM_REGION_ATTRIBUTE_
#MemBase, MemSize, MemLabel(32 Char.), BuildHob, ResourceType, ResourceAttribute, MemoryType, CacheAttributes
#--------------------- DDR -----
0x80000000, 0x05800000, "Kernel", AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN
0x86000000, 0x00200000, "SMEM", AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN
0x94000000, 0x09400000, "DXE Heap", AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN
0x9D400000, 0x02400000, "Display Reserved", AddMem, MEM_RES, SYS_MEM_CAP, LdData, WRITE_BACK_XN
0x9F800000, 0x00200000, "FV Region", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN
0x9FA00000, 0x00200000, "ABOOT FV", AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN
0x9FC00000, 0x00300000, "UEFI FD", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK
0x9FF00000, 0x0008C000, "SEC Heap", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN
0x9FF8C000, 0x00001000, "CPU Vectors", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK
0x9FF8D000, 0x00003000, "MMU PageTables", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN
0x9FF90000, 0x00040000, "UEFI Stack", AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN
0x9FFD0000, 0x00027000, "DBI Dump", AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN
0x9FFF7000, 0x00008000, "Log Buffer", AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN
0x9FFFF000, 0x00001000, "Info Blk", AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN

[RegisterMap]
#--------------------- Other -----
0x14680000, 0x00040000, "IMEM Base", NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE
0x146BF000, 0x00001000, "IMEM Cookie Base", AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE
0x16000000, 0x01000000, "QDSS_STM", AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE
#--------------------- Register --
0x00070000, 0x00010000, "BOOT_CONFIG", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x00100000, 0x000B0000, "GCC CLK CTL", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x00620000, 0x00020000, "UFS_RUMI", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x00778000, 0x00008000, "RPM MSG RAM", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x00780000, 0x00007000, "SECURITY CONTROL", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x00790000, 0x00010000, "PRNG_CFG_PRNG", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010A3000, 0x00001000, "MPM2_SLP_CNTR", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010AA000, 0x00001000, "MPM2_TSENS0", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010AB000, 0x00001000, "MPM2_TSENS0_TM", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010AC000, 0x00001000, "MPM2_PSHOLD", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010AD000, 0x00001000, "MPM2_TSENS1", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x010AE000, 0x00001000, "MPM2_TSENS1_TM", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x01C00000, 0x00007000, "PCIE WRAPPER AHB", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x01DA0000, 0x00020000, "UFS UFS REGS", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x01DC0000, 0x00040000, "CRYPTO0 CRYPTO", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x01FC0000, 0x00026000, "TCSR_TCSR_REGS", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x03400000, 0x00C00000, "TLMM CSR", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x05026000, 0x00002000, "GPMU_DRAM", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x0502A000, 0x00002000, "GPMU_BLOCK0", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x05030000, 0x00002000, "GPU_ISENSE", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x05065000, 0x00009000, "GPUCC", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x06000000, 0x00100000, "QDSS_QDSS", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x06400000, 0x00200000, "HMSS_QLL", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x08000000, 0x02800000, "PMIC ARB SPMI", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x0A800000, 0x0011B000, "USB30_PRIM", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x0A920000, 0x00010000, "USB_RUMI", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x0C000000, 0x00200000, "PERIPH_SS", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x0C800000, 0x00800000, "MMSS", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x17800000, 0x00100000, "APCS_CC", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x17900000, 0x00030000, "QTIMER", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x17A00000, 0x00010000, "APCS_GIC500_GICD", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x17B00000, 0x00100000, "APCS_GIC500_GICR", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE
0x1B000000, 0x01000000, "PCIE WRAPPER AXI", AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE

[ConfigParameters]
# Update count if more than default 30 entries #
ConfigParameterCount = 52

## UEFI CORE ##
PlatConfigFileName = "uefiplatLA.cfg"
OsTypeString = "LA"
NumCpusFuseAddr = 0x5C04C

# Force booting to shell whilst in pre-silicon phase
EnableShell = 0x1

## Shared IMEM (Cookies, Offsets)
SharedIMEMBaseAddr = 0x146BF000
DloadCookieAddr = 0x01FD3000
DloadCookieValue = 0x10
MemoryCaptureModeOffset = 0x1C
AbnormalResetOccurredOffset = 0x24
DBIDumpDDRBase = 0x9FFD0000

## MPPark ##
## NumCpus - max number of cores
## NumActiveCores - number of cores used
NumCpus = 4
NumActiveCores = 8

## ULogFile ##
SpecialLogPartition = "LOGFS:\"
MaxLogFileSize = 0x400000

## USB ##
USBHS1_Config = 0x0
UsbFnIoRevNum = 0x00010001

## Buttons / KeyPad ##
PwrBtnShutdownFlag = 0x0

## SDCC ##
Sdc1GpioConfigOn = 0x1E92
Sdc2GpioConfigOn = 0x1E92
Sdc1GpioConfigOff = 0xA00
Sdc2GpioConfigOff = 0xA00

## SDHC Mode 0:Legacy Mode, Non-zero: SDHC Mode ##
EnableSDHCSwitch = 0x1

## Reset ##
PSHoldOffset = 0xC000
PSHoldSHFT = 0x0

## Reset Reason - SharedIMEMBaseAddr + 0x28 ##
GCCResetValueAddress = 0x146BF028

## PCIE ##
#PCIeRPNumber BIT 7:0 -> number of RPs to be enabled
#PCIeRPNumber BIT 15:8 -> BIT mask to identify which RPs are enabled
#Eg. value: 0x0502 -> Total two numbers of RPs, RP0 and RP2 are enabled
#Total RPs supported 8 numbers and bits allocated are 16 bits

#PCIeRPNumber=0x0101

## Security flag ##
SecurityFlag = 0xC4
# SecBootEnableFlag = 0x1 i.e. 0b00000001
# TreeTpmEnableFlag = 0x2 i.e. 0b00000010
# CommonMbnLoadFlag = 0x4 i.e. 0b00000100
# DxHdcp2LoadFlag = 0x8 i.e. 0b00001000
# VariableServicesFlag = 0x10 i.e. 0b00010000
# WinsecappFlag = 0x20 i.e. 0b00100000
# LoadSecAppFlag = 0x40 i.e. 0b01000000
# LoadKeymasterFlag = 0x80 i.e. 0b10000000
# EnableQseeLogsFlag = 0x100 i.e. 0b 00000001 00000000

## TZ ApPs Notification parameters
TzAppsRegnAddr = 0x86D00000
TzAppsRegnSize = 0x02200000

## Default app to boot in platform BDS init
DefaultChargerApp = "QcomChargerApp"
DefaultBDSBootApp = "LinuxLoader"

## LogFs partition ##
## NOTE: Ensure logs 8MB bin is flashed from /Tools/binaries ##
EnableLogFsSyncInRetail = 0x0

## NOTE: Enabling splash partition is a security risk ##
EnableSecurityHoleForSplashPartition = 0x0

## NOTE: Do not remove last newline, required by parser ##

Am I missing something? This is from G8441_Customized CE1_1310-7123_47.2.A.10.107_R1C