[Galaxy Note 4 Android Development (Exynos)] Bajanman:
Wow this turned into a under volt thread. Something I have never done on any of my devices since I always have a extended battery really no need to UV for me. Plus I like speed and not lag. Here's a bit of info for those wanting to Uv your note 4, just know that not all devices like to be Uv...

Here's a lil info about AVS a for all.

The use of DVFS allows for power savings in a situation in which high performance is only required for a short period of time.

Example: A complex algorithm or intensive graphic-processing tasks may require a processor in order to temporarily use a higher than nominal operating frequency. To support the faster switching, a higher supply voltage may be required. To support this on-demand, or dynamic, requirement, the power-supply must be programmable or adjustable to implement DVFS.

DOMAIN CONDHON OPP_NOM OPP_OD OPP_HIGH MIN NOM MAX MIN NOM MAX MIN NOM MAXDC MAX VDD_M PU Boot (before AVS is 1.023 V 1.06 V 1.11 V NA NA NA NA NA NA NA enabled) mr AVS is AVS AVS 1.11 V AVS AVS AVS AVS AVS AVS AVS voltage enabled voltage-voltage voltage-w» ltage voltage + wnage-voltage voltage ++5% 3.5% 3.5% 5% 3.5% 2%

· The process variance and resulting process variation of the individual silicon.

Example: Strong silicon is associated with high dynamic performance. However, this dynamic

performance comes with an increase in power consumption. The more dynamic performance that a die has, the higher the leakage power. With ever-shrinking process nodes, the process variance is gaining importance.

· Process node or geometry

Example: Smaller geometries lead to lower off-resistances and higher leakage currents. Some

process nodes have higher leakage, some have high active power numbers. However, operating at the lowest voltage possible will always help reduce both leakage & active power.

· Gate munt

Example: The more complex and the more cores a processor supports, the higher the gate count and

number of leakage paths.

· Required margins. Aging, temperature, load transients, and other effects affect the minimum required voltage. Depending on the implementation, the voltage margin should account for all possible effects or

should be able to adjust for the effects dynamically(depending on the AVS class).

Example: For AVS Class-O, a margin is built into the minimum supply voltage level programmed in the device to account for these additional margins(SUCH as aging, temperature, and load transients).

One of the benefits of higher AVS-classes is the ability to adjust the voltages based on temperature changes and aging. This adjustment would be accomplished by a self-check in silicon, which translates to the device adjusting its own external voltage by using the I C or SPI bus.

Implementing AVS and DVFS

To support voltage scaling, both the processor and the power supply must be designed to support it. The processor must recognize unique voltage demands per domain (VDD_MPU, VDD_GPU, VDD_CORE, VDD_DSP, or others) per operating performance point (OPP_NOM, OPP_OD, or others). In case of different OPPs, each OPP will have a minimum voltage stored in a register. An 12C interface is used for communication between the processor and the external power supply. An SPI or GPIO can be used for this communication as well. For Class 2 and Class 3 scaling, the required IP and hardware blocks for the

self-calibration must implemented in the processor.

The general approach to implementing AVS or DVFS is to evaluate the performance characteristics of the processor on the automated test equipment (ATE) during standard production testing and to permanently

store the voltage demand on the individual IC. The storage could be an EPROM, eFuse, or similar.

The power-supply must also be adjustable in order to change the output voltage on demand. The easiest implementation is with a PMIC that supports this change in output voltage. Typically it can be implemented by digital voltage control through the i c or SPI.

Conclusion

The adaptive voltage scaling (AVS) method is a powerful technique that supports the optimization of power-consumption for modern processors. To meet strict system requirements for the power dissipation ofthe processor, AVS may be required. In order to implement DVFS or AVS, both the processor and the power supply must be carefully designed for communication and regulation in order to account for the

device operating point or process variation. Companion PMICs such as the TPS659038-01 and

TPS659039-Q1 device are highly integrated devices that enable and simplify this function. Such specific companion PMICs are listed in the processor-specific data sheet as the supported option for PCB design.