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Attached Hex Workshop Bookmark with RES and I2c register offsets bookmark see screenshot above

Here Are The Readout Modes Supported by the IMX377

typedef enum _IMX377_READOUT_MODE_e_ {
IMX377_TYPE_2_3_MODE_0A = 0, /* 12bit A/D, 12bit OUT, 4-lane, native (4096x3000) */
IMX377_TYPE_2_3_MODE_0, /* 12bit A/D, 12bit OUT, 4-lane, native */
IMX377_TYPE_2_3_MODE_1, /* 10bit A/D, 10bit OUT, 4-lane, native */
IMX377_TYPE_2_3_MODE_1A, /* 10bit A/D, 10bit OUT, 4-lane, native */
IMX377_TYPE_2_3_MODE_2, /* 10bit A/D, 12bit OUT, 4-lane, H: 2binning V: 2binning */
IMX377_TYPE_2_3_MODE_3, /* 10bit A/D, 12bit OUT, 4-lane, H: 3binning V: 3binning */
IMX377_TYPE_2_3_MODE_4, /* 10bit A/D, 12bit OUT, 4-lane, H: 3binning V: 1/3subsampling */
IMX377_TYPE_2_5_MODE_0, /* 12bit A/D, 12bit OUT, 4-lane, native */
IMX377_TYPE_2_5_MODE_1, /* 10bit A/D, 10bit OUT, 4-lane, native */
IMX377_TYPE_2_5_MODE_1A, /* 10bit A/D, 10bit OUT, 4-lane, native */
IMX377_TYPE_2_5_MODE_2, /* 10bit A/D, 12bit OUT, 4-lane, H: 2binning V: 2binning */
IMX377_TYPE_2_5_MODE_4, /* 10bit A/D, 12bit OUT, 4-lane, H: 3binning V: 1/3subsampling */
IMX377_CUSTOM_MODE_1, /* 10bit A/D, 10bit OUT, 4-lane, native (cropping, 3360x1890) */

IMX377_NUM_READOUT_MODE,
} IMX377_READOUT_MODE_e;

Registers

IMX377_MODE_REG_s IMX377ModeRegTable[IMX377_NUM_READOUT_MODE_REG] = {
/* [ Type 1/2.3 12.35M ][ Type 1/2.5 9.03M ] */
/* Addr, 0A, 0, 1, 1A, 2, 3, 4, 0, 1, 1A, 2, 4 */
{0x3004, {0x00, 0x00, 0x00, 0x06, 0xa2, 0x45, 0x08, 0x10, 0x19, 0x06, 0xb1, 0x14}}, /* [7:0]: MDSEL1 */
{0x3005, {0x07, 0x07, 0x01, 0x01, 0x25, 0x35, 0x35, 0x07, 0x01, 0x01, 0x25, 0x35}}, /* [7:0]: MDSEL2 */
{0x3006, {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x04, 0x01, 0x01}}, /* [7:0]: MDSEL3 */
{0x3007, {0xa0, 0xa0, 0xa0, 0xa2, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa2, 0xa0, 0xa0}}, /* [7:0]: MDSEL4 */
{0x300d, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: SVR_LSB */
{0x300e, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: SVR_MSB */
{0x301a, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [0]: MDVREV */
{0x3039, {0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00}}, /* [7:0]: HTRIMMING_END_LSB */
{0x303a, {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00}}, /* [4:0]: HTRIMMING_END_MSB */
{0x303e, {0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00}}, /* [7:0]: HTRIMMING_START_LSB */
{0x303f, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [4:0]: HTRIMMING_START_MSB */
{0x3040, {0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00}}, /* [0]: HTRIMMING_EN */
{0x3068, {0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00}}, /* [7:0]: MDSEL7 */
{0x307e, {0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDSEL5_LSB */
{0x307f, {0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00}}, /* [7:0]: MDSEL5_MSB */
{0x3080, {0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS01_LSB */
{0x3081, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS01_MSB */
{0x3082, {0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS02_LSB */
{0x3083, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS02_MSB */
{0x3084, {0x00, 0x00, 0x00, 0xc7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS03_LSB */
{0x3085, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS03_MSB */
{0x3086, {0x00, 0x00, 0x00, 0xca, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS04_LSB */
{0x3087, {0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS04_MSB */
{0x3095, {0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS05_LSB */
{0x3096, {0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS05_MSB */
{0x3097, {0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS06_LSB */
{0x3098, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS06_MSB */
{0x3099, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS07_LSB */
{0x309a, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS07_MSB */
{0x309b, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS08_LSB */
{0x309c, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS08_MSB */
{0x30bc, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS40_LSB */
{0x30bd, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS40_MSB */
{0x30be, {0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS41_LSB */
{0x30bf, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS41_MSB */
{0x30c0, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS42_LSB */
{0x30c1, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS42_MSB */
{0x30c2, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS43_LSB */
{0x30c3, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS43_MSB */
{0x30c4, {0x00, 0x00, 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS44_LSB */
{0x30c5, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS44_MSB */
{0x30c6, {0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS45_LSB */
{0x30c7, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS45_MSB */
{0x30c8, {0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS46_LSB */
{0x30c9, {0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS46_MSB */
{0x30ca, {0x00, 0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS47_LSB */
{0x30cb, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS47_MSB */
{0x30cc, {0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS48 */
{0x30d0, {0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS52_LSB */
{0x30d1, {0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00}}, /* [7:0]: MDPLS52_MSB */
{0x30d5, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [0]: VWINDCUTEN */
{0x30d6, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: VWIDCUT_LSB */
{0x30d7, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [2:0]: VWIDCUT_MSB */
{0x30d8, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [7:0]: VWINPOS_LSB */
{0x30d9, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, /* [3:0]: VWINPOS_MSB */
{0x30da, {0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x05, 0x00, 0x00, 0x01, 0x02, 0x05}}, /* [7:0]: MDREG01 */
{0x30ee, {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}}, /* [7:0]: MDREG02 */
{0x312f, {0xf6, 0xf6, 0xf6, 0xf6, 0xf4, 0xfe, 0xfc, 0x86, 0x86, 0x86, 0x4a, 0xe2}}, /* [7:0]: MDSEL9_LSB */
{0x3130, {0x0b, 0x0b, 0x0b, 0x0b, 0x05, 0x03, 0x03, 0x08, 0x08, 0x08, 0x04, 0x02}}, /* [4:0]: MDSEL9_MSB */
{0x3131, {0xe6, 0xe6, 0xe6, 0xe6, 0xf0, 0xfa, 0xf8, 0x7e, 0x7e, 0x7e, 0x46, 0xde}}, /* [7:0]: MDSEL10_LSB */
{0x3132, {0x0b, 0x0b, 0x0b, 0x0b, 0x05, 0x03, 0x03, 0x08, 0x08, 0x08, 0x04, 0x02}}, /* [4:0]: MDSEL10_MSB */
{0x3a41, {0x10, 0x10, 0x10, 0x10, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x04, 0x04}}, /* [7:0]: MDSEL11 */
};

Register Defs

typedef enum _IMX377_CTRL_REG_e_ {
IMX377_OP_REG = 0x3000,
IMX377_CLPSQRST_REG = 0x3001,
IMX377_MDSEL1_REG = 0x3004,
IMX377_MDSEL2_REG = 0x3005,
IMX377_MDSEL3_REG = 0x3006,
IMX377_MDSEL4_REG = 0x3007,
IMX377_SMD_REG = 0x3008,
IMX377_PGC_LSB_REG = 0x3009,
IMX377_PGC_MSB_REG = 0x300a,
IMX377_SHR_LSB_REG = 0x300b,
IMX377_SHR_MSB_REG = 0x300c,
IMX377_SVR_LSB_REG = 0x300d,
IMX377_SVR_MSB_REG = 0x300e,
IMX377_DGAIN_REG = 0x3011,
IMX377_SYNCDRV_REG = 0x3018,
IMX377_MDVREV_REG = 0x301a,
IMX377_SYS_MODE_REG = 0x303d,
IMX377_XMSTA_REG = 0x30f4,
IMX377_HMAX_LSB_REG = 0x30f5,
IMX377_HMAX_MSB_REG = 0x30f6,
IMX377_VMAX_LSB_REG = 0x30f7,
IMX377_VMAX_MSB_REG = 0x30f8,
IMX377_VMAX_HSB_REG = 0x30f9,
IMX377_STBPL_IF_AD_REG = 0x310b,
IMX377_PLRD1_LSB_REG = 0x3120,
IMX377_PLRD1_MSB_REG = 0x3121,
IMX377_PLRD3_REG = 0x3122,
IMX377_PLRD10_REG = 0x3123,
IMX377_PLRD11_REG = 0x3124,
IMX377_PLRD12_REG = 0x3125,
IMX377_PLRD13_REG = 0x3127,
IMX377_PLRD2_REG = 0x3129,
IMX377_PLRD4_REG = 0x312a,
IMX377_PLRD14_REG = 0x312d,
IMX377_LMRSVRG_REG = 0x3399,
IMX377_MIPIEBD_TAGEN_REG = 0x3a56,
IMX377_MIPI_HALF_EN_REG = 0x3ac4,
} IMX377_CTRL_REG_e;

In Hex/Arm Regs are reversed so 0x3a41 = 413a

Incase anyone wants to play with them