[Samsung Galaxy Nexus] Loufa:
Hello every one,

not sure if this the right place to ask but i really need help.

I am attempting to gather some data on Galaxy Nexus i9250 Android v4.3 CPU ARMv7.I am trying to use ARM Streamline but it provides the following error:

ARM Processor PMU event counters have been detected, however the event counters are reading zeroes. Event counters include those counters listed in the counter configuration options dialog under the core name but exclude the cycle counter (Clock:Cycles) as it is controlled by a dedicated counter. It is possible that the PMU configuration bit DBGEN has not been enabled, and counter values subsequently will always read as zero. To remedy, please update your firmware or Linux kernel to enable DBGEN.

after some search i found similar problem: on freescale

which suggest some modification to the SDER Secure Debug Enable Register, Security Extensions.

i do not know what to so i found a file perf_event in kernel source but not sure where to start.

i found out on infocenter of arm for ARM11 that i should use

// MRC p15, 0, <Rd>, CRn, CRm, opCode_2 ; base

MRC p15, 0, <Rd>, c15, c12, 0 ; Read Performance Monitor Control Register

MCR p15, 0, <Rd>, c15, c12, 0 ; Write Performance Monitor Control Register

this is in perf_event_v6.c kernel folder like this:

static inline unsigned long

armv6_pmcr_read(void)

{

u32 val;

asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));

return val;

}

since i'm using version arm7 so i should modify perf_event_v7.c

and my guessing that i should use c9 instead of c15 because this is the option used there and mentioned in the Cortex Reference manual for EX:

c9 registers

Table 4-10 shows the CP15 system control registers you can access when CRn is c9.

Table 4-10 c9 register summary

Op1 CRm Op2 Name Type Reset Description

0 c12 0 PMCR RW 0x41093000 Performance Monitor Control Register

1 PMCNTENSET RW 0x00000000 Count Enable Set Register

2 PMCNTENCLR RW 0x00000000 Count Enable Clear Register

3 PMOVSR RW - Overflow Flag Status Register

4 PMSWINC WO - Software Increment Register

5 PMSELR RW 0x00000000 Event Counter Selection Register

so it should be :

MRC p15, 0, <Rd>, c9, c12, 0 ; Read Performance Monitor Control Register

MCR p15, 0, <Rd>, c9, c12, 0 ; Write Performance Monitor Control Register

and

MRC p15, 0, <Rd>, c9, c12, 5 ; Read PMSELR Register

MCR p15, 0, <Rd>, c9, c12, 5 ; Write PMSELR Register

and to choose the event:

EXPORT pmn_config

; Sets the event for a programmable counter to record

; void pmn_config(unsigned counter, uint32_t event)

; counter (in r0) = Which counter to program (e.g. 0 for PMN0, 1 for PMN1)

; event (in r1) = The event code (from appropriate TRM or ARM Architecture Reference Manual)

pmn_config PROC

AND r0, r0, #0x1F ; Mask to leave only bits 4:0

MCR p15, 0, r0, c9, c12, 5 ; Write PMSELR Register

ISB ; Synchronize context

MCR p15, 0, r1, c9, c13, 1 ; Write PMXEVTYPER Register

BX lr

ENDP

the steps i should follow are as follow:

The following procedure should be followed:

Disable performance counters

Set what each event counter will count

Set cycle counter tick rate

Reset performance counters

Enable performance counters

Call function to profile

Disable performance counters

Read out performance counters

Check that performance counters did not overflow

i also found this EX:

following this code on google_code DirectPMUCodeGCC

i found on e2e support site that Galaxy Nexus is a secure device by checking the DBGAUTHSTATUS

i should push DBGEN or NIDEN high.

but i still did not know how to do it.

Any help?