[Desire HD Android Development] forzaferrari0:
if helps here are the clock lists with:

Pacha kernel

------------ HTC Clock -------------

pll1_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]768000000

pll2_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]806400000

pll3_clk : [EN]Y, [LOC]Y, [SRC]lpxo_clk , [FREQ]737280000

measure_clk : [EN]N, [LOC]Y, [SRC]NULL , [FREQ]0

ADSP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000000

CODEC_SSBI_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

ECODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]4096000

GP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_PHY_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

ebi_dtv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_2d_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_3d_clk : [EN]Y, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_lcdc_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_mddi_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]153000000

ebi_tv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vcd_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vfe_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_adm_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

HDMI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

JPEG_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

JPEG_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

LPA_CODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MI2S_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_S_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

SDAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

SDAC_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CAMIF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_MDC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

IMEM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

MDP_LCDC_PAD_PCLK_C: [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_LCDC_PCLK_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_VSYNC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24576000

TSIF_REF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]105468

TSIF_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_DAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

EMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

EMDH_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

I2C_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

I2C_2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

MDC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

PMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

PMDH_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]25000000

SDC1_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC2_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC4_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC4_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

UART2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_HS2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

USB_HS3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

QUP_I2C_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

SPI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]9963243

SPI_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

UART1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART2DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]64000000

USB_HS_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_CORE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

CAM_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CSI0_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

CSI0_VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

CSI0_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_DIV2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

adm_clk : [EN]N, [LOC]Y, [SRC]axi_li_apps_clk , [FREQ]0

adm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

rotator_imem_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart2dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

2d oc kernel

------------ HTC Clock -------------

pll1_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]768000000

pll2_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]806400000

pll3_clk : [EN]Y, [LOC]Y, [SRC]lpxo_clk , [FREQ]737280000

measure_clk : [EN]N, [LOC]Y, [SRC]NULL , [FREQ]0

ADSP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000000

CODEC_SSBI_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

ECODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]4096000

GP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_PHY_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

ebi_dtv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_2d_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_3d_clk : [EN]Y, [LOC]Y, [SRC]EBI1_CLK , [FREQ]192000000

ebi_lcdc_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_mddi_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]153000000

ebi_tv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vcd_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vfe_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_adm_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

HDMI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

JPEG_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

JPEG_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

LPA_CODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MI2S_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_S_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

SDAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

SDAC_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CAMIF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_MDC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

IMEM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

MDP_LCDC_PAD_PCLK_C: [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_LCDC_PCLK_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_VSYNC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24576000

TSIF_REF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]105468

TSIF_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_DAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

EMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

EMDH_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

I2C_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

I2C_2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

MDC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

PMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

PMDH_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]25000000

SDC1_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC2_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]143719

SDC3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC4_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC4_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

UART2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_HS2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

USB_HS3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

QUP_I2C_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

SPI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]9963243

SPI_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

UART1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART2DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]64000000

USB_HS_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_CORE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

CAM_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CSI0_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

CSI0_VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

CSI0_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_DIV2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

adm_clk : [EN]Y, [LOC]Y, [SRC]axi_li_apps_clk , [FREQ]0

adm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

rotator_imem_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart2dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

and 3d test kernel

------------ HTC Clock -------------

pll1_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]768000000

pll2_clk : [EN]Y, [LOC]Y, [SRC]tcxo_clk , [FREQ]806400000

pll3_clk : [EN]Y, [LOC]Y, [SRC]lpxo_clk , [FREQ]737280000

measure_clk : [EN]N, [LOC]Y, [SRC]NULL , [FREQ]0

ADSP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000000

CODEC_SSBI_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

EBI1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]200000000

ECODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]4096000

GP_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_PHY_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

ebi_dtv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_2d_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_grp_3d_clk : [EN]Y, [LOC]Y, [SRC]EBI1_CLK , [FREQ]192000000

ebi_lcdc_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_mddi_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]153000000

ebi_tv_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vcd_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_vfe_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

ebi_adm_clk : [EN]N, [LOC]Y, [SRC]EBI1_CLK , [FREQ]0

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_2D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]245760000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_2D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

HDMI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

JPEG_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

JPEG_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

LPA_CODEC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

LPA_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MI2S_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_S_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_RX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_M_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

MI2S_CODEC_TX_S_CLK: [EN]N, [LOC]N, [SRC]NULL , [FREQ]12288000

SDAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

SDAC_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]256000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_CAMIF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_MDC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]36864000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VFE_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

GRP_3D_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

IMEM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

MDP_LCDC_PAD_PCLK_C: [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_LCDC_PCLK_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]24576000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

MDP_VSYNC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24576000

TSIF_REF_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]105468

TSIF_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_DAC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

TV_ENC_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]27000000

EMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

EMDH_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

I2C_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

I2C_2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

MDC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

PMDH_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]92160000

PMDH_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]25000000

SDC1_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC2_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]143719

SDC3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

SDC4_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]50000000

SDC4_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

UART2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]19200000

USB_HS2_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS2_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

USB_HS3_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_CORE_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS3_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

QUP_I2C_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

SPI_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]9963243

SPI_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

UART1_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]19200000

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART1DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]7372800

UART2DM_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]64000000

USB_HS_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_CORE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]60000000

USB_HS_P_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]96000000

CAM_M_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]24000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CAMIF_PAD_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

CSI0_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]0

CSI0_VFE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]36864000

CSI0_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]192000000

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MDP_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_DIV2_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

MFC_P_CLK : [EN]N, [LOC]N, [SRC]NULL , [FREQ]96000000

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

VPE_CLK : [EN]Y, [LOC]N, [SRC]NULL , [FREQ]0

adm_clk : [EN]N, [LOC]Y, [SRC]axi_li_apps_clk , [FREQ]0

adm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

ce_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

axi_rotator_clk : [EN]N, [LOC]Y, [SRC]axi_li_vg_clk , [FREQ]0

rotator_imem_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

rotator_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart1dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0

uart2dm_p_clk : [EN]N, [LOC]Y, [SRC]glbl_root_clk , [FREQ]0