[Galaxy S 4 i9505 Original Android Development] chalid:
These temperatures are

very

nice.

I'd recommend you just go ahead and underclock and undervolt and see what's possible. I did the same and am pretty happy with the battery life and the temperature. Now that is ... wasn't before I tweaked things.

My settings:

CPU:

Max Clock: 1,134 GHz

Min Clock: 384 GHz

Gov: Ondemand

mpdecision: off

Eco Mode: off

Snake Charmer: on

SOC:

C0 WFI: on

Rest off

Voltage:

384: 812500

486: 825000

594: 837500

702: 850000

810: 862500

918: 875000

1026: 900000

1134: 912500

Governor:

Up Threshold: 95

Sampling Rate: 120000

Optimal Frequency: 384000

Sync Frequency: 384000

GPU:

Governor: Ondemand

GPU Clock: 200 MHz

----------

These settings are for best battery life while the phone still runs 100% smooth and stable in everyday usage. I actually had lower voltages for some time, but the phone did reboot once (in 5 days) ... I guess the problem lies with a higher frequency since I can lower voltage at 384 MHz to 775000 without a problem. I will keep testing this from time to time.

Here are the benchmarks:

Epic Citadel HP: 50,7 FPS

Epic Citadel HQ: 47,1 FPS

Epic Citadel UHQ: 23,6 FPS

Quadrant: 9743

AnTuTu: 20315

As you can see with my settings the SGS4 is about the speed of a Snapdragon S4 (LG Optimus G or Sony Xperia Z) and still 50% to 100% faster than the SGS3, with longer battery life and cooler CPU temperatures.

I'm now on 60 hours with 1 hour screen on time, 3G only (HSDPA and HSDPA+ mainly; Gmail, Calendar & Contacts sync) and still have 36 percent left. Another 24 hours will be no problem. One thing to mention though: I turn off 3G overnight. Rest as always. That way the battery only drains 1-2 percent in 6 to 8 hours standby.

Freeze or remove every app you don't need. Samsung stock ROM is bloated like hell. No point in keeping all those apps if you don't use them. Same goes for the features you don't need (air gestures maybe?).

---------- Post added at 11:57 AM ---------- Previous post was at 11:54 AM ----------

Here is the HTC One voltage table (same chip ;)):

static struct acpu_level tbl_[B]PVS0[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1175000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1225000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS1[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1150000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1187500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS2[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1162500 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS3[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS4[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS5[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
{ 0, { 0 } }
};

static struct acpu_level tbl_[B]PVS6[/B]_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
{ 0, { 0 } }
};