[Galaxy S 4 General] Turbotab:
I'm afraid that Samsung have censored, for want of a better word the last_kmsg compared to what we have seen on HTC, LG etc devices with Qualcomm SoCs.

This means that I don't know a method of reading your GS4's PVS, I will update if I find one.

There seems to be a bit of confusion, about the significance of the PVS value. They relate to Process Corners, and in part to threshold voltage, there is a lot more to it than that, but I'll keep it simple.

So far we've seen PVS values of between 0 to 6.

0 seems to indicate a SLOW corner, this means that its leakage current is lower than a 6, but its timings are slower. In theory, this chip should be good for power consumption, but offer less overclocking potential.

So, 6 means a FAST corner, this means that its leakage current is higher than a 0, but its timings are faster. Again, theoretically this chip offers good overclocking potential, at the expense of possibly higher power consumption.

Firstly, don't worry about it, all these chips have to pass Qualcomm's quality assurance, and lastly a higher PVS number is not necessarily the best, it depends on your priorities.

On 8064 (S4 Pro) devices there were 4 classes of SoC, depending on the result the kernel would load a different voltage table.

Slow / Nominal / Fast / Faster

On the HTC One / Snapdragon 600, the PVS is listing numerically, not by name. All S4 Pro that I've seen listed are marked as SPEED BIN 0, whereas all Snapdragon 600s are listed (so far) as SPEED BIN 1.

Thanks to recent HTC One Kernel Source release, I can can confirm that a Snapdragon 600 can have 1 of 7 possible PVS values: A higher PVS value is better.

0 / 1 / 2 / 3 / 4 / 5 / 6

So far, we have only see PVS values of # 2 / 3 / 4 / 5 in shipping devices

PVS 2

static struct acpu_level tbl_PVS2_2000MHz[] __initdata = {

{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },

{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },

{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },

{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },

{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 912500 },

{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },

{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },

{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },

{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },

{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },

{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 },

{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },

{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1112500 },

{ 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1162500 },

{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1212500 },

{ 0, { 0 } }

};

vs

PVS 5

static struct acpu_level tbl_PVS5_2000MHz[] __initdata = {

{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },

{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },

{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },

{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },

{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },

{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },

{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },

{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 937500 },

{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 950000 },

{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 962500 },

{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 987500 },

{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1012500 },

{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1050000 },

{ 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1087500 },

{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1125000 },

{ 0, { 0 } }

};