[Galaxy S 4 General] Shammyh:
I apologize, I didn't realize there was actually a picture of a die floating around (like in the other thread you made). Thought it was a generic promo photo, but it looks like it's actually the die. And based on that, yea, again, you're right, it's pretty obvious the A7 and A15 clusters are completely independent of each other. I must admit, I don't follow ARM's design evolutions very closely, but reading a bit, it's clear.

I'll take your word on it as far as Krait-300 vs Cortex A15 per clock percentage difference. Looking at it on paper, the A15 does seem to have a not-unsubstantial advantage; with a lot more L1 and L2 cache per core than the Krait, and all this stuff: "superscalar, out-of-order, 32-bit machine with extensive branch prediction, virtualization, register renaming, parallel execution units" etc etc... That said, the Krait-300 does supposedly have some improvements to L2 proactive caching, better branch prediction, and a few other "upgrades" over the Krait-200. And it's worth mentioning that the original A15 designs have been discussed for years... so it's not like Qualcomm was in any way unaware of A15 while designing the Krait series.

I'm not sure I agree about the pissing in the ocean though. It looks like yea, the A7's use maybe 15-20% of the power of the A15s (per clock). But hasn't there been much talk, even as far back as 2010 about how power hungry (hence hot) the A15s might be in practice? I can't imagine it's coincidence that many of the rumors regarding the Exynos delays point to power and heat as the culprits. Hey, that's just talk, but you never know. Hence my comment about 8 cores and the die thermal limits.

For me it's a fait-accompli. I have to purchase my phone in a specific time-frame and from a specific American carrier (AT&T). Hence, it's Snapdragon for me (and many millions of others) no matter what. The Exynos is more interesting from a purely technical perspective, but when it comes to heaving lifting, that's what my laptop and desktop are for.

I do really appreciate the lessons about mobile chip design. I'm much more familiar with x86/64 architecture and chip evolution, but until recently haven't paid too much attention to the inner workings of the ARM family. And this prompted me to read some interesting white papers. And yea, this much is clear: heterogeneous core designs (and IC specialization in general) are here to stay. Even in the desktop/laptop form factors.

And since you gave such an informative answer, another question: In the big.LITTLE, since it does seem each A15 and A7 package has it's own distinct cores, with their individual L0/L1, and shared L2 cache (per cluster), how does the SoC handle getting data from one CPU cluster to the other? Aka, when it's determined a specific thread/execution can be transitioned up/down from one cluster to another... Does it have to re-read from main memory? Or does the CCI have some of caching magic to handle that? And also, I assume the CCI handles the mapping of main memory to each cluster, correct? Basically, I'm curious about the latency/performance hit of active switching between cores. Especially, as you said, given the amount of main memory bandwidth available. And again, how mature is the HMP implementations that going to be used in these first-gen smartphone applications?

Also, in a much simpler question, I know Qualcomm touts there Krait as being able to independently change the "core clock" individually per core. Does the current Exynos design allow for that?

In lieu of all that, I'd also accept some good whitepaper links to find the answers myself.

Much obliged, and again, that's for the informative response!