[Galaxy S 4 General] BarryH_GEG:
That's a different conversation than one about performance and efficiency.

Exynos 5210 is most likely an orphan. It's only known future application is the P5210 (AKA: Samsung's version of the N10) and tablets have enormous batteries as 5210's not very efficient. The 5410 is both more powerful and efficient. Now that Samsung's mastered 28nm HKMG that's what their high-end chips will most likely be based on. I could see older chips being used in lower end devices if Octa's production costs are high but I can't see 5210 being used in high-end devices any longer. 5210/5410 are the only Exynos chips capable of supporting FHD so that might affect where they are used.

PowerVR will be at least equal to Adreno 320 and most likely better in some areas; especially onscreen performance. Comparing to Mali 604 isn't really relevant as it's an orphan, With the SGS4 available with Adreno 320 or PowerVR 544 that's a more relevant comparison.

Here's what Anand said about Adreno 320 on the Droid DNA which is also being used with S-600.

"The 3D graphics department is handled by the Adreno 320 GPU. The first test we ran was NenaMark 2, but just like its competitors the HTC DROID DNA managed to hit the 60fps limit of the screen, rendering the results moot. GLBenchmark let us get a better idea of the graphics power of the DROID DNA - the smartphone got the highest score of any smartphone we have tested so far. Given that its screen resolution is much higher than its competitors, though it's can't compete as successfully in on-screen tests. The HTC DROID DNA is a stunning performer and while it doesn't have the graphics power advantage to fully compensate for it vastly higher screen resolution that shouldn't be an issue in most of the real-life scenarios. "​

PowerVR 543 used by Apple is the same GPU as 544 with the addition of DirectX support. Here's what Anand said about PowerVR 543.

"As a recap, Imagination Technologies' PowerVR SGX543 GPU core features four USSE2 pipes. Each pipe has a 4-way vector ALU that can crank out 4 multiply-adds per clock, which works out to be 16 MADs per clock or 32 FLOPS. Imagination lets the customer stick multiple 543 cores together, which scales compute performance linearly. The A5 featured a two core design, running at approximately 200MHz based on our latest news. The A5X in the 3rd generation iPad featured a four core design, running at the same 200MHz clock speed."​

The big difference in Samsung's application is that the 544 is running at nearly three times (533mhz) the clock speed of Apple's implementation. I fully expect it to perform better onscreen than the Adreno 320.

I don't get the "only quad-core" thing. Is S-600 2+2 or 1+1+1+1 because its four cores are physically or s/w controlled to run independently?. Technically, it's two dual core ships used in tandem with one to four active at any given time. How they are placed or stacked on the die doesn't really impact the total core count.

I assume this is what you're referring to.

"In the big.LITTLE task migration use model the OS and applications only ever execute on Cortex-A15 or Cortex-A7 and never both processors at the same time. This use-model is a natural extension to the Dynamic Voltage and Frequency Scaling (DVFS), operating points provided by current mobile platforms with a single application processor to allow the OS to match the performance of the platform to the performance required by the application. However, in a Cortex-A15-Cortex-A7 platform these operating points are applied both to Cortex-A15 and Cortex-A7. When Cortex-A7 is executing the OS can tune the operating points as it would for an existing platform with a single applications processor. Once Cortex-A7 is at its highest operating point if more performance is required a task migration can be invoked that picks up the OS and applications and moves them to Cortex-A15.​

I don't get people slamming big.LITTLE. It's ARM's next-gen architecture that they've been working on for two years. All Qualcomm's chips use ARM designs under license. It's totally likely the chip Qualcomm releases after S-800 will be based on big.LITTLE too.

big.LITTLE Processing

big.LITTLE processing addresses one of today’s industry challenges: how to create a System on Chip (SoC) that provides both high performance as well as extreme power efficiency to extend battery life. big.LITTLE connects the performance of the ARM Cortex-A15 processor with the energy efficiency of the Cortex-A7 processors respectively, enabling the same application software to switch seamlessly between them. By selecting the optimum processor for each task, big.LITTLE can extend battery life by up to 70%.

ARM big.LITTLE processing is designed to deliver the vision of the right processor for the right job. In current big.LITTLE system implementations a ‘big’ ARM Cortex™-A15 processor is paired with a ‘LITTLE’ Cortex™-A7 processor to create a system that can accomplish both high intensity and low intensity tasks in the most energy efficient manner. For example the performance capabilities of the Cortex-A15 processor can be utilized for heavy workloads, while the Cortex-A7 can take over to most efficiently process the majority of smartphone workloads. These include operating system activities, user interface and other always on, always connected tasks.

By coherently connecting the Cortex-A15 and Cortex-A7 processors via the CoreLink™ CCI-400 coherent interconnect the system is flexible enough to support a variety of big.LITTLE use models, which can be tailored to the processing requirements of the tasks.

The central tenet of big.LITTLE is that the processors are architecturally identical. Both Cortex-A15 and Cortex-A7 implement the full ARMv7A architecture including Virtualization and Large Physical Address Extensions. Accordingly all instructions will execute in an architecturally consistent way on both Cortex-A15 and Cortex-A7, albeit with different performances. The implementation defined feature set of Cortex-A15 and Cortex-A7 is also similar. Both processors can be configured to have between one and four cores and both integrate a level-2 cache inside the processing cluster. Additionally, each processor implements a single AMBA® 4 coherent interface that can be connected to a coherent interconnect such as CoreLink CCI-400.​

Your ability to foresee the future is impressive. I get that you and a lot of devs (who I completely admire and respect) have an issue with Samsung's attitude toward the dev community. But few of the negatives you've shared will affect 95% of users of either an Octa or S-600 based SGS4 as they’ll use it out of the box. If Samsung's gotten Octa/PowerVR anywhere close to right it should be more efficient than S-600, equally capable, and provide better on device graphics than S-600/Adreno. Since I can't see the future I'm looking forward to Anandtech and GSMArena's standardized test results. ;)