[One (M7) General] BarryH_GEG:
You kind of have to take a step back. Samsung has nothing to do with big.LITTLE; it's ARM's new generation design that was conceived to improve exactly what you highlighted - performance and battery life. ARM's designs are behind everything Qualcomm builds so if you have faith in Qualcomm that faith sort of extends to ARM too. Granted the "first" release of anything is rarely trouble free but in terms of future direction big.LITTLE is sort of it. If all the lead up is true big.LITTLE is supposed to be 1/3 more effiicient than ARM's previous desgins. I guess we'll know soon enough. ;)

This is from another thread that got closed but you might find it interesting. The PDF attached goes in to even more detail.

Big.LITTLE isn't a "Samsung" thing; it's the next generation of ARM and the logic behind it is explained below. Qualcomm licenses ARM but does their own thing with it. At some point, they too will move to a big.LITTLE model because of the efficiency and load balancing (performance) it delivers which far surpasses the gating used in S-600/800. And based on the performance of A15 in Exynos 5 Dual, if anyone here thinks that the four A15 chips in Octa won't easily match the performance of S-800 they are in denial. Their also in denial if they think that the cluster of four A7 chips won't be more energy efficient than two (of four) A15-esque chips Qualcomm uses in S-600/800 when not under full load. The pipe size, memory bandwidth, and scheduling in big.LITTLE (Octa) is well above that currently used by Qualcomm and will add to the efficiency/performance benefits. ARM, Qualcomm, and Samsung don't sit around their labs thinking about benchmarks. They want to create the most powerful chip that uses the least amount of energy. Big.LITTLE is ARM's next generation architecture designed to do just that. And Octa looks to be the first commercial implementation of it.

To answer your question, yes, big.LITTLE runs in two modes based on OS requests and/or demand. The first is Clustering which runs either the A7 core

or

the A15 core. The second is Full MP where the OS sees all eight cores running in a multi-processor configuration.

big.LITTLE Processing

big.LITTLE processing addresses one of today’s industry challenges: how to create a System on Chip (SoC) that provides both high performance as well as extreme power efficiency to extend battery life. big.LITTLE connects the performance of the ARM Cortex-A15 processor with the energy efficiency of the Cortex-A7 processors respectively, enabling the same application software to switch seamlessly between them. By selecting the optimum processor for each task, big.LITTLE can extend battery life by up to 70%.

ARM big.LITTLE processing is designed to deliver the vision of the right processor for the right job. In current big.LITTLE system implementations a ‘big’ ARM Cortex™-A15 processor is paired with a ‘LITTLE’ Cortex™-A7 processor to create a system that can accomplish both high intensity and low intensity tasks in the most energy efficient manner. For example the performance capabilities of the Cortex-A15 processor can be utilized for heavy workloads, while the Cortex-A7 can take over to most efficiently process the majority of smartphone workloads. These include operating system activities, user interface and other always on, always connected tasks.

By coherently connecting the Cortex-A15 and Cortex-A7 processors via the CoreLink™ CCI-400 coherent interconnect the system is flexible enough to support a variety of big.LITTLE use models, which can be tailored to the processing requirements of the tasks.

The central tenet of big.LITTLE is that the processors are architecturally identical. Both Cortex-A15 and Cortex-A7 implement the full ARMv7A architecture including Virtualization and Large Physical Address Extensions. Accordingly all instructions will execute in an architecturally consistent way on both Cortex-A15 and Cortex-A7, albeit with different performances. The implementation defined feature set of Cortex-A15 and Cortex-A7 is also similar. Both processors can be configured to have between one and four cores and both integrate a level-2 cache inside the processing cluster. Additionally, each processor implements a single AMBA® 4 coherent interface that can be connected to a coherent interconnect such as CoreLink CCI-400

http://www.arm.com/products/processors/technologies/biglittleprocessing.php​