[LG Optimus 2x] spica1234:
Hello,

One of my friend living in next lane has also LG Optimus 2x and he has been using CM7. So I compiled Etana Kernel with SuperSonic ToolChain for him. I did install CM7 to test kernel and it's working fine, So I'd like to share them with you.​

CM-7 ETANA UNOFFICIAL KERNEL​

First Of ALL:

All Credits to VADONKA, I've just used his source and compiled with my toolchain with his permissions, thanks for his kindness. So ALL CREDITS TO A GREAT MAN, VADONKA.

​

Compiled with HP Pro SuperSonic ToolChain.​

HP Pro SuperSonic ToolChain Features: (Based on GCC Linaro Sources)

(-) Tegra specific optimization

(-) Toolchain Target flags has been optimized in same manner as the kernel drivers are written

(-) "Optimizing as the way program is written". I have overy observed all the codes by , as they're written and used same appropriate optimizations

(-) By observing codes 1st thing that comes in mind is Structures & Unions. Used Target Optimizations for it: '-fpack-struct and mstructure-size-boundary=32' for proper alignments of Structures and Unions for faster access

(-) fivopts for variable strength optimizations

(-) fforce-mem with fomit-frame-pointer for faster pointer access

(-) Except tegra codes most of the kernel codes have inlined functions. All functions inlined for faster access of codes. By inlining functions it can be accessed as fast as macro

(-) Code assembly and linking with ArmV7-A architecture's Cortex-A9 cpu's Virtulizations, Integer Division Float and Multi-Processing CPU Extensions

(-) CortexA9 Processor has support for Array Prefetching same like windows does SW based Prefetch. This CPU features during runtime loads longer arrays in advance in CPU memory via AX/BX registers. Which can significantly improve runtime execution and overall snappiness. Target toolchain optimized with array-prefetch optimizations to compile codes with array pre-fetch instructions

(-) By observing Tegra and LG drivers, there are very few short loops, which needs no optimizations, thus graphite loop optimizations disabled.

(-) LTO( Link Time Optimizations) for removal of unused codes during linking stage and re-sections of functions and data for faster access

(-) As armv7-a architecture supports Unaligned Access, instead of disabling, its optimized with 8K access

(-) This is the same toolchain that has been used since 5 months to speedup SuperSonic Test builds for Stock Kernel. No extra blind optimizations used for issue of stability but only as drivers and kernel codes are written "Target specific optimizations" for maxium possible performance

(-) toolchain: Complete set of Used CFLAGS_FOR_TARGET: -O0 -finline-functions -fpack-struct=8 -mstructure-size-boundary=32 -fpreferch-loop-arrays -fivopts -fforce-mem -fomit-frame-pointer CFLAGS_FOR_BUILD: -O0 -march=atom -mtune=atom( as my cpu is atom) Cflags:-O0 -finline-functions

Download:

https://www.dropbox.com/s/18nay2kw6tuks20/CM7-ETaNa_HOC-UnOfficial-2.6.32.y.zip

Defaultly it's 48MB RamHacked you can change it through running 'otf' command followed by 'su' in Terminal emulator.

Once again ALL Credits to Vadonka for his hard consistent work for CM-7​

Etana App can be found in Etana thread. http://xdaforums.com/showthread.php?t=1427646

Credits & Thanks to :

Vadonka and everyone else whom he has credited in his thread.