[Dell Venue] chacona:
Hi all,

I found the way to OC my kernel up. That

/* kernel/arch/arm/mach-msm/acpuclock-8x50.c */
struct clkctl_acpu_speed {
unsigned int use_for_scaling;
unsigned int acpuclk_khz;
int pll;
unsigned int acpuclk_src_sel;
unsigned int acpuclk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
unsigned int axiclk_khz;
unsigned int sc_core_src_sel_mask;
unsigned int sc_l_value;
int vdd;
unsigned long lpj; /* loops_per_jiffy */
};

What we have to do is:

1. Declare a new struct, that is copied from defaults like this:

struct clkctl_acpu_speed acpu_freq_tbl_1305[] = {
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 0, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 0, 921600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 0, 960000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1036800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1113600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1325},
{ 0, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 0, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1350},
{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1375},
/*
{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
{ 1, 1305600, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1300},
* */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};

2. Initialize: do the following changes (the commented out line is the former, the normal is my change)

/*
* static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_998; */
static struct clkctl_acpu_speed *acpu_freq_tbl = acpu_freq_tbl_1305;

3. Change static void __init acpu_freq_tbl_fixup(void)

...
case 0x00:
max_acpu_khz = 1228800;
break;
...

Build it, then you'll done!

My questions: (highly appreciated if anyone can help), about "struct clkctl_acpu_speed" meaning:

Do you know the relationship between the frequency and loops_per_jiffy?

Recommended VDD value (int vdd) with each value of frequency?

unsigned int sc_core_src_sel_mask;: how do we use it effectively?

For testing the idea, I changed the above things, and it works. However, it's better if we can set appropriate values for those fields. Please discuss, your contribution will utilize all the capabilities of this Venue phone!;)

Change list: http://www.mediafire.com/?zc3sg4i912vk681