[Galaxy Note GT-N7000 Android Development] g.lewarne:
THE CleaNote MATH CHALLENGE

Im not good at math like this but I bet some of you so I have a challenge.

Thanks to OrionBG for finding the Exynos development manual, the information is inside it to help me unlock native overclocking on the kernels.

Please, if you up for the challenge, here we go

1) Download this https://www.dropbox.com/s/ew198pkoadscbrr/SEC_Exynos4210_pulbic_manual_Ver.0.00.01.pdf

2) Go to page 364, and it states the equation to calculate the output frequency

FOUT = MDIV x FIN etc etc etc and it has a description below it on how to calculate the specific values.

3) Referring to the table 5.2.2.1 "reccommended FOUT values" on page 266 for guidance

can anyone solve the equation to give me the correct MDIV, PDIV and SDIV values for a fequency (FOUT) of 1600mhz?

AND A CHALLENGE FOR C CODERS

Also, how to correctly insert the corresponding values as calculated above into this section of code

#define CPUFREQ_LEVEL_END	L6

static int max_support_idx;
static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

struct cpufreq_clkdiv {
unsigned int	index;
unsigned int	clkdiv;
};

static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END];

static struct cpufreq_frequency_table exynos4210_freq_table[] = {
{L0, 1400*1000},
{L1, 1200*1000},
{L2, 1000*1000},
{L3, 800*1000},
{L4, 500*1000},
{L5, 200*1000},
{0, CPUFREQ_TABLE_END},
};

static struct cpufreq_clkdiv exynos4210_clkdiv_table[] = {
{L0, 0},
{L1, 0},
{L2, 0},
{L3, 0},
{L4, 0},
{L5, 0},
};

static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
/*
* Clock divider value for following
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
*	DIVATB, DIVPCLK_DBG, DIVAPLL }
*/
/* ARM L0: 1400MHz */
{ 0, 3, 7, 3, 4, 1, 7 },

/* ARM L1: 1200MHz */
{ 0, 3, 7, 3, 4, 1, 7 },

/* ARM L2: 1000MHz */
{ 0, 3, 7, 3, 4, 1, 7 },

/* ARM L3: 800MHz */
{ 0, 3, 7, 3, 3, 1, 7 },

/* ARM L4: 500MHz */
{ 0, 3, 7, 3, 3, 1, 7 },

/* ARM L5: 200MHz */
{ 0, 1, 3, 1, 3, 1, 0 },
};

static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
/* Clock divider value for following
* { DIVCOPY, DIVHPM }
*/
/* ARM L0: 1400MHz */
{ 5, 0 },

/* ARM L1: 1200MHz */
{ 5, 0 },

/* ARM L2: 1000MHz */
{ 4, 0 },

/* ARM L3: 800MHz */
{ 3, 0 },

/* ARM L4: 500MHz */
{ 3, 0 },

/* ARM L5: 200MHz */
{ 3, 0 },
};

static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1400MHz */
((350<<16)|(6<<8)|(0x1)),

/* APLL FOUT L1: 1200MHz */
((150<<16)|(3<<8)|(0x1)),

/* APLL FOUT L2: 1000MHz */
((250<<16)|(6<<8)|(0x1)),

/* APLL FOUT L3: 800MHz */
((200<<16)|(6<<8)|(0x1)),

/* APLL FOUT L4: 500MHz */
((250<<16)|(6<<8)|(0x2)),

/* APLL FOUT L5: 200MHz */
((200<<16)|(6<<8)|(0x3)),
};

/*
* ASV group voltage table
*/

static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
/*
*	SS, A1, A2, B1, B2, C1, C2, D
* @Dummy:
* @1200 :
* @1000 :
* @800	:	ASV_VOLTAGE_TABLE
* @500 :
* @200 :
*/
{ 0, 0, 0, 0, 0, 0, 0, 0 },
{ 1350000, 1350000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },
{ 1300000, 1250000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },
{ 1200000, 1150000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },
{ 1100000, 1050000, 1000000, 975000, 975000, 950000, 925000, 925000 },
{ 1050000, 1000000, 975000, 950000, 950000, 925000, 925000, 925000 },

};

static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
/*
*	S, A, B, C, D
* @1400 :
* @1200 :
* @1000 :
* @800	:	ASV_VOLTAGE_TABLE
* @500	:
* @200	:
*/
{ 1350000, 1350000, 1300000, 1250000, 1225000 },
{ 1325000, 1275000, 1225000, 1175000, 1150000 },
{ 1225000, 1175000, 1125000, 1075000, 1050000 },
{ 1150000, 1100000, 1050000, 1000000, 975000 },
{ 1050000, 1000000, 950000, 950000, 950000 },
{ 1025000, 975000, 950000, 950000, 950000 },

};