[Galaxy S III Original Android Development] AndreiLux:
Knowledge base

I'm going over time to update this post with some informations. It may be unsorted, unfinished or un-editorialized for the time being.

2) Hardware

The Galaxy Note 2 will be coming out with a new 4412 versioned Rev 2.0, where as the one currently in the S3 is versioned Rev 1.1. The new chip will be launched at 1.6GHz default clock. What is interesting is that they have increased the base clock from 800MHz to 880MHz, most of the SoC internals feed off this clock, meaning that we're going to have 10% clock boost in the internal bus and memory speeds.

Now as a side note: One thing that I haven't understood from the press releases back in May, is that there were this "internal 128bit bus" mentioned, with some idiotic websites taking that tidbit and claiming the chip was a 128bit architecture. Whatever. Anyway, the reason for this is that the way the Samsung SoCs internally function: they are separated in a "left bus" and a "right bus". The left bus is connected to the memory controllers and is also just called the MIF/Memory Interface. The right bus is called the "internal bus" and is connected to the ARM cores and everything else. The biggest difference here between the 4412 and the previous Samsung iterations was that both these were running at the same clock. In the 4412 the internal bus is running at half the memory interface bus, this corresponds to the increase to 128bit in the internal bus.

Now I got curious due to all this talk about the A6 and this tidbit:

Both the A6 and 4412 use the same memory, only difference being what seems to be a revision serial character. I was talking a few months ago how the 4412 showed a good 30% bandwidth improvement over the 4210, and credited this to it running 1066mbps memory instead of 800mbps; but in reality that is not the case.

I went over the source code of the busfrequency driver in the S3, and found that actually there is an entry for the internal frequency to run at 266MHz (128bit), but that entry is disabled in the driver; because the memory interfaces don't exceed 400MHz. The bus speed is defined in (MIF/INT) pairs and top speed available is 400200 (400MHz memory, 200 internal). Well this is interesting we can overclock our device's memory then if there's headroom! Well that idea quickly faded as I found that the C2C (Chip-to-chip) interface to the memory isn't capable of being clocked to 533MHz because simply the C2C clock divider register simply doesn't allow a divider value needed for that frequency, only being able to run 400MHz(and lower) and 800MHz. Basically we can't use the fast memory because it seems the clock dividers don't allow it. Anyway, coincidentally the i9305 sources were released two days ago and it included all the Note 2 sources and so on, so what Samsung did was simply increase the MPLL base clock from 800 to 880MHz, actually increasing the frequency of a load of things like the camera interface and who knows what at the same time.

What this also means is that Samsung increased effective bandwidth by 30% without increasing the memory speed. This indicates much improved memory controllers, and also why it easily beats the Tegra 3 and others in memory benchmarks.

Another new addition to the REV 2.0 chip is that we'll be running 533MHz for the Mali clock by default. We were already experimenting with this on the S3 and pretty much made the GPU run up to 700MHz, of course, it gets quite warm and battery hungry, but it's neat nonetheless.

3) Reserved memory spaces

There is the current reserved memory space breakdown, with red as Perseus changes over stock:

#Secure spaces on fixed memory addresses

Front-camera firmware & heap: fimc0: fmic1 =

0x65800000 - 0x66700000 => 15360K (0xF00000) => 14336K

Multi function codec B memory space: mfc-normal =

0x64000000 - 0x64400000 => 4096K

ION device memory allocator reserved space: ion =

0x5F200000 - 0x63800000 => 71680K (0x4600000) => 48128K

Multi function codec device reserved space: device_mfc =

0x5C800000 - 0x5CA80000 => 2560K (0x280000)

Multi function codec A memory space (Virtually contiguous to MFC, practically has a physical memory hole): mfc-secure =

0x5C100000 - 0x5C800000 => 7168K (0x700000)

0x5F000000 - 0x5F200000 => 2048K (0x200000)

Bootloader: sectbl =

0x5C000000 - 0x5C100000 => 1024K (0x100000)

# non secure

Camera imaging subsystem: fimc_is => 12080K (0xBCC000) => 10240K

Display interface and frame buffer: fimd => 8192K (0x800000)

Main-camera firmware & heap: fimc0 => 62464K (0x3D00000)

Audio buffer: srp => 1024K (0x100000)