[HTC One X] blubbers:
from the Tegra 3 Technical Reference Manual

15.10.1 Boot
The Tegra 3 has a two-stage boot:
\uf0a7 The BootROM is responsible for getting the chip out of reset and to the point where driver-level software can take
over.
\uf0a7 The BootLoader or the OS-recovery code is the portion of the driver responsible for completing the boot process to
the general-purpose OS.
The BootROM is an actual ROM built into the chip, and the BootLoader and OS recovery section is externally loaded code.
The BootLoader is only used for ColdBoot; WarmBoot utilizes operating-system recovery code.
Tegra 3 can \u201cboot\u201d in two ways: \u201cWarmBoot\u201d or \u201cColdBoot\u201d. ColdBoot is defined as booting from a fully powered-off or fullyreset
state. WarmBoot is defined as recovery from the lowest-power state (LP0), where the external DRAM has been held in
self-refresh mode while Tegra 3 core was powered off. WarmBoot use case occurs much more often; it is the use case hit
whenever a SmartPhone wakes from Standby to answer a call.
15.10.1.1 ColdBoot
Before Memory Subsystem boot can begin, the BootROM must read the Boot Configuration Tables (BCTs) from flash memory
(slow storage) into on-chip RAM. These tables include the configuration data for up to 4 initial DRAM configurations supported.
The BootROM then reads the strap signals assigned to the SDRAM and begins to bring up the memory subsystem.
The ColdBoot BootROM sequence:
1. Configure PLL used by MC/EMC based on BCT values
2. Wait for PLLs to lock
Tegra 3 Technical Reference Manual
Memory Controller
TEGRA 3 | TRM | DP-05644-001_v01p | SUBJECT TO CHANGE WITHOUT NOTICE| www.nvidia.com 445
3. Program necessary always-on static pad configurations in PMC
4. Configure memory clocks based on BCT values
5. Enable MC/EMC clocks
6. Release memory subsystem resets
7. Program other necessary pad/pad-macro configuration
8. Program initial configuration for MC/EMC based on BCT values
9. Perform the DRAM initialization sequence. This sequence is specific to the DRAM protocol used and varies
depending on the requirements of a particular device. For example, a DDR3 sequence goes as follows:
a. Apply power to the device
b. Wait until voltage is stable
c. Assert DRAM reset
d. Wait 200\u03bcs
e. De-assert DRAM reset
f. Apply stable clocks
g. Wait 500\u03bcs
h. Assert and hold CKE high
i. Precharge all banks
j. Send 2 Auto refresh commands
k. Write to Mode register 0, 1, 2, 3
l. Issue ZQ Calibration command
m. Wait for ZQ calibration and DRAM DLL lock time to complete
10. Enable power saving features such as clock stop, active power down, dynamic-self-refresh
11. Start periodical sequences such as auto refresh, ZQ calibration, auto-calibration
12. Release the memory-initialization hardware lock3
After this, the external DRAM and Memory Subsystem are ready for use.
15.10.1.2 WarmBoot
The WarmBoot sequence is very similar to the ColdBoot sequence, and many of the same steps are performed. One obvious
difference is that instead of powering-on the DRAM, we are waking it out of SelfRefresh. Another difference is the
configuration data for BootROM portion of MC/EMC initialization is stored in the Power Management Controller (PMC) Scratch
Registers.
The PMC Scratch registers are in Always-On partition, and are powered during LP0. The power and area limitations of this
implementation restricts the number of PMC Scratch registers available; there are a smaller number of PMC Scratch Registers
than the number of bits needed to fully configure MC and EMC. The Scratch Registers are only used to store the minimum
required configuration to get to working DRAM. The BootROM may not be able to WarmBoot to full POR speed using only the
Scratch Register data; if this limitation is confirmed, the BootLoader may be required to mimic DVFS software and reprogram
the MC/EMC to full-speed operation using data stored in DRAM. It is up to the LP0 Entry software code to ensure the proper
configuration gets written to the Scratch Registers.
The WarmBoot code provided by the MSS includes algorithms for deriving the approximate MC arbiter performance
parameters from the EMC timing parameters. The EMC has provided generation code for the packing/unpacking calls for the
scratch registers to ease the software maintenance burden.
3 AHB_ARBITRATION_XBAR_CTRL.MEM_INIT_DONE
Tegra 3 Technical Reference Manual
Memory Controller
TEGRA 3 | TRM | DP-05644-001_v01p | SUBJECT TO CHANGE WITHOUT NOTICE| www.nvidia.com 446
The WarmBoot BootROM sequence:
1. Configure memory PLLs and memory clocks based on Scratch values
2. Wait for PLLs to lock
3. Configure memory clocks based on scratch values
4. Enable MC/EMC clocks
5. Release memory subsystem resets. Program any necessary static pad configuration that was powered-off in LP0
6. Program initial configuration for MC/EMC based on Scratch values
7. Release the DRAM from software-controlled Self Refresh. This sequence is specific to the DRAM protocol used and
may further vary depending on the requirements of a particular device. For example, a DDR3 sequence goes as
follows:
a. Apply stable clocks
b. Assert and hold CKE high
c. Issue ZQ Calibration command
d. Wait for ZQ calibration and DRAM DLL lock time to complete
e. Write to Mode registers if different from LP0 entry values
f. Issue refreshes to ensure tREFI is satisfied
8. Enable power saving features such as clock stop, active power down, dynamic-self-refresh
9. Start periodical sequences such as auto refresh, ZQ calibration, auto-calibration
10. Release the memory-initialization hardware lock
After the BootROM sequence is complete, the operating system restore code may access DRAM and restore a different or
higher-speed operation. The operating system may also restore translation or client configuration settings before allowing any
user code to execute.