[Galaxy S II Q&A, Help & Troubleshooting] E:V:A:
Exynos 4210:	I/O	(Exynos Manual)

Next I will just post a few excerpts from the "public" Exynos User manual, that are directly related to the more interesting part of UART/GPIO I/O behavior.

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Modem Interface
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- Asynchronous direct/ indirect 16-bit SRAM-style interface
- On-chip 16 KB dual-ported SRAM (DPSRAM) buffer for direct interface
? (Flex)OneNAND
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4.1 GPIO Control
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Exynos4210 includes 252 multifunctional input/output port pins and 156
memory port pins. There are 37 general port groups and 2 memory port
groups as listed below:

GPA0,GPA1: 14 in/out ports - 3xUART with flow control, UART without flow control, and/ or 2xI2C
GPB: 8 in/out ports - 2xSPI and/or I2C and/ or IEM
GPC0,GPC1: 10 in/out ports - 2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, and/ or SPI
GPD0,GPD1: 8 in/out ports - PWM, I2C, and/or LCD I/F, I2C
GPE0,GPE1,GPE2,GPE3,GPE4: 35 in/out ports - Modem I/F, and/or CAM I/F, and/or TS I/F, and/ or LCD I/F, and/ or Trace I/F
GPF0, GPF1,GPF2,GPF3: 30 in/out ports - LCD I/F
GPJ0, GPJ1: 13 in/out ports - CAM I/F
GPK0, GPK1,GPK2,GPK3: 28 in/out ports - 4xMMC(4-bit MMC), and/ or 2xMMC(8-bit MMC)
GPL0, GPL1: 11 in/out ports - GPS I/F
GPL2: 8 in/out ports - GPS debugging I/F or Key pad I/F
GPX0, GPX1, GPX2, GPX3: 32 in/out ports - External wake-up, and/ or Key pad I/F

NOTE: These are in ALIVE region.

GPZ: 7 in/out ports - Low Power I2S and/or PCM
GPY0, GPY1, GPY2: 16 in/ out ports - Control signals of EBI (SROM, NF, OneNAND)
GPY3,GPY4,GPY5,GPY6: 32 in/ out memory ports - EBI (For more information about EBI configuration, refer to Chapter 5, and 6)
MP1_0 – MP1_9: 78 DRAM1 ports

NOTE: GPIO registers does not control these ports.

MP2_0 – MP2_9: 78 DRAM2 ports

NOTE: GPIO registers does not control these ports.

ETC0,ETC1,ETC6: 18 in/out ETC ports - JTAG, SLIMBUS, RESET, CLOCK
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NFCON (NAND Flash Controller)
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Owing to the recent increase in the prices of NOR flash memory and
the moderately priced DRAM and NAND flash, customers prefer to
execute boot code on NAND flash and execute the main code on DRAM.
The boot code in Exynos4210 can be executed on external NAND flash.
It will copy NAND flash data to DRAM. To validate the NAND flash
data, Exynos4210 comprises of hardware Error Correction Code (ECC).
After the NAND flash content is copied to DRAM, main program will
be executed on DRAM.

The key features of NAND flash controller include:
- Auto boot: The boot code is transferred to internal SRAM during
reset. After the transfer, the boot code will be executed on
the SRAM.
- NAND flash memory interface: Supports 512 Bytes, 2/4/8 KB pages.
- Software mode: You can directly access NAND flash memory, for
example, this feature can be used in read/erase/program NAND
flash memory.

NFCON provides a lock scheme to protect data stored in external
NAND Flash memories from malicious program. For this scheme, the
NFSBLK and NFEBLK registers are used to provide access control
methods; only the memory area between NFSBLK and NFEBLK is
erasable and programmable, but the read access is available
to whole memory area.

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13.1 UART
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The Universal Asynchronous Receiver and Transmitter (UART) in Exynos4210
provide four independent channels with asynchronous and serial input/output
ports for general purpose (ch0~3), and one dedicated channel for
communication with GPS (ch4). All the ports operate in an interrupt-based
or a DMA-based mode. The UART generates an interrupt or a DMA request
to transfer data to and from the CPU and the UART. The UART supports
bit rates up to 3Mbps. Each UART channel contains two FIFOs to receive
and transmit data: 256 bytes in ch0, 64 bytes in ch1 and ch4, and
16 bytes in ch2 and ch3.

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13.3.2 Interface Port Description
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Signal I/O Description Pad Type
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UART_0_RXD Input Receives Data for UART0 XuRXD_0 muxed
UART_0_TXD Output Transmits Data for UART0 XuTXD_0 muxed
UART_0_CTSn Input Clears to Send(active low) for UART0 XuCTSn_0 muxed
UART_0_RTSn Output Requests to Send(active low) for UART0 XuRTSn_0 muxed

UART_1_RXD Input Receives Data for UART1 XuRXD_1 muxed
UART_1_TXD Output Transmits Data for UART1 XuTXD_1 muxed
UART_1_CTSn Input Clears to Send(active low) for UART1 XuCTSn_1 muxed
UART_1_RTSn Output Requests to Send(active low) for UART1 XuRTSn_1 muxed

UART_2_RXD Input Receives Data for UART2 XuRXD_2 muxed
UART_2_TXD Output Transmits Data for UART2 XuTXD_2 muxed
UART_2_CTSn Input Clears to Send(active low) for UART2 XuCTSn_2 muxed
UART_2_RTSn Output Requests to Send(active low) for UART2 XuRTSn_2 muxed

UART_3_RXD Input Receives Data for UART3 XuRXD_3 muxed
UART_3_TXD Output Transmits Data for UART3 XuTXD_3 muxed
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NOTE:

1. Type field indicates whether pads are dedicated to the signal or pads
are connected to the multiplexed signals. UART external pads are shared
with IrDA. [COLOR=Red][B]In order to use these pads, GPIO must be set before the start
of UART.[/B][/COLOR] Please refer to Chapter 6 GPIO for exact settings.

2. UART4 has no IO ports. It is intended to communicate with the internal
GPS module.
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13.3.5 Auto Flow Control (AFC)
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The UART0 and UART1 in Exynos4210 support auto flow control (AFC) using
nRTS and nCTS signals. UART2 supports auto flow control if TxD3 and RxD3
are set as nRTS2 and nCTS2 by GPA1CON(GPIO SFR). In this case, it can be
connected to external UARTs. [COLOR=Red][B]To connect UART to a Modem, disable the AFC
bit in UMCONn register and control the signal of nRTS using software. [/B][/COLOR]
The UART4 supports auto flow control, but it is dedicated for communication
with GPS.

In AFC, the nRTS signal depends on the condition of the receiver, whereas
the nCTS signals control the operation of transmitter. The UART's
transmitter transfers the data to FIFO if nCTS signals are activated
(in AFC, nCTS signals means that other UART's FIFO is ready to receive
data). Before UART receives data, the nRTS signals must be activated if
its receive FIFO has more than 2-byte as spare. The nRTS signals must be
inactivated if its receive FIFO has less than 1-byte as spare (in AFC, the
nRTS signals means that its own receive FIFO is ready to receive data).
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13.4.1 UART Register Map Summary
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Base Addresses:
0x1380_0000,
0x1381_0000,
0x1382_0000,
0x1383_0000,
0x1384_0000
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Reg Offset Description
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ULCONn 0x0000 Specifies line control
UCONn 0x0004 Specifies control
UFCONn 0x0008 Specifies FIFO control
UMCONn 0x000C Specifies modem control
UTRSTATn 0x0010 Specifies Tx/Rx status
UERSTATn 0x0014 Specifies Rx error status
UFSTATn 0x0018 Specifies FIFO status
UMSTATn 0x001C Specifies modem status
UTXHn 0x0020 Specifies transmit buffer
URXHn 0x0024 Specifies receive buffer
UBRDIVn 0x0028 Specifies baud rate divisor
UFRACVALn 0x002C Specifies divisor fractional value
UINTPn 0x0030 Specifies interrupt pending
UINTSPn 0x0034 Specifies interrupt source pending
UINTMn 0x0038 Specifies interrupt mask
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