[Hardware Hacking General] E:V:A:
Now, "very early", and "early" is of course a bit of a hardware and terminology definition problem. That we can't get IBL output is rather likely, but anything after 1st or 2nd boot loader may be possible, depending on what's inside those bootloaders. You are the bootloader expert here, so you tell me (us) what is actually present in this one. But you surely agree that we have seen many that allow for download via USB or UART.

It may be useful to remember that the actual signal lines are the same wheter they are called RxD/TxD (UART) or DP/DM (USB). Thus the FSA is just a signal mux as you said, but there is nothing in our current documentation that states that this device (or many other for that matter), actually contain that (FSA9280) chip. In fact it seem unlikely it is using this chip, although the resistor value behavior conform to that of the data sheet. But this can be perfectly emulated in code. Furthermore, it seem that all mux chips are always in the "powered-on" state. (Another option, mentioned somewhere, was that part of this chip have been "integrated" into the PMIC, however, this seem unlikely to me. Probably this person was referring to the level shifters.)

So what I am saying is, that since debug output is eventually handed over from bootloader to kernel (which explains why certain resistor values allows for early vs. late boot/kernel debug output), it should be possible to get most of this output using your USB connection only, depending on what is available in bootloader and your USB drivers, and the initial MUX settings. (There is probably a chain of muxes here, but should be configured correctly by hardwiring or bootloader.)

Let me try to answer that, as I have been working on a FIQ document... I'll just quote:

"The difference between IRQ and FIQ is with FIQ you have to process your

stuff as quickly as possible and then get the .... out of there. An IRQ

may be interrupted by an FIQ but an IRQ cannot interrupt an FIQ. To make

FIQs faster, they have more shadow registers. FIQs cannot call SWIs. FIQs

must also disable interrupts. If it becomes necessary for an FIQ routine

to re-enable interrupts, it's too slow and should be IRQ not FIQ."

For those unaware of the acronyms, FIQ is simply the last interrupt vector

in the list which means it's not limited to a branch instruction as the other

interrupts are. That means it can execute faster than the other IRQ handlers.

Normal IRQs are limited to a branch instruction since they have to ensure

their code fits into a single word. FIQ, because it won't overwrite any

other IRQ vectors, can just run the code directly without a branch

instruction (hence the "fast").

The FIQ input line is just a way for external elements to kick the ARM

chip into FIQ mode and start executing the correct exception. There's

nothing on the ARM itself which prevents that from happening except

the CPSR.

To enable FIQ in supervisor mode:

MRS r1, cpsr ; get the cpsr.
BIC r1, r1, #0x40 ; enable FIQ (ORR to disable).
MSR cpsr_c, r1 ; copy it back, control field bit update.

A similar thing can be done for normal IRQs, but using #0x80 instead of #0x40.
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Source: Here and here.

Hope this helps.