[HD2 Android NAND Development] dorimanx:
ok some clearance about CPu steps!

the 998 is the max not overclocked 1Ghz speed...

then we can boost 5 steps up! no more...

look at the table..

struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 925, 14000},
{ 96000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 975, 14000 },
{ 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 975, 14000 },
{ 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 975, 29000 },
/* Work arround for acpu resume hung, GPLL is turn off by arm9 */
/*{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050, 29000 },*/
{ 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 975, 58000 },
{ 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 975, 117000 },
{ 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 975, 117000 },
{ 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1000, 117000 },
{ 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1025, 117000 },
{ 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1050, 117000 },
{ 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1100, 117000 },
{ 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1125, 117000 },
{ 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1150, 117000 },
{ 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1175, 117000 },
{ 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200, 128000 },
{ 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225, 128000 },
{ 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250, 128000 },
{ 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275, 128000 },
{ 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1275, 128000 },
{ 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1275, 128000 },
{ 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1275, 128000 },
#ifdef CONFIG_HTCLEO_OVERCLOCK
{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1300, 128000 },
{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1300, 128000 },
{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1152000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1190400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1F, 0, 1375, 128000 },
#endif
#ifdef CONFIG_HTCLEO_EXOVERCLOCK
{ 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1300, 128000 },
{ 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1300, 128000 },
{ 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1152000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1190400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1228800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1267200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1305600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1344000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1382400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
{ 1420800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1459200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1497600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1536000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1574400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
{ 1612800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1F, 0, 1375, 128000 },
#endif
{ 0 },
};

we are working with CONFIG_HTCLEO_EXOVERCLOCK and the 96 to 998 table.

0x1A, = 998

0x1B 1036800

0x1C 1075200

0x1D 1113600

0x1E 1152000

0x1F 1190400 <- THIS IS MAX!

but we can force cpu to use high frequency but not the max voltage..

so max voltage is 1375 and i added it only to 1612800 with 0x1F this is critical point! no more allowed!

all the rest just groups of the same freq with different voltage to save power, that all.

have fun.