[Streak 5 Android Development] ltrifonov:
Good Morning Team!

I'm still recompiling, and recompiling, and changing Freq tables and freezing after cable disconnect... with this patch

kernel is not freezing when commenting

#define OVERCLOCK_DSC

when this define is active,

streak freeze 20 seconds after disconnecting cable, every time!

row by row removed higher cpu from table, still freeze

ended with same FREQ table with lower voltage, (code below) and still freezing ?!

is it possible only my device can't work with lower voltage?

but it is working fine with olleh hacked one ?!

struct clkctl_acpu_speed acpu_freq_tbl_998[] = {
#ifdef OVERCLOCK_DSC
{ 1, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 950},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1000},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1125},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1250},
{ 1, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1250},
{ 1, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x1A, 1300},
//	{ 1, 1190400, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x1B, 1425},
//	{ 1, 1228800, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x1C, 1475},
//	{ 1, 1267200, ACPU_PLL_3, 0, 0, 0, 0, 160000, 1, 0x1D, 1525},
{ 0,0,0,0,0,0,0,0,0,0,0 },
#else
{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},
{ 1, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 1000},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
/* Update AXI_S and PLL0_S macros if above row numbers change. */
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},
{ 0, 422400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xB, 1000},
{ 0, 460800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xC, 1000},
{ 0, 499200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xD, 1050},
{ 0, 537600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xE, 1050},
{ 1, 576000, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0xF, 1050},
{ 0, 614400, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x10, 1075},
{ 0, 652800, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x11, 1100},
{ 0, 691200, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x12, 1125},
{ 0, 729600, ACPU_PLL_3, 0, 0, 0, 0, 117000, 1, 0x13, 1150},
{ 1, 768000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x14, 1150},
{ 0, 806400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x15, 1175},
{ 0, 844800, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x16, 1225},
{ 0, 883200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x17, 1250},
{ 1, 998400, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x18, 1300},
{ 1, 1075200, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x19, 1300},
{ 1, 1152000, ACPU_PLL_3, 0, 0, 0, 0, 128000, 1, 0x1A, 1400},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
#endif
};

EDIT: GOT IT !!!

that stupid comment !!!

/* Update AXI_S and PLL0_S macros if above row numbers change. */

we need first 3 rows, even starting with 0 !!!

that stupid red row !!! :)

#ifdef OVERCLOCK_DSC
[B][COLOR="Red"]{ 0, 19200, ACPU_PLL_TCXO, 0, 0, 0, 0, 14000, 0, 0, 1000},[/COLOR][/B]
{ 1, 128000, ACPU_PLL_1, 1, 5, 0, 0, 14000, 2, 0, 950},
{ 1, 245760, ACPU_PLL_0, 4, 0, 0, 0, 29000, 0, 0, 1000},
{ 1, 384000, ACPU_PLL_3, 0, 0, 0, 0, 58000, 1, 0xA, 1000},

Now, Team, i will commit this change in patch, and we must commit also your great timer fixes :)