[AT&T Samsung Galaxy S II SGH-I777] E:V:A:
Summary + Update + Uboot code

Oooh man, it's very confusing to follow well over 60 (similar) threads over

time. So let's try to summarize what we have in this case.

Ok, so far we have figured out that the Exynos-4210 is using 7-pins

(registers) for determining the processor Boot Modes by the use of the OM

(Operational Mode) register, which give its name to the XOM pins. This also

shown in the "Chip ID" section (3.2) of the Exynos Processor User's Manual.

Here is a picture of that.

(Exynos 4210 User's Manual)

In that table, it says that the OP_MODE is determined by "XOM[7:0]", however

this must be a typo since there is no XOM7 pin on the CPU pin assignments as

show in the GT-I9100 Service Manual (p.93) for chip "UPC400".

Then Adam confirmed that some of the pins are hardwired as follows:

[SIZE=2]Pin Name Defualt GPIO Function
-----------------------------------------------------------
K2 XOM0 ? ? XTAL or Tflash?
K4 XOM1 Low Device:b1
J3 XOM2 Low Device:b2
J2 XOM3 High Device:b3
J5 XOM4 Low ? --> Device:b4 ?
J4 XOM5 Low ?
K3 XOM6 ? ?
[/SIZE]

Pins marked with "?" was not found/documented.

@Adam: Can you confirm/check these? I'll update this post when you do.

Now if we gonna do some more educated guessing, instead of testing everything,

I'd like to propose the following guess, based on our experience with the

pre-decessor's processor Boot Modes of the S5PC110 (SGS-1). In that processor

we have only 6-pins (OM0..OM5) which were mapped to the input GPIO registers

ETC1[0..5].

Now, looking at the old picture below, we see that the actual boot devices

were determined by pins OM1-OM3. And as stated in the s5pc110 manual "It also

decides the device options such as bit width, wait cycles, page sizes, and ECC

modes." It further states: "USB booting is provided for system debugging and

flash reprogramming, not for normal booting. Hence, it is selected by toggling

OM[5:4] pin to "2’b10" without considering other OM pin values."

Now, that last sentence, taken in consideration with the JIG resistor values

as specified here, may be key for understanding how to boot from USB.

Basically, and so far, we have only been using the 523/619K values which are

designated for UART Factory Modes. We should instead try to use the 255/301K

values which are specified as USB Factory Modes. For this to work, we probably

also need to connect the USB VBUS (pass-through) and possibly also disconnect

our serial as stated in the s5pc110 manual shown. This lead me once again to

believe that we do not need a serial converter for getting the boot/kernel

logs etc. But that it should be enough to to have the correct (FTDI ?) serial

drivers installed on your PC, to be able to connect your terminal to virtual

serial over COM port. (All level-shifting should be taken care of automatically

by the mobile device.)

The S5PC110 OM pins (p.470):

[SIZE=2]Pin Function
---------------------------------------
XOM0 XTAL (0=? , 1=USB)
XOM1 Device:b1
XOM2 Device:b2
XOM3 Device:b3
XOM4 IROM
XOM5 MODE
---------------------------------------
Where XOM[4:5] are a combination pair:
00 = normal
01 = normal
10 = "1st Boot UART then USB"
[/SIZE]

Here's the picture:

(S5PC110 User's Manual, p.471)

The S5PV310 Boot Modes

On the Origen S5PV310 EVB CPU mainboard schematics, there are 7 pins,

XOM[0-6], where the XM0 is fixed to 3V3 and XOM6 to GND, and the others are

set by a DIP switch.

(Origen S5PV310 EVB schematics)

Similarly from another suspect Odroid A4 schematics, we have:

(in here)

with the resulting set:

[SIZE=2]Pin Defualt
----------------
XOM0 <not shown>
XOM1 0
XOM2 1
XOM3 0
XOM4 0
XOM5 <not connected>
XOM6 <not shown>
[/SIZE]

We know this device does boot from SD, but not USB. (Need verification!)

My Two Guesses

1) If the follow-up processor allows for more boot devices or functions, that

new register/pin should be added after OM3, and possibly before OM4, in order

to maintain iROM boot compatibility. (Thus left-shifting OM4 to OM5 etc..)

However, this processor is more advanced, so we can only speculate as to what

they do.

2) My second guess is about what that extra XOM pins does. That it would

determine additional boot devices seem very unlikely from both inspection of

the Uboot code below, and common sense since after iROM has passed booting to

another boot loader (BL1 etc), you can boot anything you like. But since I have no idea

if this code is the same as in our firmware there could easily be other

devices to boot from, although unlikely. More likely is that this pin is one

of:

a) used to connect to to something external,

b) used to determine the CPU core to boot from,

c) used to select/enable some secure CPU mode, RAM type, boot mode or debug interface (JTAG SW, DAP etc)

d) not used at all.

The Uboot Assembly Code

As have been mentioned elsewhere Samsung uses a minimized (?) Uboot image

for their iROM loaders. Thus you can just go check around in the Uboot sources,

for something that suit your processor and configuration. I downloaded the

uboot_22_mar_2012.tar and found the following assembly code in the file:

../uboot/board/samsung/smdkv310/lowlevel_init.S

Basically all the Boot Mode detection is happening right here, in the

subroutine called "read_om". I have edited out some comments for readability.

Now we just need to decode the cases below. But before we do that, we need to

verfiy that "smdkv310" is the code also used in our phones.

[SIZE=2]../uboot/board\/samsung/smdkv310/lowlevel_init.S read_om
-------------------------------------------------------------------------------
read_om:
/* Read booting information */
ldr r0, =S5PV310_POWER_BASE
ldr r1, [r0,#OMR_OFFSET]
bic r2, r1, #0xffffffc1

/* NAND BOOT */
cmp r2, #0xA
moveq r3, #BOOT_ONENAND

cmp r2, #0x10 @ 2KB 5-cycle 16-bit ECC
moveq r3, #BOOT_NAND

/* SD/MMC BOOT */
cmp r2, #0x4
moveq r3, #BOOT_MMCSD

/* eMMC BOOT */
cmp r2, #0x6
moveq r3, #BOOT_EMMC

#if defined(CONFIG_EVT1)
/* eMMC 4.4 BOOT */
cmp r2, #0x8
moveq r3, #BOOT_EMMC_4_4
cmp r2, #0x28
moveq r3, #BOOT_EMMC_4_4
#endif

ldr r0, =INF_REG_BASE
str r3, [r0, #INF_REG3_OFFSET]

mov pc, lr[/SIZE]

(There is also the related UART init code in there, so do have a look at the entire code.)

Thus we see that we have the following options for this early booting:

BOOT_ONENAND

BOOT_NAND

BOOT_MMCSD

BOOT_EMMC

BOOT_EMMC_4_4

including from UART0/1/2/3 which effectively also means USB.

Other Points of Interest

Overheard at the Odroid forum:

Can Odroid-A boot up from USB, MMC0 OR MMC1? How to do it?

Exynos4210's internal ROM can support eMMC43 on CH0 and eMMC44 on CH4.

There is no way to boot from MMC1.

Did you connect the eMMC memory to ODROID-A?

As per User's Manual, there is no comment of USB booting.

​

Sources and References

[1] Origen

[2] Odroid (developer site and forum)

[3] Uboot (latest)

[4] An Informative Hardkernel Presentation (~3MB, 7-zip)

[5] Chapter 6 (Booting Sequence) of the S5PC110 Manual