[Gen8 General] scholbert:
PLL fixed, but kernel still stucks...

Hey,

just a short post about the state:

- Fixed PLL by using more default values

- Clean up some code is urgently required

Texas Instruments X-Loader 1.5.1 (Mar 26 2012 - 20:41:11)
Found 0256 MB
Testing memory, please wait...
DRAM: 0253 MB OK
Memory Test success!
Archos Gen8
PRM_CLKSEL = 0x00000003
PRM_CLKSRC_CTRL = 0x00000080
CM_CLKSEL1_PLL = 0x094c0c00
CM_CLKSEL2_PLL = 0x0483600c
CM_CLKSEL3_PLL = 0x00000009
CM_CLKSEL1_PLL_MPU = 0x0011f40c
CM_CLKSEL2_PLL_MPU = 0x00000001
dpll_param_p = 0x40200d34
Reading boot sector
Loading u-boot.bin from mmc
Done!

U-Boot 2011.09 (Mar 23 2012 - 18:53:39)

OMAP3630/3730-GP ES1.2, CPU-OPP2, L3-165MHz, Max CPU Clock 1 Ghz
Archos 101IT Gen8 + LPDDR/MMC
I2C: ready
DRAM: 256 MiB
MMC: OMAP SD/MMC: 0
Using default environment
In: serial
Out: serial
Err: serial
Die ID #144800029ff800000160a4bb18027009
Hit any key to stop autoboot: 0
reading boot.scr

** Unable to read "boot.scr" from mmc 0:1 **
reading uImage

2987000 bytes read
Booting from mmc ...
## Booting kernel from Legacy Image at 82000000 ...
Image Name: Linux-2.6.29-omap1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2986936 Bytes = 2.8 MiB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux.............................................................
................................................................................
..................................................... done, booting the kernel.
<6>Initializing cgroup subsys cpu
<5>Linux version 2.6.29-omap1 (scholbert@thinkpad) (gcc version 4.4.1 (GCC) ) #1
PREEMPT Thu Mar 22 23:59:34 CET 2012
CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387f
CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
Machine: Archos A101IT board
fixup_archos: [console=ttyS2,115200n8 androidboot.console=ttyGS0 init=/linuxrc d
ebug omapdss.debug=0 vram=4915200 omapfb.vram=0:4915200 omapfb.debug=0 mmc_block
.split=0.0001:512M]
Memory policy: ECC disabled, Data cache writeback
<7>On node 0 totalpages: 65536
<7>free_area_init_node: node 0, pgdat c05fd368, node_mem_map c06a5000
<7> Normal zone: 512 pages used for memmap
<7> Normal zone: 0 pages reserved
<7> Normal zone: 65024 pages, LIFO batch:15
<4>L2 CACHE is enabled in bootloader
<6>OMAP3630 ES1.2
<6>DIE ID: 144800029FF800000160A4BB18027009
<6>FEATURE_STATUS: 00000c00
<6>SRAM: Mapped pa 0x40200000 to va 0xfc800000 size: 0x100000
<6>Reserving 4915200 bytes SDRAM for VRAM
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
<5>Kernel command line: console=ttyS2,115200n8 androidboot.console=ttyGS0 init=/
linuxrc debug omapdss.debug=0 vram=4915200 omapfb.vram=0:4915200 omapfb.debug=0
mmc_block.split=0.0001:512M
<3>Unknown boot option `androidboot.console=ttyGS0': ignoring
<3>Unknown boot option `omapdss.debug=0': ignoring
<6>Clocking rate (Crystal/DPLL/ARM core): 26.0/332/600 MHz

As you see x-load PLL values now differ from my very first post.

I know used the standard setup for beagle.

Seemed that i missed some part earlier... and also assumed that Archos uses the same setup the very beginning of boot untill Android is reached.

This definitely is not the case.

Now i'm even closer to the beagleboard track again.

Booting is pretty fine (even early boot message) up to the point when kernel is trying to re-initialize SDRC...

EDIT:

O.k. enabled PM and clock debugging in my test kernel as well:

<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered wkup_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered iva2_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered mpu_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered neon_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered core_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered cam_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dss_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered per_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered emu_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered sgx_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered usbhost_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dpll1_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dpll2_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dpll3_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dpll4_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: registered dpll5_pwrdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: associating clockdomain cm_clkdm with powerdomain core_pwrdm
<7>clockdomain: registered cm_clkdm
<7>powerdomain: associating clockdomain prm_clkdm with powerdomain wkup_pwrdm
<7>clockdomain: registered prm_clkdm
<7>powerdomain: associating clockdomain virt_opp_clkdm with powerdomain wkup_pwr
dm
<7>clockdomain: registered virt_opp_clkdm
<7>powerdomain: associating clockdomain mpu_clkdm with powerdomain mpu_pwrdm
<7>clockdomain: registered mpu_clkdm
<7>powerdomain: associating clockdomain neon_clkdm with powerdomain neon_pwrdm
<7>clockdomain: registered neon_clkdm
<7>powerdomain: associating clockdomain iva2_clkdm with powerdomain iva2_pwrdm
<7>clockdomain: registered iva2_clkdm
<7>powerdomain: associating clockdomain sgx_clkdm with powerdomain sgx_pwrdm
<7>clockdomain: registered sgx_clkdm
<7>powerdomain: associating clockdomain d2d_clkdm with powerdomain core_pwrdm
<7>clockdomain: registered d2d_clkdm
<7>powerdomain: associating clockdomain core_l3_clkdm with powerdomain core_pwrd
m
<7>clockdomain: registered core_l3_clkdm
<7>powerdomain: associating clockdomain core_l4_clkdm with powerdomain core_pwrd
m
<7>clockdomain: registered core_l4_clkdm
<7>powerdomain: associating clockdomain dss_clkdm with powerdomain dss_pwrdm
<7>clockdomain: registered dss_clkdm
<7>powerdomain: associating clockdomain cam_clkdm with powerdomain cam_pwrdm
<7>clockdomain: registered cam_clkdm
<7>powerdomain: associating clockdomain usbhost_clkdm with powerdomain usbhost_p
wrdm
<7>clockdomain: registered usbhost_clkdm
<7>powerdomain: associating clockdomain per_clkdm with powerdomain per_pwrdm
<7>clockdomain: registered per_clkdm
<7>powerdomain: associating clockdomain emu_clkdm with powerdomain emu_pwrdm
<7>clockdomain: registered emu_clkdm
<7>powerdomain: associating clockdomain dpll1_clkdm with powerdomain dpll1_pwrdm

<7>clockdomain: registered dpll1_clkdm
<7>powerdomain: associating clockdomain dpll2_clkdm with powerdomain dpll2_pwrdm

<7>clockdomain: registered dpll2_clkdm
<7>powerdomain: associating clockdomain dpll3_clkdm with powerdomain dpll3_pwrdm

<7>clockdomain: registered dpll3_clkdm
<7>powerdomain: associating clockdomain dpll4_clkdm with powerdomain dpll4_pwrdm

<7>clockdomain: registered dpll4_clkdm
<7>powerdomain: associating clockdomain dpll5_clkdm with powerdomain dpll5_pwrdm

<7>clockdomain: registered dpll5_clkdm
<6>Clocking rate (Crystal/DPLL/ARM core): 26.0/332/600 MHz
<7>clockdomain: clkdm core_l4_clkdm: clk omapctrl_ick now enabled
<7>clockdomain: core_l4_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>clockdomain: clkdm core_l3_clkdm: clk l3_ick now enabled
<7>clockdomain: core_l3_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>clockdomain: clkdm cm_clkdm: clk core_ck now enabled
<7>clockdomain: cm_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>clockdomain: clkdm dpll3_clkdm: clk dpll3_m2_ck now enabled
<7>clockdomain: dpll3_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>clockdomain: clkdm prm_clkdm: clk sys_ck now enabled
<7>clockdomain: prm_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>clockdomain: clkdm dpll5_clkdm: clk dpll5_ck now enabled
<7>clockdomain: dpll5_clkdm does not support forcing wakeup via software
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: setting next powerstate for sgx_pwrdm to 0
<7>clockdomain: enabling automatic idle transitions for sgx_clkdm
<7>powerdomain: completed transition in 7 loops
<7>powerdomain: setting next powerstate for dss_pwrdm to 1
<7>clockdomain: enabling automatic idle transitions for dss_clkdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: setting next powerstate for cam_pwrdm to 1
<7>clockdomain: enabling automatic idle transitions for cam_clkdm
<7>powerdomain: completed transition in 0 loops
<7>powerdomain: setting next powerstate for per_pwrdm to 1
<7>clockdomain: enabling automatic idle transitions for per_clkdm

Then it stucks...

Perhaps i'll need to power up some more domains in u-boot already.

Not sure though...

EDIT: Default domains are powered up already after reset.

The PM chip has to be in active state though, but this is obviously the case.

There are some differences between TWL4030 and TPS65921 regarding additional power domains.

E.g. VAUX3, VPPL2 is missing on TPS65921, VAUX2 and VPLL1 seems to be used instead.

Should be no issue here, but need to check this again.

Unfortunately there's no more debug message after the per_clkdm...

So i guess i will need to insert some printk's to get a clue where it actually stucks.

Hopefully the kernel then may give me some information where to fix up u-boot or what needs to be added at early stage.

I hope you're not bored about log postings :rolleyes:

Regards,

scholbert