[HD2 Android NAND Development] Rick_1995:
The linux kernel for the sake of cLK (as MAG is not opensource) cannot read/write to any address prior to 0x0 which is 0x11800000 after kernel init due to the MPU system on our controller which is only reset by MAGLDR for RMNET hack. Saving the list to anything after the 0x400 address is not advisable as the data is under formatted partition so buffered read and write even with a single flip in the data could lead to corruption of the all the partitions after the 1st partition that is recovery, boot, system, userdata

Leaving that alone, the fact you admit you've been into linux kernel hacking since 90s and wondering upon the fact that bootloader would be capable of marking and skipping bad blocks is totally wrong. Since we pass the CPU handle to the kernel entry and have just few ways of even passing data with limitations such as sizeof(cmdline) and the atag memory mapping. Also the fact that after passing control the bootloader is of no use and enters THREAD_SUSPENDED state of ARM assembly. So no matter what, we would have to put some code in kernel nand driver as we cannot modify the low level code on the nand controller itself.

Just to let you know after porting android to HD2, the OS partition of WM6.5 is used to store everything as we cannot modify the SPL partitions.

I really hope you have some real good background in kernel hacking and ANSI C as whatever you just said totally goes against my hope.

Since we are storing number of bad blocks x (unsigned long of 8 byte), using a unified unsigned array as a pointer to malloc wouldn't hurt much, how about 2~3 ns per cycle atleast that is what i approximate it to be assuming the IPC for qsd8250a is ~1 and running at default rate of 998400 CPS that is the values are correctly mapped in memory and aligned to the memory block size.

For starters, there can never be a unified patch for bad blocks. EVER atleast on HD2 due to the fact WM6.5 runs through older NK and WP7 uses the new SLDR while android can booted using a simple jump to linux kernel entry address.

The simple fact that NK, SLDR, SPL, MAGLDR cannot be modded and implementing the said method in cLK will lead to kernel segfault as MPU is enabled by the time we reinit nand.

I strongly agree with you about the fact that there could be a better/optimised way, but then i would laugh upon you while you go through the hacks used to run Android on HD2 and wonder how bad they are.

ARM and x86~x64 differ quite a lot in how they boot, we don't have anything called BIOS or even a slightly comparitive implementation thereof in the ARM world. The init code is hard coded on the ARM chip instead of some EEPROM/CMOS. Neither does x86~x64 MPU even come near the strictness of the said system on ARM architecture. The ARM architecture is made for and infact their whole idea/punchline is to be minimal and i dont think they or the manufacturer would even imagine that something like HD2 would be hacked with so many choices of OS that people get spoiled and start flashing their phones next to every day (Atleast i do so, infact the cLK [os - 0x400] partition is flashed every 2~3 hours)

According to the datasheet of qsd8205a, We have an ARM7 for logical operations and an ARM11 for radio, As soon as there is a power interrupt, first the ARM11(The Radio) fires first and loads the init code on the chip then switches on vreg on the ARM7 chip and passes the control, after the ARM7 chip is done doing it's init routine, it loads into memory the program stored at virtual 0x0 which is (H)SPL and that is the bootloader of our devices which cannot be hacked much due to availability of sources. HSPL at first inits the sdbank and the NAND controller, after their init, MPU kicks in then it checks for any routine method dealing with update if not it proceeds into mapping the nand(physical) 0x400 to 0x0 (Here comes in the WP7 and Android hack for HD2 if any) the software stored at 0x400 is officially the NK for WM6.5 but after cotulla got the HSPL hack to work without checking the signature in this routing, we could load any software compiled for ARM which is for now cLK or Magldr.

I am extremely sorry if i went wrong anywhere, but i won't be going by your words after going through your history on xda, sorry if i am rude or have offended you but i guess i just could be wrong. NAND flash is not like a HDD to implement something like S.M.A.R.T on, infact the way smart works is comepletely in the storage controller firmware itself by leaving some extra blocks at the trailing cylinder and remapping them to the bad blocks which pop up during use.

NAND drives aren't made for Such huge number of data writes, atleast not to the critical sections of the nand which would spell any trouble to the stability of the system where as HDD manufacturers HAVE to provide a solution for blocks which give up waay lower than the expected number of write cycles as they have no kind of presumption/idea where the user installs his OS and also most of the Critical code is stored on CMOS so we could just replace the hard disk and live well with it. Also the physical implementation of storage in HDD and NAND flash differ quite a lot having their own advantage and disadvantages.

The problem in the OP can be very particular to HD2 as in my whole life, i have never seen a device with owners flashing a new update next to everyday and hopefully you are right on the fact that linus or his team would never waste kernel space on bad block remapping.

imho - you can stop ranting about smart as it is implemented in the hard drive and not in BIOS or bootloader. unless you come up with a replacable nand controller for hd2 with inbuilt remapping logic.