[BetterBatteryStats] Karpfenhai:
Youre right, its not easy to find, i only have some pieces of circumstantial evidences collected like:

http://xdaforums.com/showpost.php?p=16772188&postcount=1

plus this address could indicate a Block in flash:

An error occurred while writing the partition.

Errors (if any):-

mtd: not writing bad block at 0x00080000
mtd: not writing bad block at 0x00080000
mtd: not writing bad block at 0x00080000
mtd: not writing bad block at 0x00080000
mtd: not writing bad block at 0x00080000

but.. in the meantime i found something better...

/* General Interrupt Enable Register */
#define SIS_GIER	0x04
#define	SIS_GIER_MODEM_TIMER_IRQ_ENABLE	0x00100000
#define	SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE	0x00080000
#define	SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE	0x00040000
#define	SIS_GIER_AC97_GPIO1_IRQ_ENABLE	0x00020000
#define	SIS_GIER_AC97_GPIO0_IRQ_ENABLE	0x00010000
#define	SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE	0x00000010
#define	SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE	0x00000008
#define	SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE	0x00000004
#define	SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE	0x00000002
#define	SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE	0x00000001

Modem receiver.. in flight mode the modem should be disabled and the issue maybe gone?

More samsung specific:

samsung-s3c6410-android.1.0 /drivers/net/ibm_emac/ibm_emac_mal.h

#ifndef __IBM_EMAC_MAL_H
#define __IBM_EMAC_MAL_H_

#include <linux/init.h>
#include <linux/list.h>
#include <linux/netdevice.h>

#include <asm/io.h>
#include <asm/dcr.h>

/*
* These MAL "versions" probably aren't the real versions IBM uses for these
* MAL cores, I assigned them just to make #ifdefs in this file nicer and
* reflect the fact that 40x and 44x have slightly different MALs. --ebs
*/
#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H)
#define MAL_VERSION 1
#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE)
#define MAL_VERSION 2
#else
#error "Unknown SoC, please check chip manual and choose MAL 'version'"
#endif

/* MALx DCR registers */
#define MAL_CFG 0x00
#define MAL_CFG_SR 0x80000000
#define MAL_CFG_PLBB 0x00004000
#define MAL_CFG_OPBBL 0x00000080
#define MAL_CFG_EOPIE 0x00000004
#define MAL_CFG_LEA 0x00000002
#define MAL_CFG_SD 0x00000001
#if MAL_VERSION == 1
#define MAL_CFG_PLBP_MASK 0x00c00000
#define MAL_CFG_PLBP_10 0x00800000
#define MAL_CFG_GA 0x00200000
#define MAL_CFG_OA 0x00100000
[B][COLOR="Red"]#define MAL_CFG_PLBLE 0x00080000[/COLOR][/B]
#define MAL_CFG_PLBT_MASK 0x00078000
#define MAL_CFG_DEFAULT (MAL_CFG_PLBP_10 | MAL_CFG_PLBT_MASK)
#elif MAL_VERSION == 2
#define MAL_CFG_RPP_MASK 0x00c00000
#define MAL_CFG_RPP_10 0x00800000
#define MAL_CFG_RMBS_MASK 0x00300000
#define MAL_CFG_WPP_MASK 0x000c0000
[COLOR="Red"][B]#define MAL_CFG_WPP_10 0x00080000[/B][/COLOR]
#define MAL_CFG_WMBS_MASK 0x00030000
#define MAL_CFG_PLBLE 0x00008000
#define MAL_CFG_DEFAULT (MAL_CFG_RMBS_MASK | MAL_CFG_WMBS_MASK | \
MAL_CFG_RPP_10 | MAL_CFG_WPP_10)
#else
#error "Unknown MAL version"
#endif

#define MAL_ESR 0x01
#define MAL_ESR_EVB 0x80000000
#define MAL_ESR_CIDT 0x40000000
#define MAL_ESR_CID_MASK 0x3e000000
#define MAL_ESR_CID_SHIFT 25
#define MAL_ESR_DE 0x00100000
#define MAL_ESR_OTE 0x00040000
#define MAL_ESR_OSE 0x00020000
#define MAL_ESR_PEIN 0x00010000
#define MAL_ESR_DEI 0x00000010
#define MAL_ESR_OTEI 0x00000004
#define MAL_ESR_OSEI 0x00000002
#define MAL_ESR_PBEI 0x00000001
#if MAL_VERSION == 1
#define MAL_ESR_ONE 0x00080000
#define MAL_ESR_ONEI 0x00000008
#elif MAL_VERSION == 2
#define MAL_ESR_PTE 0x00800000
#define MAL_ESR_PRE 0x00400000
#define MAL_ESR_PWE 0x00200000
#define MAL_ESR_PTEI 0x00000080
#define MAL_ESR_PREI 0x00000040
#define MAL_ESR_PWEI 0x00000020
#else
#error "Unknown MAL version"
#endif

#define MAL_IER 0x02
#define MAL_IER_DE 0x00000010
#define MAL_IER_OTE 0x00000004
#define MAL_IER_OE 0x00000002
#define MAL_IER_PE 0x00000001
#if MAL_VERSION == 1
#define MAL_IER_NWE 0x00000008
#define MAL_IER_SOC_EVENTS MAL_IER_NWE
#elif MAL_VERSION == 2
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
#define MAL_IER_SOC_EVENTS (MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE)
#else
#error "Unknown MAL version"
#endif
#define MAL_IER_EVENTS (MAL_IER_SOC_EVENTS | MAL_IER_OTE | \
MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE)

#define MAL_TXCASR 0x04
#define MAL_TXCARR 0x05
#define MAL_TXEOBISR 0x06
#define MAL_TXDEIR 0x07
#define MAL_RXCASR 0x10
#define MAL_RXCARR 0x11
#define MAL_RXEOBISR 0x12
#define MAL_RXDEIR 0x13
#define MAL_TXCTPR(n) ((n) + 0x20)
#define MAL_RXCTPR(n) ((n) + 0x40)
#define MAL_RCBS(n) ((n) + 0x60)

/* In reality MAL can handle TX buffers up to 4095 bytes long,
* but this isn't a good round number :) --ebs
*/
#define MAL_MAX_TX_SIZE 4080
#define MAL_MAX_RX_SIZE 4080

static inline int mal_rx_size(int len)
{
len = (len + 0xf) & ~0xf;
return len > MAL_MAX_RX_SIZE ? MAL_MAX_RX_SIZE : len;
}

static inline int mal_tx_chunks(int len)
{
return (len + MAL_MAX_TX_SIZE - 1) / MAL_MAX_TX_SIZE;
}

#define MAL_CHAN_MASK(n) (0x80000000 >> (n))

/* MAL Buffer Descriptor structure */
struct mal_descriptor {
u16 ctrl; /* MAL / Commac status control bits */
u16 data_len; /* Max length is 4K-1 (12 bits) */
u32 data_ptr; /* pointer to actual data buffer */
};

/* the following defines are for the MadMAL status and control registers. */
/* MADMAL transmit and receive status/control bits */
#define MAL_RX_CTRL_EMPTY 0x8000
#define MAL_RX_CTRL_WRAP 0x4000
#define MAL_RX_CTRL_CM 0x2000
#define MAL_RX_CTRL_LAST 0x1000
#define MAL_RX_CTRL_FIRST 0x0800
#define MAL_RX_CTRL_INTR 0x0400
#define MAL_RX_CTRL_SINGLE (MAL_RX_CTRL_LAST | MAL_RX_CTRL_FIRST)
#define MAL_IS_SINGLE_RX(ctrl) (((ctrl) & MAL_RX_CTRL_SINGLE) == MAL_RX_CTRL_SINGLE)

#define MAL_TX_CTRL_READY 0x8000
#define MAL_TX_CTRL_WRAP 0x4000
#define MAL_TX_CTRL_CM 0x2000
#define MAL_TX_CTRL_LAST 0x1000
#define MAL_TX_CTRL_INTR 0x0400

struct mal_commac_ops {
void (*poll_tx) (void *dev);
int (*poll_rx) (void *dev, int budget);
int (*peek_rx) (void *dev);
void (*rxde) (void *dev);
};

struct mal_commac {
struct mal_commac_ops *ops;
void *dev;
struct list_head poll_list;
int rx_stopped;

u32 tx_chan_mask;
u32 rx_chan_mask;
struct list_head list;
};

struct ibm_ocp_mal {
dcr_host_t dcrhost;

struct list_head poll_list;
struct napi_struct napi;

struct list_head list;
u32 tx_chan_mask;
u32 rx_chan_mask;

dma_addr_t bd_dma;
struct mal_descriptor *bd_virt;

struct ocp_def *def;
};

static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg)
{
return dcr_read(mal->dcrhost, reg);
}

static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val)
{
dcr_write(mal->dcrhost, reg, val);
}

/* Register MAL devices */
int mal_init(void) __init;
void mal_exit(void) __exit;

int mal_register_commac(struct ibm_ocp_mal *mal,
struct mal_commac *commac) __init;
void mal_unregister_commac(struct ibm_ocp_mal *mal, struct mal_commac *commac);
int mal_set_rcbs(struct ibm_ocp_mal *mal, int channel, unsigned long size);

/* Returns BD ring offset for a particular channel
(in 'struct mal_descriptor' elements)
*/
int mal_tx_bd_offset(struct ibm_ocp_mal *mal, int channel);
int mal_rx_bd_offset(struct ibm_ocp_mal *mal, int channel);

void mal_enable_tx_channel(struct ibm_ocp_mal *mal, int channel);
void mal_disable_tx_channel(struct ibm_ocp_mal *mal, int channel);
void mal_enable_rx_channel(struct ibm_ocp_mal *mal, int channel);
void mal_disable_rx_channel(struct ibm_ocp_mal *mal, int channel);

/* Add/remove EMAC to/from MAL polling list */
void mal_poll_add(struct ibm_ocp_mal *mal, struct mal_commac *commac);
void mal_poll_del(struct ibm_ocp_mal *mal, struct mal_commac *commac);

/* Ethtool MAL registers */
struct ibm_mal_regs {
u32 tx_count;
u32 rx_count;

u32 cfg;
u32 esr;
u32 ier;
u32 tx_casr;
u32 tx_carr;
u32 tx_eobisr;
u32 tx_deir;
u32 rx_casr;
u32 rx_carr;
u32 rx_eobisr;
u32 rx_deir;
u32 tx_ctpr[32];
u32 rx_ctpr[32];
u32 rcbs[32];
};

int mal_get_regs_len(struct ibm_ocp_mal *mal);
void *mal_dump_regs(struct ibm_ocp_mal *mal, void *buf);

#endif /* __IBM_EMAC_MAL_H_ */

Right from current google code:

/*

* FSL SD/MMC Defines

*-------------------------------------------------------------------

*

* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc

*

* This program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public License as

* published by the Free Software Foundation; either version 2 of

* the License, or (at your option) any later version.

*

* This program is distributed in the hope that it will be useful,

* but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

* GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, write to the Free Software

* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*

*-------------------------------------------------------------------

*

*/

#ifndef __FSL_ESDHC_H__

#define __FSL_ESDHC_H__

#include <asm/errno.h>

#include <asm/byteorder.h>

/* FSL eSDHC-specific constants */

#define SYSCTL 0x0002e02c

#define SYSCTL_INITA 0x08000000

#define SYSCTL_TIMEOUT_MASK 0x000f0000

#define SYSCTL_CLOCK_MASK 0x0000fff0

#define SYSCTL_RSTA 0x01000000

#define SYSCTL_CKEN 0x00000008

#define SYSCTL_PEREN 0x00000004

#define SYSCTL_HCKEN 0x00000002

#define SYSCTL_IPGEN 0x00000001

#define SYSCTL_RSTA 0x01000000

#define IRQSTAT 0x0002e030

#define IRQSTAT_DMAE (0x10000000)

#define IRQSTAT_AC12E (0x01000000)

#define IRQSTAT_DEBE (0x00400000)

#define IRQSTAT_DCE (0x00200000)

#define IRQSTAT_DTOE (0x00100000)

#define IRQSTAT_CIE (0x00080000)

#define IRQSTAT_CEBE (0x00040000)

#define IRQSTAT_CCE (0x00020000)

#define IRQSTAT_CTOE (0x00010000)

#define IRQSTAT_CINT (0x00000100)

#define IRQSTAT_CRM (0x00000080)

#define IRQSTAT_CINS (0x00000040)

#define IRQSTAT_BRR (0x00000020)

#define IRQSTAT_BWR (0x00000010)

#define IRQSTAT_DINT (0x00000008)

#define IRQSTAT_BGE (0x00000004)

#define IRQSTAT_TC (0x00000002)

#define IRQSTAT_CC (0x00000001)

#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)

#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)

#define IRQSTATEN 0x0002e034

#define IRQSTATEN_DMAE (0x10000000)

#define IRQSTATEN_AC12E (0x01000000)

#define IRQSTATEN_DEBE (0x00400000)

#define IRQSTATEN_DCE (0x00200000)

#define IRQSTATEN_DTOE (0x00100000)

#define IRQSTATEN_CIE (0x00080000)

#define IRQSTATEN_CEBE (0x00040000)

#define IRQSTATEN_CCE (0x00020000)

#define IRQSTATEN_CTOE (0x00010000)

#define IRQSTATEN_CINT (0x00000100)

#define IRQSTATEN_CRM (0x00000080)

#define IRQSTATEN_CINS (0x00000040)

#define IRQSTATEN_BRR (0x00000020)

#define IRQSTATEN_BWR (0x00000010)

#define IRQSTATEN_DINT (0x00000008)

#define IRQSTATEN_BGE (0x00000004)

#define IRQSTATEN_TC (0x00000002)

#define IRQSTATEN_CC (0x00000001)

#define PRSSTAT 0x0002e024

#define PRSSTAT_CLSL (0x00800000)

#define PRSSTAT_WPSPL (0x00080000)

#define PRSSTAT_CDPL (0x00040000)

#define PRSSTAT_CINS (0x00010000)

#define PRSSTAT_BREN (0x00000800)

#define PRSSTAT_BWEN (0x00000400)

#define PRSSTAT_DLA (0x00000004)

#define PRSSTAT_CICHB (0x00000002)

#define PRSSTAT_CIDHB (0x00000001)

#define PROCTL 0x0002e028

#define PROCTL_INIT 0x00000020

#define PROCTL_DTW_4 0x00000002

#define PROCTL_DTW_8 0x00000004

#define CMDARG 0x0002e008

#define XFERTYP 0x0002e00c

#define XFERTYP_CMD(x) ((x & 0x3f) << 24)

#define XFERTYP_CMDTYP_NORMAL 0x0

#define XFERTYP_CMDTYP_SUSPEND 0x00400000

#define XFERTYP_CMDTYP_RESUME 0x00800000

#define XFERTYP_CMDTYP_ABORT 0x00c00000

#define XFERTYP_DPSEL 0x00200000

#define XFERTYP_CICEN 0x00100000

#define XFERTYP_CCCEN 0x00080000

#define XFERTYP_RSPTYP_NONE 0

#define XFERTYP_RSPTYP_136 0x00010000

#define XFERTYP_RSPTYP_48 0x00020000

#define XFERTYP_RSPTYP_48_BUSY 0x00030000

#define XFERTYP_MSBSEL 0x00000020

#define XFERTYP_DTDSEL 0x00000010

#define XFERTYP_AC12EN 0x00000004

#define XFERTYP_BCEN 0x00000002

#define XFERTYP_DMAEN 0x00000001

#define CINS_TIMEOUT 1000

#define PIO_TIMEOUT 100000

#define DSADDR 0x2e004

#define CMDRSP0 0x2e010

#define CMDRSP1 0x2e014

#define CMDRSP2 0x2e018

#define CMDRSP3 0x2e01c

#define DATPORT 0x2e020

#define WML 0x2e044

#define WML_WRITE 0x00010000

#ifdef CONFIG_FSL_SDHC_V2_3

#define WML_RD_WML_MAX 0x80

#define WML_WR_WML_MAX 0x80

#define WML_RD_WML_MAX_VAL 0x0

#define WML_WR_WML_MAX_VAL 0x0

#define WML_RD_WML_MASK 0x7f

#define WML_WR_WML_MASK 0x7f0000

#else

#define WML_RD_WML_MAX 0x10

#define WML_WR_WML_MAX 0x80

#define WML_RD_WML_MAX_VAL 0x10

#define WML_WR_WML_MAX_VAL 0x80

#define WML_RD_WML_MASK 0xff

#define WML_WR_WML_MASK 0xff0000

#endif

#define BLKATTR 0x2e004

#define BLKATTR_CNT(x) ((x & 0xffff) << 16)

#define BLKATTR_SIZE(x) (x & 0x1fff)

#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */

#define ESDHC_HOSTCAPBLT_VS18 0x04000000

#define ESDHC_HOSTCAPBLT_VS30 0x02000000

#define ESDHC_HOSTCAPBLT_VS33 0x01000000

#define ESDHC_HOSTCAPBLT_SRS 0x00800000

#define ESDHC_HOSTCAPBLT_DMAS 0x00400000

#define ESDHC_HOSTCAPBLT_HSS 0x00200000

struct fsl_esdhc_cfg {

u32 esdhc_base;

u32 no_snoop;

};

/* Select the correct accessors depending on endianess */

#if __BYTE_ORDER == __LITTLE_ENDIAN

#define esdhc_read32 in_le32

#define esdhc_write32 out_le32

#define esdhc_clrsetbits32 clrsetbits_le32

#define esdhc_clrbits32 clrbits_le32

#define esdhc_setbits32 setbits_le32

#elif __BYTE_ORDER == __BIG_ENDIAN

#define esdhc_read32 in_be32

#define esdhc_write32 out_be32

#define esdhc_clrsetbits32 clrsetbits_be32

#define esdhc_clrbits32 clrbits_be32

#define esdhc_setbits32 setbits_be32

#else

#error "Endianess is not defined: please fix to continue"

#endif

#ifdef CONFIG_FSL_ESDHC

int fsl_esdhc_mmc_init(bd_t *bis);

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);

void fdt_fixup_esdhc(void *blob, bd_t *bd);

#else

static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }

static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}

#endif /* CONFIG_FSL_ESDHC */

#endif /* __FSL_ESDHC_H__ */

@ Tungstwenty, i appreciate your input!