[Galaxy 3 Android Development] Dharam_Maniar:
3) Hardware

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Processor: Samsung S5P6442 (It is modified version of S5P6440)

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General Description

SAMSUNG's S5P6440, AKA "Vega-L", is the first member of the "Vega" Series, which is our newest family of Application Processors. Each Application Processor in the Vega Series will maintain a high level of compatibility with each other in order to allow for PND Makers to design their entire line-up of products on a single SoC platform.

The S5P6440 will be Samsung's first AP designed solely for PND's with a strong emphasis on high performance while maintaining cost competitiveness.

In terms of performance, the S5P6440 is run by a powerful ARM1176 processor running at 533MHz, 667MHz with a 64-bit AXI bus.

Additionally, the S5P6440 features both 2D Graphics HW and OpenVG HW, thus providing exceptional graphics acceleration for mainstream PND products. We have also focused heavily on providing optimum IP's and interfaces in order to reduce the Bill-of-Materials of the system as a whole. As an example, the S5P6440 features upgraded NAND Error Correction HW to be able to support next generation MLC NAND Flash devices. The S5P6440 also supports serial LCD protocols via the MIPI DSI standard, which allows for lower cost, lower EMI and simpler integration.

Block Diagram

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Features

ARM1176JZF-S 533MHz, 667MHz, 16KB/16KB L1 Cache with Java acceleration Engine

Memory Subsystem

- NAND Flash Interface with x8 data bus, with 1/4/8/12/16-bit hardware ECC circuit and 4KB page mode

- Mobile DDR Interface with x16 or x32 data bus (up to 333Mbps/pin)

- DDR2 Interface with x16 or x32 data bus (up to 333Mbps/pin)

2D Graphics Accelerator with BitBlit and Rotation

Vector Graphics Accelerator with dedicated Anti-Aliasing HW

1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT support up to 800x480

Serial LCD I/F support with MIPI DSI

- Two data lanes and one clock lane

4 channel UART: 1 channel muxed with IrDA SIR/FIR

1 channel I2S

2 channel I2C interface support

3 channel MMC/SDHC/SDIO (or 1 ch HS-MMC & 1 ch SD/MMC/SDIO)

On-chip USB 2.0 OTG controller and PHY transceiver supporting high speed

Real time clock, 3 PLL's, timer with PWM and watch dog timer

8 channel DMA controller

12 channel 12-bit ADC (Touch screen interface)

2 channel SPI: 1ch muxed with TSI (transport stream interface)

Configurable GPIOs

Technical Documents:

The Only Technical Document that we have currently is the User Manual of S3C6410 RISC Processor. It is not exactly same as S5P6442 but can be used as a reference.

Download S3C6410 User Manual

TouchScreen: ATMEL mXT224(AT42QT602240)

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General Desciption

A 224-node highly configurable touchscreen controller that is part of the Atmel maXTouch product platform. An optimal and scalable architecture enables smart processing of a capacitive touch image to accurately regenerate and report the user’s interaction with the touchscreen. Multi-touch performance identifies and individually tracks touches and allows a range of built-in gestures to be reported to the host processor. The IC provides position data of 12-bit x 12-bit resolution, as well as information on the size and angle of touch. Position data is reported at >250Hz, providing fast and smooth finger tracking, making it suitable for use with demanding applications such as handwriting recognition. Due to the high signal-to-noise ratio (SNR) of up to 80:1, the device works well with fingertip touch and can also be used with a conductive stylus. It is designed to work in demanding, rapidly changing environments. Only the touchscreen area is touch-sensitive, allowing design freedom to place the chip on the main board or adjacent to the sensor. The device is ideally suited to mobile phone-sized touchscreens and can also be used on screens of up to 7", supporting single-touch or two-touch with a larger finger separation.

Technical Documents

mXT224 Datasheet

TFT LCD PANEL: Samsung S6D04D1

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General Description

S6D04D1 is a single-chip display driver IC for a TFT-LCD panel. Integrated on this chip are source drivers with built-in

memory, gate drivers and power sources. S6D04D1 can support a TFT-LCD panel up to a resolution of 240-RGB x 432-

dot graphics with 16M-color. S6D04D1 also supports various types of peripheral interface such as 80-series MCU

interface (8-/9-/16-/18-/24-bits data), 3-wire 9bit / 4-wire 8bit serial interface, and MDDI(Mobile Display Digital Interface)

S6D04D1 supports various types of RGB interface (24-/18-/16-/8-/6-bits data).

The Integrated on-chip functions that are described in this document include:

- Power saving: It reduces the overall power consumed in a TFT-LCD panel module.

- Internal GRAM:

- Internal DC/DC voltage converter

- MIE (Mobile Image Enhancement) functions

S6D04D1 features several power saving functions to reduce the overall power consumed in a TFT-LCD panel module:

S6D04D1 operates at low voltage and has internal GRAMs that can store 240-RGB x 432-dot 16M-color image data. In

addition, it has an internal DC/DC voltage converter that generates various voltages needed for driving the TFT-LCD

panel by using breeder resistors and the voltage followers.

Features

A single-chip TFT-LCD Controller/gate driver/source driver with built-in Graphic RAM

Supported Display panel resolution: 240*R/G/B (H) * 432 (V) , 240*R/G/B (H) * 400 (V) & 240*R/G/B (H) * 320 (V)

Integrated 2,488,320bit of graphic RAM (GRAM)

-GRAM configuration: 240 x 432 x 24-bits = 2,488,320bits

Supported Interfaces

-3-wire 9-bit data, 4-wire 8-bit data serial interface (for RGB parallel Interface)

-8-/9-/16-/18-/24- bit interface with 80-Series MCU (so called 80-Series)

-VSYNC I/F

-MDDI(Mobile Display Digital Interface)

Outputs

-Common electrode output

-Gate outputs

-Source outputs

Color Display mode

-Full color mode (Idle mode off): 16M / 260k / 65k colors

-Reduced color mode (Idle mode on): 8-colors (3-bit binary mode)

Color modes on the display host interface

-16-bits/Pixel: RGB= (565) using the 1,843k bit frame memory

-18-bits/Pixel: RGB= (666) using the 1,843k bit frame memory

-24-bits/Pixel: RGB= (888) using the 1,843k bit frame memory

Display features

-Partial display mode

Driving scheme: line inversion & frame inversion

MIE (Mobile Image Enhancement) functions

-Adaptive luminance/contrast enhancement function.

-Reduce the power consumption of backlight.

SE ( Sharpness Enhancement) functions

On-chip functions

-Voltage Boosters

-Adjustable VCOM voltage source generator

-An oscillator for display clock generation & Timing generation

-Factory default value (Contrast, Module ID, Module version, etc) can be stored inside IC

-MTP (Multi-time Programmable) Memory

-MTP initialization & program voltages are generated automatically from the built-in power circuit.

-Each 8-bits product ID1, ID2, ID3

-6-bits VCM Offset adjustment

-Each 5-bits for VML, GVD Offset adjustment

-1 bit for MTP writing protection

Voltage Supplies

-2.3V – 3.3V for VCI, supply voltage for Analog blocks

-1.65V – 3.3V for VDD3, Supply voltage for I/O

Output voltage levels

-2.5V to 5.0V for GVDD, Source output voltage

-AVDD, Power supply for driver circuit (Note 1)

-Maximum 6.0V for VCOM, Common electrode output voltage

-11.25V to 16.50V for VGH, Positive Gate output voltage (Note 2, Note 3)

--13.75V to - 6.75V for VGL, Negative Gate output voltage (Note 2)

CMOS compatible inputs

COG package

Operating temperature range: -40℃ to +85℃

Technical Documents

S6D04D1 Datasheet