[Eee Pad Transformer Android Development] Blades:
I don't know who he is either. I heard hes in a band.

and what I meant by posting mach-tegra/* is.. posting the contents of each file in the tegra directory of the kernel.. here.. xdagit ftw..

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig

index 9fc3449..cb9d6a4

--- a/arch/arm/mach-tegra/Kconfig

+++ b/arch/arm/mach-tegra/Kconfig

@@ -69,6 +69,10 @@ config TEGRA_OC

bool "Enable Overclocking"

default n

+config TEGRA_OC_1P6

+ bool "1.6ghz, toasty"

+ default n

+

config VENTANA_USB_MASS_STORAGE

bool "Enable Mass Storage"

default n

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c

index 33d80f9..1c8aa03 100755

--- a/arch/arm/mach-tegra/tegra2_clocks.c

+++ b/arch/arm/mach-tegra/tegra2_clocks.c

@@ -1607,10 +1607,10 @@ static struct clk tegra_pll_u = {

static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {

/* 1.6 GHz */

-/* { 12000000, 1600000000, 800, 6, 1, 12},

+ { 12000000, 1600000000, 800, 6, 1, 12},

{ 13000000, 1600000000, 985, 8, 1, 12},

{ 19200000, 1600000000, 1000, 12, 1, 8},

- { 26000000, 1600000000, 800, 13, 1, 12},*/

+ { 26000000, 1600000000, 800, 13, 1, 12},

/* 1.504 GHz */

{ 12000000, 1504000000, 752, 6, 1, 12},

@@ -1689,6 +1689,8 @@ static struct clk tegra_pll_x = {

.parent = &tegra_clk_m,

#ifdef CONFIG_TEGRA_OC

.max_rate = 1504000000,

+#elif CONFIG_TEGRA_OC_1P6

+ .max_rate = 1600000000,

#else

.max_rate = 1000000000,

#endif

@@ -1842,6 +1844,8 @@ static struct clk tegra_clk_cclk = {

.ops = &tegra_super_ops,

#ifdef CONFIG_TEGRA_OC

.max_rate = 1504000000,

+#elif CONFIG_TEGRA_OC_1P6

+ .max_rate = 1600000000,

#else

.max_rate = 1000000000,

#endif

@@ -1862,6 +1866,8 @@ static struct clk tegra_clk_virtual_cpu = {

.ops = &tegra_cpu_ops,

#ifdef CONFIG_TEGRA_OC

.max_rate = 1504000000,

+#elif CONFIG_TEGRA_OC_1P6

+ .max_rate = 1600000000,

#else

.max_rate = 1000000000,

#endif

@@ -2201,6 +2207,10 @@ static struct tegra_sku_rate_limit sku_limits[] =

RATE_LIMIT("cpu", 1504000000, 0x04, 0x08, 0x0F),

RATE_LIMIT("cclk", 1504000000, 0x04, 0x08, 0x0F),

RATE_LIMIT("pll_x", 1504000000, 0x04, 0x08, 0x0F),

+#elif CONFIG_TEGRA_OC_1P6

+ RATE_LIMIT("cpu", 1600000000, 0x04, 0x08, 0x0F),

+ RATE_LIMIT("cclk", 1600000000, 0x04, 0x08, 0x0F),

+ RATE_LIMIT("pll_x", 1600000000, 0x04, 0x08, 0x0F),

#else

RATE_LIMIT("cpu", 1000000000, 0x04, 0x08, 0x0F),

RATE_LIMIT("cclk", 1000000000, 0x04, 0x08, 0x0F),

@@ -2354,7 +2364,8 @@ static struct cpufreq_frequency_table freq_table_1p5GHz[] = {

{ 10, 1504000 },

{ 11, CPUFREQ_TABLE_END },

};

-/*static struct cpufreq_frequency_table freq_table_1p6GHz[] = {

+#ifdef CONFIG_TEGRA_OC_1P6

+static struct cpufreq_frequency_table freq_table_1p6GHz[] = {

{ 0, 216000 },

{ 1, 312000 },

{ 2, 456000 },

@@ -2365,9 +2376,11 @@ static struct cpufreq_frequency_table freq_table_1p5GHz[] = {

{ 7, 1000000 },

{ 8, 1200000 },

{ 9, 1400000 },

- { 10, 1600000 },

- { 11, CPUFREQ_TABLE_END },

-};*/

+ { 10, 1504000 },

+ { 11, 1600000 },

+ { 12, CPUFREQ_TABLE_END },

+};

+#endif

static struct tegra_cpufreq_table_data cpufreq_tables[] = {

{ freq_table_750MHz, 1, 4 },

@@ -2375,6 +2388,9 @@ static struct tegra_cpufreq_table_data cpufreq_tables[] = {

{ freq_table_1p2GHz, 2, 7 },

{ freq_table_1p4GHz, 2, 6 },

{ freq_table_1p5GHz, 2, 6 },

+#ifdef CONFIG_TEGRA_OC_1P6

+ { freq_table_1p6GHz, 2, 6 },

+#endif

};

struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)

kinda like this.. but longer