#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
void ADCHardwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32Factor) {
  uint32_t ui32Value;
  ASSERT((ui32Base == 0x40038000) || (ui32Base == 0x40039000));
  ASSERT(((ui32Factor == 0) || (ui32Factor == 2) || (ui32Factor == 4) ||
          (ui32Factor == 8) || (ui32Factor == 16) || (ui32Factor == 32) ||
          (ui32Factor == 64)));
  for (ui32Value = 0, ui32Factor >>= 1; ui32Factor;
       ui32Value++, ui32Factor >>= 1) {
  }
  (*((volatile uint32_t *)(ui32Base + 0x00000030))) = ui32Value;
}


x86 assembly (clang, -O0):
<ADCHardwareOversampleConfigure>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    $0x1,%al
cmpl   $0x40038000,-0x4(%rbp)
mov    %al,-0xd(%rbp)
je     113d <ADCHardwareOversampleConfigure+0x2d>
cmpl   $0x40039000,-0x4(%rbp)
sete   %al
mov    %al,-0xd(%rbp)
mov    -0xd(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    $0x1,%al
cmpl   $0x0,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
mov    $0x1,%al
cmpl   $0x2,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
mov    $0x1,%al
cmpl   $0x4,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
mov    $0x1,%al
cmpl   $0x8,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
mov    $0x1,%al
cmpl   $0x10,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
mov    $0x1,%al
cmpl   $0x20,-0x8(%rbp)
mov    %al,-0xe(%rbp)
je     11ae <ADCHardwareOversampleConfigure+0x9e>
cmpl   $0x40,-0x8(%rbp)
sete   %al
mov    %al,-0xe(%rbp)
mov    -0xe(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
movl   $0x0,-0xc(%rbp)
mov    -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %eax,-0x8(%rbp)
cmpl   $0x0,-0x8(%rbp)
je     11f1 <ADCHardwareOversampleConfigure+0xe1>
jmp    11da <ADCHardwareOversampleConfigure+0xca>
mov    -0xc(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %eax,-0x8(%rbp)
jmp    11cb <ADCHardwareOversampleConfigure+0xbb>
mov    -0xc(%rbp),%ecx
mov    -0x4(%rbp),%eax
add    $0x30,%eax
cltq
mov    %ecx,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCHardwareOversampleConfigure>:
push   %rbp
push   %rbx
push   %rax
mov    %esi,%ebp
mov    %edi,%ebx
mov    %edi,%eax
and    $0xffffefff,%eax
xor    %edi,%edi
cmp    $0x40038000,%eax
sete   %dil
call   1030 <ASSERT@plt>
cmp    $0x20,%ebp
ja     1179 <ADCHardwareOversampleConfigure+0x69>
mov    $0x1,%edi
mov    %ebp,%eax
movabs $0x100010115,%rcx
bt     %rax,%rcx
jae    1179 <ADCHardwareOversampleConfigure+0x69>
call   1030 <ASSERT@plt>
xor    %eax,%eax
cmp    $0x2,%ebp
jb     116c <ADCHardwareOversampleConfigure+0x5c>
xor    %eax,%eax
mov    %ebp,%ecx
nopw   0x0(%rax,%rax,1)
sar    %ecx
add    $0x1,%eax
cmp    $0x3,%ebp
mov    %ecx,%ebp
ja     1160 <ADCHardwareOversampleConfigure+0x50>
movslq %ebx,%rcx
mov    %eax,0x30(%rcx)
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret
xor    %edi,%edi
cmp    $0x40,%ebp
sete   %dil
jmp    114a <ADCHardwareOversampleConfigure+0x3a>

LLVM IR (-O0):
define void @ADCHardwareOversampleConfigure(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%6 = load i32, i32* %3
%7 = icmp eq i32 %6, 1073971200
br i1 %7, label %11, label %8
8: ; preds = %2
%9 = load i32, i32* %3
%10 = icmp eq i32 %9, 1073975296
br label %11
11: ; preds = %8, %2
%12 = phi i1 [ true, %2 ], [ %10, %8 ]
%13 = zext i1 %12 to i32
%14 = call i32 @ASSERT(i32 %13)
%15 = load i32, i32* %4
%16 = icmp eq i32 %15, 0
br i1 %16, label %35, label %17
17: ; preds = %11
%18 = load i32, i32* %4
%19 = icmp eq i32 %18, 2
br i1 %19, label %35, label %20
20: ; preds = %17
%21 = load i32, i32* %4
%22 = icmp eq i32 %21, 4
br i1 %22, label %35, label %23
23: ; preds = %20
%24 = load i32, i32* %4
%25 = icmp eq i32 %24, 8
br i1 %25, label %35, label %26
26: ; preds = %23
%27 = load i32, i32* %4
%28 = icmp eq i32 %27, 16
br i1 %28, label %35, label %29
29: ; preds = %26
%30 = load i32, i32* %4
%31 = icmp eq i32 %30, 32
br i1 %31, label %35, label %32
32: ; preds = %29
%33 = load i32, i32* %4
%34 = icmp eq i32 %33, 64
br label %35
35: ; preds = %32, %29, %26, %23, %20, %17, %11
%36 = phi i1 [ true, %29 ], [ true, %26 ], [ true, %23 ], [ true, %20 ], [ true, %17 ], [ true, %11 ], [ %34, %32 ]
%37 = zext i1 %36 to i32
%38 = call i32 @ASSERT(i32 %37)
store i32 0, i32* %5
%39 = load i32, i32* %4
%40 = ashr i32 %39, 1
store i32 %40, i32* %4
br label %41
41: ; preds = %45, %35
%42 = load i32, i32* %4
%43 = icmp ne i32 %42, 0
br i1 %43, label %44, label %50
44: ; preds = %41
br label %45
45: ; preds = %44
%46 = load i32, i32* %5
%47 = add nsw i32 %46, 1
store i32 %47, i32* %5
%48 = load i32, i32* %4
%49 = ashr i32 %48, 1
store i32 %49, i32* %4
br label %41
50: ; preds = %41
%51 = load i32, i32* %5
%52 = load i32, i32* %3
%53 = add nsw i32 %52, 48
%54 = sext i32 %53 to i64
%55 = inttoptr i64 %54 to i32*
store volatile i32 %51, i32* %55
ret void
}

LLVM IR (-O2):
define void @ADCHardwareOversampleConfigure(i32 %0, i32 %1) {
%3 = and i32 %0, -4097
%4 = icmp eq i32 %3, 1073971200
%5 = zext i1 %4 to i32
%6 = tail call i32 @ASSERT(i32 %5)
switch i32 %1, label %7 [
i32 32, label %10
i32 16, label %10
i32 8, label %10
i32 4, label %10
i32 2, label %10
i32 0, label %10
]
7: ; preds = %2
%8 = icmp eq i32 %1, 64
%9 = zext i1 %8 to i32
br label %10
10: ; preds = %2, %2, %2, %2, %2, %2, %7
%11 = phi i32 [ 1, %2 ], [ %9, %7 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ]
%12 = tail call i32 @ASSERT(i32 %11)
%13 = icmp ult i32 %1, 2
br i1 %13, label %20, label %14
14: ; preds = %10, %14
%15 = phi i32 [ %18, %14 ], [ 0, %10 ]
%16 = phi i32 [ %17, %14 ], [ %1, %10 ]
%17 = ashr i32 %16, 1
%18 = add nuw nsw i32 %15, 1
%19 = icmp ult i32 %16, 4
br i1 %19, label %20, label %14
20: ; preds = %14, %10
%21 = phi i32 [ 0, %10 ], [ %18, %14 ]
%22 = add nsw i32 %0, 48
%23 = sext i32 %22 to i64
%24 = inttoptr i64 %23 to i32*
store volatile i32 %21, i32* %24
ret void
}