#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
scalar_t__ branch_conditional_is_conditional(int);
bool is_conditional_branch(uint32_t insn) {
  uint32_t opcode = ((insn) >> 26);
  if ((opcode == 16) && branch_conditional_is_conditional(insn))
    return true;
  if (opcode == 19) {
    uint32_t sub_opcode = (((insn) >> 1) & 0x3ff);
    switch (sub_opcode) {
    case 16:
    case 528:
    case 560:
      if (branch_conditional_is_conditional(insn))
        return true;
      break;
    }
  }
  return false;
}


x86 assembly (clang, -O0):
<is_conditional_branch>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
sar    $0x1a,%eax
mov    %eax,-0xc(%rbp)
cmpl   $0x10,-0xc(%rbp)
jne    114c <is_conditional_branch+0x3c>
mov    -0x8(%rbp),%edi
call   1030 <branch_conditional_is_conditional@plt>
cmp    $0x0,%rax
je     114c <is_conditional_branch+0x3c>
movl   $0x1,-0x4(%rbp)
jmp    11cc <is_conditional_branch+0xbc>
cmpl   $0x13,-0xc(%rbp)
jne    11c5 <is_conditional_branch+0xb5>
mov    -0x8(%rbp),%eax
shr    %eax
and    $0x3ff,%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
mov    %eax,-0x14(%rbp)
sub    $0x10,%eax
je     119d <is_conditional_branch+0x8d>
jmp    1177 <is_conditional_branch+0x67>
mov    -0x14(%rbp),%eax
sub    $0x210,%eax
je     119d <is_conditional_branch+0x8d>
jmp    118a <is_conditional_branch+0x7a>
mov    -0x14(%rbp),%eax
sub    $0x230,%eax
jne    11c0 <is_conditional_branch+0xb0>
jmp    119d <is_conditional_branch+0x8d>
mov    -0x8(%rbp),%edi
call   1030 <branch_conditional_is_conditional@plt>
cmp    $0x0,%rax
je     11bb <is_conditional_branch+0xab>
movl   $0x1,-0x4(%rbp)
jmp    11cc <is_conditional_branch+0xbc>
jmp    11c0 <is_conditional_branch+0xb0>
jmp    11c5 <is_conditional_branch+0xb5>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<is_conditional_branch>:
push   %rax
mov    %edi,%ecx
sar    $0x1a,%ecx
cmp    $0x13,%ecx
je     1137 <is_conditional_branch+0x27>
mov    $0x0,%eax
cmp    $0x10,%ecx
jne    1165 <is_conditional_branch+0x55>
call   1030 <branch_conditional_is_conditional@plt>
mov    %rax,%rcx
xor    %eax,%eax
test   %rcx,%rcx
setne  %al
pop    %rcx
ret
mov    %edi,%eax
shr    %eax
and    $0x3ff,%eax
cmp    $0x10,%eax
je     1153 <is_conditional_branch+0x43>
cmp    $0x230,%eax
je     1153 <is_conditional_branch+0x43>
cmp    $0x210,%eax
jne    1167 <is_conditional_branch+0x57>
call   1030 <branch_conditional_is_conditional@plt>
mov    %rax,%rcx
mov    $0x1,%eax
test   %rcx,%rcx
je     1167 <is_conditional_branch+0x57>
pop    %rcx
ret
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
define i32 @is_conditional_branch(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
%6 = load i32, i32* %3
%7 = ashr i32 %6, 26
store i32 %7, i32* %4
%8 = load i32, i32* %4
%9 = icmp eq i32 %8, 16
br i1 %9, label %10, label %15
10: ; preds = %1
%11 = load i32, i32* %3
%12 = call i64 @branch_conditional_is_conditional(i32 %11)
%13 = icmp ne i64 %12, 0
br i1 %13, label %14, label %15
14: ; preds = %10
store i32 1, i32* %2
br label %31
15: ; preds = %10, %1
%16 = load i32, i32* %4
%17 = icmp eq i32 %16, 19
br i1 %17, label %18, label %30
18: ; preds = %15
%19 = load i32, i32* %3
%20 = ashr i32 %19, 1
%21 = and i32 %20, 1023
store i32 %21, i32* %5
%22 = load i32, i32* %5
switch i32 %22, label %29 [
i32 16, label %23
i32 528, label %23
i32 560, label %23
]
23: ; preds = %18, %18, %18
%24 = load i32, i32* %3
%25 = call i64 @branch_conditional_is_conditional(i32 %24)
%26 = icmp ne i64 %25, 0
br i1 %26, label %27, label %28
27: ; preds = %23
store i32 1, i32* %2
br label %31
28: ; preds = %23
br label %29
29: ; preds = %18, %28
br label %30
30: ; preds = %29, %15
store i32 0, i32* %2
br label %31
31: ; preds = %30, %27, %14
%32 = load i32, i32* %2
ret i32 %32
}

LLVM IR (-O2):
define i32 @is_conditional_branch(i32 %0) {
%2 = ashr i32 %0, 26
switch i32 %2, label %14 [
i32 16, label %3
i32 19, label %7
]
3: ; preds = %1
%4 = tail call i64 @branch_conditional_is_conditional(i32 %0)
%5 = icmp ne i64 %4, 0
%6 = zext i1 %5 to i32
br label %14
7: ; preds = %1
%8 = lshr i32 %0, 1
%9 = and i32 %8, 1023
switch i32 %9, label %13 [
i32 16, label %10
i32 528, label %10
i32 560, label %10
]
10: ; preds = %7, %7, %7
%11 = tail call i64 @branch_conditional_is_conditional(i32 %0)
%12 = icmp eq i64 %11, 0
br i1 %12, label %13, label %14
13: ; preds = %7, %10
br label %14
14: ; preds = %3, %1, %13, %10
%15 = phi i32 [ 1, %10 ], [ 0, %13 ], [ 0, %1 ], [ %6, %3 ]
ret i32 %15
}