#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
scalar_t__ __FLOAT_WORD_ORDER;
scalar_t__ __LITTLE_ENDIAN;
unsigned int log2(uint32_t val) {
  union {
    uint32_t u[2];
    double d;
  } t;
  t.u[__FLOAT_WORD_ORDER == __LITTLE_ENDIAN] = 0x43300000;
  t.u[__FLOAT_WORD_ORDER != __LITTLE_ENDIAN] = val;
  t.d -= 4503599627370496.0;
  return (t.u[__FLOAT_WORD_ORDER == __LITTLE_ENDIAN] >> 20) - 0x3ff;
}


x86 assembly (clang, -O0):
<log2>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    0x2ed2(%rip),%rax
mov    (%rax),%rax
mov    0x2ee0(%rip),%rcx
cmp    (%rcx),%rax
sete   %al
and    $0x1,%al
movzbl %al,%eax
cltq
movl   $0x43300000,-0x10(%rbp,%rax,4)
43
mov    -0x4(%rbp),%ecx
mov    0x2ea9(%rip),%rax
mov    (%rax),%rax
mov    0x2eb7(%rip),%rdx
cmp    (%rdx),%rax
setne  %al
and    $0x1,%al
movzbl %al,%eax
cltq
mov    %ecx,-0x10(%rbp,%rax,4)
movsd  -0x10(%rbp),%xmm0
movsd  0xea1(%rip),%xmm1
subsd  %xmm1,%xmm0
movsd  %xmm0,-0x10(%rbp)
mov    0x2e71(%rip),%rax
mov    (%rax),%rax
mov    0x2e7f(%rip),%rcx
cmp    (%rcx),%rax
sete   %al
and    $0x1,%al
movzbl %al,%eax
cltq
mov    -0x10(%rbp,%rax,4),%eax
sar    $0x14,%eax
sub    $0x3ff,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<log2>:
mov    0x2ed9(%rip),%rax
mov    (%rax),%rax
mov    0x2ee7(%rip),%rcx
xor    %edx,%edx
xor    %esi,%esi
cmp    (%rcx),%rax
sete   %dl
movl   $0x43300000,-0x8(%rsp,%rdx,4)
43
setne  %sil
mov    %edi,-0x8(%rsp,%rsi,4)
movsd  -0x8(%rsp),%xmm0
addsd  0xec7(%rip),%xmm0
movsd  %xmm0,-0x8(%rsp)
mov    -0x8(%rsp,%rdx,4),%eax
sar    $0x14,%eax
add    $0xfffffc01,%eax
ret

LLVM IR (-O0):
%union.anon = type { double }
@__FLOAT_WORD_ORDER = global i64 0
@__LITTLE_ENDIAN = global i64 0
define i32 @log2(i32 %0) {
%2 = alloca i32
%3 = alloca %union.anon
store i32 %0, i32* %2
%4 = bitcast %union.anon* %3 to [2 x i32]*
%5 = load i64, i64* @__FLOAT_WORD_ORDER
%6 = load i64, i64* @__LITTLE_ENDIAN
%7 = icmp eq i64 %5, %6
%8 = zext i1 %7 to i32
%9 = sext i32 %8 to i64
%10 = getelementptr inbounds [2 x i32], [2 x i32]* %4, i64 0, i64 %9
store i32 1127219200, i32* %10
%11 = load i32, i32* %2
%12 = bitcast %union.anon* %3 to [2 x i32]*
%13 = load i64, i64* @__FLOAT_WORD_ORDER
%14 = load i64, i64* @__LITTLE_ENDIAN
%15 = icmp ne i64 %13, %14
%16 = zext i1 %15 to i32
%17 = sext i32 %16 to i64
%18 = getelementptr inbounds [2 x i32], [2 x i32]* %12, i64 0, i64 %17
store i32 %11, i32* %18
%19 = bitcast %union.anon* %3 to double*
%20 = load double, double* %19
%21 = fsub double %20, 0x4330000000000000
store double %21, double* %19
%22 = bitcast %union.anon* %3 to [2 x i32]*
%23 = load i64, i64* @__FLOAT_WORD_ORDER
%24 = load i64, i64* @__LITTLE_ENDIAN
%25 = icmp eq i64 %23, %24
%26 = zext i1 %25 to i32
%27 = sext i32 %26 to i64
%28 = getelementptr inbounds [2 x i32], [2 x i32]* %22, i64 0, i64 %27
%29 = load i32, i32* %28
%30 = ashr i32 %29, 20
%31 = sub nsw i32 %30, 1023
ret i32 %31
}

LLVM IR (-O2):
%union.anon = type { double }
@__FLOAT_WORD_ORDER = global i64 0
@__LITTLE_ENDIAN = global i64 0
define i32 @log2(i32 %0) {
%2 = alloca %union.anon
%3 = bitcast %union.anon* %2 to i8*
%4 = bitcast %union.anon* %2 to [2 x i32]*
%5 = load i64, i64* @__FLOAT_WORD_ORDER
%6 = load i64, i64* @__LITTLE_ENDIAN
%7 = icmp eq i64 %5, %6
%8 = zext i1 %7 to i64
%9 = getelementptr inbounds [2 x i32], [2 x i32]* %4, i64 0, i64 %8
store i32 1127219200, i32* %9
%10 = icmp ne i64 %5, %6
%11 = zext i1 %10 to i64
%12 = getelementptr inbounds [2 x i32], [2 x i32]* %4, i64 0, i64 %11
store i32 %0, i32* %12
%13 = getelementptr inbounds %union.anon, %union.anon* %2, i64 0, i32 0
%14 = load double, double* %13
%15 = fadd double %14, 0xC330000000000000
store double %15, double* %13
%16 = load i32, i32* %9
%17 = ashr i32 %16, 20
%18 = add nsw i32 %17, -1023
ret i32 %18
}