void _L3L4_clock_domain_open(void) {
  (*((volatile unsigned int *)((0x44E00000) + (0x4)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0x4)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0xc)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0xc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0xdc)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0xdc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0xe0)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0xe0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0x12c)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0x12c)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0x0)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0x0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)((0x44E00000) + (0x60)))) |= (0x2u);
  while (((*((volatile unsigned int *)((0x44E00000) + (0x60)))) &
          (0x00000003u)) != (0x2u))
    ;
  while (
      !((*((volatile unsigned int *)((0x44E00000) + (0x4)))) & (0x00000008u)))
    ;
  while (
      !((*((volatile unsigned int *)((0x44E00000) + (0xc)))) & (0x00000010u)))
    ;
  while (!((*((volatile unsigned int *)((0x44E00000) + (0x12c)))) &
           ((0x00000010u) | (0x00000020u))))
    ;
  while (
      !((*((volatile unsigned int *)((0x44E00000) + (0x0)))) & ((0x00000100u))))
    ;
}


x86 assembly (clang, -O0):
<_L3L4_clock_domain_open>:
push   %rbp
mov    %rsp,%rbp
mov    $0x44e00004,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00004,%eax
mov    %ecx,(%rax)
mov    $0x44e00004,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     112d <_L3L4_clock_domain_open+0x2d>
jmp    1115 <_L3L4_clock_domain_open+0x15>
mov    $0x44e0000c,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e0000c,%eax
mov    %ecx,(%rax)
mov    $0x44e0000c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1156 <_L3L4_clock_domain_open+0x56>
jmp    113e <_L3L4_clock_domain_open+0x3e>
mov    $0x44e000dc,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e000dc,%eax
mov    %ecx,(%rax)
mov    $0x44e000dc,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     117f <_L3L4_clock_domain_open+0x7f>
jmp    1167 <_L3L4_clock_domain_open+0x67>
mov    $0x44e000e0,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e000e0,%eax
mov    %ecx,(%rax)
mov    $0x44e000e0,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11a8 <_L3L4_clock_domain_open+0xa8>
jmp    1190 <_L3L4_clock_domain_open+0x90>
mov    $0x44e0012c,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e0012c,%eax
mov    %ecx,(%rax)
mov    $0x44e0012c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11d1 <_L3L4_clock_domain_open+0xd1>
jmp    11b9 <_L3L4_clock_domain_open+0xb9>
mov    $0x44e00000,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00000,%eax
mov    %ecx,(%rax)
mov    $0x44e00000,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11fa <_L3L4_clock_domain_open+0xfa>
jmp    11e2 <_L3L4_clock_domain_open+0xe2>
mov    $0x44e00060,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00060,%eax
mov    %ecx,(%rax)
mov    $0x44e00060,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1223 <_L3L4_clock_domain_open+0x123>
jmp    120b <_L3L4_clock_domain_open+0x10b>
jmp    1228 <_L3L4_clock_domain_open+0x128>
mov    $0x44e00004,%eax
mov    (%rax),%eax
and    $0x8,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    1247 <_L3L4_clock_domain_open+0x147>
jmp    124c <_L3L4_clock_domain_open+0x14c>
jmp    1228 <_L3L4_clock_domain_open+0x128>
jmp    1251 <_L3L4_clock_domain_open+0x151>
mov    $0x44e0000c,%eax
mov    (%rax),%eax
and    $0x10,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    1270 <_L3L4_clock_domain_open+0x170>
jmp    1275 <_L3L4_clock_domain_open+0x175>
jmp    1251 <_L3L4_clock_domain_open+0x151>
jmp    127a <_L3L4_clock_domain_open+0x17a>
mov    $0x44e0012c,%eax
mov    (%rax),%eax
and    $0x30,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    1299 <_L3L4_clock_domain_open+0x199>
jmp    129e <_L3L4_clock_domain_open+0x19e>
jmp    127a <_L3L4_clock_domain_open+0x17a>
jmp    12a3 <_L3L4_clock_domain_open+0x1a3>
mov    $0x44e00000,%eax
mov    (%rax),%eax
and    $0x100,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    12c4 <_L3L4_clock_domain_open+0x1c4>
jmp    12c9 <_L3L4_clock_domain_open+0x1c9>
jmp    12a3 <_L3L4_clock_domain_open+0x1a3>
pop    %rbp
ret

x86 assembly (clang, -O2):
<_L3L4_clock_domain_open>:
orl    $0x2,0x44e00004
02
nopl   0x0(%rax,%rax,1)
mov    0x44e00004,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1110 <_L3L4_clock_domain_open+0x10>
orl    $0x2,0x44e0000c
02
nopw   0x0(%rax,%rax,1)
mov    0x44e0000c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1130 <_L3L4_clock_domain_open+0x30>
orl    $0x2,0x44e000dc
02
nopw   0x0(%rax,%rax,1)
mov    0x44e000dc,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1150 <_L3L4_clock_domain_open+0x50>
orl    $0x2,0x44e000e0
02
nopw   0x0(%rax,%rax,1)
mov    0x44e000e0,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1170 <_L3L4_clock_domain_open+0x70>
orl    $0x2,0x44e0012c
02
nopw   0x0(%rax,%rax,1)
mov    0x44e0012c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1190 <_L3L4_clock_domain_open+0x90>
orl    $0x2,0x44e00000
02
nopw   0x0(%rax,%rax,1)
mov    0x44e00000,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11b0 <_L3L4_clock_domain_open+0xb0>
orl    $0x2,0x44e00060
02
nopw   0x0(%rax,%rax,1)
mov    0x44e00060,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11d0 <_L3L4_clock_domain_open+0xd0>
nop
testl  $0x8,0x44e00004
je     11e0 <_L3L4_clock_domain_open+0xe0>
nopl   (%rax)
testl  $0x10,0x44e0000c
je     11f0 <_L3L4_clock_domain_open+0xf0>
nopl   (%rax)
testl  $0x30,0x44e0012c
je     1200 <_L3L4_clock_domain_open+0x100>
nopl   (%rax)
testl  $0x100,0x44e00000
je     1210 <_L3L4_clock_domain_open+0x110>
ret

LLVM IR (-O0):
define void @_L3L4_clock_domain_open() {
%1 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%2 = or i32 %1, 2
store volatile i32 %2, i32* inttoptr (i64 1155530756 to i32*)
br label %3
3: ; preds = %7, %0
%4 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%5 = and i32 %4, 3
%6 = icmp ne i32 %5, 2
br i1 %6, label %7, label %8
7: ; preds = %3
br label %3
8: ; preds = %3
%9 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%10 = or i32 %9, 2
store volatile i32 %10, i32* inttoptr (i64 1155530764 to i32*)
br label %11
11: ; preds = %15, %8
%12 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%13 = and i32 %12, 3
%14 = icmp ne i32 %13, 2
br i1 %14, label %15, label %16
15: ; preds = %11
br label %11
16: ; preds = %11
%17 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%18 = or i32 %17, 2
store volatile i32 %18, i32* inttoptr (i64 1155530972 to i32*)
br label %19
19: ; preds = %23, %16
%20 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%21 = and i32 %20, 3
%22 = icmp ne i32 %21, 2
br i1 %22, label %23, label %24
23: ; preds = %19
br label %19
24: ; preds = %19
%25 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%26 = or i32 %25, 2
store volatile i32 %26, i32* inttoptr (i64 1155530976 to i32*)
br label %27
27: ; preds = %31, %24
%28 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%29 = and i32 %28, 3
%30 = icmp ne i32 %29, 2
br i1 %30, label %31, label %32
31: ; preds = %27
br label %27
32: ; preds = %27
%33 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%34 = or i32 %33, 2
store volatile i32 %34, i32* inttoptr (i64 1155531052 to i32*)
br label %35
35: ; preds = %39, %32
%36 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%37 = and i32 %36, 3
%38 = icmp ne i32 %37, 2
br i1 %38, label %39, label %40
39: ; preds = %35
br label %35
40: ; preds = %35
%41 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%42 = or i32 %41, 2
store volatile i32 %42, i32* inttoptr (i64 1155530752 to i32*)
br label %43
43: ; preds = %47, %40
%44 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%45 = and i32 %44, 3
%46 = icmp ne i32 %45, 2
br i1 %46, label %47, label %48
47: ; preds = %43
br label %43
48: ; preds = %43
%49 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%50 = or i32 %49, 2
store volatile i32 %50, i32* inttoptr (i64 1155530848 to i32*)
br label %51
51: ; preds = %55, %48
%52 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%53 = and i32 %52, 3
%54 = icmp ne i32 %53, 2
br i1 %54, label %55, label %56
55: ; preds = %51
br label %51
56: ; preds = %51
br label %57
57: ; preds = %62, %56
%58 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%59 = and i32 %58, 8
%60 = icmp ne i32 %59, 0
%61 = xor i1 %60, true
br i1 %61, label %62, label %63
62: ; preds = %57
br label %57
63: ; preds = %57
br label %64
64: ; preds = %69, %63
%65 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%66 = and i32 %65, 16
%67 = icmp ne i32 %66, 0
%68 = xor i1 %67, true
br i1 %68, label %69, label %70
69: ; preds = %64
br label %64
70: ; preds = %64
br label %71
71: ; preds = %76, %70
%72 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%73 = and i32 %72, 48
%74 = icmp ne i32 %73, 0
%75 = xor i1 %74, true
br i1 %75, label %76, label %77
76: ; preds = %71
br label %71
77: ; preds = %71
br label %78
78: ; preds = %83, %77
%79 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%80 = and i32 %79, 256
%81 = icmp ne i32 %80, 0
%82 = xor i1 %81, true
br i1 %82, label %83, label %84
83: ; preds = %78
br label %78
84: ; preds = %78
ret void
}

LLVM IR (-O2):
define void @_L3L4_clock_domain_open() {
%1 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%2 = or i32 %1, 2
store volatile i32 %2, i32* inttoptr (i64 1155530756 to i32*)
br label %3
3: ; preds = %3, %0
%4 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%5 = and i32 %4, 3
%6 = icmp eq i32 %5, 2
br i1 %6, label %7, label %3
7: ; preds = %3
%8 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%9 = or i32 %8, 2
store volatile i32 %9, i32* inttoptr (i64 1155530764 to i32*)
br label %10
10: ; preds = %10, %7
%11 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%12 = and i32 %11, 3
%13 = icmp eq i32 %12, 2
br i1 %13, label %14, label %10
14: ; preds = %10
%15 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%16 = or i32 %15, 2
store volatile i32 %16, i32* inttoptr (i64 1155530972 to i32*)
br label %17
17: ; preds = %17, %14
%18 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%19 = and i32 %18, 3
%20 = icmp eq i32 %19, 2
br i1 %20, label %21, label %17
21: ; preds = %17
%22 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%23 = or i32 %22, 2
store volatile i32 %23, i32* inttoptr (i64 1155530976 to i32*)
br label %24
24: ; preds = %24, %21
%25 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%26 = and i32 %25, 3
%27 = icmp eq i32 %26, 2
br i1 %27, label %28, label %24
28: ; preds = %24
%29 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%30 = or i32 %29, 2
store volatile i32 %30, i32* inttoptr (i64 1155531052 to i32*)
br label %31
31: ; preds = %31, %28
%32 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%33 = and i32 %32, 3
%34 = icmp eq i32 %33, 2
br i1 %34, label %35, label %31
35: ; preds = %31
%36 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%37 = or i32 %36, 2
store volatile i32 %37, i32* inttoptr (i64 1155530752 to i32*)
br label %38
38: ; preds = %38, %35
%39 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%40 = and i32 %39, 3
%41 = icmp eq i32 %40, 2
br i1 %41, label %42, label %38
42: ; preds = %38
%43 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%44 = or i32 %43, 2
store volatile i32 %44, i32* inttoptr (i64 1155530848 to i32*)
br label %45
45: ; preds = %45, %42
%46 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%47 = and i32 %46, 3
%48 = icmp eq i32 %47, 2
br i1 %48, label %49, label %45
49: ; preds = %45, %49
%50 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%51 = and i32 %50, 8
%52 = icmp eq i32 %51, 0
br i1 %52, label %49, label %53
53: ; preds = %49, %53
%54 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%55 = and i32 %54, 16
%56 = icmp eq i32 %55, 0
br i1 %56, label %53, label %57
57: ; preds = %53, %57
%58 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%59 = and i32 %58, 48
%60 = icmp eq i32 %59, 0
br i1 %60, label %57, label %61
61: ; preds = %57, %61
%62 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%63 = and i32 %62, 256
%64 = icmp eq i32 %63, 0
br i1 %64, label %61, label %65
65: ; preds = %61
ret void
}