void GPIODMATriggerDisable(unsigned long ulPort) {
  ;
  if (ulPort == 0x40004000) {
    (*((volatile unsigned long *)(0x400F7000 + 0x000000C8))) &= ~0x1;
  } else if (ulPort == 0x40005000) {
    (*((volatile unsigned long *)(0x400F7000 + 0x000000C8))) &= ~0x2;
  } else if (ulPort == 0x40006000) {
    (*((volatile unsigned long *)(0x400F7000 + 0x000000C8))) &= ~0x4;
  } else if (ulPort == 0x40007000) {
    (*((volatile unsigned long *)(0x400F7000 + 0x000000C8))) &= ~0x8;
  }
}


x86 assembly (clang, -O0):
<GPIODMATriggerDisable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
cmpq   $0x40004000,-0x8(%rbp)
40
jne    112f <GPIODMATriggerDisable+0x2f>
mov    $0x400f70c8,%eax
mov    (%rax),%rcx
and    $0xfffffffffffffffe,%rcx
mov    $0x400f70c8,%eax
mov    %rcx,(%rax)
jmp    11ae <GPIODMATriggerDisable+0xae>
cmpq   $0x40005000,-0x8(%rbp)
40
jne    1156 <GPIODMATriggerDisable+0x56>
mov    $0x400f70c8,%eax
mov    (%rax),%rcx
and    $0xfffffffffffffffd,%rcx
mov    $0x400f70c8,%eax
mov    %rcx,(%rax)
jmp    11a9 <GPIODMATriggerDisable+0xa9>
cmpq   $0x40006000,-0x8(%rbp)
40
jne    117d <GPIODMATriggerDisable+0x7d>
mov    $0x400f70c8,%eax
mov    (%rax),%rcx
and    $0xfffffffffffffffb,%rcx
mov    $0x400f70c8,%eax
mov    %rcx,(%rax)
jmp    11a4 <GPIODMATriggerDisable+0xa4>
cmpq   $0x40007000,-0x8(%rbp)
40
jne    119f <GPIODMATriggerDisable+0x9f>
mov    $0x400f70c8,%eax
mov    (%rax),%rcx
and    $0xfffffffffffffff7,%rcx
mov    $0x400f70c8,%eax
mov    %rcx,(%rax)
jmp    11a4 <GPIODMATriggerDisable+0xa4>
jmp    11a9 <GPIODMATriggerDisable+0xa9>
jmp    11ae <GPIODMATriggerDisable+0xae>
pop    %rbp
ret

x86 assembly (clang, -O2):
<GPIODMATriggerDisable>:
add    $0xffffffffbfffc000,%rdi
rol    $0x34,%rdi
cmp    $0x3,%rdi
ja     1124 <GPIODMATriggerDisable+0x24>
lea    0xee8(%rip),%rax
mov    (%rax,%rdi,8),%rax
and    %rax,0x400f70c8
40
ret

LLVM IR (-O0):
define void @GPIODMATriggerDisable(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = icmp eq i64 %3, 1073758208
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load volatile i64, i64* inttoptr (i64 1074753736 to i64*)
%7 = and i64 %6, -2
store volatile i64 %7, i64* inttoptr (i64 1074753736 to i64*)
br label %29
8: ; preds = %1
%9 = load i64, i64* %2
%10 = icmp eq i64 %9, 1073762304
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load volatile i64, i64* inttoptr (i64 1074753736 to i64*)
%13 = and i64 %12, -3
store volatile i64 %13, i64* inttoptr (i64 1074753736 to i64*)
br label %28
14: ; preds = %8
%15 = load i64, i64* %2
%16 = icmp eq i64 %15, 1073766400
br i1 %16, label %17, label %20
17: ; preds = %14
%18 = load volatile i64, i64* inttoptr (i64 1074753736 to i64*)
%19 = and i64 %18, -5
store volatile i64 %19, i64* inttoptr (i64 1074753736 to i64*)
br label %27
20: ; preds = %14
%21 = load i64, i64* %2
%22 = icmp eq i64 %21, 1073770496
br i1 %22, label %23, label %26
23: ; preds = %20
%24 = load volatile i64, i64* inttoptr (i64 1074753736 to i64*)
%25 = and i64 %24, -9
store volatile i64 %25, i64* inttoptr (i64 1074753736 to i64*)
br label %26
26: ; preds = %23, %20
br label %27
27: ; preds = %26, %17
br label %28
28: ; preds = %27, %11
br label %29
29: ; preds = %28, %5
ret void
}

LLVM IR (-O2):
@switch.table.GPIODMATriggerDisable = [4 x i64] [i64 -2, i64 -3, i64 -5, i64 -9]
define void @GPIODMATriggerDisable(i64 %0) {
%2 = add i64 %0, -1073758208
%3 = tail call i64 @llvm.fshl.i64(i64 %2, i64 %2, i64 52)
%4 = icmp ult i64 %3, 4
br i1 %4, label %5, label %10
5: ; preds = %1
%6 = getelementptr inbounds [4 x i64], [4 x i64]* @switch.table.GPIODMATriggerDisable, i64 0, i64 %3
%7 = load i64, i64* %6
%8 = load volatile i64, i64* inttoptr (i64 1074753736 to i64*)
%9 = and i64 %8, %7
store volatile i64 %9, i64* inttoptr (i64 1074753736 to i64*)
br label %10
10: ; preds = %1, %5
ret void
}