#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) {
  uint32_t ui32Config;
  ASSERT((ui32Base == 0x40038000) || (ui32Base == 0x40039000));
  ui32Config = (*((volatile uint32_t *)(ui32Base + 0x00000FC8)));
  if (pui32ClockDiv) {
    *pui32ClockDiv = ((ui32Config & 0x000003F0) >> 4) + 1;
  }
  ui32Config &= ~0x000003F0;
  ui32Config |= ((*((volatile uint32_t *)(ui32Base + 0x00000FC4))) & 0x0000000F)
                << 4;
  return (ui32Config);
}


x86 assembly (clang, -O0):
<ADCClockConfigGet>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    $0x1,%al
cmpl   $0x40038000,-0x4(%rbp)
mov    %al,-0x15(%rbp)
je     113e <ADCClockConfigGet+0x2e>
cmpl   $0x40039000,-0x4(%rbp)
sete   %al
mov    %al,-0x15(%rbp)
mov    -0x15(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0x4(%rbp),%eax
add    $0xfc8,%eax
cltq
mov    (%rax),%eax
mov    %eax,-0x14(%rbp)
cmpq   $0x0,-0x10(%rbp)
je     117a <ADCClockConfigGet+0x6a>
mov    -0x14(%rbp),%ecx
and    $0x3f0,%ecx
sar    $0x4,%ecx
add    $0x1,%ecx
mov    -0x10(%rbp),%rax
mov    %ecx,(%rax)
mov    -0x14(%rbp),%eax
and    $0xfffffc0f,%eax
mov    %eax,-0x14(%rbp)
mov    -0x4(%rbp),%eax
add    $0xfc4,%eax
cltq
mov    (%rax),%eax
and    $0xf,%eax
shl    $0x4,%eax
or     -0x14(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCClockConfigGet>:
push   %rbp
push   %rbx
push   %rax
mov    %rsi,%rbx
mov    %edi,%ebp
mov    %edi,%eax
and    $0xffffefff,%eax
xor    %edi,%edi
cmp    $0x40038000,%eax
sete   %dil
call   1030 <ASSERT@plt>
movslq %ebp,%rax
mov    0xfc8(%rax),%ecx
test   %rbx,%rbx
je     114a <ADCClockConfigGet+0x3a>
mov    %ecx,%edx
shr    $0x4,%edx
and    $0x3f,%edx
add    $0x1,%edx
mov    %edx,(%rbx)
and    $0xfffffc0f,%ecx
mov    0xfc4(%rax),%eax
shl    $0x4,%eax
movzbl %al,%eax
or     %ecx,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
define i32 @ADCClockConfigGet(i32 %0, i32* %1) {
%3 = alloca i32
%4 = alloca i32*
%5 = alloca i32
store i32 %0, i32* %3
store i32* %1, i32** %4
%6 = load i32, i32* %3
%7 = icmp eq i32 %6, 1073971200
br i1 %7, label %11, label %8
8: ; preds = %2
%9 = load i32, i32* %3
%10 = icmp eq i32 %9, 1073975296
br label %11
11: ; preds = %8, %2
%12 = phi i1 [ true, %2 ], [ %10, %8 ]
%13 = zext i1 %12 to i32
%14 = call i32 @ASSERT(i32 %13)
%15 = load i32, i32* %3
%16 = add nsw i32 %15, 4040
%17 = sext i32 %16 to i64
%18 = inttoptr i64 %17 to i32*
%19 = load volatile i32, i32* %18
store i32 %19, i32* %5
%20 = load i32*, i32** %4
%21 = icmp ne i32* %20, null
br i1 %21, label %22, label %28
22: ; preds = %11
%23 = load i32, i32* %5
%24 = and i32 %23, 1008
%25 = ashr i32 %24, 4
%26 = add nsw i32 %25, 1
%27 = load i32*, i32** %4
store i32 %26, i32* %27
br label %28
28: ; preds = %22, %11
%29 = load i32, i32* %5
%30 = and i32 %29, -1009
store i32 %30, i32* %5
%31 = load i32, i32* %3
%32 = add nsw i32 %31, 4036
%33 = sext i32 %32 to i64
%34 = inttoptr i64 %33 to i32*
%35 = load volatile i32, i32* %34
%36 = and i32 %35, 15
%37 = shl i32 %36, 4
%38 = load i32, i32* %5
%39 = or i32 %38, %37
store i32 %39, i32* %5
%40 = load i32, i32* %5
ret i32 %40
}

LLVM IR (-O2):
define i32 @ADCClockConfigGet(i32 %0, i32* writeonly %1) {
%3 = and i32 %0, -4097
%4 = icmp eq i32 %3, 1073971200
%5 = zext i1 %4 to i32
%6 = tail call i32 @ASSERT(i32 %5)
%7 = add nsw i32 %0, 4040
%8 = sext i32 %7 to i64
%9 = inttoptr i64 %8 to i32*
%10 = load volatile i32, i32* %9
%11 = icmp eq i32* %1, null
br i1 %11, label %16, label %12
12: ; preds = %2
%13 = lshr i32 %10, 4
%14 = and i32 %13, 63
%15 = add nuw nsw i32 %14, 1
store i32 %15, i32* %1
br label %16
16: ; preds = %12, %2
%17 = and i32 %10, -1009
%18 = add nsw i32 %0, 4036
%19 = sext i32 %18 to i64
%20 = inttoptr i64 %19 to i32*
%21 = load volatile i32, i32* %20
%22 = shl i32 %21, 4
%23 = and i32 %22, 240
%24 = or i32 %23, %17
ret i32 %24
}