void uDMAChannelAttributeEnable(unsigned long ulChannel, unsigned long ulAttr) {
  ;

  ;
  if (ulAttr & 0x00000001) {
    (*((volatile unsigned long *)(0x400FF018))) = 1 << ulChannel;
  }
  if (ulAttr & 0x00000002) {
    (*((volatile unsigned long *)(0x400FF030))) = 1 << ulChannel;
  }
  if (ulAttr & 0x00000004) {
    (*((volatile unsigned long *)(0x400FF038))) = 1 << ulChannel;
  }
  if (ulAttr & 0x00000008) {
    (*((volatile unsigned long *)(0x400FF020))) = 1 << ulChannel;
  }
}


x86 assembly (clang, -O0):
<uDMAChannelAttributeEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x10(%rbp),%rax
and    $0x1,%rax
cmp    $0x0,%rax
je     1136 <uDMAChannelAttributeEnable+0x36>
mov    -0x8(%rbp),%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0x400ff018,%eax
mov    %rcx,(%rax)
mov    -0x10(%rbp),%rax
and    $0x2,%rax
cmp    $0x0,%rax
je     1160 <uDMAChannelAttributeEnable+0x60>
mov    -0x8(%rbp),%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0x400ff030,%eax
mov    %rcx,(%rax)
mov    -0x10(%rbp),%rax
and    $0x4,%rax
cmp    $0x0,%rax
je     118a <uDMAChannelAttributeEnable+0x8a>
mov    -0x8(%rbp),%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0x400ff038,%eax
mov    %rcx,(%rax)
mov    -0x10(%rbp),%rax
and    $0x8,%rax
cmp    $0x0,%rax
je     11b4 <uDMAChannelAttributeEnable+0xb4>
mov    -0x8(%rbp),%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0x400ff020,%eax
mov    %rcx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<uDMAChannelAttributeEnable>:
mov    %rdi,%rcx
test   $0x1,%sil
jne    111c <uDMAChannelAttributeEnable+0x1c>
test   $0x2,%sil
jne    1133 <uDMAChannelAttributeEnable+0x33>
test   $0x4,%sil
jne    114a <uDMAChannelAttributeEnable+0x4a>
test   $0x8,%sil
jne    1161 <uDMAChannelAttributeEnable+0x61>
ret
mov    $0x1,%eax
shl    %cl,%eax
cltq
mov    %rax,0x400ff018
40
test   $0x2,%sil
je     110f <uDMAChannelAttributeEnable+0xf>
mov    $0x1,%eax
shl    %cl,%eax
cltq
mov    %rax,0x400ff030
40
test   $0x4,%sil
je     1115 <uDMAChannelAttributeEnable+0x15>
mov    $0x1,%eax
shl    %cl,%eax
cltq
mov    %rax,0x400ff038
40
test   $0x8,%sil
je     111b <uDMAChannelAttributeEnable+0x1b>
mov    $0x1,%eax
shl    %cl,%eax
cltq
mov    %rax,0x400ff020
40
ret

LLVM IR (-O0):
define void @uDMAChannelAttributeEnable(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%5 = load i64, i64* %4
%6 = and i64 %5, 1
%7 = icmp ne i64 %6, 0
br i1 %7, label %8, label %13
8: ; preds = %2
%9 = load i64, i64* %3
%10 = trunc i64 %9 to i32
%11 = shl i32 1, %10
%12 = sext i32 %11 to i64
store volatile i64 %12, i64* inttoptr (i64 1074786328 to i64*)
br label %13
13: ; preds = %8, %2
%14 = load i64, i64* %4
%15 = and i64 %14, 2
%16 = icmp ne i64 %15, 0
br i1 %16, label %17, label %22
17: ; preds = %13
%18 = load i64, i64* %3
%19 = trunc i64 %18 to i32
%20 = shl i32 1, %19
%21 = sext i32 %20 to i64
store volatile i64 %21, i64* inttoptr (i64 1074786352 to i64*)
br label %22
22: ; preds = %17, %13
%23 = load i64, i64* %4
%24 = and i64 %23, 4
%25 = icmp ne i64 %24, 0
br i1 %25, label %26, label %31
26: ; preds = %22
%27 = load i64, i64* %3
%28 = trunc i64 %27 to i32
%29 = shl i32 1, %28
%30 = sext i32 %29 to i64
store volatile i64 %30, i64* inttoptr (i64 1074786360 to i64*)
br label %31
31: ; preds = %26, %22
%32 = load i64, i64* %4
%33 = and i64 %32, 8
%34 = icmp ne i64 %33, 0
br i1 %34, label %35, label %40
35: ; preds = %31
%36 = load i64, i64* %3
%37 = trunc i64 %36 to i32
%38 = shl i32 1, %37
%39 = sext i32 %38 to i64
store volatile i64 %39, i64* inttoptr (i64 1074786336 to i64*)
br label %40
40: ; preds = %35, %31
ret void
}

LLVM IR (-O2):
define void @uDMAChannelAttributeEnable(i64 %0, i64 %1) {
%3 = and i64 %1, 1
%4 = icmp eq i64 %3, 0
br i1 %4, label %9, label %5
5: ; preds = %2
%6 = trunc i64 %0 to i32
%7 = shl nuw i32 1, %6
%8 = sext i32 %7 to i64
store volatile i64 %8, i64* inttoptr (i64 1074786328 to i64*)
br label %9
9: ; preds = %5, %2
%10 = and i64 %1, 2
%11 = icmp eq i64 %10, 0
br i1 %11, label %16, label %12
12: ; preds = %9
%13 = trunc i64 %0 to i32
%14 = shl nuw i32 1, %13
%15 = sext i32 %14 to i64
store volatile i64 %15, i64* inttoptr (i64 1074786352 to i64*)
br label %16
16: ; preds = %12, %9
%17 = and i64 %1, 4
%18 = icmp eq i64 %17, 0
br i1 %18, label %23, label %19
19: ; preds = %16
%20 = trunc i64 %0 to i32
%21 = shl nuw i32 1, %20
%22 = sext i32 %21 to i64
store volatile i64 %22, i64* inttoptr (i64 1074786360 to i64*)
br label %23
23: ; preds = %19, %16
%24 = and i64 %1, 8
%25 = icmp eq i64 %24, 0
br i1 %25, label %30, label %26
26: ; preds = %23
%27 = trunc i64 %0 to i32
%28 = shl nuw i32 1, %27
%29 = sext i32 %28 to i64
store volatile i64 %29, i64* inttoptr (i64 1074786336 to i64*)
br label %30
30: ; preds = %26, %23
ret void
}