#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ IPCLiteMtoCDataRead(int, int, int, int);
int /*<<< orphan*/ IPCLiteMtoCSetBits_Protected(int, int, int, int, int);
unsigned char RAMControlInitM1MsgRam(void) {
  unsigned int ii = 0;
  IPCLiteMtoCSetBits_Protected(0x00000001, 0x4920, (0x0004 | 0x0010),
                               0x00000002, 0x80000000);
  while ((*((volatile unsigned long *)(0x400FB700 + 0x000000010))) & 0x00000001)
    ;
  if ((*((volatile unsigned long *)(0x400FB700 + 0x000000010))) & 0x80000000) {
    return 1;
  }
  do {
    IPCLiteMtoCDataRead(0x00000001, 0x4930, 0x00000002, 0x80000000);
    while ((*((volatile unsigned long *)(0x400FB700 + 0x000000010))) &
           0x00000001)
      ;
    if ((*((volatile unsigned long *)(0x400FB700 + 0x000000010))) &
        0x80000000) {
      return 1;
    } else {
      if ((*((volatile unsigned long *)(0x400FB700 + 0x00000003C))) &
          (0x0004 | 0x0010)) {
        return 0;
      } else {
        for (ii = 0; ii < 2048; ii++)
          ;
        continue;
      }
    }
  } while (1);
}


x86 assembly (clang, -O0):
<RAMControlInitM1MsgRam>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x8(%rbp)
mov    $0x1,%edi
mov    $0x4920,%esi
mov    $0x14,%edx
mov    $0x2,%ecx
mov    $0x80000000,%r8d
call   1030 <IPCLiteMtoCSetBits_Protected@plt>
mov    $0x400fb710,%eax
mov    (%rax),%rax
and    $0x1,%rax
cmp    $0x0,%rax
je     1169 <RAMControlInitM1MsgRam+0x49>
jmp    114e <RAMControlInitM1MsgRam+0x2e>
mov    $0x400fb710,%eax
mov    (%rax),%rax
movabs $0x80000000,%rcx
and    %rcx,%rax
cmp    $0x0,%rax
je     1191 <RAMControlInitM1MsgRam+0x71>
movb   $0x1,-0x1(%rbp)
jmp    124c <RAMControlInitM1MsgRam+0x12c>
jmp    1196 <RAMControlInitM1MsgRam+0x76>
mov    $0x1,%edi
mov    $0x4930,%esi
mov    $0x2,%edx
mov    $0x80000000,%ecx
call   1040 <IPCLiteMtoCDataRead@plt>
mov    $0x400fb710,%eax
mov    (%rax),%rax
and    $0x1,%rax
cmp    $0x0,%rax
je     11ca <RAMControlInitM1MsgRam+0xaa>
jmp    11af <RAMControlInitM1MsgRam+0x8f>
mov    $0x400fb710,%eax
mov    (%rax),%rax
movabs $0x80000000,%rcx
and    %rcx,%rax
cmp    $0x0,%rax
je     11f2 <RAMControlInitM1MsgRam+0xd2>
movb   $0x1,-0x1(%rbp)
jmp    124c <RAMControlInitM1MsgRam+0x12c>
mov    $0x400fb73c,%eax
mov    (%rax),%rax
and    $0x14,%rax
cmp    $0x0,%rax
je     1211 <RAMControlInitM1MsgRam+0xf1>
movb   $0x0,-0x1(%rbp)
jmp    124c <RAMControlInitM1MsgRam+0x12c>
movl   $0x0,-0x8(%rbp)
cmpl   $0x800,-0x8(%rbp)
jae    1238 <RAMControlInitM1MsgRam+0x118>
jmp    122a <RAMControlInitM1MsgRam+0x10a>
mov    -0x8(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x8(%rbp)
jmp    1218 <RAMControlInitM1MsgRam+0xf8>
jmp    123d <RAMControlInitM1MsgRam+0x11d>
mov    $0x1,%al
test   $0x1,%al
jne    1196 <RAMControlInitM1MsgRam+0x76>
jmp    124c <RAMControlInitM1MsgRam+0x12c>
movzbl -0x1(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<RAMControlInitM1MsgRam>:
push   %rbx
mov    $0x1,%edi
mov    $0x4920,%esi
mov    $0x14,%edx
mov    $0x2,%ecx
mov    $0x80000000,%r8d
call   1030 <IPCLiteMtoCSetBits_Protected@plt>
mov    0x400fb710,%rax
40
test   $0x1,%al
jne    1140 <RAMControlInitM1MsgRam+0x20>
mov    0x400fb710,%rax
40
and    $0x80000000,%eax
mov    $0x1,%bl
test   %rax,%rax
jne    11ae <RAMControlInitM1MsgRam+0x8e>
mov    $0x1,%edi
mov    $0x4930,%esi
mov    $0x2,%edx
mov    $0x80000000,%ecx
call   1040 <IPCLiteMtoCDataRead@plt>
nopl   0x0(%rax)
mov    0x400fb710,%rax
40
test   $0x1,%al
jne    1180 <RAMControlInitM1MsgRam+0x60>
mov    0x400fb710,%rax
40
and    $0x80000000,%eax
test   %rax,%rax
jne    11ae <RAMControlInitM1MsgRam+0x8e>
testq  $0x14,0x400fb73c
je     1160 <RAMControlInitM1MsgRam+0x40>
xor    %ebx,%ebx
mov    %ebx,%eax
pop    %rbx
ret

LLVM IR (-O0):
define zeroext i8 @RAMControlInitM1MsgRam() {
%1 = alloca i8
%2 = alloca i32
store i32 0, i32* %2
%3 = call i32 @IPCLiteMtoCSetBits_Protected(i32 1, i32 18720, i32 20, i32 2, i32 -2147483648)
br label %4
4: ; preds = %8, %0
%5 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%6 = and i64 %5, 1
%7 = icmp ne i64 %6, 0
br i1 %7, label %8, label %9
8: ; preds = %4
br label %4
9: ; preds = %4
%10 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%11 = and i64 %10, 2147483648
%12 = icmp ne i64 %11, 0
br i1 %12, label %13, label %14
13: ; preds = %9
store i8 1, i8* %1
br label %42
14: ; preds = %9
br label %15
15: ; preds = %41, %14
%16 = call i32 @IPCLiteMtoCDataRead(i32 1, i32 18736, i32 2, i32 -2147483648)
br label %17
17: ; preds = %21, %15
%18 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%19 = and i64 %18, 1
%20 = icmp ne i64 %19, 0
br i1 %20, label %21, label %22
21: ; preds = %17
br label %17
22: ; preds = %17
%23 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%24 = and i64 %23, 2147483648
%25 = icmp ne i64 %24, 0
br i1 %25, label %26, label %27
26: ; preds = %22
store i8 1, i8* %1
br label %42
27: ; preds = %22
%28 = load volatile i64, i64* inttoptr (i64 1074771772 to i64*)
%29 = and i64 %28, 20
%30 = icmp ne i64 %29, 0
br i1 %30, label %31, label %32
31: ; preds = %27
store i8 0, i8* %1
br label %42
32: ; preds = %27
store i32 0, i32* %2
br label %33
33: ; preds = %37, %32
%34 = load i32, i32* %2
%35 = icmp ult i32 %34, 2048
br i1 %35, label %36, label %40
36: ; preds = %33
br label %37
37: ; preds = %36
%38 = load i32, i32* %2
%39 = add i32 %38, 1
store i32 %39, i32* %2
br label %33
40: ; preds = %33
br label %41
41: ; preds = %40
br i1 true, label %15, label %42
42: ; preds = %13, %26, %31, %41
%43 = load i8, i8* %1
ret i8 %43
}

LLVM IR (-O2):
define zeroext i8 @RAMControlInitM1MsgRam() {
%1 = tail call i32 @IPCLiteMtoCSetBits_Protected(i32 1, i32 18720, i32 20, i32 2, i32 -2147483648)
br label %2
2: ; preds = %2, %0
%3 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%4 = and i64 %3, 1
%5 = icmp eq i64 %4, 0
br i1 %5, label %6, label %2
6: ; preds = %2
%7 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%8 = and i64 %7, 2147483648
%9 = icmp eq i64 %8, 0
br i1 %9, label %10, label %24
10: ; preds = %6, %20
%11 = tail call i32 @IPCLiteMtoCDataRead(i32 1, i32 18736, i32 2, i32 -2147483648)
br label %12
12: ; preds = %12, %10
%13 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%14 = and i64 %13, 1
%15 = icmp eq i64 %14, 0
br i1 %15, label %16, label %12
16: ; preds = %12
%17 = load volatile i64, i64* inttoptr (i64 1074771728 to i64*)
%18 = and i64 %17, 2147483648
%19 = icmp eq i64 %18, 0
br i1 %19, label %20, label %24
20: ; preds = %16
%21 = load volatile i64, i64* inttoptr (i64 1074771772 to i64*)
%22 = and i64 %21, 20
%23 = icmp eq i64 %22, 0
br i1 %23, label %10, label %24
24: ; preds = %20, %16, %6
%25 = phi i8 [ 1, %6 ], [ 0, %20 ], [ 1, %16 ]
ret i8 %25
}