#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(
    char const *);
int fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(
    const char *text) {
  int pos = 0;
  pos =
      fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(
          text);
  if (pos != -1)
    return pos;
  return -1;
}


x86 assembly (clang, -O0):
<fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
movl   $0x0,-0x14(%rbp)
mov    -0x10(%rbp),%rdi
call   1030 <fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0xffffffff,-0x14(%rbp)
je     1144 <fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122+0x34>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    114b <fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122+0x3b>
movl   $0xffffffff,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122>:
jmp    1030 <fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122@plt>

LLVM IR (-O0):
define i32 @fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(i8* %0) {
%2 = alloca i32
%3 = alloca i8*
%4 = alloca i32
store i8* %0, i8** %3
store i32 0, i32* %4
%5 = load i8*, i8** %3
%6 = call i32 @fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(i8* %5)
store i32 %6, i32* %4
%7 = load i32, i32* %4
%8 = icmp ne i32 %7, -1
br i1 %8, label %9, label %11
9: ; preds = %1
%10 = load i32, i32* %4
store i32 %10, i32* %2
br label %12
11: ; preds = %1
store i32 -1, i32* %2
br label %12
12: ; preds = %11, %9
%13 = load i32, i32* %2
ret i32 %13
}

LLVM IR (-O2):
define i32 @fn_al_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(i8* %0) {
%2 = tail call i32 @fn_sq_ch_64_al_sq_qtg_2_3_cl_65_91_97_122_qtg_0_3_sq_ch_45_qtg_3_3_cl_65_91_97_122_sq_qtg_4_4_cl_65_91_97_122_sq_qtg_5_8_cl_65_91_97_122_qtg_0_1_sq_ch_45_qtg_4_4_cl_65_91_97_122_qtg_0_1_al_sq_ch_45_qtg_2_2_cl_65_91_97_122_sq_qtg_3_3_cl_48_57_qtg_0_4294967295_al_sq_ch_45_qtg_5_8_cl_48_57_65_91_97_122_sq_cl_48_57_qtg_3_3_cl_48_57_65_91_97_122_qtg_0_4294967295_sq_ch_45_cl_48_57_65_87_89_90_97_119_121_122_qtg_1_4294967295_sq_ch_45_qtg_2_8_cl_48_57_65_91_97_122_qtg_0_1_sq_ch_45_ch_120_qtg_1_4294967295_sq_ch_45_qtg_1_8_cl_48_57_65_91_97_122(i8* %0)
ret i32 %2
}