int tc_rand_r(unsigned int *seed) {
  unsigned int next = *seed;
  int result;
  next *= 1103515245;
  next += 12345;
  result = (unsigned int)(next / 65536) % 2048;
  next *= 1103515245;
  next += 12345;
  result <<= 10;
  result ^= (unsigned int)(next / 65536) % 1024;
  next *= 1103515245;
  next += 12345;
  result <<= 10;
  result ^= (unsigned int)(next / 65536) % 1024;
  *seed = next;
  return result;
}


x86 assembly (clang, -O0):
<tc_rand_r>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    (%rax),%eax
mov    %eax,-0xc(%rbp)
imul   $0x41c64e6d,-0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x3039,%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
shr    $0x10,%eax
and    $0x7ff,%eax
mov    %eax,-0x10(%rbp)
imul   $0x41c64e6d,-0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x3039,%eax
mov    %eax,-0xc(%rbp)
mov    -0x10(%rbp),%eax
shl    $0xa,%eax
mov    %eax,-0x10(%rbp)
mov    -0xc(%rbp),%eax
shr    $0x10,%eax
and    $0x3ff,%eax
xor    -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
imul   $0x41c64e6d,-0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x3039,%eax
mov    %eax,-0xc(%rbp)
mov    -0x10(%rbp),%eax
shl    $0xa,%eax
mov    %eax,-0x10(%rbp)
mov    -0xc(%rbp),%eax
shr    $0x10,%eax
and    $0x3ff,%eax
xor    -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0xc(%rbp),%ecx
mov    -0x8(%rbp),%rax
mov    %ecx,(%rax)
mov    -0x10(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<tc_rand_r>:
imul   $0x41c64e6d,(%rdi),%eax
add    $0x3039,%eax
imul   $0x41c64e6d,%eax,%ecx
add    $0x3039,%ecx
shr    $0x6,%eax
and    $0x1ffc00,%eax
imul   $0x41c64e6d,%ecx,%edx
shr    $0x10,%ecx
and    $0x3ff,%ecx
or     %eax,%ecx
add    $0x3039,%edx
shl    $0xa,%ecx
mov    %edx,(%rdi)
mov    %edx,%eax
shr    $0x10,%eax
and    $0x3ff,%eax
or     %ecx,%eax
ret

LLVM IR (-O0):
define i32 @tc_rand_r(i32* %0) {
%2 = alloca i32*
%3 = alloca i32
%4 = alloca i32
store i32* %0, i32** %2
%5 = load i32*, i32** %2
%6 = load i32, i32* %5
store i32 %6, i32* %3
%7 = load i32, i32* %3
%8 = mul i32 %7, 1103515245
store i32 %8, i32* %3
%9 = load i32, i32* %3
%10 = add i32 %9, 12345
store i32 %10, i32* %3
%11 = load i32, i32* %3
%12 = udiv i32 %11, 65536
%13 = urem i32 %12, 2048
store i32 %13, i32* %4
%14 = load i32, i32* %3
%15 = mul i32 %14, 1103515245
store i32 %15, i32* %3
%16 = load i32, i32* %3
%17 = add i32 %16, 12345
store i32 %17, i32* %3
%18 = load i32, i32* %4
%19 = shl i32 %18, 10
store i32 %19, i32* %4
%20 = load i32, i32* %3
%21 = udiv i32 %20, 65536
%22 = urem i32 %21, 1024
%23 = load i32, i32* %4
%24 = xor i32 %23, %22
store i32 %24, i32* %4
%25 = load i32, i32* %3
%26 = mul i32 %25, 1103515245
store i32 %26, i32* %3
%27 = load i32, i32* %3
%28 = add i32 %27, 12345
store i32 %28, i32* %3
%29 = load i32, i32* %4
%30 = shl i32 %29, 10
store i32 %30, i32* %4
%31 = load i32, i32* %3
%32 = udiv i32 %31, 65536
%33 = urem i32 %32, 1024
%34 = load i32, i32* %4
%35 = xor i32 %34, %33
store i32 %35, i32* %4
%36 = load i32, i32* %3
%37 = load i32*, i32** %2
store i32 %36, i32* %37
%38 = load i32, i32* %4
ret i32 %38
}

LLVM IR (-O2):
define i32 @tc_rand_r(i32* nocapture %0) {
%2 = load i32, i32* %0
%3 = mul i32 %2, 1103515245
%4 = add i32 %3, 12345
%5 = mul i32 %4, 1103515245
%6 = add i32 %5, 12345
%7 = lshr i32 %4, 6
%8 = and i32 %7, 2096128
%9 = lshr i32 %6, 16
%10 = and i32 %9, 1023
%11 = or i32 %10, %8
%12 = mul i32 %6, 1103515245
%13 = add i32 %12, 12345
%14 = shl nuw nsw i32 %11, 10
%15 = lshr i32 %13, 16
%16 = and i32 %15, 1023
%17 = or i32 %14, %16
store i32 %13, i32* %0
ret i32 %17
}