void nand_addr(unsigned long addr) {
  unsigned int col = addr % 2048;
  unsigned int page = addr / 2048;
  volatile char i = 0;
  (*(volatile unsigned char *)0x7020000C) = col & 0xFF;
  for (i = 0; i < 10; i++)
    ;
  (*(volatile unsigned char *)0x7020000C) = (col >> 8) & 0xFF;
  for (i = 0; i < 10; i++)
    ;
  (*(volatile unsigned char *)0x7020000C) = page & 0xFF;
  for (i = 0; i < 10; i++)
    ;
  (*(volatile unsigned char *)0x7020000C) = (page >> 8) & 0xFF;
  for (i = 0; i < 10; i++)
    ;
  (*(volatile unsigned char *)0x7020000C) = (page >> 16) & 0xFF;
  for (i = 0; i < 10; i++)
    ;
}


x86 assembly (clang, -O0):
<nand_addr>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
and    $0x7ff,%rax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%rax
shr    $0xb,%rax
mov    %eax,-0x10(%rbp)
movb   $0x0,-0x11(%rbp)
mov    -0xc(%rbp),%eax
and    $0xff,%eax
mov    %al,%cl
mov    $0x7020000c,%eax
mov    %cl,(%rax)
movb   $0x0,-0x11(%rbp)
mov    -0x11(%rbp),%al
movsbl %al,%eax
cmp    $0xa,%eax
jge    115a <nand_addr+0x5a>
jmp    114d <nand_addr+0x4d>
mov    -0x11(%rbp),%al
add    $0x1,%al
mov    %al,-0x11(%rbp)
jmp    1139 <nand_addr+0x39>
mov    -0xc(%rbp),%eax
shr    $0x8,%eax
and    $0xff,%eax
mov    %al,%cl
mov    $0x7020000c,%eax
mov    %cl,(%rax)
movb   $0x0,-0x11(%rbp)
mov    -0x11(%rbp),%al
movsbl %al,%eax
cmp    $0xa,%eax
jge    1193 <nand_addr+0x93>
jmp    1186 <nand_addr+0x86>
mov    -0x11(%rbp),%al
add    $0x1,%al
mov    %al,-0x11(%rbp)
jmp    1172 <nand_addr+0x72>
mov    -0x10(%rbp),%eax
and    $0xff,%eax
mov    %al,%cl
mov    $0x7020000c,%eax
mov    %cl,(%rax)
movb   $0x0,-0x11(%rbp)
mov    -0x11(%rbp),%al
movsbl %al,%eax
cmp    $0xa,%eax
jge    11c9 <nand_addr+0xc9>
jmp    11bc <nand_addr+0xbc>
mov    -0x11(%rbp),%al
add    $0x1,%al
mov    %al,-0x11(%rbp)
jmp    11a8 <nand_addr+0xa8>
mov    -0x10(%rbp),%eax
shr    $0x8,%eax
and    $0xff,%eax
mov    %al,%cl
mov    $0x7020000c,%eax
mov    %cl,(%rax)
movb   $0x0,-0x11(%rbp)
mov    -0x11(%rbp),%al
movsbl %al,%eax
cmp    $0xa,%eax
jge    1202 <nand_addr+0x102>
jmp    11f5 <nand_addr+0xf5>
mov    -0x11(%rbp),%al
add    $0x1,%al
mov    %al,-0x11(%rbp)
jmp    11e1 <nand_addr+0xe1>
mov    -0x10(%rbp),%eax
shr    $0x10,%eax
and    $0xff,%eax
mov    %al,%cl
mov    $0x7020000c,%eax
mov    %cl,(%rax)
movb   $0x0,-0x11(%rbp)
mov    -0x11(%rbp),%al
movsbl %al,%eax
cmp    $0xa,%eax
jge    123b <nand_addr+0x13b>
jmp    122e <nand_addr+0x12e>
mov    -0x11(%rbp),%al
add    $0x1,%al
mov    %al,-0x11(%rbp)
jmp    121a <nand_addr+0x11a>
pop    %rbp
ret

x86 assembly (clang, -O2):
<nand_addr>:
movb   $0x0,-0x1(%rsp)
mov    %dil,0x7020000c
70
movb   $0x0,-0x1(%rsp)
mov    -0x1(%rsp),%al
cmp    $0x9,%al
jg     112e <nand_addr+0x2e>
nopw   0x0(%rax,%rax,1)
addb   $0x1,-0x1(%rsp)
movzbl -0x1(%rsp),%eax
cmp    $0xa,%al
jl     1120 <nand_addr+0x20>
mov    %rdi,%rax
shr    $0xb,%rax
mov    %rdi,%rcx
shr    $0x8,%rcx
and    $0x7,%cl
mov    %cl,0x7020000c
movb   $0x0,-0x1(%rsp)
mov    -0x1(%rsp),%cl
cmp    $0x9,%cl
jg     116f <nand_addr+0x6f>
cs nopw 0x0(%rax,%rax,1)
xchg   %ax,%ax
addb   $0x1,-0x1(%rsp)
movzbl -0x1(%rsp),%ecx
cmp    $0xa,%cl
jl     1160 <nand_addr+0x60>
mov    %al,0x7020000c
movb   $0x0,-0x1(%rsp)
mov    -0x1(%rsp),%al
cmp    $0x9,%al
jg     119e <nand_addr+0x9e>
cs nopw 0x0(%rax,%rax,1)
nopl   (%rax)
addb   $0x1,-0x1(%rsp)
movzbl -0x1(%rsp),%eax
cmp    $0xa,%al
jl     1190 <nand_addr+0x90>
mov    %rdi,%rax
shr    $0x13,%rax
mov    %al,0x7020000c
movb   $0x0,-0x1(%rsp)
mov    -0x1(%rsp),%al
cmp    $0x9,%al
jg     11ce <nand_addr+0xce>
nopl   0x0(%rax)
addb   $0x1,-0x1(%rsp)
movzbl -0x1(%rsp),%eax
cmp    $0xa,%al
jl     11c0 <nand_addr+0xc0>
shr    $0x1b,%rdi
mov    %dil,0x7020000c
70
movb   $0x0,-0x1(%rsp)
mov    -0x1(%rsp),%al
cmp    $0x9,%al
jg     11fe <nand_addr+0xfe>
nopw   0x0(%rax,%rax,1)
addb   $0x1,-0x1(%rsp)
movzbl -0x1(%rsp),%eax
cmp    $0xa,%al
jl     11f0 <nand_addr+0xf0>
ret

LLVM IR (-O0):
define void @nand_addr(i64 %0) {
%2 = alloca i64
%3 = alloca i32
%4 = alloca i32
%5 = alloca i8
store i64 %0, i64* %2
%6 = load i64, i64* %2
%7 = urem i64 %6, 2048
%8 = trunc i64 %7 to i32
store i32 %8, i32* %3
%9 = load i64, i64* %2
%10 = udiv i64 %9, 2048
%11 = trunc i64 %10 to i32
store i32 %11, i32* %4
store volatile i8 0, i8* %5
%12 = load i32, i32* %3
%13 = and i32 %12, 255
%14 = trunc i32 %13 to i8
store volatile i8 %14, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %5
br label %15
15: ; preds = %20, %1
%16 = load volatile i8, i8* %5
%17 = sext i8 %16 to i32
%18 = icmp slt i32 %17, 10
br i1 %18, label %19, label %23
19: ; preds = %15
br label %20
20: ; preds = %19
%21 = load volatile i8, i8* %5
%22 = add i8 %21, 1
store volatile i8 %22, i8* %5
br label %15
23: ; preds = %15
%24 = load i32, i32* %3
%25 = lshr i32 %24, 8
%26 = and i32 %25, 255
%27 = trunc i32 %26 to i8
store volatile i8 %27, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %5
br label %28
28: ; preds = %33, %23
%29 = load volatile i8, i8* %5
%30 = sext i8 %29 to i32
%31 = icmp slt i32 %30, 10
br i1 %31, label %32, label %36
32: ; preds = %28
br label %33
33: ; preds = %32
%34 = load volatile i8, i8* %5
%35 = add i8 %34, 1
store volatile i8 %35, i8* %5
br label %28
36: ; preds = %28
%37 = load i32, i32* %4
%38 = and i32 %37, 255
%39 = trunc i32 %38 to i8
store volatile i8 %39, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %5
br label %40
40: ; preds = %45, %36
%41 = load volatile i8, i8* %5
%42 = sext i8 %41 to i32
%43 = icmp slt i32 %42, 10
br i1 %43, label %44, label %48
44: ; preds = %40
br label %45
45: ; preds = %44
%46 = load volatile i8, i8* %5
%47 = add i8 %46, 1
store volatile i8 %47, i8* %5
br label %40
48: ; preds = %40
%49 = load i32, i32* %4
%50 = lshr i32 %49, 8
%51 = and i32 %50, 255
%52 = trunc i32 %51 to i8
store volatile i8 %52, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %5
br label %53
53: ; preds = %58, %48
%54 = load volatile i8, i8* %5
%55 = sext i8 %54 to i32
%56 = icmp slt i32 %55, 10
br i1 %56, label %57, label %61
57: ; preds = %53
br label %58
58: ; preds = %57
%59 = load volatile i8, i8* %5
%60 = add i8 %59, 1
store volatile i8 %60, i8* %5
br label %53
61: ; preds = %53
%62 = load i32, i32* %4
%63 = lshr i32 %62, 16
%64 = and i32 %63, 255
%65 = trunc i32 %64 to i8
store volatile i8 %65, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %5
br label %66
66: ; preds = %71, %61
%67 = load volatile i8, i8* %5
%68 = sext i8 %67 to i32
%69 = icmp slt i32 %68, 10
br i1 %69, label %70, label %74
70: ; preds = %66
br label %71
71: ; preds = %70
%72 = load volatile i8, i8* %5
%73 = add i8 %72, 1
store volatile i8 %73, i8* %5
br label %66
74: ; preds = %66
ret void
}

LLVM IR (-O2):
define void @nand_addr(i64 %0) {
%2 = alloca i8
%3 = lshr i64 %0, 11
store volatile i8 0, i8* %2
%4 = trunc i64 %0 to i8
store volatile i8 %4, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %2
%5 = load volatile i8, i8* %2
%6 = icmp slt i8 %5, 10
br i1 %6, label %7, label %12
7: ; preds = %1, %7
%8 = load volatile i8, i8* %2
%9 = add i8 %8, 1
store volatile i8 %9, i8* %2
%10 = load volatile i8, i8* %2
%11 = icmp slt i8 %10, 10
br i1 %11, label %7, label %12
12: ; preds = %7, %1
%13 = lshr i64 %0, 8
%14 = trunc i64 %13 to i8
%15 = and i8 %14, 7
store volatile i8 %15, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %2
%16 = load volatile i8, i8* %2
%17 = icmp slt i8 %16, 10
br i1 %17, label %18, label %23
18: ; preds = %12, %18
%19 = load volatile i8, i8* %2
%20 = add i8 %19, 1
store volatile i8 %20, i8* %2
%21 = load volatile i8, i8* %2
%22 = icmp slt i8 %21, 10
br i1 %22, label %18, label %23
23: ; preds = %18, %12
%24 = trunc i64 %3 to i8
store volatile i8 %24, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %2
%25 = load volatile i8, i8* %2
%26 = icmp slt i8 %25, 10
br i1 %26, label %27, label %32
27: ; preds = %23, %27
%28 = load volatile i8, i8* %2
%29 = add i8 %28, 1
store volatile i8 %29, i8* %2
%30 = load volatile i8, i8* %2
%31 = icmp slt i8 %30, 10
br i1 %31, label %27, label %32
32: ; preds = %27, %23
%33 = lshr i64 %0, 19
%34 = trunc i64 %33 to i8
store volatile i8 %34, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %2
%35 = load volatile i8, i8* %2
%36 = icmp slt i8 %35, 10
br i1 %36, label %37, label %42
37: ; preds = %32, %37
%38 = load volatile i8, i8* %2
%39 = add i8 %38, 1
store volatile i8 %39, i8* %2
%40 = load volatile i8, i8* %2
%41 = icmp slt i8 %40, 10
br i1 %41, label %37, label %42
42: ; preds = %37, %32
%43 = lshr i64 %0, 27
%44 = trunc i64 %43 to i8
store volatile i8 %44, i8* inttoptr (i64 1881145356 to i8*)
store volatile i8 0, i8* %2
%45 = load volatile i8, i8* %2
%46 = icmp slt i8 %45, 10
br i1 %46, label %47, label %52
47: ; preds = %42, %47
%48 = load volatile i8, i8* %2
%49 = add i8 %48, 1
store volatile i8 %49, i8* %2
%50 = load volatile i8, i8* %2
%51 = icmp slt i8 %50, 10
br i1 %51, label %47, label %52
52: ; preds = %47, %42
ret void
}