void sync_barrier(int nprocs) {
  static volatile int _count;
  static volatile int _sense;
  static __thread volatile int _local_sense;
  int sense = !_local_sense;
  if (__sync_fetch_and_add(&(_count), 1) == nprocs - 1) {
    _count = 0;
    _sense = sense;
  }
  while (_sense != sense)
    ;
  _local_sense = sense;
  __sync_synchronize();
}


x86 assembly (clang, -O0):
<sync_barrier>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
lea    0x2eae(%rip),%rdi
call   1030 <__tls_get_addr@plt>
mov    0x0(%rax),%eax
test   %eax,%eax
sete   %al
movzbl %al,%eax
mov    %eax,-0x8(%rbp)
mov    $0x1,%eax
lock xadd %eax,0x2ee7(%rip)
mov    -0x4(%rbp),%ecx
sub    $0x1,%ecx
cmp    %ecx,%eax
jne    1166 <sync_barrier+0x56>
movl   $0x0,0x2ecf(%rip)
mov    -0x8(%rbp),%eax
mov    %eax,0x2eca(%rip)
jmp    116b <sync_barrier+0x5b>
mov    0x2ebf(%rip),%eax
cmp    -0x8(%rbp),%eax
je     117f <sync_barrier+0x6f>
jmp    116b <sync_barrier+0x5b>
mov    -0x8(%rbp),%eax
mov    %eax,-0xc(%rbp)
lea    0x2e44(%rip),%rdi
call   1030 <__tls_get_addr@plt>
mov    -0xc(%rbp),%ecx
mov    %ecx,0x0(%rax)
mfence
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sync_barrier>:
push   %rbx
mov    %edi,%ebx
lea    0x2eb6(%rip),%rdi
call   1030 <__tls_get_addr@plt>
xor    %ecx,%ecx
cmpl   $0x0,0x0(%rax)
sete   %cl
mov    $0x1,%edx
lock xadd %edx,0x2ef4(%rip)
add    $0xffffffff,%ebx
cmp    %ebx,%edx
jne    1150 <sync_barrier+0x40>
movl   $0x0,0x2ee3(%rip)
mov    %ecx,0x2ee1(%rip)
nop
mov    0x2eda(%rip),%edx
cmp    %ecx,%edx
jne    1150 <sync_barrier+0x40>
mov    %ecx,0x0(%rax)
mfence
pop    %rbx
ret

LLVM IR (-O0):
@sync_barrier._count = internal global i32 0
@sync_barrier._sense = internal global i32 0
@sync_barrier._local_sense = internal thread_local global i32 0
define void @sync_barrier(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %2
%4 = load volatile i32, i32* @sync_barrier._local_sense
%5 = icmp ne i32 %4, 0
%6 = xor i1 %5, true
%7 = zext i1 %6 to i32
store i32 %7, i32* %3
%8 = atomicrmw add i32* @sync_barrier._count, i32 1 seq_cst
%9 = load i32, i32* %2
%10 = sub nsw i32 %9, 1
%11 = icmp eq i32 %8, %10
br i1 %11, label %12, label %14
12: ; preds = %1
store volatile i32 0, i32* @sync_barrier._count
%13 = load i32, i32* %3
store volatile i32 %13, i32* @sync_barrier._sense
br label %14
14: ; preds = %12, %1
br label %15
15: ; preds = %19, %14
%16 = load volatile i32, i32* @sync_barrier._sense
%17 = load i32, i32* %3
%18 = icmp ne i32 %16, %17
br i1 %18, label %19, label %20
19: ; preds = %15
br label %15
20: ; preds = %15
%21 = load i32, i32* %3
store volatile i32 %21, i32* @sync_barrier._local_sense
fence seq_cst
ret void
}

LLVM IR (-O2):
@sync_barrier._count = internal global i32 0
@sync_barrier._sense = internal global i32 0
@sync_barrier._local_sense = internal thread_local global i32 0
define void @sync_barrier(i32 %0) {
%2 = load volatile i32, i32* @sync_barrier._local_sense
%3 = icmp eq i32 %2, 0
%4 = zext i1 %3 to i32
%5 = atomicrmw add i32* @sync_barrier._count, i32 1 seq_cst
%6 = add nsw i32 %0, -1
%7 = icmp eq i32 %5, %6
br i1 %7, label %8, label %9
8: ; preds = %1
store volatile i32 0, i32* @sync_barrier._count
store volatile i32 %4, i32* @sync_barrier._sense
br label %9
9: ; preds = %8, %1
br label %10
10: ; preds = %9, %10
%11 = load volatile i32, i32* @sync_barrier._sense
%12 = icmp eq i32 %11, %4
br i1 %12, label %13, label %10
13: ; preds = %10
store volatile i32 %4, i32* @sync_barrier._local_sense
fence seq_cst
ret void
}