unsigned long shift_32_bit_feedback_register() {
  static unsigned long register_32 = 1;
  unsigned long new_bit;
  new_bit = (register_32 & 0x01) ^ ((register_32 & 0x02) >> 1) ^
            ((register_32 & 0x04) >> 2) ^ ((register_32 & 0x08) >> 3);
  new_bit = new_bit ^ ((register_32 & 0x20) >> 5) ^ ((register_32 & 0x80) >> 7);
  register_32 = register_32 >> 1;
  register_32 = register_32 | (new_bit << 31);
  return (register_32);
}


x86 assembly (clang, -O0):
<shift_32_bit_feedback_register>:
push   %rbp
mov    %rsp,%rbp
mov    0x2f15(%rip),%rax
and    $0x1,%rax
mov    0x2f0a(%rip),%rcx
and    $0x2,%rcx
shr    $0x1,%rcx
xor    %rcx,%rax
mov    0x2ef8(%rip),%rcx
and    $0x4,%rcx
shr    $0x2,%rcx
xor    %rcx,%rax
mov    0x2ee6(%rip),%rcx
and    $0x8,%rcx
shr    $0x3,%rcx
xor    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    0x2ecc(%rip),%rcx
and    $0x20,%rcx
shr    $0x5,%rcx
xor    %rcx,%rax
mov    0x2eba(%rip),%rcx
and    $0x80,%rcx
shr    $0x7,%rcx
xor    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    0x2ea1(%rip),%rax
shr    $0x1,%rax
mov    %rax,0x2e96(%rip)
mov    0x2e8f(%rip),%rax
mov    -0x8(%rbp),%rcx
shl    $0x1f,%rcx
or     %rcx,%rax
mov    %rax,0x2e7d(%rip)
mov    0x2e76(%rip),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<shift_32_bit_feedback_register>:
mov    0x2f19(%rip),%rax
mov    %rax,%rcx
shr    %rcx
mov    %ecx,%edx
xor    %eax,%edx
mov    %eax,%esi
shr    $0x2,%esi
mov    %eax,%edi
shr    $0x3,%edi
xor    %esi,%edi
xor    %edx,%edi
mov    %eax,%edx
shr    $0x5,%edx
shr    $0x7,%eax
xor    %edx,%eax
xor    %edi,%eax
shl    $0x1f,%eax
or     %rcx,%rax
mov    %rax,0x2ee8(%rip)
ret

LLVM IR (-O0):
@shift_32_bit_feedback_register.register_32 = internal global i64 1
define i64 @shift_32_bit_feedback_register() {
%1 = alloca i64
%2 = load i64, i64* @shift_32_bit_feedback_register.register_32
%3 = and i64 %2, 1
%4 = load i64, i64* @shift_32_bit_feedback_register.register_32
%5 = and i64 %4, 2
%6 = lshr i64 %5, 1
%7 = xor i64 %3, %6
%8 = load i64, i64* @shift_32_bit_feedback_register.register_32
%9 = and i64 %8, 4
%10 = lshr i64 %9, 2
%11 = xor i64 %7, %10
%12 = load i64, i64* @shift_32_bit_feedback_register.register_32
%13 = and i64 %12, 8
%14 = lshr i64 %13, 3
%15 = xor i64 %11, %14
store i64 %15, i64* %1
%16 = load i64, i64* %1
%17 = load i64, i64* @shift_32_bit_feedback_register.register_32
%18 = and i64 %17, 32
%19 = lshr i64 %18, 5
%20 = xor i64 %16, %19
%21 = load i64, i64* @shift_32_bit_feedback_register.register_32
%22 = and i64 %21, 128
%23 = lshr i64 %22, 7
%24 = xor i64 %20, %23
store i64 %24, i64* %1
%25 = load i64, i64* @shift_32_bit_feedback_register.register_32
%26 = lshr i64 %25, 1
store i64 %26, i64* @shift_32_bit_feedback_register.register_32
%27 = load i64, i64* @shift_32_bit_feedback_register.register_32
%28 = load i64, i64* %1
%29 = shl i64 %28, 31
%30 = or i64 %27, %29
store i64 %30, i64* @shift_32_bit_feedback_register.register_32
%31 = load i64, i64* @shift_32_bit_feedback_register.register_32
ret i64 %31
}

LLVM IR (-O2):
@shift_32_bit_feedback_register.register_32 = internal unnamed_addr global i64 1
define i64 @shift_32_bit_feedback_register() {
%1 = load i64, i64* @shift_32_bit_feedback_register.register_32
%2 = lshr i64 %1, 1
%3 = xor i64 %2, %1
%4 = lshr i64 %1, 2
%5 = xor i64 %3, %4
%6 = lshr i64 %1, 3
%7 = xor i64 %5, %6
%8 = lshr i64 %1, 5
%9 = xor i64 %7, %8
%10 = lshr i64 %1, 7
%11 = xor i64 %9, %10
%12 = shl i64 %11, 31
%13 = and i64 %12, 2147483648
%14 = or i64 %13, %2
store i64 %14, i64* @shift_32_bit_feedback_register.register_32
ret i64 %14
}