double SIM_power_draincap(width, nchannel, stack)
double width;
int nchannel;
int stack;
{
  double Cdiffside, Cdiffarea, Coverlap, cap;
  double overlapCap;
  double swAreaUnderGate;
  double area_peri;
  double diffArea;
  double diffPeri;
  double l = 0.4 * 0.0875;
  diffArea = l * width;
  diffPeri = 2 * l + 2 * width;
  Cdiffside = (nchannel) ? (2.750000e-16) : (2.750000e-16);
  Cdiffarea = (nchannel) ? (1.370000e-16) : (3.430000e-16);
  Coverlap = (nchannel) ? ((1.380000e-16) + (2.630000e-16))
                        : ((1.380000e-16) + (3.380000e-16));
  if (width >= 10) {
    cap = 3.0 * (0.8 * 0.0875) * width / 2.0 * Cdiffarea +
          6.0 * (0.8 * 0.0875) * Cdiffside + width * Coverlap;
    cap += (double)(stack - 1) *
           ((0.8 * 0.0875) * width * Cdiffarea +
            4.0 * (0.8 * 0.0875) * Cdiffside + 2.0 * width * Coverlap);
  } else {
    cap = 3.0 * (0.8 * 0.0875) * width * Cdiffarea +
          (6.0 * (0.8 * 0.0875) + width) * Cdiffside + width * Coverlap;
    cap += (double)(stack - 1) *
           ((0.8 * 0.0875) * width * Cdiffarea +
            2.0 * (0.8 * 0.0875) * Cdiffside + 2.0 * width * Coverlap);
  }
  return (cap);
}


x86 assembly (clang, -O0):
<SIM_power_draincap>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movsd  %xmm0,-0x8(%rbp)
mov    %edi,-0xc(%rbp)
mov    %esi,-0x10(%rbp)
movsd  0xf1d(%rip),%xmm0
movsd  %xmm0,-0x60(%rbp)
movsd  -0x60(%rbp),%xmm0
mulsd  -0x8(%rbp),%xmm0
movsd  %xmm0,-0x50(%rbp)
movsd  -0x60(%rbp),%xmm0
movsd  0xef4(%rip),%xmm1
mulsd  -0x8(%rbp),%xmm1
addsd  %xmm0,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x58(%rbp)
mov    -0xc(%rbp),%eax
movsd  0xecf(%rip),%xmm0
movsd  %xmm0,-0x70(%rbp)
cmp    $0x0,%eax
movsd  %xmm0,-0x68(%rbp)
jne    1176 <SIM_power_draincap+0x76>
movsd  -0x70(%rbp),%xmm0
movsd  %xmm0,-0x68(%rbp)
movsd  -0x68(%rbp),%xmm0
movsd  %xmm0,-0x18(%rbp)
mov    -0xc(%rbp),%eax
movsd  0xe8d(%rip),%xmm0
movsd  0xe8d(%rip),%xmm1
movsd  %xmm1,-0x80(%rbp)
cmp    $0x0,%eax
movsd  %xmm0,-0x78(%rbp)
jne    11b0 <SIM_power_draincap+0xb0>
movsd  -0x80(%rbp),%xmm0
movsd  %xmm0,-0x78(%rbp)
movsd  -0x78(%rbp),%xmm0
movsd  %xmm0,-0x20(%rbp)
mov    -0xc(%rbp),%eax
movsd  0xe43(%rip),%xmm0
movsd  0xe43(%rip),%xmm1
movsd  %xmm1,-0x90(%rbp)
ff
cmp    $0x0,%eax
movsd  %xmm0,-0x88(%rbp)
ff
jne    11f6 <SIM_power_draincap+0xf6>
movsd  -0x90(%rbp),%xmm0
ff
movsd  %xmm0,-0x88(%rbp)
ff
movsd  -0x88(%rbp),%xmm0
ff
movsd  %xmm0,-0x28(%rbp)
movsd  -0x8(%rbp),%xmm0
movsd  0xdf0(%rip),%xmm1
ucomisd %xmm1,%xmm0
jb     12c6 <SIM_power_draincap+0x1c6>
movsd  0xe36(%rip),%xmm1
mulsd  -0x8(%rbp),%xmm1
movsd  0xe01(%rip),%xmm0
divsd  %xmm0,%xmm1
movsd  -0x20(%rbp),%xmm2
movsd  0xe10(%rip),%xmm0
mulsd  -0x18(%rbp),%xmm0
mulsd  %xmm2,%xmm1
addsd  %xmm0,%xmm1
movsd  -0x8(%rbp),%xmm0
movsd  -0x28(%rbp),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
mov    -0x10(%rbp),%eax
sub    $0x1,%eax
cvtsi2sd %eax,%xmm0
movsd  0xdd2(%rip),%xmm1
mulsd  -0x8(%rbp),%xmm1
movsd  -0x20(%rbp),%xmm3
movsd  0xdd8(%rip),%xmm2
mulsd  -0x18(%rbp),%xmm2
mulsd  %xmm3,%xmm1
addsd  %xmm2,%xmm1
movsd  0xd93(%rip),%xmm2
mulsd  -0x8(%rbp),%xmm2
movsd  -0x28(%rbp),%xmm3
mulsd  %xmm3,%xmm2
addsd  %xmm1,%xmm2
movsd  -0x30(%rbp),%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
jmp    1366 <SIM_power_draincap+0x266>
movsd  0xd8a(%rip),%xmm1
mulsd  -0x8(%rbp),%xmm1
movsd  -0x20(%rbp),%xmm2
movsd  0xd70(%rip),%xmm0
addsd  -0x8(%rbp),%xmm0
mulsd  -0x18(%rbp),%xmm0
mulsd  %xmm2,%xmm1
addsd  %xmm0,%xmm1
movsd  -0x8(%rbp),%xmm0
movsd  -0x28(%rbp),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
mov    -0x10(%rbp),%eax
sub    $0x1,%eax
cvtsi2sd %eax,%xmm0
movsd  0xd2d(%rip),%xmm1
mulsd  -0x8(%rbp),%xmm1
movsd  -0x20(%rbp),%xmm3
movsd  0xd13(%rip),%xmm2
mulsd  -0x18(%rbp),%xmm2
mulsd  %xmm3,%xmm1
addsd  %xmm2,%xmm1
movsd  0xcee(%rip),%xmm2
mulsd  -0x8(%rbp),%xmm2
movsd  -0x28(%rbp),%xmm3
mulsd  %xmm3,%xmm2
addsd  %xmm1,%xmm2
movsd  -0x30(%rbp),%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
movsd  -0x30(%rbp),%xmm0
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<SIM_power_draincap>:
movapd %xmm0,%xmm1
addsd  %xmm0,%xmm0
xor    %eax,%eax
test   %edi,%edi
sete   %al
lea    0xeea(%rip),%rcx
movsd  (%rcx,%rax,8),%xmm3
ucomisd 0xefd(%rip),%xmm1
lea    0xee6(%rip),%rcx
movsd  (%rcx,%rax,8),%xmm2
movsd  0xef1(%rip),%xmm4
mulsd  %xmm1,%xmm4
jae    1182 <SIM_power_draincap+0x82>
movsd  0xf0b(%rip),%xmm5
addsd  %xmm1,%xmm5
mulsd  0xf07(%rip),%xmm5
mulsd  %xmm3,%xmm4
addsd  %xmm5,%xmm4
movapd %xmm1,%xmm5
mulsd  %xmm2,%xmm5
add    $0xffffffff,%esi
cvtsi2sd %esi,%xmm6
mulsd  0xed0(%rip),%xmm1
addsd  %xmm4,%xmm5
mulsd  %xmm3,%xmm1
addsd  0xee0(%rip),%xmm1
jmp    11bd <SIM_power_draincap+0xbd>
mulsd  0xea6(%rip),%xmm4
mulsd  %xmm3,%xmm4
addsd  0xea2(%rip),%xmm4
movapd %xmm1,%xmm5
mulsd  %xmm2,%xmm5
add    $0xffffffff,%esi
cvtsi2sd %esi,%xmm6
mulsd  0xe93(%rip),%xmm1
addsd  %xmm4,%xmm5
mulsd  %xmm3,%xmm1
addsd  0xe8b(%rip),%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
mulsd  %xmm6,%xmm0
addsd  %xmm5,%xmm0
ret

LLVM IR (-O0):
define double @SIM_power_draincap(double %0, i32 %1, i32 %2) {
%4 = alloca double
%5 = alloca i32
%6 = alloca i32
%7 = alloca double
%8 = alloca double
%9 = alloca double
%10 = alloca double
%11 = alloca double
%12 = alloca double
%13 = alloca double
%14 = alloca double
%15 = alloca double
%16 = alloca double
store double %0, double* %4
store i32 %1, i32* %5
store i32 %2, i32* %6
store double 0x3FA1EB851EB851EB, double* %16
%17 = load double, double* %16
%18 = load double, double* %4
%19 = fmul double %17, %18
store double %19, double* %14
%20 = load double, double* %16
%21 = load double, double* %4
%22 = fmul double 2.000000e+00, %21
%23 = call double @llvm.fmuladd.f64(double 2.000000e+00, double %20, double %22)
store double %23, double* %15
%24 = load i32, i32* %5
%25 = icmp ne i32 %24, 0
%26 = zext i1 %25 to i64
%27 = select i1 %25, double 2.750000e-16, double 2.750000e-16
store double %27, double* %7
%28 = load i32, i32* %5
%29 = icmp ne i32 %28, 0
%30 = zext i1 %29 to i64
%31 = select i1 %29, double 1.370000e-16, double 3.430000e-16
store double %31, double* %8
%32 = load i32, i32* %5
%33 = icmp ne i32 %32, 0
%34 = zext i1 %33 to i64
%35 = select i1 %33, double 4.010000e-16, double 4.760000e-16
store double %35, double* %9
%36 = load double, double* %4
%37 = fcmp oge double %36, 1.000000e+01
br i1 %37, label %38, label %64
38: ; preds = %3
%39 = load double, double* %4
%40 = fmul double 0x3FCAE147AE147AE0, %39
%41 = fdiv double %40, 2.000000e+00
%42 = load double, double* %8
%43 = load double, double* %7
%44 = fmul double 0x3FDAE147AE147AE0, %43
%45 = call double @llvm.fmuladd.f64(double %41, double %42, double %44)
%46 = load double, double* %4
%47 = load double, double* %9
%48 = call double @llvm.fmuladd.f64(double %46, double %47, double %45)
store double %48, double* %10
%49 = load i32, i32* %6
%50 = sub nsw i32 %49, 1
%51 = sitofp i32 %50 to double
%52 = load double, double* %4
%53 = fmul double 0x3FB1EB851EB851EB, %52
%54 = load double, double* %8
%55 = load double, double* %7
%56 = fmul double 0x3FD1EB851EB851EB, %55
%57 = call double @llvm.fmuladd.f64(double %53, double %54, double %56)
%58 = load double, double* %4
%59 = fmul double 2.000000e+00, %58
%60 = load double, double* %9
%61 = call double @llvm.fmuladd.f64(double %59, double %60, double %57)
%62 = load double, double* %10
%63 = call double @llvm.fmuladd.f64(double %51, double %61, double %62)
store double %63, double* %10
br label %91
64: ; preds = %3
%65 = load double, double* %4
%66 = fmul double 0x3FCAE147AE147AE0, %65
%67 = load double, double* %8
%68 = load double, double* %4
%69 = fadd double 0x3FDAE147AE147AE0, %68
%70 = load double, double* %7
%71 = fmul double %69, %70
%72 = call double @llvm.fmuladd.f64(double %66, double %67, double %71)
%73 = load double, double* %4
%74 = load double, double* %9
%75 = call double @llvm.fmuladd.f64(double %73, double %74, double %72)
store double %75, double* %10
%76 = load i32, i32* %6
%77 = sub nsw i32 %76, 1
%78 = sitofp i32 %77 to double
%79 = load double, double* %4
%80 = fmul double 0x3FB1EB851EB851EB, %79
%81 = load double, double* %8
%82 = load double, double* %7
%83 = fmul double 0x3FC1EB851EB851EB, %82
%84 = call double @llvm.fmuladd.f64(double %80, double %81, double %83)
%85 = load double, double* %4
%86 = fmul double 2.000000e+00, %85
%87 = load double, double* %9
%88 = call double @llvm.fmuladd.f64(double %86, double %87, double %84)
%89 = load double, double* %10
%90 = call double @llvm.fmuladd.f64(double %78, double %88, double %89)
store double %90, double* %10
br label %91
91: ; preds = %64, %38
%92 = load double, double* %10
ret double %92
}

LLVM IR (-O2):
define double @SIM_power_draincap(double %0, i32 %1, i32 %2) {
%4 = fmul double %0, 2.000000e+00
%5 = icmp eq i32 %1, 0
%6 = select i1 %5, double 3.430000e-16, double 1.370000e-16
%7 = select i1 %5, double 4.760000e-16, double 4.010000e-16
%8 = fcmp ult double %0, 1.000000e+01
%9 = fmul double %0, 0x3FCAE147AE147AE0
br i1 %8, label %20, label %10
10: ; preds = %3
%11 = fmul double %9, 5.000000e-01
%12 = tail call double @llvm.fmuladd.f64(double %11, double %6, double 0x3CA0A532A854BB0F)
%13 = tail call double @llvm.fmuladd.f64(double %0, double %7, double %12)
%14 = add nsw i32 %2, -1
%15 = sitofp i32 %14 to double
%16 = fmul double %0, 0x3FB1EB851EB851EB
%17 = tail call double @llvm.fmuladd.f64(double %16, double %6, double 0x3C963198E070F969)
%18 = tail call double @llvm.fmuladd.f64(double %4, double %7, double %17)
%19 = tail call double @llvm.fmuladd.f64(double %15, double %18, double %13)
br label %31
20: ; preds = %3
%21 = fadd double %0, 0x3FDAE147AE147AE0
%22 = fmul double %21, 2.750000e-16
%23 = tail call double @llvm.fmuladd.f64(double %9, double %6, double %22)
%24 = tail call double @llvm.fmuladd.f64(double %0, double %7, double %23)
%25 = add nsw i32 %2, -1
%26 = sitofp i32 %25 to double
%27 = fmul double %0, 0x3FB1EB851EB851EB
%28 = tail call double @llvm.fmuladd.f64(double %27, double %6, double 0x3C863198E070F969)
%29 = tail call double @llvm.fmuladd.f64(double %4, double %7, double %28)
%30 = tail call double @llvm.fmuladd.f64(double %26, double %29, double %24)
br label %31
31: ; preds = %20, %10
%32 = phi double [ %19, %10 ], [ %30, %20 ]
ret double %32
}