#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
#define _SC_LEVEL1_DCACHE_ASSOC 136
#define _SC_LEVEL1_DCACHE_LINESIZE 135
#define _SC_LEVEL1_DCACHE_SIZE 134
int _SC_LEVEL1_ICACHE_SIZE;
#define _SC_LEVEL2_CACHE_ASSOC 133
#define _SC_LEVEL2_CACHE_LINESIZE 132
#define _SC_LEVEL2_CACHE_SIZE 131
#define _SC_LEVEL3_CACHE_ASSOC 130
#define _SC_LEVEL3_CACHE_LINESIZE 129
#define _SC_LEVEL3_CACHE_SIZE 128
int /*<<< orphan*/ __cpuid(unsigned int, unsigned int, unsigned int,
                           unsigned int, unsigned int);
int /*<<< orphan*/ assert(int);
long int __attribute__((no)) handle_amd(int name) {
  unsigned int eax;
  unsigned int ebx;
  unsigned int ecx;
  unsigned int edx;
  __cpuid(0x80000000, eax, ebx, ecx, edx);
  if (name > _SC_LEVEL3_CACHE_LINESIZE)
    return 0;
  unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
  if (eax < fn)
    return 0;
  __cpuid(fn, eax, ebx, ecx, edx);
  if (name < _SC_LEVEL1_DCACHE_SIZE) {
    name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
    ecx = edx;
  }
  switch (name) {
  case _SC_LEVEL1_DCACHE_SIZE:
    return (ecx >> 14) & 0x3fc00;
  case _SC_LEVEL1_DCACHE_ASSOC:
    ecx >>= 16;
    if ((ecx & 0xff) == 0xff)
      return (ecx << 2) & 0x3fc00;
    return ecx & 0xff;
  case _SC_LEVEL1_DCACHE_LINESIZE:
    return ecx & 0xff;
  case _SC_LEVEL2_CACHE_SIZE:
    return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
  case _SC_LEVEL2_CACHE_ASSOC:
    switch ((ecx >> 12) & 0xf) {
    case 0:
    case 1:
    case 2:
    case 4:
      return (ecx >> 12) & 0xf;
    case 6:
      return 8;
    case 8:
      return 16;
    case 10:
      return 32;
    case 11:
      return 48;
    case 12:
      return 64;
    case 13:
      return 96;
    case 14:
      return 128;
    case 15:
      return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
    default:
      return 0;
    }
  case _SC_LEVEL2_CACHE_LINESIZE:
    return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
  case _SC_LEVEL3_CACHE_SIZE:
    return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1;
  case _SC_LEVEL3_CACHE_ASSOC:
    switch ((edx >> 12) & 0xf) {
    case 0:
    case 1:
    case 2:
    case 4:
      return (edx >> 12) & 0xf;
    case 6:
      return 8;
    case 8:
      return 16;
    case 10:
      return 32;
    case 11:
      return 48;
    case 12:
      return 64;
    case 13:
      return 96;
    case 14:
      return 128;
    case 15:
      return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
    default:
      return 0;
    }
  case _SC_LEVEL3_CACHE_LINESIZE:
    return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
  default:
    assert(!"cannot happen");
  }
  return -1;
}


x86 assembly (clang, -O0):
<handle_amd>:
push   %rbp
mov    %rsp,%rbp
sub    $0x50,%rsp
mov    %edi,-0xc(%rbp)
mov    -0x10(%rbp),%esi
mov    -0x14(%rbp),%edx
mov    -0x18(%rbp),%ecx
mov    -0x1c(%rbp),%r8d
mov    $0x80000000,%edi
call   1040 <__cpuid@plt>
cmpl   $0x81,-0xc(%rbp)
jle    115c <handle_amd+0x3c>
movq   $0x0,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
cmpl   $0x83,-0xc(%rbp)
setge  %al
and    $0x1,%al
movzbl %al,%eax
add    $0x80000005,%eax
mov    %eax,-0x20(%rbp)
mov    -0x10(%rbp),%eax
cmp    -0x20(%rbp),%eax
jae    118c <handle_amd+0x6c>
movq   $0x0,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x20(%rbp),%edi
mov    -0x10(%rbp),%esi
mov    -0x14(%rbp),%edx
mov    -0x18(%rbp),%ecx
mov    -0x1c(%rbp),%r8d
call   1040 <__cpuid@plt>
cmpl   $0x86,-0xc(%rbp)
jge    11c8 <handle_amd+0xa8>
mov    $0x86,%eax
mov    0x2e2e(%rip),%rcx
sub    (%rcx),%eax
add    -0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0x1c(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0xc(%rbp),%eax
add    $0xffffff80,%eax
mov    %eax,%ecx
mov    %rcx,-0x28(%rbp)
sub    $0x8,%eax
ja     14cb <handle_amd+0x3ab>
mov    -0x28(%rbp),%rax
lea    0xe18(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x18(%rbp),%eax
shr    $0xe,%eax
and    $0x3fc00,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
shr    $0x10,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
and    $0xff,%eax
cmp    $0xff,%eax
jne    1239 <handle_amd+0x119>
mov    -0x18(%rbp),%eax
shl    $0x2,%eax
and    $0x3fc00,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
and    $0xff,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
and    $0xff,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
and    $0xf000,%eax
cmp    $0x0,%eax
jne    127a <handle_amd+0x15a>
xor    %eax,%eax
mov    %eax,-0x2c(%rbp)
jmp    1288 <handle_amd+0x168>
mov    -0x18(%rbp),%eax
shr    $0x6,%eax
and    $0x3fffc00,%eax
mov    %eax,-0x2c(%rbp)
mov    -0x2c(%rbp),%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
shr    $0xc,%eax
and    $0xf,%eax
mov    %eax,%ecx
mov    %rcx,-0x38(%rbp)
sub    $0xf,%eax
ja     1354 <handle_amd+0x234>
mov    -0x38(%rbp),%rax
lea    0xdab(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x18(%rbp),%eax
shr    $0xc,%eax
and    $0xf,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x8,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x10,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x20,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x30,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x40,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x60,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x80,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
shr    $0x6,%eax
and    $0x3fffc00,%eax
mov    -0x18(%rbp),%ecx
and    $0xff,%ecx
xor    %edx,%edx
div    %ecx
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x0,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x18(%rbp),%eax
and    $0xf000,%eax
cmp    $0x0,%eax
jne    137c <handle_amd+0x25c>
xor    %eax,%eax
mov    %eax,-0x3c(%rbp)
jmp    1387 <handle_amd+0x267>
mov    -0x18(%rbp),%eax
and    $0xff,%eax
mov    %eax,-0x3c(%rbp)
mov    -0x3c(%rbp),%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x1c(%rbp),%eax
and    $0xf000,%eax
cmp    $0x0,%eax
jne    13b0 <handle_amd+0x290>
xor    %eax,%eax
mov    %eax,-0x40(%rbp)
jmp    13be <handle_amd+0x29e>
mov    -0x1c(%rbp),%eax
and    $0x3ffc0000,%eax
shl    $0x1,%eax
mov    %eax,-0x40(%rbp)
mov    -0x40(%rbp),%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x1c(%rbp),%eax
shr    $0xc,%eax
and    $0xf,%eax
mov    %eax,%ecx
mov    %rcx,-0x48(%rbp)
sub    $0xf,%eax
ja     148a <handle_amd+0x36a>
mov    -0x48(%rbp),%rax
lea    0xc35(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x1c(%rbp),%eax
shr    $0xc,%eax
and    $0xf,%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x8,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x10,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x20,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x30,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x40,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x60,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x80,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x1c(%rbp),%eax
and    $0x3ffc0000,%eax
shl    $0x1,%eax
mov    -0x1c(%rbp),%ecx
and    $0xff,%ecx
xor    %edx,%edx
div    %ecx
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
movq   $0x0,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
mov    -0x1c(%rbp),%eax
and    $0xf000,%eax
cmp    $0x0,%eax
jne    14b2 <handle_amd+0x392>
xor    %eax,%eax
mov    %eax,-0x4c(%rbp)
jmp    14bd <handle_amd+0x39d>
mov    -0x1c(%rbp),%eax
and    $0xff,%eax
mov    %eax,-0x4c(%rbp)
mov    -0x4c(%rbp),%eax
mov    %eax,%eax
mov    %rax,-0x8(%rbp)
jmp    14da <handle_amd+0x3ba>
xor    %edi,%edi
call   1030 <assert@plt>
movq   $0xffffffffffffffff,-0x8(%rbp)
ff
mov    -0x8(%rbp),%rax
add    $0x50,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<handle_amd>:
push   %rbx
mov    %edi,%ebx
mov    $0x80000000,%edi
call   1040 <__cpuid@plt>
cmp    $0x81,%ebx
jg     1150 <handle_amd+0x30>
mov    $0x80000005,%edi
call   1040 <__cpuid@plt>
mov    0x2ea2(%rip),%rax
sub    (%rax),%ebx
add    $0x6,%ebx
cmp    $0x9,%ebx
jae    1154 <handle_amd+0x34>
xor    %eax,%eax
pop    %rbx
ret
xor    %edi,%edi
call   1030 <assert@plt>
mov    $0xffffffffffffffff,%rax
pop    %rbx
ret

LLVM IR (-O0):
@_SC_LEVEL1_ICACHE_SIZE = global i32 0
@.str = [14 x i8] c"cannot happen\00"
define i64 @handle_amd(i32 %0) {
%2 = alloca i64
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
store i32 %0, i32* %3
%9 = load i32, i32* %4
%10 = load i32, i32* %5
%11 = load i32, i32* %6
%12 = load i32, i32* %7
%13 = call i32 @__cpuid(i32 -2147483648, i32 %9, i32 %10, i32 %11, i32 %12)
%14 = load i32, i32* %3
%15 = icmp sgt i32 %14, 129
br i1 %15, label %16, label %17
16: ; preds = %1
store i64 0, i64* %2
br label %166
17: ; preds = %1
%18 = load i32, i32* %3
%19 = icmp sge i32 %18, 131
%20 = zext i1 %19 to i32
%21 = add i32 -2147483643, %20
store i32 %21, i32* %8
%22 = load i32, i32* %4
%23 = load i32, i32* %8
%24 = icmp ult i32 %22, %23
br i1 %24, label %25, label %26
25: ; preds = %17
store i64 0, i64* %2
br label %166
26: ; preds = %17
%27 = load i32, i32* %8
%28 = load i32, i32* %4
%29 = load i32, i32* %5
%30 = load i32, i32* %6
%31 = load i32, i32* %7
%32 = call i32 @__cpuid(i32 %27, i32 %28, i32 %29, i32 %30, i32 %31)
%33 = load i32, i32* %3
%34 = icmp slt i32 %33, 134
br i1 %34, label %35, label %41
35: ; preds = %26
%36 = load i32, i32* @_SC_LEVEL1_ICACHE_SIZE
%37 = sub nsw i32 134, %36
%38 = load i32, i32* %3
%39 = add nsw i32 %38, %37
store i32 %39, i32* %3
%40 = load i32, i32* %7
store i32 %40, i32* %6
br label %41
41: ; preds = %35, %26
%42 = load i32, i32* %3
switch i32 %42, label %163 [
i32 134, label %43
i32 136, label %48
i32 135, label %63
i32 131, label %67
i32 133, label %79
i32 132, label %104
i32 128, label %115
i32 130, label %127
i32 129, label %152
]
43: ; preds = %41
%44 = load i32, i32* %6
%45 = lshr i32 %44, 14
%46 = and i32 %45, 261120
%47 = zext i32 %46 to i64
store i64 %47, i64* %2
br label %166
48: ; preds = %41
%49 = load i32, i32* %6
%50 = lshr i32 %49, 16
store i32 %50, i32* %6
%51 = load i32, i32* %6
%52 = and i32 %51, 255
%53 = icmp eq i32 %52, 255
br i1 %53, label %54, label %59
54: ; preds = %48
%55 = load i32, i32* %6
%56 = shl i32 %55, 2
%57 = and i32 %56, 261120
%58 = zext i32 %57 to i64
store i64 %58, i64* %2
br label %166
59: ; preds = %48
%60 = load i32, i32* %6
%61 = and i32 %60, 255
%62 = zext i32 %61 to i64
store i64 %62, i64* %2
br label %166
63: ; preds = %41
%64 = load i32, i32* %6
%65 = and i32 %64, 255
%66 = zext i32 %65 to i64
store i64 %66, i64* %2
br label %166
67: ; preds = %41
%68 = load i32, i32* %6
%69 = and i32 %68, 61440
%70 = icmp eq i32 %69, 0
br i1 %70, label %71, label %72
71: ; preds = %67
br label %76
72: ; preds = %67
%73 = load i32, i32* %6
%74 = lshr i32 %73, 6
%75 = and i32 %74, 67107840
br label %76
76: ; preds = %72, %71
%77 = phi i32 [ 0, %71 ], [ %75, %72 ]
%78 = zext i32 %77 to i64
store i64 %78, i64* %2
br label %166
79: ; preds = %41
%80 = load i32, i32* %6
%81 = lshr i32 %80, 12
%82 = and i32 %81, 15
switch i32 %82, label %103 [
i32 0, label %83
i32 1, label %83
i32 2, label %83
i32 4, label %83
i32 6, label %88
i32 8, label %89
i32 10, label %90
i32 11, label %91
i32 12, label %92
i32 13, label %93
i32 14, label %94
i32 15, label %95
]
83: ; preds = %79, %79, %79, %79
%84 = load i32, i32* %6
%85 = lshr i32 %84, 12
%86 = and i32 %85, 15
%87 = zext i32 %86 to i64
store i64 %87, i64* %2
br label %166
88: ; preds = %79
store i64 8, i64* %2
br label %166
89: ; preds = %79
store i64 16, i64* %2
br label %166
90: ; preds = %79
store i64 32, i64* %2
br label %166
91: ; preds = %79
store i64 48, i64* %2
br label %166
92: ; preds = %79
store i64 64, i64* %2
br label %166
93: ; preds = %79
store i64 96, i64* %2
br label %166
94: ; preds = %79
store i64 128, i64* %2
br label %166
95: ; preds = %79
%96 = load i32, i32* %6
%97 = lshr i32 %96, 6
%98 = and i32 %97, 67107840
%99 = load i32, i32* %6
%100 = and i32 %99, 255
%101 = udiv i32 %98, %100
%102 = zext i32 %101 to i64
store i64 %102, i64* %2
br label %166
103: ; preds = %79
store i64 0, i64* %2
br label %166
104: ; preds = %41
%105 = load i32, i32* %6
%106 = and i32 %105, 61440
%107 = icmp eq i32 %106, 0
br i1 %107, label %108, label %109
108: ; preds = %104
br label %112
109: ; preds = %104
%110 = load i32, i32* %6
%111 = and i32 %110, 255
br label %112
112: ; preds = %109, %108
%113 = phi i32 [ 0, %108 ], [ %111, %109 ]
%114 = zext i32 %113 to i64
store i64 %114, i64* %2
br label %166
115: ; preds = %41
%116 = load i32, i32* %7
%117 = and i32 %116, 61440
%118 = icmp eq i32 %117, 0
br i1 %118, label %119, label %120
119: ; preds = %115
br label %124
120: ; preds = %115
%121 = load i32, i32* %7
%122 = and i32 %121, 1073479680
%123 = shl i32 %122, 1
br label %124
124: ; preds = %120, %119
%125 = phi i32 [ 0, %119 ], [ %123, %120 ]
%126 = zext i32 %125 to i64
store i64 %126, i64* %2
br label %166
127: ; preds = %41
%128 = load i32, i32* %7
%129 = lshr i32 %128, 12
%130 = and i32 %129, 15
switch i32 %130, label %151 [
i32 0, label %131
i32 1, label %131
i32 2, label %131
i32 4, label %131
i32 6, label %136
i32 8, label %137
i32 10, label %138
i32 11, label %139
i32 12, label %140
i32 13, label %141
i32 14, label %142
i32 15, label %143
]
131: ; preds = %127, %127, %127, %127
%132 = load i32, i32* %7
%133 = lshr i32 %132, 12
%134 = and i32 %133, 15
%135 = zext i32 %134 to i64
store i64 %135, i64* %2
br label %166
136: ; preds = %127
store i64 8, i64* %2
br label %166
137: ; preds = %127
store i64 16, i64* %2
br label %166
138: ; preds = %127
store i64 32, i64* %2
br label %166
139: ; preds = %127
store i64 48, i64* %2
br label %166
140: ; preds = %127
store i64 64, i64* %2
br label %166
141: ; preds = %127
store i64 96, i64* %2
br label %166
142: ; preds = %127
store i64 128, i64* %2
br label %166
143: ; preds = %127
%144 = load i32, i32* %7
%145 = and i32 %144, 1073479680
%146 = shl i32 %145, 1
%147 = load i32, i32* %7
%148 = and i32 %147, 255
%149 = udiv i32 %146, %148
%150 = zext i32 %149 to i64
store i64 %150, i64* %2
br label %166
151: ; preds = %127
store i64 0, i64* %2
br label %166
152: ; preds = %41
%153 = load i32, i32* %7
%154 = and i32 %153, 61440
%155 = icmp eq i32 %154, 0
br i1 %155, label %156, label %157
156: ; preds = %152
br label %160
157: ; preds = %152
%158 = load i32, i32* %7
%159 = and i32 %158, 255
br label %160
160: ; preds = %157, %156
%161 = phi i32 [ 0, %156 ], [ %159, %157 ]
%162 = zext i32 %161 to i64
store i64 %162, i64* %2
br label %166
163: ; preds = %41
%164 = call i32 @assert(i32 0)
br label %165
165: ; preds = %163
store i64 -1, i64* %2
br label %166
166: ; preds = %165, %160, %151, %143, %142, %141, %140, %139, %138, %137, %136, %131, %124, %112, %103, %95, %94, %93, %92, %91, %90, %89, %88, %83, %76, %63, %59, %54, %43, %25, %16
%167 = load i64, i64* %2
ret i64 %167
}

LLVM IR (-O2):
@_SC_LEVEL1_ICACHE_SIZE = global i32 0
define i64 @handle_amd(i32 %0) {
%2 = tail call i32 @__cpuid(i32 -2147483648, i32 undef, i32 undef, i32 undef, i32 undef)
%3 = icmp sgt i32 %0, 129
br i1 %3, label %12, label %4
4: ; preds = %1
%5 = tail call i32 @__cpuid(i32 -2147483643, i32 undef, i32 undef, i32 undef, i32 undef)
%6 = load i32, i32* @_SC_LEVEL1_ICACHE_SIZE
%7 = add nsw i32 %0, 6
%8 = sub i32 %7, %6
%9 = icmp ult i32 %8, 9
br i1 %9, label %12, label %10
10: ; preds = %4
%11 = tail call i32 @assert(i32 0)
br label %12
12: ; preds = %4, %10, %1
%13 = phi i64 [ 0, %1 ], [ -1, %10 ], [ 0, %4 ]
ret i64 %13
}