#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) {
  ;

  ;
  (*((volatile unsigned long *)(ui32Base + 0xFFFFC010))) |=
      (((ui32IntFlags & 0x00010000) >> 14) |
       ((ui32IntFlags & 0x00020000) >> 16) |
       ((ui32IntFlags & 0x00040000) >> 19));
  (*((volatile unsigned long *)(ui32Base + 0x0000011C))) |=
      ui32IntFlags & 0x0000ffff;
  (*((volatile unsigned long *)(ui32Base + 0x00000110))) |= 0x00000004;
}


x86 assembly (clang, -O0):
<SHAMD5IntEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0x10000,%eax
sar    $0xe,%eax
mov    -0x8(%rbp),%ecx
and    $0x20000,%ecx
sar    $0x10,%ecx
or     %ecx,%eax
mov    -0x8(%rbp),%ecx
and    $0x40000,%ecx
sar    $0x13,%ecx
or     %ecx,%eax
movslq %eax,%rdx
mov    -0x4(%rbp),%eax
add    $0xffffc010,%eax
mov    %eax,%eax
mov    (%rax),%rcx
or     %rdx,%rcx
mov    %rcx,(%rax)
mov    -0x8(%rbp),%eax
and    $0xffff,%eax
movslq %eax,%rdx
mov    -0x4(%rbp),%eax
add    $0x11c,%eax
cltq
mov    (%rax),%rcx
or     %rdx,%rcx
mov    %rcx,(%rax)
mov    -0x4(%rbp),%eax
add    $0x110,%eax
cltq
mov    (%rax),%rcx
or     $0x4,%rcx
mov    %rcx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<SHAMD5IntEnable>:
mov    %esi,%eax
movzwl %si,%ecx
shr    $0xe,%esi
and    $0x4,%esi
shr    $0x10,%eax
and    $0x2,%eax
or     %esi,%eax
lea    -0x3ff0(%rdi),%edx
or     %rax,(%rdx)
movslq %edi,%rax
or     %rcx,0x11c(%rax)
orq    $0x4,0x110(%rax)
04
ret

LLVM IR (-O0):
define void @SHAMD5IntEnable(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %4
%6 = and i32 %5, 65536
%7 = ashr i32 %6, 14
%8 = load i32, i32* %4
%9 = and i32 %8, 131072
%10 = ashr i32 %9, 16
%11 = or i32 %7, %10
%12 = load i32, i32* %4
%13 = and i32 %12, 262144
%14 = ashr i32 %13, 19
%15 = or i32 %11, %14
%16 = sext i32 %15 to i64
%17 = load i32, i32* %3
%18 = add i32 %17, -16368
%19 = zext i32 %18 to i64
%20 = inttoptr i64 %19 to i64*
%21 = load volatile i64, i64* %20
%22 = or i64 %21, %16
store volatile i64 %22, i64* %20
%23 = load i32, i32* %4
%24 = and i32 %23, 65535
%25 = sext i32 %24 to i64
%26 = load i32, i32* %3
%27 = add nsw i32 %26, 284
%28 = sext i32 %27 to i64
%29 = inttoptr i64 %28 to i64*
%30 = load volatile i64, i64* %29
%31 = or i64 %30, %25
store volatile i64 %31, i64* %29
%32 = load i32, i32* %3
%33 = add nsw i32 %32, 272
%34 = sext i32 %33 to i64
%35 = inttoptr i64 %34 to i64*
%36 = load volatile i64, i64* %35
%37 = or i64 %36, 4
store volatile i64 %37, i64* %35
ret void
}

LLVM IR (-O2):
define void @SHAMD5IntEnable(i32 %0, i32 %1) {
%3 = lshr i32 %1, 14
%4 = and i32 %3, 4
%5 = lshr i32 %1, 16
%6 = and i32 %5, 2
%7 = or i32 %4, %6
%8 = zext i32 %7 to i64
%9 = add i32 %0, -16368
%10 = zext i32 %9 to i64
%11 = inttoptr i64 %10 to i64*
%12 = load volatile i64, i64* %11
%13 = or i64 %12, %8
store volatile i64 %13, i64* %11
%14 = and i32 %1, 65535
%15 = zext i32 %14 to i64
%16 = add nsw i32 %0, 284
%17 = sext i32 %16 to i64
%18 = inttoptr i64 %17 to i64*
%19 = load volatile i64, i64* %18
%20 = or i64 %19, %15
store volatile i64 %20, i64* %18
%21 = add nsw i32 %0, 272
%22 = sext i32 %21 to i64
%23 = inttoptr i64 %22 to i64*
%24 = load volatile i64, i64* %23
%25 = or i64 %24, 4
store volatile i64 %25, i64* %23
ret void
}