int DisableInterrupt(const unsigned int nIRQ) {
  if (nIRQ > 127) {
    return -1;
  }
  const unsigned int mod = nIRQ % 32;
  const unsigned int div = nIRQ / 32;
  switch (div) {
  case 0:
    (*((volatile unsigned int *)(((0x0FFFC000) + 0x180)))) = (0x1 << mod);
    break;
  case 1:
    (*((volatile unsigned int *)(((0x0FFFC000) + 0x184)))) = (0x1 << mod);
    break;
  case 2:
    (*((volatile unsigned int *)(((0x0FFFC000) + 0x188)))) = (0x1 << mod);
    break;
  case 3:
    (*((volatile unsigned int *)(((0x0FFFC000) + 0x18C)))) = (0x1 << mod);
    break;
  default:
    return -1;
  }
  return 0;
}


x86 assembly (clang, -O0):
<DisableInterrupt>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
cmpl   $0x7f,-0x8(%rbp)
jbe    111d <DisableInterrupt+0x1d>
movl   $0xffffffff,-0x4(%rbp)
jmp    11c7 <DisableInterrupt+0xc7>
mov    -0x8(%rbp),%eax
and    $0x1f,%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%eax
shr    $0x5,%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
mov    %rax,-0x18(%rbp)
sub    $0x3,%rax
ja     11b4 <DisableInterrupt+0xb4>
mov    -0x18(%rbp),%rax
lea    0xeb5(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0xc(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,%ecx
mov    $0xfffc180,%eax
mov    %ecx,(%rax)
jmp    11c0 <DisableInterrupt+0xc0>
mov    -0xc(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,%ecx
mov    $0xfffc184,%eax
mov    %ecx,(%rax)
jmp    11c0 <DisableInterrupt+0xc0>
mov    -0xc(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,%ecx
mov    $0xfffc188,%eax
mov    %ecx,(%rax)
jmp    11c0 <DisableInterrupt+0xc0>
mov    -0xc(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,%ecx
mov    $0xfffc18c,%eax
mov    %ecx,(%rax)
jmp    11c0 <DisableInterrupt+0xc0>
movl   $0xffffffff,-0x4(%rbp)
jmp    11c7 <DisableInterrupt+0xc7>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<DisableInterrupt>:
mov    $0xffffffff,%eax
cmp    $0x7f,%edi
ja     116f <DisableInterrupt+0x6f>
mov    %edi,%ecx
shr    $0x5,%ecx
cmp    $0x3,%ecx
ja     116f <DisableInterrupt+0x6f>
and    $0x1f,%edi
lea    0xee2(%rip),%rax
movslq (%rax,%rcx,4),%rcx
add    %rax,%rcx
jmp    *%rcx
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
mov    %eax,0xfffc180
jmp    116d <DisableInterrupt+0x6d>
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
mov    %eax,0xfffc184
jmp    116d <DisableInterrupt+0x6d>
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
mov    %eax,0xfffc188
jmp    116d <DisableInterrupt+0x6d>
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
mov    %eax,0xfffc18c
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @DisableInterrupt(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
%6 = load i32, i32* %3
%7 = icmp ugt i32 %6, 127
br i1 %7, label %8, label %9
8: ; preds = %1
store i32 -1, i32* %2
br label %29
9: ; preds = %1
%10 = load i32, i32* %3
%11 = urem i32 %10, 32
store i32 %11, i32* %4
%12 = load i32, i32* %3
%13 = udiv i32 %12, 32
store i32 %13, i32* %5
%14 = load i32, i32* %5
switch i32 %14, label %27 [
i32 0, label %15
i32 1, label %18
i32 2, label %21
i32 3, label %24
]
15: ; preds = %9
%16 = load i32, i32* %4
%17 = shl i32 1, %16
store volatile i32 %17, i32* inttoptr (i64 268419456 to i32*)
br label %28
18: ; preds = %9
%19 = load i32, i32* %4
%20 = shl i32 1, %19
store volatile i32 %20, i32* inttoptr (i64 268419460 to i32*)
br label %28
21: ; preds = %9
%22 = load i32, i32* %4
%23 = shl i32 1, %22
store volatile i32 %23, i32* inttoptr (i64 268419464 to i32*)
br label %28
24: ; preds = %9
%25 = load i32, i32* %4
%26 = shl i32 1, %25
store volatile i32 %26, i32* inttoptr (i64 268419468 to i32*)
br label %28
27: ; preds = %9
store i32 -1, i32* %2
br label %29
28: ; preds = %24, %21, %18, %15
store i32 0, i32* %2
br label %29
29: ; preds = %28, %27, %8
%30 = load i32, i32* %2
ret i32 %30
}

LLVM IR (-O2):
define i32 @DisableInterrupt(i32 %0) {
%2 = icmp ugt i32 %0, 127
br i1 %2, label %14, label %3
3: ; preds = %1
%4 = and i32 %0, 31
%5 = lshr i32 %0, 5
switch i32 %5, label %14 [
i32 0, label %6
i32 1, label %8
i32 2, label %10
i32 3, label %12
]
6: ; preds = %3
%7 = shl nuw i32 1, %4
store volatile i32 %7, i32* inttoptr (i64 268419456 to i32*)
br label %14
8: ; preds = %3
%9 = shl nuw i32 1, %4
store volatile i32 %9, i32* inttoptr (i64 268419460 to i32*)
br label %14
10: ; preds = %3
%11 = shl nuw i32 1, %4
store volatile i32 %11, i32* inttoptr (i64 268419464 to i32*)
br label %14
12: ; preds = %3
%13 = shl nuw i32 1, %4
store volatile i32 %13, i32* inttoptr (i64 268419468 to i32*)
br label %14
14: ; preds = %3, %12, %10, %8, %6, %1
%15 = phi i32 [ -1, %1 ], [ -1, %3 ], [ 0, %12 ], [ 0, %10 ], [ 0, %8 ], [ 0, %6 ]
ret i32 %15
}