#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ DEBUG_ASSERT(int);
void ADCHardwareOversampleConfigure(unsigned long ulBase,
                                    unsigned long ulFactor) {
  unsigned long ulValue;
  DEBUG_ASSERT((ulBase == 0x40038000) || (ulBase == 0x40039000));
  DEBUG_ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
                (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
                (ulFactor == 64)));
  for (ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1) {
  }
  (*((volatile unsigned long *)(ulBase + 0x00000030))) = ulValue;
}


x86 assembly (clang, -O0):
<ADCHardwareOversampleConfigure>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    $0x1,%al
cmpq   $0x40038000,-0x8(%rbp)
40
mov    %al,-0x19(%rbp)
je     1141 <ADCHardwareOversampleConfigure+0x31>
cmpq   $0x40039000,-0x8(%rbp)
40
sete   %al
mov    %al,-0x19(%rbp)
mov    -0x19(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <DEBUG_ASSERT@plt>
mov    $0x1,%al
cmpq   $0x0,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
mov    $0x1,%al
cmpq   $0x2,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
mov    $0x1,%al
cmpq   $0x4,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
mov    $0x1,%al
cmpq   $0x8,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
mov    $0x1,%al
cmpq   $0x10,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
mov    $0x1,%al
cmpq   $0x20,-0x10(%rbp)
mov    %al,-0x1a(%rbp)
je     11b9 <ADCHardwareOversampleConfigure+0xa9>
cmpq   $0x40,-0x10(%rbp)
sete   %al
mov    %al,-0x1a(%rbp)
mov    -0x1a(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <DEBUG_ASSERT@plt>
movq   $0x0,-0x18(%rbp)
mov    -0x10(%rbp),%rax
shr    $0x1,%rax
mov    %rax,-0x10(%rbp)
cmpq   $0x0,-0x10(%rbp)
je     1207 <ADCHardwareOversampleConfigure+0xf7>
jmp    11ea <ADCHardwareOversampleConfigure+0xda>
mov    -0x18(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x18(%rbp)
mov    -0x10(%rbp),%rax
shr    $0x1,%rax
mov    %rax,-0x10(%rbp)
jmp    11da <ADCHardwareOversampleConfigure+0xca>
mov    -0x18(%rbp),%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x30(%rax)
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCHardwareOversampleConfigure>:
push   %r14
push   %rbx
push   %rax
mov    %rsi,%rbx
mov    %rdi,%r14
mov    %rdi,%rax
and    $0xffffffffffffefff,%rax
xor    %edi,%edi
cmp    $0x40038000,%rax
sete   %dil
call   1030 <DEBUG_ASSERT@plt>
cmp    $0x20,%rbx
ja     117c <ADCHardwareOversampleConfigure+0x6c>
mov    $0x1,%edi
movabs $0x100010115,%rax
bt     %rbx,%rax
jae    117c <ADCHardwareOversampleConfigure+0x6c>
call   1030 <DEBUG_ASSERT@plt>
xor    %eax,%eax
cmp    $0x2,%rbx
jb     1170 <ADCHardwareOversampleConfigure+0x60>
mov    %rbx,%rcx
nop
shr    %rcx
add    $0x1,%rax
cmp    $0x3,%rbx
mov    %rcx,%rbx
ja     1160 <ADCHardwareOversampleConfigure+0x50>
mov    %rax,0x30(%r14)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret
xor    %edi,%edi
cmp    $0x40,%rbx
sete   %dil
jmp    114f <ADCHardwareOversampleConfigure+0x3f>

LLVM IR (-O0):
define void @ADCHardwareOversampleConfigure(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
%5 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%6 = load i64, i64* %3
%7 = icmp eq i64 %6, 1073971200
br i1 %7, label %11, label %8
8: ; preds = %2
%9 = load i64, i64* %3
%10 = icmp eq i64 %9, 1073975296
br label %11
11: ; preds = %8, %2
%12 = phi i1 [ true, %2 ], [ %10, %8 ]
%13 = zext i1 %12 to i32
%14 = call i32 @DEBUG_ASSERT(i32 %13)
%15 = load i64, i64* %4
%16 = icmp eq i64 %15, 0
br i1 %16, label %35, label %17
17: ; preds = %11
%18 = load i64, i64* %4
%19 = icmp eq i64 %18, 2
br i1 %19, label %35, label %20
20: ; preds = %17
%21 = load i64, i64* %4
%22 = icmp eq i64 %21, 4
br i1 %22, label %35, label %23
23: ; preds = %20
%24 = load i64, i64* %4
%25 = icmp eq i64 %24, 8
br i1 %25, label %35, label %26
26: ; preds = %23
%27 = load i64, i64* %4
%28 = icmp eq i64 %27, 16
br i1 %28, label %35, label %29
29: ; preds = %26
%30 = load i64, i64* %4
%31 = icmp eq i64 %30, 32
br i1 %31, label %35, label %32
32: ; preds = %29
%33 = load i64, i64* %4
%34 = icmp eq i64 %33, 64
br label %35
35: ; preds = %32, %29, %26, %23, %20, %17, %11
%36 = phi i1 [ true, %29 ], [ true, %26 ], [ true, %23 ], [ true, %20 ], [ true, %17 ], [ true, %11 ], [ %34, %32 ]
%37 = zext i1 %36 to i32
%38 = call i32 @DEBUG_ASSERT(i32 %37)
store i64 0, i64* %5
%39 = load i64, i64* %4
%40 = lshr i64 %39, 1
store i64 %40, i64* %4
br label %41
41: ; preds = %45, %35
%42 = load i64, i64* %4
%43 = icmp ne i64 %42, 0
br i1 %43, label %44, label %50
44: ; preds = %41
br label %45
45: ; preds = %44
%46 = load i64, i64* %5
%47 = add i64 %46, 1
store i64 %47, i64* %5
%48 = load i64, i64* %4
%49 = lshr i64 %48, 1
store i64 %49, i64* %4
br label %41
50: ; preds = %41
%51 = load i64, i64* %5
%52 = load i64, i64* %3
%53 = add i64 %52, 48
%54 = inttoptr i64 %53 to i64*
store volatile i64 %51, i64* %54
ret void
}

LLVM IR (-O2):
define void @ADCHardwareOversampleConfigure(i64 %0, i64 %1) {
%3 = and i64 %0, -4097
%4 = icmp eq i64 %3, 1073971200
%5 = zext i1 %4 to i32
%6 = tail call i32 @DEBUG_ASSERT(i32 %5)
switch i64 %1, label %7 [
i64 32, label %10
i64 16, label %10
i64 8, label %10
i64 4, label %10
i64 2, label %10
i64 0, label %10
]
7: ; preds = %2
%8 = icmp eq i64 %1, 64
%9 = zext i1 %8 to i32
br label %10
10: ; preds = %2, %2, %2, %2, %2, %2, %7
%11 = phi i32 [ 1, %2 ], [ %9, %7 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ], [ 1, %2 ]
%12 = tail call i32 @DEBUG_ASSERT(i32 %11)
%13 = icmp ult i64 %1, 2
br i1 %13, label %20, label %14
14: ; preds = %10, %14
%15 = phi i64 [ %18, %14 ], [ 0, %10 ]
%16 = phi i64 [ %17, %14 ], [ %1, %10 ]
%17 = lshr i64 %16, 1
%18 = add nuw nsw i64 %15, 1
%19 = icmp ult i64 %16, 4
br i1 %19, label %20, label %14
20: ; preds = %14, %10
%21 = phi i64 [ 0, %10 ], [ %18, %14 ]
%22 = add i64 %0, 48
%23 = inttoptr i64 %22 to i64*
store volatile i64 %21, i64* %23
ret void
}