unsigned int MT_gen_hash_bits(unsigned long int address) {
  address = (~address) + (address << 21);
  address = address ^ (address >> 24);
  address = (address + (address << 3)) + (address << 8);
  address = address ^ (address >> 14);
  address = (address + (address << 2)) + (address << 4);
  address = address ^ (address >> 28);
  address = address + (address << 31);
  return (unsigned int)address;
}


x86 assembly (clang, -O0):
<MT_gen_hash_bits>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
xor    $0xffffffffffffffff,%rax
mov    -0x8(%rbp),%rcx
shl    $0x15,%rcx
add    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shr    $0x18,%rcx
xor    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shl    $0x3,%rcx
add    %rcx,%rax
mov    -0x8(%rbp),%rcx
shl    $0x8,%rcx
add    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shr    $0xe,%rcx
xor    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shl    $0x2,%rcx
add    %rcx,%rax
mov    -0x8(%rbp),%rcx
shl    $0x4,%rcx
add    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shr    $0x1c,%rcx
xor    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x8(%rbp),%rcx
shl    $0x1f,%rcx
add    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<MT_gen_hash_bits>:
mov    %rdi,%rax
not    %rax
shl    $0x15,%rdi
add    %rax,%rdi
mov    %rdi,%rax
shr    $0x18,%rax
xor    %rdi,%rax
imul   $0x109,%rax,%rax
mov    %rax,%rcx
shr    $0xe,%rcx
xor    %rax,%rcx
lea    (%rcx,%rcx,4),%rax
lea    (%rcx,%rax,4),%rcx
mov    %rcx,%rax
shr    $0x1c,%rax
xor    %ecx,%eax
mov    %eax,%ecx
shl    $0x1f,%ecx
sub    %ecx,%eax
ret

LLVM IR (-O0):
define i32 @MT_gen_hash_bits(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = xor i64 %3, -1
%5 = load i64, i64* %2
%6 = shl i64 %5, 21
%7 = add i64 %4, %6
store i64 %7, i64* %2
%8 = load i64, i64* %2
%9 = load i64, i64* %2
%10 = lshr i64 %9, 24
%11 = xor i64 %8, %10
store i64 %11, i64* %2
%12 = load i64, i64* %2
%13 = load i64, i64* %2
%14 = shl i64 %13, 3
%15 = add i64 %12, %14
%16 = load i64, i64* %2
%17 = shl i64 %16, 8
%18 = add i64 %15, %17
store i64 %18, i64* %2
%19 = load i64, i64* %2
%20 = load i64, i64* %2
%21 = lshr i64 %20, 14
%22 = xor i64 %19, %21
store i64 %22, i64* %2
%23 = load i64, i64* %2
%24 = load i64, i64* %2
%25 = shl i64 %24, 2
%26 = add i64 %23, %25
%27 = load i64, i64* %2
%28 = shl i64 %27, 4
%29 = add i64 %26, %28
store i64 %29, i64* %2
%30 = load i64, i64* %2
%31 = load i64, i64* %2
%32 = lshr i64 %31, 28
%33 = xor i64 %30, %32
store i64 %33, i64* %2
%34 = load i64, i64* %2
%35 = load i64, i64* %2
%36 = shl i64 %35, 31
%37 = add i64 %34, %36
store i64 %37, i64* %2
%38 = load i64, i64* %2
%39 = trunc i64 %38 to i32
ret i32 %39
}

LLVM IR (-O2):
define i32 @MT_gen_hash_bits(i64 %0) {
%2 = xor i64 %0, -1
%3 = shl i64 %0, 21
%4 = add i64 %3, %2
%5 = lshr i64 %4, 24
%6 = xor i64 %5, %4
%7 = mul i64 %6, 265
%8 = lshr i64 %7, 14
%9 = xor i64 %8, %7
%10 = mul i64 %9, 21
%11 = lshr i64 %10, 28
%12 = xor i64 %11, %10
%13 = trunc i64 %12 to i32
%14 = mul i32 %13, -2147483647
ret i32 %14
}