xunge/DecIR huggingface dataset:
int isdigit(int a) { return (47 < a && a < 57) ? 1 : 0; }


x86 assembly (clang, -O0):
<isdigit>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
xor    %eax,%eax
mov    $0x2f,%ecx
cmp    -0x4(%rbp),%ecx
mov    %al,-0x5(%rbp)
jge    1124 <isdigit+0x24>
cmpl   $0x39,-0x4(%rbp)
setl   %al
mov    %al,-0x5(%rbp)
mov    -0x5(%rbp),%dl
xor    %eax,%eax
mov    $0x1,%ecx
test   $0x1,%dl
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<isdigit>:
add    $0xffffffd0,%edi
xor    %eax,%eax
cmp    $0x9,%edi
setb   %al
ret

LLVM IR (-O0):
define i32 @isdigit(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp slt i32 47, %3
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load i32, i32* %2
%7 = icmp slt i32 %6, 57
br label %8
8: ; preds = %5, %1
%9 = phi i1 [ false, %1 ], [ %7, %5 ]
%10 = zext i1 %9 to i64
%11 = select i1 %9, i32 1, i32 0
ret i32 %11
}

LLVM IR (-O2):
define i32 @isdigit(i32 %0) {
%2 = add i32 %0, -48
%3 = icmp ult i32 %2, 9
%4 = zext i1 %3 to i32
ret i32 %4
}
/* Variables and functions */
void *malloc(size_t);
size_t state_size(int const);
void *create_state(const int type) {
  size_t statesize;
  statesize = state_size(type);
  if (statesize)
    return malloc(statesize);
  else
    return NULL;
}


x86 assembly (clang, -O0):
<create_state>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0xc(%rbp)
mov    -0xc(%rbp),%edi
call   1030 <state_size@plt>
mov    %rax,-0x18(%rbp)
cmpq   $0x0,-0x18(%rbp)
je     1154 <create_state+0x34>
mov    -0x18(%rbp),%rdi
call   1040 <malloc@plt>
mov    %rax,-0x8(%rbp)
jmp    115c <create_state+0x3c>
movq   $0x0,-0x8(%rbp)
mov    -0x8(%rbp),%rax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<create_state>:
push   %rax
call   1030 <state_size@plt>
test   %rax,%rax
je     1134 <create_state+0x14>
mov    %rax,%rdi
pop    %rax
jmp    1040 <malloc@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
define i8* @create_state(i32 %0) {
%2 = alloca i8*
%3 = alloca i32
%4 = alloca i64
store i32 %0, i32* %3
%5 = load i32, i32* %3
%6 = call i64 @state_size(i32 %5)
store i64 %6, i64* %4
%7 = load i64, i64* %4
%8 = icmp ne i64 %7, 0
br i1 %8, label %9, label %12
9: ; preds = %1
%10 = load i64, i64* %4
%11 = call i8* @malloc(i64 %10)
store i8* %11, i8** %2
br label %13
12: ; preds = %1
store i8* null, i8** %2
br label %13
13: ; preds = %12, %9
%14 = load i8*, i8** %2
ret i8* %14
}

LLVM IR (-O2):
define noalias i8* @create_state(i32 %0) {
%2 = tail call i64 @state_size(i32 %0)
%3 = icmp eq i64 %2, 0
br i1 %3, label %6, label %4
4: ; preds = %1
%5 = tail call i8* @malloc(i64 %2)
br label %6
6: ; preds = %1, %4
%7 = phi i8* [ %5, %4 ], [ null, %1 ]
ret i8* %7
}
void *foo2(unsigned long x) {
  (void)x;
  static int bar = 0xbee;
  return &bar;
}


x86 assembly (clang, -O0):
<foo2>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
lea    0x2f11(%rip),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<foo2>:
lea    0x2f19(%rip),%rax
ret

LLVM IR (-O0):
@foo2.bar = internal global i32 3054
define i8* @foo2(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
ret i8* bitcast (i32* @foo2.bar to i8*)
}

LLVM IR (-O2):
@foo2.bar = internal global i32 3054
define i8* @foo2(i64 %0) {
ret i8* bitcast (i32* @foo2.bar to i8*)
}
void nullclose(int status) {}


x86 assembly (clang, -O0):
<nullclose>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<nullclose>:
ret

LLVM IR (-O0):
define void @nullclose(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
ret void
}

LLVM IR (-O2):
define void @nullclose(i32 %0) {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ int32_t;

/* Variables and functions */
int /*<<< orphan*/ close(int /*<<< orphan*/);
int32_t aliyun_iot_network_close(int32_t fd) { return close(fd); }


x86 assembly (clang, -O0):
<aliyun_iot_network_close>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
call   1030 <close@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<aliyun_iot_network_close>:
jmp    1030 <close@plt>

LLVM IR (-O0):
define i32 @aliyun_iot_network_close(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i32 @close(i32 %3)
ret i32 %4
}

LLVM IR (-O2):
define i32 @aliyun_iot_network_close(i32 %0) {
%2 = tail call i32 @close(i32 %0)
ret i32 %2
}
/* Variables and functions */
int /*<<< orphan*/ EXIT_SUCCESS;
int /*<<< orphan*/ exit(int /*<<< orphan*/);
int /*<<< orphan*/ fprintf(int /*<<< orphan*/, char *);
int /*<<< orphan*/ stdout;
void printUsage(void) {
  fprintf(stdout,
          "Usage: whoami [OPTION]...\n      Print the user name associated "
          "with the current effective user ID.\n\n      -h help\n");
  exit(EXIT_SUCCESS);
}


x86 assembly (clang, -O0):
<printUsage>:
push   %rbp
mov    %rsp,%rbp
mov    0x2eb5(%rip),%rax
mov    (%rax),%edi
lea    0xecc(%rip),%rsi
call   1030 <fprintf@plt>
mov    0x2e98(%rip),%rax
mov    (%rax),%edi
call   1040 <exit@plt>

x86 assembly (clang, -O2):
<printUsage>:
push   %rax
mov    0x2eb8(%rip),%rax
mov    (%rax),%edi
lea    0xecf(%rip),%rsi
call   1030 <fprintf@plt>
mov    0x2e9b(%rip),%rax
mov    (%rax),%edi
call   1040 <exit@plt>

LLVM IR (-O0):
@stdout = global i32 0
@.str = [115 x i8] c"Usage: whoami [OPTION]...\0A Print the user name associated with the current effective user ID.\0A\0A -h help\0A\00"
@EXIT_SUCCESS = global i32 0
define void @printUsage() {
%1 = load i32, i32* @stdout
%2 = call i32 @fprintf(i32 %1, i8* getelementptr inbounds ([115 x i8], [115 x i8]* @.str, i64 0, i64 0))
%3 = load i32, i32* @EXIT_SUCCESS
%4 = call i32 @exit(i32 %3)
unreachable
}

LLVM IR (-O2):
@stdout = global i32 0
@.str = [115 x i8] c"Usage: whoami [OPTION]...\0A Print the user name associated with the current effective user ID.\0A\0A -h help\0A\00"
@EXIT_SUCCESS = global i32 0
define void @printUsage() {
%1 = load i32, i32* @stdout
%2 = tail call i32 @fprintf(i32 %1, i8* getelementptr inbounds ([115 x i8], [115 x i8]* @.str, i64 0, i64 0))
%3 = load i32, i32* @EXIT_SUCCESS
%4 = tail call i32 @exit(i32 %3)
unreachable
}
/* Type definitions */
struct yaffs_dev {
  int dummy;
};

/* Variables and functions */
int yaffs_mount_common(struct yaffs_dev *, int /*<<< orphan*/, int, int);
int yaffs_mount3_reldev(struct yaffs_dev *dev, int read_only,
                        int skip_checkpt) {
  return yaffs_mount_common(dev, (0), read_only, skip_checkpt);
}


x86 assembly (clang, -O0):
<yaffs_mount3_reldev>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %edx,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0xc(%rbp),%edx
mov    -0x10(%rbp),%ecx
xor    %esi,%esi
call   1030 <yaffs_mount_common@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<yaffs_mount3_reldev>:
mov    %edx,%ecx
mov    %esi,%edx
xor    %esi,%esi
jmp    1030 <yaffs_mount_common@plt>

LLVM IR (-O0):
%struct.yaffs_dev = type { i32 }
define i32 @yaffs_mount3_reldev(%struct.yaffs_dev* %0, i32 %1, i32 %2) {
%4 = alloca %struct.yaffs_dev*
%5 = alloca i32
%6 = alloca i32
store %struct.yaffs_dev* %0, %struct.yaffs_dev** %4
store i32 %1, i32* %5
store i32 %2, i32* %6
%7 = load %struct.yaffs_dev*, %struct.yaffs_dev** %4
%8 = load i32, i32* %5
%9 = load i32, i32* %6
%10 = call i32 @yaffs_mount_common(%struct.yaffs_dev* %7, i32 0, i32 %8, i32 %9)
ret i32 %10
}

LLVM IR (-O2):
%struct.yaffs_dev = type { i32 }
define i32 @yaffs_mount3_reldev(%struct.yaffs_dev* %0, i32 %1, i32 %2) {
%4 = tail call i32 @yaffs_mount_common(%struct.yaffs_dev* %0, i32 0, i32 %1, i32 %2)
ret i32 %4
}
void evdev_cleanup(void) {}


x86 assembly (clang, -O0):
<evdev_cleanup>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<evdev_cleanup>:
ret

LLVM IR (-O0):
define void @evdev_cleanup() {
ret void
}

LLVM IR (-O2):
define void @evdev_cleanup() {
ret void
}
int twist_l_on_cornerperm(cperm)
int cperm;
{
  int temp_arr[8];
  cornerperm_unpack(cperm, temp_arr);
  four_cycle(temp_arr, 6, 5, 3, 2);
  return cornerperm_pack(temp_arr);
}


x86 assembly (clang, -O0):
<twist_l_on_cornerperm>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
lea    -0x30(%rbp),%rsi
mov    $0x0,%al
call   1040 <cornerperm_unpack@plt>
lea    -0x30(%rbp),%rdi
mov    $0x6,%esi
mov    $0x5,%edx
mov    $0x3,%ecx
mov    $0x2,%r8d
mov    $0x0,%al
call   1030 <four_cycle@plt>
lea    -0x30(%rbp),%rdi
mov    $0x0,%al
call   1050 <cornerperm_pack@plt>
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<twist_l_on_cornerperm>:
push   %rbx
sub    $0x20,%rsp
mov    %rsp,%rbx
mov    %rbx,%rsi
xor    %eax,%eax
call   1040 <cornerperm_unpack@plt>
mov    %rbx,%rdi
mov    $0x6,%esi
mov    $0x5,%edx
mov    $0x3,%ecx
mov    $0x2,%r8d
xor    %eax,%eax
call   1030 <four_cycle@plt>
mov    %rbx,%rdi
xor    %eax,%eax
call   1050 <cornerperm_pack@plt>
add    $0x20,%rsp
pop    %rbx
ret

LLVM IR (-O0):
define i32 @twist_l_on_cornerperm(i32 %0) {
%2 = alloca i32
%3 = alloca [8 x i32]
store i32 %0, i32* %2
%4 = load i32, i32* %2
%5 = getelementptr inbounds [8 x i32], [8 x i32]* %3, i64 0, i64 0
%6 = call i32 (i32, i32*, ...) bitcast (i32 (...)* @cornerperm_unpack to i32 (i32, i32*, ...)*)(i32 %4, i32* %5)
%7 = getelementptr inbounds [8 x i32], [8 x i32]* %3, i64 0, i64 0
%8 = call i32 (i32*, i32, i32, i32, i32, ...) bitcast (i32 (...)* @four_cycle to i32 (i32*, i32, i32, i32, i32, ...)*)(i32* %7, i32 6, i32 5, i32 3, i32 2)
%9 = getelementptr inbounds [8 x i32], [8 x i32]* %3, i64 0, i64 0
%10 = call i32 (i32*, ...) bitcast (i32 (...)* @cornerperm_pack to i32 (i32*, ...)*)(i32* %9)
ret i32 %10
}

LLVM IR (-O2):
define i32 @twist_l_on_cornerperm(i32 %0) {
%2 = alloca [8 x i32]
%3 = bitcast [8 x i32]* %2 to i8*
%4 = getelementptr inbounds [8 x i32], [8 x i32]* %2, i64 0, i64 0
%5 = call i32 (i32, i32*, ...) bitcast (i32 (...)* @cornerperm_unpack to i32 (i32, i32*, ...)*)(i32 %0, i32* %4)
%6 = call i32 (i32*, i32, i32, i32, i32, ...) bitcast (i32 (...)* @four_cycle to i32 (i32*, i32, i32, i32, i32, ...)*)(i32* %4, i32 6, i32 5, i32 3, i32 2)
%7 = call i32 (i32*, ...) bitcast (i32 (...)* @cornerperm_pack to i32 (i32*, ...)*)(i32* %4)
ret i32 %7
}
/* Variables and functions */
unsigned short x87_get_control_word();
int /*<<< orphan*/ x87_set_control_word(unsigned short);
unsigned short x87_set_double_precision(void) {
  unsigned short mode = x87_get_control_word();
  x87_set_control_word((mode & ~0x300) | 0x200);
  return mode;
}


x86 assembly (clang, -O0):
<x87_set_double_precision>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    $0x0,%al
call   1040 <x87_get_control_word@plt>
mov    %ax,-0x2(%rbp)
movzwl -0x2(%rbp),%eax
and    $0xfffffcff,%eax
or     $0x200,%eax
movzwl %ax,%edi
call   1030 <x87_set_control_word@plt>
movzwl -0x2(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<x87_set_double_precision>:
push   %rbx
xor    %eax,%eax
call   1040 <x87_get_control_word@plt>
mov    %eax,%ebx
mov    %ebx,%eax
and    $0xfffffcff,%eax
or     $0x200,%eax
movzwl %ax,%edi
call   1030 <x87_set_control_word@plt>
mov    %ebx,%eax
pop    %rbx
ret

LLVM IR (-O0):
define zeroext i16 @x87_set_double_precision() {
%1 = alloca i16
%2 = call zeroext i16 (...) @x87_get_control_word()
store i16 %2, i16* %1
%3 = load i16, i16* %1
%4 = zext i16 %3 to i32
%5 = and i32 %4, -769
%6 = or i32 %5, 512
%7 = trunc i32 %6 to i16
%8 = call i32 @x87_set_control_word(i16 zeroext %7)
%9 = load i16, i16* %1
ret i16 %9
}

LLVM IR (-O2):
define zeroext i16 @x87_set_double_precision() {
%1 = tail call zeroext i16 (...) @x87_get_control_word()
%2 = and i16 %1, -769
%3 = or i16 %2, 512
%4 = tail call i32 @x87_set_control_word(i16 zeroext %3)
ret i16 %1
}
/* Variables and functions */
scalar_t__ RAND_MAX;
double rand();
double unif(double a, double b) {
  return (rand() / (double)RAND_MAX) * (b - a) + a;
}


x86 assembly (clang, -O0):
<unif>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movsd  %xmm0,-0x8(%rbp)
movsd  %xmm1,-0x10(%rbp)
mov    $0x0,%al
call   1030 <rand@plt>
mov    0x2eb8(%rip),%rax
cvtsi2sdq (%rax),%xmm1
divsd  %xmm1,%xmm0
movsd  -0x10(%rbp),%xmm2
subsd  -0x8(%rbp),%xmm2
movsd  -0x8(%rbp),%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<unif>:
sub    $0x18,%rsp
movsd  %xmm1,0x10(%rsp)
movsd  %xmm0,0x8(%rsp)
xor    %eax,%eax
call   1030 <rand@plt>
mov    0x2eba(%rip),%rax
xorps  %xmm1,%xmm1
cvtsi2sdq (%rax),%xmm1
divsd  %xmm1,%xmm0
movsd  0x8(%rsp),%xmm1
movsd  0x10(%rsp),%xmm2
subsd  %xmm1,%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
add    $0x18,%rsp
ret

LLVM IR (-O0):
@RAND_MAX = global i64 0
define double @unif(double %0, double %1) {
%3 = alloca double
%4 = alloca double
store double %0, double* %3
store double %1, double* %4
%5 = call double (...) @rand()
%6 = load i64, i64* @RAND_MAX
%7 = sitofp i64 %6 to double
%8 = fdiv double %5, %7
%9 = load double, double* %4
%10 = load double, double* %3
%11 = fsub double %9, %10
%12 = load double, double* %3
%13 = call double @llvm.fmuladd.f64(double %8, double %11, double %12)
ret double %13
}

LLVM IR (-O2):
@RAND_MAX = global i64 0
define double @unif(double %0, double %1) {
%3 = tail call double (...) @rand()
%4 = load i64, i64* @RAND_MAX
%5 = sitofp i64 %4 to double
%6 = fdiv double %3, %5
%7 = fsub double %1, %0
%8 = tail call double @llvm.fmuladd.f64(double %6, double %7, double %0)
ret double %8
}
/* Variables and functions */
int /*<<< orphan*/ spd_set_drb();
void sdram_set_spd_registers(void) { spd_set_drb(); }


x86 assembly (clang, -O0):
<sdram_set_spd_registers>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <spd_set_drb@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<sdram_set_spd_registers>:
xor    %eax,%eax
jmp    1030 <spd_set_drb@plt>

LLVM IR (-O0):
define void @sdram_set_spd_registers() {
%1 = call i32 (...) @spd_set_drb()
ret void
}

LLVM IR (-O2):
define void @sdram_set_spd_registers() {
%1 = tail call i32 (...) @spd_set_drb()
ret void
}
int ms_gcd(int m, int n) {
  while (n != 0) {
    int t = m % n;
    m = n;
    n = t;
  }
  return m;
}


x86 assembly (clang, -O0):
<ms_gcd>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
cmpl   $0x0,-0x8(%rbp)
je     112f <ms_gcd+0x2f>
mov    -0x4(%rbp),%eax
cltd
idivl  -0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x4(%rbp)
mov    -0xc(%rbp),%eax
mov    %eax,-0x8(%rbp)
jmp    110a <ms_gcd+0xa>
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ms_gcd>:
mov    %edi,%eax
test   %esi,%esi
je     111d <ms_gcd+0x1d>
mov    %esi,%edx
nopl   0x0(%rax,%rax,1)
mov    %edx,%ecx
cltd
idiv   %ecx
mov    %ecx,%eax
test   %edx,%edx
jne    1110 <ms_gcd+0x10>
mov    %ecx,%eax
ret

LLVM IR (-O0):
define i32 @ms_gcd(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
br label %6
6: ; preds = %9, %2
%7 = load i32, i32* %4
%8 = icmp ne i32 %7, 0
br i1 %8, label %9, label %15
9: ; preds = %6
%10 = load i32, i32* %3
%11 = load i32, i32* %4
%12 = srem i32 %10, %11
store i32 %12, i32* %5
%13 = load i32, i32* %4
store i32 %13, i32* %3
%14 = load i32, i32* %5
store i32 %14, i32* %4
br label %6
15: ; preds = %6
%16 = load i32, i32* %3
ret i32 %16
}

LLVM IR (-O2):
define i32 @ms_gcd(i32 %0, i32 %1) {
%3 = icmp eq i32 %1, 0
br i1 %3, label %9, label %4
4: ; preds = %2, %4
%5 = phi i32 [ %6, %4 ], [ %0, %2 ]
%6 = phi i32 [ %7, %4 ], [ %1, %2 ]
%7 = srem i32 %5, %6
%8 = icmp eq i32 %7, 0
br i1 %8, label %9, label %4
9: ; preds = %4, %2
%10 = phi i32 [ %0, %2 ], [ %6, %4 ]
ret i32 %10
}
/* Type definitions */
typedef int /*<<< orphan*/ iconv_t;

/* Variables and functions */
size_t __bsd_iconv(int /*<<< orphan*/, char const **, size_t *, char **,
                   size_t *);
size_t iconv_compat(iconv_t a, const char **__restrict b, size_t *__restrict c,
                    char **__restrict d, size_t *__restrict e) {
  return __bsd_iconv(a, b, c, d, e);
}


x86 assembly (clang, -O0):
<iconv_compat>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8,-0x28(%rbp)
mov    -0x4(%rbp),%edi
mov    -0x10(%rbp),%rsi
mov    -0x18(%rbp),%rdx
mov    -0x20(%rbp),%rcx
mov    -0x28(%rbp),%r8
call   1030 <__bsd_iconv@plt>
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<iconv_compat>:
jmp    1030 <__bsd_iconv@plt>

LLVM IR (-O0):
define i64 @iconv_compat(i32 %0, i8** noalias %1, i64* noalias %2, i8** noalias %3, i64* noalias %4) {
%6 = alloca i32
%7 = alloca i8**
%8 = alloca i64*
%9 = alloca i8**
%10 = alloca i64*
store i32 %0, i32* %6
store i8** %1, i8*** %7
store i64* %2, i64** %8
store i8** %3, i8*** %9
store i64* %4, i64** %10
%11 = load i32, i32* %6
%12 = load i8**, i8*** %7
%13 = load i64*, i64** %8
%14 = load i8**, i8*** %9
%15 = load i64*, i64** %10
%16 = call i64 @__bsd_iconv(i32 %11, i8** %12, i64* %13, i8** %14, i64* %15)
ret i64 %16
}

LLVM IR (-O2):
define i64 @iconv_compat(i32 %0, i8** noalias %1, i64* noalias %2, i8** noalias %3, i64* noalias %4) {
%6 = tail call i64 @__bsd_iconv(i32 %0, i8** %1, i64* %2, i8** %3, i64* %4)
ret i64 %6
}
/* Variables and functions */
int /*<<< orphan*/ __asid_setup(int, int, int, int);
extern void r4xx0_asid_setup(void) { __asid_setup(1, 0xff, 0xff00, 0x100); }


x86 assembly (clang, -O0):
<r4xx0_asid_setup>:
push   %rbp
mov    %rsp,%rbp
mov    $0x1,%edi
mov    $0xff,%esi
mov    $0xff00,%edx
mov    $0x100,%ecx
call   1030 <__asid_setup@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<r4xx0_asid_setup>:
mov    $0x1,%edi
mov    $0xff,%esi
mov    $0xff00,%edx
mov    $0x100,%ecx
jmp    1030 <__asid_setup@plt>

LLVM IR (-O0):
define void @r4xx0_asid_setup() {
%1 = call i32 @__asid_setup(i32 1, i32 255, i32 65280, i32 256)
ret void
}

LLVM IR (-O2):
define void @r4xx0_asid_setup() {
%1 = tail call i32 @__asid_setup(i32 1, i32 255, i32 65280, i32 256)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ EZI2C_EzI2CStop();
void EZI2C_ScbModeStop(void) { EZI2C_EzI2CStop(); }


x86 assembly (clang, -O0):
<EZI2C_ScbModeStop>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <EZI2C_EzI2CStop@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<EZI2C_ScbModeStop>:
xor    %eax,%eax
jmp    1030 <EZI2C_EzI2CStop@plt>

LLVM IR (-O0):
define void @EZI2C_ScbModeStop() {
%1 = call i32 (...) @EZI2C_EzI2CStop()
ret void
}

LLVM IR (-O2):
define void @EZI2C_ScbModeStop() {
%1 = tail call i32 (...) @EZI2C_EzI2CStop()
ret void
}
/* Variables and functions */
int ft_strlen(char const *);
int /*<<< orphan*/ write(int, char const *, int);
void ft_putendl(char const *s) {
  write(1, s, ft_strlen(s));
  write(1, "\n", 1);
}


x86 assembly (clang, -O0):
<ft_putendl>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
call   1040 <ft_strlen@plt>
mov    -0x10(%rbp),%rsi
mov    %eax,%edx
mov    $0x1,%edi
call   1030 <write@plt>
mov    $0x1,%edx
lea    0xea7(%rip),%rsi
mov    %edx,%edi
call   1030 <write@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ft_putendl>:
push   %rbx
mov    %rdi,%rbx
call   1040 <ft_strlen@plt>
mov    $0x1,%edi
mov    %rbx,%rsi
mov    %eax,%edx
call   1030 <write@plt>
lea    0xec1(%rip),%rsi
mov    $0x1,%edi
mov    $0x1,%edx
pop    %rbx
jmp    1030 <write@plt>

LLVM IR (-O0):
@.str = [2 x i8] c"\0A\00"
define void @ft_putendl(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = load i8*, i8** %2
%5 = call i32 @ft_strlen(i8* %4)
%6 = call i32 @write(i32 1, i8* %3, i32 %5)
%7 = call i32 @write(i32 1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0), i32 1)
ret void
}

LLVM IR (-O2):
@.str = [2 x i8] c"\0A\00"
define void @ft_putendl(i8* %0) {
%2 = tail call i32 @ft_strlen(i8* %0)
%3 = tail call i32 @write(i32 1, i8* %0, i32 %2)
%4 = tail call i32 @write(i32 1, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0), i32 1)
ret void
}
int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz) { return 0; }


x86 assembly (clang, -O0):
<thermal_add_hwmon_sysfs>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<thermal_add_hwmon_sysfs>:
xor    %eax,%eax
ret

LLVM IR (-O0):
%struct.thermal_zone_device = type opaque
define i32 @thermal_add_hwmon_sysfs(%struct.thermal_zone_device* %0) {
%2 = alloca %struct.thermal_zone_device*
store %struct.thermal_zone_device* %0, %struct.thermal_zone_device** %2
ret i32 0
}

LLVM IR (-O2):
%struct.thermal_zone_device = type opaque
define i32 @thermal_add_hwmon_sysfs(%struct.thermal_zone_device* nocapture readnone %0) {
ret i32 0
}
const char *sbgEComGetVersionAsString(void) { return "1.3.0.0"; }


x86 assembly (clang, -O0):
<sbgEComGetVersionAsString>:
push   %rbp
mov    %rsp,%rbp
lea    0xef5(%rip),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<sbgEComGetVersionAsString>:
lea    0xef9(%rip),%rax
ret

LLVM IR (-O0):
@.str = [8 x i8] c"1.3.0.0\00"
define i8* @sbgEComGetVersionAsString() {
ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0)
}

LLVM IR (-O2):
@.str = [8 x i8] c"1.3.0.0\00"
define i8* @sbgEComGetVersionAsString() {
ret i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0)
}
/* Variables and functions */
void *malloc(size_t size) { return NULL; }


x86 assembly (clang, -O0):
<malloc>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<malloc>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i8* @malloc(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
ret i8* null
}

LLVM IR (-O2):
define noalias i8* @malloc(i64 %0) {
ret i8* null
}
/* Variables and functions */
int bmm050_compensate_X(short, unsigned short);
signed int bmm050_compensate_X_s32(signed short mdata_x,
                                   unsigned short data_R) {
  signed int retval;
  retval = bmm050_compensate_X(mdata_x, data_R);
  if (retval == (signed int)-32768) {
    retval = ((signed int)(-2147483647 - 1));
  }
  return retval;
}


x86 assembly (clang, -O0):
<bmm050_compensate_X_s32>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %si,%ax
mov    %di,%cx
mov    %cx,-0x2(%rbp)
mov    %ax,-0x4(%rbp)
mov    -0x2(%rbp),%ax
movswl %ax,%edi
movzwl -0x4(%rbp),%esi
call   1030 <bmm050_compensate_X@plt>
mov    %eax,-0x8(%rbp)
cmpl   $0xffff8000,-0x8(%rbp)
jne    114d <bmm050_compensate_X_s32+0x3d>
movl   $0x80000000,-0x8(%rbp)
mov    -0x8(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<bmm050_compensate_X_s32>:
push   %rax
call   1030 <bmm050_compensate_X@plt>
cmp    $0xffff8000,%eax
mov    $0x80000000,%ecx
cmove  %ecx,%eax
pop    %rcx
ret

LLVM IR (-O0):
define i32 @bmm050_compensate_X_s32(i16 signext %0, i16 zeroext %1) {
%3 = alloca i16
%4 = alloca i16
%5 = alloca i32
store i16 %0, i16* %3
store i16 %1, i16* %4
%6 = load i16, i16* %3
%7 = load i16, i16* %4
%8 = call i32 @bmm050_compensate_X(i16 signext %6, i16 zeroext %7)
store i32 %8, i32* %5
%9 = load i32, i32* %5
%10 = icmp eq i32 %9, -32768
br i1 %10, label %11, label %12
11: ; preds = %2
store i32 -2147483648, i32* %5
br label %12
12: ; preds = %11, %2
%13 = load i32, i32* %5
ret i32 %13
}

LLVM IR (-O2):
define i32 @bmm050_compensate_X_s32(i16 signext %0, i16 zeroext %1) {
%3 = tail call i32 @bmm050_compensate_X(i16 signext %0, i16 zeroext %1)
%4 = icmp eq i32 %3, -32768
%5 = select i1 %4, i32 -2147483648, i32 %3
ret i32 %5
}
/* Variables and functions */
int /*<<< orphan*/ fgets(char *, int, int /*<<< orphan*/);
int /*<<< orphan*/ hash(char *);
int /*<<< orphan*/ stdin;
int main() {
  char word[200];
  fgets(word, 200, stdin);
  hash(word);
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0xd0,%rsp
movl   $0x0,-0x4(%rbp)
lea    -0xd0(%rbp),%rdi
mov    0x2ea8(%rip),%rax
mov    (%rax),%edx
mov    $0xc8,%esi
call   1040 <fgets@plt>
lea    -0xd0(%rbp),%rdi
call   1030 <hash@plt>
xor    %eax,%eax
add    $0xd0,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rbx
sub    $0xd0,%rsp
mov    0x2eb9(%rip),%rax
mov    (%rax),%edx
mov    %rsp,%rbx
mov    %rbx,%rdi
mov    $0xc8,%esi
call   1040 <fgets@plt>
mov    %rbx,%rdi
call   1030 <hash@plt>
xor    %eax,%eax
add    $0xd0,%rsp
pop    %rbx
ret

LLVM IR (-O0):
@stdin = global i32 0
define i32 @main() {
%1 = alloca i32
%2 = alloca [200 x i8]
store i32 0, i32* %1
%3 = getelementptr inbounds [200 x i8], [200 x i8]* %2, i64 0, i64 0
%4 = load i32, i32* @stdin
%5 = call i32 @fgets(i8* %3, i32 200, i32 %4)
%6 = getelementptr inbounds [200 x i8], [200 x i8]* %2, i64 0, i64 0
%7 = call i32 @hash(i8* %6)
ret i32 0
}

LLVM IR (-O2):
@stdin = global i32 0
define i32 @main() {
%1 = alloca [200 x i8]
%2 = getelementptr inbounds [200 x i8], [200 x i8]* %1, i64 0, i64 0
%3 = load i32, i32* @stdin
%4 = call i32 @fgets(i8* %2, i32 200, i32 %3)
%5 = call i32 @hash(i8* %2)
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ free(void *);
void framework_aligned_free(void *ptr) { free(ptr); }


x86 assembly (clang, -O0):
<framework_aligned_free>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <free@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<framework_aligned_free>:
jmp    1030 <free@plt>

LLVM IR (-O0):
define void @framework_aligned_free(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = call i32 @free(i8* %3)
ret void
}

LLVM IR (-O2):
define void @framework_aligned_free(i8* nocapture %0) {
%2 = tail call i32 @free(i8* %0)
ret void
}
int urlenc_fromHex(int ch) {
  if (ch >= '0' && ch <= '9')
    return ch - '0';
  if (ch >= 'a' && ch <= 'f')
    return ch - ('a' - 10);
  if (ch >= 'A' && ch <= 'F')
    return ch - ('A' - 10);
  return 0;
}


x86 assembly (clang, -O0):
<urlenc_fromHex>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
cmpl   $0x30,-0x8(%rbp)
jl     1129 <urlenc_fromHex+0x29>
cmpl   $0x39,-0x8(%rbp)
jg     1129 <urlenc_fromHex+0x29>
mov    -0x8(%rbp),%eax
sub    $0x30,%eax
mov    %eax,-0x4(%rbp)
jmp    1174 <urlenc_fromHex+0x74>
cmpl   $0x61,-0x8(%rbp)
jl     114b <urlenc_fromHex+0x4b>
cmpl   $0x66,-0x8(%rbp)
jg     114b <urlenc_fromHex+0x4b>
mov    -0x8(%rbp),%eax
sub    $0x57,%eax
mov    %eax,-0x4(%rbp)
jmp    1174 <urlenc_fromHex+0x74>
cmpl   $0x41,-0x8(%rbp)
jl     116d <urlenc_fromHex+0x6d>
cmpl   $0x46,-0x8(%rbp)
jg     116d <urlenc_fromHex+0x6d>
mov    -0x8(%rbp),%eax
sub    $0x37,%eax
mov    %eax,-0x4(%rbp)
jmp    1174 <urlenc_fromHex+0x74>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<urlenc_fromHex>:
lea    -0x30(%rdi),%eax
cmp    $0xa,%eax
jb     1124 <urlenc_fromHex+0x24>
lea    -0x61(%rdi),%eax
cmp    $0x5,%eax
ja     1116 <urlenc_fromHex+0x16>
add    $0xffffffa9,%edi
mov    %edi,%eax
ret
lea    -0x41(%rdi),%ecx
add    $0xffffffc9,%edi
xor    %eax,%eax
cmp    $0x6,%ecx
cmovb  %edi,%eax
ret

LLVM IR (-O0):
define i32 @urlenc_fromHex(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp sge i32 %4, 48
br i1 %5, label %6, label %12
6: ; preds = %1
%7 = load i32, i32* %3
%8 = icmp sle i32 %7, 57
br i1 %8, label %9, label %12
9: ; preds = %6
%10 = load i32, i32* %3
%11 = sub nsw i32 %10, 48
store i32 %11, i32* %2
br label %31
12: ; preds = %6, %1
%13 = load i32, i32* %3
%14 = icmp sge i32 %13, 97
br i1 %14, label %15, label %21
15: ; preds = %12
%16 = load i32, i32* %3
%17 = icmp sle i32 %16, 102
br i1 %17, label %18, label %21
18: ; preds = %15
%19 = load i32, i32* %3
%20 = sub nsw i32 %19, 87
store i32 %20, i32* %2
br label %31
21: ; preds = %15, %12
%22 = load i32, i32* %3
%23 = icmp sge i32 %22, 65
br i1 %23, label %24, label %30
24: ; preds = %21
%25 = load i32, i32* %3
%26 = icmp sle i32 %25, 70
br i1 %26, label %27, label %30
27: ; preds = %24
%28 = load i32, i32* %3
%29 = sub nsw i32 %28, 55
store i32 %29, i32* %2
br label %31
30: ; preds = %24, %21
store i32 0, i32* %2
br label %31
31: ; preds = %30, %27, %18, %9
%32 = load i32, i32* %2
ret i32 %32
}

LLVM IR (-O2):
define i32 @urlenc_fromHex(i32 %0) {
%2 = add i32 %0, -48
%3 = icmp ult i32 %2, 10
br i1 %3, label %14, label %4
4: ; preds = %1
%5 = add i32 %0, -97
%6 = icmp ult i32 %5, 6
br i1 %6, label %7, label %9
7: ; preds = %4
%8 = add nsw i32 %0, -87
br label %14
9: ; preds = %4
%10 = add i32 %0, -65
%11 = icmp ult i32 %10, 6
%12 = add nsw i32 %0, -55
%13 = select i1 %11, i32 %12, i32 0
br label %14
14: ; preds = %1, %9, %7
%15 = phi i32 [ %8, %7 ], [ %13, %9 ], [ %2, %1 ]
ret i32 %15
}
/* Variables and functions */
int reverse_int(int);
int is_palindrome(int n) { return n == reverse_int(n); }


x86 assembly (clang, -O0):
<is_palindrome>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%edi
call   1030 <reverse_int@plt>
mov    %eax,%ecx
mov    -0x8(%rbp),%eax
cmp    %ecx,%eax
sete   %al
and    $0x1,%al
movzbl %al,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<is_palindrome>:
push   %rbx
mov    %edi,%ebx
call   1030 <reverse_int@plt>
xor    %ecx,%ecx
cmp    %ebx,%eax
sete   %cl
mov    %ecx,%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @is_palindrome(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = load i32, i32* %2
%5 = call i32 @reverse_int(i32 %4)
%6 = icmp eq i32 %3, %5
%7 = zext i1 %6 to i32
ret i32 %7
}

LLVM IR (-O2):
define i32 @is_palindrome(i32 %0) {
%2 = tail call i32 @reverse_int(i32 %0)
%3 = icmp eq i32 %2, %0
%4 = zext i1 %3 to i32
ret i32 %4
}
/* Variables and functions */
int /*<<< orphan*/ dcac_mask_ops(int, int);
void dcac_unlock(void) { dcac_mask_ops(48, -1); }


x86 assembly (clang, -O0):
<dcac_unlock>:
push   %rbp
mov    %rsp,%rbp
mov    $0x30,%edi
mov    $0xffffffff,%esi
call   1030 <dcac_mask_ops@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<dcac_unlock>:
mov    $0x30,%edi
mov    $0xffffffff,%esi
jmp    1030 <dcac_mask_ops@plt>

LLVM IR (-O0):
define void @dcac_unlock() {
%1 = call i32 @dcac_mask_ops(i32 48, i32 -1)
ret void
}

LLVM IR (-O2):
define void @dcac_unlock() {
%1 = tail call i32 @dcac_mask_ops(i32 48, i32 -1)
ret void
}
int divup(int a, int b) { return a / b + (a % b ? 1 : 0); }


x86 assembly (clang, -O0):
<divup>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x4(%rbp),%eax
cltd
idivl  -0x8(%rbp)
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
cltd
idivl  -0x8(%rbp)
mov    -0xc(%rbp),%eax
mov    %edx,%esi
xor    %ecx,%ecx
mov    $0x1,%edx
cmp    $0x0,%esi
cmovne %edx,%ecx
add    %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<divup>:
mov    %edi,%eax
cltd
idiv   %esi
cmp    $0x1,%edx
sbb    $0xffffffff,%eax
ret

LLVM IR (-O0):
define i32 @divup(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %3
%6 = load i32, i32* %4
%7 = sdiv i32 %5, %6
%8 = load i32, i32* %3
%9 = load i32, i32* %4
%10 = srem i32 %8, %9
%11 = icmp ne i32 %10, 0
%12 = zext i1 %11 to i64
%13 = select i1 %11, i32 1, i32 0
%14 = add nsw i32 %7, %13
ret i32 %14
}

LLVM IR (-O2):
define i32 @divup(i32 %0, i32 %1) {
%3 = sdiv i32 %0, %1
%4 = srem i32 %0, %1
%5 = icmp ne i32 %4, 0
%6 = zext i1 %5 to i32
%7 = add nsw i32 %3, %6
ret i32 %7
}
void Grille_init(char grille[10][10]) {
  int i, j;
  for (i = 0; i < 10; i++) {
    for (j = 0; j < 10; j++) {
      grille[i][j] = '*';
    }
  }
}


x86 assembly (clang, -O0):
<Grille_init>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
cmpl   $0xa,-0xc(%rbp)
jge    1162 <Grille_init+0x62>
movl   $0x0,-0x10(%rbp)
cmpl   $0xa,-0x10(%rbp)
jge    114f <Grille_init+0x4f>
mov    -0x8(%rbp),%rax
movslq -0xc(%rbp),%rcx
imul   $0xa,%rcx,%rcx
add    %rcx,%rax
movslq -0x10(%rbp),%rcx
movb   $0x2a,(%rax,%rcx,1)
mov    -0x10(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x10(%rbp)
jmp    1120 <Grille_init+0x20>
jmp    1154 <Grille_init+0x54>
mov    -0xc(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0xc(%rbp)
jmp    110f <Grille_init+0xf>
pop    %rbp
ret

x86 assembly (clang, -O2):
<Grille_init>:
movaps 0xef9(%rip),%xmm0
movups %xmm0,0x50(%rdi)
movups %xmm0,0x40(%rdi)
movups %xmm0,0x30(%rdi)
movups %xmm0,0x20(%rdi)
movups %xmm0,0x10(%rdi)
movups %xmm0,(%rdi)
movl   $0x2a2a2a2a,0x60(%rdi)
ret

LLVM IR (-O0):
define void @Grille_init([10 x i8]* %0) {
%2 = alloca [10 x i8]*
%3 = alloca i32
%4 = alloca i32
store [10 x i8]* %0, [10 x i8]** %2
store i32 0, i32* %3
br label %5
5: ; preds = %24, %1
%6 = load i32, i32* %3
%7 = icmp slt i32 %6, 10
br i1 %7, label %8, label %27
8: ; preds = %5
store i32 0, i32* %4
br label %9
9: ; preds = %20, %8
%10 = load i32, i32* %4
%11 = icmp slt i32 %10, 10
br i1 %11, label %12, label %23
12: ; preds = %9
%13 = load [10 x i8]*, [10 x i8]** %2
%14 = load i32, i32* %3
%15 = sext i32 %14 to i64
%16 = getelementptr inbounds [10 x i8], [10 x i8]* %13, i64 %15
%17 = load i32, i32* %4
%18 = sext i32 %17 to i64
%19 = getelementptr inbounds [10 x i8], [10 x i8]* %16, i64 0, i64 %18
store i8 42, i8* %19
br label %20
20: ; preds = %12
%21 = load i32, i32* %4
%22 = add nsw i32 %21, 1
store i32 %22, i32* %4
br label %9
23: ; preds = %9
br label %24
24: ; preds = %23
%25 = load i32, i32* %3
%26 = add nsw i32 %25, 1
store i32 %26, i32* %3
br label %5
27: ; preds = %5
ret void
}

LLVM IR (-O2):
define void @Grille_init([10 x i8]* nocapture writeonly %0) {
%2 = getelementptr [10 x i8], [10 x i8]* %0, i64 0, i64 0
ret void
}
unsigned long rewind_frame_pointer(int n) {
  struct stack_frame *frame;
  asm("movq %%rbp, %0" : "=r"(frame) :);
  return (unsigned long)frame;
}


x86 assembly (clang, -O0):
<rewind_frame_pointer>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %rbp,%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<rewind_frame_pointer>:
mov    %rbp,%rax
ret

LLVM IR (-O0):
%struct.stack_frame = type opaque
define i64 @rewind_frame_pointer(i32 %0) {
%2 = alloca i32
%3 = alloca %struct.stack_frame*
store i32 %0, i32* %2
%4 = call %struct.stack_frame* asm "movq %rbp, $0", "=r,~{dirflag},~{fpsr},~{flags}"()
store %struct.stack_frame* %4, %struct.stack_frame** %3
%5 = load %struct.stack_frame*, %struct.stack_frame** %3
%6 = ptrtoint %struct.stack_frame* %5 to i64
ret i64 %6
}

LLVM IR (-O2):
%struct.stack_frame = type opaque
define i64 @rewind_frame_pointer(i32 %0) {
%2 = tail call %struct.stack_frame* asm "movq %rbp, $0", "=r,~{dirflag},~{fpsr},~{flags}"()
%3 = ptrtoint %struct.stack_frame* %2 to i64
ret i64 %3
}
void kgsl_device_debugfs_init(struct kgsl_device *device) {}


x86 assembly (clang, -O0):
<kgsl_device_debugfs_init>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<kgsl_device_debugfs_init>:
ret

LLVM IR (-O0):
%struct.kgsl_device = type opaque
define void @kgsl_device_debugfs_init(%struct.kgsl_device* %0) {
%2 = alloca %struct.kgsl_device*
store %struct.kgsl_device* %0, %struct.kgsl_device** %2
ret void
}

LLVM IR (-O2):
%struct.kgsl_device = type opaque
define void @kgsl_device_debugfs_init(%struct.kgsl_device* nocapture %0) {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ uint32_t;
struct hle_t {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ UNKNOWN(struct hle_t *, int /*<<< orphan*/,
                           int /*<<< orphan*/);
void NAUDIO_0000(struct hle_t *hle, uint32_t w1, uint32_t w2) {
  UNKNOWN(hle, w1, w2);
}


x86 assembly (clang, -O0):
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %edx,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0xc(%rbp),%esi
mov    -0x10(%rbp),%edx
call   1030 <UNKNOWN@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
jmp    1030 <UNKNOWN@plt>

LLVM IR (-O0):
%struct.hle_t = type { i32 }
define void @NAUDIO_0000(%struct.hle_t* %0, i32 %1, i32 %2) {
%4 = alloca %struct.hle_t*
%5 = alloca i32
%6 = alloca i32
store %struct.hle_t* %0, %struct.hle_t** %4
store i32 %1, i32* %5
store i32 %2, i32* %6
%7 = load %struct.hle_t*, %struct.hle_t** %4
%8 = load i32, i32* %5
%9 = load i32, i32* %6
%10 = call i32 @UNKNOWN(%struct.hle_t* %7, i32 %8, i32 %9)
ret void
}

LLVM IR (-O2):
%struct.hle_t = type { i32 }
define void @NAUDIO_0000(%struct.hle_t* %0, i32 %1, i32 %2) {
%4 = tail call i32 @UNKNOWN(%struct.hle_t* %0, i32 %1, i32 %2)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ gets(char *);
int /*<<< orphan*/ printf(char *, char *);
int main(void) {
  char text[256] = {'\0'};
  gets(text);
  printf("text = %s\n", text);
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x110,%rsp
movl   $0x0,-0x4(%rbp)
lea    -0x110(%rbp),%rdi
xor    %esi,%esi
mov    $0x100,%edx
call   1040 <memset@plt>
lea    -0x110(%rbp),%rdi
call   1050 <gets@plt>
lea    -0x110(%rbp),%rsi
lea    0xe91(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
add    $0x110,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rbx
sub    $0x100,%rsp
xorps  %xmm0,%xmm0
movaps %xmm0,0xf0(%rsp)
movaps %xmm0,0xe0(%rsp)
movaps %xmm0,0xd0(%rsp)
movaps %xmm0,0xc0(%rsp)
movaps %xmm0,0xb0(%rsp)
movaps %xmm0,0xa0(%rsp)
movaps %xmm0,0x90(%rsp)
movaps %xmm0,0x80(%rsp)
movaps %xmm0,0x70(%rsp)
movaps %xmm0,0x60(%rsp)
movaps %xmm0,0x50(%rsp)
movaps %xmm0,0x40(%rsp)
movaps %xmm0,0x30(%rsp)
movaps %xmm0,0x20(%rsp)
movaps %xmm0,0x10(%rsp)
movaps %xmm0,(%rsp)
mov    %rsp,%rbx
mov    %rbx,%rdi
call   1040 <gets@plt>
lea    0xe5c(%rip),%rdi
mov    %rbx,%rsi
call   1030 <printf@plt>
xor    %eax,%eax
add    $0x100,%rsp
pop    %rbx
ret

LLVM IR (-O0):
@.str = [11 x i8] c"text = %s\0A\00"
define i32 @main() {
%1 = alloca i32
%2 = alloca [256 x i8]
store i32 0, i32* %1
%3 = bitcast [256 x i8]* %2 to i8*
%4 = getelementptr inbounds [256 x i8], [256 x i8]* %2, i64 0, i64 0
%5 = call i32 @gets(i8* %4)
%6 = getelementptr inbounds [256 x i8], [256 x i8]* %2, i64 0, i64 0
%7 = call i32 @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i8* %6)
ret i32 0
}

LLVM IR (-O2):
@.str = [11 x i8] c"text = %s\0A\00"
define i32 @main() {
%1 = alloca [256 x i8]
%2 = getelementptr inbounds [256 x i8], [256 x i8]* %1, i64 0, i64 0
%3 = call i32 @gets(i8* %2)
%4 = call i32 @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i64 0, i64 0), i8* %2)
ret i32 0
}
signed short signedshort_ignoring_unsignedshortint(signed short x,
                                                   unsigned short int y) {
  return x;
}


x86 assembly (clang, -O0):
<signedshort_ignoring_unsignedshortint>:
push   %rbp
mov    %rsp,%rbp
mov    %si,%ax
mov    %di,%cx
mov    %cx,-0x2(%rbp)
mov    %ax,-0x4(%rbp)
movswl -0x2(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<signedshort_ignoring_unsignedshortint>:
mov    %edi,%eax
ret

LLVM IR (-O0):
define signext i16 @signedshort_ignoring_unsignedshortint(i16 signext %0, i16 zeroext %1) {
%3 = alloca i16
%4 = alloca i16
store i16 %0, i16* %3
store i16 %1, i16* %4
%5 = load i16, i16* %3
ret i16 %5
}

LLVM IR (-O2):
define signext i16 @signedshort_ignoring_unsignedshortint(i16 returned signext %0, i16 zeroext %1) {
ret i16 %0
}
/* Variables and functions */
int /*<<< orphan*/ alwaysInline();
void use101() { alwaysInline(); }


x86 assembly (clang, -O0):
<use101>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <alwaysInline@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<use101>:
xor    %eax,%eax
jmp    1030 <alwaysInline@plt>

LLVM IR (-O0):
define void @use101() {
%1 = call i32 (...) @alwaysInline()
ret void
}

LLVM IR (-O2):
define void @use101() {
%1 = tail call i32 (...) @alwaysInline()
ret void
}
/* Variables and functions */
int /*<<< orphan*/ chdir(char *);
int /*<<< orphan*/ close(int);
int /*<<< orphan*/ sleep(int);
int /*<<< orphan*/ sync();
int main() {
  close(0);
  close(1);
  close(2);
  chdir("/");
  while (1) {
    sync();
    sleep(30);
  }
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x4(%rbp)
xor    %edi,%edi
call   1040 <close@plt>
mov    $0x1,%edi
call   1040 <close@plt>
mov    $0x2,%edi
call   1040 <close@plt>
lea    0xe8f(%rip),%rdi
call   1030 <chdir@plt>
mov    $0x0,%al
call   1050 <sync@plt>
mov    $0x1e,%edi
call   1060 <sleep@plt>
jmp    1176 <main+0x36>

x86 assembly (clang, -O2):
<main>:
push   %rax
xor    %edi,%edi
call   1040 <close@plt>
mov    $0x1,%edi
call   1040 <close@plt>
mov    $0x2,%edi
call   1040 <close@plt>
lea    0xe9d(%rip),%rdi
call   1030 <chdir@plt>
nopl   0x0(%rax,%rax,1)
xor    %eax,%eax
call   1050 <sync@plt>
mov    $0x1e,%edi
call   1060 <sleep@plt>
jmp    1170 <main+0x30>

LLVM IR (-O0):
@.str = [2 x i8] c"/\00"
define i32 @main() {
%1 = alloca i32
store i32 0, i32* %1
%2 = call i32 @close(i32 0)
%3 = call i32 @close(i32 1)
%4 = call i32 @close(i32 2)
%5 = call i32 @chdir(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
br label %6
6: ; preds = %0, %6
%7 = call i32 (...) @sync()
%8 = call i32 @sleep(i32 30)
br label %6
}

LLVM IR (-O2):
@.str = [2 x i8] c"/\00"
define i32 @main() {
%1 = tail call i32 @close(i32 0)
%2 = tail call i32 @close(i32 1)
%3 = tail call i32 @close(i32 2)
%4 = tail call i32 @chdir(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
br label %5
5: ; preds = %0, %5
%6 = tail call i32 (...) @sync()
%7 = tail call i32 @sleep(i32 30)
br label %5
}
void MHD_monotonic_sec_counter_finish(void) {}


x86 assembly (clang, -O0):
<MHD_monotonic_sec_counter_finish>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<MHD_monotonic_sec_counter_finish>:
ret

LLVM IR (-O0):
define void @MHD_monotonic_sec_counter_finish() {
ret void
}

LLVM IR (-O2):
define void @MHD_monotonic_sec_counter_finish() {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ wint_t;
typedef int /*<<< orphan*/ wchar_t;
typedef int /*<<< orphan*/ FILE;

/* Variables and functions */
int /*<<< orphan*/ _DIAGASSERT(int /*<<< orphan*/);
int /*<<< orphan*/ __fputwc_unlock(int /*<<< orphan*/, int /*<<< orphan*/ *);
wint_t fputwc(wchar_t wc, FILE *fp) {
  wint_t r;
  _DIAGASSERT(fp != NULL);
  ;
  r = __fputwc_unlock(wc, fp);
  ;
  return r;
}


x86 assembly (clang, -O0):
<fputwc>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x0,-0x10(%rbp)
setne  %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <_DIAGASSERT@plt>
mov    -0x4(%rbp),%edi
mov    -0x10(%rbp),%rsi
call   1040 <__fputwc_unlock@plt>
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<fputwc>:
push   %rbp
push   %rbx
push   %rax
mov    %rsi,%rbx
mov    %edi,%ebp
xor    %edi,%edi
test   %rsi,%rsi
setne  %dil
call   1030 <_DIAGASSERT@plt>
mov    %ebp,%edi
mov    %rbx,%rsi
add    $0x8,%rsp
pop    %rbx
pop    %rbp
jmp    1040 <__fputwc_unlock@plt>

LLVM IR (-O0):
define i32 @fputwc(i32 %0, i32* %1) {
%3 = alloca i32
%4 = alloca i32*
%5 = alloca i32
store i32 %0, i32* %3
store i32* %1, i32** %4
%6 = load i32*, i32** %4
%7 = icmp ne i32* %6, null
%8 = zext i1 %7 to i32
%9 = call i32 @_DIAGASSERT(i32 %8)
%10 = load i32, i32* %3
%11 = load i32*, i32** %4
%12 = call i32 @__fputwc_unlock(i32 %10, i32* %11)
store i32 %12, i32* %5
%13 = load i32, i32* %5
ret i32 %13
}

LLVM IR (-O2):
define i32 @fputwc(i32 %0, i32* %1) {
%3 = icmp ne i32* %1, null
%4 = zext i1 %3 to i32
%5 = tail call i32 @_DIAGASSERT(i32 %4)
%6 = tail call i32 @__fputwc_unlock(i32 %0, i32* %1)
ret i32 %6
}
/* Type definitions */
struct task_struct {
  int dummy;
};
struct rq {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ dec_nr_running(struct rq *);
void dequeue_task_stop(struct rq *rq, struct task_struct *p, int flags) {
  dec_nr_running(rq);
}


x86 assembly (clang, -O0):
<dequeue_task_stop>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %edx,-0x14(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <dec_nr_running@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<dequeue_task_stop>:
jmp    1030 <dec_nr_running@plt>

LLVM IR (-O0):
%struct.rq = type { i32 }
%struct.task_struct = type { i32 }
define void @dequeue_task_stop(%struct.rq* %0, %struct.task_struct* %1, i32 %2) {
%4 = alloca %struct.rq*
%5 = alloca %struct.task_struct*
%6 = alloca i32
store %struct.rq* %0, %struct.rq** %4
store %struct.task_struct* %1, %struct.task_struct** %5
store i32 %2, i32* %6
%7 = load %struct.rq*, %struct.rq** %4
%8 = call i32 @dec_nr_running(%struct.rq* %7)
ret void
}

LLVM IR (-O2):
%struct.rq = type { i32 }
%struct.task_struct = type { i32 }
define void @dequeue_task_stop(%struct.rq* %0, %struct.task_struct* nocapture readnone %1, i32 %2) {
%4 = tail call i32 @dec_nr_running(%struct.rq* %0)
ret void
}
int test_imm_54int64_lowword_mem(long long *val) {
  return ((*val) & (0x54 << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_54int64_lowword_mem>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    (%rax),%rdx
and    $0x54,%rdx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%rdx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_54int64_lowword_mem>:
testb  $0x54,(%rdi)
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_54int64_lowword_mem(i64* %0) {
%2 = alloca i64*
store i64* %0, i64** %2
%3 = load i64*, i64** %2
%4 = load i64, i64* %3
%5 = and i64 %4, 84
%6 = icmp ne i64 %5, 0
%7 = zext i1 %6 to i64
%8 = select i1 %6, i32 -20, i32 -40
ret i32 %8
}

LLVM IR (-O2):
define i32 @test_imm_54int64_lowword_mem(i64* nocapture %0) {
%2 = load i64, i64* %0
%3 = and i64 %2, 84
%4 = icmp eq i64 %3, 0
%5 = select i1 %4, i32 -40, i32 -20
ret i32 %5
}
void glmQuaternionFromVectorAndScalarf(float q[4], const float v[3],
                                       const float w) {
  q[0] = w;
  q[1] = v[0];
  q[2] = v[1];
  q[3] = v[2];
}


x86 assembly (clang, -O0):
<glmQuaternionFromVectorAndScalarf>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
movss  %xmm0,-0x14(%rbp)
movss  -0x14(%rbp),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,(%rax)
mov    -0x10(%rbp),%rax
movss  (%rax),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,0x4(%rax)
mov    -0x10(%rbp),%rax
movss  0x4(%rax),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,0x8(%rax)
mov    -0x10(%rbp),%rax
movss  0x8(%rax),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,0xc(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<glmQuaternionFromVectorAndScalarf>:
movss  %xmm0,(%rdi)
movss  (%rsi),%xmm0
movss  %xmm0,0x4(%rdi)
movss  0x4(%rsi),%xmm0
movss  %xmm0,0x8(%rdi)
movss  0x8(%rsi),%xmm0
movss  %xmm0,0xc(%rdi)
ret

LLVM IR (-O0):
define void @glmQuaternionFromVectorAndScalarf(float* %0, float* %1, float %2) {
%4 = alloca float*
%5 = alloca float*
%6 = alloca float
store float* %0, float** %4
store float* %1, float** %5
store float %2, float* %6
%7 = load float, float* %6
%8 = load float*, float** %4
%9 = getelementptr inbounds float, float* %8, i64 0
store float %7, float* %9
%10 = load float*, float** %5
%11 = getelementptr inbounds float, float* %10, i64 0
%12 = load float, float* %11
%13 = load float*, float** %4
%14 = getelementptr inbounds float, float* %13, i64 1
store float %12, float* %14
%15 = load float*, float** %5
%16 = getelementptr inbounds float, float* %15, i64 1
%17 = load float, float* %16
%18 = load float*, float** %4
%19 = getelementptr inbounds float, float* %18, i64 2
store float %17, float* %19
%20 = load float*, float** %5
%21 = getelementptr inbounds float, float* %20, i64 2
%22 = load float, float* %21
%23 = load float*, float** %4
%24 = getelementptr inbounds float, float* %23, i64 3
store float %22, float* %24
ret void
}

LLVM IR (-O2):
define void @glmQuaternionFromVectorAndScalarf(float* nocapture writeonly %0, float* nocapture %1, float %2) {
store float %2, float* %0
%4 = load float, float* %1
%5 = getelementptr inbounds float, float* %0, i64 1
store float %4, float* %5
%6 = getelementptr inbounds float, float* %1, i64 1
%7 = load float, float* %6
%8 = getelementptr inbounds float, float* %0, i64 2
store float %7, float* %8
%9 = getelementptr inbounds float, float* %1, i64 2
%10 = load float, float* %9
%11 = getelementptr inbounds float, float* %0, i64 3
store float %10, float* %11
ret void
}
void gtk_tree_view_insert_column() {}


x86 assembly (clang, -O0):
<gtk_tree_view_insert_column>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gtk_tree_view_insert_column>:
ret

LLVM IR (-O0):
define void @gtk_tree_view_insert_column() {
ret void
}

LLVM IR (-O2):
define void @gtk_tree_view_insert_column() {
ret void
}