unsigned char linear2ulaw(sample)
long sample;
{
  static int exp_lut[256] = {
      0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,
      4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
      5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
  int sign, exponent, mantissa;
  unsigned char ulawbyte;
  sign = (sample >> 8) & 0x80;
  if (sign != 0)
    sample = -sample;
  if (sample > 32635)
    sample = 32635;
  sample = sample + 0x84;
  exponent = exp_lut[(sample >> 7) & 0xFF];
  mantissa = (sample >> (exponent + 3)) & 0x0F;
  ulawbyte = ~(sign | (exponent << 4) | mantissa);
  return (ulawbyte);
}


x86 assembly (clang, -O0):
<linear2ulaw>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
sar    $0x8,%rax
and    $0x80,%rax
mov    %eax,-0xc(%rbp)
cmpl   $0x0,-0xc(%rbp)
je     112d <linear2ulaw+0x2d>
xor    %eax,%eax
sub    -0x8(%rbp),%rax
mov    %rax,-0x8(%rbp)
cmpq   $0x7f7b,-0x8(%rbp)
jle    1143 <linear2ulaw+0x43>
movq   $0x7f7b,-0x8(%rbp)
mov    -0x8(%rbp),%rax
add    $0x84,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rcx
sar    $0x7,%rcx
and    $0xff,%rcx
lea    0x2ec9(%rip),%rax
mov    (%rax,%rcx,4),%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x10(%rbp),%ecx
add    $0x3,%ecx
mov    %ecx,%ecx
sar    %cl,%rax
and    $0xf,%rax
mov    %eax,-0x14(%rbp)
mov    -0xc(%rbp),%eax
mov    -0x10(%rbp),%ecx
shl    $0x4,%ecx
or     %ecx,%eax
or     -0x14(%rbp),%eax
xor    $0xffffffff,%eax
mov    %al,-0x15(%rbp)
movzbl -0x15(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<linear2ulaw>:
mov    %edi,%edx
shr    $0x8,%edx
and    $0x80,%edx
mov    %rdi,%rax
neg    %rax
test   %edx,%edx
cmove  %rdi,%rax
cmp    $0x7f7b,%rax
mov    $0x7f7b,%esi
cmovl  %rax,%rsi
add    $0x84,%rsi
mov    %rsi,%rax
shr    $0x5,%rax
and    $0x3fc,%eax
lea    0xec0(%rip),%rcx
mov    (%rax,%rcx,1),%eax
lea    0x3(%rax),%ecx
sar    %cl,%rsi
and    $0xf,%esi
shl    $0x4,%eax
or     %edx,%eax
or     %esi,%eax
not    %al
ret

LLVM IR (-O0):
@linear2ulaw.exp_lut = internal global [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @linear2ulaw(i64 %0) {
%2 = alloca i64
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i8
store i64 %0, i64* %2
%7 = load i64, i64* %2
%8 = ashr i64 %7, 8
%9 = and i64 %8, 128
%10 = trunc i64 %9 to i32
store i32 %10, i32* %3
%11 = load i32, i32* %3
%12 = icmp ne i32 %11, 0
br i1 %12, label %13, label %16
13: ; preds = %1
%14 = load i64, i64* %2
%15 = sub nsw i64 0, %14
store i64 %15, i64* %2
br label %16
16: ; preds = %13, %1
%17 = load i64, i64* %2
%18 = icmp sgt i64 %17, 32635
br i1 %18, label %19, label %20
19: ; preds = %16
store i64 32635, i64* %2
br label %20
20: ; preds = %19, %16
%21 = load i64, i64* %2
%22 = add nsw i64 %21, 132
store i64 %22, i64* %2
%23 = load i64, i64* %2
%24 = ashr i64 %23, 7
%25 = and i64 %24, 255
%26 = getelementptr inbounds [256 x i32], [256 x i32]* @linear2ulaw.exp_lut, i64 0, i64 %25
%27 = load i32, i32* %26
store i32 %27, i32* %4
%28 = load i64, i64* %2
%29 = load i32, i32* %4
%30 = add nsw i32 %29, 3
%31 = zext i32 %30 to i64
%32 = ashr i64 %28, %31
%33 = and i64 %32, 15
%34 = trunc i64 %33 to i32
store i32 %34, i32* %5
%35 = load i32, i32* %3
%36 = load i32, i32* %4
%37 = shl i32 %36, 4
%38 = or i32 %35, %37
%39 = load i32, i32* %5
%40 = or i32 %38, %39
%41 = xor i32 %40, -1
%42 = trunc i32 %41 to i8
store i8 %42, i8* %6
%43 = load i8, i8* %6
ret i8 %43
}

LLVM IR (-O2):
@linear2ulaw.exp_lut = internal unnamed_addr constant [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @linear2ulaw(i64 %0) {
%2 = trunc i64 %0 to i32
%3 = lshr i32 %2, 8
%4 = and i32 %3, 128
%5 = icmp eq i32 %4, 0
%6 = sub nsw i64 0, %0
%7 = select i1 %5, i64 %0, i64 %6
%8 = icmp slt i64 %7, 32635
%9 = select i1 %8, i64 %7, i64 32635
%10 = add nsw i64 %9, 132
%11 = lshr i64 %10, 7
%12 = and i64 %11, 255
%13 = getelementptr inbounds [256 x i32], [256 x i32]* @linear2ulaw.exp_lut, i64 0, i64 %12
%14 = load i32, i32* %13
%15 = add nsw i32 %14, 3
%16 = zext i32 %15 to i64
%17 = ashr i64 %10, %16
%18 = trunc i64 %17 to i32
%19 = and i32 %18, 15
%20 = shl i32 %14, 4
%21 = or i32 %20, %4
%22 = or i32 %21, %19
%23 = trunc i32 %22 to i8
%24 = xor i8 %23, -1
ret i8 %24
}