void BSP_Timer_InterruptInit(unsigned int timerIndex) {
  if (timerIndex == 0) {
    (*(volatile unsigned *)0x4a000008) &= ~(0x1 << 10);
  } else if (timerIndex == 1) {
    (*(volatile unsigned *)0x4a000008) &= ~(0x1 << 11);
  } else if (timerIndex == 2) {
    (*(volatile unsigned *)0x4a000008) &= ~(0x1 << 12);
  } else if (timerIndex == 3) {
    (*(volatile unsigned *)0x4a000008) &= ~(0x1 << 13);
  } else {
    (*(volatile unsigned *)0x4a000008) &= ~(0x1 << 14);
  }
}


x86 assembly (clang, -O0):
<BSP_Timer_InterruptInit>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
cmpl   $0x0,-0x4(%rbp)
jne    112a <BSP_Timer_InterruptInit+0x2a>
mov    $0x4a000008,%eax
mov    (%rax),%ecx
and    $0xfffffbff,%ecx
mov    $0x4a000008,%eax
mov    %ecx,(%rax)
jmp    11b6 <BSP_Timer_InterruptInit+0xb6>
cmpl   $0x1,-0x4(%rbp)
jne    114d <BSP_Timer_InterruptInit+0x4d>
mov    $0x4a000008,%eax
mov    (%rax),%ecx
and    $0xfffff7ff,%ecx
mov    $0x4a000008,%eax
mov    %ecx,(%rax)
jmp    11b1 <BSP_Timer_InterruptInit+0xb1>
cmpl   $0x2,-0x4(%rbp)
jne    1170 <BSP_Timer_InterruptInit+0x70>
mov    $0x4a000008,%eax
mov    (%rax),%ecx
and    $0xffffefff,%ecx
mov    $0x4a000008,%eax
mov    %ecx,(%rax)
jmp    11ac <BSP_Timer_InterruptInit+0xac>
cmpl   $0x3,-0x4(%rbp)
jne    1193 <BSP_Timer_InterruptInit+0x93>
mov    $0x4a000008,%eax
mov    (%rax),%ecx
and    $0xffffdfff,%ecx
mov    $0x4a000008,%eax
mov    %ecx,(%rax)
jmp    11a7 <BSP_Timer_InterruptInit+0xa7>
mov    $0x4a000008,%eax
mov    (%rax),%ecx
and    $0xffffbfff,%ecx
mov    $0x4a000008,%eax
mov    %ecx,(%rax)
jmp    11ac <BSP_Timer_InterruptInit+0xac>
jmp    11b1 <BSP_Timer_InterruptInit+0xb1>
jmp    11b6 <BSP_Timer_InterruptInit+0xb6>
pop    %rbp
ret

x86 assembly (clang, -O2):
<BSP_Timer_InterruptInit>:
mov    $0xffffbfff,%eax
cmp    $0x3,%edi
ja     1117 <BSP_Timer_InterruptInit+0x17>
movslq %edi,%rax
lea    0xeec(%rip),%rcx
mov    (%rcx,%rax,4),%eax
and    %eax,0x4a000008
ret

LLVM IR (-O0):
define void @BSP_Timer_InterruptInit(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp eq i32 %3, 0
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%7 = and i32 %6, -1025
store volatile i32 %7, i32* inttoptr (i64 1241513992 to i32*)
br label %32
8: ; preds = %1
%9 = load i32, i32* %2
%10 = icmp eq i32 %9, 1
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%13 = and i32 %12, -2049
store volatile i32 %13, i32* inttoptr (i64 1241513992 to i32*)
br label %31
14: ; preds = %8
%15 = load i32, i32* %2
%16 = icmp eq i32 %15, 2
br i1 %16, label %17, label %20
17: ; preds = %14
%18 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%19 = and i32 %18, -4097
store volatile i32 %19, i32* inttoptr (i64 1241513992 to i32*)
br label %30
20: ; preds = %14
%21 = load i32, i32* %2
%22 = icmp eq i32 %21, 3
br i1 %22, label %23, label %26
23: ; preds = %20
%24 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%25 = and i32 %24, -8193
store volatile i32 %25, i32* inttoptr (i64 1241513992 to i32*)
br label %29
26: ; preds = %20
%27 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%28 = and i32 %27, -16385
store volatile i32 %28, i32* inttoptr (i64 1241513992 to i32*)
br label %29
29: ; preds = %26, %23
br label %30
30: ; preds = %29, %17
br label %31
31: ; preds = %30, %11
br label %32
32: ; preds = %31, %5
ret void
}

LLVM IR (-O2):
@switch.table.BSP_Timer_InterruptInit = [4 x i32] [i32 -1025, i32 -2049, i32 -4097, i32 -8193]
define void @BSP_Timer_InterruptInit(i32 %0) {
%2 = icmp ult i32 %0, 4
br i1 %2, label %3, label %7
3: ; preds = %1
%4 = sext i32 %0 to i64
%5 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.BSP_Timer_InterruptInit, i64 0, i64 %4
%6 = load i32, i32* %5
br label %7
7: ; preds = %1, %3
%8 = phi i32 [ %6, %3 ], [ -16385, %1 ]
%9 = load volatile i32, i32* inttoptr (i64 1241513992 to i32*)
%10 = and i32 %9, %8
store volatile i32 %10, i32* inttoptr (i64 1241513992 to i32*)
ret void
}