void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
                      unsigned long ulData) {
  ;
  while ((*((volatile unsigned long *)(ulBase + 0x00000020))) & 0x00000001) {
  }
  (*((volatile unsigned long *)(ulBase + 0x0000002C))) = ulData & 0x0000FFFF;
  (*((volatile unsigned long *)(ulBase + 0x00000020))) =
      (((ucRegAddr << 3) & 0x000000F8) | 0x00000002 | 0x00000001);
  while ((*((volatile unsigned long *)(ulBase + 0x00000020))) & 0x00000001) {
  }
}


x86 assembly (clang, -O0):
<EthernetPHYWrite>:
push   %rbp
mov    %rsp,%rbp
mov    %sil,%al
mov    %rdi,-0x8(%rbp)
mov    %al,-0x9(%rbp)
mov    %rdx,-0x18(%rbp)
mov    -0x8(%rbp),%rax
mov    0x20(%rax),%rax
and    $0x1,%rax
cmp    $0x0,%rax
je     112d <EthernetPHYWrite+0x2d>
jmp    1112 <EthernetPHYWrite+0x12>
mov    -0x18(%rbp),%rcx
and    $0xffff,%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x2c(%rax)
movzbl -0x9(%rbp),%eax
shl    $0x3,%eax
and    $0xf8,%eax
or     $0x2,%eax
or     $0x1,%eax
movslq %eax,%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x20(%rax)
mov    -0x8(%rbp),%rax
mov    0x20(%rax),%rax
and    $0x1,%rax
cmp    $0x0,%rax
je     1178 <EthernetPHYWrite+0x78>
jmp    115d <EthernetPHYWrite+0x5d>
pop    %rbp
ret

x86 assembly (clang, -O2):
<EthernetPHYWrite>:
mov    0x20(%rdi),%rax
test   $0x1,%al
jne    1100 <EthernetPHYWrite>
movzwl %dx,%eax
mov    %rax,0x2c(%rdi)
movzbl %sil,%eax
lea    0x3(,%rax,8),%eax
movzbl %al,%eax
mov    %rax,0x20(%rdi)
cs nopw 0x0(%rax,%rax,1)
nopl   0x0(%rax,%rax,1)
mov    0x20(%rdi),%rax
test   $0x1,%al
jne    1130 <EthernetPHYWrite+0x30>
ret

LLVM IR (-O0):
define void @EthernetPHYWrite(i64 %0, i8 zeroext %1, i64 %2) {
%4 = alloca i64
%5 = alloca i8
%6 = alloca i64
store i64 %0, i64* %4
store i8 %1, i8* %5
store i64 %2, i64* %6
br label %7
7: ; preds = %14, %3
%8 = load i64, i64* %4
%9 = add i64 %8, 32
%10 = inttoptr i64 %9 to i64*
%11 = load volatile i64, i64* %10
%12 = and i64 %11, 1
%13 = icmp ne i64 %12, 0
br i1 %13, label %14, label %15
14: ; preds = %7
br label %7
15: ; preds = %7
%16 = load i64, i64* %6
%17 = and i64 %16, 65535
%18 = load i64, i64* %4
%19 = add i64 %18, 44
%20 = inttoptr i64 %19 to i64*
store volatile i64 %17, i64* %20
%21 = load i8, i8* %5
%22 = zext i8 %21 to i32
%23 = shl i32 %22, 3
%24 = and i32 %23, 248
%25 = or i32 %24, 2
%26 = or i32 %25, 1
%27 = sext i32 %26 to i64
%28 = load i64, i64* %4
%29 = add i64 %28, 32
%30 = inttoptr i64 %29 to i64*
store volatile i64 %27, i64* %30
br label %31
31: ; preds = %38, %15
%32 = load i64, i64* %4
%33 = add i64 %32, 32
%34 = inttoptr i64 %33 to i64*
%35 = load volatile i64, i64* %34
%36 = and i64 %35, 1
%37 = icmp ne i64 %36, 0
br i1 %37, label %38, label %39
38: ; preds = %31
br label %31
39: ; preds = %31
ret void
}

LLVM IR (-O2):
define void @EthernetPHYWrite(i64 %0, i8 zeroext %1, i64 %2) {
%4 = add i64 %0, 32
%5 = inttoptr i64 %4 to i64*
br label %6
6: ; preds = %6, %3
%7 = load volatile i64, i64* %5
%8 = and i64 %7, 1
%9 = icmp eq i64 %8, 0
br i1 %9, label %10, label %6
10: ; preds = %6
%11 = and i64 %2, 65535
%12 = add i64 %0, 44
%13 = inttoptr i64 %12 to i64*
store volatile i64 %11, i64* %13
%14 = zext i8 %1 to i64
%15 = shl nuw nsw i64 %14, 3
%16 = and i64 %15, 248
%17 = or i64 %16, 3
store volatile i64 %17, i64* %5
br label %18
18: ; preds = %18, %10
%19 = load volatile i64, i64* %5
%20 = and i64 %19, 1
%21 = icmp eq i64 %20, 0
br i1 %21, label %22, label %18
22: ; preds = %18
ret void
}