unsigned int altera_a10_cdr_lookup_vco_speed_fix(unsigned int fvco) {
  if (fvco < 6060000)
    return 60;
  else if (fvco < 7060000)
    return 74;
  else if (fvco < 9060000)
    return 90;
  else if (fvco < 11350000)
    return 116;
  else if (fvco < 12760000)
    return 150;
  else if (fvco < 13460000)
    return 159;
  else
    return 174;
}


x86 assembly (clang, -O0):
<altera_a10_cdr_lookup_vco_speed_fix>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
cmpl   $0x5c77e0,-0x8(%rbp)
jae    1120 <altera_a10_cdr_lookup_vco_speed_fix+0x20>
movl   $0x3c,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
cmpl   $0x6bba20,-0x8(%rbp)
jae    1139 <altera_a10_cdr_lookup_vco_speed_fix+0x39>
movl   $0x4a,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
cmpl   $0x8a3ea0,-0x8(%rbp)
jae    1152 <altera_a10_cdr_lookup_vco_speed_fix+0x52>
movl   $0x5a,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
cmpl   $0xad2ff0,-0x8(%rbp)
jae    116b <altera_a10_cdr_lookup_vco_speed_fix+0x6b>
movl   $0x74,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
cmpl   $0xc2b3c0,-0x8(%rbp)
jae    1184 <altera_a10_cdr_lookup_vco_speed_fix+0x84>
movl   $0x96,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
cmpl   $0xcd6220,-0x8(%rbp)
jae    119d <altera_a10_cdr_lookup_vco_speed_fix+0x9d>
movl   $0x9f,-0x4(%rbp)
jmp    11a4 <altera_a10_cdr_lookup_vco_speed_fix+0xa4>
movl   $0xae,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<altera_a10_cdr_lookup_vco_speed_fix>:
mov    $0x3c,%eax
cmp    $0x5c77e0,%edi
jb     1154 <altera_a10_cdr_lookup_vco_speed_fix+0x54>
mov    $0x4a,%eax
cmp    $0x6bba20,%edi
jb     1154 <altera_a10_cdr_lookup_vco_speed_fix+0x54>
mov    $0x5a,%eax
cmp    $0x8a3ea0,%edi
jb     1154 <altera_a10_cdr_lookup_vco_speed_fix+0x54>
mov    $0x74,%eax
cmp    $0xad2ff0,%edi
jb     1154 <altera_a10_cdr_lookup_vco_speed_fix+0x54>
mov    $0x96,%eax
cmp    $0xc2b3c0,%edi
jb     1154 <altera_a10_cdr_lookup_vco_speed_fix+0x54>
cmp    $0xcd6220,%edi
mov    $0x9f,%ecx
mov    $0xae,%eax
cmovb  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @altera_a10_cdr_lookup_vco_speed_fix(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp ult i32 %4, 6060000
br i1 %5, label %6, label %7
6: ; preds = %1
store i32 60, i32* %2
br label %28
7: ; preds = %1
%8 = load i32, i32* %3
%9 = icmp ult i32 %8, 7060000
br i1 %9, label %10, label %11
10: ; preds = %7
store i32 74, i32* %2
br label %28
11: ; preds = %7
%12 = load i32, i32* %3
%13 = icmp ult i32 %12, 9060000
br i1 %13, label %14, label %15
14: ; preds = %11
store i32 90, i32* %2
br label %28
15: ; preds = %11
%16 = load i32, i32* %3
%17 = icmp ult i32 %16, 11350000
br i1 %17, label %18, label %19
18: ; preds = %15
store i32 116, i32* %2
br label %28
19: ; preds = %15
%20 = load i32, i32* %3
%21 = icmp ult i32 %20, 12760000
br i1 %21, label %22, label %23
22: ; preds = %19
store i32 150, i32* %2
br label %28
23: ; preds = %19
%24 = load i32, i32* %3
%25 = icmp ult i32 %24, 13460000
br i1 %25, label %26, label %27
26: ; preds = %23
store i32 159, i32* %2
br label %28
27: ; preds = %23
store i32 174, i32* %2
br label %28
28: ; preds = %27, %26, %22, %18, %14, %10, %6
%29 = load i32, i32* %2
ret i32 %29
}

LLVM IR (-O2):
define i32 @altera_a10_cdr_lookup_vco_speed_fix(i32 %0) {
%2 = icmp ult i32 %0, 6060000
br i1 %2, label %14, label %3
3: ; preds = %1
%4 = icmp ult i32 %0, 7060000
br i1 %4, label %14, label %5
5: ; preds = %3
%6 = icmp ult i32 %0, 9060000
br i1 %6, label %14, label %7
7: ; preds = %5
%8 = icmp ult i32 %0, 11350000
br i1 %8, label %14, label %9
9: ; preds = %7
%10 = icmp ult i32 %0, 12760000
br i1 %10, label %14, label %11
11: ; preds = %9
%12 = icmp ult i32 %0, 13460000
%13 = select i1 %12, i32 159, i32 174
br label %14
14: ; preds = %11, %9, %7, %5, %3, %1
%15 = phi i32 [ 60, %1 ], [ 74, %3 ], [ 90, %5 ], [ 116, %7 ], [ 150, %9 ], [ %13, %11 ]
ret i32 %15
}