#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
                          uint32_t ui32Trigger, uint32_t ui32Priority) {
  ;
  ;

  ;
  ;
  ui32SequenceNum *= 4;
  (*((volatile uint32_t *)(ui32Base + 0x00000014))) =
      (((*((volatile uint32_t *)(ui32Base + 0x00000014))) &
        ~(0xf << ui32SequenceNum)) |
       ((ui32Trigger & 0xf) << ui32SequenceNum));
  (*((volatile uint32_t *)(ui32Base + 0x00000020))) =
      (((*((volatile uint32_t *)(ui32Base + 0x00000020))) &
        ~(0xf << ui32SequenceNum)) |
       ((ui32Priority & 0x3) << ui32SequenceNum));
  ui32SequenceNum *= 2;
  (*((volatile uint32_t *)(ui32Base + 0x0000001C))) =
      (((*((volatile uint32_t *)(ui32Base + 0x0000001C))) &
        ~(0x30 << ui32SequenceNum)) |
       ((ui32Trigger & 0x30) << ui32SequenceNum));
}


x86 assembly (clang, -O0):
<ADCSequenceConfigure>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    %ecx,-0x10(%rbp)
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%eax
add    $0x14,%eax
cltq
mov    (%rax),%eax
mov    -0x8(%rbp),%ecx
mov    $0xf,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x1c(%rbp)
mov    -0xc(%rbp),%eax
and    $0xf,%eax
mov    -0x8(%rbp),%ecx
shl    %cl,%eax
mov    -0x1c(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x14,%eax
cltq
mov    %ecx,(%rax)
mov    -0x4(%rbp),%eax
add    $0x20,%eax
cltq
mov    (%rax),%eax
mov    -0x8(%rbp),%ecx
mov    $0xf,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x18(%rbp)
mov    -0x10(%rbp),%eax
and    $0x3,%eax
mov    -0x8(%rbp),%ecx
shl    %cl,%eax
mov    -0x18(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x20,%eax
cltq
mov    %ecx,(%rax)
mov    -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
cltq
mov    (%rax),%eax
mov    -0x8(%rbp),%ecx
mov    $0x30,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x14(%rbp)
mov    -0xc(%rbp),%eax
and    $0x30,%eax
mov    -0x8(%rbp),%ecx
shl    %cl,%eax
mov    -0x14(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
cltq
mov    %ecx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCSequenceConfigure>:
mov    %ecx,%r8d
lea    0x0(,%rsi,4),%ecx
mov    $0xf,%eax
shl    %cl,%eax
movslq %edi,%r9
not    %eax
mov    0x14(%r9),%r10d
and    %eax,%r10d
mov    %edx,%edi
and    $0xf,%edi
shl    %cl,%edi
or     %r10d,%edi
mov    %edi,0x14(%r9)
and    0x20(%r9),%eax
and    $0x3,%r8d
shl    %cl,%r8d
or     %eax,%r8d
mov    %r8d,0x20(%r9)
lea    0x0(,%rsi,8),%ecx
mov    $0x30,%eax
shl    %cl,%eax
not    %eax
and    $0x30,%edx
shl    %cl,%edx
and    0x1c(%r9),%eax
or     %eax,%edx
mov    %edx,0x1c(%r9)
ret

LLVM IR (-O0):
define void @ADCSequenceConfigure(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
store i32 %0, i32* %5
store i32 %1, i32* %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%9 = load i32, i32* %6
%10 = mul nsw i32 %9, 4
store i32 %10, i32* %6
%11 = load i32, i32* %5
%12 = add nsw i32 %11, 20
%13 = sext i32 %12 to i64
%14 = inttoptr i64 %13 to i32*
%15 = load volatile i32, i32* %14
%16 = load i32, i32* %6
%17 = shl i32 15, %16
%18 = xor i32 %17, -1
%19 = and i32 %15, %18
%20 = load i32, i32* %7
%21 = and i32 %20, 15
%22 = load i32, i32* %6
%23 = shl i32 %21, %22
%24 = or i32 %19, %23
%25 = load i32, i32* %5
%26 = add nsw i32 %25, 20
%27 = sext i32 %26 to i64
%28 = inttoptr i64 %27 to i32*
store volatile i32 %24, i32* %28
%29 = load i32, i32* %5
%30 = add nsw i32 %29, 32
%31 = sext i32 %30 to i64
%32 = inttoptr i64 %31 to i32*
%33 = load volatile i32, i32* %32
%34 = load i32, i32* %6
%35 = shl i32 15, %34
%36 = xor i32 %35, -1
%37 = and i32 %33, %36
%38 = load i32, i32* %8
%39 = and i32 %38, 3
%40 = load i32, i32* %6
%41 = shl i32 %39, %40
%42 = or i32 %37, %41
%43 = load i32, i32* %5
%44 = add nsw i32 %43, 32
%45 = sext i32 %44 to i64
%46 = inttoptr i64 %45 to i32*
store volatile i32 %42, i32* %46
%47 = load i32, i32* %6
%48 = mul nsw i32 %47, 2
store i32 %48, i32* %6
%49 = load i32, i32* %5
%50 = add nsw i32 %49, 28
%51 = sext i32 %50 to i64
%52 = inttoptr i64 %51 to i32*
%53 = load volatile i32, i32* %52
%54 = load i32, i32* %6
%55 = shl i32 48, %54
%56 = xor i32 %55, -1
%57 = and i32 %53, %56
%58 = load i32, i32* %7
%59 = and i32 %58, 48
%60 = load i32, i32* %6
%61 = shl i32 %59, %60
%62 = or i32 %57, %61
%63 = load i32, i32* %5
%64 = add nsw i32 %63, 28
%65 = sext i32 %64 to i64
%66 = inttoptr i64 %65 to i32*
store volatile i32 %62, i32* %66
ret void
}

LLVM IR (-O2):
define void @ADCSequenceConfigure(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = shl nsw i32 %1, 2
%6 = add nsw i32 %0, 20
%7 = sext i32 %6 to i64
%8 = inttoptr i64 %7 to i32*
%9 = load volatile i32, i32* %8
%10 = shl i32 15, %5
%11 = xor i32 %10, -1
%12 = and i32 %9, %11
%13 = and i32 %2, 15
%14 = shl i32 %13, %5
%15 = or i32 %12, %14
store volatile i32 %15, i32* %8
%16 = add nsw i32 %0, 32
%17 = sext i32 %16 to i64
%18 = inttoptr i64 %17 to i32*
%19 = load volatile i32, i32* %18
%20 = and i32 %19, %11
%21 = and i32 %3, 3
%22 = shl i32 %21, %5
%23 = or i32 %20, %22
store volatile i32 %23, i32* %18
%24 = shl nsw i32 %1, 3
%25 = add nsw i32 %0, 28
%26 = sext i32 %25 to i64
%27 = inttoptr i64 %26 to i32*
%28 = load volatile i32, i32* %27
%29 = shl i32 48, %24
%30 = xor i32 %29, -1
%31 = and i32 %28, %30
%32 = and i32 %2, 48
%33 = shl i32 %32, %24
%34 = or i32 %31, %33
store volatile i32 %34, i32* %27
ret void
}