int computeSignal(int exceptionVector) {
  int sigval;
  switch (exceptionVector) {
  case 4:
    sigval = 4;
    break;
  case 6:
    sigval = 4;
    break;
  case 9:
    sigval = 10;
    break;
  case 10:
    sigval = 10;
    break;
  case 11:
    sigval = 2;
    break;
  case 32:
  case 127:
    sigval = 5;
    break;
  default:
    sigval = 7;
    break;
  }
  return (sigval);
}


x86 assembly (clang, -O0):
<computeSignal>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0xc(%rbp)
sub    $0x4,%eax
je     1181 <computeSignal+0x81>
jmp    111b <computeSignal+0x1b>
mov    -0xc(%rbp),%eax
sub    $0x6,%eax
je     118d <computeSignal+0x8d>
jmp    112c <computeSignal+0x2c>
mov    -0xc(%rbp),%eax
sub    $0x9,%eax
je     1199 <computeSignal+0x99>
jmp    113d <computeSignal+0x3d>
mov    -0xc(%rbp),%eax
sub    $0xa,%eax
je     11a5 <computeSignal+0xa5>
jmp    114e <computeSignal+0x4e>
mov    -0xc(%rbp),%eax
sub    $0xb,%eax
je     11b1 <computeSignal+0xb1>
jmp    115f <computeSignal+0x5f>
mov    -0xc(%rbp),%eax
sub    $0x20,%eax
je     11bd <computeSignal+0xbd>
jmp    1170 <computeSignal+0x70>
mov    -0xc(%rbp),%eax
sub    $0x7f,%eax
je     11bd <computeSignal+0xbd>
jmp    11c9 <computeSignal+0xc9>
movl   $0x4,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0x4,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0xa,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0xa,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0x2,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0x5,-0x8(%rbp)
jmp    11d0 <computeSignal+0xd0>
movl   $0x7,-0x8(%rbp)
mov    -0x8(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<computeSignal>:
lea    -0x4(%rdi),%ecx
cmp    $0x1c,%ecx
ja     1123 <computeSignal+0x23>
mov    $0x4,%eax
lea    0xeec(%rip),%rdx
movslq (%rdx,%rcx,4),%rcx
add    %rdx,%rcx
jmp    *%rcx
mov    $0xa,%eax
ret
cmp    $0x7f,%edi
jne    112e <computeSignal+0x2e>
mov    $0x5,%eax
ret
mov    $0x7,%eax
ret
mov    $0x2,%eax
ret

LLVM IR (-O0):
define i32 @computeSignal(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %2
%4 = load i32, i32* %2
switch i32 %4, label %11 [
i32 4, label %5
i32 6, label %6
i32 9, label %7
i32 10, label %8
i32 11, label %9
i32 32, label %10
i32 127, label %10
]
5: ; preds = %1
store i32 4, i32* %3
br label %12
6: ; preds = %1
store i32 4, i32* %3
br label %12
7: ; preds = %1
store i32 10, i32* %3
br label %12
8: ; preds = %1
store i32 10, i32* %3
br label %12
9: ; preds = %1
store i32 2, i32* %3
br label %12
10: ; preds = %1, %1
store i32 5, i32* %3
br label %12
11: ; preds = %1
store i32 7, i32* %3
br label %12
12: ; preds = %11, %10, %9, %8, %7, %6, %5
%13 = load i32, i32* %3
ret i32 %13
}

LLVM IR (-O2):
define i32 @computeSignal(i32 %0) {
switch i32 %0, label %6 [
i32 4, label %7
i32 6, label %7
i32 9, label %2
i32 10, label %3
i32 11, label %4
i32 32, label %5
i32 127, label %5
]
2: ; preds = %1
br label %7
3: ; preds = %1
br label %7
4: ; preds = %1
br label %7
5: ; preds = %1, %1
br label %7
6: ; preds = %1
br label %7
7: ; preds = %1, %1, %6, %5, %4, %3, %2
%8 = phi i32 [ 7, %6 ], [ 5, %5 ], [ 2, %4 ], [ 10, %3 ], [ 10, %2 ], [ 4, %1 ], [ 4, %1 ]
ret i32 %8
}