float ran1(idum)
int *idum;
{
  static long ix1, ix2, ix3;
  static float r[98];
  float temp;
  static int iff = 0;
  int j;
  void nrerror();
  if (*idum < 0 || iff == 0) {
    iff = 1;
    ix1 = (54773 - (*idum)) % 259200;
    ix1 = (7141 * ix1 + 54773) % 259200;
    ix2 = ix1 % 134456;
    ix1 = (7141 * ix1 + 54773) % 259200;
    ix3 = ix1 % 243000;
    for (j = 1; j <= 97; j++) {
      ix1 = (7141 * ix1 + 54773) % 259200;
      ix2 = (8121 * ix2 + 28411) % 134456;
      r[j] = (ix1 + ix2 * (1.0 / 134456)) * (1.0 / 259200);
    }
    *idum = 1;
  }
  ix1 = (7141 * ix1 + 54773) % 259200;
  ix2 = (8121 * ix2 + 28411) % 134456;
  ix3 = (4561 * ix3 + 51349) % 243000;
  j = 1 + ((97 * ix3) / 243000);
  if (j > 97 || j < 1)
    nrerror("RAN1: This cannot happen.");
  temp = r[j];
  r[j] = (ix1 + ix2 * (1.0 / 134456)) * (1.0 / 259200);
  return temp;
}


x86 assembly (clang, -O0):
<ran1>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
cmpl   $0x0,(%rax)
jl     1136 <ran1+0x26>
cmpl   $0x0,0x30b8(%rip)
jne    1280 <ran1+0x170>
movl   $0x1,0x30a8(%rip)
mov    -0x8(%rbp),%rcx
mov    $0xd5f5,%eax
sub    (%rcx),%eax
mov    $0x3f480,%ecx
cltd
idiv   %ecx
movslq %edx,%rax
mov    %rax,0x2ee3(%rip)
imul   $0x1be5,0x2ed8(%rip),%rax
add    $0xd5f5,%rax
mov    $0x3f480,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2ec1(%rip)
mov    0x2eba(%rip),%rax
mov    $0x20d38,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2eb1(%rip)
imul   $0x1be5,0x2e9e(%rip),%rax
add    $0xd5f5,%rax
mov    $0x3f480,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2e87(%rip)
mov    0x2e80(%rip),%rax
mov    $0x3b538,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2e7f(%rip)
movl   $0x1,-0x10(%rbp)
cmpl   $0x61,-0x10(%rbp)
jg     1276 <ran1+0x166>
imul   $0x1be5,0x2e53(%rip),%rax
add    $0xd5f5,%rax
mov    $0x3f480,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2e3c(%rip)
imul   $0x1fb9,0x2e39(%rip),%rax
add    $0x6efb,%rax
mov    $0x20d38,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2e22(%rip)
cvtsi2sdq 0x2e11(%rip),%xmm1
cvtsi2sdq 0x2e10(%rip),%xmm0
movsd  0xdc8(%rip),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xdb0(%rip),%xmm1
mulsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movslq -0x10(%rbp),%rcx
lea    0x2dfd(%rip),%rax
movss  %xmm0,(%rax,%rcx,4)
mov    -0x10(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x10(%rbp)
jmp    11d8 <ran1+0xc8>
mov    -0x8(%rbp),%rax
movl   $0x1,(%rax)
imul   $0x1be5,0x2db5(%rip),%rax
add    $0xd5f5,%rax
mov    $0x3f480,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2d9e(%rip)
imul   $0x1fb9,0x2d9b(%rip),%rax
add    $0x6efb,%rax
mov    $0x20d38,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2d84(%rip)
imul   $0x11d1,0x2d81(%rip),%rax
add    $0xc895,%rax
mov    $0x3b538,%ecx
cqto
idiv   %rcx
mov    %rdx,0x2d6a(%rip)
imul   $0x61,0x2d62(%rip),%rax
61
mov    $0x3b538,%ecx
cqto
idiv   %rcx
add    $0x1,%rax
mov    %eax,-0x10(%rbp)
cmpl   $0x61,-0x10(%rbp)
jg     1313 <ran1+0x203>
cmpl   $0x1,-0x10(%rbp)
jge    1321 <ran1+0x211>
lea    0xcf6(%rip),%rdi
mov    $0x0,%al
call   1030 <nrerror@plt>
movslq -0x10(%rbp),%rcx
lea    0x2d34(%rip),%rax
movss  (%rax,%rcx,4),%xmm0
movss  %xmm0,-0xc(%rbp)
cvtsi2sdq 0x2d01(%rip),%xmm1
cvtsi2sdq 0x2d00(%rip),%xmm0
movsd  0xcb8(%rip),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xca0(%rip),%xmm1
mulsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movslq -0x10(%rbp),%rcx
lea    0x2ced(%rip),%rax
movss  %xmm0,(%rax,%rcx,4)
movss  -0xc(%rbp),%xmm0
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ran1>:
push   %r14
push   %rbx
push   %rax
mov    (%rdi),%eax
movabs $0x81742e044c5b8725,%r9
2e 74 81
movabs $0x1f31d2b36647fc39,%r8
d2 31 1f
test   %eax,%eax
js     1151 <ran1+0x41>
testb  $0x1,0x30b3(%rip)
je     1151 <ran1+0x41>
mov    0x2f02(%rip),%rsi
mov    0x2f03(%rip),%rcx
mov    0x2f04(%rip),%r10
jmp    12ef <ran1+0x1df>
movb   $0x1,0x3090(%rip)
mov    $0xd5f5,%ecx
sub    %eax,%ecx
movslq %ecx,%rax
imul   $0xffffffff81742e05,%rax,%rcx
shr    $0x20,%rcx
add    %eax,%ecx
mov    %ecx,%edx
shr    $0x1f,%edx
sar    $0x11,%ecx
add    %edx,%ecx
imul   $0x3f480,%ecx,%ecx
sub    %ecx,%eax
imul   $0x1be5,%eax,%eax
mov    %eax,%ecx
add    $0xd5f5,%ecx
movslq %ecx,%rcx
imul   $0xffffffff81742e05,%rcx,%rdx
shr    $0x20,%rdx
add    %edx,%eax
add    $0xd5f5,%eax
mov    %eax,%edx
shr    $0x1f,%edx
sar    $0x11,%eax
add    %edx,%eax
imul   $0x3f480,%eax,%eax
sub    %eax,%ecx
movslq %ecx,%rax
imul   $0x3e63a567,%rax,%rcx
mov    %rcx,%rdx
shr    $0x3f,%rdx
shr    $0x20,%rcx
sar    $0xf,%ecx
add    %edx,%ecx
imul   $0x20d38,%ecx,%ecx
imul   $0x1be5,%eax,%edx
sub    %ecx,%eax
movslq %eax,%rcx
mov    %edx,%eax
add    $0xd5f5,%eax
cltq
imul   $0xffffffff81742e05,%rax,%rsi
shr    $0x20,%rsi
add    %esi,%edx
add    $0xd5f5,%edx
mov    %edx,%esi
shr    $0x1f,%esi
sar    $0x11,%edx
add    %esi,%edx
imul   $0x3f480,%edx,%edx
sub    %edx,%eax
movslq %eax,%rsi
imul   $0x2285619b,%rsi,%rax
mov    %rax,%rdx
shr    $0x3f,%rdx
sar    $0x2f,%rax
add    %edx,%eax
imul   $0x3b538,%eax,%eax
mov    %esi,%edx
sub    %eax,%edx
movslq %edx,%r10
mov    $0x1,%r11d
movsd  0xdbf(%rip),%xmm0
movsd  0xdbf(%rip),%xmm1
lea    0x2e10(%rip),%r14
imul   $0x1be5,%rsi,%rbx
lea    0xd5f5(%rbx),%rsi
mov    %rsi,%rax
imul   %r9
lea    (%rdx,%rbx,1),%rax
add    $0xd5f5,%rax
mov    %rax,%rdx
shr    $0x3f,%rdx
sar    $0x11,%rax
add    %rdx,%rax
imul   $0x3f480,%rax,%rax
sub    %rax,%rsi
imul   $0x1fb9,%rcx,%rcx
add    $0x6efb,%rcx
mov    %rcx,%rax
imul   %r8
mov    %rdx,%rax
shr    $0x3f,%rax
sar    $0xe,%rdx
add    %rax,%rdx
imul   $0x20d38,%rdx,%rax
xorps  %xmm2,%xmm2
cvtsi2sd %rsi,%xmm2
sub    %rax,%rcx
xorps  %xmm3,%xmm3
cvtsi2sd %rcx,%xmm3
mulsd  %xmm0,%xmm3
addsd  %xmm2,%xmm3
mulsd  %xmm1,%xmm3
xorps  %xmm2,%xmm2
cvtsd2ss %xmm3,%xmm2
movss  %xmm2,(%r14,%r11,4)
add    $0x1,%r11
cmp    $0x62,%r11
jne    1250 <ran1+0x140>
movl   $0x1,(%rdi)
imul   $0x1be5,%rsi,%rdi
lea    0xd5f5(%rdi),%rsi
mov    %rsi,%rax
imul   %r9
lea    (%rdx,%rdi,1),%rax
add    $0xd5f5,%rax
mov    %rax,%rdx
shr    $0x3f,%rdx
sar    $0x11,%rax
add    %rdx,%rax
imul   $0x3f480,%rax,%rax
sub    %rax,%rsi
mov    %rsi,0x2d14(%rip)
imul   $0x1fb9,%rcx,%rcx
add    $0x6efb,%rcx
mov    %rcx,%rax
imul   %r8
mov    %rdx,%rax
shr    $0x3f,%rax
sar    $0xe,%rdx
add    %rax,%rdx
imul   $0x20d38,%rdx,%rax
sub    %rax,%rcx
mov    %rcx,0x2ce9(%rip)
imul   $0x11d1,%r10,%rdi
add    $0xc895,%rdi
movabs $0x2285619abf07573d,%rdx
61 85 22
mov    %rdi,%rax
imul   %rdx
mov    %rdx,%rax
shr    $0x3f,%rax
sar    $0xf,%rdx
add    %rax,%rdx
imul   $0x3b538,%rdx,%rax
sub    %rax,%rdi
mov    %rdi,0x2cb4(%rip)
imul   $0x61,%edi,%eax
cltq
imul   $0x2285619b,%rax,%rbx
mov    %rbx,%rax
shr    $0x3f,%rax
sar    $0x2f,%rbx
add    %eax,%ebx
cmp    $0x7fffffff,%ebx
jb     13d9 <ran1+0x2c9>
lea    0xc4c(%rip),%rdi
xor    %eax,%eax
call   1030 <nrerror@plt>
mov    0x2c6e(%rip),%rsi
mov    0x2c6f(%rip),%rcx
movslq %ebx,%rax
cvtsi2sd %rsi,%xmm0
cvtsi2sd %rcx,%xmm1
mulsd  0xc12(%rip),%xmm1
lea    0x2c6b(%rip),%rcx
addsd  %xmm0,%xmm1
mulsd  0xc07(%rip),%xmm1
movss  0x4(%rcx,%rax,4),%xmm0
cvtsd2ss %xmm1,%xmm1
movss  %xmm1,0x4(%rcx,%rax,4)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
@ran1.ix1 = internal global i64 0
@ran1.ix2 = internal global i64 0
@ran1.ix3 = internal global i64 0
@ran1.r = internal global [98 x float] zeroinitializer
@ran1.iff = internal global i32 0
@.str = [26 x i8] c"RAN1: This cannot happen.\00"
define float @ran1(i32* %0) {
%2 = alloca i32*
%3 = alloca float
%4 = alloca i32
store i32* %0, i32** %2
%5 = load i32*, i32** %2
%6 = load i32, i32* %5
%7 = icmp slt i32 %6, 0
br i1 %7, label %11, label %8
8: ; preds = %1
%9 = load i32, i32* @ran1.iff
%10 = icmp eq i32 %9, 0
br i1 %10, label %11, label %56
11: ; preds = %8, %1
store i32 1, i32* @ran1.iff
%12 = load i32*, i32** %2
%13 = load i32, i32* %12
%14 = sub nsw i32 54773, %13
%15 = srem i32 %14, 259200
%16 = sext i32 %15 to i64
store i64 %16, i64* @ran1.ix1
%17 = load i64, i64* @ran1.ix1
%18 = mul nsw i64 7141, %17
%19 = add nsw i64 %18, 54773
%20 = srem i64 %19, 259200
store i64 %20, i64* @ran1.ix1
%21 = load i64, i64* @ran1.ix1
%22 = srem i64 %21, 134456
store i64 %22, i64* @ran1.ix2
%23 = load i64, i64* @ran1.ix1
%24 = mul nsw i64 7141, %23
%25 = add nsw i64 %24, 54773
%26 = srem i64 %25, 259200
store i64 %26, i64* @ran1.ix1
%27 = load i64, i64* @ran1.ix1
%28 = srem i64 %27, 243000
store i64 %28, i64* @ran1.ix3
store i32 1, i32* %4
br label %29
29: ; preds = %51, %11
%30 = load i32, i32* %4
%31 = icmp sle i32 %30, 97
br i1 %31, label %32, label %54
32: ; preds = %29
%33 = load i64, i64* @ran1.ix1
%34 = mul nsw i64 7141, %33
%35 = add nsw i64 %34, 54773
%36 = srem i64 %35, 259200
store i64 %36, i64* @ran1.ix1
%37 = load i64, i64* @ran1.ix2
%38 = mul nsw i64 8121, %37
%39 = add nsw i64 %38, 28411
%40 = srem i64 %39, 134456
store i64 %40, i64* @ran1.ix2
%41 = load i64, i64* @ran1.ix1
%42 = sitofp i64 %41 to double
%43 = load i64, i64* @ran1.ix2
%44 = sitofp i64 %43 to double
%45 = call double @llvm.fmuladd.f64(double %44, double 0x3EDF31D2B36647FC, double %42)
%46 = fmul double %45, 0x3ED02E85C0898B71
%47 = fptrunc double %46 to float
%48 = load i32, i32* %4
%49 = sext i32 %48 to i64
%50 = getelementptr inbounds [98 x float], [98 x float]* @ran1.r, i64 0, i64 %49
store float %47, float* %50
br label %51
51: ; preds = %32
%52 = load i32, i32* %4
%53 = add nsw i32 %52, 1
store i32 %53, i32* %4
br label %29
54: ; preds = %29
%55 = load i32*, i32** %2
store i32 1, i32* %55
br label %56
56: ; preds = %54, %8
%57 = load i64, i64* @ran1.ix1
%58 = mul nsw i64 7141, %57
%59 = add nsw i64 %58, 54773
%60 = srem i64 %59, 259200
store i64 %60, i64* @ran1.ix1
%61 = load i64, i64* @ran1.ix2
%62 = mul nsw i64 8121, %61
%63 = add nsw i64 %62, 28411
%64 = srem i64 %63, 134456
store i64 %64, i64* @ran1.ix2
%65 = load i64, i64* @ran1.ix3
%66 = mul nsw i64 4561, %65
%67 = add nsw i64 %66, 51349
%68 = srem i64 %67, 243000
store i64 %68, i64* @ran1.ix3
%69 = load i64, i64* @ran1.ix3
%70 = mul nsw i64 97, %69
%71 = sdiv i64 %70, 243000
%72 = add nsw i64 1, %71
%73 = trunc i64 %72 to i32
store i32 %73, i32* %4
%74 = load i32, i32* %4
%75 = icmp sgt i32 %74, 97
br i1 %75, label %79, label %76
76: ; preds = %56
%77 = load i32, i32* %4
%78 = icmp slt i32 %77, 1
br i1 %78, label %79, label %80
79: ; preds = %76, %56
br label %80
80: ; preds = %79, %76
%81 = load i32, i32* %4
%82 = sext i32 %81 to i64
%83 = getelementptr inbounds [98 x float], [98 x float]* @ran1.r, i64 0, i64 %82
%84 = load float, float* %83
store float %84, float* %3
%85 = load i64, i64* @ran1.ix1
%86 = sitofp i64 %85 to double
%87 = load i64, i64* @ran1.ix2
%88 = sitofp i64 %87 to double
%89 = call double @llvm.fmuladd.f64(double %88, double 0x3EDF31D2B36647FC, double %86)
%90 = fmul double %89, 0x3ED02E85C0898B71
%91 = fptrunc double %90 to float
%92 = load i32, i32* %4
%93 = sext i32 %92 to i64
%94 = getelementptr inbounds [98 x float], [98 x float]* @ran1.r, i64 0, i64 %93
store float %91, float* %94
%95 = load float, float* %3
ret float %95
}

LLVM IR (-O2):
@ran1.ix1 = internal unnamed_addr global i64 0
@ran1.ix2 = internal unnamed_addr global i64 0
@ran1.ix3 = internal unnamed_addr global i64 0
@ran1.r = internal unnamed_addr global [98 x float] zeroinitializer
@ran1.iff = internal unnamed_addr global i1 false
@.str = [26 x i8] c"RAN1: This cannot happen.\00"
define float @ran1(i32* nocapture %0) {
%2 = load i32, i32* %0
%3 = icmp slt i32 %2, 0
%4 = load i1, i1* @ran1.iff
%5 = xor i1 %4, true
%6 = select i1 %3, i1 true, i1 %5
br i1 %6, label %11, label %7
7: ; preds = %1
%8 = load i64, i64* @ran1.ix1
%9 = load i64, i64* @ran1.ix2
%10 = load i64, i64* @ran1.ix3
br label %44
11: ; preds = %1
store i1 true, i1* @ran1.iff
%12 = sub nsw i32 54773, %2
%13 = srem i32 %12, 259200
%14 = mul nsw i32 %13, 7141
%15 = add nsw i32 %14, 54773
%16 = srem i32 %15, 259200
%17 = srem i32 %16, 134456
%18 = sext i32 %17 to i64
%19 = mul nsw i32 %16, 7141
%20 = add nsw i32 %19, 54773
%21 = srem i32 %20, 259200
%22 = sext i32 %21 to i64
%23 = srem i32 %21, 243000
%24 = sext i32 %23 to i64
br label %25
25: ; preds = %11, %25
%26 = phi i64 [ 1, %11 ], [ %41, %25 ]
%27 = phi i64 [ %22, %11 ], [ %31, %25 ]
%28 = phi i64 [ %18, %11 ], [ %34, %25 ]
%29 = mul nsw i64 %27, 7141
%30 = add nsw i64 %29, 54773
%31 = srem i64 %30, 259200
%32 = mul nsw i64 %28, 8121
%33 = add nsw i64 %32, 28411
%34 = srem i64 %33, 134456
%35 = sitofp i64 %31 to double
%36 = sitofp i64 %34 to double
%37 = tail call double @llvm.fmuladd.f64(double %36, double 0x3EDF31D2B36647FC, double %35)
%38 = fmul double %37, 0x3ED02E85C0898B71
%39 = fptrunc double %38 to float
%40 = getelementptr inbounds [98 x float], [98 x float]* @ran1.r, i64 0, i64 %26
store float %39, float* %40
%41 = add nuw nsw i64 %26, 1
%42 = icmp eq i64 %41, 98
br i1 %42, label %43, label %25
43: ; preds = %25
store i32 1, i32* %0
br label %44
44: ; preds = %7, %43
%45 = phi i64 [ %10, %7 ], [ %24, %43 ]
%46 = phi i64 [ %9, %7 ], [ %34, %43 ]
%47 = phi i64 [ %8, %7 ], [ %31, %43 ]
%48 = mul nsw i64 %47, 7141
%49 = add nsw i64 %48, 54773
%50 = srem i64 %49, 259200
store i64 %50, i64* @ran1.ix1
%51 = mul nsw i64 %46, 8121
%52 = add nsw i64 %51, 28411
%53 = srem i64 %52, 134456
store i64 %53, i64* @ran1.ix2
%54 = mul nsw i64 %45, 4561
%55 = add nsw i64 %54, 51349
%56 = srem i64 %55, 243000
store i64 %56, i64* @ran1.ix3
%57 = trunc i64 %56 to i32
%58 = mul nsw i32 %57, 97
%59 = sdiv i32 %58, 243000
%60 = icmp ugt i32 %59, 2147483646
br i1 %60, label %61, label %64
61: ; preds = %44
tail call void (i8*, ...) bitcast (void (...)* @nrerror to void (i8*, ...)*)(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str, i64 0, i64 0))
%62 = load i64, i64* @ran1.ix1
%63 = load i64, i64* @ran1.ix2
br label %64
64: ; preds = %44, %61
%65 = phi i64 [ %53, %44 ], [ %63, %61 ]
%66 = phi i64 [ %50, %44 ], [ %62, %61 ]
%67 = add nsw i32 %59, 1
%68 = sext i32 %67 to i64
%69 = getelementptr inbounds [98 x float], [98 x float]* @ran1.r, i64 0, i64 %68
%70 = load float, float* %69
%71 = sitofp i64 %66 to double
%72 = sitofp i64 %65 to double
%73 = tail call double @llvm.fmuladd.f64(double %72, double 0x3EDF31D2B36647FC, double %71)
%74 = fmul double %73, 0x3ED02E85C0898B71
%75 = fptrunc double %74 to float
store float %75, float* %69
ret float %70
}