#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
struct training_data {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ dqs_bdl_enable();
void config_ddr_dq_wr(struct training_data *training, unsigned int deskew_value,
                      unsigned int bytenum, unsigned int dqindex) {
  unsigned int val;
  dqindex &= 0x07;
  if (dqindex < 4) {
    val = (*(volatile unsigned int *)(0x20118000 + (0x210 + ((bytenum) << 7))));
    val &= ~(0xFF << (dqindex << 3));
    val |= ((0x1F & deskew_value) << (dqindex << 3));
    (*(volatile unsigned int *)(0x20118000 + (0x210 + ((bytenum) << 7))) =
         (val));
  } else {
    dqindex -= 4;
    val = (*(volatile unsigned int *)(0x20118000 + (0x214 + ((bytenum) << 7))));
    val &= ~(0xFF << (dqindex << 3));
    val |= ((0x1F & deskew_value) << (dqindex << 3));
    (*(volatile unsigned int *)(0x20118000 + (0x214 + ((bytenum) << 7))) =
         (val));
  }
  dqs_bdl_enable();
}


x86 assembly (clang, -O0):
<config_ddr_dq_wr>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %edx,-0x10(%rbp)
mov    %ecx,-0x14(%rbp)
mov    -0x14(%rbp),%eax
and    $0x7,%eax
mov    %eax,-0x14(%rbp)
cmpl   $0x4,-0x14(%rbp)
jae    1195 <config_ddr_dq_wr+0x85>
mov    -0x10(%rbp),%eax
shl    $0x7,%eax
add    $0x210,%eax
add    $0x20118000,%eax
mov    %eax,%eax
mov    (%rax),%eax
mov    %eax,-0x18(%rbp)
mov    -0x14(%rbp),%ecx
shl    $0x3,%ecx
mov    $0xff,%eax
shl    %cl,%eax
xor    $0xffffffff,%eax
and    -0x18(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0xc(%rbp),%eax
and    $0x1f,%eax
mov    -0x14(%rbp),%ecx
shl    $0x3,%ecx
shl    %cl,%eax
or     -0x18(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%ecx
mov    -0x10(%rbp),%eax
shl    $0x7,%eax
add    $0x210,%eax
add    $0x20118000,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
jmp    11f6 <config_ddr_dq_wr+0xe6>
mov    -0x14(%rbp),%eax
sub    $0x4,%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
shl    $0x7,%eax
add    $0x214,%eax
add    $0x20118000,%eax
mov    %eax,%eax
mov    (%rax),%eax
mov    %eax,-0x18(%rbp)
mov    -0x14(%rbp),%ecx
shl    $0x3,%ecx
mov    $0xff,%eax
shl    %cl,%eax
xor    $0xffffffff,%eax
and    -0x18(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0xc(%rbp),%eax
and    $0x1f,%eax
mov    -0x14(%rbp),%ecx
shl    $0x3,%ecx
shl    %cl,%eax
or     -0x18(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%ecx
mov    -0x10(%rbp),%eax
shl    $0x7,%eax
add    $0x214,%eax
add    $0x20118000,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    $0x0,%al
call   1030 <dqs_bdl_enable@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<config_ddr_dq_wr>:
and    $0x7,%ecx
shl    $0x7,%edx
cmp    $0x3,%ecx
ja     1123 <config_ddr_dq_wr+0x13>
add    $0x20118210,%edx
jmp    1129 <config_ddr_dq_wr+0x19>
add    $0x20118214,%edx
shl    $0x3,%ecx
mov    $0xff,%eax
shl    %cl,%eax
not    %eax
and    $0x1f,%esi
shl    %cl,%esi
and    (%rdx),%eax
or     %eax,%esi
mov    %esi,(%rdx)
xor    %eax,%eax
jmp    1030 <dqs_bdl_enable@plt>

LLVM IR (-O0):
%struct.training_data = type { i32 }
define void @config_ddr_dq_wr(%struct.training_data* %0, i32 %1, i32 %2, i32 %3) {
%5 = alloca %struct.training_data*
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
%9 = alloca i32
store %struct.training_data* %0, %struct.training_data** %5
store i32 %1, i32* %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%10 = load i32, i32* %8
%11 = and i32 %10, 7
store i32 %11, i32* %8
%12 = load i32, i32* %8
%13 = icmp ult i32 %12, 4
br i1 %13, label %14, label %42
14: ; preds = %4
%15 = load i32, i32* %7
%16 = shl i32 %15, 7
%17 = add i32 528, %16
%18 = add i32 538017792, %17
%19 = zext i32 %18 to i64
%20 = inttoptr i64 %19 to i32*
%21 = load volatile i32, i32* %20
store i32 %21, i32* %9
%22 = load i32, i32* %8
%23 = shl i32 %22, 3
%24 = shl i32 255, %23
%25 = xor i32 %24, -1
%26 = load i32, i32* %9
%27 = and i32 %26, %25
store i32 %27, i32* %9
%28 = load i32, i32* %6
%29 = and i32 31, %28
%30 = load i32, i32* %8
%31 = shl i32 %30, 3
%32 = shl i32 %29, %31
%33 = load i32, i32* %9
%34 = or i32 %33, %32
store i32 %34, i32* %9
%35 = load i32, i32* %9
%36 = load i32, i32* %7
%37 = shl i32 %36, 7
%38 = add i32 528, %37
%39 = add i32 538017792, %38
%40 = zext i32 %39 to i64
%41 = inttoptr i64 %40 to i32*
store volatile i32 %35, i32* %41
br label %72
42: ; preds = %4
%43 = load i32, i32* %8
%44 = sub i32 %43, 4
store i32 %44, i32* %8
%45 = load i32, i32* %7
%46 = shl i32 %45, 7
%47 = add i32 532, %46
%48 = add i32 538017792, %47
%49 = zext i32 %48 to i64
%50 = inttoptr i64 %49 to i32*
%51 = load volatile i32, i32* %50
store i32 %51, i32* %9
%52 = load i32, i32* %8
%53 = shl i32 %52, 3
%54 = shl i32 255, %53
%55 = xor i32 %54, -1
%56 = load i32, i32* %9
%57 = and i32 %56, %55
store i32 %57, i32* %9
%58 = load i32, i32* %6
%59 = and i32 31, %58
%60 = load i32, i32* %8
%61 = shl i32 %60, 3
%62 = shl i32 %59, %61
%63 = load i32, i32* %9
%64 = or i32 %63, %62
store i32 %64, i32* %9
%65 = load i32, i32* %9
%66 = load i32, i32* %7
%67 = shl i32 %66, 7
%68 = add i32 532, %67
%69 = add i32 538017792, %68
%70 = zext i32 %69 to i64
%71 = inttoptr i64 %70 to i32*
store volatile i32 %65, i32* %71
br label %72
72: ; preds = %42, %14
%73 = call i32 (...) @dqs_bdl_enable()
ret void
}

LLVM IR (-O2):
%struct.training_data = type { i32 }
define void @config_ddr_dq_wr(%struct.training_data* nocapture readnone %0, i32 %1, i32 %2, i32 %3) {
%5 = and i32 %3, 7
%6 = icmp ult i32 %5, 4
%7 = shl i32 %2, 7
br i1 %6, label %8, label %20
8: ; preds = %4
%9 = add i32 %7, 538018320
%10 = zext i32 %9 to i64
%11 = inttoptr i64 %10 to i32*
%12 = load volatile i32, i32* %11
%13 = shl nuw nsw i32 %5, 3
%14 = shl nuw i32 255, %13
%15 = xor i32 %14, -1
%16 = and i32 %12, %15
%17 = and i32 %1, 31
%18 = shl nuw nsw i32 %17, %13
%19 = or i32 %16, %18
store volatile i32 %19, i32* %11
br label %33
20: ; preds = %4
%21 = add i32 %7, 538018324
%22 = zext i32 %21 to i64
%23 = inttoptr i64 %22 to i32*
%24 = load volatile i32, i32* %23
%25 = shl nuw nsw i32 %5, 3
%26 = add nsw i32 %25, -32
%27 = shl nuw i32 255, %26
%28 = xor i32 %27, -1
%29 = and i32 %24, %28
%30 = and i32 %1, 31
%31 = shl nuw nsw i32 %30, %26
%32 = or i32 %29, %31
store volatile i32 %32, i32* %23
br label %33
33: ; preds = %20, %8
%34 = tail call i32 (...) @dqs_bdl_enable()
ret void
}