#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS,
                                     uint32_t *pui32CR) {
  uint32_t ui32Offset;
  ASSERT(ui32Base == 0x400D0000);
  ASSERT(ui32CS < 4);
  if (ui32CS < 2) {
    ui32Offset = 0x00000010 + (ui32CS << 2);
  } else {
    ui32Offset = 0x00000308 + ((ui32CS - 2) << 2);
  }
  if ((*((volatile uint32_t *)(ui32Base + ui32Offset))) & 0x00020000) {
    return (false);
  }
  *pui32CR = (*((volatile uint32_t *)(ui32Base + 0x00000360))) & 0xffff;
  return (true);
}


x86 assembly (clang, -O0):
<EPIPSRAMConfigRegGetNonBlocking>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %rdx,-0x18(%rbp)
cmpl   $0x400d0000,-0x8(%rbp)
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x4,-0xc(%rbp)
setl   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x2,-0xc(%rbp)
jge    1162 <EPIPSRAMConfigRegGetNonBlocking+0x52>
mov    -0xc(%rbp),%eax
shl    $0x2,%eax
add    $0x10,%eax
mov    %eax,-0x1c(%rbp)
jmp    1173 <EPIPSRAMConfigRegGetNonBlocking+0x63>
mov    -0xc(%rbp),%eax
sub    $0x2,%eax
shl    $0x2,%eax
add    $0x308,%eax
mov    %eax,-0x1c(%rbp)
mov    -0x8(%rbp),%eax
add    -0x1c(%rbp),%eax
cltq
mov    (%rax),%eax
and    $0x20000,%eax
cmp    $0x0,%eax
je     1197 <EPIPSRAMConfigRegGetNonBlocking+0x87>
movl   $0x0,-0x4(%rbp)
jmp    11b6 <EPIPSRAMConfigRegGetNonBlocking+0xa6>
mov    -0x8(%rbp),%eax
add    $0x360,%eax
cltq
mov    (%rax),%ecx
and    $0xffff,%ecx
mov    -0x18(%rbp),%rax
mov    %ecx,(%rax)
movl   $0x1,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<EPIPSRAMConfigRegGetNonBlocking>:
push   %r15
push   %r14
push   %rbx
mov    %rdx,%r14
mov    %esi,%ebx
mov    %edi,%r15d
xor    %edi,%edi
cmp    $0x400d0000,%r15d
sete   %dil
call   1030 <ASSERT@plt>
xor    %edi,%edi
cmp    $0x4,%ebx
setl   %dil
call   1030 <ASSERT@plt>
cmp    $0x2,%ebx
lea    0x10(%r15,%rbx,4),%eax
lea    0x300(%r15,%rbx,4),%ecx
cmovl  %eax,%ecx
movslq %ecx,%rcx
xor    %eax,%eax
testl  $0x20000,(%rcx)
jne    1171 <EPIPSRAMConfigRegGetNonBlocking+0x61>
movslq %r15d,%rax
mov    0x360(%rax),%eax
movzwl %ax,%eax
mov    %eax,(%r14)
mov    $0x1,%eax
pop    %rbx
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define i32 @EPIPSRAMConfigRegGetNonBlocking(i32 %0, i32 %1, i32* %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32*
%8 = alloca i32
store i32 %0, i32* %5
store i32 %1, i32* %6
store i32* %2, i32** %7
%9 = load i32, i32* %5
%10 = icmp eq i32 %9, 1074593792
%11 = zext i1 %10 to i32
%12 = call i32 @ASSERT(i32 %11)
%13 = load i32, i32* %6
%14 = icmp slt i32 %13, 4
%15 = zext i1 %14 to i32
%16 = call i32 @ASSERT(i32 %15)
%17 = load i32, i32* %6
%18 = icmp slt i32 %17, 2
br i1 %18, label %19, label %23
19: ; preds = %3
%20 = load i32, i32* %6
%21 = shl i32 %20, 2
%22 = add nsw i32 16, %21
store i32 %22, i32* %8
br label %28
23: ; preds = %3
%24 = load i32, i32* %6
%25 = sub nsw i32 %24, 2
%26 = shl i32 %25, 2
%27 = add nsw i32 776, %26
store i32 %27, i32* %8
br label %28
28: ; preds = %23, %19
%29 = load i32, i32* %5
%30 = load i32, i32* %8
%31 = add nsw i32 %29, %30
%32 = sext i32 %31 to i64
%33 = inttoptr i64 %32 to i32*
%34 = load volatile i32, i32* %33
%35 = and i32 %34, 131072
%36 = icmp ne i32 %35, 0
br i1 %36, label %37, label %38
37: ; preds = %28
store i32 0, i32* %4
br label %46
38: ; preds = %28
%39 = load i32, i32* %5
%40 = add nsw i32 %39, 864
%41 = sext i32 %40 to i64
%42 = inttoptr i64 %41 to i32*
%43 = load volatile i32, i32* %42
%44 = and i32 %43, 65535
%45 = load i32*, i32** %7
store i32 %44, i32* %45
store i32 1, i32* %4
br label %46
46: ; preds = %38, %37
%47 = load i32, i32* %4
ret i32 %47
}

LLVM IR (-O2):
define i32 @EPIPSRAMConfigRegGetNonBlocking(i32 %0, i32 %1, i32* nocapture writeonly %2) {
%4 = icmp eq i32 %0, 1074593792
%5 = zext i1 %4 to i32
%6 = tail call i32 @ASSERT(i32 %5)
%7 = icmp slt i32 %1, 4
%8 = zext i1 %7 to i32
%9 = tail call i32 @ASSERT(i32 %8)
%10 = icmp slt i32 %1, 2
%11 = shl i32 %1, 2
%12 = select i1 %10, i32 16, i32 768
%13 = add i32 %11, %0
%14 = add i32 %13, %12
%15 = sext i32 %14 to i64
%16 = inttoptr i64 %15 to i32*
%17 = load volatile i32, i32* %16
%18 = and i32 %17, 131072
%19 = icmp eq i32 %18, 0
br i1 %19, label %20, label %26
20: ; preds = %3
%21 = add nsw i32 %0, 864
%22 = sext i32 %21 to i64
%23 = inttoptr i64 %22 to i32*
%24 = load volatile i32, i32* %23
%25 = and i32 %24, 65535
store i32 %25, i32* %2
br label %26
26: ; preds = %3, %20
%27 = phi i32 [ 1, %20 ], [ 0, %3 ]
ret i32 %27
}