void intc_enable(unsigned long intnum) {
  unsigned long temp;
  if (intnum < 32) {
    temp = (*((volatile unsigned long *)((0xF2000000) + 0x10)));
    temp |= (1 << intnum);
    (*((volatile unsigned long *)((0xF2000000) + 0x10))) = temp;
  } else if (intnum < 64) {
    temp = (*((volatile unsigned long *)((0xF2100000) + 0x10)));
    temp |= (1 << (intnum - 32));
    (*((volatile unsigned long *)((0xF2100000) + 0x10))) = temp;
  } else if (intnum < 96) {
    temp = (*((volatile unsigned long *)((0xF2200000) + 0x10)));
    temp |= (1 << (intnum - 64));
    (*((volatile unsigned long *)((0xF2200000) + 0x10))) = temp;
  } else if (intnum < (200)) {
    temp = (*((volatile unsigned long *)((0xF2300000) + 0x10)));
    temp |= (1 << (intnum - 96));
    (*((volatile unsigned long *)((0xF2300000) + 0x10))) = temp;
  } else {
    (*((volatile unsigned long *)((0xF2000000) + 0x10))) = 0xFFFFFFFF;
    (*((volatile unsigned long *)((0xF2100000) + 0x10))) = 0xFFFFFFFF;
    (*((volatile unsigned long *)((0xF2200000) + 0x10))) = 0xFFFFFFFF;
    (*((volatile unsigned long *)((0xF2300000) + 0x10))) = 0xFFFFFFFF;
  }
}


x86 assembly (clang, -O0):
<intc_enable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
cmpq   $0x20,-0x8(%rbp)
jae    1147 <intc_enable+0x47>
mov    $0xf2000010,%eax
mov    (%rax),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
cltq
or     -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rcx
mov    $0xf2000010,%eax
mov    %rcx,(%rax)
jmp    1256 <intc_enable+0x156>
cmpq   $0x40,-0x8(%rbp)
jae    118a <intc_enable+0x8a>
mov    $0xf2100010,%eax
mov    (%rax),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
sub    $0x20,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
cltq
or     -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rcx
mov    $0xf2100010,%eax
mov    %rcx,(%rax)
jmp    1251 <intc_enable+0x151>
cmpq   $0x60,-0x8(%rbp)
jae    11cd <intc_enable+0xcd>
mov    $0xf2200010,%eax
mov    (%rax),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
sub    $0x40,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
cltq
or     -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rcx
mov    $0xf2200010,%eax
mov    %rcx,(%rax)
jmp    124c <intc_enable+0x14c>
cmpq   $0xc8,-0x8(%rbp)
jae    1213 <intc_enable+0x113>
mov    $0xf2300010,%eax
mov    (%rax),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
sub    $0x60,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
cltq
or     -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rcx
mov    $0xf2300010,%eax
mov    %rcx,(%rax)
jmp    1247 <intc_enable+0x147>
mov    $0xf2000010,%eax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
mov    $0xf2100010,%eax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
mov    $0xf2200010,%eax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
mov    $0xf2300010,%eax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
jmp    124c <intc_enable+0x14c>
jmp    1251 <intc_enable+0x151>
jmp    1256 <intc_enable+0x156>
pop    %rbp
ret

x86 assembly (clang, -O2):
<intc_enable>:
mov    $0xffffffff,%eax
cmp    $0x1f,%rdi
ja     111f <intc_enable+0x1f>
mov    $0x1,%edx
mov    %edi,%ecx
shl    %cl,%edx
movslq %edx,%rcx
or     %rcx,-0xdffffef(%rax)
ret
cmp    $0x3f,%rdi
ja     1139 <intc_enable+0x39>
mov    $0x1,%edx
mov    %edi,%ecx
shl    %cl,%edx
movslq %edx,%rcx
or     %rcx,-0xdefffef(%rax)
ret
cmp    $0x5f,%rdi
ja     1153 <intc_enable+0x53>
mov    $0x1,%edx
mov    %edi,%ecx
shl    %cl,%edx
movslq %edx,%rcx
or     %rcx,-0xddfffef(%rax)
ret
cmp    $0xc7,%rdi
ja     1170 <intc_enable+0x70>
mov    $0x1,%edx
mov    %edi,%ecx
shl    %cl,%edx
movslq %edx,%rcx
or     %rcx,-0xdcfffef(%rax)
ret
mov    %rax,-0xdffffef(%rax)
mov    %rax,-0xdefffef(%rax)
mov    %rax,-0xddfffef(%rax)
mov    %rax,-0xdcfffef(%rax)
ret

LLVM IR (-O0):
define void @intc_enable(i64 %0) {
%2 = alloca i64
%3 = alloca i64
store i64 %0, i64* %2
%4 = load i64, i64* %2
%5 = icmp ult i64 %4, 32
br i1 %5, label %6, label %15
6: ; preds = %1
%7 = load volatile i64, i64* inttoptr (i64 4060086288 to i64*)
store i64 %7, i64* %3
%8 = load i64, i64* %2
%9 = trunc i64 %8 to i32
%10 = shl i32 1, %9
%11 = sext i32 %10 to i64
%12 = load i64, i64* %3
%13 = or i64 %12, %11
store i64 %13, i64* %3
%14 = load i64, i64* %3
store volatile i64 %14, i64* inttoptr (i64 4060086288 to i64*)
br label %58
15: ; preds = %1
%16 = load i64, i64* %2
%17 = icmp ult i64 %16, 64
br i1 %17, label %18, label %28
18: ; preds = %15
%19 = load volatile i64, i64* inttoptr (i64 4061134864 to i64*)
store i64 %19, i64* %3
%20 = load i64, i64* %2
%21 = sub i64 %20, 32
%22 = trunc i64 %21 to i32
%23 = shl i32 1, %22
%24 = sext i32 %23 to i64
%25 = load i64, i64* %3
%26 = or i64 %25, %24
store i64 %26, i64* %3
%27 = load i64, i64* %3
store volatile i64 %27, i64* inttoptr (i64 4061134864 to i64*)
br label %57
28: ; preds = %15
%29 = load i64, i64* %2
%30 = icmp ult i64 %29, 96
br i1 %30, label %31, label %41
31: ; preds = %28
%32 = load volatile i64, i64* inttoptr (i64 4062183440 to i64*)
store i64 %32, i64* %3
%33 = load i64, i64* %2
%34 = sub i64 %33, 64
%35 = trunc i64 %34 to i32
%36 = shl i32 1, %35
%37 = sext i32 %36 to i64
%38 = load i64, i64* %3
%39 = or i64 %38, %37
store i64 %39, i64* %3
%40 = load i64, i64* %3
store volatile i64 %40, i64* inttoptr (i64 4062183440 to i64*)
br label %56
41: ; preds = %28
%42 = load i64, i64* %2
%43 = icmp ult i64 %42, 200
br i1 %43, label %44, label %54
44: ; preds = %41
%45 = load volatile i64, i64* inttoptr (i64 4063232016 to i64*)
store i64 %45, i64* %3
%46 = load i64, i64* %2
%47 = sub i64 %46, 96
%48 = trunc i64 %47 to i32
%49 = shl i32 1, %48
%50 = sext i32 %49 to i64
%51 = load i64, i64* %3
%52 = or i64 %51, %50
store i64 %52, i64* %3
%53 = load i64, i64* %3
store volatile i64 %53, i64* inttoptr (i64 4063232016 to i64*)
br label %55
54: ; preds = %41
store volatile i64 4294967295, i64* inttoptr (i64 4060086288 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4061134864 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4062183440 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4063232016 to i64*)
br label %55
55: ; preds = %54, %44
br label %56
56: ; preds = %55, %31
br label %57
57: ; preds = %56, %18
br label %58
58: ; preds = %57, %6
ret void
}

LLVM IR (-O2):
define void @intc_enable(i64 %0) {
%2 = icmp ult i64 %0, 32
br i1 %2, label %3, label %9
3: ; preds = %1
%4 = load volatile i64, i64* inttoptr (i64 4060086288 to i64*)
%5 = trunc i64 %0 to i32
%6 = shl nuw i32 1, %5
%7 = sext i32 %6 to i64
%8 = or i64 %4, %7
store volatile i64 %8, i64* inttoptr (i64 4060086288 to i64*)
br label %37
9: ; preds = %1
%10 = icmp ult i64 %0, 64
br i1 %10, label %11, label %18
11: ; preds = %9
%12 = load volatile i64, i64* inttoptr (i64 4061134864 to i64*)
%13 = trunc i64 %0 to i32
%14 = add nsw i32 %13, -32
%15 = shl nuw i32 1, %14
%16 = sext i32 %15 to i64
%17 = or i64 %12, %16
store volatile i64 %17, i64* inttoptr (i64 4061134864 to i64*)
br label %37
18: ; preds = %9
%19 = icmp ult i64 %0, 96
br i1 %19, label %20, label %27
20: ; preds = %18
%21 = load volatile i64, i64* inttoptr (i64 4062183440 to i64*)
%22 = trunc i64 %0 to i32
%23 = add nsw i32 %22, -64
%24 = shl nuw i32 1, %23
%25 = sext i32 %24 to i64
%26 = or i64 %21, %25
store volatile i64 %26, i64* inttoptr (i64 4062183440 to i64*)
br label %37
27: ; preds = %18
%28 = icmp ult i64 %0, 200
br i1 %28, label %29, label %36
29: ; preds = %27
%30 = load volatile i64, i64* inttoptr (i64 4063232016 to i64*)
%31 = trunc i64 %0 to i32
%32 = add nsw i32 %31, -96
%33 = shl nuw i32 1, %32
%34 = sext i32 %33 to i64
%35 = or i64 %30, %34
store volatile i64 %35, i64* inttoptr (i64 4063232016 to i64*)
br label %37
36: ; preds = %27
store volatile i64 4294967295, i64* inttoptr (i64 4060086288 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4061134864 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4062183440 to i64*)
store volatile i64 4294967295, i64* inttoptr (i64 4063232016 to i64*)
br label %37
37: ; preds = %11, %29, %36, %20, %3
ret void
}