float bounceEaseOutf(float p) {
  if (p < 4 / 11.0) {
    return (121 * p * p) / 16.0;
  } else if (p < 8 / 11.0) {
    return (363 / 40.0 * p * p) - (99 / 10.0 * p) + 17 / 5.0;
  } else if (p < 9 / 10.0) {
    return (4356 / 361.0 * p * p) - (35442 / 1805.0 * p) + 16061 / 1805.0;
  } else {
    return (54 / 5.0 * p * p) - (513 / 25.0 * p) + 268 / 25.0;
  }
}


x86 assembly (clang, -O0):
<bounceEaseOutf>:
push   %rbp
mov    %rsp,%rbp
movss  %xmm0,-0x8(%rbp)
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xee6(%rip),%xmm0
ucomisd %xmm1,%xmm0
jbe    1154 <bounceEaseOutf+0x54>
movss  0xf3c(%rip),%xmm0
mulss  -0x8(%rbp),%xmm0
mulss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm0
movsd  0xf1e(%rip),%xmm1
divsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    12c9 <bounceEaseOutf+0x1c9>
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xea3(%rip),%xmm0
ucomisd %xmm1,%xmm0
jbe    11db <bounceEaseOutf+0xdb>
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xed8(%rip),%xmm0
mulsd  %xmm1,%xmm0
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm3
movsd  0xeb2(%rip),%xmm1
mulsd  %xmm3,%xmm1
movq   %xmm1,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xe7f(%rip),%xmm1
addsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    12c9 <bounceEaseOutf+0x1c9>
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xe24(%rip),%xmm0
ucomisd %xmm1,%xmm0
jbe    1262 <bounceEaseOutf+0x162>
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xe39(%rip),%xmm0
mulsd  %xmm1,%xmm0
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm3
movsd  0xe13(%rip),%xmm1
mulsd  %xmm3,%xmm1
movq   %xmm1,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xde0(%rip),%xmm1
addsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    12c9 <bounceEaseOutf+0x1c9>
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xdb5(%rip),%xmm0
mulsd  %xmm1,%xmm0
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm3
movsd  0xd8f(%rip),%xmm1
mulsd  %xmm3,%xmm1
movq   %xmm1,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xd5c(%rip),%xmm1
addsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movss  %xmm0,-0x4(%rbp)
movss  -0x4(%rbp),%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<bounceEaseOutf>:
cvtss2sd %xmm0,%xmm1
movsd  0xef4(%rip),%xmm2
ucomisd %xmm1,%xmm2
jbe    1136 <bounceEaseOutf+0x36>
movss  0xf4e(%rip),%xmm1
mulss  %xmm0,%xmm1
mulss  %xmm0,%xmm1
cvtss2sd %xmm1,%xmm1
mulsd  0xf32(%rip),%xmm1
xorps  %xmm0,%xmm0
cvtsd2ss %xmm1,%xmm0
ret
movsd  0xeca(%rip),%xmm0
ucomisd %xmm1,%xmm0
jbe    1170 <bounceEaseOutf+0x70>
movsd  0xefc(%rip),%xmm0
mulsd  %xmm1,%xmm0
mulsd  %xmm1,%xmm0
mulsd  0xef4(%rip),%xmm1
addsd  %xmm0,%xmm1
addsd  0xef0(%rip),%xmm1
xorps  %xmm0,%xmm0
cvtsd2ss %xmm1,%xmm0
ret
movsd  0xe98(%rip),%xmm0
ucomisd %xmm1,%xmm0
jbe    11aa <bounceEaseOutf+0xaa>
movsd  0xeaa(%rip),%xmm0
mulsd  %xmm1,%xmm0
mulsd  %xmm1,%xmm0
mulsd  0xea2(%rip),%xmm1
addsd  %xmm0,%xmm1
addsd  0xe9e(%rip),%xmm1
xorps  %xmm0,%xmm0
cvtsd2ss %xmm1,%xmm0
ret
movsd  0xe66(%rip),%xmm0
mulsd  %xmm1,%xmm0
mulsd  %xmm1,%xmm0
mulsd  0xe5e(%rip),%xmm1
addsd  %xmm0,%xmm1
addsd  0xe5a(%rip),%xmm1
xorps  %xmm0,%xmm0
cvtsd2ss %xmm1,%xmm0
ret

LLVM IR (-O0):
define float @bounceEaseOutf(float %0) {
%2 = alloca float
%3 = alloca float
store float %0, float* %3
%4 = load float, float* %3
%5 = fpext float %4 to double
%6 = fcmp olt double %5, 0x3FD745D1745D1746
br i1 %6, label %7, label %15
7: ; preds = %1
%8 = load float, float* %3
%9 = fmul float 1.210000e+02, %8
%10 = load float, float* %3
%11 = fmul float %9, %10
%12 = fpext float %11 to double
%13 = fdiv double %12, 1.600000e+01
%14 = fptrunc double %13 to float
store float %14, float* %2
br label %62
15: ; preds = %1
%16 = load float, float* %3
%17 = fpext float %16 to double
%18 = fcmp olt double %17, 0x3FE745D1745D1746
br i1 %18, label %19, label %32
19: ; preds = %15
%20 = load float, float* %3
%21 = fpext float %20 to double
%22 = fmul double 0x4022266666666666, %21
%23 = load float, float* %3
%24 = fpext float %23 to double
%25 = load float, float* %3
%26 = fpext float %25 to double
%27 = fmul double 9.900000e+00, %26
%28 = fneg double %27
%29 = call double @llvm.fmuladd.f64(double %22, double %24, double %28)
%30 = fadd double %29, 3.400000e+00
%31 = fptrunc double %30 to float
store float %31, float* %2
br label %62
32: ; preds = %15
%33 = load float, float* %3
%34 = fpext float %33 to double
%35 = fcmp olt double %34, 9.000000e-01
br i1 %35, label %36, label %49
36: ; preds = %32
%37 = load float, float* %3
%38 = fpext float %37 to double
%39 = fmul double 0x40282209ED8FF4A7, %38
%40 = load float, float* %3
%41 = fpext float %40 to double
%42 = load float, float* %3
%43 = fpext float %42 to double
%44 = fmul double 0x4033A2AD506AA7A4, %43
%45 = fneg double %44
%46 = call double @llvm.fmuladd.f64(double %39, double %41, double %45)
%47 = fadd double %46, 0x4021CBCEA4CDEF44
%48 = fptrunc double %47 to float
store float %48, float* %2
br label %62
49: ; preds = %32
%50 = load float, float* %3
%51 = fpext float %50 to double
%52 = fmul double 1.080000e+01, %51
%53 = load float, float* %3
%54 = fpext float %53 to double
%55 = load float, float* %3
%56 = fpext float %55 to double
%57 = fmul double 2.052000e+01, %56
%58 = fneg double %57
%59 = call double @llvm.fmuladd.f64(double %52, double %54, double %58)
%60 = fadd double %59, 1.072000e+01
%61 = fptrunc double %60 to float
store float %61, float* %2
br label %62
62: ; preds = %49, %36, %19, %7
%63 = load float, float* %2
ret float %63
}

LLVM IR (-O2):
define float @bounceEaseOutf(float %0) {
%2 = fpext float %0 to double
%3 = fcmp olt double %2, 0x3FD745D1745D1746
br i1 %3, label %4, label %9
4: ; preds = %1
%5 = fmul float %0, 1.210000e+02
%6 = fmul float %5, %0
%7 = fpext float %6 to double
%8 = fmul double %7, 6.250000e-02
br label %28
9: ; preds = %1
%10 = fcmp olt double %2, 0x3FE745D1745D1746
br i1 %10, label %11, label %16
11: ; preds = %9
%12 = fmul double %2, 0x4022266666666666
%13 = fmul double %2, -9.900000e+00
%14 = tail call double @llvm.fmuladd.f64(double %12, double %2, double %13)
%15 = fadd double %14, 3.400000e+00
br label %28
16: ; preds = %9
%17 = fcmp olt double %2, 9.000000e-01
br i1 %17, label %18, label %23
18: ; preds = %16
%19 = fmul double %2, 0x40282209ED8FF4A7
%20 = fmul double %2, 0xC033A2AD506AA7A4
%21 = tail call double @llvm.fmuladd.f64(double %19, double %2, double %20)
%22 = fadd double %21, 0x4021CBCEA4CDEF44
br label %28
23: ; preds = %16
%24 = fmul double %2, 1.080000e+01
%25 = fmul double %2, -2.052000e+01
%26 = tail call double @llvm.fmuladd.f64(double %24, double %2, double %25)
%27 = fadd double %26, 1.072000e+01
br label %28
28: ; preds = %23, %18, %11, %4
%29 = phi double [ %8, %4 ], [ %15, %11 ], [ %22, %18 ], [ %27, %23 ]
%30 = fptrunc double %29 to float
ret float %30
}