int main() {
  unsigned char uc;
  signed char sc;
  uc = 0xFF;
  uc = uc >> 1;
  uc = 0;
  uc = 0x00;
  uc = uc >> 1;
  uc = 0;
  uc = 0x01;
  uc = uc >> 1;
  uc = 0;
  uc = 0x80;
  uc = uc >> 1;
  uc = 0;
  uc = 0xAA;
  uc = uc >> 1;
  uc = 0;
  uc = 0x3C;
  uc = uc >> 2;
  uc = 0;
  sc = 0xFF;
  sc = sc >> 1;
  sc = 0;
  sc = 0x00;
  sc = sc >> 1;
  sc = 0;
  sc = 0x01;
  sc = sc >> 1;
  sc = 0;
  sc = 0x80;
  sc = sc >> 1;
  sc = 0;
  sc = 0xAA;
  sc = sc >> 1;
  sc = 0;
  sc = 0x3C;
  sc = sc >> 2;
  sc = 0;
  uc = 0xFF;
  uc = uc << 1;
  uc = 0;
  uc = 0x00;
  uc = uc << 1;
  uc = 0;
  uc = 0x01;
  uc = uc << 1;
  uc = 0;
  uc = 0x80;
  uc = uc << 1;
  uc = 0;
  uc = 0xAA;
  uc = uc << 1;
  uc = 0;
  uc = 0x3C;
  uc = uc << 2;
  uc = 0;
  sc = 0xFF;
  sc = sc << 1;
  sc = 0;
  sc = 0x00;
  sc = sc << 1;
  sc = 0;
  sc = 0x01;
  sc = sc << 1;
  sc = 0;
  sc = 0x80;
  sc = sc << 1;
  sc = 0;
  sc = 0xAA;
  sc = sc << 1;
  sc = 0;
  sc = 0x3C;
  sc = sc << 2;
  sc = 0;
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
movl   $0x0,-0x4(%rbp)
movb   $0xff,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x1,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x80,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0xaa,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x3c,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
sar    $0x2,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0xff,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x1,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x80,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0xaa,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x3c,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
sar    $0x2,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0xff,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x1,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x80,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0xaa,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0x3c,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
shl    $0x2,%eax
mov    %al,-0x5(%rbp)
movb   $0x0,-0x5(%rbp)
movb   $0xff,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x1,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x80,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0xaa,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
movb   $0x3c,-0x6(%rbp)
movsbl -0x6(%rbp),%eax
shl    $0x2,%eax
mov    %al,-0x6(%rbp)
movb   $0x0,-0x6(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca i8
%3 = alloca i8
store i32 0, i32* %1
store i8 -1, i8* %2
%4 = load i8, i8* %2
%5 = zext i8 %4 to i32
%6 = ashr i32 %5, 1
%7 = trunc i32 %6 to i8
store i8 %7, i8* %2
store i8 0, i8* %2
store i8 0, i8* %2
%8 = load i8, i8* %2
%9 = zext i8 %8 to i32
%10 = ashr i32 %9, 1
%11 = trunc i32 %10 to i8
store i8 %11, i8* %2
store i8 0, i8* %2
store i8 1, i8* %2
%12 = load i8, i8* %2
%13 = zext i8 %12 to i32
%14 = ashr i32 %13, 1
%15 = trunc i32 %14 to i8
store i8 %15, i8* %2
store i8 0, i8* %2
store i8 -128, i8* %2
%16 = load i8, i8* %2
%17 = zext i8 %16 to i32
%18 = ashr i32 %17, 1
%19 = trunc i32 %18 to i8
store i8 %19, i8* %2
store i8 0, i8* %2
store i8 -86, i8* %2
%20 = load i8, i8* %2
%21 = zext i8 %20 to i32
%22 = ashr i32 %21, 1
%23 = trunc i32 %22 to i8
store i8 %23, i8* %2
store i8 0, i8* %2
store i8 60, i8* %2
%24 = load i8, i8* %2
%25 = zext i8 %24 to i32
%26 = ashr i32 %25, 2
%27 = trunc i32 %26 to i8
store i8 %27, i8* %2
store i8 0, i8* %2
store i8 -1, i8* %3
%28 = load i8, i8* %3
%29 = sext i8 %28 to i32
%30 = ashr i32 %29, 1
%31 = trunc i32 %30 to i8
store i8 %31, i8* %3
store i8 0, i8* %3
store i8 0, i8* %3
%32 = load i8, i8* %3
%33 = sext i8 %32 to i32
%34 = ashr i32 %33, 1
%35 = trunc i32 %34 to i8
store i8 %35, i8* %3
store i8 0, i8* %3
store i8 1, i8* %3
%36 = load i8, i8* %3
%37 = sext i8 %36 to i32
%38 = ashr i32 %37, 1
%39 = trunc i32 %38 to i8
store i8 %39, i8* %3
store i8 0, i8* %3
store i8 -128, i8* %3
%40 = load i8, i8* %3
%41 = sext i8 %40 to i32
%42 = ashr i32 %41, 1
%43 = trunc i32 %42 to i8
store i8 %43, i8* %3
store i8 0, i8* %3
store i8 -86, i8* %3
%44 = load i8, i8* %3
%45 = sext i8 %44 to i32
%46 = ashr i32 %45, 1
%47 = trunc i32 %46 to i8
store i8 %47, i8* %3
store i8 0, i8* %3
store i8 60, i8* %3
%48 = load i8, i8* %3
%49 = sext i8 %48 to i32
%50 = ashr i32 %49, 2
%51 = trunc i32 %50 to i8
store i8 %51, i8* %3
store i8 0, i8* %3
store i8 -1, i8* %2
%52 = load i8, i8* %2
%53 = zext i8 %52 to i32
%54 = shl i32 %53, 1
%55 = trunc i32 %54 to i8
store i8 %55, i8* %2
store i8 0, i8* %2
store i8 0, i8* %2
%56 = load i8, i8* %2
%57 = zext i8 %56 to i32
%58 = shl i32 %57, 1
%59 = trunc i32 %58 to i8
store i8 %59, i8* %2
store i8 0, i8* %2
store i8 1, i8* %2
%60 = load i8, i8* %2
%61 = zext i8 %60 to i32
%62 = shl i32 %61, 1
%63 = trunc i32 %62 to i8
store i8 %63, i8* %2
store i8 0, i8* %2
store i8 -128, i8* %2
%64 = load i8, i8* %2
%65 = zext i8 %64 to i32
%66 = shl i32 %65, 1
%67 = trunc i32 %66 to i8
store i8 %67, i8* %2
store i8 0, i8* %2
store i8 -86, i8* %2
%68 = load i8, i8* %2
%69 = zext i8 %68 to i32
%70 = shl i32 %69, 1
%71 = trunc i32 %70 to i8
store i8 %71, i8* %2
store i8 0, i8* %2
store i8 60, i8* %2
%72 = load i8, i8* %2
%73 = zext i8 %72 to i32
%74 = shl i32 %73, 2
%75 = trunc i32 %74 to i8
store i8 %75, i8* %2
store i8 0, i8* %2
store i8 -1, i8* %3
%76 = load i8, i8* %3
%77 = sext i8 %76 to i32
%78 = shl i32 %77, 1
%79 = trunc i32 %78 to i8
store i8 %79, i8* %3
store i8 0, i8* %3
store i8 0, i8* %3
%80 = load i8, i8* %3
%81 = sext i8 %80 to i32
%82 = shl i32 %81, 1
%83 = trunc i32 %82 to i8
store i8 %83, i8* %3
store i8 0, i8* %3
store i8 1, i8* %3
%84 = load i8, i8* %3
%85 = sext i8 %84 to i32
%86 = shl i32 %85, 1
%87 = trunc i32 %86 to i8
store i8 %87, i8* %3
store i8 0, i8* %3
store i8 -128, i8* %3
%88 = load i8, i8* %3
%89 = sext i8 %88 to i32
%90 = shl i32 %89, 1
%91 = trunc i32 %90 to i8
store i8 %91, i8* %3
store i8 0, i8* %3
store i8 -86, i8* %3
%92 = load i8, i8* %3
%93 = sext i8 %92 to i32
%94 = shl i32 %93, 1
%95 = trunc i32 %94 to i8
store i8 %95, i8* %3
store i8 0, i8* %3
store i8 60, i8* %3
%96 = load i8, i8* %3
%97 = sext i8 %96 to i32
%98 = shl i32 %97, 2
%99 = trunc i32 %98 to i8
store i8 %99, i8* %3
store i8 0, i8* %3
ret i32 0
}

LLVM IR (-O2):
define i32 @main() {
ret i32 0
}