#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
unsigned long long nanotime();
unsigned long long rdtsc();
float cpu_get_speed_mhz(void) {
  unsigned long long diff1, diff2;
  unsigned long long val11, val12, val21, val22;
  val11 = nanotime();
  val21 = rdtsc();
  while ((val12 = nanotime()) < val11 + 50000)
    val22 = rdtsc();
  diff1 = (unsigned long long)((unsigned long long)val22 -
                               (unsigned long long)val21);
  diff2 = (unsigned long long)((unsigned long long)val12 -
                               (unsigned long long)val11);
  return ((float)diff1 / diff2);
}


x86 assembly (clang, -O0):
<cpu_get_speed_mhz>:
push   %rbp
mov    %rsp,%rbp
sub    $0x50,%rsp
mov    $0x0,%al
call   1040 <nanotime@plt>
mov    %rax,-0x18(%rbp)
mov    $0x0,%al
call   1030 <rdtsc@plt>
mov    %rax,-0x28(%rbp)
mov    $0x0,%al
call   1040 <nanotime@plt>
mov    %rax,-0x20(%rbp)
mov    -0x18(%rbp),%rcx
add    $0xc350,%rcx
cmp    %rcx,%rax
jae    116d <cpu_get_speed_mhz+0x4d>
mov    $0x0,%al
call   1030 <rdtsc@plt>
mov    %rax,-0x30(%rbp)
jmp    113e <cpu_get_speed_mhz+0x1e>
mov    -0x30(%rbp),%rax
mov    -0x28(%rbp),%rcx
sub    %rcx,%rax
mov    %rax,-0x8(%rbp)
mov    -0x20(%rbp),%rax
mov    -0x18(%rbp),%rcx
sub    %rcx,%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,%rdx
shr    %rdx
mov    %eax,%ecx
and    $0x1,%ecx
or     %rdx,%rcx
cvtsi2ss %rcx,%xmm0
addss  %xmm0,%xmm0
cvtsi2ss %rax,%xmm1
movss  %xmm1,-0x38(%rbp)
test   %rax,%rax
movss  %xmm0,-0x34(%rbp)
js     11c8 <cpu_get_speed_mhz+0xa8>
movss  -0x38(%rbp),%xmm0
movss  %xmm0,-0x34(%rbp)
movss  -0x34(%rbp),%xmm0
movss  %xmm0,-0x44(%rbp)
mov    -0x10(%rbp),%rax
mov    %rax,%rdx
shr    %rdx
mov    %eax,%ecx
and    $0x1,%ecx
or     %rdx,%rcx
cvtsi2ss %rcx,%xmm0
addss  %xmm0,%xmm0
cvtsi2ss %rax,%xmm1
movss  %xmm1,-0x40(%rbp)
test   %rax,%rax
movss  %xmm0,-0x3c(%rbp)
js     120f <cpu_get_speed_mhz+0xef>
movss  -0x40(%rbp),%xmm0
movss  %xmm0,-0x3c(%rbp)
movss  -0x44(%rbp),%xmm0
movss  -0x3c(%rbp),%xmm1
divss  %xmm1,%xmm0
add    $0x50,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<cpu_get_speed_mhz>:
push   %r15
push   %r14
push   %r12
push   %rbx
push   %rax
xor    %eax,%eax
call   1040 <nanotime@plt>
mov    %rax,%r15
xor    %eax,%eax
call   1030 <rdtsc@plt>
mov    %rax,%r14
xor    %eax,%eax
call   1040 <nanotime@plt>
lea    0xc350(%r15),%r12
cmp    %r12,%rax
jae    1168 <cpu_get_speed_mhz+0x48>
nop
xor    %eax,%eax
call   1030 <rdtsc@plt>
mov    %rax,%rbx
xor    %eax,%eax
call   1040 <nanotime@plt>
cmp    %r12,%rax
jb     1150 <cpu_get_speed_mhz+0x30>
jmp    1168 <cpu_get_speed_mhz+0x48>
sub    %r14,%rbx
sub    %r15,%rax
test   %rbx,%rbx
js     1194 <cpu_get_speed_mhz+0x74>
cvtsi2ss %rbx,%xmm0
test   %rax,%rax
jns    11ae <cpu_get_speed_mhz+0x8e>
mov    %rax,%rcx
shr    %rcx
and    $0x1,%eax
or     %rcx,%rax
cvtsi2ss %rax,%xmm1
addss  %xmm1,%xmm1
jmp    11b3 <cpu_get_speed_mhz+0x93>
mov    %rbx,%rcx
shr    %rcx
and    $0x1,%ebx
or     %rcx,%rbx
cvtsi2ss %rbx,%xmm0
addss  %xmm0,%xmm0
test   %rax,%rax
js     117d <cpu_get_speed_mhz+0x5d>
cvtsi2ss %rax,%xmm1
divss  %xmm1,%xmm0
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define float @cpu_get_speed_mhz() {
%1 = alloca i64
%2 = alloca i64
%3 = alloca i64
%4 = alloca i64
%5 = alloca i64
%6 = alloca i64
%7 = call i64 (...) @nanotime()
store i64 %7, i64* %3
%8 = call i64 (...) @rdtsc()
store i64 %8, i64* %5
br label %9
9: ; preds = %14, %0
%10 = call i64 (...) @nanotime()
store i64 %10, i64* %4
%11 = load i64, i64* %3
%12 = add i64 %11, 50000
%13 = icmp ult i64 %10, %12
br i1 %13, label %14, label %16
14: ; preds = %9
%15 = call i64 (...) @rdtsc()
store i64 %15, i64* %6
br label %9
16: ; preds = %9
%17 = load i64, i64* %6
%18 = load i64, i64* %5
%19 = sub i64 %17, %18
store i64 %19, i64* %1
%20 = load i64, i64* %4
%21 = load i64, i64* %3
%22 = sub i64 %20, %21
store i64 %22, i64* %2
%23 = load i64, i64* %1
%24 = uitofp i64 %23 to float
%25 = load i64, i64* %2
%26 = uitofp i64 %25 to float
%27 = fdiv float %24, %26
ret float %27
}

LLVM IR (-O2):
define float @cpu_get_speed_mhz() {
%1 = tail call i64 (...) @nanotime()
%2 = tail call i64 (...) @rdtsc()
%3 = tail call i64 (...) @nanotime()
%4 = add i64 %1, 50000
%5 = icmp ult i64 %3, %4
br i1 %5, label %6, label %10
6: ; preds = %0, %6
%7 = tail call i64 (...) @rdtsc()
%8 = tail call i64 (...) @nanotime()
%9 = icmp ult i64 %8, %4
br i1 %9, label %6, label %10
10: ; preds = %6, %0
%11 = phi i64 [ undef, %0 ], [ %7, %6 ]
%12 = phi i64 [ %3, %0 ], [ %8, %6 ]
%13 = sub i64 %11, %2
%14 = sub i64 %12, %1
%15 = uitofp i64 %13 to float
%16 = uitofp i64 %14 to float
%17 = fdiv float %15, %16
ret float %17
}