int in_alpha(const int glyph) {
  int retval = 0;
  char cglyph = (char)glyph;
  if ((cglyph >= '0') && (cglyph <= '9')) {
    retval = 1;
  }
  if ((cglyph >= 'A') && (cglyph <= 'Z')) {
    retval = 1;
  }
  switch (cglyph) {
  case ' ':
  case '$':
  case '%':
  case '*':
  case '+':
  case '-':
  case '.':
  case '/':
  case ':':
    retval = 1;
    break;
  }
  return retval;
}


x86 assembly (clang, -O0):
<in_alpha>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
movl   $0x0,-0x8(%rbp)
mov    -0x4(%rbp),%eax
mov    %al,-0x9(%rbp)
movsbl -0x9(%rbp),%eax
cmp    $0x30,%eax
jl     1135 <in_alpha+0x35>
movsbl -0x9(%rbp),%eax
cmp    $0x39,%eax
jg     1135 <in_alpha+0x35>
movl   $0x1,-0x8(%rbp)
movsbl -0x9(%rbp),%eax
cmp    $0x41,%eax
jl     1156 <in_alpha+0x56>
movsbl -0x9(%rbp),%eax
cmp    $0x5a,%eax
jg     1156 <in_alpha+0x56>
movl   $0x1,-0x8(%rbp)
movsbl -0x9(%rbp),%eax
mov    %eax,-0x10(%rbp)
sub    $0x20,%eax
je     11b8 <in_alpha+0xb8>
jmp    116b <in_alpha+0x6b>
mov    -0x10(%rbp),%eax
add    $0xffffffdc,%eax
sub    $0x2,%eax
jb     11b8 <in_alpha+0xb8>
jmp    117f <in_alpha+0x7f>
mov    -0x10(%rbp),%eax
add    $0xffffffd6,%eax
sub    $0x2,%eax
jb     11b8 <in_alpha+0xb8>
jmp    1193 <in_alpha+0x93>
mov    -0x10(%rbp),%eax
add    $0xffffffd3,%eax
sub    $0x3,%eax
jb     11b8 <in_alpha+0xb8>
jmp    11a7 <in_alpha+0xa7>
mov    -0x10(%rbp),%eax
sub    $0x3a,%eax
jne    11bf <in_alpha+0xbf>
jmp    11b8 <in_alpha+0xb8>
movl   $0x1,-0x8(%rbp)
mov    -0x8(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<in_alpha>:
movsbl %dil,%ecx
mov    %edi,%eax
shl    $0x18,%eax
lea    -0x2f000001(%rax),%edx
cmp    $0xaffffff,%edx
setb   %dl
add    $0xbfffffff,%eax
cmp    $0x1affffff,%eax
setb   %al
or     %dl,%al
movzbl %al,%eax
cmp    $0x3a,%ecx
ja     1144 <in_alpha+0x44>
movabs $0x400ec3100000000,%rdx
bt     %rcx,%rdx
jae    1144 <in_alpha+0x44>
mov    $0x1,%eax
ret

LLVM IR (-O0):
define i32 @in_alpha(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i8
store i32 %0, i32* %2
store i32 0, i32* %3
%5 = load i32, i32* %2
%6 = trunc i32 %5 to i8
store i8 %6, i8* %4
%7 = load i8, i8* %4
%8 = sext i8 %7 to i32
%9 = icmp sge i32 %8, 48
br i1 %9, label %10, label %15
10: ; preds = %1
%11 = load i8, i8* %4
%12 = sext i8 %11 to i32
%13 = icmp sle i32 %12, 57
br i1 %13, label %14, label %15
14: ; preds = %10
store i32 1, i32* %3
br label %15
15: ; preds = %14, %10, %1
%16 = load i8, i8* %4
%17 = sext i8 %16 to i32
%18 = icmp sge i32 %17, 65
br i1 %18, label %19, label %24
19: ; preds = %15
%20 = load i8, i8* %4
%21 = sext i8 %20 to i32
%22 = icmp sle i32 %21, 90
br i1 %22, label %23, label %24
23: ; preds = %19
store i32 1, i32* %3
br label %24
24: ; preds = %23, %19, %15
%25 = load i8, i8* %4
%26 = sext i8 %25 to i32
switch i32 %26, label %28 [
i32 32, label %27
i32 36, label %27
i32 37, label %27
i32 42, label %27
i32 43, label %27
i32 45, label %27
i32 46, label %27
i32 47, label %27
i32 58, label %27
]
27: ; preds = %24, %24, %24, %24, %24, %24, %24, %24, %24
store i32 1, i32* %3
br label %28
28: ; preds = %24, %27
%29 = load i32, i32* %3
ret i32 %29
}

LLVM IR (-O2):
define i32 @in_alpha(i32 %0) {
%2 = shl i32 %0, 24
%3 = ashr exact i32 %2, 24
%4 = add i32 %2, -788529153
%5 = icmp ult i32 %4, 184549375
%6 = add i32 %2, -1073741825
%7 = icmp ult i32 %6, 452984831
%8 = or i1 %7, %5
%9 = zext i1 %8 to i32
switch i32 %3, label %11 [
i32 32, label %10
i32 36, label %10
i32 37, label %10
i32 42, label %10
i32 43, label %10
i32 45, label %10
i32 46, label %10
i32 47, label %10
i32 58, label %10
]
10: ; preds = %1, %1, %1, %1, %1, %1, %1, %1, %1
br label %11
11: ; preds = %1, %10
%12 = phi i32 [ %9, %1 ], [ 1, %10 ]
ret i32 %12
}