xunge/DecIR huggingface dataset:
/* Variables and functions */
int /*<<< orphan*/ ft_putchar(int);
void ft_putnbr(int nb) {
  if (nb < 0) {
    ft_putchar('-');
    nb *= -1;
  }
  if (nb > 9)
    ft_putnbr(nb / 10);
  ft_putchar(nb % 10 + '0');
}


x86 assembly (clang, -O0):
<ft_putnbr>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
cmpl   $0x0,-0x4(%rbp)
jge    1146 <ft_putnbr+0x26>
mov    $0x2d,%edi
call   1030 <ft_putchar@plt>
imul   $0xffffffff,-0x4(%rbp),%eax
mov    %eax,-0x4(%rbp)
cmpl   $0x9,-0x4(%rbp)
jle    1162 <ft_putnbr+0x42>
mov    -0x4(%rbp),%eax
mov    $0xa,%ecx
cltd
idiv   %ecx
mov    %eax,%edi
call   1040 <ft_putnbr@plt>
mov    -0x4(%rbp),%eax
mov    $0xa,%ecx
cltd
idiv   %ecx
mov    %edx,%edi
add    $0x30,%edi
call   1030 <ft_putchar@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ft_putnbr>:
push   %r14
push   %rbx
push   %rax
mov    %edi,%ebx
test   %edi,%edi
jns    1136 <ft_putnbr+0x16>
mov    $0x2d,%edi
call   1030 <ft_putchar@plt>
neg    %ebx
mov    %ebx,%r14d
cmp    $0xa,%ebx
jb     1150 <ft_putnbr+0x30>
mov    $0xcccccccd,%edi
imul   %r14,%rdi
shr    $0x23,%rdi
call   1040 <ft_putnbr@plt>
mov    $0xcccccccd,%eax
imul   %r14,%rax
shr    $0x23,%rax
add    %eax,%eax
lea    (%rax,%rax,4),%eax
sub    %eax,%ebx
or     $0x30,%ebx
mov    %ebx,%edi
add    $0x8,%rsp
pop    %rbx
pop    %r14
jmp    1030 <ft_putchar@plt>

LLVM IR (-O0):
define void @ft_putnbr(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp slt i32 %3, 0
br i1 %4, label %5, label %9
5: ; preds = %1
%6 = call i32 @ft_putchar(i32 45)
%7 = load i32, i32* %2
%8 = mul nsw i32 %7, -1
store i32 %8, i32* %2
br label %9
9: ; preds = %5, %1
%10 = load i32, i32* %2
%11 = icmp sgt i32 %10, 9
br i1 %11, label %12, label %15
12: ; preds = %9
%13 = load i32, i32* %2
%14 = sdiv i32 %13, 10
br label %15
15: ; preds = %12, %9
%16 = load i32, i32* %2
%17 = srem i32 %16, 10
%18 = add nsw i32 %17, 48
%19 = call i32 @ft_putchar(i32 %18)
ret void
}

LLVM IR (-O2):
define void @ft_putnbr(i32 %0) {
%2 = icmp slt i32 %0, 0
br i1 %2, label %3, label %6
3: ; preds = %1
%4 = tail call i32 @ft_putchar(i32 45)
%5 = sub nsw i32 0, %0
br label %6
6: ; preds = %3, %1
%7 = phi i32 [ %5, %3 ], [ %0, %1 ]
%8 = icmp ugt i32 %7, 9
br i1 %8, label %9, label %11
9: ; preds = %6
%10 = udiv i32 %7, 10
tail call void @ft_putnbr(i32 %10)
br label %11
11: ; preds = %9, %6
%12 = urem i32 %7, 10
%13 = or i32 %12, 48
%14 = tail call i32 @ft_putchar(i32 %13)
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ uint8_t;

/* Variables and functions */
int /*<<< orphan*/ ehrpwm_write(int /*<<< orphan*/, unsigned int,
                                unsigned short);
int ehrpwm_reg_write(uint8_t module, unsigned int reg, unsigned short val) {
  if (reg > 0x1040)
    return -1;
  ehrpwm_write(module, reg, val);
  return 0;
}


x86 assembly (clang, -O0):
<ehrpwm_reg_write>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %dx,%ax
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %ax,-0xe(%rbp)
cmpl   $0x1040,-0xc(%rbp)
jbe    113e <ehrpwm_reg_write+0x2e>
movl   $0xffffffff,-0x4(%rbp)
jmp    1154 <ehrpwm_reg_write+0x44>
mov    -0x8(%rbp),%edi
mov    -0xc(%rbp),%esi
movzwl -0xe(%rbp),%edx
call   1030 <ehrpwm_write@plt>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ehrpwm_reg_write>:
mov    $0xffffffff,%eax
cmp    $0x1040,%esi
ja     112c <ehrpwm_reg_write+0x1c>
push   %rax
movzwl %dx,%edx
call   1030 <ehrpwm_write@plt>
xor    %eax,%eax
add    $0x8,%rsp
ret

LLVM IR (-O0):
define i32 @ehrpwm_reg_write(i32 %0, i32 %1, i16 zeroext %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i16
store i32 %0, i32* %5
store i32 %1, i32* %6
store i16 %2, i16* %7
%8 = load i32, i32* %6
%9 = icmp ugt i32 %8, 4160
br i1 %9, label %10, label %11
10: ; preds = %3
store i32 -1, i32* %4
br label %16
11: ; preds = %3
%12 = load i32, i32* %5
%13 = load i32, i32* %6
%14 = load i16, i16* %7
%15 = call i32 @ehrpwm_write(i32 %12, i32 %13, i16 zeroext %14)
store i32 0, i32* %4
br label %16
16: ; preds = %11, %10
%17 = load i32, i32* %4
ret i32 %17
}

LLVM IR (-O2):
define i32 @ehrpwm_reg_write(i32 %0, i32 %1, i16 zeroext %2) {
%4 = icmp ugt i32 %1, 4160
br i1 %4, label %7, label %5
5: ; preds = %3
%6 = tail call i32 @ehrpwm_write(i32 %0, i32 %1, i16 zeroext %2)
br label %7
7: ; preds = %3, %5
%8 = phi i32 [ 0, %5 ], [ -1, %3 ]
ret i32 %8
}
/* Variables and functions */
int /*<<< orphan*/ F_GETFL;
int /*<<< orphan*/ F_SETFL;
int O_NONBLOCK;
int fcntl(int, int /*<<< orphan*/, int);
int slp_socknoblock(int sock) {
  int flags = fcntl(sock, F_GETFL, 0);
  flags |= O_NONBLOCK;
  if (fcntl(sock, F_SETFL, flags) == -1)
    return -1;
  return 0;
}


x86 assembly (clang, -O0):
<slp_socknoblock>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%edi
mov    0x2eab(%rip),%rax
mov    (%rax),%esi
xor    %edx,%edx
call   1030 <fcntl@plt>
mov    %eax,-0xc(%rbp)
mov    0x2eb0(%rip),%rax
mov    (%rax),%eax
or     -0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%edi
mov    0x2e8e(%rip),%rax
mov    (%rax),%esi
mov    -0xc(%rbp),%edx
call   1030 <fcntl@plt>
cmp    $0xffffffff,%eax
jne    1169 <slp_socknoblock+0x59>
movl   $0xffffffff,-0x4(%rbp)
jmp    1170 <slp_socknoblock+0x60>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<slp_socknoblock>:
push   %rbx
mov    %edi,%ebx
mov    0x2eb6(%rip),%rax
mov    (%rax),%esi
xor    %edx,%edx
call   1030 <fcntl@plt>
mov    0x2ebe(%rip),%rcx
or     (%rcx),%eax
mov    0x2ea5(%rip),%rcx
mov    (%rcx),%esi
mov    %ebx,%edi
mov    %eax,%edx
call   1030 <fcntl@plt>
xor    %ecx,%ecx
cmp    $0xffffffff,%eax
sete   %cl
neg    %ecx
mov    %ecx,%eax
pop    %rbx
ret

LLVM IR (-O0):
@F_GETFL = global i32 0
@O_NONBLOCK = global i32 0
@F_SETFL = global i32 0
define i32 @slp_socknoblock(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
%5 = load i32, i32* %3
%6 = load i32, i32* @F_GETFL
%7 = call i32 @fcntl(i32 %5, i32 %6, i32 0)
store i32 %7, i32* %4
%8 = load i32, i32* @O_NONBLOCK
%9 = load i32, i32* %4
%10 = or i32 %9, %8
store i32 %10, i32* %4
%11 = load i32, i32* %3
%12 = load i32, i32* @F_SETFL
%13 = load i32, i32* %4
%14 = call i32 @fcntl(i32 %11, i32 %12, i32 %13)
%15 = icmp eq i32 %14, -1
br i1 %15, label %16, label %17
16: ; preds = %1
store i32 -1, i32* %2
br label %18
17: ; preds = %1
store i32 0, i32* %2
br label %18
18: ; preds = %17, %16
%19 = load i32, i32* %2
ret i32 %19
}

LLVM IR (-O2):
@F_GETFL = global i32 0
@O_NONBLOCK = global i32 0
@F_SETFL = global i32 0
define i32 @slp_socknoblock(i32 %0) {
%2 = load i32, i32* @F_GETFL
%3 = tail call i32 @fcntl(i32 %0, i32 %2, i32 0)
%4 = load i32, i32* @O_NONBLOCK
%5 = or i32 %4, %3
%6 = load i32, i32* @F_SETFL
%7 = tail call i32 @fcntl(i32 %0, i32 %6, i32 %5)
%8 = icmp eq i32 %7, -1
%9 = sext i1 %8 to i32
ret i32 %9
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *);
int main(void) {
  printf("ABCDE\n");
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x4(%rbp)
lea    0xeda(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rax
lea    0xee8(%rip),%rdi
call   1030 <puts@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [7 x i8] c"ABCDE\0A\00"
define i32 @main() {
%1 = alloca i32
store i32 0, i32* %1
%2 = call i32 @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i64 0, i64 0))
ret i32 0
}

LLVM IR (-O2):
@str = [6 x i8] c"ABCDE\00"
define i32 @main() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([6 x i8], [6 x i8]* @str, i64 0, i64 0))
ret i32 0
}
float __fdimf(float x, float y) { return x <= y ? 0 : x - y; }


x86 assembly (clang, -O0):
<__fdimf>:
push   %rbp
mov    %rsp,%rbp
movss  %xmm0,-0x4(%rbp)
movss  %xmm1,-0x8(%rbp)
movss  -0x4(%rbp),%xmm1
movss  -0x8(%rbp),%xmm0
ucomiss %xmm1,%xmm0
jb     112e <__fdimf+0x2e>
xorps  %xmm0,%xmm0
movss  %xmm0,-0xc(%rbp)
jmp    113d <__fdimf+0x3d>
movss  -0x4(%rbp),%xmm0
subss  -0x8(%rbp),%xmm0
movss  %xmm0,-0xc(%rbp)
movss  -0xc(%rbp),%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<__fdimf>:
movaps %xmm0,%xmm2
subss  %xmm1,%xmm2
cmpless %xmm1,%xmm0
andnps %xmm2,%xmm0
ret

LLVM IR (-O0):
define float @__fdimf(float %0, float %1) {
%3 = alloca float
%4 = alloca float
store float %0, float* %3
store float %1, float* %4
%5 = load float, float* %3
%6 = load float, float* %4
%7 = fcmp ole float %5, %6
br i1 %7, label %8, label %9
8: ; preds = %2
br label %13
9: ; preds = %2
%10 = load float, float* %3
%11 = load float, float* %4
%12 = fsub float %10, %11
br label %13
13: ; preds = %9, %8
%14 = phi float [ 0.000000e+00, %8 ], [ %12, %9 ]
ret float %14
}

LLVM IR (-O2):
define float @__fdimf(float %0, float %1) {
%3 = fcmp ole float %0, %1
%4 = fsub float %0, %1
%5 = select i1 %3, float 0.000000e+00, float %4
ret float %5
}
/* Variables and functions */
int /*<<< orphan*/ HplMsp430GeneralIOP__38__IO__toggle();
void Msp430GpioC__2__HplGeneralIO__toggle(void) {
  HplMsp430GeneralIOP__38__IO__toggle();
}


x86 assembly (clang, -O0):
<Msp430GpioC__2__HplGeneralIO__toggle>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <HplMsp430GeneralIOP__38__IO__toggle@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<Msp430GpioC__2__HplGeneralIO__toggle>:
xor    %eax,%eax
jmp    1030 <HplMsp430GeneralIOP__38__IO__toggle@plt>

LLVM IR (-O0):
define void @Msp430GpioC__2__HplGeneralIO__toggle() {
%1 = call i32 (...) @HplMsp430GeneralIOP__38__IO__toggle()
ret void
}

LLVM IR (-O2):
define void @Msp430GpioC__2__HplGeneralIO__toggle() {
%1 = tail call i32 (...) @HplMsp430GeneralIOP__38__IO__toggle()
ret void
}
/* Variables and functions */
int SSL_CTX_use_PrivateKey_file(void *, char const *, int /*<<< orphan*/);
int /*<<< orphan*/ SSL_FILETYPE_PEM;
int dv_openssl_ctx_use_private_key_file(void *ctx, const char *file) {
  int ret = 0;
  ret = SSL_CTX_use_PrivateKey_file(ctx, file, SSL_FILETYPE_PEM);
  if (ret <= 0) {
    return (-1);
  }
  return 0;
}


x86 assembly (clang, -O0):
<dv_openssl_ctx_use_private_key_file>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
movl   $0x0,-0x1c(%rbp)
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
mov    0x2eb2(%rip),%rax
mov    (%rax),%edx
call   1030 <SSL_CTX_use_PrivateKey_file@plt>
mov    %eax,-0x1c(%rbp)
cmpl   $0x0,-0x1c(%rbp)
jg     1156 <dv_openssl_ctx_use_private_key_file+0x46>
movl   $0xffffffff,-0x4(%rbp)
jmp    115d <dv_openssl_ctx_use_private_key_file+0x4d>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<dv_openssl_ctx_use_private_key_file>:
push   %rax
mov    0x2ed0(%rip),%rax
mov    (%rax),%edx
call   1030 <SSL_CTX_use_PrivateKey_file@plt>
xor    %ecx,%ecx
test   %eax,%eax
setle  %cl
neg    %ecx
mov    %ecx,%eax
pop    %rcx
ret

LLVM IR (-O0):
@SSL_FILETYPE_PEM = global i32 0
define i32 @dv_openssl_ctx_use_private_key_file(i8* %0, i8* %1) {
%3 = alloca i32
%4 = alloca i8*
%5 = alloca i8*
%6 = alloca i32
store i8* %0, i8** %4
store i8* %1, i8** %5
store i32 0, i32* %6
%7 = load i8*, i8** %4
%8 = load i8*, i8** %5
%9 = load i32, i32* @SSL_FILETYPE_PEM
%10 = call i32 @SSL_CTX_use_PrivateKey_file(i8* %7, i8* %8, i32 %9)
store i32 %10, i32* %6
%11 = load i32, i32* %6
%12 = icmp sle i32 %11, 0
br i1 %12, label %13, label %14
13: ; preds = %2
store i32 -1, i32* %3
br label %15
14: ; preds = %2
store i32 0, i32* %3
br label %15
15: ; preds = %14, %13
%16 = load i32, i32* %3
ret i32 %16
}

LLVM IR (-O2):
@SSL_FILETYPE_PEM = global i32 0
define i32 @dv_openssl_ctx_use_private_key_file(i8* %0, i8* %1) {
%3 = load i32, i32* @SSL_FILETYPE_PEM
%4 = tail call i32 @SSL_CTX_use_PrivateKey_file(i8* %0, i8* %1, i32 %3)
%5 = icmp slt i32 %4, 1
%6 = sext i1 %5 to i32
ret i32 %6
}
/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
void LCDIDDConfigSet(uint32_t ui32Base, uint32_t ui32Config) {
  ASSERT(ui32Base == 0x44050000);
  ASSERT(!(ui32Config &
           ~(0x00000000 | 0x00000001 | 0x00000002 | 0x00000003 | 0x00000004 |
             0x00000008 | 0x00000010 | 0x00000020 | 0x00000040 | 0x00000080)));
  (*((volatile uint32_t *)(ui32Base + 0x0000000C))) = ui32Config;
}


x86 assembly (clang, -O0):
<LCDIDDConfigSet>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
cmpl   $0x44050000,-0x4(%rbp)
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0x8(%rbp),%eax
and    $0xffffff00,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0x8(%rbp),%ecx
mov    -0x4(%rbp),%eax
add    $0xc,%eax
cltq
mov    %ecx,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<LCDIDDConfigSet>:
push   %rbp
push   %rbx
push   %rax
mov    %esi,%ebx
mov    %edi,%ebp
xor    %edi,%edi
cmp    $0x44050000,%ebp
sete   %dil
call   1030 <ASSERT@plt>
xor    %edi,%edi
cmp    $0x100,%ebx
setb   %dil
call   1030 <ASSERT@plt>
movslq %ebp,%rax
mov    %ebx,0xc(%rax)
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
define void @LCDIDDConfigSet(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %3
%6 = icmp eq i32 %5, 1141178368
%7 = zext i1 %6 to i32
%8 = call i32 @ASSERT(i32 %7)
%9 = load i32, i32* %4
%10 = and i32 %9, -256
%11 = icmp ne i32 %10, 0
%12 = xor i1 %11, true
%13 = zext i1 %12 to i32
%14 = call i32 @ASSERT(i32 %13)
%15 = load i32, i32* %4
%16 = load i32, i32* %3
%17 = add nsw i32 %16, 12
%18 = sext i32 %17 to i64
%19 = inttoptr i64 %18 to i32*
store volatile i32 %15, i32* %19
ret void
}

LLVM IR (-O2):
define void @LCDIDDConfigSet(i32 %0, i32 %1) {
%3 = icmp eq i32 %0, 1141178368
%4 = zext i1 %3 to i32
%5 = tail call i32 @ASSERT(i32 %4)
%6 = icmp ult i32 %1, 256
%7 = zext i1 %6 to i32
%8 = tail call i32 @ASSERT(i32 %7)
%9 = add nsw i32 %0, 12
%10 = sext i32 %9 to i64
%11 = inttoptr i64 %10 to i32*
store volatile i32 %1, i32* %11
ret void
}
int valid_block_length(int block_length_in_bits) {
  if (block_length_in_bits == 128)
    return 1;
  else if (block_length_in_bits == 192)
    return 1;
  else if (block_length_in_bits == 256)
    return 1;
  else
    return 0;
}


x86 assembly (clang, -O0):
<valid_block_length>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
cmpl   $0x80,-0x8(%rbp)
jne    1120 <valid_block_length+0x20>
movl   $0x1,-0x4(%rbp)
jmp    1159 <valid_block_length+0x59>
cmpl   $0xc0,-0x8(%rbp)
jne    1139 <valid_block_length+0x39>
movl   $0x1,-0x4(%rbp)
jmp    1159 <valid_block_length+0x59>
cmpl   $0x100,-0x8(%rbp)
jne    1152 <valid_block_length+0x52>
movl   $0x1,-0x4(%rbp)
jmp    1159 <valid_block_length+0x59>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<valid_block_length>:
mov    $0x1,%eax
cmp    $0x80,%edi
je     111f <valid_block_length+0x1f>
cmp    $0xc0,%edi
je     111f <valid_block_length+0x1f>
cmp    $0x100,%edi
je     111f <valid_block_length+0x1f>
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @valid_block_length(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp eq i32 %4, 128
br i1 %5, label %6, label %7
6: ; preds = %1
store i32 1, i32* %2
br label %16
7: ; preds = %1
%8 = load i32, i32* %3
%9 = icmp eq i32 %8, 192
br i1 %9, label %10, label %11
10: ; preds = %7
store i32 1, i32* %2
br label %16
11: ; preds = %7
%12 = load i32, i32* %3
%13 = icmp eq i32 %12, 256
br i1 %13, label %14, label %15
14: ; preds = %11
store i32 1, i32* %2
br label %16
15: ; preds = %11
store i32 0, i32* %2
br label %16
16: ; preds = %15, %14, %10, %6
%17 = load i32, i32* %2
ret i32 %17
}

LLVM IR (-O2):
define i32 @valid_block_length(i32 %0) {
switch i32 %0, label %2 [
i32 128, label %3
i32 192, label %3
i32 256, label %3
]
2: ; preds = %1
br label %3
3: ; preds = %1, %1, %1, %2
%4 = phi i32 [ 0, %2 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ]
ret i32 %4
}
/* Variables and functions */
int U_WMRCORENONE_get(char *);
int U_WMRBF_get(void) { return U_WMRCORENONE_get("U_WMRBF"); }


x86 assembly (clang, -O0):
<U_WMRBF_get>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <U_WMRCORENONE_get@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<U_WMRBF_get>:
lea    0xee9(%rip),%rdi
jmp    1030 <U_WMRCORENONE_get@plt>

LLVM IR (-O0):
@.str = [8 x i8] c"U_WMRBF\00"
define i32 @U_WMRBF_get() {
%1 = call i32 @U_WMRCORENONE_get(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0))
ret i32 %1
}

LLVM IR (-O2):
@.str = [8 x i8] c"U_WMRBF\00"
define i32 @U_WMRBF_get() {
%1 = tail call i32 @U_WMRCORENONE_get(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0))
ret i32 %1
}
void foo319() {}


x86 assembly (clang, -O0):
<foo319>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<foo319>:
ret

LLVM IR (-O0):
define void @foo319() {
ret void
}

LLVM IR (-O2):
define void @foo319() {
ret void
}
void gtk_window_set_default() {}


x86 assembly (clang, -O0):
<gtk_window_set_default>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gtk_window_set_default>:
ret

LLVM IR (-O0):
define void @gtk_window_set_default() {
ret void
}

LLVM IR (-O2):
define void @gtk_window_set_default() {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ int16_t;

/* Variables and functions */
int /*<<< orphan*/ od_filter_dering_direction_c(int /*<<< orphan*/ *, int,
                                                int /*<<< orphan*/ const *, int,
                                                int, int);
void od_filter_dering_direction_8x8_c(int16_t *y, int ystride,
                                      const int16_t *in, int threshold,
                                      int dir) {
  od_filter_dering_direction_c(y, ystride, in, 3, threshold, dir);
}


x86 assembly (clang, -O0):
<od_filter_dering_direction_8x8_c>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %ecx,-0x1c(%rbp)
mov    %r8d,-0x20(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0xc(%rbp),%esi
mov    -0x18(%rbp),%rdx
mov    -0x1c(%rbp),%r8d
mov    -0x20(%rbp),%r9d
mov    $0x3,%ecx
call   1030 <od_filter_dering_direction_c@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<od_filter_dering_direction_8x8_c>:
mov    %r8d,%r9d
mov    %ecx,%r8d
mov    $0x3,%ecx
jmp    1030 <od_filter_dering_direction_c@plt>

LLVM IR (-O0):
define void @od_filter_dering_direction_8x8_c(i32* %0, i32 %1, i32* %2, i32 %3, i32 %4) {
%6 = alloca i32*
%7 = alloca i32
%8 = alloca i32*
%9 = alloca i32
%10 = alloca i32
store i32* %0, i32** %6
store i32 %1, i32* %7
store i32* %2, i32** %8
store i32 %3, i32* %9
store i32 %4, i32* %10
%11 = load i32*, i32** %6
%12 = load i32, i32* %7
%13 = load i32*, i32** %8
%14 = load i32, i32* %9
%15 = load i32, i32* %10
%16 = call i32 @od_filter_dering_direction_c(i32* %11, i32 %12, i32* %13, i32 3, i32 %14, i32 %15)
ret void
}

LLVM IR (-O2):
define void @od_filter_dering_direction_8x8_c(i32* %0, i32 %1, i32* %2, i32 %3, i32 %4) {
%6 = tail call i32 @od_filter_dering_direction_c(i32* %0, i32 %1, i32* %2, i32 3, i32 %3, i32 %4)
ret void
}
/* Type definitions */
struct sockaddr_in6 {
  int dummy;
};
struct sockaddr_in {
  int dummy;
};
typedef int socklen_t;

/* Variables and functions */
int const AF_INET;
socklen_t __attribute__((const)) sa_len(const int af) {
  return af == AF_INET ? sizeof(struct sockaddr_in)
                       : sizeof(struct sockaddr_in6);
}


x86 assembly (clang, -O0):
<sa_len>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%ecx
mov    0x2ed7(%rip),%rax
mov    (%rax),%edx
mov    $0x4,%eax
cmp    %edx,%ecx
cmove  %rax,%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<sa_len>:
mov    $0x4,%eax
ret

LLVM IR (-O0):
@AF_INET = constant i32 0
define i32 @sa_len(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = load i32, i32* @AF_INET
%5 = icmp eq i32 %3, %4
%6 = zext i1 %5 to i64
%7 = select i1 %5, i64 4, i64 4
%8 = trunc i64 %7 to i32
ret i32 %8
}

LLVM IR (-O2):
@AF_INET = constant i32 0
define i32 @sa_len(i32 %0) {
ret i32 4
}
/* Variables and functions */
int /*<<< orphan*/ get_grid_great_circle_area_ug(int const *, double const *,
                                                 double const *, double *);
void get_grid_great_circle_area_ug_(const int *npts, const double *lon,
                                    const double *lat, double *area) {
  get_grid_great_circle_area_ug(npts, lon, lat, area);
}


x86 assembly (clang, -O0):
<get_grid_great_circle_area_ug_>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
mov    -0x18(%rbp),%rdx
mov    -0x20(%rbp),%rcx
call   1030 <get_grid_great_circle_area_ug@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<get_grid_great_circle_area_ug_>:
jmp    1030 <get_grid_great_circle_area_ug@plt>

LLVM IR (-O0):
define void @get_grid_great_circle_area_ug_(i32* %0, double* %1, double* %2, double* %3) {
%5 = alloca i32*
%6 = alloca double*
%7 = alloca double*
%8 = alloca double*
store i32* %0, i32** %5
store double* %1, double** %6
store double* %2, double** %7
store double* %3, double** %8
%9 = load i32*, i32** %5
%10 = load double*, double** %6
%11 = load double*, double** %7
%12 = load double*, double** %8
%13 = call i32 @get_grid_great_circle_area_ug(i32* %9, double* %10, double* %11, double* %12)
ret void
}

LLVM IR (-O2):
define void @get_grid_great_circle_area_ug_(i32* %0, double* %1, double* %2, double* %3) {
%5 = tail call i32 @get_grid_great_circle_area_ug(i32* %0, double* %1, double* %2, double* %3)
ret void
}
void pops(s) char *s;
{
  void pushc(), trash();
  trash();
  for (; myisalnum(*s = popc()); ++s)
    ;
  pushc(*s);
  *s = '\0';
  return;
}


x86 assembly (clang, -O0):
<pops>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    $0x0,%al
call   1030 <trash@plt>
mov    $0x0,%al
call   1050 <popc@plt>
mov    -0x8(%rbp),%rcx
mov    %al,(%rcx)
movsbl %al,%edi
mov    $0x0,%al
call   1060 <myisalnum@plt>
cmp    $0x0,%eax
je     1189 <pops+0x49>
jmp    1178 <pops+0x38>
mov    -0x8(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    1153 <pops+0x13>
mov    -0x8(%rbp),%rax
movsbl (%rax),%edi
mov    $0x0,%al
call   1040 <pushc@plt>
mov    -0x8(%rbp),%rax
movb   $0x0,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<pops>:
push   %rbx
mov    %rdi,%rbx
xor    %eax,%eax
call   1030 <trash@plt>
nopl   0x0(%rax,%rax,1)
xor    %eax,%eax
call   1050 <popc@plt>
mov    %al,(%rbx)
movsbl %al,%edi
xor    %eax,%eax
call   1060 <myisalnum@plt>
add    $0x1,%rbx
test   %eax,%eax
jne    1150 <pops+0x10>
movsbl -0x1(%rbx),%edi
xor    %eax,%eax
call   1040 <pushc@plt>
movb   $0x0,-0x1(%rbx)
pop    %rbx
ret

LLVM IR (-O0):
define void @pops(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
br label %3
3: ; preds = %11, %1
%4 = call i32 (...) @popc()
%5 = trunc i32 %4 to i8
%6 = load i8*, i8** %2
store i8 %5, i8* %6
%7 = sext i8 %5 to i32
%8 = call i32 (i32, ...) bitcast (i32 (...)* @myisalnum to i32 (i32, ...)*)(i32 %7)
%9 = icmp ne i32 %8, 0
br i1 %9, label %10, label %14
10: ; preds = %3
br label %11
11: ; preds = %10
%12 = load i8*, i8** %2
%13 = getelementptr inbounds i8, i8* %12, i32 1
store i8* %13, i8** %2
br label %3
14: ; preds = %3
%15 = load i8*, i8** %2
%16 = load i8, i8* %15
%17 = sext i8 %16 to i32
%18 = load i8*, i8** %2
store i8 0, i8* %18
ret void
}

LLVM IR (-O2):
define void @pops(i8* nocapture %0) {
tail call void (...) @trash()
br label %2
2: ; preds = %2, %1
%3 = phi i8* [ %0, %1 ], [ %10, %2 ]
%4 = tail call i32 (...) @popc()
%5 = trunc i32 %4 to i8
store i8 %5, i8* %3
%6 = shl i32 %4, 24
%7 = ashr exact i32 %6, 24
%8 = tail call i32 (i32, ...) bitcast (i32 (...)* @myisalnum to i32 (i32, ...)*)(i32 %7)
%9 = icmp eq i32 %8, 0
%10 = getelementptr inbounds i8, i8* %3, i64 1
br i1 %9, label %11, label %2
11: ; preds = %2
%12 = load i8, i8* %3
%13 = sext i8 %12 to i32
tail call void (i32, ...) bitcast (void (...)* @pushc to void (i32, ...)*)(i32 %13)
store i8 0, i8* %3
ret void
}
int isalpha(int a) {
  return ((64 < a && a < 91) || (96 < a && a < 123)) ? 1 : 0;
}


x86 assembly (clang, -O0):
<isalpha>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    $0x40,%eax
cmp    -0x4(%rbp),%eax
jge    1124 <isalpha+0x24>
mov    $0x1,%al
cmpl   $0x5b,-0x4(%rbp)
mov    %al,-0x5(%rbp)
jl     1147 <isalpha+0x47>
xor    %eax,%eax
mov    $0x60,%ecx
cmp    -0x4(%rbp),%ecx
mov    %al,-0x6(%rbp)
jge    1141 <isalpha+0x41>
cmpl   $0x7b,-0x4(%rbp)
setl   %al
mov    %al,-0x6(%rbp)
mov    -0x6(%rbp),%al
mov    %al,-0x5(%rbp)
mov    -0x5(%rbp),%dl
xor    %eax,%eax
mov    $0x1,%ecx
test   $0x1,%dl
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<isalpha>:
and    $0xffffffdf,%edi
add    $0xffffffbf,%edi
xor    %eax,%eax
cmp    $0x1a,%edi
setb   %al
ret

LLVM IR (-O0):
define i32 @isalpha(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp slt i32 64, %3
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load i32, i32* %2
%7 = icmp slt i32 %6, 91
br i1 %7, label %16, label %8
8: ; preds = %5, %1
%9 = load i32, i32* %2
%10 = icmp slt i32 96, %9
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load i32, i32* %2
%13 = icmp slt i32 %12, 123
br label %14
14: ; preds = %11, %8
%15 = phi i1 [ false, %8 ], [ %13, %11 ]
br label %16
16: ; preds = %14, %5
%17 = phi i1 [ true, %5 ], [ %15, %14 ]
%18 = zext i1 %17 to i64
%19 = select i1 %17, i32 1, i32 0
ret i32 %19
}

LLVM IR (-O2):
define i32 @isalpha(i32 %0) {
%2 = and i32 %0, -33
%3 = add i32 %2, -65
%4 = icmp ult i32 %3, 26
%5 = zext i1 %4 to i32
ret i32 %5
}
/* Type definitions */
typedef int /*<<< orphan*/ uint8_t;
typedef int /*<<< orphan*/ uint32_t;

/* Variables and functions */
uint8_t implicitUnsignedTruncation(uint32_t argc) { return argc; }


x86 assembly (clang, -O0):
<implicitUnsignedTruncation>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<implicitUnsignedTruncation>:
mov    %edi,%eax
ret

LLVM IR (-O0):
define i32 @implicitUnsignedTruncation(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
ret i32 %3
}

LLVM IR (-O2):
define i32 @implicitUnsignedTruncation(i32 returned %0) {
ret i32 %0
}
int test_imm_F3uint16_mem(unsigned short *val) {
  return ((*val) & (-0xF3 << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_F3uint16_mem>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
movzwl (%rax),%edx
and    $0xffffff0d,%edx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%edx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_F3uint16_mem>:
movzwl (%rdi),%eax
test   $0xff0d,%eax
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_F3uint16_mem(i16* %0) {
%2 = alloca i16*
store i16* %0, i16** %2
%3 = load i16*, i16** %2
%4 = load i16, i16* %3
%5 = zext i16 %4 to i32
%6 = and i32 %5, -243
%7 = icmp ne i32 %6, 0
%8 = zext i1 %7 to i64
%9 = select i1 %7, i32 -20, i32 -40
ret i32 %9
}

LLVM IR (-O2):
define i32 @test_imm_F3uint16_mem(i16* nocapture %0) {
%2 = load i16, i16* %0
%3 = and i16 %2, -243
%4 = icmp eq i16 %3, 0
%5 = select i1 %4, i32 -40, i32 -20
ret i32 %5
}
extern int strlen(const char *s) {
  register int __res __asm__("cx");
  __asm__("cld\n\t"
          "repne\n\t"
          "scasb\n\t"
          "notl %0\n\t"
          "decl %0"
          : "=c"(__res)
          : "D"(s), "a"(0), "0"(0xffffffff));
  return __res;
}


x86 assembly (clang, -O0):
<strlen>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
xor    %eax,%eax
mov    $0xffffffff,%ecx
cld
repnz scas %es:(%rdi),%al
not    %ecx
dec    %ecx
mov    %ecx,-0xc(%rbp)
mov    -0xc(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<strlen>:
xor    %eax,%eax
mov    $0xffffffff,%ecx
cld
repnz scas %es:(%rdi),%al
not    %ecx
dec    %ecx
mov    %ecx,%eax
ret

LLVM IR (-O0):
define i32 @strlen(i8* %0) {
%2 = alloca i8*
%3 = alloca i32
store i8* %0, i8** %2
%4 = load i8*, i8** %2
%5 = call i32 asm "cld\0A\09repne\0A\09scasb\0A\09notl $0\0A\09decl $0", "={cx},{di},{ax},0,~{dirflag},~{fpsr},~{flags}"(i8* %4, i32 0, i32 -1)
store i32 %5, i32* %3
%6 = load i32, i32* %3
ret i32 %6
}

LLVM IR (-O2):
define i32 @strlen(i8* readnone %0) {
%2 = tail call i32 asm "cld\0A\09repne\0A\09scasb\0A\09notl $0\0A\09decl $0", "={cx},{di},{ax},0,~{dirflag},~{fpsr},~{flags}"(i8* %0, i32 0, i32 -1)
ret i32 %2
}
/* Variables and functions */
int sprintf(char *, char *);
int detstatsprint(char *buf) {
  return sprintf(buf, "Det stats are disabled (define DETSTATS in det.c)\n");
}


x86 assembly (clang, -O0):
<detstatsprint>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
lea    0xed9(%rip),%rsi
call   1030 <sprintf@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<detstatsprint>:
movups 0xf19(%rip),%xmm0
movups %xmm0,0x20(%rdi)
movups 0xefe(%rip),%xmm0
movups %xmm0,0x10(%rdi)
movups 0xee3(%rip),%xmm0
movups %xmm0,(%rdi)
movl   $0xa2963,0x2f(%rdi)
mov    $0x32,%eax
ret

LLVM IR (-O0):
@.str = [51 x i8] c"Det stats are disabled (define DETSTATS in det.c)\0A\00"
define i32 @detstatsprint(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = call i32 @sprintf(i8* %3, i8* getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0))
ret i32 %4
}

LLVM IR (-O2):
@.str = [51 x i8] c"Det stats are disabled (define DETSTATS in det.c)\0A\00"
define i32 @detstatsprint(i8* nocapture writeonly %0) {
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 dereferenceable(51) %0, i8* align 1 dereferenceable(51) getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0), i64 51, i1 false)
ret i32 50
}
/* Variables and functions */
char toupper(char);
char *strupr(char *s1) {
  do
    *s1 = toupper(*s1);
  while (*s1++ != '\0');
  return s1;
}


x86 assembly (clang, -O0):
<strupr>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
movsbl (%rax),%edi
call   1030 <toupper@plt>
mov    %al,%cl
mov    -0x8(%rbp),%rax
mov    %cl,(%rax)
mov    -0x8(%rbp),%rax
mov    %rax,%rcx
add    $0x1,%rcx
mov    %rcx,-0x8(%rbp)
movsbl (%rax),%eax
cmp    $0x0,%eax
jne    111c <strupr+0xc>
mov    -0x8(%rbp),%rax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<strupr>:
push   %rbx
mov    %rdi,%rbx
cs nopw 0x0(%rax,%rax,1)
xchg   %ax,%ax
movsbl (%rbx),%edi
call   1030 <toupper@plt>
mov    %al,(%rbx)
add    $0x1,%rbx
test   %al,%al
jne    1120 <strupr+0x10>
mov    %rbx,%rax
pop    %rbx
ret

LLVM IR (-O0):
define i8* @strupr(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
br label %3
3: ; preds = %8, %1
%4 = load i8*, i8** %2
%5 = load i8, i8* %4
%6 = call signext i8 @toupper(i8 signext %5)
%7 = load i8*, i8** %2
store i8 %6, i8* %7
br label %8
8: ; preds = %3
%9 = load i8*, i8** %2
%10 = getelementptr inbounds i8, i8* %9, i32 1
store i8* %10, i8** %2
%11 = load i8, i8* %9
%12 = sext i8 %11 to i32
%13 = icmp ne i32 %12, 0
br i1 %13, label %3, label %14
14: ; preds = %8
%15 = load i8*, i8** %2
ret i8* %15
}

LLVM IR (-O2):
define i8* @strupr(i8* %0) {
br label %2
2: ; preds = %2, %1
%3 = phi i8* [ %0, %1 ], [ %6, %2 ]
%4 = load i8, i8* %3
%5 = tail call signext i8 @toupper(i8 signext %4)
store i8 %5, i8* %3
%6 = getelementptr inbounds i8, i8* %3, i64 1
%7 = icmp eq i8 %5, 0
br i1 %7, label %8, label %2
8: ; preds = %2
ret i8* %6
}
void to_lower(char *str) {
  while (*str != '\0') {
    if (*str >= 'A' && *str <= 'Z') {
      *str += 32;
    }
    ++str;
  }
}


x86 assembly (clang, -O0):
<to_lower>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
movsbl (%rax),%eax
cmp    $0x0,%eax
je     1155 <to_lower+0x55>
mov    -0x8(%rbp),%rax
movsbl (%rax),%eax
cmp    $0x41,%eax
jl     1144 <to_lower+0x44>
mov    -0x8(%rbp),%rax
movsbl (%rax),%eax
cmp    $0x5a,%eax
jg     1144 <to_lower+0x44>
mov    -0x8(%rbp),%rax
movsbl (%rax),%ecx
add    $0x20,%ecx
mov    %cl,(%rax)
mov    -0x8(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    1108 <to_lower+0x8>
pop    %rbp
ret

x86 assembly (clang, -O2):
<to_lower>:
mov    (%rdi),%al
test   %al,%al
je     112a <to_lower+0x2a>
add    $0x1,%rdi
jmp    111b <to_lower+0x1b>
nopl   0x0(%rax)
movzbl (%rdi),%eax
add    $0x1,%rdi
test   %al,%al
je     112a <to_lower+0x2a>
lea    -0x41(%rax),%ecx
cmp    $0x19,%cl
ja     1110 <to_lower+0x10>
add    $0x20,%al
mov    %al,-0x1(%rdi)
jmp    1110 <to_lower+0x10>
ret

LLVM IR (-O0):
define void @to_lower(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
br label %3
3: ; preds = %24, %1
%4 = load i8*, i8** %2
%5 = load i8, i8* %4
%6 = sext i8 %5 to i32
%7 = icmp ne i32 %6, 0
br i1 %7, label %8, label %27
8: ; preds = %3
%9 = load i8*, i8** %2
%10 = load i8, i8* %9
%11 = sext i8 %10 to i32
%12 = icmp sge i32 %11, 65
br i1 %12, label %13, label %24
13: ; preds = %8
%14 = load i8*, i8** %2
%15 = load i8, i8* %14
%16 = sext i8 %15 to i32
%17 = icmp sle i32 %16, 90
br i1 %17, label %18, label %24
18: ; preds = %13
%19 = load i8*, i8** %2
%20 = load i8, i8* %19
%21 = sext i8 %20 to i32
%22 = add nsw i32 %21, 32
%23 = trunc i32 %22 to i8
store i8 %23, i8* %19
br label %24
24: ; preds = %18, %13, %8
%25 = load i8*, i8** %2
%26 = getelementptr inbounds i8, i8* %25, i32 1
store i8* %26, i8** %2
br label %3
27: ; preds = %3
ret void
}

LLVM IR (-O2):
define void @to_lower(i8* nocapture %0) {
%2 = load i8, i8* %0
%3 = icmp eq i8 %2, 0
br i1 %3, label %15, label %4
4: ; preds = %1, %11
%5 = phi i8 [ %13, %11 ], [ %2, %1 ]
%6 = phi i8* [ %12, %11 ], [ %0, %1 ]
%7 = add i8 %5, -65
%8 = icmp ult i8 %7, 26
br i1 %8, label %9, label %11
9: ; preds = %4
%10 = add nuw nsw i8 %5, 32
store i8 %10, i8* %6
br label %11
11: ; preds = %9, %4
%12 = getelementptr inbounds i8, i8* %6, i64 1
%13 = load i8, i8* %12
%14 = icmp eq i8 %13, 0
br i1 %14, label %15, label %4
15: ; preds = %11, %1
ret void
}
/* Variables and functions */
double sin(double);
double calc_fx(double x) {
  double fx;
  fx = -0.2 * sin(x) + x - 0.5;
  return fx;
}


x86 assembly (clang, -O0):
<calc_fx>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movsd  %xmm0,-0x8(%rbp)
movsd  -0x8(%rbp),%xmm0
call   1030 <sin@plt>
movsd  -0x8(%rbp),%xmm1
movsd  0xed4(%rip),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  0xebc(%rip),%xmm1
subsd  %xmm1,%xmm0
movsd  %xmm0,-0x10(%rbp)
movsd  -0x10(%rbp),%xmm0
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<calc_fx>:
push   %rax
movsd  %xmm0,(%rsp)
call   1030 <sin@plt>
mulsd  0xedd(%rip),%xmm0
addsd  (%rsp),%xmm0
addsd  0xed8(%rip),%xmm0
pop    %rax
ret

LLVM IR (-O0):
define double @calc_fx(double %0) {
%2 = alloca double
%3 = alloca double
store double %0, double* %2
%4 = load double, double* %2
%5 = call double @sin(double %4)
%6 = load double, double* %2
%7 = call double @llvm.fmuladd.f64(double -2.000000e-01, double %5, double %6)
%8 = fsub double %7, 5.000000e-01
store double %8, double* %3
%9 = load double, double* %3
ret double %9
}

LLVM IR (-O2):
define double @calc_fx(double %0) {
%2 = tail call double @sin(double %0)
%3 = tail call double @llvm.fmuladd.f64(double %2, double -2.000000e-01, double %0)
%4 = fadd double %3, -5.000000e-01
ret double %4
}
/* Variables and functions */
int /*<<< orphan*/ IntEnable(unsigned long);
int /*<<< orphan*/ IntRegister(unsigned long, void (*)());
void uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) {
  ;
  ;
  IntRegister(ulIntChannel, pfnHandler);
  IntEnable(ulIntChannel);
}


x86 assembly (clang, -O0):
<uDMAIntRegister>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
call   1040 <IntRegister@plt>
mov    -0x8(%rbp),%rdi
call   1030 <IntEnable@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<uDMAIntRegister>:
push   %rbx
mov    %rdi,%rbx
call   1040 <IntRegister@plt>
mov    %rbx,%rdi
pop    %rbx
jmp    1030 <IntEnable@plt>

LLVM IR (-O0):
define void @uDMAIntRegister(i64 %0, void ()* %1) {
%3 = alloca i64
%4 = alloca void ()*
store i64 %0, i64* %3
store void ()* %1, void ()** %4
%5 = load i64, i64* %3
%6 = load void ()*, void ()** %4
%7 = bitcast void ()* %6 to void (...)*
%8 = call i32 @IntRegister(i64 %5, void (...)* %7)
%9 = load i64, i64* %3
%10 = call i32 @IntEnable(i64 %9)
ret void
}

LLVM IR (-O2):
define void @uDMAIntRegister(i64 %0, void ()* %1) {
%3 = bitcast void ()* %1 to void (...)*
%4 = tail call i32 @IntRegister(i64 %0, void (...)* %3)
%5 = tail call i32 @IntEnable(i64 %0)
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ uint32_t;

/* Variables and functions */
int /*<<< orphan*/ librpip_gpio_pin_clear(int /*<<< orphan*/);
scalar_t__ librpip_gpio_pin_get(int /*<<< orphan*/);
int /*<<< orphan*/ librpip_gpio_pin_set(int /*<<< orphan*/);
void librpip_gpio_pin_switch(uint32_t pin) {
  if (librpip_gpio_pin_get(pin)) {
    librpip_gpio_pin_clear(pin);
  } else {
    librpip_gpio_pin_set(pin);
  }
}


x86 assembly (clang, -O0):
<librpip_gpio_pin_switch>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
call   1040 <librpip_gpio_pin_get@plt>
cmp    $0x0,%rax
je     115a <librpip_gpio_pin_switch+0x2a>
mov    -0x4(%rbp),%edi
call   1030 <librpip_gpio_pin_clear@plt>
jmp    1162 <librpip_gpio_pin_switch+0x32>
mov    -0x4(%rbp),%edi
call   1050 <librpip_gpio_pin_set@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<librpip_gpio_pin_switch>:
push   %rbx
mov    %edi,%ebx
call   1040 <librpip_gpio_pin_get@plt>
mov    %ebx,%edi
test   %rax,%rax
je     1145 <librpip_gpio_pin_switch+0x15>
pop    %rbx
jmp    1030 <librpip_gpio_pin_clear@plt>
pop    %rbx
jmp    1050 <librpip_gpio_pin_set@plt>

LLVM IR (-O0):
define void @librpip_gpio_pin_switch(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i64 @librpip_gpio_pin_get(i32 %3)
%5 = icmp ne i64 %4, 0
br i1 %5, label %6, label %9
6: ; preds = %1
%7 = load i32, i32* %2
%8 = call i32 @librpip_gpio_pin_clear(i32 %7)
br label %12
9: ; preds = %1
%10 = load i32, i32* %2
%11 = call i32 @librpip_gpio_pin_set(i32 %10)
br label %12
12: ; preds = %9, %6
ret void
}

LLVM IR (-O2):
define void @librpip_gpio_pin_switch(i32 %0) {
%2 = tail call i64 @librpip_gpio_pin_get(i32 %0)
%3 = icmp eq i64 %2, 0
br i1 %3, label %6, label %4
4: ; preds = %1
%5 = tail call i32 @librpip_gpio_pin_clear(i32 %0)
br label %8
6: ; preds = %1
%7 = tail call i32 @librpip_gpio_pin_set(i32 %0)
br label %8
8: ; preds = %6, %4
ret void
}
int test3u(unsigned int x) { return x / 10U != 2; }


x86 assembly (clang, -O0):
<test3u>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    $0xa,%ecx
xor    %edx,%edx
div    %ecx
cmp    $0x2,%eax
setne  %al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test3u>:
add    $0xffffffe2,%edi
xor    %eax,%eax
cmp    $0xfffffff6,%edi
setb   %al
ret

LLVM IR (-O0):
define i32 @test3u(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = udiv i32 %3, 10
%5 = icmp ne i32 %4, 2
%6 = zext i1 %5 to i32
ret i32 %6
}

LLVM IR (-O2):
define i32 @test3u(i32 %0) {
%2 = add i32 %0, -30
%3 = icmp ult i32 %2, -10
%4 = zext i1 %3 to i32
ret i32 %4
}
void RTStrAPrintf2VTag(void) {}


x86 assembly (clang, -O0):
<RTStrAPrintf2VTag>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<RTStrAPrintf2VTag>:
ret

LLVM IR (-O0):
define void @RTStrAPrintf2VTag() {
ret void
}

LLVM IR (-O2):
define void @RTStrAPrintf2VTag() {
ret void
}
int test_imm_09uint8_reg(unsigned char val) {
  return ((val) & (0x09 << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_09uint8_reg>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x1(%rbp)
movzbl -0x1(%rbp),%edx
and    $0x9,%edx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%edx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_09uint8_reg>:
test   $0x9,%dil
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_09uint8_reg(i8 zeroext %0) {
%2 = alloca i8
store i8 %0, i8* %2
%3 = load i8, i8* %2
%4 = zext i8 %3 to i32
%5 = and i32 %4, 9
%6 = icmp ne i32 %5, 0
%7 = zext i1 %6 to i64
%8 = select i1 %6, i32 -20, i32 -40
ret i32 %8
}

LLVM IR (-O2):
define i32 @test_imm_09uint8_reg(i8 zeroext %0) {
%2 = and i8 %0, 9
%3 = icmp eq i8 %2, 0
%4 = select i1 %3, i32 -40, i32 -20
ret i32 %4
}
void ff_hevc_put_hevc_epel_hv4_8_sse4() {}


x86 assembly (clang, -O0):
<ff_hevc_put_hevc_epel_hv4_8_sse4>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ff_hevc_put_hevc_epel_hv4_8_sse4>:
ret

LLVM IR (-O0):
define void @ff_hevc_put_hevc_epel_hv4_8_sse4() {
ret void
}

LLVM IR (-O2):
define void @ff_hevc_put_hevc_epel_hv4_8_sse4() {
ret void
}
void Init_Extensions(void) {}


x86 assembly (clang, -O0):
<Init_Extensions>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<Init_Extensions>:
ret

LLVM IR (-O0):
define void @Init_Extensions() {
ret void
}

LLVM IR (-O2):
define void @Init_Extensions() {
ret void
}
/* Variables and functions */
int /*<<< orphan*/ puts(char *);
int do_test(void) {
  puts("_POSIX_CLOCK_SELECTION not supported, test skipped");
  return 0;
}


x86 assembly (clang, -O0):
<do_test>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <puts@plt>
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<do_test>:
push   %rax
lea    0xee8(%rip),%rdi
call   1030 <puts@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [51 x i8] c"_POSIX_CLOCK_SELECTION not supported, test skipped\00"
define i32 @do_test() {
%1 = call i32 @puts(i8* getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0))
ret i32 0
}

LLVM IR (-O2):
@.str = [51 x i8] c"_POSIX_CLOCK_SELECTION not supported, test skipped\00"
define i32 @do_test() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0))
ret i32 0
}
void lidt(void *p) { asm volatile("lidt (%0)" : : "r"(p)); }


x86 assembly (clang, -O0):
<lidt>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
lidt   (%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<lidt>:
lidt   (%rdi)
ret

LLVM IR (-O0):
define void @lidt(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
ret void
}

LLVM IR (-O2):
define void @lidt(i8* %0) {
tail call void asm sideeffect "lidt ($0)", "r,~{dirflag},~{fpsr},~{flags}"(i8* %0)
ret void
}
/* Variables and functions */
float mycalc(float, float);
int /*<<< orphan*/ printf(char *, float, float, float);
int /*<<< orphan*/ scanf(char *, float *, float *);
main() {
  float x, y, z;
  scanf("%f %f", &x, &y);
  z = mycalc(x, y);
  printf("result of %f - %f = %.2f\n", x, y, z);
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
lea    0xec1(%rip),%rdi
lea    -0x4(%rbp),%rsi
lea    -0x8(%rbp),%rdx
call   1050 <scanf@plt>
movss  -0x4(%rbp),%xmm0
movss  -0x8(%rbp),%xmm1
call   1040 <mycalc@plt>
movss  %xmm0,-0xc(%rbp)
movss  -0x4(%rbp),%xmm0
movss  -0x8(%rbp),%xmm1
movss  -0xc(%rbp),%xmm2
lea    0xe90(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rax
lea    0xec8(%rip),%rdi
lea    0x4(%rsp),%rsi
mov    %rsp,%rdx
call   1050 <scanf@plt>
movss  0x4(%rsp),%xmm0
movss  (%rsp),%xmm1
call   1040 <mycalc@plt>
movaps %xmm0,%xmm2
movss  0x4(%rsp),%xmm0
movss  (%rsp),%xmm1
lea    0xe9c(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [6 x i8] c"%f %f\00"
@.str.1 = [26 x i8] c"result of %f - %f = %.2f\0A\00"
define i32 @main() {
%1 = alloca float
%2 = alloca float
%3 = alloca float
%4 = call i32 @scanf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), float* %1, float* %2)
%5 = load float, float* %1
%6 = load float, float* %2
%7 = call float @mycalc(float %5, float %6)
store float %7, float* %3
%8 = load float, float* %1
%9 = load float, float* %2
%10 = load float, float* %3
%11 = call i32 @printf(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str.1, i64 0, i64 0), float %8, float %9, float %10)
ret i32 0
}

LLVM IR (-O2):
@.str = [6 x i8] c"%f %f\00"
@.str.1 = [26 x i8] c"result of %f - %f = %.2f\0A\00"
define i32 @main() {
%1 = alloca float
%2 = alloca float
%3 = bitcast float* %1 to i8*
%4 = bitcast float* %2 to i8*
%5 = call i32 @scanf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), float* %1, float* %2)
%6 = load float, float* %1
%7 = load float, float* %2
%8 = call float @mycalc(float %6, float %7)
%9 = load float, float* %1
%10 = load float, float* %2
%11 = call i32 @printf(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str.1, i64 0, i64 0), float %9, float %10, float %8)
ret i32 0
}
int bitReverse(int x) {
  unsigned x1 = (unsigned)x;
  x1 = (((x1 & 0xaaaaaaaa) >> 1) | ((x1 & 0x55555555) << 1));
  x1 = (((x1 & 0xcccccccc) >> 2) | ((x1 & 0x33333333) << 2));
  x1 = (((x1 & 0xf0f0f0f0) >> 4) | ((x1 & 0x0f0f0f0f) << 4));
  x1 = (((x1 & 0xff00ff00) >> 8) | ((x1 & 0x00ff00ff) << 8));
  return ((x1 >> 16) | (x1 << 16));
  return ((x >> 24) & 0xff) | (((x >> 16) & 0xff) << 8) |
         (((x >> 8) & 0xff) << 16) | ((x & 0xff) << 24);
}


x86 assembly (clang, -O0):
<bitReverse>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0xaaaaaaaa,%eax
shr    $0x1,%eax
mov    -0x8(%rbp),%ecx
and    $0x55555555,%ecx
shl    $0x1,%ecx
or     %ecx,%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0xcccccccc,%eax
shr    $0x2,%eax
mov    -0x8(%rbp),%ecx
and    $0x33333333,%ecx
shl    $0x2,%ecx
or     %ecx,%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0xf0f0f0f0,%eax
shr    $0x4,%eax
mov    -0x8(%rbp),%ecx
and    $0xf0f0f0f,%ecx
shl    $0x4,%ecx
or     %ecx,%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0xff00ff00,%eax
shr    $0x8,%eax
mov    -0x8(%rbp),%ecx
and    $0xff00ff,%ecx
shl    $0x8,%ecx
or     %ecx,%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
shr    $0x10,%eax
mov    -0x8(%rbp),%ecx
shl    $0x10,%ecx
or     %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<bitReverse>:
bswap  %edi
mov    %edi,%eax
and    $0xf0f0f0f,%eax
shl    $0x4,%eax
shr    $0x4,%edi
and    $0xf0f0f0f,%edi
or     %eax,%edi
mov    %edi,%eax
and    $0x33333333,%eax
shr    $0x2,%edi
and    $0x33333333,%edi
lea    (%rdi,%rax,4),%eax
mov    %eax,%ecx
and    $0x55555555,%ecx
shr    %eax
and    $0x55555555,%eax
lea    (%rax,%rcx,2),%eax
ret

LLVM IR (-O0):
define i32 @bitReverse(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %2
%4 = load i32, i32* %2
store i32 %4, i32* %3
%5 = load i32, i32* %3
%6 = and i32 %5, -1431655766
%7 = lshr i32 %6, 1
%8 = load i32, i32* %3
%9 = and i32 %8, 1431655765
%10 = shl i32 %9, 1
%11 = or i32 %7, %10
store i32 %11, i32* %3
%12 = load i32, i32* %3
%13 = and i32 %12, -858993460
%14 = lshr i32 %13, 2
%15 = load i32, i32* %3
%16 = and i32 %15, 858993459
%17 = shl i32 %16, 2
%18 = or i32 %14, %17
store i32 %18, i32* %3
%19 = load i32, i32* %3
%20 = and i32 %19, -252645136
%21 = lshr i32 %20, 4
%22 = load i32, i32* %3
%23 = and i32 %22, 252645135
%24 = shl i32 %23, 4
%25 = or i32 %21, %24
store i32 %25, i32* %3
%26 = load i32, i32* %3
%27 = and i32 %26, -16711936
%28 = lshr i32 %27, 8
%29 = load i32, i32* %3
%30 = and i32 %29, 16711935
%31 = shl i32 %30, 8
%32 = or i32 %28, %31
store i32 %32, i32* %3
%33 = load i32, i32* %3
%34 = lshr i32 %33, 16
%35 = load i32, i32* %3
%36 = shl i32 %35, 16
%37 = or i32 %34, %36
ret i32 %37
}

LLVM IR (-O2):
define i32 @bitReverse(i32 %0) {
%2 = tail call i32 @llvm.bitreverse.i32(i32 %0)
ret i32 %2
}