#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ enable_L1_D();
int /*<<< orphan*/ enable_L1_D_side_prefetch();
int /*<<< orphan*/ enable_L1_I();
int /*<<< orphan*/ enable_L2_prefetch_hint();
int /*<<< orphan*/ enable_L2_speculative_linefill();
int /*<<< orphan*/ enable_MMU();
int /*<<< orphan*/ enable_SCU();
int /*<<< orphan*/ enable_branch_prediction();
int /*<<< orphan*/ enable_caches();
int /*<<< orphan*/ enable_early_BRESP();
int /*<<< orphan*/ enable_store_buffer_device_limitation();
int /*<<< orphan*/ enable_write_full_line_zeros();
int /*<<< orphan*/ initialize_L2C();
int /*<<< orphan*/ printf(char *);
void cache_configuration(int cache_config) {
  if (cache_config <= 0) {
    printf("\n\rCACHE CONFIG:0 No cache\n\r");
  } else if (cache_config <= 1) {
    printf("\n\rCACHE CONFIG:1 Enable MMU\n\r");
    enable_MMU();
  } else if (cache_config <= 2) {
    printf("\n\rCACHE CONFIG:2 Enable MMU and init L2C\n\r");
    enable_MMU();
    initialize_L2C();
  } else if (cache_config <= 3) {
    printf("\n\rCACHE CONFIG:3 Enable MMU and SCU and init L2C\n\r");
    enable_MMU();
    initialize_L2C();
    enable_SCU();
  } else if (cache_config <= 4) {
    printf("\n\rCACHE CONFIG:4 L1_I\n\r");
    enable_MMU();
    initialize_L2C();
    enable_SCU();
    enable_L1_I();
  } else if (cache_config <= 5) {
    printf("\n\rCACHE CONFIG:5 L1_I and branch prediction\n\r");
    enable_MMU();
    initialize_L2C();
    enable_SCU();
    enable_L1_I();
    enable_branch_prediction();
  } else if (cache_config <= 6) {
    printf("\n\rCACHE CONFIG:6 L1_D, L1_I and branch prediction\n\r");
    enable_MMU();
    initialize_L2C();
    enable_SCU();
    enable_L1_D();
    enable_L1_I();
    enable_branch_prediction();
  } else if (cache_config <= 7) {
    printf("\n\rCACHE CONFIG:7 L1_D with side prefetch), L1_I with branch "
           "prediction\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_SCU();
    enable_L1_D();
    enable_L1_I();
    enable_branch_prediction();
  } else if (cache_config <= 8) {
    printf("\n\rCACHE CONFIG:8 L1_D side prefetch, L1_I with branch pre. and "
           "enable L2\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_SCU();
    enable_caches();
  } else if (cache_config <= 9) {
    printf("\n\rCACHE CONFIG:9 basic config. + L2 prefetch hint\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_L2_prefetch_hint();
    enable_SCU();
    enable_caches();
  } else if (cache_config <= 10) {
    printf("\n\rCACHE CONFIG:10 basic config. + L2ph + wr full line 0s\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_L2_prefetch_hint();
    enable_SCU();
    enable_write_full_line_zeros();
    enable_caches();
  } else if (cache_config <= 11) {
    printf("\n\rCACHE CONFIG:11 basic config. + L2ph + wrfl0s + speculative "
           "linefills\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_L2_prefetch_hint();
    enable_SCU();
    enable_L2_speculative_linefill();
    enable_write_full_line_zeros();
    enable_caches();
  } else if (cache_config <= 12) {
    printf(
        "\n\rCACHE CONFIG:12 basic config. + L2ph + wrfl0s + sl + eBRESP\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_L2_prefetch_hint();
    enable_SCU();
    enable_L2_speculative_linefill();
    enable_write_full_line_zeros();
    enable_early_BRESP();
    enable_caches();
  } else if (cache_config <= 13) {
    printf("\n\rCACHE CONFIG:13 basic config. + L2ph + wrfl0s + sl + eBRESP + "
           "buffer store limitation\n\r");
    enable_MMU();
    initialize_L2C();
    enable_L1_D_side_prefetch();
    enable_L2_prefetch_hint();
    enable_SCU();
    enable_L2_speculative_linefill();
    enable_write_full_line_zeros();
    enable_early_BRESP();
    enable_store_buffer_device_limitation();
    enable_caches();
  }
}


x86 assembly (clang, -O0):
<cache_configuration>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
cmpl   $0x0,-0x4(%rbp)
jg     1206 <cache_configuration+0x26>
lea    0xe04(%rip),%rdi
call   1050 <printf@plt>
jmp    15a0 <cache_configuration+0x3c0>
cmpl   $0x1,-0x4(%rbp)
jg     1228 <cache_configuration+0x48>
lea    0xe05(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
jmp    159b <cache_configuration+0x3bb>
cmpl   $0x2,-0x4(%rbp)
jg     1251 <cache_configuration+0x71>
lea    0xe01(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
jmp    1596 <cache_configuration+0x3b6>
cmpl   $0x3,-0x4(%rbp)
jg     1281 <cache_configuration+0xa1>
lea    0xe03(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
jmp    1591 <cache_configuration+0x3b1>
cmpl   $0x4,-0x4(%rbp)
jg     12b8 <cache_configuration+0xd8>
lea    0xe06(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   1060 <enable_L1_I@plt>
jmp    158c <cache_configuration+0x3ac>
cmpl   $0x5,-0x4(%rbp)
jg     12f6 <cache_configuration+0x116>
lea    0xde7(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   1060 <enable_L1_I@plt>
mov    $0x0,%al
call   1030 <enable_branch_prediction@plt>
jmp    1587 <cache_configuration+0x3a7>
cmpl   $0x6,-0x4(%rbp)
jg     133b <cache_configuration+0x15b>
lea    0xdd7(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   10f0 <enable_L1_D@plt>
mov    $0x0,%al
call   1060 <enable_L1_I@plt>
mov    $0x0,%al
call   1030 <enable_branch_prediction@plt>
jmp    1582 <cache_configuration+0x3a2>
cmpl   $0x7,-0x4(%rbp)
jg     1387 <cache_configuration+0x1a7>
lea    0xdc6(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   10f0 <enable_L1_D@plt>
mov    $0x0,%al
call   1060 <enable_L1_I@plt>
mov    $0x0,%al
call   1030 <enable_branch_prediction@plt>
jmp    157d <cache_configuration+0x39d>
cmpl   $0x8,-0x4(%rbp)
jg     13c5 <cache_configuration+0x1e5>
lea    0xdc3(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    1578 <cache_configuration+0x398>
cmpl   $0x9,-0x4(%rbp)
jg     140a <cache_configuration+0x22a>
lea    0xdd0(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   10b0 <enable_L2_prefetch_hint@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    1573 <cache_configuration+0x393>
cmpl   $0xa,-0x4(%rbp)
jg     1456 <cache_configuration+0x276>
lea    0xdbf(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   10b0 <enable_L2_prefetch_hint@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   1100 <enable_write_full_line_zeros@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    156e <cache_configuration+0x38e>
cmpl   $0xb,-0x4(%rbp)
jg     14a9 <cache_configuration+0x2c9>
lea    0xdae(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   10b0 <enable_L2_prefetch_hint@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   10d0 <enable_L2_speculative_linefill@plt>
mov    $0x0,%al
call   1100 <enable_write_full_line_zeros@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    1569 <cache_configuration+0x389>
cmpl   $0xc,-0x4(%rbp)
jg     1503 <cache_configuration+0x323>
lea    0xda5(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   10b0 <enable_L2_prefetch_hint@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   10d0 <enable_L2_speculative_linefill@plt>
mov    $0x0,%al
call   1100 <enable_write_full_line_zeros@plt>
mov    $0x0,%al
call   1070 <enable_early_BRESP@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    1564 <cache_configuration+0x384>
cmpl   $0xd,-0x4(%rbp)
jg     155f <cache_configuration+0x37f>
lea    0xd8b(%rip),%rdi
call   1050 <printf@plt>
mov    $0x0,%al
call   1080 <enable_MMU@plt>
mov    $0x0,%al
call   10c0 <initialize_L2C@plt>
mov    $0x0,%al
call   10a0 <enable_L1_D_side_prefetch@plt>
mov    $0x0,%al
call   10b0 <enable_L2_prefetch_hint@plt>
mov    $0x0,%al
call   1090 <enable_SCU@plt>
mov    $0x0,%al
call   10d0 <enable_L2_speculative_linefill@plt>
mov    $0x0,%al
call   1100 <enable_write_full_line_zeros@plt>
mov    $0x0,%al
call   1070 <enable_early_BRESP@plt>
mov    $0x0,%al
call   10e0 <enable_store_buffer_device_limitation@plt>
mov    $0x0,%al
call   1040 <enable_caches@plt>
jmp    1564 <cache_configuration+0x384>
jmp    1569 <cache_configuration+0x389>
jmp    156e <cache_configuration+0x38e>
jmp    1573 <cache_configuration+0x393>
jmp    1578 <cache_configuration+0x398>
jmp    157d <cache_configuration+0x39d>
jmp    1582 <cache_configuration+0x3a2>
jmp    1587 <cache_configuration+0x3a7>
jmp    158c <cache_configuration+0x3ac>
jmp    1591 <cache_configuration+0x3b1>
jmp    1596 <cache_configuration+0x3b6>
jmp    159b <cache_configuration+0x3bb>
jmp    15a0 <cache_configuration+0x3c0>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<cache_configuration>:
push   %rax
test   %edi,%edi
jle    11fe <cache_configuration+0x1e>
cmp    $0x1,%edi
jne    120b <cache_configuration+0x2b>
lea    0xe2b(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
pop    %rcx
jmp    1080 <enable_MMU@plt>
lea    0xdfb(%rip),%rdi
pop    %rax
jmp    1050 <printf@plt>
cmp    $0x2,%edi
ja     122b <cache_configuration+0x4b>
lea    0xe23(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
pop    %rcx
jmp    10c0 <initialize_L2C@plt>
cmp    $0x3,%edi
jne    1252 <cache_configuration+0x72>
lea    0xe2e(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
pop    %rcx
jmp    1090 <enable_SCU@plt>
cmp    $0x4,%edi
ja     1280 <cache_configuration+0xa0>
lea    0xe3a(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
xor    %eax,%eax
pop    %rcx
jmp    1060 <enable_L1_I@plt>
cmp    $0x5,%edi
jne    12a8 <cache_configuration+0xc8>
lea    0xe24(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
jmp    12fd <cache_configuration+0x11d>
cmp    $0x6,%edi
ja     12c9 <cache_configuration+0xe9>
lea    0xe2a(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
jmp    12ef <cache_configuration+0x10f>
cmp    $0x7,%edi
jne    130c <cache_configuration+0x12c>
lea    0xe3d(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
xor    %eax,%eax
call   10f0 <enable_L1_D@plt>
xor    %eax,%eax
call   1060 <enable_L1_I@plt>
xor    %eax,%eax
pop    %rcx
jmp    1030 <enable_branch_prediction@plt>
cmp    $0x8,%edi
ja     1334 <cache_configuration+0x154>
lea    0xe43(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
jmp    1361 <cache_configuration+0x181>
cmp    $0x9,%edi
jne    136a <cache_configuration+0x18a>
lea    0xe66(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   10b0 <enable_L2_prefetch_hint@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
jmp    13e2 <cache_configuration+0x202>
cmp    $0xa,%edi
ja     13a0 <cache_configuration+0x1c0>
lea    0xe64(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   10b0 <enable_L2_prefetch_hint@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
jmp    13db <cache_configuration+0x1fb>
cmp    $0xb,%edi
jne    13ea <cache_configuration+0x20a>
lea    0xe69(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   10b0 <enable_L2_prefetch_hint@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
xor    %eax,%eax
call   10d0 <enable_L2_speculative_linefill@plt>
xor    %eax,%eax
call   1100 <enable_write_full_line_zeros@plt>
xor    %eax,%eax
pop    %rcx
jmp    1040 <enable_caches@plt>
cmp    $0xc,%edi
ja     1435 <cache_configuration+0x255>
lea    0xe69(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   10b0 <enable_L2_prefetch_hint@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
xor    %eax,%eax
call   10d0 <enable_L2_speculative_linefill@plt>
xor    %eax,%eax
call   1100 <enable_write_full_line_zeros@plt>
xor    %eax,%eax
call   1070 <enable_early_BRESP@plt>
jmp    13e2 <cache_configuration+0x202>
cmp    $0xd,%edi
jne    148a <cache_configuration+0x2aa>
lea    0xe5e(%rip),%rdi
call   1050 <printf@plt>
xor    %eax,%eax
call   1080 <enable_MMU@plt>
xor    %eax,%eax
call   10c0 <initialize_L2C@plt>
xor    %eax,%eax
call   10a0 <enable_L1_D_side_prefetch@plt>
xor    %eax,%eax
call   10b0 <enable_L2_prefetch_hint@plt>
xor    %eax,%eax
call   1090 <enable_SCU@plt>
xor    %eax,%eax
call   10d0 <enable_L2_speculative_linefill@plt>
xor    %eax,%eax
call   1100 <enable_write_full_line_zeros@plt>
xor    %eax,%eax
call   1070 <enable_early_BRESP@plt>
xor    %eax,%eax
call   10e0 <enable_store_buffer_device_limitation@plt>
jmp    13e2 <cache_configuration+0x202>
pop    %rax
ret

LLVM IR (-O0):
@.str = [28 x i8] c"\0A\0DCACHE CONFIG:0 No cache\0A\0D\00"
@.str.1 = [30 x i8] c"\0A\0DCACHE CONFIG:1 Enable MMU\0A\0D\00"
@.str.2 = [43 x i8] c"\0A\0DCACHE CONFIG:2 Enable MMU and init L2C\0A\0D\00"
@.str.3 = [51 x i8] c"\0A\0DCACHE CONFIG:3 Enable MMU and SCU and init L2C\0A\0D\00"
@.str.4 = [24 x i8] c"\0A\0DCACHE CONFIG:4 L1_I\0A\0D\00"
@.str.5 = [46 x i8] c"\0A\0DCACHE CONFIG:5 L1_I and branch prediction\0A\0D\00"
@.str.6 = [52 x i8] c"\0A\0DCACHE CONFIG:6 L1_D, L1_I and branch prediction\0A\0D\00"
@.str.7 = [73 x i8] c"\0A\0DCACHE CONFIG:7 L1_D with side prefetch), L1_I with branch prediction\0A\0D\00"
@.str.8 = [75 x i8] c"\0A\0DCACHE CONFIG:8 L1_D side prefetch, L1_I with branch pre. and enable L2\0A\0D\00"
@.str.9 = [52 x i8] c"\0A\0DCACHE CONFIG:9 basic config. + L2 prefetch hint\0A\0D\00"
@.str.10 = [59 x i8] c"\0A\0DCACHE CONFIG:10 basic config. + L2ph + wr full line 0s\0A\0D\00"
@.str.11 = [74 x i8] c"\0A\0DCACHE CONFIG:11 basic config. + L2ph + wrfl0s + speculative linefills\0A\0D\00"
@.str.12 = [64 x i8] c"\0A\0DCACHE CONFIG:12 basic config. + L2ph + wrfl0s + sl + eBRESP\0A\0D\00"
@.str.13 = [90 x i8] c"\0A\0DCACHE CONFIG:13 basic config. + L2ph + wrfl0s + sl + eBRESP + buffer store limitation\0A\0D\00"
define void @cache_configuration(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp sle i32 %3, 0
br i1 %4, label %5, label %7
5: ; preds = %1
%6 = call i32 @printf(i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str, i64 0, i64 0))
br label %158
7: ; preds = %1
%8 = load i32, i32* %2
%9 = icmp sle i32 %8, 1
br i1 %9, label %10, label %13
10: ; preds = %7
%11 = call i32 @printf(i8* getelementptr inbounds ([30 x i8], [30 x i8]* @.str.1, i64 0, i64 0))
%12 = call i32 (...) @enable_MMU()
br label %157
13: ; preds = %7
%14 = load i32, i32* %2
%15 = icmp sle i32 %14, 2
br i1 %15, label %16, label %20
16: ; preds = %13
%17 = call i32 @printf(i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str.2, i64 0, i64 0))
%18 = call i32 (...) @enable_MMU()
%19 = call i32 (...) @initialize_L2C()
br label %156
20: ; preds = %13
%21 = load i32, i32* %2
%22 = icmp sle i32 %21, 3
br i1 %22, label %23, label %28
23: ; preds = %20
%24 = call i32 @printf(i8* getelementptr inbounds ([51 x i8], [51 x i8]* @.str.3, i64 0, i64 0))
%25 = call i32 (...) @enable_MMU()
%26 = call i32 (...) @initialize_L2C()
%27 = call i32 (...) @enable_SCU()
br label %155
28: ; preds = %20
%29 = load i32, i32* %2
%30 = icmp sle i32 %29, 4
br i1 %30, label %31, label %37
31: ; preds = %28
%32 = call i32 @printf(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str.4, i64 0, i64 0))
%33 = call i32 (...) @enable_MMU()
%34 = call i32 (...) @initialize_L2C()
%35 = call i32 (...) @enable_SCU()
%36 = call i32 (...) @enable_L1_I()
br label %154
37: ; preds = %28
%38 = load i32, i32* %2
%39 = icmp sle i32 %38, 5
br i1 %39, label %40, label %47
40: ; preds = %37
%41 = call i32 @printf(i8* getelementptr inbounds ([46 x i8], [46 x i8]* @.str.5, i64 0, i64 0))
%42 = call i32 (...) @enable_MMU()
%43 = call i32 (...) @initialize_L2C()
%44 = call i32 (...) @enable_SCU()
%45 = call i32 (...) @enable_L1_I()
%46 = call i32 (...) @enable_branch_prediction()
br label %153
47: ; preds = %37
%48 = load i32, i32* %2
%49 = icmp sle i32 %48, 6
br i1 %49, label %50, label %58
50: ; preds = %47
%51 = call i32 @printf(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @.str.6, i64 0, i64 0))
%52 = call i32 (...) @enable_MMU()
%53 = call i32 (...) @initialize_L2C()
%54 = call i32 (...) @enable_SCU()
%55 = call i32 (...) @enable_L1_D()
%56 = call i32 (...) @enable_L1_I()
%57 = call i32 (...) @enable_branch_prediction()
br label %152
58: ; preds = %47
%59 = load i32, i32* %2
%60 = icmp sle i32 %59, 7
br i1 %60, label %61, label %70
61: ; preds = %58
%62 = call i32 @printf(i8* getelementptr inbounds ([73 x i8], [73 x i8]* @.str.7, i64 0, i64 0))
%63 = call i32 (...) @enable_MMU()
%64 = call i32 (...) @initialize_L2C()
%65 = call i32 (...) @enable_L1_D_side_prefetch()
%66 = call i32 (...) @enable_SCU()
%67 = call i32 (...) @enable_L1_D()
%68 = call i32 (...) @enable_L1_I()
%69 = call i32 (...) @enable_branch_prediction()
br label %151
70: ; preds = %58
%71 = load i32, i32* %2
%72 = icmp sle i32 %71, 8
br i1 %72, label %73, label %80
73: ; preds = %70
%74 = call i32 @printf(i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str.8, i64 0, i64 0))
%75 = call i32 (...) @enable_MMU()
%76 = call i32 (...) @initialize_L2C()
%77 = call i32 (...) @enable_L1_D_side_prefetch()
%78 = call i32 (...) @enable_SCU()
%79 = call i32 (...) @enable_caches()
br label %150
80: ; preds = %70
%81 = load i32, i32* %2
%82 = icmp sle i32 %81, 9
br i1 %82, label %83, label %91
83: ; preds = %80
%84 = call i32 @printf(i8* getelementptr inbounds ([52 x i8], [52 x i8]* @.str.9, i64 0, i64 0))
%85 = call i32 (...) @enable_MMU()
%86 = call i32 (...) @initialize_L2C()
%87 = call i32 (...) @enable_L1_D_side_prefetch()
%88 = call i32 (...) @enable_L2_prefetch_hint()
%89 = call i32 (...) @enable_SCU()
%90 = call i32 (...) @enable_caches()
br label %149
91: ; preds = %80
%92 = load i32, i32* %2
%93 = icmp sle i32 %92, 10
br i1 %93, label %94, label %103
94: ; preds = %91
%95 = call i32 @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str.10, i64 0, i64 0))
%96 = call i32 (...) @enable_MMU()
%97 = call i32 (...) @initialize_L2C()
%98 = call i32 (...) @enable_L1_D_side_prefetch()
%99 = call i32 (...) @enable_L2_prefetch_hint()
%100 = call i32 (...) @enable_SCU()
%101 = call i32 (...) @enable_write_full_line_zeros()
%102 = call i32 (...) @enable_caches()
br label %148
103: ; preds = %91
%104 = load i32, i32* %2
%105 = icmp sle i32 %104, 11
br i1 %105, label %106, label %116
106: ; preds = %103
%107 = call i32 @printf(i8* getelementptr inbounds ([74 x i8], [74 x i8]* @.str.11, i64 0, i64 0))
%108 = call i32 (...) @enable_MMU()
%109 = call i32 (...) @initialize_L2C()
%110 = call i32 (...) @enable_L1_D_side_prefetch()
%111 = call i32 (...) @enable_L2_prefetch_hint()
%112 = call i32 (...) @enable_SCU()
%113 = call i32 (...) @enable_L2_speculative_linefill()
%114 = call i32 (...) @enable_write_full_line_zeros()
%115 = call i32 (...) @enable_caches()
br label %147
116: ; preds = %103
%117 = load i32, i32* %2
%118 = icmp sle i32 %117, 12
br i1 %118, label %119, label %130
119: ; preds = %116
%120 = call i32 @printf(i8* getelementptr inbounds ([64 x i8], [64 x i8]* @.str.12, i64 0, i64 0))
%121 = call i32 (...) @enable_MMU()
%122 = call i32 (...) @initialize_L2C()
%123 = call i32 (...) @enable_L1_D_side_prefetch()
%124 = call i32 (...) @enable_L2_prefetch_hint()
%125 = call i32 (...) @enable_SCU()
%126 = call i32 (...) @enable_L2_speculative_linefill()
%127 = call i32 (...) @enable_write_full_line_zeros()
%128 = call i32 (...) @enable_early_BRESP()
%129 = call i32 (...) @enable_caches()
br label %146
130: ; preds = %116
%131 = load i32, i32* %2
%132 = icmp sle i32 %131, 13
br i1 %132, label %133, label %145
133: ; preds = %130
%134 = call i32 @printf(i8* getelementptr inbounds ([90 x i8], [90 x i8]* @.str.13, i64 0, i64 0))
%135 = call i32 (...) @enable_MMU()
%136 = call i32 (...) @initialize_L2C()
%137 = call i32 (...) @enable_L1_D_side_prefetch()
%138 = call i32 (...) @enable_L2_prefetch_hint()
%139 = call i32 (...) @enable_SCU()
%140 = call i32 (...) @enable_L2_speculative_linefill()
%141 = call i32 (...) @enable_write_full_line_zeros()
%142 = call i32 (...) @enable_early_BRESP()
%143 = call i32 (...) @enable_store_buffer_device_limitation()
%144 = call i32 (...) @enable_caches()
br label %145
145: ; preds = %133, %130
br label %146
146: ; preds = %145, %119
br label %147
147: ; preds = %146, %106
br label %148
148: ; preds = %147, %94
br label %149
149: ; preds = %148, %83
br label %150
150: ; preds = %149, %73
br label %151
151: ; preds = %150, %61
br label %152
152: ; preds = %151, %50
br label %153
153: ; preds = %152, %40
br label %154
154: ; preds = %153, %31
br label %155
155: ; preds = %154, %23
br label %156
156: ; preds = %155, %16
br label %157
157: ; preds = %156, %10
br label %158
158: ; preds = %157, %5
ret void
}

LLVM IR (-O2):
@.str = [28 x i8] c"\0A\0DCACHE CONFIG:0 No cache\0A\0D\00"
@.str.1 = [30 x i8] c"\0A\0DCACHE CONFIG:1 Enable MMU\0A\0D\00"
@.str.2 = [43 x i8] c"\0A\0DCACHE CONFIG:2 Enable MMU and init L2C\0A\0D\00"
@.str.3 = [51 x i8] c"\0A\0DCACHE CONFIG:3 Enable MMU and SCU and init L2C\0A\0D\00"
@.str.4 = [24 x i8] c"\0A\0DCACHE CONFIG:4 L1_I\0A\0D\00"
@.str.5 = [46 x i8] c"\0A\0DCACHE CONFIG:5 L1_I and branch prediction\0A\0D\00"
@.str.6 = [52 x i8] c"\0A\0DCACHE CONFIG:6 L1_D, L1_I and branch prediction\0A\0D\00"
@.str.7 = [73 x i8] c"\0A\0DCACHE CONFIG:7 L1_D with side prefetch), L1_I with branch prediction\0A\0D\00"
@.str.8 = [75 x i8] c"\0A\0DCACHE CONFIG:8 L1_D side prefetch, L1_I with branch pre. and enable L2\0A\0D\00"
@.str.9 = [52 x i8] c"\0A\0DCACHE CONFIG:9 basic config. + L2 prefetch hint\0A\0D\00"
@.str.10 = [59 x i8] c"\0A\0DCACHE CONFIG:10 basic config. + L2ph + wr full line 0s\0A\0D\00"
@.str.11 = [74 x i8] c"\0A\0DCACHE CONFIG:11 basic config. + L2ph + wrfl0s + speculative linefills\0A\0D\00"
@.str.12 = [64 x i8] c"\0A\0DCACHE CONFIG:12 basic config. + L2ph + wrfl0s + sl + eBRESP\0A\0D\00"
@.str.13 = [90 x i8] c"\0A\0DCACHE CONFIG:13 basic config. + L2ph + wrfl0s + sl + eBRESP + buffer store limitation\0A\0D\00"
define void @cache_configuration(i32 %0) {
%2 = icmp slt i32 %0, 1
br i1 %2, label %3, label %5
3: ; preds = %1
%4 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([28 x i8], [28 x i8]* @.str, i64 0, i64 0))
br label %130
5: ; preds = %1
%6 = icmp eq i32 %0, 1
br i1 %6, label %7, label %10
7: ; preds = %5
%8 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([30 x i8], [30 x i8]* @.str.1, i64 0, i64 0))
%9 = tail call i32 (...) @enable_MMU()
br label %130
10: ; preds = %5
%11 = icmp ult i32 %0, 3
br i1 %11, label %12, label %16
12: ; preds = %10
%13 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([43 x i8], [43 x i8]* @.str.2, i64 0, i64 0))
%14 = tail call i32 (...) @enable_MMU()
%15 = tail call i32 (...) @initialize_L2C()
br label %130
16: ; preds = %10
%17 = icmp eq i32 %0, 3
br i1 %17, label %18, label %23
18: ; preds = %16
%19 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([51 x i8], [51 x i8]* @.str.3, i64 0, i64 0))
%20 = tail call i32 (...) @enable_MMU()
%21 = tail call i32 (...) @initialize_L2C()
%22 = tail call i32 (...) @enable_SCU()
br label %130
23: ; preds = %16
%24 = icmp ult i32 %0, 5
br i1 %24, label %25, label %31
25: ; preds = %23
%26 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([24 x i8], [24 x i8]* @.str.4, i64 0, i64 0))
%27 = tail call i32 (...) @enable_MMU()
%28 = tail call i32 (...) @initialize_L2C()
%29 = tail call i32 (...) @enable_SCU()
%30 = tail call i32 (...) @enable_L1_I()
br label %130
31: ; preds = %23
%32 = icmp eq i32 %0, 5
br i1 %32, label %33, label %40
33: ; preds = %31
%34 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([46 x i8], [46 x i8]* @.str.5, i64 0, i64 0))
%35 = tail call i32 (...) @enable_MMU()
%36 = tail call i32 (...) @initialize_L2C()
%37 = tail call i32 (...) @enable_SCU()
%38 = tail call i32 (...) @enable_L1_I()
%39 = tail call i32 (...) @enable_branch_prediction()
br label %130
40: ; preds = %31
%41 = icmp ult i32 %0, 7
br i1 %41, label %42, label %50
42: ; preds = %40
%43 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([52 x i8], [52 x i8]* @.str.6, i64 0, i64 0))
%44 = tail call i32 (...) @enable_MMU()
%45 = tail call i32 (...) @initialize_L2C()
%46 = tail call i32 (...) @enable_SCU()
%47 = tail call i32 (...) @enable_L1_D()
%48 = tail call i32 (...) @enable_L1_I()
%49 = tail call i32 (...) @enable_branch_prediction()
br label %130
50: ; preds = %40
%51 = icmp eq i32 %0, 7
br i1 %51, label %52, label %61
52: ; preds = %50
%53 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([73 x i8], [73 x i8]* @.str.7, i64 0, i64 0))
%54 = tail call i32 (...) @enable_MMU()
%55 = tail call i32 (...) @initialize_L2C()
%56 = tail call i32 (...) @enable_L1_D_side_prefetch()
%57 = tail call i32 (...) @enable_SCU()
%58 = tail call i32 (...) @enable_L1_D()
%59 = tail call i32 (...) @enable_L1_I()
%60 = tail call i32 (...) @enable_branch_prediction()
br label %130
61: ; preds = %50
%62 = icmp ult i32 %0, 9
br i1 %62, label %63, label %70
63: ; preds = %61
%64 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([75 x i8], [75 x i8]* @.str.8, i64 0, i64 0))
%65 = tail call i32 (...) @enable_MMU()
%66 = tail call i32 (...) @initialize_L2C()
%67 = tail call i32 (...) @enable_L1_D_side_prefetch()
%68 = tail call i32 (...) @enable_SCU()
%69 = tail call i32 (...) @enable_caches()
br label %130
70: ; preds = %61
%71 = icmp eq i32 %0, 9
br i1 %71, label %72, label %80
72: ; preds = %70
%73 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([52 x i8], [52 x i8]* @.str.9, i64 0, i64 0))
%74 = tail call i32 (...) @enable_MMU()
%75 = tail call i32 (...) @initialize_L2C()
%76 = tail call i32 (...) @enable_L1_D_side_prefetch()
%77 = tail call i32 (...) @enable_L2_prefetch_hint()
%78 = tail call i32 (...) @enable_SCU()
%79 = tail call i32 (...) @enable_caches()
br label %130
80: ; preds = %70
%81 = icmp ult i32 %0, 11
br i1 %81, label %82, label %91
82: ; preds = %80
%83 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([59 x i8], [59 x i8]* @.str.10, i64 0, i64 0))
%84 = tail call i32 (...) @enable_MMU()
%85 = tail call i32 (...) @initialize_L2C()
%86 = tail call i32 (...) @enable_L1_D_side_prefetch()
%87 = tail call i32 (...) @enable_L2_prefetch_hint()
%88 = tail call i32 (...) @enable_SCU()
%89 = tail call i32 (...) @enable_write_full_line_zeros()
%90 = tail call i32 (...) @enable_caches()
br label %130
91: ; preds = %80
%92 = icmp eq i32 %0, 11
br i1 %92, label %93, label %103
93: ; preds = %91
%94 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([74 x i8], [74 x i8]* @.str.11, i64 0, i64 0))
%95 = tail call i32 (...) @enable_MMU()
%96 = tail call i32 (...) @initialize_L2C()
%97 = tail call i32 (...) @enable_L1_D_side_prefetch()
%98 = tail call i32 (...) @enable_L2_prefetch_hint()
%99 = tail call i32 (...) @enable_SCU()
%100 = tail call i32 (...) @enable_L2_speculative_linefill()
%101 = tail call i32 (...) @enable_write_full_line_zeros()
%102 = tail call i32 (...) @enable_caches()
br label %130
103: ; preds = %91
%104 = icmp ult i32 %0, 13
br i1 %104, label %105, label %116
105: ; preds = %103
%106 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([64 x i8], [64 x i8]* @.str.12, i64 0, i64 0))
%107 = tail call i32 (...) @enable_MMU()
%108 = tail call i32 (...) @initialize_L2C()
%109 = tail call i32 (...) @enable_L1_D_side_prefetch()
%110 = tail call i32 (...) @enable_L2_prefetch_hint()
%111 = tail call i32 (...) @enable_SCU()
%112 = tail call i32 (...) @enable_L2_speculative_linefill()
%113 = tail call i32 (...) @enable_write_full_line_zeros()
%114 = tail call i32 (...) @enable_early_BRESP()
%115 = tail call i32 (...) @enable_caches()
br label %130
116: ; preds = %103
%117 = icmp eq i32 %0, 13
br i1 %117, label %118, label %130
118: ; preds = %116
%119 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([90 x i8], [90 x i8]* @.str.13, i64 0, i64 0))
%120 = tail call i32 (...) @enable_MMU()
%121 = tail call i32 (...) @initialize_L2C()
%122 = tail call i32 (...) @enable_L1_D_side_prefetch()
%123 = tail call i32 (...) @enable_L2_prefetch_hint()
%124 = tail call i32 (...) @enable_SCU()
%125 = tail call i32 (...) @enable_L2_speculative_linefill()
%126 = tail call i32 (...) @enable_write_full_line_zeros()
%127 = tail call i32 (...) @enable_early_BRESP()
%128 = tail call i32 (...) @enable_store_buffer_device_limitation()
%129 = tail call i32 (...) @enable_caches()
br label %130
130: ; preds = %7, %18, %33, %52, %72, %93, %116, %118, %105, %82, %63, %42, %25, %12, %3
ret void
}