unsigned long SetI2CRegClient(unsigned long MMIOBase,
                              unsigned char DeviceSelect,
                              unsigned char DeviceAddress,
                              unsigned char RegisterIndex,
                              unsigned char RegisterValue) {
  unsigned long Status;
  unsigned long Count = 0;
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x00)) = (unsigned long)(0);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x04)) =
      (unsigned long)(0x77743355);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x08)) = (unsigned long)(0);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x10)) =
      (unsigned long)(0xFFFFFFFF);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x00)) = (unsigned long)(1);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x0C)) = (unsigned long)(0xAF);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x20)) =
      (unsigned long)(DeviceAddress);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x14)) = (unsigned long)(0x3);
  do {
    Count++;
    Status = *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                         (unsigned long)(0xA000 +
                                                         DeviceSelect * 0x40 +
                                                         0x10)) &
             0x03;
    if (2 == Status) {
      *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                  (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                                  0x10)) =
          (unsigned long)(0xFFFFFFFF);
      *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                  (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                                  0x20)) =
          (unsigned long)(DeviceAddress);
      *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                  (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                                  0x14)) = (unsigned long)(0x3);
    }
    {
      if (Count > 1000) {
        return 1;
      }
    }
  } while (Status != 1);
  Count = 0;
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x10)) =
      (unsigned long)(0xFFFFFFFF);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x20)) =
      (unsigned long)(RegisterIndex);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x14)) = (unsigned long)(0x2);
  do {
    Count++;
    Status = *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                         (unsigned long)(0xA000 +
                                                         DeviceSelect * 0x40 +
                                                         0x10)) &
             0x03;
    if (Count > 1000) {
      return 1;
    }
  } while (Status != 1);
  Count = 0;
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x10)) =
      (unsigned long)(0xFFFFFFFF);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x20)) =
      (unsigned long)(RegisterValue);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x14)) = (unsigned long)(0x2);
  do {
    Count++;
    Status = *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                         (unsigned long)(0xA000 +
                                                         DeviceSelect * 0x40 +
                                                         0x10)) &
             0x03;
    if (Count > 1000) {
      return 1;
    }
  } while (Status != 1);
  Count = 0;
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x10)) =
      (unsigned long)(0xFFFFFFFF);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x0C)) =
      (((*(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                     (unsigned long)(0xA000 +
                                                     DeviceSelect * 0x40 +
                                                     0x0C))) &
        (~0x10)) |
       (unsigned long)((0x10) & (0x10)));
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x14)) = (unsigned long)(0x20);
  do {
    Count++;
    Status = (*(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                          (unsigned long)(0xA000 +
                                                          DeviceSelect * 0x40 +
                                                          0x10)) &
              0x10) >>
             4;
    if (Count > 1000) {
      return 1;
    }
  } while (Status != 1);
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x0C)) =
      (((*(volatile unsigned long *)((unsigned long)(0x1E780000) +
                                     (unsigned long)(0xA000 +
                                                     DeviceSelect * 0x40 +
                                                     0x0C))) &
        (~0x10)) |
       (unsigned long)((0) & (0x10)));
  *(volatile unsigned long *)((unsigned long)(0x1E780000) +
                              (unsigned long)(0xA000 + DeviceSelect * 0x40 +
                                              0x10)) =
      (unsigned long)(0xFFFFFFFF);
  return 0;
}


x86 assembly (clang, -O0):
<SetI2CRegClient>:
push   %rbp
mov    %rsp,%rbp
mov    %r8b,%al
mov    %rdi,-0x10(%rbp)
mov    %sil,-0x11(%rbp)
mov    %dl,-0x12(%rbp)
mov    %cl,-0x13(%rbp)
mov    %al,-0x14(%rbp)
movq   $0x0,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x0,%eax
cltq
add    $0x1e780000,%rax
movq   $0x0,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x4,%eax
cltq
add    $0x1e780000,%rax
movq   $0x77743355,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x8,%eax
cltq
add    $0x1e780000,%rax
movq   $0x0,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x0,%eax
cltq
add    $0x1e780000,%rax
movq   $0x1,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0xc,%eax
cltq
add    $0x1e780000,%rax
movq   $0xaf,(%rax)
movzbl -0x12(%rbp),%eax
mov    %eax,%ecx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x20,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x14,%eax
cltq
add    $0x1e780000,%rax
movq   $0x3,(%rax)
mov    -0x28(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rax
and    $0x3,%rax
mov    %rax,-0x20(%rbp)
mov    $0x2,%eax
cmp    -0x20(%rbp),%rax
jne    12ad <SetI2CRegClient+0x1ad>
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movzbl -0x12(%rbp),%eax
mov    %eax,%ecx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x20,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x14,%eax
cltq
add    $0x1e780000,%rax
movq   $0x3,(%rax)
cmpq   $0x3e8,-0x28(%rbp)
jbe    12c8 <SetI2CRegClient+0x1c8>
movq   $0x1,-0x8(%rbp)
jmp    1595 <SetI2CRegClient+0x495>
jmp    12cd <SetI2CRegClient+0x1cd>
cmpq   $0x1,-0x20(%rbp)
jne    1213 <SetI2CRegClient+0x113>
movq   $0x0,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movzbl -0x13(%rbp),%eax
mov    %eax,%ecx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x20,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x14,%eax
cltq
add    $0x1e780000,%rax
movq   $0x2,(%rax)
mov    -0x28(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rax
and    $0x3,%rax
mov    %rax,-0x20(%rbp)
cmpq   $0x3e8,-0x28(%rbp)
jbe    1386 <SetI2CRegClient+0x286>
movq   $0x1,-0x8(%rbp)
jmp    1595 <SetI2CRegClient+0x495>
jmp    138b <SetI2CRegClient+0x28b>
cmpq   $0x1,-0x20(%rbp)
jne    133d <SetI2CRegClient+0x23d>
movq   $0x0,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movzbl -0x14(%rbp),%eax
mov    %eax,%ecx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x20,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x14,%eax
cltq
add    $0x1e780000,%rax
movq   $0x2,(%rax)
mov    -0x28(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rax
and    $0x3,%rax
mov    %rax,-0x20(%rbp)
cmpq   $0x3e8,-0x28(%rbp)
jbe    1444 <SetI2CRegClient+0x344>
movq   $0x1,-0x8(%rbp)
jmp    1595 <SetI2CRegClient+0x495>
jmp    1449 <SetI2CRegClient+0x349>
cmpq   $0x1,-0x20(%rbp)
jne    13fb <SetI2CRegClient+0x2fb>
movq   $0x0,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0xc,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rcx
and    $0xffffffffffffffef,%rcx
or     $0x10,%rcx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0xc,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x14,%eax
cltq
add    $0x1e780000,%rax
movq   $0x20,(%rax)
mov    -0x28(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x28(%rbp)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rax
and    $0x10,%rax
shr    $0x4,%rax
mov    %rax,-0x20(%rbp)
cmpq   $0x3e8,-0x28(%rbp)
jbe    1522 <SetI2CRegClient+0x422>
movq   $0x1,-0x8(%rbp)
jmp    1595 <SetI2CRegClient+0x495>
jmp    1527 <SetI2CRegClient+0x427>
cmpq   $0x1,-0x20(%rbp)
jne    14d5 <SetI2CRegClient+0x3d5>
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0xc,%eax
cltq
add    $0x1e780000,%rax
mov    (%rax),%rcx
and    $0xffffffffffffffef,%rcx
or     $0x0,%rcx
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0xc,%eax
cltq
add    $0x1e780000,%rax
mov    %rcx,(%rax)
movzbl -0x11(%rbp),%eax
shl    $0x6,%eax
add    $0xa000,%eax
add    $0x10,%eax
cltq
add    $0x1e780000,%rax
mov    $0xffffffff,%ecx
mov    %rcx,(%rax)
movq   $0x0,-0x8(%rbp)
mov    -0x8(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<SetI2CRegClient>:
mov    $0xffffffff,%r9d
mov    %esi,%esi
shl    $0x6,%rsi
movq   $0x0,0x1e78a000(%rsi)
movq   $0x77743355,0x1e78a004(%rsi)
55 33 74 77
movq   $0x0,0x1e78a008(%rsi)
mov    %r9,0x1e78a010(%rsi)
movq   $0x1,0x1e78a000(%rsi)
movq   $0xaf,0x1e78a00c(%rsi)
mov    %edx,%r10d
mov    %r10,0x1e78a020(%rsi)
movq   $0x3,0x1e78a014(%rsi)
mov    $0x3e8,%edi
mov    $0x1,%eax
jmp    118d <SetI2CRegClient+0x8d>
nopl   0x0(%rax,%rax,1)
mov    %r9,0x1e78a010(%rsi)
mov    %r10,0x1e78a020(%rsi)
movq   $0x3,0x1e78a014(%rsi)
add    $0xfffffffffffffffe,%rdi
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x2,%rdx
jne    11b6 <SetI2CRegClient+0xb6>
mov    %r9,0x1e78a010(%rsi)
mov    %r10,0x1e78a020(%rsi)
movq   $0x3,0x1e78a014(%rsi)
test   %rdi,%rdi
je     132a <SetI2CRegClient+0x22a>
cmp    $0x1,%edx
je     11df <SetI2CRegClient+0xdf>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x2,%rdx
je     1170 <SetI2CRegClient+0x70>
cmp    $0x1,%edx
je     11df <SetI2CRegClient+0xdf>
add    $0xfffffffffffffffe,%rdi
jmp    118d <SetI2CRegClient+0x8d>
mov    %r9,0x1e78a010(%rsi)
movzbl %cl,%ecx
mov    %rcx,0x1e78a020(%rsi)
movq   $0x2,0x1e78a014(%rsi)
mov    $0x3ec,%ecx
mov    0x1e78a010(%rsi),%rdx
add    $0xfffffffffffffffc,%rcx
je     132a <SetI2CRegClient+0x22a>
and    $0x3,%edx
cmp    $0x1,%edx
je     1246 <SetI2CRegClient+0x146>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
je     1246 <SetI2CRegClient+0x146>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
je     1246 <SetI2CRegClient+0x146>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
jne    1200 <SetI2CRegClient+0x100>
mov    %r9,0x1e78a010(%rsi)
movzbl %r8b,%ecx
mov    %rcx,0x1e78a020(%rsi)
movq   $0x2,0x1e78a014(%rsi)
mov    $0x3ec,%ecx
nopl   0x0(%rax,%rax,1)
mov    0x1e78a010(%rsi),%rdx
add    $0xfffffffffffffffc,%rcx
je     132a <SetI2CRegClient+0x22a>
and    $0x3,%edx
cmp    $0x1,%edx
je     12b6 <SetI2CRegClient+0x1b6>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
je     12b6 <SetI2CRegClient+0x1b6>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
je     12b6 <SetI2CRegClient+0x1b6>
mov    0x1e78a010(%rsi),%rdx
and    $0x3,%edx
cmp    $0x1,%edx
jne    1270 <SetI2CRegClient+0x170>
mov    %r9,0x1e78a010(%rsi)
orq    $0x10,0x1e78a00c(%rsi)
10
movq   $0x20,0x1e78a014(%rsi)
mov    $0x3ec,%ecx
cs nopw 0x0(%rax,%rax,1)
nop
mov    0x1e78a010(%rsi),%rdx
add    $0xfffffffffffffffc,%rcx
je     132a <SetI2CRegClient+0x22a>
test   $0x10,%dl
jne    1319 <SetI2CRegClient+0x219>
testq  $0x10,0x1e78a010(%rsi)
jne    1319 <SetI2CRegClient+0x219>
testq  $0x10,0x1e78a010(%rsi)
jne    1319 <SetI2CRegClient+0x219>
testq  $0x10,0x1e78a010(%rsi)
je     12e0 <SetI2CRegClient+0x1e0>
andq   $0xffffffffffffffef,0x1e78a00c(%rsi)
ef
mov    %r9,0x1e78a010(%rsi)
xor    %eax,%eax
ret

LLVM IR (-O0):
define i64 @SetI2CRegClient(i64 %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, i8 zeroext %4) {
%6 = alloca i64
%7 = alloca i64
%8 = alloca i8
%9 = alloca i8
%10 = alloca i8
%11 = alloca i8
%12 = alloca i64
%13 = alloca i64
store i64 %0, i64* %7
store i8 %1, i8* %8
store i8 %2, i8* %9
store i8 %3, i8* %10
store i8 %4, i8* %11
store i64 0, i64* %13
%14 = load i8, i8* %8
%15 = zext i8 %14 to i32
%16 = mul nsw i32 %15, 64
%17 = add nsw i32 40960, %16
%18 = add nsw i32 %17, 0
%19 = sext i32 %18 to i64
%20 = add i64 511180800, %19
%21 = inttoptr i64 %20 to i64*
store volatile i64 0, i64* %21
%22 = load i8, i8* %8
%23 = zext i8 %22 to i32
%24 = mul nsw i32 %23, 64
%25 = add nsw i32 40960, %24
%26 = add nsw i32 %25, 4
%27 = sext i32 %26 to i64
%28 = add i64 511180800, %27
%29 = inttoptr i64 %28 to i64*
store volatile i64 2004104021, i64* %29
%30 = load i8, i8* %8
%31 = zext i8 %30 to i32
%32 = mul nsw i32 %31, 64
%33 = add nsw i32 40960, %32
%34 = add nsw i32 %33, 8
%35 = sext i32 %34 to i64
%36 = add i64 511180800, %35
%37 = inttoptr i64 %36 to i64*
store volatile i64 0, i64* %37
%38 = load i8, i8* %8
%39 = zext i8 %38 to i32
%40 = mul nsw i32 %39, 64
%41 = add nsw i32 40960, %40
%42 = add nsw i32 %41, 16
%43 = sext i32 %42 to i64
%44 = add i64 511180800, %43
%45 = inttoptr i64 %44 to i64*
store volatile i64 4294967295, i64* %45
%46 = load i8, i8* %8
%47 = zext i8 %46 to i32
%48 = mul nsw i32 %47, 64
%49 = add nsw i32 40960, %48
%50 = add nsw i32 %49, 0
%51 = sext i32 %50 to i64
%52 = add i64 511180800, %51
%53 = inttoptr i64 %52 to i64*
store volatile i64 1, i64* %53
%54 = load i8, i8* %8
%55 = zext i8 %54 to i32
%56 = mul nsw i32 %55, 64
%57 = add nsw i32 40960, %56
%58 = add nsw i32 %57, 12
%59 = sext i32 %58 to i64
%60 = add i64 511180800, %59
%61 = inttoptr i64 %60 to i64*
store volatile i64 175, i64* %61
%62 = load i8, i8* %9
%63 = zext i8 %62 to i64
%64 = load i8, i8* %8
%65 = zext i8 %64 to i32
%66 = mul nsw i32 %65, 64
%67 = add nsw i32 40960, %66
%68 = add nsw i32 %67, 32
%69 = sext i32 %68 to i64
%70 = add i64 511180800, %69
%71 = inttoptr i64 %70 to i64*
store volatile i64 %63, i64* %71
%72 = load i8, i8* %8
%73 = zext i8 %72 to i32
%74 = mul nsw i32 %73, 64
%75 = add nsw i32 40960, %74
%76 = add nsw i32 %75, 20
%77 = sext i32 %76 to i64
%78 = add i64 511180800, %77
%79 = inttoptr i64 %78 to i64*
store volatile i64 3, i64* %79
br label %80
80: ; preds = %127, %5
%81 = load i64, i64* %13
%82 = add i64 %81, 1
store i64 %82, i64* %13
%83 = load i8, i8* %8
%84 = zext i8 %83 to i32
%85 = mul nsw i32 %84, 64
%86 = add nsw i32 40960, %85
%87 = add nsw i32 %86, 16
%88 = sext i32 %87 to i64
%89 = add i64 511180800, %88
%90 = inttoptr i64 %89 to i64*
%91 = load volatile i64, i64* %90
%92 = and i64 %91, 3
store i64 %92, i64* %12
%93 = load i64, i64* %12
%94 = icmp eq i64 2, %93
br i1 %94, label %95, label %122
95: ; preds = %80
%96 = load i8, i8* %8
%97 = zext i8 %96 to i32
%98 = mul nsw i32 %97, 64
%99 = add nsw i32 40960, %98
%100 = add nsw i32 %99, 16
%101 = sext i32 %100 to i64
%102 = add i64 511180800, %101
%103 = inttoptr i64 %102 to i64*
store volatile i64 4294967295, i64* %103
%104 = load i8, i8* %9
%105 = zext i8 %104 to i64
%106 = load i8, i8* %8
%107 = zext i8 %106 to i32
%108 = mul nsw i32 %107, 64
%109 = add nsw i32 40960, %108
%110 = add nsw i32 %109, 32
%111 = sext i32 %110 to i64
%112 = add i64 511180800, %111
%113 = inttoptr i64 %112 to i64*
store volatile i64 %105, i64* %113
%114 = load i8, i8* %8
%115 = zext i8 %114 to i32
%116 = mul nsw i32 %115, 64
%117 = add nsw i32 40960, %116
%118 = add nsw i32 %117, 20
%119 = sext i32 %118 to i64
%120 = add i64 511180800, %119
%121 = inttoptr i64 %120 to i64*
store volatile i64 3, i64* %121
br label %122
122: ; preds = %95, %80
%123 = load i64, i64* %13
%124 = icmp ugt i64 %123, 1000
br i1 %124, label %125, label %126
125: ; preds = %122
store i64 1, i64* %6
br label %309
126: ; preds = %122
br label %127
127: ; preds = %126
%128 = load i64, i64* %12
%129 = icmp ne i64 %128, 1
br i1 %129, label %80, label %130
130: ; preds = %127
store i64 0, i64* %13
%131 = load i8, i8* %8
%132 = zext i8 %131 to i32
%133 = mul nsw i32 %132, 64
%134 = add nsw i32 40960, %133
%135 = add nsw i32 %134, 16
%136 = sext i32 %135 to i64
%137 = add i64 511180800, %136
%138 = inttoptr i64 %137 to i64*
store volatile i64 4294967295, i64* %138
%139 = load i8, i8* %10
%140 = zext i8 %139 to i64
%141 = load i8, i8* %8
%142 = zext i8 %141 to i32
%143 = mul nsw i32 %142, 64
%144 = add nsw i32 40960, %143
%145 = add nsw i32 %144, 32
%146 = sext i32 %145 to i64
%147 = add i64 511180800, %146
%148 = inttoptr i64 %147 to i64*
store volatile i64 %140, i64* %148
%149 = load i8, i8* %8
%150 = zext i8 %149 to i32
%151 = mul nsw i32 %150, 64
%152 = add nsw i32 40960, %151
%153 = add nsw i32 %152, 20
%154 = sext i32 %153 to i64
%155 = add i64 511180800, %154
%156 = inttoptr i64 %155 to i64*
store volatile i64 2, i64* %156
br label %157
157: ; preds = %174, %130
%158 = load i64, i64* %13
%159 = add i64 %158, 1
store i64 %159, i64* %13
%160 = load i8, i8* %8
%161 = zext i8 %160 to i32
%162 = mul nsw i32 %161, 64
%163 = add nsw i32 40960, %162
%164 = add nsw i32 %163, 16
%165 = sext i32 %164 to i64
%166 = add i64 511180800, %165
%167 = inttoptr i64 %166 to i64*
%168 = load volatile i64, i64* %167
%169 = and i64 %168, 3
store i64 %169, i64* %12
%170 = load i64, i64* %13
%171 = icmp ugt i64 %170, 1000
br i1 %171, label %172, label %173
172: ; preds = %157
store i64 1, i64* %6
br label %309
173: ; preds = %157
br label %174
174: ; preds = %173
%175 = load i64, i64* %12
%176 = icmp ne i64 %175, 1
br i1 %176, label %157, label %177
177: ; preds = %174
store i64 0, i64* %13
%178 = load i8, i8* %8
%179 = zext i8 %178 to i32
%180 = mul nsw i32 %179, 64
%181 = add nsw i32 40960, %180
%182 = add nsw i32 %181, 16
%183 = sext i32 %182 to i64
%184 = add i64 511180800, %183
%185 = inttoptr i64 %184 to i64*
store volatile i64 4294967295, i64* %185
%186 = load i8, i8* %11
%187 = zext i8 %186 to i64
%188 = load i8, i8* %8
%189 = zext i8 %188 to i32
%190 = mul nsw i32 %189, 64
%191 = add nsw i32 40960, %190
%192 = add nsw i32 %191, 32
%193 = sext i32 %192 to i64
%194 = add i64 511180800, %193
%195 = inttoptr i64 %194 to i64*
store volatile i64 %187, i64* %195
%196 = load i8, i8* %8
%197 = zext i8 %196 to i32
%198 = mul nsw i32 %197, 64
%199 = add nsw i32 40960, %198
%200 = add nsw i32 %199, 20
%201 = sext i32 %200 to i64
%202 = add i64 511180800, %201
%203 = inttoptr i64 %202 to i64*
store volatile i64 2, i64* %203
br label %204
204: ; preds = %221, %177
%205 = load i64, i64* %13
%206 = add i64 %205, 1
store i64 %206, i64* %13
%207 = load i8, i8* %8
%208 = zext i8 %207 to i32
%209 = mul nsw i32 %208, 64
%210 = add nsw i32 40960, %209
%211 = add nsw i32 %210, 16
%212 = sext i32 %211 to i64
%213 = add i64 511180800, %212
%214 = inttoptr i64 %213 to i64*
%215 = load volatile i64, i64* %214
%216 = and i64 %215, 3
store i64 %216, i64* %12
%217 = load i64, i64* %13
%218 = icmp ugt i64 %217, 1000
br i1 %218, label %219, label %220
219: ; preds = %204
store i64 1, i64* %6
br label %309
220: ; preds = %204
br label %221
221: ; preds = %220
%222 = load i64, i64* %12
%223 = icmp ne i64 %222, 1
br i1 %223, label %204, label %224
224: ; preds = %221
store i64 0, i64* %13
%225 = load i8, i8* %8
%226 = zext i8 %225 to i32
%227 = mul nsw i32 %226, 64
%228 = add nsw i32 40960, %227
%229 = add nsw i32 %228, 16
%230 = sext i32 %229 to i64
%231 = add i64 511180800, %230
%232 = inttoptr i64 %231 to i64*
store volatile i64 4294967295, i64* %232
%233 = load i8, i8* %8
%234 = zext i8 %233 to i32
%235 = mul nsw i32 %234, 64
%236 = add nsw i32 40960, %235
%237 = add nsw i32 %236, 12
%238 = sext i32 %237 to i64
%239 = add i64 511180800, %238
%240 = inttoptr i64 %239 to i64*
%241 = load volatile i64, i64* %240
%242 = and i64 %241, -17
%243 = or i64 %242, 16
%244 = load i8, i8* %8
%245 = zext i8 %244 to i32
%246 = mul nsw i32 %245, 64
%247 = add nsw i32 40960, %246
%248 = add nsw i32 %247, 12
%249 = sext i32 %248 to i64
%250 = add i64 511180800, %249
%251 = inttoptr i64 %250 to i64*
store volatile i64 %243, i64* %251
%252 = load i8, i8* %8
%253 = zext i8 %252 to i32
%254 = mul nsw i32 %253, 64
%255 = add nsw i32 40960, %254
%256 = add nsw i32 %255, 20
%257 = sext i32 %256 to i64
%258 = add i64 511180800, %257
%259 = inttoptr i64 %258 to i64*
store volatile i64 32, i64* %259
br label %260
260: ; preds = %278, %224
%261 = load i64, i64* %13
%262 = add i64 %261, 1
store i64 %262, i64* %13
%263 = load i8, i8* %8
%264 = zext i8 %263 to i32
%265 = mul nsw i32 %264, 64
%266 = add nsw i32 40960, %265
%267 = add nsw i32 %266, 16
%268 = sext i32 %267 to i64
%269 = add i64 511180800, %268
%270 = inttoptr i64 %269 to i64*
%271 = load volatile i64, i64* %270
%272 = and i64 %271, 16
%273 = lshr i64 %272, 4
store i64 %273, i64* %12
%274 = load i64, i64* %13
%275 = icmp ugt i64 %274, 1000
br i1 %275, label %276, label %277
276: ; preds = %260
store i64 1, i64* %6
br label %309
277: ; preds = %260
br label %278
278: ; preds = %277
%279 = load i64, i64* %12
%280 = icmp ne i64 %279, 1
br i1 %280, label %260, label %281
281: ; preds = %278
%282 = load i8, i8* %8
%283 = zext i8 %282 to i32
%284 = mul nsw i32 %283, 64
%285 = add nsw i32 40960, %284
%286 = add nsw i32 %285, 12
%287 = sext i32 %286 to i64
%288 = add i64 511180800, %287
%289 = inttoptr i64 %288 to i64*
%290 = load volatile i64, i64* %289
%291 = and i64 %290, -17
%292 = or i64 %291, 0
%293 = load i8, i8* %8
%294 = zext i8 %293 to i32
%295 = mul nsw i32 %294, 64
%296 = add nsw i32 40960, %295
%297 = add nsw i32 %296, 12
%298 = sext i32 %297 to i64
%299 = add i64 511180800, %298
%300 = inttoptr i64 %299 to i64*
store volatile i64 %292, i64* %300
%301 = load i8, i8* %8
%302 = zext i8 %301 to i32
%303 = mul nsw i32 %302, 64
%304 = add nsw i32 40960, %303
%305 = add nsw i32 %304, 16
%306 = sext i32 %305 to i64
%307 = add i64 511180800, %306
%308 = inttoptr i64 %307 to i64*
store volatile i64 4294967295, i64* %308
store i64 0, i64* %6
br label %309
309: ; preds = %281, %276, %219, %172, %125
%310 = load i64, i64* %6
ret i64 %310
}

LLVM IR (-O2):
define i64 @SetI2CRegClient(i64 %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3, i8 zeroext %4) {
%6 = zext i8 %1 to i32
%7 = shl nuw nsw i32 %6, 6
%8 = add nuw nsw i32 %7, 511221760
%9 = zext i32 %8 to i64
%10 = inttoptr i64 %9 to i64*
store volatile i64 0, i64* %10
%11 = add nuw nsw i32 %7, 511221764
%12 = zext i32 %11 to i64
%13 = inttoptr i64 %12 to i64*
store volatile i64 2004104021, i64* %13
%14 = add nuw nsw i32 %7, 511221768
%15 = zext i32 %14 to i64
%16 = inttoptr i64 %15 to i64*
store volatile i64 0, i64* %16
%17 = add nuw nsw i32 %7, 511221776
%18 = zext i32 %17 to i64
%19 = inttoptr i64 %18 to i64*
store volatile i64 4294967295, i64* %19
store volatile i64 1, i64* %10
%20 = add nuw nsw i32 %7, 511221772
%21 = zext i32 %20 to i64
%22 = inttoptr i64 %21 to i64*
store volatile i64 175, i64* %22
%23 = zext i8 %2 to i64
%24 = add nuw nsw i32 %7, 511221792
%25 = zext i32 %24 to i64
%26 = inttoptr i64 %25 to i64*
store volatile i64 %23, i64* %26
%27 = add nuw nsw i32 %7, 511221780
%28 = zext i32 %27 to i64
%29 = inttoptr i64 %28 to i64*
store volatile i64 3, i64* %29
br label %30
30: ; preds = %44, %40, %5
%31 = phi i64 [ 0, %5 ], [ %41, %44 ], [ %41, %40 ]
%32 = load volatile i64, i64* %19
%33 = and i64 %32, 3
%34 = icmp eq i64 %33, 2
br i1 %34, label %35, label %36
35: ; preds = %30
store volatile i64 4294967295, i64* %19
store volatile i64 %23, i64* %26
store volatile i64 3, i64* %29
br label %36
36: ; preds = %35, %30
%37 = icmp eq i64 %31, 1000
br i1 %37, label %115, label %38
38: ; preds = %36
%39 = icmp eq i64 %33, 1
br i1 %39, label %45, label %40
40: ; preds = %38
%41 = add nuw nsw i64 %31, 2
%42 = load volatile i64, i64* %19
%43 = and i64 %42, 3
switch i64 %43, label %30 [
i64 2, label %44
i64 1, label %45
]
44: ; preds = %40
store volatile i64 4294967295, i64* %19
store volatile i64 %23, i64* %26
store volatile i64 3, i64* %29
br label %30
45: ; preds = %40, %38
store volatile i64 4294967295, i64* %19
%46 = zext i8 %3 to i64
store volatile i64 %46, i64* %26
store volatile i64 2, i64* %29
br label %47
47: ; preds = %62, %45
%48 = phi i64 [ 0, %45 ], [ %64, %62 ]
%49 = load volatile i64, i64* %19
%50 = icmp eq i64 %48, 1000
br i1 %50, label %115, label %51
51: ; preds = %47
%52 = and i64 %49, 3
%53 = icmp eq i64 %52, 1
br i1 %53, label %67, label %54
54: ; preds = %51
%55 = load volatile i64, i64* %19
%56 = and i64 %55, 3
%57 = icmp eq i64 %56, 1
br i1 %57, label %67, label %58
58: ; preds = %54
%59 = load volatile i64, i64* %19
%60 = and i64 %59, 3
%61 = icmp eq i64 %60, 1
br i1 %61, label %67, label %62
62: ; preds = %58
%63 = load volatile i64, i64* %19
%64 = add nuw nsw i64 %48, 4
%65 = and i64 %63, 3
%66 = icmp eq i64 %65, 1
br i1 %66, label %67, label %47
67: ; preds = %62, %58, %54, %51
store volatile i64 4294967295, i64* %19
%68 = zext i8 %4 to i64
store volatile i64 %68, i64* %26
store volatile i64 2, i64* %29
br label %69
69: ; preds = %84, %67
%70 = phi i64 [ 0, %67 ], [ %86, %84 ]
%71 = load volatile i64, i64* %19
%72 = icmp eq i64 %70, 1000
br i1 %72, label %115, label %73
73: ; preds = %69
%74 = and i64 %71, 3
%75 = icmp eq i64 %74, 1
br i1 %75, label %89, label %76
76: ; preds = %73
%77 = load volatile i64, i64* %19
%78 = and i64 %77, 3
%79 = icmp eq i64 %78, 1
br i1 %79, label %89, label %80
80: ; preds = %76
%81 = load volatile i64, i64* %19
%82 = and i64 %81, 3
%83 = icmp eq i64 %82, 1
br i1 %83, label %89, label %84
84: ; preds = %80
%85 = load volatile i64, i64* %19
%86 = add nuw nsw i64 %70, 4
%87 = and i64 %85, 3
%88 = icmp eq i64 %87, 1
br i1 %88, label %89, label %69
89: ; preds = %84, %80, %76, %73
store volatile i64 4294967295, i64* %19
%90 = load volatile i64, i64* %22
%91 = or i64 %90, 16
store volatile i64 %91, i64* %22
store volatile i64 32, i64* %29
br label %92
92: ; preds = %107, %89
%93 = phi i64 [ 0, %89 ], [ %109, %107 ]
%94 = load volatile i64, i64* %19
%95 = icmp eq i64 %93, 1000
br i1 %95, label %115, label %96
96: ; preds = %92
%97 = and i64 %94, 16
%98 = icmp eq i64 %97, 0
br i1 %98, label %99, label %112
99: ; preds = %96
%100 = load volatile i64, i64* %19
%101 = and i64 %100, 16
%102 = icmp eq i64 %101, 0
br i1 %102, label %103, label %112
103: ; preds = %99
%104 = load volatile i64, i64* %19
%105 = and i64 %104, 16
%106 = icmp eq i64 %105, 0
br i1 %106, label %107, label %112
107: ; preds = %103
%108 = load volatile i64, i64* %19
%109 = add nuw nsw i64 %93, 4
%110 = and i64 %108, 16
%111 = icmp eq i64 %110, 0
br i1 %111, label %92, label %112
112: ; preds = %107, %103, %99, %96
%113 = load volatile i64, i64* %22
%114 = and i64 %113, -17
store volatile i64 %114, i64* %22
store volatile i64 4294967295, i64* %19
br label %115
115: ; preds = %36, %47, %69, %92, %112
%116 = phi i64 [ 0, %112 ], [ 1, %92 ], [ 1, %69 ], [ 1, %47 ], [ 1, %36 ]
ret i64 %116
}