#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ CodecRegBitClr(unsigned int, int, int);
int /*<<< orphan*/ CodecRegWrite(unsigned int, int, unsigned char);
void AIC31SampleRateConfig(unsigned int baseAddr, unsigned int mode,
                           unsigned int sampleRate) {
  unsigned char fs;
  unsigned char ref = 0x0Au;
  unsigned char temp;
  unsigned char pllPval = 2u;
  unsigned char pllRval = 1u;
  unsigned char pllJval = 7u;
  unsigned short pllDval = 5264u;
  switch (sampleRate) {
  case 8000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0xAAu;
    break;
  case 11025:
    fs = 0x66u;
    ref = 0x8Au;
    break;
  case 16000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0x44u;
    break;
  case 22050:
    fs = 0x22u;
    ref = 0x8Au;
    break;
  case 24000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0x22u;
    break;
  case 32000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0x22u;
    break;
  case 44100:
    ref = 0x8Au;
    fs = 0x00u;
    break;
  case 48000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0x00u;
    break;
  case 96000:
    pllJval = 8u;
    pllDval = 1920u;
    fs = 0x00u;
    break;
  default:
    fs = 0x00u;
    break;
  }
  temp = (mode & fs);
  CodecRegWrite(baseAddr, (2), temp);
  CodecRegWrite(baseAddr, (3), 0x80 | pllPval);
  CodecRegWrite(baseAddr, (102), 0x08);
  CodecRegBitClr(baseAddr, (101), 0x01);
  CodecRegWrite(baseAddr, (98), 0x20);
  CodecRegWrite(baseAddr, (4), pllJval << 2);
  CodecRegWrite(baseAddr, (5), (pllDval >> 6) & 0xFF);
  CodecRegWrite(baseAddr, (6), (pllDval & 0x3F) << 2);
  CodecRegWrite(baseAddr, (11), pllRval);
  CodecRegWrite(baseAddr, (8), 0xD0);
  CodecRegWrite(baseAddr, (7), ref);
}


x86 assembly (clang, -O0):
<AIC31SampleRateConfig>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
movb   $0xa,-0xe(%rbp)
movb   $0x2,-0x10(%rbp)
movb   $0x1,-0x11(%rbp)
movb   $0x7,-0x12(%rbp)
movw   $0x1490,-0x14(%rbp)
mov    -0xc(%rbp),%eax
mov    %eax,-0x18(%rbp)
sub    $0x1f40,%eax
je     11f5 <AIC31SampleRateConfig+0xd5>
jmp    115d <AIC31SampleRateConfig+0x3d>
mov    -0x18(%rbp),%eax
sub    $0x2b11,%eax
je     1208 <AIC31SampleRateConfig+0xe8>
jmp    1170 <AIC31SampleRateConfig+0x50>
mov    -0x18(%rbp),%eax
sub    $0x3e80,%eax
je     1215 <AIC31SampleRateConfig+0xf5>
jmp    1183 <AIC31SampleRateConfig+0x63>
mov    -0x18(%rbp),%eax
sub    $0x5622,%eax
je     1228 <AIC31SampleRateConfig+0x108>
jmp    1196 <AIC31SampleRateConfig+0x76>
mov    -0x18(%rbp),%eax
sub    $0x5dc0,%eax
je     1235 <AIC31SampleRateConfig+0x115>
jmp    11a9 <AIC31SampleRateConfig+0x89>
mov    -0x18(%rbp),%eax
sub    $0x7d00,%eax
je     1248 <AIC31SampleRateConfig+0x128>
jmp    11bc <AIC31SampleRateConfig+0x9c>
mov    -0x18(%rbp),%eax
sub    $0xac44,%eax
je     125b <AIC31SampleRateConfig+0x13b>
jmp    11cf <AIC31SampleRateConfig+0xaf>
mov    -0x18(%rbp),%eax
sub    $0xbb80,%eax
je     1268 <AIC31SampleRateConfig+0x148>
jmp    11e2 <AIC31SampleRateConfig+0xc2>
mov    -0x18(%rbp),%eax
sub    $0x17700,%eax
je     127b <AIC31SampleRateConfig+0x15b>
jmp    128e <AIC31SampleRateConfig+0x16e>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0xaa,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x66,-0xd(%rbp)
movb   $0x8a,-0xe(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0x44,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x22,-0xd(%rbp)
movb   $0x8a,-0xe(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0x22,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0x22,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8a,-0xe(%rbp)
movb   $0x0,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0x0,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x8,-0x12(%rbp)
movw   $0x780,-0x14(%rbp)
movb   $0x0,-0xd(%rbp)
jmp    1292 <AIC31SampleRateConfig+0x172>
movb   $0x0,-0xd(%rbp)
mov    -0x8(%rbp),%eax
movzbl -0xd(%rbp),%ecx
and    %ecx,%eax
mov    %al,-0xf(%rbp)
mov    -0x4(%rbp),%edi
mov    $0x2,%esi
movzbl -0xf(%rbp),%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
movzbl -0x10(%rbp),%eax
or     $0x80,%eax
mov    $0x3,%esi
movzbl %al,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
mov    $0x66,%esi
mov    $0x8,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
mov    $0x65,%esi
mov    $0x1,%edx
call   1040 <CodecRegBitClr@plt>
mov    -0x4(%rbp),%edi
mov    $0x62,%esi
mov    $0x20,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
movzbl -0x12(%rbp),%eax
shl    $0x2,%eax
mov    $0x4,%esi
movzbl %al,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
movzwl -0x14(%rbp),%eax
sar    $0x6,%eax
and    $0xff,%eax
mov    $0x5,%esi
movzbl %al,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
movzwl -0x14(%rbp),%eax
and    $0x3f,%eax
shl    $0x2,%eax
mov    $0x6,%esi
movzbl %al,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
mov    $0xb,%esi
movzbl -0x11(%rbp),%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
mov    $0x8,%esi
mov    $0xd0,%edx
call   1030 <CodecRegWrite@plt>
mov    -0x4(%rbp),%edi
mov    $0x7,%esi
movzbl -0xe(%rbp),%edx
call   1030 <CodecRegWrite@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<AIC31SampleRateConfig>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
mov    %edx,%eax
mov    %edi,%ebx
mov    $0x780,%ebp
mov    $0x20,%r15b
mov    $0xa,%r14b
cmp    $0x5dbf,%edx
jle    1160 <AIC31SampleRateConfig+0x40>
cmp    $0xac43,%eax
jle    1189 <AIC31SampleRateConfig+0x69>
cmp    $0xac44,%eax
je     11bb <AIC31SampleRateConfig+0x9b>
cmp    $0xbb80,%eax
je     11d9 <AIC31SampleRateConfig+0xb9>
cmp    $0x17700,%eax
je     11d9 <AIC31SampleRateConfig+0xb9>
jmp    11d1 <AIC31SampleRateConfig+0xb1>
cmp    $0x3e7f,%eax
jg     119e <AIC31SampleRateConfig+0x7e>
mov    $0xaa,%edx
cmp    $0x1f40,%eax
je     11db <AIC31SampleRateConfig+0xbb>
cmp    $0x2b11,%eax
jne    11d1 <AIC31SampleRateConfig+0xb1>
mov    $0x1490,%ebp
mov    $0x1c,%r15b
mov    $0x66,%edx
jmp    11c5 <AIC31SampleRateConfig+0xa5>
cmp    $0x5dc0,%eax
je     1197 <AIC31SampleRateConfig+0x77>
cmp    $0x7d00,%eax
jne    11d1 <AIC31SampleRateConfig+0xb1>
mov    $0x22,%edx
jmp    11db <AIC31SampleRateConfig+0xbb>
cmp    $0x3e80,%eax
je     11ca <AIC31SampleRateConfig+0xaa>
cmp    $0x5622,%eax
jne    11d1 <AIC31SampleRateConfig+0xb1>
mov    $0x1490,%ebp
mov    $0x1c,%r15b
mov    $0x22,%edx
jmp    11c5 <AIC31SampleRateConfig+0xa5>
mov    $0x1490,%ebp
mov    $0x1c,%r15b
xor    %edx,%edx
mov    $0x8a,%r14b
jmp    11db <AIC31SampleRateConfig+0xbb>
mov    $0x44,%edx
jmp    11db <AIC31SampleRateConfig+0xbb>
mov    $0x1490,%ebp
mov    $0x1c,%r15b
xor    %edx,%edx
and    %esi,%edx
mov    %ebx,%edi
mov    $0x2,%esi
call   1030 <CodecRegWrite@plt>
mov    %ebx,%edi
mov    $0x3,%esi
mov    $0x82,%edx
call   1030 <CodecRegWrite@plt>
mov    %ebx,%edi
mov    $0x66,%esi
mov    $0x8,%edx
call   1030 <CodecRegWrite@plt>
mov    %ebx,%edi
mov    $0x65,%esi
mov    $0x1,%edx
call   1040 <CodecRegBitClr@plt>
mov    %ebx,%edi
mov    $0x62,%esi
mov    $0x20,%edx
call   1030 <CodecRegWrite@plt>
movzbl %r15b,%edx
mov    %ebx,%edi
mov    $0x4,%esi
call   1030 <CodecRegWrite@plt>
mov    %ebp,%edx
shr    $0x6,%edx
mov    %ebx,%edi
mov    $0x5,%esi
call   1030 <CodecRegWrite@plt>
shl    $0x2,%bpl
movzbl %bpl,%edx
mov    %ebx,%edi
mov    $0x6,%esi
call   1030 <CodecRegWrite@plt>
mov    %ebx,%edi
mov    $0xb,%esi
mov    $0x1,%edx
call   1030 <CodecRegWrite@plt>
mov    %ebx,%edi
mov    $0x8,%esi
mov    $0xd0,%edx
call   1030 <CodecRegWrite@plt>
movzbl %r14b,%edx
mov    %ebx,%edi
mov    $0x7,%esi
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
jmp    1030 <CodecRegWrite@plt>

LLVM IR (-O0):
define void @AIC31SampleRateConfig(i32 %0, i32 %1, i32 %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i8
%8 = alloca i8
%9 = alloca i8
%10 = alloca i8
%11 = alloca i8
%12 = alloca i8
%13 = alloca i16
store i32 %0, i32* %4
store i32 %1, i32* %5
store i32 %2, i32* %6
store i8 10, i8* %8
store i8 2, i8* %10
store i8 1, i8* %11
store i8 7, i8* %12
store i16 5264, i16* %13
%14 = load i32, i32* %6
switch i32 %14, label %24 [
i32 8000, label %15
i32 11025, label %16
i32 16000, label %17
i32 22050, label %18
i32 24000, label %19
i32 32000, label %20
i32 44100, label %21
i32 48000, label %22
i32 96000, label %23
]
15: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 -86, i8* %7
br label %25
16: ; preds = %3
store i8 102, i8* %7
store i8 -118, i8* %8
br label %25
17: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 68, i8* %7
br label %25
18: ; preds = %3
store i8 34, i8* %7
store i8 -118, i8* %8
br label %25
19: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 34, i8* %7
br label %25
20: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 34, i8* %7
br label %25
21: ; preds = %3
store i8 -118, i8* %8
store i8 0, i8* %7
br label %25
22: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 0, i8* %7
br label %25
23: ; preds = %3
store i8 8, i8* %12
store i16 1920, i16* %13
store i8 0, i8* %7
br label %25
24: ; preds = %3
store i8 0, i8* %7
br label %25
25: ; preds = %24, %23, %22, %21, %20, %19, %18, %17, %16, %15
%26 = load i32, i32* %5
%27 = load i8, i8* %7
%28 = zext i8 %27 to i32
%29 = and i32 %26, %28
%30 = trunc i32 %29 to i8
store i8 %30, i8* %9
%31 = load i32, i32* %4
%32 = load i8, i8* %9
%33 = call i32 @CodecRegWrite(i32 %31, i32 2, i8 zeroext %32)
%34 = load i32, i32* %4
%35 = load i8, i8* %10
%36 = zext i8 %35 to i32
%37 = or i32 128, %36
%38 = trunc i32 %37 to i8
%39 = call i32 @CodecRegWrite(i32 %34, i32 3, i8 zeroext %38)
%40 = load i32, i32* %4
%41 = call i32 @CodecRegWrite(i32 %40, i32 102, i8 zeroext 8)
%42 = load i32, i32* %4
%43 = call i32 @CodecRegBitClr(i32 %42, i32 101, i32 1)
%44 = load i32, i32* %4
%45 = call i32 @CodecRegWrite(i32 %44, i32 98, i8 zeroext 32)
%46 = load i32, i32* %4
%47 = load i8, i8* %12
%48 = zext i8 %47 to i32
%49 = shl i32 %48, 2
%50 = trunc i32 %49 to i8
%51 = call i32 @CodecRegWrite(i32 %46, i32 4, i8 zeroext %50)
%52 = load i32, i32* %4
%53 = load i16, i16* %13
%54 = zext i16 %53 to i32
%55 = ashr i32 %54, 6
%56 = and i32 %55, 255
%57 = trunc i32 %56 to i8
%58 = call i32 @CodecRegWrite(i32 %52, i32 5, i8 zeroext %57)
%59 = load i32, i32* %4
%60 = load i16, i16* %13
%61 = zext i16 %60 to i32
%62 = and i32 %61, 63
%63 = shl i32 %62, 2
%64 = trunc i32 %63 to i8
%65 = call i32 @CodecRegWrite(i32 %59, i32 6, i8 zeroext %64)
%66 = load i32, i32* %4
%67 = load i8, i8* %11
%68 = call i32 @CodecRegWrite(i32 %66, i32 11, i8 zeroext %67)
%69 = load i32, i32* %4
%70 = call i32 @CodecRegWrite(i32 %69, i32 8, i8 zeroext -48)
%71 = load i32, i32* %4
%72 = load i8, i8* %8
%73 = call i32 @CodecRegWrite(i32 %71, i32 7, i8 zeroext %72)
ret void
}

LLVM IR (-O2):
define void @AIC31SampleRateConfig(i32 %0, i32 %1, i32 %2) {
switch i32 %2, label %12 [
i32 8000, label %13
i32 11025, label %4
i32 16000, label %5
i32 22050, label %6
i32 24000, label %7
i32 32000, label %8
i32 44100, label %9
i32 48000, label %10
i32 96000, label %11
]
4: ; preds = %3
br label %13
5: ; preds = %3
br label %13
6: ; preds = %3
br label %13
7: ; preds = %3
br label %13
8: ; preds = %3
br label %13
9: ; preds = %3
br label %13
10: ; preds = %3
br label %13
11: ; preds = %3
br label %13
12: ; preds = %3
br label %13
13: ; preds = %3, %12, %11, %10, %9, %8, %7, %6, %5, %4
%14 = phi i8 [ 10, %12 ], [ 10, %11 ], [ 10, %10 ], [ -118, %9 ], [ 10, %8 ], [ 10, %7 ], [ -118, %6 ], [ 10, %5 ], [ -118, %4 ], [ 10, %3 ]
%15 = phi i32 [ 0, %12 ], [ 0, %11 ], [ 0, %10 ], [ 0, %9 ], [ 34, %8 ], [ 34, %7 ], [ 34, %6 ], [ 68, %5 ], [ 102, %4 ], [ 170, %3 ]
%16 = phi i8 [ 28, %12 ], [ 32, %11 ], [ 32, %10 ], [ 28, %9 ], [ 32, %8 ], [ 32, %7 ], [ 28, %6 ], [ 32, %5 ], [ 28, %4 ], [ 32, %3 ]
%17 = phi i32 [ 5264, %12 ], [ 1920, %11 ], [ 1920, %10 ], [ 5264, %9 ], [ 1920, %8 ], [ 1920, %7 ], [ 5264, %6 ], [ 1920, %5 ], [ 5264, %4 ], [ 1920, %3 ]
%18 = and i32 %15, %1
%19 = trunc i32 %18 to i8
%20 = tail call i32 @CodecRegWrite(i32 %0, i32 2, i8 zeroext %19)
%21 = tail call i32 @CodecRegWrite(i32 %0, i32 3, i8 zeroext -126)
%22 = tail call i32 @CodecRegWrite(i32 %0, i32 102, i8 zeroext 8)
%23 = tail call i32 @CodecRegBitClr(i32 %0, i32 101, i32 1)
%24 = tail call i32 @CodecRegWrite(i32 %0, i32 98, i8 zeroext 32)
%25 = tail call i32 @CodecRegWrite(i32 %0, i32 4, i8 zeroext %16)
%26 = lshr i32 %17, 6
%27 = trunc i32 %26 to i8
%28 = tail call i32 @CodecRegWrite(i32 %0, i32 5, i8 zeroext %27)
%29 = trunc i32 %17 to i8
%30 = shl i8 %29, 2
%31 = tail call i32 @CodecRegWrite(i32 %0, i32 6, i8 zeroext %30)
%32 = tail call i32 @CodecRegWrite(i32 %0, i32 11, i8 zeroext 1)
%33 = tail call i32 @CodecRegWrite(i32 %0, i32 8, i8 zeroext -48)
%34 = tail call i32 @CodecRegWrite(i32 %0, i32 7, i8 zeroext %14)
ret void
}