void IntEnable(unsigned long ulInterrupt) {
  ;
  if (ulInterrupt == 4) {
    (*((volatile unsigned long *)(0xE000ED24))) |= 0x00010000;
  } else if (ulInterrupt == 5) {
    (*((volatile unsigned long *)(0xE000ED24))) |= 0x00020000;
  } else if (ulInterrupt == 6) {
    (*((volatile unsigned long *)(0xE000ED24))) |= 0x00040000;
  } else if (ulInterrupt == 15) {
    (*((volatile unsigned long *)(0xE000E010))) |= 0x00000002;
  } else if ((ulInterrupt >= 16) && (ulInterrupt <= 47)) {
    (*((volatile unsigned long *)(0xE000E100))) = 1 << (ulInterrupt - 16);
  } else if (ulInterrupt >= 48) {
    (*((volatile unsigned long *)(0xE000E104))) = 1 << (ulInterrupt - 48);
  }
}


x86 assembly (clang, -O0):
<IntEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
cmpq   $0x4,-0x8(%rbp)
jne    112f <IntEnable+0x2f>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
or     $0x10000,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    1218 <IntEnable+0x118>
cmpq   $0x5,-0x8(%rbp)
jne    1156 <IntEnable+0x56>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
or     $0x20000,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    1213 <IntEnable+0x113>
cmpq   $0x6,-0x8(%rbp)
jne    117d <IntEnable+0x7d>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
or     $0x40000,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    120e <IntEnable+0x10e>
cmpq   $0xf,-0x8(%rbp)
jne    11a1 <IntEnable+0xa1>
mov    $0xe000e010,%eax
mov    (%rax),%rcx
or     $0x2,%rcx
mov    $0xe000e010,%eax
mov    %rcx,(%rax)
jmp    1209 <IntEnable+0x109>
cmpq   $0x10,-0x8(%rbp)
jb     11d8 <IntEnable+0xd8>
cmpq   $0x2f,-0x8(%rbp)
ja     11d8 <IntEnable+0xd8>
mov    -0x8(%rbp),%rax
sub    $0x10,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0xe000e100,%eax
mov    %rcx,(%rax)
jmp    1204 <IntEnable+0x104>
cmpq   $0x30,-0x8(%rbp)
jb     11ff <IntEnable+0xff>
mov    -0x8(%rbp),%rax
sub    $0x30,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0xe000e104,%eax
mov    %rcx,(%rax)
jmp    1204 <IntEnable+0x104>
jmp    1209 <IntEnable+0x109>
jmp    120e <IntEnable+0x10e>
jmp    1213 <IntEnable+0x113>
jmp    1218 <IntEnable+0x118>
pop    %rbp
ret

x86 assembly (clang, -O2):
<IntEnable>:
lea    -0x4(%rdi),%rax
cmp    $0xb,%rax
ja     114f <IntEnable+0x4f>
lea    0xeef(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    $0xe000ed24,%eax
orq    $0x10000,(%rax)
ret
mov    $0xe000ed24,%eax
orq    $0x20000,(%rax)
ret
mov    $0xe000ed24,%eax
orq    $0x40000,(%rax)
ret
mov    $0xe000ed24,%eax
orq    $0x2,-0xd14(%rax)
02
ret
lea    -0x10(%rdi),%rax
cmp    $0x1f,%rax
ja     1175 <IntEnable+0x75>
add    $0xf0,%dil
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
cltq
mov    $0xe000ed24,%ecx
mov    %rax,-0xc24(%rcx)
ret
cmp    $0x30,%rdi
jb     1196 <IntEnable+0x96>
add    $0xd0,%dil
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
cltq
mov    $0xe000ed24,%ecx
mov    %rax,-0xc20(%rcx)
ret

LLVM IR (-O0):
define void @IntEnable(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = icmp eq i64 %3, 4
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%7 = or i64 %6, 65536
store volatile i64 %7, i64* inttoptr (i64 3758157092 to i64*)
br label %52
8: ; preds = %1
%9 = load i64, i64* %2
%10 = icmp eq i64 %9, 5
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%13 = or i64 %12, 131072
store volatile i64 %13, i64* inttoptr (i64 3758157092 to i64*)
br label %51
14: ; preds = %8
%15 = load i64, i64* %2
%16 = icmp eq i64 %15, 6
br i1 %16, label %17, label %20
17: ; preds = %14
%18 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%19 = or i64 %18, 262144
store volatile i64 %19, i64* inttoptr (i64 3758157092 to i64*)
br label %50
20: ; preds = %14
%21 = load i64, i64* %2
%22 = icmp eq i64 %21, 15
br i1 %22, label %23, label %26
23: ; preds = %20
%24 = load volatile i64, i64* inttoptr (i64 3758153744 to i64*)
%25 = or i64 %24, 2
store volatile i64 %25, i64* inttoptr (i64 3758153744 to i64*)
br label %49
26: ; preds = %20
%27 = load i64, i64* %2
%28 = icmp uge i64 %27, 16
br i1 %28, label %29, label %38
29: ; preds = %26
%30 = load i64, i64* %2
%31 = icmp ule i64 %30, 47
br i1 %31, label %32, label %38
32: ; preds = %29
%33 = load i64, i64* %2
%34 = sub i64 %33, 16
%35 = trunc i64 %34 to i32
%36 = shl i32 1, %35
%37 = sext i32 %36 to i64
store volatile i64 %37, i64* inttoptr (i64 3758153984 to i64*)
br label %48
38: ; preds = %29, %26
%39 = load i64, i64* %2
%40 = icmp uge i64 %39, 48
br i1 %40, label %41, label %47
41: ; preds = %38
%42 = load i64, i64* %2
%43 = sub i64 %42, 48
%44 = trunc i64 %43 to i32
%45 = shl i32 1, %44
%46 = sext i32 %45 to i64
store volatile i64 %46, i64* inttoptr (i64 3758153988 to i64*)
br label %47
47: ; preds = %41, %38
br label %48
48: ; preds = %47, %32
br label %49
49: ; preds = %48, %23
br label %50
50: ; preds = %49, %17
br label %51
51: ; preds = %50, %11
br label %52
52: ; preds = %51, %5
ret void
}

LLVM IR (-O2):
define void @IntEnable(i64 %0) {
switch i64 %0, label %14 [
i64 4, label %2
i64 5, label %5
i64 6, label %8
i64 15, label %11
]
2: ; preds = %1
%3 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%4 = or i64 %3, 65536
store volatile i64 %4, i64* inttoptr (i64 3758157092 to i64*)
br label %29
5: ; preds = %1
%6 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%7 = or i64 %6, 131072
store volatile i64 %7, i64* inttoptr (i64 3758157092 to i64*)
br label %29
8: ; preds = %1
%9 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%10 = or i64 %9, 262144
store volatile i64 %10, i64* inttoptr (i64 3758157092 to i64*)
br label %29
11: ; preds = %1
%12 = load volatile i64, i64* inttoptr (i64 3758153744 to i64*)
%13 = or i64 %12, 2
store volatile i64 %13, i64* inttoptr (i64 3758153744 to i64*)
br label %29
14: ; preds = %1
%15 = add i64 %0, -16
%16 = icmp ult i64 %15, 32
br i1 %16, label %17, label %22
17: ; preds = %14
%18 = trunc i64 %0 to i32
%19 = add nsw i32 %18, -16
%20 = shl nuw i32 1, %19
%21 = sext i32 %20 to i64
store volatile i64 %21, i64* inttoptr (i64 3758153984 to i64*)
br label %29
22: ; preds = %14
%23 = icmp ugt i64 %0, 47
br i1 %23, label %24, label %29
24: ; preds = %22
%25 = trunc i64 %0 to i32
%26 = add i32 %25, -48
%27 = shl nuw i32 1, %26
%28 = sext i32 %27 to i64
store volatile i64 %28, i64* inttoptr (i64 3758153988 to i64*)
br label %29
29: ; preds = %5, %11, %22, %24, %17, %8, %2
ret void
}