int ea_mode(int opcode) {
  switch (opcode & 0x38) {
  case 0x00:
    return 0;
  case 0x08:
    return 1;
  case 0x10:
    return 2;
  case 0x18:
    return 3;
  case 0x20:
    return 4;
  case 0x28:
    return 5;
  case 0x30:
    return 6;
  case 0x38:
    switch (opcode & 7) {
    case 0:
      return 7;
    case 1:
      return 8;
    case 2:
      return 9;
    case 3:
      return 10;
    case 4:
      return 11;
    default:
      return -1;
    }
  default:
    return -1;
  }
}


x86 assembly (clang, -O0):
<ea_mode>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
and    $0x38,%eax
mov    %rax,-0x10(%rbp)
sub    $0x38,%eax
ja     11f1 <ea_mode+0xf1>
mov    -0x10(%rbp),%rax
lea    0xedb(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x0,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x1,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x2,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x3,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x4,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x5,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x6,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
mov    -0x8(%rbp),%eax
and    $0x7,%eax
mov    %rax,-0x18(%rbp)
sub    $0x4,%eax
ja     11e5 <ea_mode+0xe5>
mov    -0x18(%rbp),%rax
lea    0xf44(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x7,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x8,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0x9,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0xa,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0xb,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0xffffffff,-0x4(%rbp)
jmp    11f8 <ea_mode+0xf8>
movl   $0xffffffff,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ea_mode>:
mov    %edi,%ecx
shr    $0x3,%ecx
and    $0x7,%ecx
and    $0x7,%edi
lea    0x7(%rdi),%edx
cmp    $0x5,%edi
mov    $0xffffffff,%eax
cmovb  %edx,%eax
cmp    $0x7,%ecx
cmovne %ecx,%eax
ret

LLVM IR (-O0):
define i32 @ea_mode(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = and i32 %4, 56
switch i32 %5, label %22 [
i32 0, label %6
i32 8, label %7
i32 16, label %8
i32 24, label %9
i32 32, label %10
i32 40, label %11
i32 48, label %12
i32 56, label %13
]
6: ; preds = %1
store i32 0, i32* %2
br label %23
7: ; preds = %1
store i32 1, i32* %2
br label %23
8: ; preds = %1
store i32 2, i32* %2
br label %23
9: ; preds = %1
store i32 3, i32* %2
br label %23
10: ; preds = %1
store i32 4, i32* %2
br label %23
11: ; preds = %1
store i32 5, i32* %2
br label %23
12: ; preds = %1
store i32 6, i32* %2
br label %23
13: ; preds = %1
%14 = load i32, i32* %3
%15 = and i32 %14, 7
switch i32 %15, label %21 [
i32 0, label %16
i32 1, label %17
i32 2, label %18
i32 3, label %19
i32 4, label %20
]
16: ; preds = %13
store i32 7, i32* %2
br label %23
17: ; preds = %13
store i32 8, i32* %2
br label %23
18: ; preds = %13
store i32 9, i32* %2
br label %23
19: ; preds = %13
store i32 10, i32* %2
br label %23
20: ; preds = %13
store i32 11, i32* %2
br label %23
21: ; preds = %13
store i32 -1, i32* %2
br label %23
22: ; preds = %1
store i32 -1, i32* %2
br label %23
23: ; preds = %22, %21, %20, %19, %18, %17, %16, %12, %11, %10, %9, %8, %7, %6
%24 = load i32, i32* %2
ret i32 %24
}

LLVM IR (-O2):
define i32 @ea_mode(i32 %0) {
%2 = lshr i32 %0, 3
%3 = and i32 %2, 7
%4 = icmp eq i32 %3, 7
%5 = and i32 %0, 7
%6 = icmp ult i32 %5, 5
%7 = add nuw nsw i32 %5, 7
%8 = select i1 %6, i32 %7, i32 -1
%9 = select i1 %4, i32 %8, i32 %3
ret i32 %9
}