xunge/DecIR huggingface dataset:
/* Variables and functions */
int /*<<< orphan*/ execve(char *, int /*<<< orphan*/ *, int /*<<< orphan*/ *);
void get_shell() { execve("/bin/sh", NULL, NULL); }


x86 assembly (clang, -O0):
<get_shell>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
xor    %eax,%eax
mov    %eax,%edx
mov    %rdx,%rsi
call   1030 <execve@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<get_shell>:
lea    0xee9(%rip),%rdi
xor    %esi,%esi
xor    %edx,%edx
jmp    1030 <execve@plt>

LLVM IR (-O0):
@.str = [8 x i8] c"/bin/sh\00"
define void @get_shell() {
%1 = call i32 @execve(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32* null, i32* null)
ret void
}

LLVM IR (-O2):
@.str = [8 x i8] c"/bin/sh\00"
define void @get_shell() {
%1 = tail call i32 @execve(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i32* null, i32* null)
ret void
}
/* Variables and functions */
int _ada_use_c2phc4c(int, int *, int *, double *, int /*<<< orphan*/);
int padcon_quaddobl_initialize_homotopy(int verbose, int homo) {
  int fail;
  int precision = 2;
  int pars[2];
  double *c;
  pars[0] = verbose;
  pars[1] = homo;
  fail = _ada_use_c2phc4c(860, &precision, pars, c, 0);
  return fail;
}


x86 assembly (clang, -O0):
<padcon_quaddobl_initialize_homotopy>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
movl   $0x2,-0x10(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
lea    -0x18(%rbp),%rdx
mov    -0x20(%rbp),%rcx
mov    $0x35c,%edi
lea    -0x10(%rbp),%rsi
xor    %r8d,%r8d
call   1030 <_ada_use_c2phc4c@plt>
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<padcon_quaddobl_initialize_homotopy>:
sub    $0x18,%rsp
movl   $0x2,0xc(%rsp)
mov    %edi,0x10(%rsp)
mov    %esi,0x14(%rsp)
lea    0xc(%rsp),%rsi
lea    0x10(%rsp),%rdx
mov    $0x35c,%edi
xor    %r8d,%r8d
call   1030 <_ada_use_c2phc4c@plt>
add    $0x18,%rsp
ret

LLVM IR (-O0):
define i32 @padcon_quaddobl_initialize_homotopy(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca [2 x i32]
%8 = alloca double*
store i32 %0, i32* %3
store i32 %1, i32* %4
store i32 2, i32* %6
%9 = load i32, i32* %3
%10 = getelementptr inbounds [2 x i32], [2 x i32]* %7, i64 0, i64 0
store i32 %9, i32* %10
%11 = load i32, i32* %4
%12 = getelementptr inbounds [2 x i32], [2 x i32]* %7, i64 0, i64 1
store i32 %11, i32* %12
%13 = getelementptr inbounds [2 x i32], [2 x i32]* %7, i64 0, i64 0
%14 = load double*, double** %8
%15 = call i32 @_ada_use_c2phc4c(i32 860, i32* %6, i32* %13, double* %14, i32 0)
store i32 %15, i32* %5
%16 = load i32, i32* %5
ret i32 %16
}

LLVM IR (-O2):
define i32 @padcon_quaddobl_initialize_homotopy(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca [2 x i32]
%5 = bitcast i32* %3 to i8*
store i32 2, i32* %3
%6 = bitcast [2 x i32]* %4 to i8*
%7 = getelementptr inbounds [2 x i32], [2 x i32]* %4, i64 0, i64 0
store i32 %0, i32* %7
%8 = getelementptr inbounds [2 x i32], [2 x i32]* %4, i64 0, i64 1
store i32 %1, i32* %8
%9 = call i32 @_ada_use_c2phc4c(i32 860, i32* %3, i32* %7, double* undef, i32 0)
ret i32 %9
}
void x_shutdown(struct sc *sc) {}


x86 assembly (clang, -O0):
<x_shutdown>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<x_shutdown>:
ret

LLVM IR (-O0):
%struct.sc = type opaque
define void @x_shutdown(%struct.sc* %0) {
%2 = alloca %struct.sc*
store %struct.sc* %0, %struct.sc** %2
ret void
}

LLVM IR (-O2):
%struct.sc = type opaque
define void @x_shutdown(%struct.sc* nocapture %0) {
ret void
}
__attribute__((always_)) void native_halt(void) {
  asm volatile("hlt" : : : "memory");
}


x86 assembly (clang, -O0):
<native_halt>:
push   %rbp
mov    %rsp,%rbp
hlt
pop    %rbp
ret

x86 assembly (clang, -O2):
<native_halt>:
hlt
ret

LLVM IR (-O0):
define void @native_halt() {
ret void
}

LLVM IR (-O2):
define void @native_halt() {
tail call void asm sideeffect "hlt", "~{memory},~{dirflag},~{fpsr},~{flags}"()
ret void
}
/* Variables and functions */
scalar_t__ isspace(char);
size_t strlen(char *);
void trim_back(char *line) {
  size_t n = strlen(line);
  while (n >= 0 && isspace(line[n]))
    line[n--] = '\0';
}


x86 assembly (clang, -O0):
<trim_back>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <strlen@plt>
mov    %rax,-0x10(%rbp)
xor    %eax,%eax
cmpq   $0x0,-0x10(%rbp)
mov    %al,-0x11(%rbp)
jb     1164 <trim_back+0x44>
mov    -0x8(%rbp),%rax
mov    -0x10(%rbp),%rcx
movsbl (%rax,%rcx,1),%edi
call   1040 <isspace@plt>
cmp    $0x0,%rax
setne  %al
mov    %al,-0x11(%rbp)
mov    -0x11(%rbp),%al
test   $0x1,%al
jne    1174 <trim_back+0x54>
jmp    1190 <trim_back+0x70>
mov    -0x8(%rbp),%rax
mov    -0x10(%rbp),%rcx
mov    %rcx,%rdx
add    $0xffffffffffffffff,%rdx
mov    %rdx,-0x10(%rbp)
movb   $0x0,(%rax,%rcx,1)
jmp    1139 <trim_back+0x19>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<trim_back>:
push   %r14
push   %rbx
push   %rax
mov    %rdi,%rbx
call   1030 <strlen@plt>
mov    %rax,%r14
movsbl (%rbx,%rax,1),%edi
call   1040 <isspace@plt>
test   %rax,%rax
je     1155 <trim_back+0x35>
add    %r14,%rbx
movb   $0x0,(%rbx)
movsbl -0x1(%rbx),%edi
add    $0xffffffffffffffff,%rbx
call   1040 <isspace@plt>
test   %rax,%rax
jne    1140 <trim_back+0x20>
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define void @trim_back(i8* %0) {
%2 = alloca i8*
%3 = alloca i64
store i8* %0, i8** %2
%4 = load i8*, i8** %2
%5 = call i64 @strlen(i8* %4)
store i64 %5, i64* %3
br label %6
6: ; preds = %18, %1
%7 = load i64, i64* %3
%8 = icmp uge i64 %7, 0
br i1 %8, label %9, label %16
9: ; preds = %6
%10 = load i8*, i8** %2
%11 = load i64, i64* %3
%12 = getelementptr inbounds i8, i8* %10, i64 %11
%13 = load i8, i8* %12
%14 = call i64 @isspace(i8 signext %13)
%15 = icmp ne i64 %14, 0
br label %16
16: ; preds = %9, %6
%17 = phi i1 [ false, %6 ], [ %15, %9 ]
br i1 %17, label %18, label %23
18: ; preds = %16
%19 = load i8*, i8** %2
%20 = load i64, i64* %3
%21 = add i64 %20, -1
store i64 %21, i64* %3
%22 = getelementptr inbounds i8, i8* %19, i64 %20
store i8 0, i8* %22
br label %6
23: ; preds = %16
ret void
}

LLVM IR (-O2):
define void @trim_back(i8* nocapture %0) {
%2 = tail call i64 @strlen(i8* dereferenceable(1) %0)
%3 = getelementptr inbounds i8, i8* %0, i64 %2
%4 = load i8, i8* %3
%5 = tail call i64 @isspace(i8 signext %4)
%6 = icmp eq i64 %5, 0
br i1 %6, label %15, label %7
7: ; preds = %1, %7
%8 = phi i8* [ %11, %7 ], [ %3, %1 ]
%9 = phi i64 [ %10, %7 ], [ %2, %1 ]
%10 = add i64 %9, -1
store i8 0, i8* %8
%11 = getelementptr inbounds i8, i8* %0, i64 %10
%12 = load i8, i8* %11
%13 = tail call i64 @isspace(i8 signext %12)
%14 = icmp eq i64 %13, 0
br i1 %14, label %15, label %7
15: ; preds = %7, %1
ret void
}
void init_pic(void) {
  asm volatile("outb %%al, %%dx" ::"d"(0x20), "a"(0x11));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0xA0), "a"(0x11));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0x21), "a"(0x20));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0xA1), "a"(0x70));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0x21), "a"(0x04));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0xA1), "a"(0x02));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0x21), "a"(0x01));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0xA1), "a"(0x01));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0x21), "a"(0x0));
  ;
  asm volatile("outb %%al, %%dx" ::"d"(0xA1), "a"(0x0));
  ;
}


x86 assembly (clang, -O0):
<init_pic>:
push   %rbp
mov    %rsp,%rbp
mov    $0x20,%edx
mov    $0x11,%eax
out    %al,(%dx)
mov    $0xa0,%edx
mov    $0x11,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x20,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x70,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x4,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x2,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x1,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x1,%eax
out    %al,(%dx)
mov    $0x21,%edx
xor    %eax,%eax
out    %al,(%dx)
mov    $0xa1,%edx
xor    %eax,%eax
out    %al,(%dx)
pop    %rbp
ret

x86 assembly (clang, -O2):
<init_pic>:
mov    $0x20,%edx
mov    $0x11,%eax
out    %al,(%dx)
mov    $0xa0,%edx
mov    $0x11,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x20,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x70,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x4,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x2,%eax
out    %al,(%dx)
mov    $0x21,%edx
mov    $0x1,%eax
out    %al,(%dx)
mov    $0xa1,%edx
mov    $0x1,%eax
out    %al,(%dx)
mov    $0x21,%edx
xor    %eax,%eax
out    %al,(%dx)
mov    $0xa1,%edx
xor    %eax,%eax
out    %al,(%dx)
ret

LLVM IR (-O0):
define void @init_pic() {
ret void
}

LLVM IR (-O2):
define void @init_pic() {
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 32, i32 17)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 160, i32 17)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 33, i32 32)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 161, i32 112)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 33, i32 4)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 161, i32 2)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 33, i32 1)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 161, i32 1)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 33, i32 0)
tail call void asm sideeffect "outb %al, %dx", "{dx},{ax},~{dirflag},~{fpsr},~{flags}"(i32 161, i32 0)
ret void
}
void INT_Excep_PERIB_INTB184(void) {}


x86 assembly (clang, -O0):
<INT_Excep_PERIB_INTB184>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<INT_Excep_PERIB_INTB184>:
ret

LLVM IR (-O0):
define void @INT_Excep_PERIB_INTB184() {
ret void
}

LLVM IR (-O2):
define void @INT_Excep_PERIB_INTB184() {
ret void
}
unsigned long potato_uart_divisor(unsigned long proc_freq,
                                  unsigned long uart_freq) {
  return proc_freq / (uart_freq * 16) - 1;
}


x86 assembly (clang, -O0):
<potato_uart_divisor>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rax
mov    -0x10(%rbp),%rcx
shl    $0x4,%rcx
xor    %edx,%edx
div    %rcx
sub    $0x1,%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<potato_uart_divisor>:
mov    %rdi,%rax
shl    $0x4,%rsi
mov    %rdi,%rcx
or     %rsi,%rcx
shr    $0x20,%rcx
je     111d <potato_uart_divisor+0x1d>
xor    %edx,%edx
div    %rsi
add    $0xffffffffffffffff,%rax
ret
xor    %edx,%edx
div    %esi
add    $0xffffffffffffffff,%rax
ret

LLVM IR (-O0):
define i64 @potato_uart_divisor(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%5 = load i64, i64* %3
%6 = load i64, i64* %4
%7 = mul i64 %6, 16
%8 = udiv i64 %5, %7
%9 = sub i64 %8, 1
ret i64 %9
}

LLVM IR (-O2):
define i64 @potato_uart_divisor(i64 %0, i64 %1) {
%3 = shl i64 %1, 4
%4 = udiv i64 %0, %3
%5 = add i64 %4, -1
ret i64 %5
}
/* Variables and functions */
scalar_t__ dcac_acl_ops(int, int, int, char const *, char const *);
int dcac_set_file_mdacl(const char *file, const char *acl) {
  return (int)dcac_acl_ops(28, -1, -1, acl, file);
}


x86 assembly (clang, -O0):
<dcac_set_file_mdacl>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x10(%rbp),%rcx
mov    -0x8(%rbp),%r8
mov    $0x1c,%edi
mov    $0xffffffff,%edx
mov    %edx,%esi
call   1030 <dcac_acl_ops@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<dcac_set_file_mdacl>:
mov    %rsi,%rcx
mov    %rdi,%r8
mov    $0x1c,%edi
mov    $0xffffffff,%esi
mov    $0xffffffff,%edx
jmp    1030 <dcac_acl_ops@plt>

LLVM IR (-O0):
define i32 @dcac_set_file_mdacl(i8* %0, i8* %1) {
%3 = alloca i8*
%4 = alloca i8*
store i8* %0, i8** %3
store i8* %1, i8** %4
%5 = load i8*, i8** %4
%6 = load i8*, i8** %3
%7 = call i64 @dcac_acl_ops(i32 28, i32 -1, i32 -1, i8* %5, i8* %6)
%8 = trunc i64 %7 to i32
ret i32 %8
}

LLVM IR (-O2):
define i32 @dcac_set_file_mdacl(i8* %0, i8* %1) {
%3 = tail call i64 @dcac_acl_ops(i32 28, i32 -1, i32 -1, i8* %1, i8* %0)
%4 = trunc i64 %3 to i32
ret i32 %4
}
void gtk_calendar_new() {}


x86 assembly (clang, -O0):
<gtk_calendar_new>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gtk_calendar_new>:
ret

LLVM IR (-O0):
define void @gtk_calendar_new() {
ret void
}

LLVM IR (-O2):
define void @gtk_calendar_new() {
ret void
}
int lines(char input[]) { return 0; }


x86 assembly (clang, -O0):
<lines>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<lines>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @lines(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
ret i32 0
}

LLVM IR (-O2):
define i32 @lines(i8* nocapture readnone %0) {
ret i32 0
}
/* Variables and functions */
one() { return 1; }


x86 assembly (clang, -O0):
<one>:
push   %rbp
mov    %rsp,%rbp
mov    $0x1,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<one>:
mov    $0x1,%eax
ret

LLVM IR (-O0):
define i32 @one() {
ret i32 1
}

LLVM IR (-O2):
define i32 @one() {
ret i32 1
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *);
int pa_strbuf_puts() {
  printf("NOT IMPLEMENTED:"
         "pa_strbuf_puts"
         "\n");
}


x86 assembly (clang, -O0):
<pa_strbuf_puts>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
lea    0xee1(%rip),%rdi
call   1030 <printf@plt>
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<pa_strbuf_puts>:
lea    0xee9(%rip),%rdi
jmp    1030 <puts@plt>

LLVM IR (-O0):
@.str = [32 x i8] c"NOT IMPLEMENTED:pa_strbuf_puts\0A\00"
define i32 @pa_strbuf_puts() {
%1 = alloca i32
%2 = call i32 @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i64 0, i64 0))
%3 = load i32, i32* %1
ret i32 %3
}

LLVM IR (-O2):
@str = [31 x i8] c"NOT IMPLEMENTED:pa_strbuf_puts\00"
define i32 @pa_strbuf_puts() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([31 x i8], [31 x i8]* @str, i64 0, i64 0))
ret i32 undef
}
/* Variables and functions */
scalar_t__ isObstext(char *, int *);
scalar_t__ isVCHAR(char *, int *);
int isFieldvchar(char *request, int *cursor) {
  if (isObstext(request, cursor) || isVCHAR(request, cursor)) {
    return 1;
  }
  return 0;
}


x86 assembly (clang, -O0):
<isFieldvchar>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
call   1040 <isObstext@plt>
cmp    $0x0,%rax
jne    115e <isFieldvchar+0x3e>
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
call   1030 <isVCHAR@plt>
cmp    $0x0,%rax
je     116a <isFieldvchar+0x4a>
movl   $0x1,-0x4(%rbp)
jmp    1171 <isFieldvchar+0x51>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<isFieldvchar>:
push   %r14
push   %rbx
push   %rax
mov    %rsi,%r14
mov    %rdi,%rbx
call   1040 <isObstext@plt>
mov    %rax,%rcx
mov    $0x1,%eax
test   %rcx,%rcx
jne    1152 <isFieldvchar+0x32>
mov    %rbx,%rdi
mov    %r14,%rsi
call   1030 <isVCHAR@plt>
mov    %rax,%rcx
xor    %eax,%eax
test   %rcx,%rcx
setne  %al
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define i32 @isFieldvchar(i8* %0, i32* %1) {
%3 = alloca i32
%4 = alloca i8*
%5 = alloca i32*
store i8* %0, i8** %4
store i32* %1, i32** %5
%6 = load i8*, i8** %4
%7 = load i32*, i32** %5
%8 = call i64 @isObstext(i8* %6, i32* %7)
%9 = icmp ne i64 %8, 0
br i1 %9, label %15, label %10
10: ; preds = %2
%11 = load i8*, i8** %4
%12 = load i32*, i32** %5
%13 = call i64 @isVCHAR(i8* %11, i32* %12)
%14 = icmp ne i64 %13, 0
br i1 %14, label %15, label %16
15: ; preds = %10, %2
store i32 1, i32* %3
br label %17
16: ; preds = %10
store i32 0, i32* %3
br label %17
17: ; preds = %16, %15
%18 = load i32, i32* %3
ret i32 %18
}

LLVM IR (-O2):
define i32 @isFieldvchar(i8* %0, i32* %1) {
%3 = tail call i64 @isObstext(i8* %0, i32* %1)
%4 = icmp eq i64 %3, 0
br i1 %4, label %5, label %9
5: ; preds = %2
%6 = tail call i64 @isVCHAR(i8* %0, i32* %1)
%7 = icmp ne i64 %6, 0
%8 = zext i1 %7 to i32
br label %9
9: ; preds = %5, %2
%10 = phi i32 [ 1, %2 ], [ %8, %5 ]
ret i32 %10
}
/* Variables and functions */
int /*<<< orphan*/ _get_path();
int /*<<< orphan*/ asprintf(char **, char *, int /*<<< orphan*/, char *);
int /*<<< orphan*/ free(char *);
int /*<<< orphan*/ remove(char *);
int arch_delete(char *name) {
  char *filename;
  asprintf(&filename, "%s/%s.bas", _get_path(), name);
  remove(filename);
  free(filename);
  return 0;
}


x86 assembly (clang, -O0):
<arch_delete>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    $0x0,%al
call   1050 <_get_path@plt>
mov    %eax,%edx
mov    -0x8(%rbp),%rcx
lea    -0x10(%rbp),%rdi
lea    0xe9c(%rip),%rsi
call   1060 <asprintf@plt>
mov    -0x10(%rbp),%rdi
call   1040 <remove@plt>
mov    -0x10(%rbp),%rdi
call   1030 <free@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<arch_delete>:
push   %rbx
sub    $0x10,%rsp
mov    %rdi,%rbx
xor    %eax,%eax
call   1050 <_get_path@plt>
lea    0xeaa(%rip),%rsi
lea    0x8(%rsp),%rdi
mov    %eax,%edx
mov    %rbx,%rcx
call   1060 <asprintf@plt>
mov    0x8(%rsp),%rdi
call   1040 <remove@plt>
mov    0x8(%rsp),%rdi
call   1030 <free@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbx
ret

LLVM IR (-O0):
@.str = [10 x i8] c"%s/%s.bas\00"
define i32 @arch_delete(i8* %0) {
%2 = alloca i8*
%3 = alloca i8*
store i8* %0, i8** %2
%4 = call i32 (...) @_get_path()
%5 = load i8*, i8** %2
%6 = call i32 @asprintf(i8** %3, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i64 0, i64 0), i32 %4, i8* %5)
%7 = load i8*, i8** %3
%8 = call i32 @remove(i8* %7)
%9 = load i8*, i8** %3
%10 = call i32 @free(i8* %9)
ret i32 0
}

LLVM IR (-O2):
@.str = [10 x i8] c"%s/%s.bas\00"
define i32 @arch_delete(i8* %0) {
%2 = alloca i8*
%3 = bitcast i8** %2 to i8*
%4 = tail call i32 (...) @_get_path()
%5 = call i32 @asprintf(i8** %2, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i64 0, i64 0), i32 %4, i8* %0)
%6 = load i8*, i8** %2
%7 = call i32 @remove(i8* %6)
%8 = load i8*, i8** %2
%9 = call i32 @free(i8* %8)
ret i32 0
}
void set_ProcessID(unsigned char *pds, int id) { pds[5] = id; }


x86 assembly (clang, -O0):
<set_ProcessID>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0xc(%rbp),%eax
mov    %al,%cl
mov    -0x8(%rbp),%rax
mov    %cl,0x5(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<set_ProcessID>:
mov    %sil,0x5(%rdi)
ret

LLVM IR (-O0):
define void @set_ProcessID(i8* %0, i32 %1) {
%3 = alloca i8*
%4 = alloca i32
store i8* %0, i8** %3
store i32 %1, i32* %4
%5 = load i32, i32* %4
%6 = trunc i32 %5 to i8
%7 = load i8*, i8** %3
%8 = getelementptr inbounds i8, i8* %7, i64 5
store i8 %6, i8* %8
ret void
}

LLVM IR (-O2):
define void @set_ProcessID(i8* nocapture writeonly %0, i32 %1) {
%3 = trunc i32 %1 to i8
%4 = getelementptr inbounds i8, i8* %0, i64 5
store i8 %3, i8* %4
ret void
}
/* Variables and functions */
int /*<<< orphan*/ strcpy(char *, char *);
main(int argc, char **argv) {
  char buf[200];
  strcpy(buf, argv[1]);
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0xe0,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
lea    -0xe0(%rbp),%rdi
mov    -0x10(%rbp),%rax
mov    0x8(%rax),%rsi
call   1030 <strcpy@plt>
xor    %eax,%eax
add    $0xe0,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
sub    $0xc8,%rsp
mov    0x8(%rsi),%rsi
mov    %rsp,%rdi
call   1030 <strcpy@plt>
xor    %eax,%eax
add    $0xc8,%rsp
ret

LLVM IR (-O0):
define i32 @main(i32 %0, i8** %1) {
%3 = alloca i32
%4 = alloca i8**
%5 = alloca [200 x i8]
store i32 %0, i32* %3
store i8** %1, i8*** %4
%6 = getelementptr inbounds [200 x i8], [200 x i8]* %5, i64 0, i64 0
%7 = load i8**, i8*** %4
%8 = getelementptr inbounds i8*, i8** %7, i64 1
%9 = load i8*, i8** %8
%10 = call i32 @strcpy(i8* %6, i8* %9)
ret i32 0
}

LLVM IR (-O2):
define i32 @main(i32 %0, i8** nocapture %1) {
%3 = alloca [200 x i8]
%4 = getelementptr inbounds [200 x i8], [200 x i8]* %3, i64 0, i64 0
%5 = getelementptr inbounds i8*, i8** %1, i64 1
%6 = load i8*, i8** %5
%7 = call i32 @strcpy(i8* %4, i8* %6)
ret i32 0
}
struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) {
  return (struct s3c24x0_lcd *)0x4D000000;
}


x86 assembly (clang, -O0):
<s3c24x0_get_base_lcd>:
push   %rbp
mov    %rsp,%rbp
mov    $0x4d000000,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<s3c24x0_get_base_lcd>:
mov    $0x4d000000,%eax
ret

LLVM IR (-O0):
%struct.s3c24x0_lcd = type opaque
define %struct.s3c24x0_lcd* @s3c24x0_get_base_lcd() {
ret %struct.s3c24x0_lcd* inttoptr (i64 1291845632 to %struct.s3c24x0_lcd*)
}

LLVM IR (-O2):
%struct.s3c24x0_lcd = type opaque
define %struct.s3c24x0_lcd* @s3c24x0_get_base_lcd() {
ret %struct.s3c24x0_lcd* inttoptr (i64 1291845632 to %struct.s3c24x0_lcd*)
}
int Bematech_FI_AbrePortaSerial(porta)
char *porta;
{ return AbrePorta(porta); }


x86 assembly (clang, -O0):
<Bematech_FI_AbrePortaSerial>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
mov    $0x0,%al
call   1030 <AbrePorta@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<Bematech_FI_AbrePortaSerial>:
xor    %eax,%eax
jmp    1030 <AbrePorta@plt>

LLVM IR (-O0):
define i32 @Bematech_FI_AbrePortaSerial(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = call i32 (i8*, ...) bitcast (i32 (...)* @AbrePorta to i32 (i8*, ...)*)(i8* %3)
ret i32 %4
}

LLVM IR (-O2):
define i32 @Bematech_FI_AbrePortaSerial(i8* %0) {
%2 = tail call i32 (i8*, ...) bitcast (i32 (...)* @AbrePorta to i32 (i8*, ...)*)(i8* %0)
ret i32 %2
}
/* Variables and functions */
int /*<<< orphan*/ assert(int /*<<< orphan*/);
scalar_t__ nrealloc(char *, size_t);
void null_at(char **data, size_t index) {
  assert(data != NULL);
  *data = (char *)nrealloc(*data, (index + 1) * sizeof(char));
  (*data)[index] = '\0';
}


x86 assembly (clang, -O0):
<null_at>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x0,-0x8(%rbp)
setne  %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <assert@plt>
mov    -0x8(%rbp),%rax
mov    (%rax),%rdi
mov    -0x10(%rbp),%rsi
add    $0x1,%rsi
shl    $0x0,%rsi
call   1040 <nrealloc@plt>
mov    %rax,%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,(%rax)
mov    -0x8(%rbp),%rax
mov    (%rax),%rax
mov    -0x10(%rbp),%rcx
movb   $0x0,(%rax,%rcx,1)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<null_at>:
push   %r14
push   %rbx
push   %rax
mov    %rsi,%r14
mov    %rdi,%rbx
xor    %edi,%edi
test   %rbx,%rbx
setne  %dil
call   1030 <assert@plt>
mov    (%rbx),%rdi
lea    0x1(%r14),%rsi
call   1040 <nrealloc@plt>
mov    %rax,(%rbx)
movb   $0x0,(%rax,%r14,1)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define void @null_at(i8** %0, i64 %1) {
%3 = alloca i8**
%4 = alloca i64
store i8** %0, i8*** %3
store i64 %1, i64* %4
%5 = load i8**, i8*** %3
%6 = icmp ne i8** %5, null
%7 = zext i1 %6 to i32
%8 = call i32 @assert(i32 %7)
%9 = load i8**, i8*** %3
%10 = load i8*, i8** %9
%11 = load i64, i64* %4
%12 = add i64 %11, 1
%13 = mul i64 %12, 1
%14 = call i64 @nrealloc(i8* %10, i64 %13)
%15 = inttoptr i64 %14 to i8*
%16 = load i8**, i8*** %3
store i8* %15, i8** %16
%17 = load i8**, i8*** %3
%18 = load i8*, i8** %17
%19 = load i64, i64* %4
%20 = getelementptr inbounds i8, i8* %18, i64 %19
store i8 0, i8* %20
ret void
}

LLVM IR (-O2):
define void @null_at(i8** %0, i64 %1) {
%3 = icmp ne i8** %0, null
%4 = zext i1 %3 to i32
%5 = tail call i32 @assert(i32 %4)
%6 = load i8*, i8** %0
%7 = add i64 %1, 1
%8 = tail call i64 @nrealloc(i8* %6, i64 %7)
%9 = inttoptr i64 %8 to i8*
store i8* %9, i8** %0
%10 = getelementptr inbounds i8, i8* %9, i64 %1
store i8 0, i8* %10
ret void
}
void idle_threads_init(void) {}


x86 assembly (clang, -O0):
<idle_threads_init>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<idle_threads_init>:
ret

LLVM IR (-O0):
define void @idle_threads_init() {
ret void
}

LLVM IR (-O2):
define void @idle_threads_init() {
ret void
}
int main() {
  int int_var = 5;
  int *int_ptr;
  int_ptr = &int_var;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
movl   $0x5,-0x4(%rbp)
lea    -0x4(%rbp),%rax
mov    %rax,-0x10(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca i32*
store i32 5, i32* %1
store i32* %1, i32** %2
ret i32 0
}

LLVM IR (-O2):
define i32 @main() {
ret i32 0
}
int test_imm_5Aint16_reg(short val) {
  return ((val) & (-0x5A << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_5Aint16_reg>:
push   %rbp
mov    %rsp,%rbp
mov    %di,%ax
mov    %ax,-0x2(%rbp)
movswl -0x2(%rbp),%edx
and    $0xffffffa6,%edx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%edx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_5Aint16_reg>:
test   $0xffa6,%edi
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_5Aint16_reg(i16 signext %0) {
%2 = alloca i16
store i16 %0, i16* %2
%3 = load i16, i16* %2
%4 = sext i16 %3 to i32
%5 = and i32 %4, -90
%6 = icmp ne i32 %5, 0
%7 = zext i1 %6 to i64
%8 = select i1 %6, i32 -20, i32 -40
ret i32 %8
}

LLVM IR (-O2):
define i32 @test_imm_5Aint16_reg(i16 signext %0) {
%2 = and i16 %0, -90
%3 = icmp eq i16 %2, 0
%4 = select i1 %3, i32 -40, i32 -20
ret i32 %4
}
void ceph_disable_fscache_readpage(struct ceph_inode_info *ci) {}


x86 assembly (clang, -O0):
<ceph_disable_fscache_readpage>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<ceph_disable_fscache_readpage>:
ret

LLVM IR (-O0):
%struct.ceph_inode_info = type opaque
define void @ceph_disable_fscache_readpage(%struct.ceph_inode_info* %0) {
%2 = alloca %struct.ceph_inode_info*
store %struct.ceph_inode_info* %0, %struct.ceph_inode_info** %2
ret void
}

LLVM IR (-O2):
%struct.ceph_inode_info = type opaque
define void @ceph_disable_fscache_readpage(%struct.ceph_inode_info* nocapture %0) {
ret void
}
/* Variables and functions */
int /*<<< orphan*/ b(int);
int /*<<< orphan*/ proc1();
int main(int argc, char *argv[], char *envp[]) {
  proc1();
  b(argc * 3);
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
movl   $0x0,-0x4(%rbp)
mov    %edi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    $0x0,%al
call   1040 <proc1@plt>
imul   $0x3,-0x8(%rbp),%edi
call   1030 <b@plt>
xor    %eax,%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rbx
mov    %edi,%ebx
xor    %eax,%eax
call   1040 <proc1@plt>
lea    (%rbx,%rbx,2),%edi
call   1030 <b@plt>
xor    %eax,%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @main(i32 %0, i8** %1, i8** %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i8**
%7 = alloca i8**
store i32 0, i32* %4
store i32 %0, i32* %5
store i8** %1, i8*** %6
store i8** %2, i8*** %7
%8 = call i32 (...) @proc1()
%9 = load i32, i32* %5
%10 = mul nsw i32 %9, 3
%11 = call i32 @b(i32 %10)
ret i32 0
}

LLVM IR (-O2):
define i32 @main(i32 %0, i8** nocapture readnone %1, i8** nocapture readnone %2) {
%4 = tail call i32 (...) @proc1()
%5 = mul nsw i32 %0, 3
%6 = tail call i32 @b(i32 %5)
ret i32 0
}
double CubicEaseInOut(double p) {
  if (p < 0.5) {
    return 4 * p * p * p;
  } else {
    double f = ((2 * p) - 2);
    return 0.5 * f * f * f + 1;
  }
}


x86 assembly (clang, -O0):
<CubicEaseInOut>:
push   %rbp
mov    %rsp,%rbp
movsd  %xmm0,-0x10(%rbp)
movsd  0xeef(%rip),%xmm0
ucomisd -0x10(%rbp),%xmm0
jbe    113d <CubicEaseInOut+0x3d>
movsd  0xef4(%rip),%xmm0
mulsd  -0x10(%rbp),%xmm0
mulsd  -0x10(%rbp),%xmm0
mulsd  -0x10(%rbp),%xmm0
movsd  %xmm0,-0x8(%rbp)
jmp    1183 <CubicEaseInOut+0x83>
movsd  -0x10(%rbp),%xmm0
addsd  %xmm0,%xmm0
movsd  0xec2(%rip),%xmm1
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x18(%rbp)
movsd  0xea1(%rip),%xmm0
mulsd  -0x18(%rbp),%xmm0
mulsd  -0x18(%rbp),%xmm0
movsd  -0x18(%rbp),%xmm1
mulsd  %xmm1,%xmm0
movsd  0xe8e(%rip),%xmm1
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x8(%rbp)
movsd  -0x8(%rbp),%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<CubicEaseInOut>:
movsd  0xef8(%rip),%xmm1
ucomisd %xmm0,%xmm1
jbe    1127 <CubicEaseInOut+0x27>
movsd  0xf02(%rip),%xmm1
mulsd  %xmm0,%xmm1
mulsd  %xmm0,%xmm1
mulsd  %xmm0,%xmm1
movapd %xmm1,%xmm0
ret
addsd  %xmm0,%xmm0
addsd  0xed5(%rip),%xmm0
movsd  0xec5(%rip),%xmm1
mulsd  %xmm0,%xmm1
mulsd  %xmm0,%xmm1
mulsd  %xmm0,%xmm1
addsd  0xec1(%rip),%xmm1
movapd %xmm1,%xmm0
ret

LLVM IR (-O0):
define double @CubicEaseInOut(double %0) {
%2 = alloca double
%3 = alloca double
%4 = alloca double
store double %0, double* %3
%5 = load double, double* %3
%6 = fcmp olt double %5, 5.000000e-01
br i1 %6, label %7, label %14
7: ; preds = %1
%8 = load double, double* %3
%9 = fmul double 4.000000e+00, %8
%10 = load double, double* %3
%11 = fmul double %9, %10
%12 = load double, double* %3
%13 = fmul double %11, %12
store double %13, double* %2
br label %23
14: ; preds = %1
%15 = load double, double* %3
%16 = call double @llvm.fmuladd.f64(double 2.000000e+00, double %15, double -2.000000e+00)
store double %16, double* %4
%17 = load double, double* %4
%18 = fmul double 5.000000e-01, %17
%19 = load double, double* %4
%20 = fmul double %18, %19
%21 = load double, double* %4
%22 = call double @llvm.fmuladd.f64(double %20, double %21, double 1.000000e+00)
store double %22, double* %2
br label %23
23: ; preds = %14, %7
%24 = load double, double* %2
ret double %24
}

LLVM IR (-O2):
define double @CubicEaseInOut(double %0) {
%2 = fcmp olt double %0, 5.000000e-01
br i1 %2, label %3, label %7
3: ; preds = %1
%4 = fmul double %0, 4.000000e+00
%5 = fmul double %4, %0
%6 = fmul double %5, %0
br label %12
7: ; preds = %1
%8 = tail call double @llvm.fmuladd.f64(double %0, double 2.000000e+00, double -2.000000e+00)
%9 = fmul double %8, 5.000000e-01
%10 = fmul double %8, %9
%11 = tail call double @llvm.fmuladd.f64(double %10, double %8, double 1.000000e+00)
br label %12
12: ; preds = %7, %3
%13 = phi double [ %6, %3 ], [ %11, %7 ]
ret double %13
}
/* Variables and functions */
unsigned long os_random(void) { return 0; }


x86 assembly (clang, -O0):
<os_random>:
push   %rbp
mov    %rsp,%rbp
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<os_random>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i64 @os_random() {
ret i64 0
}

LLVM IR (-O2):
define i64 @os_random() {
ret i64 0
}
/* Variables and functions */
int /*<<< orphan*/ list3(int, int, int);
int pair(int, int /*<<< orphan*/);
int list4(int a, int b, int c, int d) { return pair(a, list3(b, c, d)); }


x86 assembly (clang, -O0):
<list4>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    %ecx,-0x10(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x8(%rbp),%edi
mov    -0xc(%rbp),%esi
mov    -0x10(%rbp),%edx
call   1030 <list3@plt>
mov    -0x14(%rbp),%edi
mov    %eax,%esi
call   1040 <pair@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<list4>:
push   %rbx
mov    %edi,%ebx
mov    %esi,%edi
mov    %edx,%esi
mov    %ecx,%edx
call   1030 <list3@plt>
mov    %ebx,%edi
mov    %eax,%esi
pop    %rbx
jmp    1040 <pair@plt>

LLVM IR (-O0):
define i32 @list4(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
store i32 %0, i32* %5
store i32 %1, i32* %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%9 = load i32, i32* %5
%10 = load i32, i32* %6
%11 = load i32, i32* %7
%12 = load i32, i32* %8
%13 = call i32 @list3(i32 %10, i32 %11, i32 %12)
%14 = call i32 @pair(i32 %9, i32 %13)
ret i32 %14
}

LLVM IR (-O2):
define i32 @list4(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = tail call i32 @list3(i32 %1, i32 %2, i32 %3)
%6 = tail call i32 @pair(i32 %0, i32 %5)
ret i32 %6
}
int bit_count(unsigned int i) {
  i = i - ((i >> 1) & 0x55555555);
  i = (i & 0x33333333) + ((i >> 2) & 0x33333333);
  return (((i + (i >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
}


x86 assembly (clang, -O0):
<bit_count>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    -0x4(%rbp),%ecx
shr    $0x1,%ecx
and    $0x55555555,%ecx
sub    %ecx,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
and    $0x33333333,%eax
mov    -0x4(%rbp),%ecx
shr    $0x2,%ecx
and    $0x33333333,%ecx
add    %ecx,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    -0x4(%rbp),%ecx
shr    $0x4,%ecx
add    %ecx,%eax
and    $0xf0f0f0f,%eax
imul   $0x1010101,%eax,%eax
shr    $0x18,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<bit_count>:
mov    %edi,%eax
shr    %eax
and    $0x55555555,%eax
sub    %eax,%edi
mov    %edi,%eax
and    $0x33333333,%eax
shr    $0x2,%edi
and    $0x33333333,%edi
add    %eax,%edi
mov    %edi,%eax
shr    $0x4,%eax
add    %edi,%eax
and    $0xf0f0f0f,%eax
imul   $0x1010101,%eax,%eax
shr    $0x18,%eax
ret

LLVM IR (-O0):
define i32 @bit_count(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = load i32, i32* %2
%5 = lshr i32 %4, 1
%6 = and i32 %5, 1431655765
%7 = sub i32 %3, %6
store i32 %7, i32* %2
%8 = load i32, i32* %2
%9 = and i32 %8, 858993459
%10 = load i32, i32* %2
%11 = lshr i32 %10, 2
%12 = and i32 %11, 858993459
%13 = add i32 %9, %12
store i32 %13, i32* %2
%14 = load i32, i32* %2
%15 = load i32, i32* %2
%16 = lshr i32 %15, 4
%17 = add i32 %14, %16
%18 = and i32 %17, 252645135
%19 = mul i32 %18, 16843009
%20 = lshr i32 %19, 24
ret i32 %20
}

LLVM IR (-O2):
define i32 @bit_count(i32 %0) {
%2 = lshr i32 %0, 1
%3 = and i32 %2, 1431655765
%4 = sub i32 %0, %3
%5 = and i32 %4, 858993459
%6 = lshr i32 %4, 2
%7 = and i32 %6, 858993459
%8 = add nuw nsw i32 %7, %5
%9 = lshr i32 %8, 4
%10 = add nuw nsw i32 %9, %8
%11 = and i32 %10, 252645135
%12 = mul i32 %11, 16843009
%13 = lshr i32 %12, 24
ret i32 %13
}
/* Variables and functions */
int isEmptyName(char *s) {
  if (s == NULL)
    return 1;
  if (s[0] == '\0')
    return 1;
  if (s[0] == '{' && s[1] == '}')
    return 1;
  return 0;
}


x86 assembly (clang, -O0):
<isEmptyName>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x10(%rbp)
cmpq   $0x0,-0x10(%rbp)
jne    111f <isEmptyName+0x1f>
movl   $0x1,-0x4(%rbp)
jmp    116f <isEmptyName+0x6f>
mov    -0x10(%rbp),%rax
movsbl (%rax),%eax
cmp    $0x0,%eax
jne    113b <isEmptyName+0x3b>
movl   $0x1,-0x4(%rbp)
jmp    116f <isEmptyName+0x6f>
mov    -0x10(%rbp),%rax
movsbl (%rax),%eax
cmp    $0x7b,%eax
jne    1168 <isEmptyName+0x68>
mov    -0x10(%rbp),%rax
movsbl 0x1(%rax),%eax
cmp    $0x7d,%eax
jne    1168 <isEmptyName+0x68>
movl   $0x1,-0x4(%rbp)
jmp    116f <isEmptyName+0x6f>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<isEmptyName>:
mov    $0x1,%eax
test   %rdi,%rdi
je     111d <isEmptyName+0x1d>
mov    (%rdi),%cl
test   %cl,%cl
je     111d <isEmptyName+0x1d>
cmp    $0x7b,%cl
jne    111b <isEmptyName+0x1b>
cmpb   $0x7d,0x1(%rdi)
je     111d <isEmptyName+0x1d>
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @isEmptyName(i8* %0) {
%2 = alloca i32
%3 = alloca i8*
store i8* %0, i8** %3
%4 = load i8*, i8** %3
%5 = icmp eq i8* %4, null
br i1 %5, label %6, label %7
6: ; preds = %1
store i32 1, i32* %2
br label %28
7: ; preds = %1
%8 = load i8*, i8** %3
%9 = getelementptr inbounds i8, i8* %8, i64 0
%10 = load i8, i8* %9
%11 = sext i8 %10 to i32
%12 = icmp eq i32 %11, 0
br i1 %12, label %13, label %14
13: ; preds = %7
store i32 1, i32* %2
br label %28
14: ; preds = %7
%15 = load i8*, i8** %3
%16 = getelementptr inbounds i8, i8* %15, i64 0
%17 = load i8, i8* %16
%18 = sext i8 %17 to i32
%19 = icmp eq i32 %18, 123
br i1 %19, label %20, label %27
20: ; preds = %14
%21 = load i8*, i8** %3
%22 = getelementptr inbounds i8, i8* %21, i64 1
%23 = load i8, i8* %22
%24 = sext i8 %23 to i32
%25 = icmp eq i32 %24, 125
br i1 %25, label %26, label %27
26: ; preds = %20
store i32 1, i32* %2
br label %28
27: ; preds = %20, %14
store i32 0, i32* %2
br label %28
28: ; preds = %27, %26, %13, %6
%29 = load i32, i32* %2
ret i32 %29
}

LLVM IR (-O2):
define i32 @isEmptyName(i8* %0) {
%2 = icmp eq i8* %0, null
br i1 %2, label %10, label %3
3: ; preds = %1
%4 = load i8, i8* %0
switch i8 %4, label %9 [
i8 0, label %10
i8 123, label %5
]
5: ; preds = %3
%6 = getelementptr inbounds i8, i8* %0, i64 1
%7 = load i8, i8* %6
%8 = icmp eq i8 %7, 125
br i1 %8, label %10, label %9
9: ; preds = %3, %5
br label %10
10: ; preds = %5, %3, %1, %9
%11 = phi i32 [ 0, %9 ], [ 1, %1 ], [ 1, %3 ], [ 1, %5 ]
ret i32 %11
}
unsigned short int f86(unsigned short int x, long int y) {
  return (x << (8 * 2 - y)) + (x >> y);
}


x86 assembly (clang, -O0):
<f86>:
push   %rbp
mov    %rsp,%rbp
mov    %di,%ax
mov    %ax,-0x2(%rbp)
mov    %rsi,-0x10(%rbp)
movzwl -0x2(%rbp),%eax
mov    $0x10,%ecx
sub    -0x10(%rbp),%rcx
shl    %cl,%eax
movzwl -0x2(%rbp),%edx
mov    -0x10(%rbp),%rcx
sar    %cl,%edx
mov    %edx,%ecx
add    %ecx,%eax
movzwl %ax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<f86>:
mov    $0x10,%cl
sub    %sil,%cl
mov    %edi,%eax
shl    %cl,%eax
mov    %esi,%ecx
shr    %cl,%edi
add    %edi,%eax
ret

LLVM IR (-O0):
define zeroext i16 @f86(i16 zeroext %0, i64 %1) {
%3 = alloca i16
%4 = alloca i64
store i16 %0, i16* %3
store i64 %1, i64* %4
%5 = load i16, i16* %3
%6 = zext i16 %5 to i32
%7 = load i64, i64* %4
%8 = sub nsw i64 16, %7
%9 = trunc i64 %8 to i32
%10 = shl i32 %6, %9
%11 = load i16, i16* %3
%12 = zext i16 %11 to i32
%13 = load i64, i64* %4
%14 = trunc i64 %13 to i32
%15 = ashr i32 %12, %14
%16 = add nsw i32 %10, %15
%17 = trunc i32 %16 to i16
ret i16 %17
}

LLVM IR (-O2):
define zeroext i16 @f86(i16 zeroext %0, i64 %1) {
%3 = zext i16 %0 to i32
%4 = trunc i64 %1 to i32
%5 = sub i32 16, %4
%6 = shl i32 %3, %5
%7 = lshr i32 %3, %4
%8 = add nsw i32 %6, %7
%9 = trunc i32 %8 to i16
ret i16 %9
}
/* Variables and functions */
int /*<<< orphan*/ debug(char *, ...);
int M567_f(char *s) {
  debug("M567_f(const char *s) is not yet implemented!\n");
  debug("%s\n", s);
  return 1;
}


x86 assembly (clang, -O0):
<M567_f>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
lea    0xedd(%rip),%rdi
mov    $0x0,%al
call   1030 <debug@plt>
mov    -0x8(%rbp),%rsi
lea    0xefa(%rip),%rdi
mov    $0x0,%al
call   1030 <debug@plt>
mov    $0x1,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<M567_f>:
push   %rbx
mov    %rdi,%rbx
lea    0xee5(%rip),%rdi
xor    %eax,%eax
call   1030 <debug@plt>
lea    0xf06(%rip),%rdi
mov    %rbx,%rsi
xor    %eax,%eax
call   1030 <debug@plt>
mov    $0x1,%eax
pop    %rbx
ret

LLVM IR (-O0):
@.str = [47 x i8] c"M567_f(const char *s) is not yet implemented!\0A\00"
@.str.1 = [4 x i8] c"%s\0A\00"
define i32 @M567_f(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = call i32 (i8*, ...) @debug(i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str, i64 0, i64 0))
%4 = load i8*, i8** %2
%5 = call i32 (i8*, ...) @debug(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.1, i64 0, i64 0), i8* %4)
ret i32 1
}

LLVM IR (-O2):
@.str = [47 x i8] c"M567_f(const char *s) is not yet implemented!\0A\00"
@.str.1 = [4 x i8] c"%s\0A\00"
define i32 @M567_f(i8* %0) {
%2 = tail call i32 (i8*, ...) @debug(i8* getelementptr inbounds ([47 x i8], [47 x i8]* @.str, i64 0, i64 0))
%3 = tail call i32 (i8*, ...) @debug(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.1, i64 0, i64 0), i8* %0)
ret i32 1
}
/* Type definitions */
typedef int /*<<< orphan*/ uint16_t;
struct sockaddr {
  int sa_family;
};

/* Variables and functions */
#define AF_INET 129
#define AF_INET6 128
int /*<<< orphan*/ get_port4(struct sockaddr const *);
int /*<<< orphan*/ get_port6(struct sockaddr const *);
uint16_t nfs_get_port(const struct sockaddr *sap) {
  switch (sap->sa_family) {
  case AF_INET:
    return get_port4(sap);
  case AF_INET6:
    return get_port6(sap);
  }
  return 0;
}


x86 assembly (clang, -O0):
<nfs_get_port>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    -0x10(%rbp),%rax
mov    (%rax),%eax
mov    %eax,-0x14(%rbp)
sub    $0x80,%eax
je     1169 <nfs_get_port+0x49>
jmp    1145 <nfs_get_port+0x25>
mov    -0x14(%rbp),%eax
sub    $0x81,%eax
jne    117a <nfs_get_port+0x5a>
jmp    1158 <nfs_get_port+0x38>
mov    -0x10(%rbp),%rdi
call   1030 <get_port4@plt>
mov    %eax,-0x4(%rbp)
jmp    1181 <nfs_get_port+0x61>
mov    -0x10(%rbp),%rdi
call   1040 <get_port6@plt>
mov    %eax,-0x4(%rbp)
jmp    1181 <nfs_get_port+0x61>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<nfs_get_port>:
mov    (%rdi),%eax
cmp    $0x80,%eax
je     1135 <nfs_get_port+0x15>
cmp    $0x81,%eax
jne    113a <nfs_get_port+0x1a>
jmp    1030 <get_port4@plt>
jmp    1040 <get_port6@plt>
xor    %eax,%eax
ret

LLVM IR (-O0):
%struct.sockaddr = type { i32 }
define i32 @nfs_get_port(%struct.sockaddr* %0) {
%2 = alloca i32
%3 = alloca %struct.sockaddr*
store %struct.sockaddr* %0, %struct.sockaddr** %3
%4 = load %struct.sockaddr*, %struct.sockaddr** %3
%5 = getelementptr inbounds %struct.sockaddr, %struct.sockaddr* %4, i32 0, i32 0
%6 = load i32, i32* %5
switch i32 %6, label %13 [
i32 129, label %7
i32 128, label %10
]
7: ; preds = %1
%8 = load %struct.sockaddr*, %struct.sockaddr** %3
%9 = call i32 @get_port4(%struct.sockaddr* %8)
store i32 %9, i32* %2
br label %14
10: ; preds = %1
%11 = load %struct.sockaddr*, %struct.sockaddr** %3
%12 = call i32 @get_port6(%struct.sockaddr* %11)
store i32 %12, i32* %2
br label %14
13: ; preds = %1
store i32 0, i32* %2
br label %14
14: ; preds = %13, %10, %7
%15 = load i32, i32* %2
ret i32 %15
}

LLVM IR (-O2):
%struct.sockaddr = type { i32 }
define i32 @nfs_get_port(%struct.sockaddr* %0) {
%2 = getelementptr inbounds %struct.sockaddr, %struct.sockaddr* %0, i64 0, i32 0
%3 = load i32, i32* %2
switch i32 %3, label %8 [
i32 129, label %4
i32 128, label %6
]
4: ; preds = %1
%5 = tail call i32 @get_port4(%struct.sockaddr* %0)
br label %8
6: ; preds = %1
%7 = tail call i32 @get_port6(%struct.sockaddr* %0)
br label %8
8: ; preds = %1, %6, %4
%9 = phi i32 [ %7, %6 ], [ %5, %4 ], [ 0, %1 ]
ret i32 %9
}
void CPU_WriteBufferEnable(void) {
  (*((volatile unsigned long
          *)(((unsigned long)(0xE000E000 + 0x00000008) & 0xF0000000) |
             0x02000000 |
             (((unsigned long)(0xE000E000 + 0x00000008) & 0x000FFFFF) << 5) |
             ((1) << 2)))) = 0;
}


x86 assembly (clang, -O0):
<CPU_WriteBufferEnable>:
push   %rbp
mov    %rsp,%rbp
mov    $0xe21c0104,%eax
movq   $0x0,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<CPU_WriteBufferEnable>:
mov    $0xe21c0104,%eax
movq   $0x0,(%rax)
ret

LLVM IR (-O0):
define void @CPU_WriteBufferEnable() {
store volatile i64 0, i64* inttoptr (i64 3793486084 to i64*)
ret void
}

LLVM IR (-O2):
define void @CPU_WriteBufferEnable() {
store volatile i64 0, i64* inttoptr (i64 3793486084 to i64*)
ret void
}
void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {}


x86 assembly (clang, -O0):
<ath79_nfc_set_select_chip>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<ath79_nfc_set_select_chip>:
ret

LLVM IR (-O0):
define void @ath79_nfc_set_select_chip(void (i32)* %0) {
%2 = alloca void (i32)*
store void (i32)* %0, void (i32)** %2
ret void
}

LLVM IR (-O2):
define void @ath79_nfc_set_select_chip(void (i32)* nocapture %0) {
ret void
}
void AKSC_SetHDOELevel(void) {}


x86 assembly (clang, -O0):
<AKSC_SetHDOELevel>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<AKSC_SetHDOELevel>:
ret

LLVM IR (-O0):
define void @AKSC_SetHDOELevel() {
ret void
}

LLVM IR (-O2):
define void @AKSC_SetHDOELevel() {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ __m128i;

/* Variables and functions */
int /*<<< orphan*/ _mm_storeu_si128(int /*<<< orphan*/ *, int /*<<< orphan*/);
void storeu(const void *p, __m128i x) { _mm_storeu_si128((__m128i *)p, x); }


x86 assembly (clang, -O0):
<storeu>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0xc(%rbp),%esi
call   1030 <_mm_storeu_si128@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<storeu>:
jmp    1030 <_mm_storeu_si128@plt>

LLVM IR (-O0):
define void @storeu(i8* %0, i32 %1) {
%3 = alloca i8*
%4 = alloca i32
store i8* %0, i8** %3
store i32 %1, i32* %4
%5 = load i8*, i8** %3
%6 = bitcast i8* %5 to i32*
%7 = load i32, i32* %4
%8 = call i32 @_mm_storeu_si128(i32* %6, i32 %7)
ret void
}

LLVM IR (-O2):
define void @storeu(i8* %0, i32 %1) {
%3 = bitcast i8* %0 to i32*
%4 = tail call i32 @_mm_storeu_si128(i32* %3, i32 %1)
ret void
}
/* Variables and functions */
void *fdopen(int, char *);
void *stdio_file_handler_dopen(int fileno) { return fdopen(fileno, "w"); }


x86 assembly (clang, -O0):
<stdio_file_handler_dopen>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
lea    0xedb(%rip),%rsi
call   1030 <fdopen@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<stdio_file_handler_dopen>:
lea    0xee9(%rip),%rsi
jmp    1030 <fdopen@plt>

LLVM IR (-O0):
@.str = [2 x i8] c"w\00"
define i8* @stdio_file_handler_dopen(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i8* @fdopen(i32 %3, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
ret i8* %4
}

LLVM IR (-O2):
@.str = [2 x i8] c"w\00"
define noalias i8* @stdio_file_handler_dopen(i32 %0) {
%2 = tail call i8* @fdopen(i32 %0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
ret i8* %2
}
/* Variables and functions */
void Sys_PlatformExit(void) {}


x86 assembly (clang, -O0):
<Sys_PlatformExit>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<Sys_PlatformExit>:
ret

LLVM IR (-O0):
define void @Sys_PlatformExit() {
ret void
}

LLVM IR (-O2):
define void @Sys_PlatformExit() {
ret void
}
void CL_HTTP_Reset(void) {}


x86 assembly (clang, -O0):
<CL_HTTP_Reset>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<CL_HTTP_Reset>:
ret

LLVM IR (-O0):
define void @CL_HTTP_Reset() {
ret void
}

LLVM IR (-O2):
define void @CL_HTTP_Reset() {
ret void
}
/* Type definitions */
typedef scalar_t__ uint16_t;

/* Variables and functions */
int /*<<< orphan*/ sg_put_unaligned_be16(scalar_t__, void *);
void sg_nz_put_unaligned_be16(uint16_t val, void *p) {
  if (val)
    sg_put_unaligned_be16(val, p);
}


x86 assembly (clang, -O0):
<sg_nz_put_unaligned_be16>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x0,-0x8(%rbp)
je     1138 <sg_nz_put_unaligned_be16+0x28>
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
call   1030 <sg_put_unaligned_be16@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sg_nz_put_unaligned_be16>:
test   %rdi,%rdi
je     111a <sg_nz_put_unaligned_be16+0xa>
jmp    1030 <sg_put_unaligned_be16@plt>
ret

LLVM IR (-O0):
define void @sg_nz_put_unaligned_be16(i64 %0, i8* %1) {
%3 = alloca i64
%4 = alloca i8*
store i64 %0, i64* %3
store i8* %1, i8** %4
%5 = load i64, i64* %3
%6 = icmp ne i64 %5, 0
br i1 %6, label %7, label %11
7: ; preds = %2
%8 = load i64, i64* %3
%9 = load i8*, i8** %4
%10 = call i32 @sg_put_unaligned_be16(i64 %8, i8* %9)
br label %11
11: ; preds = %7, %2
ret void
}

LLVM IR (-O2):
define void @sg_nz_put_unaligned_be16(i64 %0, i8* %1) {
%3 = icmp eq i64 %0, 0
br i1 %3, label %6, label %4
4: ; preds = %2
%5 = tail call i32 @sg_put_unaligned_be16(i64 %0, i8* %1)
br label %6
6: ; preds = %4, %2
ret void
}