#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) {
  ASSERT(ui32Base == 0x44034000);
  ASSERT((ui32IntFlags == 0x00000008) || (ui32IntFlags == 0x00000004) ||
         (ui32IntFlags == 0x00000002) || (ui32IntFlags == 0x00000001));
  (*((volatile uint32_t *)(ui32Base + 0xFFFFC010))) |=
      (((ui32IntFlags & 0x00010000) >> 14) |
       ((ui32IntFlags & 0x00020000) >> 16) |
       ((ui32IntFlags & 0x00040000) >> 19));
  (*((volatile uint32_t *)(ui32Base + 0x0000011C))) |=
      ui32IntFlags & 0x0000ffff;
  (*((volatile uint32_t *)(ui32Base + 0x00000110))) |= 0x00000004;
}


x86 assembly (clang, -O0):
<SHAMD5IntEnable>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
cmpl   $0x44034000,-0x4(%rbp)
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    $0x1,%al
cmpl   $0x8,-0x8(%rbp)
mov    %al,-0x9(%rbp)
je     1169 <SHAMD5IntEnable+0x59>
mov    $0x1,%al
cmpl   $0x4,-0x8(%rbp)
mov    %al,-0x9(%rbp)
je     1169 <SHAMD5IntEnable+0x59>
mov    $0x1,%al
cmpl   $0x2,-0x8(%rbp)
mov    %al,-0x9(%rbp)
je     1169 <SHAMD5IntEnable+0x59>
cmpl   $0x1,-0x8(%rbp)
sete   %al
mov    %al,-0x9(%rbp)
mov    -0x9(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0x8(%rbp),%edx
and    $0x10000,%edx
sar    $0xe,%edx
mov    -0x8(%rbp),%eax
and    $0x20000,%eax
sar    $0x10,%eax
or     %eax,%edx
mov    -0x8(%rbp),%eax
and    $0x40000,%eax
sar    $0x13,%eax
or     %eax,%edx
mov    -0x4(%rbp),%eax
add    $0xffffc010,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     %edx,%ecx
mov    %ecx,(%rax)
mov    -0x8(%rbp),%edx
and    $0xffff,%edx
mov    -0x4(%rbp),%eax
add    $0x11c,%eax
cltq
mov    (%rax),%ecx
or     %edx,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%eax
add    $0x110,%eax
cltq
mov    (%rax),%ecx
or     $0x4,%ecx
mov    %ecx,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<SHAMD5IntEnable>:
push   %r14
push   %rbx
push   %rax
mov    %esi,%ebx
mov    %edi,%r14d
xor    %edi,%edi
cmp    $0x44034000,%r14d
sete   %dil
call   1030 <ASSERT@plt>
cmp    $0x8,%ebx
ja     113f <SHAMD5IntEnable+0x2f>
mov    $0x1,%edi
mov    $0x114,%eax
bt     %ebx,%eax
jb     1148 <SHAMD5IntEnable+0x38>
xor    %edi,%edi
cmp    $0x1,%ebx
sete   %dil
call   1030 <ASSERT@plt>
mov    %ebx,%eax
shr    $0xe,%eax
and    $0x4,%eax
mov    %ebx,%ecx
shr    $0x10,%ecx
and    $0x2,%ecx
or     %eax,%ecx
lea    -0x3ff0(%r14),%eax
or     %ecx,(%rax)
movzwl %bx,%eax
movslq %r14d,%rcx
or     %eax,0x11c(%rcx)
orl    $0x4,0x110(%rcx)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define void @SHAMD5IntEnable(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %3
%6 = icmp eq i32 %5, 1141063680
%7 = zext i1 %6 to i32
%8 = call i32 @ASSERT(i32 %7)
%9 = load i32, i32* %4
%10 = icmp eq i32 %9, 8
br i1 %10, label %20, label %11
11: ; preds = %2
%12 = load i32, i32* %4
%13 = icmp eq i32 %12, 4
br i1 %13, label %20, label %14
14: ; preds = %11
%15 = load i32, i32* %4
%16 = icmp eq i32 %15, 2
br i1 %16, label %20, label %17
17: ; preds = %14
%18 = load i32, i32* %4
%19 = icmp eq i32 %18, 1
br label %20
20: ; preds = %17, %14, %11, %2
%21 = phi i1 [ true, %14 ], [ true, %11 ], [ true, %2 ], [ %19, %17 ]
%22 = zext i1 %21 to i32
%23 = call i32 @ASSERT(i32 %22)
%24 = load i32, i32* %4
%25 = and i32 %24, 65536
%26 = ashr i32 %25, 14
%27 = load i32, i32* %4
%28 = and i32 %27, 131072
%29 = ashr i32 %28, 16
%30 = or i32 %26, %29
%31 = load i32, i32* %4
%32 = and i32 %31, 262144
%33 = ashr i32 %32, 19
%34 = or i32 %30, %33
%35 = load i32, i32* %3
%36 = add i32 %35, -16368
%37 = zext i32 %36 to i64
%38 = inttoptr i64 %37 to i32*
%39 = load volatile i32, i32* %38
%40 = or i32 %39, %34
store volatile i32 %40, i32* %38
%41 = load i32, i32* %4
%42 = and i32 %41, 65535
%43 = load i32, i32* %3
%44 = add nsw i32 %43, 284
%45 = sext i32 %44 to i64
%46 = inttoptr i64 %45 to i32*
%47 = load volatile i32, i32* %46
%48 = or i32 %47, %42
store volatile i32 %48, i32* %46
%49 = load i32, i32* %3
%50 = add nsw i32 %49, 272
%51 = sext i32 %50 to i64
%52 = inttoptr i64 %51 to i32*
%53 = load volatile i32, i32* %52
%54 = or i32 %53, 4
store volatile i32 %54, i32* %52
ret void
}

LLVM IR (-O2):
define void @SHAMD5IntEnable(i32 %0, i32 %1) {
%3 = icmp eq i32 %0, 1141063680
%4 = zext i1 %3 to i32
%5 = tail call i32 @ASSERT(i32 %4)
switch i32 %1, label %6 [
i32 8, label %9
i32 4, label %9
i32 2, label %9
]
6: ; preds = %2
%7 = icmp eq i32 %1, 1
%8 = zext i1 %7 to i32
br label %9
9: ; preds = %2, %2, %2, %6
%10 = phi i32 [ 1, %2 ], [ %8, %6 ], [ 1, %2 ], [ 1, %2 ]
%11 = tail call i32 @ASSERT(i32 %10)
%12 = lshr i32 %1, 14
%13 = and i32 %12, 4
%14 = lshr i32 %1, 16
%15 = and i32 %14, 2
%16 = or i32 %13, %15
%17 = add i32 %0, -16368
%18 = zext i32 %17 to i64
%19 = inttoptr i64 %18 to i32*
%20 = load volatile i32, i32* %19
%21 = or i32 %16, %20
store volatile i32 %21, i32* %19
%22 = and i32 %1, 65535
%23 = add nsw i32 %0, 284
%24 = sext i32 %23 to i64
%25 = inttoptr i64 %24 to i32*
%26 = load volatile i32, i32* %25
%27 = or i32 %26, %22
store volatile i32 %27, i32* %25
%28 = add nsw i32 %0, 272
%29 = sext i32 %28 to i64
%30 = inttoptr i64 %29 to i32*
%31 = load volatile i32, i32* %30
%32 = or i32 %31, 4
store volatile i32 %32, i32* %30
ret void
}