double SIM_power_bitline_delay(C, A, B, Ndwl, Ndbl, Nspd, inrisetime,
                               outrisetime)
int C, A, B, Ndwl, Ndbl, Nspd;
double inrisetime, *outrisetime;
{
  double Tbit, Cline, Ccolmux, Rlineb, r1, r2, c1, c2, a, b, c;
  double m, tstep;
  double Cbitrow;
  int rows, cols;
  Cbitrow = SIM_power_draincap((2.4 * 0.0875), 1, 1) / 2.0;
  rows = C / (B * A * Ndbl * Nspd);
  cols = 8 * B * A * Nspd / Ndwl;
  if (Ndbl * Nspd == 1) {
    Cline = rows * (Cbitrow + (4.4e-15 * ((172.2157) * (0.0875 * 0.0875)))) +
            2 * SIM_power_draincap((10.0 * 0.0875), 0, 1);
    Ccolmux = 2 * SIM_power_gatecap((4.0 * 0.0875), 10.0);
    Rlineb = (0.320 * ((160.0000) * (0.0875 * 0.0875))) * rows / 2.0;
    r1 = Rlineb;
  } else {
    Cline = rows * (Cbitrow + (4.4e-15 * ((172.2157) * (0.0875 * 0.0875)))) +
            2 * SIM_power_draincap((10.0 * 0.0875), 0, 1) +
            SIM_power_draincap((10.0 * 0.0875), 1, 1);
    Ccolmux = Nspd * Ndbl * (SIM_power_draincap((10.0 * 0.0875), 1, 1)) +
              2 * SIM_power_gatecap((4.0 * 0.0875), 10.0);
    Rlineb = (0.320 * ((160.0000) * (0.0875 * 0.0875))) * rows / 2.0;
    r1 = Rlineb + SIM_power_transreson((10.0 * 0.0875), 1, 1);
  }
  r2 = SIM_power_transreson((2.4 * 0.0875), 1, 1) +
       SIM_power_transreson((2.4 * 0.0875) * 2, 1, 1);
  c1 = Ccolmux;
  c2 = Cline;
  tstep = (r2 * c2 + (r1 + r2) * c1) *
          log(((3.3 * 0.75)) / ((3.3 * 0.75) - (0.10 * 0.75)));
  m = (5 * 0.36) / inrisetime;
  if (tstep <= (0.5 * ((5 * 0.36) - (1.09 * 0.46)) / m)) {
    a = m;
    b = 2 * (((5 * 0.36) * 0.5) - (1.09 * 0.46));
    c = -2 * tstep * ((5 * 0.36) - (1.09 * 0.46)) +
        1 / m * (((5 * 0.36) * 0.5) - (1.09 * 0.46)) *
            (((5 * 0.36) * 0.5) - (1.09 * 0.46));
    Tbit = (-b + sqrt(b * b - 4 * a * c)) / (2 * a);
  } else {
    Tbit =
        tstep + ((5 * 0.36) + (1.09 * 0.46)) / (2 * m) - ((5 * 0.36) * 0.5) / m;
  }
  *outrisetime = Tbit / (log(((3.3 * 0.75) - (0.10 * 0.75)) / (5 * 0.36)));
  return (Tbit);
}


x86 assembly (clang, -O0):
<SIM_power_bitline_delay>:
push   %rbp
mov    %rsp,%rbp
sub    $0xf0,%rsp
mov    0x10(%rbp),%rax
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    %ecx,-0x10(%rbp)
mov    %r8d,-0x14(%rbp)
mov    %r9d,-0x18(%rbp)
movsd  %xmm0,-0x20(%rbp)
movsd  0xe88(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
cvtsi2sd %eax,%xmm0
movsd  0xe66(%rip),%xmm1
divsd  %xmm1,%xmm0
movsd  %xmm0,-0x90(%rbp)
ff
mov    -0x4(%rbp),%eax
mov    -0xc(%rbp),%ecx
imul   -0x8(%rbp),%ecx
imul   -0x14(%rbp),%ecx
imul   -0x18(%rbp),%ecx
cltd
idiv   %ecx
mov    %eax,-0x94(%rbp)
mov    -0xc(%rbp),%eax
shl    $0x3,%eax
imul   -0x8(%rbp),%eax
imul   -0x18(%rbp),%eax
cltd
idivl  -0x10(%rbp)
mov    %eax,-0x98(%rbp)
mov    -0x14(%rbp),%eax
imul   -0x18(%rbp),%eax
cmp    $0x1,%eax
jne    12a2 <SIM_power_bitline_delay+0x152>
cvtsi2sdl -0x94(%rbp),%xmm0
ff
movsd  %xmm0,-0xa8(%rbp)
ff
movsd  0xe2f(%rip),%xmm0
addsd  -0x90(%rbp),%xmm0
ff
movsd  %xmm0,-0xa0(%rbp)
ff
movsd  0xdf7(%rip),%xmm0
xor    %edi,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
movsd  -0xa8(%rbp),%xmm0
ff
movsd  -0xa0(%rbp),%xmm2
ff
shl    $0x1,%eax
cvtsi2sd %eax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
movsd  0xdcd(%rip),%xmm0
movsd  0xdcd(%rip),%xmm1
mov    $0x2,%al
call   1060 <SIM_power_gatecap@plt>
shl    $0x1,%eax
cvtsi2sd %eax,%xmm0
movsd  %xmm0,-0x38(%rbp)
cvtsi2sdl -0x94(%rbp),%xmm1
ff
movsd  0xd9a(%rip),%xmm0
mulsd  %xmm1,%xmm0
movsd  0xd76(%rip),%xmm1
divsd  %xmm1,%xmm0
movsd  %xmm0,-0x40(%rbp)
movsd  -0x40(%rbp),%xmm0
movsd  %xmm0,-0x48(%rbp)
jmp    13f0 <SIM_power_bitline_delay+0x2a0>
cvtsi2sdl -0x94(%rbp),%xmm0
ff
movsd  %xmm0,-0xd0(%rbp)
ff
movsd  0xd76(%rip),%xmm0
addsd  -0x90(%rbp),%xmm0
ff
movsd  %xmm0,-0xc8(%rbp)
ff
movsd  0xd3e(%rip),%xmm0
xor    %edi,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
movsd  -0xd0(%rbp),%xmm0
ff
movsd  -0xc8(%rbp),%xmm2
ff
shl    $0x1,%eax
cvtsi2sd %eax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0xc0(%rbp)
ff
movsd  0xd01(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
movsd  -0xc0(%rbp),%xmm0
ff
cvtsi2sd %eax,%xmm1
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x30(%rbp)
mov    -0x18(%rbp),%eax
imul   -0x14(%rbp),%eax
mov    %eax,-0xb8(%rbp)
movsd  0xcc9(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
mov    %eax,%ecx
mov    -0xb8(%rbp),%eax
imul   %ecx,%eax
mov    %eax,-0xb4(%rbp)
movsd  0xcb2(%rip),%xmm0
movsd  0xcb2(%rip),%xmm1
mov    $0x2,%al
call   1060 <SIM_power_gatecap@plt>
mov    %eax,%ecx
mov    -0xb4(%rbp),%eax
shl    $0x1,%ecx
add    %ecx,%eax
cvtsi2sd %eax,%xmm0
movsd  %xmm0,-0x38(%rbp)
cvtsi2sdl -0x94(%rbp),%xmm1
ff
movsd  0xc75(%rip),%xmm0
mulsd  %xmm1,%xmm0
movsd  0xc51(%rip),%xmm1
divsd  %xmm1,%xmm0
movsd  %xmm0,-0x40(%rbp)
movsd  -0x40(%rbp),%xmm0
movsd  %xmm0,-0xb0(%rbp)
ff
movsd  0xc43(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
movsd  -0xb0(%rbp),%xmm0
ff
cvtsi2sd %eax,%xmm1
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x48(%rbp)
movsd  0xc10(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
mov    %eax,-0xdc(%rbp)
movsd  0xc3c(%rip),%xmm0
mov    $0x1,%esi
mov    %esi,%edi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
mov    %eax,%ecx
mov    -0xdc(%rbp),%eax
add    %ecx,%eax
cvtsi2sd %eax,%xmm0
movsd  %xmm0,-0x50(%rbp)
movsd  -0x38(%rbp),%xmm0
movsd  %xmm0,-0x58(%rbp)
movsd  -0x30(%rbp),%xmm0
movsd  %xmm0,-0x60(%rbp)
movsd  -0x50(%rbp),%xmm0
movsd  -0x60(%rbp),%xmm2
movsd  -0x48(%rbp),%xmm1
addsd  -0x50(%rbp),%xmm1
mulsd  -0x58(%rbp),%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0xd8(%rbp)
ff
movsd  0xbce(%rip),%xmm0
call   1050 <log@plt>
movaps %xmm0,%xmm1
movsd  -0xd8(%rbp),%xmm0
ff
mulsd  %xmm1,%xmm0
movsd  %xmm0,-0x88(%rbp)
ff
movsd  0xba2(%rip),%xmm0
divsd  -0x20(%rbp),%xmm0
movsd  %xmm0,-0x80(%rbp)
movsd  -0x88(%rbp),%xmm1
ff
movsd  0xb80(%rip),%xmm0
divsd  -0x80(%rbp),%xmm0
ucomisd %xmm1,%xmm0
jb     15b6 <SIM_power_bitline_delay+0x466>
movsd  -0x80(%rbp),%xmm0
movsd  %xmm0,-0x68(%rbp)
movsd  0xbb7(%rip),%xmm0
movsd  %xmm0,-0x70(%rbp)
movsd  0xba2(%rip),%xmm0
mulsd  -0x88(%rbp),%xmm0
ff
movsd  0xb8a(%rip),%xmm1
divsd  -0x80(%rbp),%xmm1
movsd  0xb75(%rip),%xmm2
mulsd  %xmm2,%xmm1
movsd  0xb69(%rip),%xmm2
mulsd  %xmm2,%xmm1
movsd  0xb55(%rip),%xmm2
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x78(%rbp)
movsd  -0x70(%rbp),%xmm0
movq   %xmm0,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm0
movsd  %xmm0,-0xe8(%rbp)
ff
movsd  -0x70(%rbp),%xmm0
movsd  -0x70(%rbp),%xmm2
movsd  0xb0a(%rip),%xmm1
mulsd  -0x68(%rbp),%xmm1
mulsd  -0x78(%rbp),%xmm1
movq   %xmm1,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
call   1070 <sqrt@plt>
movaps %xmm0,%xmm1
movsd  -0xe8(%rbp),%xmm0
ff
addsd  %xmm1,%xmm0
movsd  0xa5d(%rip),%xmm1
mulsd  -0x68(%rbp),%xmm1
divsd  %xmm1,%xmm0
movsd  %xmm0,-0x28(%rbp)
jmp    15f1 <SIM_power_bitline_delay+0x4a1>
movsd  -0x88(%rbp),%xmm0
ff
movsd  0xa3a(%rip),%xmm2
mulsd  -0x80(%rbp),%xmm2
movsd  0xa8d(%rip),%xmm1
divsd  %xmm2,%xmm1
addsd  %xmm1,%xmm0
movsd  0xa75(%rip),%xmm1
divsd  -0x80(%rbp),%xmm1
subsd  %xmm1,%xmm0
movsd  %xmm0,-0x28(%rbp)
movsd  -0x28(%rbp),%xmm0
movsd  %xmm0,-0xf0(%rbp)
ff
movsd  0xa92(%rip),%xmm0
call   1050 <log@plt>
movaps %xmm0,%xmm1
movsd  -0xf0(%rbp),%xmm0
ff
divsd  %xmm1,%xmm0
mov    0x10(%rbp),%rax
movsd  %xmm0,(%rax)
movsd  -0x28(%rbp),%xmm0
add    $0xf0,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<SIM_power_bitline_delay>:
push   %rbp
push   %r15
push   %r14
push   %r12
push   %rbx
sub    $0x30,%rsp
movsd  %xmm0,0x28(%rsp)
mov    %r9d,%r15d
mov    %r8d,%ebx
mov    %edx,%r14d
mov    %esi,%ebp
mov    %edi,%r12d
movsd  0xe98(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
xorps  %xmm0,%xmm0
cvtsi2sd %eax,%xmm0
mulsd  0xe80(%rip),%xmm0
movsd  %xmm0,0x10(%rsp)
imul   %r15d,%ebx
imul   %r14d,%ebp
imul   %ebx,%ebp
mov    %r12d,%eax
cltd
idiv   %ebp
mov    %eax,%ebp
movsd  0xe67(%rip),%xmm0
xor    %edi,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
add    %eax,%eax
cvtsi2sd %ebp,%xmm1
movsd  0x10(%rsp),%xmm2
addsd  0xe4d(%rip),%xmm2
xorps  %xmm0,%xmm0
cvtsi2sd %eax,%xmm0
movsd  %xmm1,0x8(%rsp)
mulsd  %xmm1,%xmm2
addsd  %xmm0,%xmm2
movsd  %xmm2,0x10(%rsp)
cmp    $0x1,%ebx
jne    1227 <SIM_power_bitline_delay+0xe7>
movsd  0xe2d(%rip),%xmm0
movsd  0xe2d(%rip),%xmm1
mov    $0x2,%al
call   1050 <SIM_power_gatecap@plt>
mov    %eax,%ebx
add    %eax,%ebx
movsd  0x8(%rsp),%xmm0
mulsd  0xe1c(%rip),%xmm0
mulsd  0xdec(%rip),%xmm0
movsd  %xmm0,0x8(%rsp)
jmp    12dc <SIM_power_bitline_delay+0x19c>
movsd  0xde1(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
xorps  %xmm0,%xmm0
cvtsi2sd %eax,%xmm0
movsd  0x10(%rsp),%xmm1
addsd  %xmm0,%xmm1
movsd  %xmm1,0x10(%rsp)
movsd  0xdb1(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1040 <SIM_power_draincap@plt>
mov    %eax,%ebp
imul   %ebx,%ebp
movsd  0xda3(%rip),%xmm0
movsd  0xda3(%rip),%xmm1
mov    $0x2,%al
call   1050 <SIM_power_gatecap@plt>
lea    0x0(%rbp,%rax,2),%ebx
movsd  0x8(%rsp),%xmm0
mulsd  0xd92(%rip),%xmm0
mulsd  0xd62(%rip),%xmm0
movsd  %xmm0,0x8(%rsp)
movsd  0xd5c(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
xorps  %xmm0,%xmm0
cvtsi2sd %eax,%xmm0
movsd  0x8(%rsp),%xmm1
addsd  %xmm0,%xmm1
movsd  %xmm1,0x8(%rsp)
mov    0x60(%rsp),%rbp
xorps  %xmm0,%xmm0
cvtsi2sd %ebx,%xmm0
movsd  %xmm0,0x20(%rsp)
movsd  0xd0a(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
mov    %eax,%ebx
movsd  0xd27(%rip),%xmm0
mov    $0x1,%edi
mov    $0x1,%esi
mov    $0x1,%al
call   1030 <SIM_power_transreson@plt>
add    %ebx,%eax
xorps  %xmm0,%xmm0
cvtsi2sd %eax,%xmm0
movsd  0x8(%rsp),%xmm1
addsd  %xmm0,%xmm1
mulsd  0x20(%rsp),%xmm1
movsd  0x10(%rsp),%xmm2
mulsd  %xmm0,%xmm2
addsd  %xmm1,%xmm2
mulsd  0xcef(%rip),%xmm2
movsd  0xcef(%rip),%xmm3
divsd  0x28(%rsp),%xmm3
movsd  0xce9(%rip),%xmm0
divsd  %xmm3,%xmm0
ucomisd %xmm2,%xmm0
jae    139a <SIM_power_bitline_delay+0x25a>
movapd %xmm3,%xmm0
addsd  %xmm3,%xmm0
unpcklpd %xmm3,%xmm0
movapd 0xd1b(%rip),%xmm1
divpd  %xmm0,%xmm1
addsd  %xmm1,%xmm2
unpckhpd %xmm1,%xmm1
subsd  %xmm1,%xmm2
jmp    141a <SIM_power_bitline_delay+0x2da>
mulsd  0xcb6(%rip),%xmm2
movsd  0xcb6(%rip),%xmm0
divsd  %xmm3,%xmm0
movsd  0xcb2(%rip),%xmm1
mulsd  %xmm1,%xmm0
mulsd  %xmm1,%xmm0
mulsd  0xcaa(%rip),%xmm2
addsd  %xmm0,%xmm2
movsd  0xca6(%rip),%xmm0
mulsd  %xmm3,%xmm0
mulsd  %xmm2,%xmm0
addsd  0xc9e(%rip),%xmm0
xorpd  %xmm1,%xmm1
ucomisd %xmm1,%xmm0
jb     13f5 <SIM_power_bitline_delay+0x2b5>
xorps  %xmm2,%xmm2
sqrtsd %xmm0,%xmm2
jmp    140a <SIM_power_bitline_delay+0x2ca>
movapd %xmm3,0x10(%rsp)
call   1060 <sqrt@plt>
movapd 0x10(%rsp),%xmm3
movapd %xmm0,%xmm2
addsd  0xc76(%rip),%xmm2
addsd  %xmm3,%xmm3
divsd  %xmm3,%xmm2
movapd %xmm2,%xmm0
divsd  0xc6a(%rip),%xmm0
movsd  %xmm0,0x0(%rbp)
movapd %xmm2,%xmm0
add    $0x30,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define double @SIM_power_bitline_delay(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, double %6, double* %7) {
%9 = alloca i32
%10 = alloca i32
%11 = alloca i32
%12 = alloca i32
%13 = alloca i32
%14 = alloca i32
%15 = alloca double
%16 = alloca double*
%17 = alloca double
%18 = alloca double
%19 = alloca double
%20 = alloca double
%21 = alloca double
%22 = alloca double
%23 = alloca double
%24 = alloca double
%25 = alloca double
%26 = alloca double
%27 = alloca double
%28 = alloca double
%29 = alloca double
%30 = alloca double
%31 = alloca i32
%32 = alloca i32
store i32 %0, i32* %9
store i32 %1, i32* %10
store i32 %2, i32* %11
store i32 %3, i32* %12
store i32 %4, i32* %13
store i32 %5, i32* %14
store double %6, double* %15
store double* %7, double** %16
%33 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 2.100000e-01, i32 1, i32 1)
%34 = sitofp i32 %33 to double
%35 = fdiv double %34, 2.000000e+00
store double %35, double* %30
%36 = load i32, i32* %9
%37 = load i32, i32* %11
%38 = load i32, i32* %10
%39 = mul nsw i32 %37, %38
%40 = load i32, i32* %13
%41 = mul nsw i32 %39, %40
%42 = load i32, i32* %14
%43 = mul nsw i32 %41, %42
%44 = sdiv i32 %36, %43
store i32 %44, i32* %31
%45 = load i32, i32* %11
%46 = mul nsw i32 8, %45
%47 = load i32, i32* %10
%48 = mul nsw i32 %46, %47
%49 = load i32, i32* %14
%50 = mul nsw i32 %48, %49
%51 = load i32, i32* %12
%52 = sdiv i32 %50, %51
store i32 %52, i32* %32
%53 = load i32, i32* %13
%54 = load i32, i32* %14
%55 = mul nsw i32 %53, %54
%56 = icmp eq i32 %55, 1
br i1 %56, label %57, label %74
57: ; preds = %8
%58 = load i32, i32* %31
%59 = sitofp i32 %58 to double
%60 = load double, double* %30
%61 = fadd double %60, 0x3CFA20B16915269B
%62 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 0, i32 1)
%63 = mul nsw i32 2, %62
%64 = sitofp i32 %63 to double
%65 = call double @llvm.fmuladd.f64(double %59, double %61, double %64)
store double %65, double* %18
%66 = call i32 (double, double, ...) bitcast (i32 (...)* @SIM_power_gatecap to i32 (double, double, ...)*)(double 3.500000e-01, double 1.000000e+01)
%67 = mul nsw i32 2, %66
%68 = sitofp i32 %67 to double
store double %68, double* %19
%69 = load i32, i32* %31
%70 = sitofp i32 %69 to double
%71 = fmul double 0x3FD916872B020C49, %70
%72 = fdiv double %71, 2.000000e+00
store double %72, double* %20
%73 = load double, double* %20
store double %73, double* %21
br label %103
74: ; preds = %8
%75 = load i32, i32* %31
%76 = sitofp i32 %75 to double
%77 = load double, double* %30
%78 = fadd double %77, 0x3CFA20B16915269B
%79 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 0, i32 1)
%80 = mul nsw i32 2, %79
%81 = sitofp i32 %80 to double
%82 = call double @llvm.fmuladd.f64(double %76, double %78, double %81)
%83 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%84 = sitofp i32 %83 to double
%85 = fadd double %82, %84
store double %85, double* %18
%86 = load i32, i32* %14
%87 = load i32, i32* %13
%88 = mul nsw i32 %86, %87
%89 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%90 = mul nsw i32 %88, %89
%91 = call i32 (double, double, ...) bitcast (i32 (...)* @SIM_power_gatecap to i32 (double, double, ...)*)(double 3.500000e-01, double 1.000000e+01)
%92 = mul nsw i32 2, %91
%93 = add nsw i32 %90, %92
%94 = sitofp i32 %93 to double
store double %94, double* %19
%95 = load i32, i32* %31
%96 = sitofp i32 %95 to double
%97 = fmul double 0x3FD916872B020C49, %96
%98 = fdiv double %97, 2.000000e+00
store double %98, double* %20
%99 = load double, double* %20
%100 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%101 = sitofp i32 %100 to double
%102 = fadd double %99, %101
store double %102, double* %21
br label %103
103: ; preds = %74, %57
%104 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 2.100000e-01, i32 1, i32 1)
%105 = call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 4.200000e-01, i32 1, i32 1)
%106 = add nsw i32 %104, %105
%107 = sitofp i32 %106 to double
store double %107, double* %22
%108 = load double, double* %19
store double %108, double* %23
%109 = load double, double* %18
store double %109, double* %24
%110 = load double, double* %22
%111 = load double, double* %24
%112 = load double, double* %21
%113 = load double, double* %22
%114 = fadd double %112, %113
%115 = load double, double* %23
%116 = fmul double %114, %115
%117 = call double @llvm.fmuladd.f64(double %110, double %111, double %116)
%118 = call double @log(double 1.031250e+00)
%119 = fmul double %117, %118
store double %119, double* %29
%120 = load double, double* %15
%121 = fdiv double 0x3FFCCCCCCCCCCCCC, %120
store double %121, double* %28
%122 = load double, double* %29
%123 = load double, double* %28
%124 = fdiv double 0x3FE4C710CB295E9D, %123
%125 = fcmp ole double %122, %124
br i1 %125, label %126, label %150
126: ; preds = %103
%127 = load double, double* %28
store double %127, double* %25
store double 0x3FE982A9930BE0DC, double* %26
%128 = load double, double* %29
%129 = fmul double -2.000000e+00, %128
%130 = load double, double* %28
%131 = fdiv double 1.000000e+00, %130
%132 = fmul double %131, 0x3FD982A9930BE0DC
%133 = fmul double %132, 0x3FD982A9930BE0DC
%134 = call double @llvm.fmuladd.f64(double %129, double 0x3FF4C710CB295E9D, double %133)
store double %134, double* %27
%135 = load double, double* %26
%136 = fneg double %135
%137 = load double, double* %26
%138 = load double, double* %26
%139 = load double, double* %25
%140 = fmul double 4.000000e+00, %139
%141 = load double, double* %27
%142 = fmul double %140, %141
%143 = fneg double %142
%144 = call double @llvm.fmuladd.f64(double %137, double %138, double %143)
%145 = call double @sqrt(double %144)
%146 = fadd double %136, %145
%147 = load double, double* %25
%148 = fmul double 2.000000e+00, %147
%149 = fdiv double %146, %148
store double %149, double* %17
br label %159
150: ; preds = %103
%151 = load double, double* %29
%152 = load double, double* %28
%153 = fmul double 2.000000e+00, %152
%154 = fdiv double 2.301400e+00, %153
%155 = fadd double %151, %154
%156 = load double, double* %28
%157 = fdiv double 0x3FECCCCCCCCCCCCC, %156
%158 = fsub double %155, %157
store double %158, double* %17
br label %159
159: ; preds = %150, %126
%160 = load double, double* %17
%161 = call double @log(double 0x3FF5555555555555)
%162 = fdiv double %160, %161
%163 = load double*, double** %16
store double %162, double* %163
%164 = load double, double* %17
ret double %164
}

LLVM IR (-O2):
define double @SIM_power_bitline_delay(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, double %6, double* nocapture writeonly %7) {
%9 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 2.100000e-01, i32 1, i32 1)
%10 = sitofp i32 %9 to double
%11 = fmul double %10, 5.000000e-01
%12 = mul i32 %5, %4
%13 = mul i32 %12, %1
%14 = mul i32 %13, %2
%15 = sdiv i32 %0, %14
%16 = icmp eq i32 %12, 1
%17 = sitofp i32 %15 to double
%18 = fadd double %11, 0x3CFA20B16915269B
%19 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 0, i32 1)
%20 = shl nsw i32 %19, 1
%21 = sitofp i32 %20 to double
%22 = tail call double @llvm.fmuladd.f64(double %17, double %18, double %21)
br i1 %16, label %23, label %28
23: ; preds = %8
%24 = tail call i32 (double, double, ...) bitcast (i32 (...)* @SIM_power_gatecap to i32 (double, double, ...)*)(double 3.500000e-01, double 1.000000e+01)
%25 = shl nsw i32 %24, 1
%26 = fmul double %17, 0x3FD916872B020C49
%27 = fmul double %26, 5.000000e-01
br label %42
28: ; preds = %8
%29 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%30 = sitofp i32 %29 to double
%31 = fadd double %22, %30
%32 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_draincap to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%33 = mul nsw i32 %32, %12
%34 = tail call i32 (double, double, ...) bitcast (i32 (...)* @SIM_power_gatecap to i32 (double, double, ...)*)(double 3.500000e-01, double 1.000000e+01)
%35 = shl nsw i32 %34, 1
%36 = add nsw i32 %35, %33
%37 = fmul double %17, 0x3FD916872B020C49
%38 = fmul double %37, 5.000000e-01
%39 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 8.750000e-01, i32 1, i32 1)
%40 = sitofp i32 %39 to double
%41 = fadd double %38, %40
br label %42
42: ; preds = %28, %23
%43 = phi double [ %27, %23 ], [ %41, %28 ]
%44 = phi i32 [ %25, %23 ], [ %36, %28 ]
%45 = phi double [ %22, %23 ], [ %31, %28 ]
%46 = sitofp i32 %44 to double
%47 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 2.100000e-01, i32 1, i32 1)
%48 = tail call i32 (double, i32, i32, ...) bitcast (i32 (...)* @SIM_power_transreson to i32 (double, i32, i32, ...)*)(double 4.200000e-01, i32 1, i32 1)
%49 = add nsw i32 %48, %47
%50 = sitofp i32 %49 to double
%51 = fadd double %43, %50
%52 = fmul double %51, %46
%53 = tail call double @llvm.fmuladd.f64(double %50, double %45, double %52)
%54 = fmul double %53, 0x3F9F829B0E783300
%55 = fdiv double 0x3FFCCCCCCCCCCCCC, %6
%56 = fdiv double 0x3FE4C710CB295E9D, %55
%57 = fcmp ugt double %54, %56
br i1 %57, label %71, label %58
58: ; preds = %42
%59 = fmul double %54, -2.000000e+00
%60 = fdiv double 1.000000e+00, %55
%61 = fmul double %60, 0x3FD982A9930BE0DC
%62 = fmul double %61, 0x3FD982A9930BE0DC
%63 = tail call double @llvm.fmuladd.f64(double %59, double 0x3FF4C710CB295E9D, double %62)
%64 = fmul double %55, 4.000000e+00
%65 = fmul double %64, %63
%66 = fsub double 0x3FE4563E7B0FEBAC, %65
%67 = tail call double @sqrt(double %66)
%68 = fadd double %67, 0xBFE982A9930BE0DC
%69 = fmul double %55, 2.000000e+00
%70 = fdiv double %68, %69
br label %80
71: ; preds = %42
%72 = fmul double %55, 2.000000e+00
%73 = insertelement <2 x double> poison, double %72, i64 0
%74 = insertelement <2 x double> %73, double %55, i64 1
%75 = fdiv <2 x double> <double 2.301400e+00, double 0x3FECCCCCCCCCCCCC>, %74
%76 = extractelement <2 x double> %75, i64 0
%77 = fadd double %76, %54
%78 = extractelement <2 x double> %75, i64 1
%79 = fsub double %77, %78
br label %80
80: ; preds = %71, %58
%81 = phi double [ %70, %58 ], [ %79, %71 ]
%82 = fdiv double %81, 0x3FD269621134DB91
store double %82, double* %7
ret double %81
}