int guess_streamtype(int streamid) {
  if ((streamid >= (0xC0)) && (streamid < (0xC0) + (0x20))) {
    return (0x04);
  }
  if ((streamid >= (0xE0)) && (streamid < (0xE0) + (0x10))) {
    return (0x02);
  }
  switch (streamid) {
  case (0xBD):
  case (0xBF):
    return (0x06);
  case (0xF2):
    return (0x08);
  case (0xF4):
  case (0xF5):
  case (0xF6):
  case (0xF7):
  case (0xF8):
    return (0x09);
  case (0xF3):
    return (0x07);
  default:
    return (0);
  }
}


x86 assembly (clang, -O0):
<guess_streamtype>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
cmpl   $0xc0,-0x8(%rbp)
jl     112d <guess_streamtype+0x2d>
cmpl   $0xe0,-0x8(%rbp)
jge    112d <guess_streamtype+0x2d>
movl   $0x4,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
cmpl   $0xe0,-0x8(%rbp)
jl     1153 <guess_streamtype+0x53>
cmpl   $0xf0,-0x8(%rbp)
jge    1153 <guess_streamtype+0x53>
movl   $0x2,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
mov    -0x8(%rbp),%eax
add    $0xffffff43,%eax
mov    %eax,%ecx
mov    %rcx,-0x10(%rbp)
sub    $0x3b,%eax
ja     11ae <guess_streamtype+0xae>
mov    -0x10(%rbp),%rax
lea    0xe8b(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x6,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
movl   $0x8,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
movl   $0x9,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
movl   $0x7,-0x4(%rbp)
jmp    11b5 <guess_streamtype+0xb5>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<guess_streamtype>:
mov    %edi,%ecx
and    $0xffffffe0,%ecx
mov    $0x4,%eax
cmp    $0xc0,%ecx
je     1124 <guess_streamtype+0x24>
mov    %edi,%ecx
and    $0xfffffff0,%ecx
mov    $0x2,%eax
cmp    $0xe0,%ecx
jne    1125 <guess_streamtype+0x25>
ret
add    $0xffffff43,%edi
cmp    $0x3b,%edi
ja     114b <guess_streamtype+0x4b>
mov    $0x6,%eax
lea    0xec4(%rip),%rcx
movslq (%rcx,%rdi,4),%rdx
add    %rcx,%rdx
jmp    *%rdx
mov    $0x9,%eax
ret
xor    %eax,%eax
ret
mov    $0x8,%eax
ret
mov    $0x7,%eax
ret

LLVM IR (-O0):
define i32 @guess_streamtype(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp sge i32 %4, 192
br i1 %5, label %6, label %10
6: ; preds = %1
%7 = load i32, i32* %3
%8 = icmp slt i32 %7, 224
br i1 %8, label %9, label %10
9: ; preds = %6
store i32 4, i32* %2
br label %24
10: ; preds = %6, %1
%11 = load i32, i32* %3
%12 = icmp sge i32 %11, 224
br i1 %12, label %13, label %17
13: ; preds = %10
%14 = load i32, i32* %3
%15 = icmp slt i32 %14, 240
br i1 %15, label %16, label %17
16: ; preds = %13
store i32 2, i32* %2
br label %24
17: ; preds = %13, %10
%18 = load i32, i32* %3
switch i32 %18, label %23 [
i32 189, label %19
i32 191, label %19
i32 242, label %20
i32 244, label %21
i32 245, label %21
i32 246, label %21
i32 247, label %21
i32 248, label %21
i32 243, label %22
]
19: ; preds = %17, %17
store i32 6, i32* %2
br label %24
20: ; preds = %17
store i32 8, i32* %2
br label %24
21: ; preds = %17, %17, %17, %17, %17
store i32 9, i32* %2
br label %24
22: ; preds = %17
store i32 7, i32* %2
br label %24
23: ; preds = %17
store i32 0, i32* %2
br label %24
24: ; preds = %23, %22, %21, %20, %19, %16, %9
%25 = load i32, i32* %2
ret i32 %25
}

LLVM IR (-O2):
define i32 @guess_streamtype(i32 %0) {
%2 = and i32 %0, -32
%3 = icmp eq i32 %2, 192
br i1 %3, label %12, label %4
4: ; preds = %1
%5 = and i32 %0, -16
%6 = icmp eq i32 %5, 224
br i1 %6, label %12, label %7
7: ; preds = %4
switch i32 %0, label %11 [
i32 189, label %12
i32 191, label %12
i32 242, label %8
i32 244, label %9
i32 245, label %9
i32 246, label %9
i32 247, label %9
i32 248, label %9
i32 243, label %10
]
8: ; preds = %7
br label %12
9: ; preds = %7, %7, %7, %7, %7
br label %12
10: ; preds = %7
br label %12
11: ; preds = %7
br label %12
12: ; preds = %7, %7, %4, %1, %11, %10, %9, %8
%13 = phi i32 [ 0, %11 ], [ 7, %10 ], [ 9, %9 ], [ 8, %8 ], [ 4, %1 ], [ 2, %4 ], [ 6, %7 ], [ 6, %7 ]
ret i32 %13
}