int Operand_b4const_encode(unsigned int *valp) {
  unsigned r_0, b4const_0;
  b4const_0 = *valp;
  switch (b4const_0) {
  case 0xffffffff:
    r_0 = 0;
    break;
  case 0x1:
    r_0 = 0x1;
    break;
  case 0x2:
    r_0 = 0x2;
    break;
  case 0x3:
    r_0 = 0x3;
    break;
  case 0x4:
    r_0 = 0x4;
    break;
  case 0x5:
    r_0 = 0x5;
    break;
  case 0x6:
    r_0 = 0x6;
    break;
  case 0x7:
    r_0 = 0x7;
    break;
  case 0x8:
    r_0 = 0x8;
    break;
  case 0xa:
    r_0 = 0x9;
    break;
  case 0xc:
    r_0 = 0xa;
    break;
  case 0x10:
    r_0 = 0xb;
    break;
  case 0x20:
    r_0 = 0xc;
    break;
  case 0x40:
    r_0 = 0xd;
    break;
  case 0x80:
    r_0 = 0xe;
    break;
  default:
    r_0 = 0xf;
    break;
  }
  *valp = r_0;
  return 0;
}


x86 assembly (clang, -O0):
<Operand_b4const_encode>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    (%rax),%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
add    $0x1,%eax
mov    %eax,%ecx
mov    %rcx,-0x18(%rbp)
sub    $0x81,%eax
ja     11f0 <Operand_b4const_encode+0xf0>
mov    -0x18(%rbp),%rax
lea    0xecd(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x0,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x1,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x2,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x3,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x4,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x5,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x6,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x7,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x8,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0x9,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xa,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xb,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xc,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xd,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xe,-0xc(%rbp)
jmp    11f7 <Operand_b4const_encode+0xf7>
movl   $0xf,-0xc(%rbp)
mov    -0xc(%rbp),%ecx
mov    -0x8(%rbp),%rax
mov    %ecx,(%rax)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<Operand_b4const_encode>:
mov    (%rdi),%ecx
lea    0x1(%rcx),%edx
cmp    $0x81,%edx
ja     1126 <Operand_b4const_encode+0x26>
xor    %eax,%eax
lea    0xeea(%rip),%rsi
movslq (%rsi,%rdx,4),%rdx
add    %rsi,%rdx
jmp    *%rdx
mov    %ecx,%eax
mov    %eax,(%rdi)
xor    %eax,%eax
ret
mov    $0xf,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0x9,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0xa,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0xb,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0xc,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0xd,%eax
jmp    1121 <Operand_b4const_encode+0x21>
mov    $0xe,%eax
jmp    1121 <Operand_b4const_encode+0x21>

LLVM IR (-O0):
define i32 @Operand_b4const_encode(i32* %0) {
%2 = alloca i32*
%3 = alloca i32
%4 = alloca i32
store i32* %0, i32** %2
%5 = load i32*, i32** %2
%6 = load i32, i32* %5
store i32 %6, i32* %4
%7 = load i32, i32* %4
switch i32 %7, label %23 [
i32 -1, label %8
i32 1, label %9
i32 2, label %10
i32 3, label %11
i32 4, label %12
i32 5, label %13
i32 6, label %14
i32 7, label %15
i32 8, label %16
i32 10, label %17
i32 12, label %18
i32 16, label %19
i32 32, label %20
i32 64, label %21
i32 128, label %22
]
8: ; preds = %1
store i32 0, i32* %3
br label %24
9: ; preds = %1
store i32 1, i32* %3
br label %24
10: ; preds = %1
store i32 2, i32* %3
br label %24
11: ; preds = %1
store i32 3, i32* %3
br label %24
12: ; preds = %1
store i32 4, i32* %3
br label %24
13: ; preds = %1
store i32 5, i32* %3
br label %24
14: ; preds = %1
store i32 6, i32* %3
br label %24
15: ; preds = %1
store i32 7, i32* %3
br label %24
16: ; preds = %1
store i32 8, i32* %3
br label %24
17: ; preds = %1
store i32 9, i32* %3
br label %24
18: ; preds = %1
store i32 10, i32* %3
br label %24
19: ; preds = %1
store i32 11, i32* %3
br label %24
20: ; preds = %1
store i32 12, i32* %3
br label %24
21: ; preds = %1
store i32 13, i32* %3
br label %24
22: ; preds = %1
store i32 14, i32* %3
br label %24
23: ; preds = %1
store i32 15, i32* %3
br label %24
24: ; preds = %23, %22, %21, %20, %19, %18, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8
%25 = load i32, i32* %3
%26 = load i32*, i32** %2
store i32 %25, i32* %26
ret i32 0
}

LLVM IR (-O2):
define i32 @Operand_b4const_encode(i32* nocapture %0) {
%2 = load i32, i32* %0
switch i32 %2, label %17 [
i32 -1, label %18
i32 1, label %3
i32 2, label %4
i32 3, label %5
i32 4, label %6
i32 5, label %7
i32 6, label %8
i32 7, label %9
i32 8, label %10
i32 10, label %11
i32 12, label %12
i32 16, label %13
i32 32, label %14
i32 64, label %15
i32 128, label %16
]
3: ; preds = %1
br label %18
4: ; preds = %1
br label %18
5: ; preds = %1
br label %18
6: ; preds = %1
br label %18
7: ; preds = %1
br label %18
8: ; preds = %1
br label %18
9: ; preds = %1
br label %18
10: ; preds = %1
br label %18
11: ; preds = %1
br label %18
12: ; preds = %1
br label %18
13: ; preds = %1
br label %18
14: ; preds = %1
br label %18
15: ; preds = %1
br label %18
16: ; preds = %1
br label %18
17: ; preds = %1
br label %18
18: ; preds = %1, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5, %4, %3
%19 = phi i32 [ 15, %17 ], [ 14, %16 ], [ 13, %15 ], [ 12, %14 ], [ 11, %13 ], [ 10, %12 ], [ 9, %11 ], [ %2, %10 ], [ %2, %9 ], [ %2, %8 ], [ %2, %7 ], [ %2, %6 ], [ %2, %5 ], [ %2, %4 ], [ %2, %3 ], [ 0, %1 ]
store i32 %19, i32* %0
ret i32 0
}