#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int blender_read_reg(int, unsigned int *);
int blender_write_reg(int, unsigned int);
int sio_read_reg(int, unsigned long *);
int sio_write_reg(int, unsigned long);
int FS460_set_sync_delay(int delay_point, int delay_clocks) {
  int err;
  switch (delay_point) {
  case 0: {
    unsigned long reg;
    err = sio_read_reg(0x3E, &reg);
    if (err)
      return err;
    switch (0x03 & delay_clocks) {
    case 0:
      reg = (reg & ~(0x03 << 14)) | (0 << 14);
      break;
    case 1:
      reg = (reg & ~(0x03 << 14)) | (2 << 14);
      break;
    case 2:
      reg = (reg & ~(0x03 << 14)) | (1 << 14);
      break;
    case 3:
      reg = (reg & ~(0x03 << 14)) | (3 << 14);
      break;
    }
    err = sio_write_reg(0x3E, reg);
    if (err)
      return err;
  } break;
  case 1: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & delay_clocks) {
    case 0:
      reg = (reg & ~(0x03 << 4)) | (1 << 4);
      break;
    case 1:
      reg = (reg & ~(0x03 << 4)) | (0 << 4);
      break;
    case 2:
      reg = (reg & ~(0x03 << 4)) | (2 << 4);
      break;
    case 3:
      reg = (reg & ~(0x03 << 4)) | (3 << 4);
      break;
    }
    err = blender_write_reg(0x504, reg);
    if (err)
      return err;
  } break;
  case 2: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & delay_clocks) {
    case 0:
      reg = (reg & ~(0x03 << 1)) | (1 << 1);
      break;
    case 1:
      reg = (reg & ~(0x03 << 1)) | (2 << 1);
      break;
    case 2:
      reg = (reg & ~(0x03 << 1)) | (0 << 1);
      break;
    case 3:
      reg = (reg & ~(0x03 << 1)) | (3 << 1);
      break;
    }
    err = blender_write_reg(0x504, reg);
    if (err)
      return err;
  } break;
  case 3: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & delay_clocks) {
    case 0:
      reg = (reg & ~(0x03 << 14)) | (1 << 14);
      break;
    case 1:
      reg = (reg & ~(0x03 << 14)) | (0 << 14);
      break;
    case 2:
      reg = (reg & ~(0x03 << 14)) | (2 << 14);
      break;
    case 3:
      reg = (reg & ~(0x03 << 14)) | (3 << 14);
      break;
    }
    err = blender_write_reg(0x504, reg);
    if (err)
      return err;
  } break;
  }
  return 0;
}


x86 assembly (clang, -O0):
<FS460_set_sync_delay>:
push   %rbp
mov    %rsp,%rbp
sub    $0x50,%rsp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0x8(%rbp),%eax
mov    %rax,-0x30(%rbp)
sub    $0x3,%rax
ja     1478 <FS460_set_sync_delay+0x338>
mov    -0x30(%rbp),%rax
lea    0xe96(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    $0x3e,%edi
lea    -0x18(%rbp),%rsi
call   1050 <sio_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1199 <FS460_set_sync_delay+0x59>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
mov    -0xc(%rbp),%eax
and    $0x3,%eax
mov    %rax,-0x38(%rbp)
sub    $0x3,%eax
ja     121d <FS460_set_sync_delay+0xdd>
mov    -0x38(%rbp),%rax
lea    0xe89(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x18(%rbp),%rax
and    $0xffffffffffff3fff,%rax
or     $0x0,%rax
mov    %rax,-0x18(%rbp)
jmp    121d <FS460_set_sync_delay+0xdd>
mov    -0x18(%rbp),%rax
and    $0xffffffffffff3fff,%rax
or     $0x8000,%rax
mov    %rax,-0x18(%rbp)
jmp    121d <FS460_set_sync_delay+0xdd>
mov    -0x18(%rbp),%rax
and    $0xffffffffffff3fff,%rax
or     $0x4000,%rax
mov    %rax,-0x18(%rbp)
jmp    121d <FS460_set_sync_delay+0xdd>
mov    -0x18(%rbp),%rax
and    $0xffffffffffff3fff,%rax
or     $0xc000,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rsi
mov    $0x3e,%edi
call   1030 <sio_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1243 <FS460_set_sync_delay+0x103>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
jmp    1478 <FS460_set_sync_delay+0x338>
mov    $0x504,%edi
lea    -0x1c(%rbp),%rsi
call   1040 <blender_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     126e <FS460_set_sync_delay+0x12e>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
mov    -0xc(%rbp),%eax
and    $0x3,%eax
mov    %rax,-0x40(%rbp)
sub    $0x3,%eax
ja     12d4 <FS460_set_sync_delay+0x194>
mov    -0x40(%rbp),%rax
lea    0xda4(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x1c(%rbp),%eax
and    $0xffffffcf,%eax
or     $0x10,%eax
mov    %eax,-0x1c(%rbp)
jmp    12d4 <FS460_set_sync_delay+0x194>
mov    -0x1c(%rbp),%eax
and    $0xffffffcf,%eax
or     $0x0,%eax
mov    %eax,-0x1c(%rbp)
jmp    12d4 <FS460_set_sync_delay+0x194>
mov    -0x1c(%rbp),%eax
and    $0xffffffcf,%eax
or     $0x20,%eax
mov    %eax,-0x1c(%rbp)
jmp    12d4 <FS460_set_sync_delay+0x194>
mov    -0x1c(%rbp),%eax
and    $0xffffffcf,%eax
or     $0x30,%eax
mov    %eax,-0x1c(%rbp)
mov    -0x1c(%rbp),%esi
mov    $0x504,%edi
call   1060 <blender_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     12f9 <FS460_set_sync_delay+0x1b9>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
jmp    1478 <FS460_set_sync_delay+0x338>
mov    $0x504,%edi
lea    -0x20(%rbp),%rsi
call   1040 <blender_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1324 <FS460_set_sync_delay+0x1e4>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
mov    -0xc(%rbp),%eax
and    $0x3,%eax
mov    %rax,-0x48(%rbp)
sub    $0x3,%eax
ja     138a <FS460_set_sync_delay+0x24a>
mov    -0x48(%rbp),%rax
lea    0xcde(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x20(%rbp),%eax
and    $0xfffffff9,%eax
or     $0x2,%eax
mov    %eax,-0x20(%rbp)
jmp    138a <FS460_set_sync_delay+0x24a>
mov    -0x20(%rbp),%eax
and    $0xfffffff9,%eax
or     $0x4,%eax
mov    %eax,-0x20(%rbp)
jmp    138a <FS460_set_sync_delay+0x24a>
mov    -0x20(%rbp),%eax
and    $0xfffffff9,%eax
or     $0x0,%eax
mov    %eax,-0x20(%rbp)
jmp    138a <FS460_set_sync_delay+0x24a>
mov    -0x20(%rbp),%eax
and    $0xfffffff9,%eax
or     $0x6,%eax
mov    %eax,-0x20(%rbp)
mov    -0x20(%rbp),%esi
mov    $0x504,%edi
call   1060 <blender_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     13af <FS460_set_sync_delay+0x26f>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
jmp    1478 <FS460_set_sync_delay+0x338>
mov    $0x504,%edi
lea    -0x24(%rbp),%rsi
call   1040 <blender_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     13da <FS460_set_sync_delay+0x29a>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
mov    -0xc(%rbp),%eax
and    $0x3,%eax
mov    %rax,-0x50(%rbp)
sub    $0x3,%eax
ja     144e <FS460_set_sync_delay+0x30e>
mov    -0x50(%rbp),%rax
lea    0xc18(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x24(%rbp),%eax
and    $0xffff3fff,%eax
or     $0x4000,%eax
mov    %eax,-0x24(%rbp)
jmp    144e <FS460_set_sync_delay+0x30e>
mov    -0x24(%rbp),%eax
and    $0xffff3fff,%eax
or     $0x0,%eax
mov    %eax,-0x24(%rbp)
jmp    144e <FS460_set_sync_delay+0x30e>
mov    -0x24(%rbp),%eax
and    $0xffff3fff,%eax
or     $0x8000,%eax
mov    %eax,-0x24(%rbp)
jmp    144e <FS460_set_sync_delay+0x30e>
mov    -0x24(%rbp),%eax
and    $0xffff3fff,%eax
or     $0xc000,%eax
mov    %eax,-0x24(%rbp)
mov    -0x24(%rbp),%esi
mov    $0x504,%edi
call   1060 <blender_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1473 <FS460_set_sync_delay+0x333>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    147f <FS460_set_sync_delay+0x33f>
jmp    1478 <FS460_set_sync_delay+0x338>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x50,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<FS460_set_sync_delay>:
push   %rbx
sub    $0x10,%rsp
cmp    $0x3,%edi
ja     1309 <FS460_set_sync_delay+0x1c9>
mov    %esi,%ebx
mov    %edi,%eax
lea    0xea7(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
lea    0x8(%rsp),%rsi
mov    $0x3e,%edi
call   1050 <sio_read_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
and    $0x3,%ebx
lea    0xebd(%rip),%rax
movslq (%rax,%rbx,4),%rcx
add    %rax,%rcx
jmp    *%rcx
mov    $0xffffffffffff3fff,%rsi
and    0x8(%rsp),%rsi
jmp    1281 <FS460_set_sync_delay+0x141>
lea    0x8(%rsp),%rsi
mov    $0x504,%edi
call   1040 <blender_read_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
and    $0x3,%ebx
lea    0xe72(%rip),%rax
movslq (%rax,%rbx,4),%rcx
add    %rax,%rcx
jmp    *%rcx
mov    0x8(%rsp),%esi
and    $0xffffffcf,%esi
or     $0x10,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
lea    0x8(%rsp),%rsi
mov    $0x504,%edi
call   1040 <blender_read_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
and    $0x3,%ebx
lea    0xe29(%rip),%rax
movslq (%rax,%rbx,4),%rcx
add    %rax,%rcx
jmp    *%rcx
mov    0x8(%rsp),%esi
and    $0xfffffff9,%esi
or     $0x2,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
lea    0x8(%rsp),%rsi
mov    $0x504,%edi
call   1040 <blender_read_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
and    $0x3,%ebx
lea    0xde0(%rip),%rax
movslq (%rax,%rbx,4),%rcx
add    %rax,%rcx
jmp    *%rcx
mov    $0xffff3fff,%esi
and    0x8(%rsp),%esi
or     $0x4000,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    $0xffffffffffff3fff,%rsi
and    0x8(%rsp),%rsi
or     $0x8000,%rsi
jmp    1281 <FS460_set_sync_delay+0x141>
mov    $0xffffffffffff3fff,%rsi
and    0x8(%rsp),%rsi
or     $0x4000,%rsi
jmp    1281 <FS460_set_sync_delay+0x141>
mov    $0xc000,%esi
or     0x8(%rsp),%rsi
mov    %rsi,0x8(%rsp)
mov    $0x3e,%edi
call   1030 <sio_write_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
jmp    1309 <FS460_set_sync_delay+0x1c9>
mov    0x8(%rsp),%esi
and    $0xffffffcf,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    0x8(%rsp),%esi
and    $0xffffffcf,%esi
or     $0x20,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    0x8(%rsp),%esi
or     $0x30,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    0x8(%rsp),%esi
and    $0xfffffff9,%esi
or     $0x4,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    0x8(%rsp),%esi
and    $0xfffffff9,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    0x8(%rsp),%esi
or     $0x6,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    $0xffff3fff,%esi
and    0x8(%rsp),%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    $0xffff3fff,%esi
and    0x8(%rsp),%esi
or     $0x8000,%esi
jmp    12f7 <FS460_set_sync_delay+0x1b7>
mov    $0xc000,%esi
or     0x8(%rsp),%esi
mov    %esi,0x8(%rsp)
mov    $0x504,%edi
call   1060 <blender_write_reg@plt>
test   %eax,%eax
jne    130b <FS460_set_sync_delay+0x1cb>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbx
ret

LLVM IR (-O0):
define i32 @FS460_set_sync_delay(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i64
%8 = alloca i32
%9 = alloca i32
%10 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
%11 = load i32, i32* %4
switch i32 %11, label %144 [
i32 0, label %12
i32 1, label %45
i32 2, label %78
i32 3, label %111
]
12: ; preds = %2
%13 = call i32 @sio_read_reg(i32 62, i64* %7)
store i32 %13, i32* %6
%14 = load i32, i32* %6
%15 = icmp ne i32 %14, 0
br i1 %15, label %16, label %18
16: ; preds = %12
%17 = load i32, i32* %6
store i32 %17, i32* %3
br label %145
18: ; preds = %12
%19 = load i32, i32* %5
%20 = and i32 3, %19
switch i32 %20, label %37 [
i32 0, label %21
i32 1, label %25
i32 2, label %29
i32 3, label %33
]
21: ; preds = %18
%22 = load i64, i64* %7
%23 = and i64 %22, -49153
%24 = or i64 %23, 0
store i64 %24, i64* %7
br label %37
25: ; preds = %18
%26 = load i64, i64* %7
%27 = and i64 %26, -49153
%28 = or i64 %27, 32768
store i64 %28, i64* %7
br label %37
29: ; preds = %18
%30 = load i64, i64* %7
%31 = and i64 %30, -49153
%32 = or i64 %31, 16384
store i64 %32, i64* %7
br label %37
33: ; preds = %18
%34 = load i64, i64* %7
%35 = and i64 %34, -49153
%36 = or i64 %35, 49152
store i64 %36, i64* %7
br label %37
37: ; preds = %18, %33, %29, %25, %21
%38 = load i64, i64* %7
%39 = call i32 @sio_write_reg(i32 62, i64 %38)
store i32 %39, i32* %6
%40 = load i32, i32* %6
%41 = icmp ne i32 %40, 0
br i1 %41, label %42, label %44
42: ; preds = %37
%43 = load i32, i32* %6
store i32 %43, i32* %3
br label %145
44: ; preds = %37
br label %144
45: ; preds = %2
%46 = call i32 @blender_read_reg(i32 1284, i32* %8)
store i32 %46, i32* %6
%47 = load i32, i32* %6
%48 = icmp ne i32 %47, 0
br i1 %48, label %49, label %51
49: ; preds = %45
%50 = load i32, i32* %6
store i32 %50, i32* %3
br label %145
51: ; preds = %45
%52 = load i32, i32* %5
%53 = and i32 3, %52
switch i32 %53, label %70 [
i32 0, label %54
i32 1, label %58
i32 2, label %62
i32 3, label %66
]
54: ; preds = %51
%55 = load i32, i32* %8
%56 = and i32 %55, -49
%57 = or i32 %56, 16
store i32 %57, i32* %8
br label %70
58: ; preds = %51
%59 = load i32, i32* %8
%60 = and i32 %59, -49
%61 = or i32 %60, 0
store i32 %61, i32* %8
br label %70
62: ; preds = %51
%63 = load i32, i32* %8
%64 = and i32 %63, -49
%65 = or i32 %64, 32
store i32 %65, i32* %8
br label %70
66: ; preds = %51
%67 = load i32, i32* %8
%68 = and i32 %67, -49
%69 = or i32 %68, 48
store i32 %69, i32* %8
br label %70
70: ; preds = %51, %66, %62, %58, %54
%71 = load i32, i32* %8
%72 = call i32 @blender_write_reg(i32 1284, i32 %71)
store i32 %72, i32* %6
%73 = load i32, i32* %6
%74 = icmp ne i32 %73, 0
br i1 %74, label %75, label %77
75: ; preds = %70
%76 = load i32, i32* %6
store i32 %76, i32* %3
br label %145
77: ; preds = %70
br label %144
78: ; preds = %2
%79 = call i32 @blender_read_reg(i32 1284, i32* %9)
store i32 %79, i32* %6
%80 = load i32, i32* %6
%81 = icmp ne i32 %80, 0
br i1 %81, label %82, label %84
82: ; preds = %78
%83 = load i32, i32* %6
store i32 %83, i32* %3
br label %145
84: ; preds = %78
%85 = load i32, i32* %5
%86 = and i32 3, %85
switch i32 %86, label %103 [
i32 0, label %87
i32 1, label %91
i32 2, label %95
i32 3, label %99
]
87: ; preds = %84
%88 = load i32, i32* %9
%89 = and i32 %88, -7
%90 = or i32 %89, 2
store i32 %90, i32* %9
br label %103
91: ; preds = %84
%92 = load i32, i32* %9
%93 = and i32 %92, -7
%94 = or i32 %93, 4
store i32 %94, i32* %9
br label %103
95: ; preds = %84
%96 = load i32, i32* %9
%97 = and i32 %96, -7
%98 = or i32 %97, 0
store i32 %98, i32* %9
br label %103
99: ; preds = %84
%100 = load i32, i32* %9
%101 = and i32 %100, -7
%102 = or i32 %101, 6
store i32 %102, i32* %9
br label %103
103: ; preds = %84, %99, %95, %91, %87
%104 = load i32, i32* %9
%105 = call i32 @blender_write_reg(i32 1284, i32 %104)
store i32 %105, i32* %6
%106 = load i32, i32* %6
%107 = icmp ne i32 %106, 0
br i1 %107, label %108, label %110
108: ; preds = %103
%109 = load i32, i32* %6
store i32 %109, i32* %3
br label %145
110: ; preds = %103
br label %144
111: ; preds = %2
%112 = call i32 @blender_read_reg(i32 1284, i32* %10)
store i32 %112, i32* %6
%113 = load i32, i32* %6
%114 = icmp ne i32 %113, 0
br i1 %114, label %115, label %117
115: ; preds = %111
%116 = load i32, i32* %6
store i32 %116, i32* %3
br label %145
117: ; preds = %111
%118 = load i32, i32* %5
%119 = and i32 3, %118
switch i32 %119, label %136 [
i32 0, label %120
i32 1, label %124
i32 2, label %128
i32 3, label %132
]
120: ; preds = %117
%121 = load i32, i32* %10
%122 = and i32 %121, -49153
%123 = or i32 %122, 16384
store i32 %123, i32* %10
br label %136
124: ; preds = %117
%125 = load i32, i32* %10
%126 = and i32 %125, -49153
%127 = or i32 %126, 0
store i32 %127, i32* %10
br label %136
128: ; preds = %117
%129 = load i32, i32* %10
%130 = and i32 %129, -49153
%131 = or i32 %130, 32768
store i32 %131, i32* %10
br label %136
132: ; preds = %117
%133 = load i32, i32* %10
%134 = and i32 %133, -49153
%135 = or i32 %134, 49152
store i32 %135, i32* %10
br label %136
136: ; preds = %117, %132, %128, %124, %120
%137 = load i32, i32* %10
%138 = call i32 @blender_write_reg(i32 1284, i32 %137)
store i32 %138, i32* %6
%139 = load i32, i32* %6
%140 = icmp ne i32 %139, 0
br i1 %140, label %141, label %143
141: ; preds = %136
%142 = load i32, i32* %6
store i32 %142, i32* %3
br label %145
143: ; preds = %136
br label %144
144: ; preds = %2, %143, %110, %77, %44
store i32 0, i32* %3
br label %145
145: ; preds = %144, %141, %115, %108, %82, %75, %49, %42, %16
%146 = load i32, i32* %3
ret i32 %146
}

LLVM IR (-O2):
define i32 @FS460_set_sync_delay(i32 %0, i32 %1) {
%3 = alloca i64
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
switch i32 %0, label %111 [
i32 0, label %7
i32 1, label %33
i32 2, label %59
i32 3, label %85
]
7: ; preds = %2
%8 = bitcast i64* %3 to i8*
%9 = call i32 @sio_read_reg(i32 62, i64* %3)
%10 = icmp eq i32 %9, 0
br i1 %10, label %12, label %11
11: ; preds = %7
br label %112
12: ; preds = %7
%13 = and i32 %1, 3
switch i32 %13, label %28 [
i32 0, label %14
i32 1, label %17
i32 2, label %21
i32 3, label %25
]
14: ; preds = %12
%15 = load i64, i64* %3
%16 = and i64 %15, -49153
store i64 %16, i64* %3
br label %29
17: ; preds = %12
%18 = load i64, i64* %3
%19 = and i64 %18, -49153
%20 = or i64 %19, 32768
store i64 %20, i64* %3
br label %29
21: ; preds = %12
%22 = load i64, i64* %3
%23 = and i64 %22, -49153
%24 = or i64 %23, 16384
store i64 %24, i64* %3
br label %29
25: ; preds = %12
%26 = load i64, i64* %3
%27 = or i64 %26, 49152
store i64 %27, i64* %3
br label %29
28: ; preds = %12
unreachable
29: ; preds = %14, %17, %21, %25
%30 = phi i64 [ %16, %14 ], [ %20, %17 ], [ %24, %21 ], [ %27, %25 ]
%31 = call i32 @sio_write_reg(i32 62, i64 %30)
%32 = icmp eq i32 %31, 0
br i1 %32, label %111, label %112
33: ; preds = %2
%34 = bitcast i32* %4 to i8*
%35 = call i32 @blender_read_reg(i32 1284, i32* %4)
%36 = icmp eq i32 %35, 0
br i1 %36, label %38, label %37
37: ; preds = %33
br label %112
38: ; preds = %33
%39 = and i32 %1, 3
switch i32 %39, label %54 [
i32 0, label %40
i32 1, label %44
i32 2, label %47
i32 3, label %51
]
40: ; preds = %38
%41 = load i32, i32* %4
%42 = and i32 %41, -49
%43 = or i32 %42, 16
store i32 %43, i32* %4
br label %55
44: ; preds = %38
%45 = load i32, i32* %4
%46 = and i32 %45, -49
store i32 %46, i32* %4
br label %55
47: ; preds = %38
%48 = load i32, i32* %4
%49 = and i32 %48, -49
%50 = or i32 %49, 32
store i32 %50, i32* %4
br label %55
51: ; preds = %38
%52 = load i32, i32* %4
%53 = or i32 %52, 48
store i32 %53, i32* %4
br label %55
54: ; preds = %38
unreachable
55: ; preds = %40, %44, %47, %51
%56 = phi i32 [ %43, %40 ], [ %46, %44 ], [ %50, %47 ], [ %53, %51 ]
%57 = call i32 @blender_write_reg(i32 1284, i32 %56)
%58 = icmp eq i32 %57, 0
br i1 %58, label %111, label %112
59: ; preds = %2
%60 = bitcast i32* %5 to i8*
%61 = call i32 @blender_read_reg(i32 1284, i32* %5)
%62 = icmp eq i32 %61, 0
br i1 %62, label %64, label %63
63: ; preds = %59
br label %112
64: ; preds = %59
%65 = and i32 %1, 3
switch i32 %65, label %80 [
i32 0, label %66
i32 1, label %70
i32 2, label %74
i32 3, label %77
]
66: ; preds = %64
%67 = load i32, i32* %5
%68 = and i32 %67, -7
%69 = or i32 %68, 2
store i32 %69, i32* %5
br label %81
70: ; preds = %64
%71 = load i32, i32* %5
%72 = and i32 %71, -7
%73 = or i32 %72, 4
store i32 %73, i32* %5
br label %81
74: ; preds = %64
%75 = load i32, i32* %5
%76 = and i32 %75, -7
store i32 %76, i32* %5
br label %81
77: ; preds = %64
%78 = load i32, i32* %5
%79 = or i32 %78, 6
store i32 %79, i32* %5
br label %81
80: ; preds = %64
unreachable
81: ; preds = %66, %70, %74, %77
%82 = phi i32 [ %69, %66 ], [ %73, %70 ], [ %76, %74 ], [ %79, %77 ]
%83 = call i32 @blender_write_reg(i32 1284, i32 %82)
%84 = icmp eq i32 %83, 0
br i1 %84, label %111, label %112
85: ; preds = %2
%86 = bitcast i32* %6 to i8*
%87 = call i32 @blender_read_reg(i32 1284, i32* %6)
%88 = icmp eq i32 %87, 0
br i1 %88, label %90, label %89
89: ; preds = %85
br label %112
90: ; preds = %85
%91 = and i32 %1, 3
switch i32 %91, label %106 [
i32 0, label %92
i32 1, label %96
i32 2, label %99
i32 3, label %103
]
92: ; preds = %90
%93 = load i32, i32* %6
%94 = and i32 %93, -49153
%95 = or i32 %94, 16384
store i32 %95, i32* %6
br label %107
96: ; preds = %90
%97 = load i32, i32* %6
%98 = and i32 %97, -49153
store i32 %98, i32* %6
br label %107
99: ; preds = %90
%100 = load i32, i32* %6
%101 = and i32 %100, -49153
%102 = or i32 %101, 32768
store i32 %102, i32* %6
br label %107
103: ; preds = %90
%104 = load i32, i32* %6
%105 = or i32 %104, 49152
store i32 %105, i32* %6
br label %107
106: ; preds = %90
unreachable
107: ; preds = %92, %96, %99, %103
%108 = phi i32 [ %95, %92 ], [ %98, %96 ], [ %102, %99 ], [ %105, %103 ]
%109 = call i32 @blender_write_reg(i32 1284, i32 %108)
%110 = icmp eq i32 %109, 0
br i1 %110, label %111, label %112
111: ; preds = %107, %81, %55, %29, %2
br label %112
112: ; preds = %89, %63, %37, %11, %29, %55, %81, %107, %111
%113 = phi i32 [ 0, %111 ], [ %109, %107 ], [ %83, %81 ], [ %57, %55 ], [ %31, %29 ], [ %9, %11 ], [ %35, %37 ], [ %61, %63 ], [ %87, %89 ]
ret i32 %113
}