int OperU(char *s, char **ss) {
  int op = 0;
  int dd = 0;
  switch (s[0]) {
  case '+':
    op = 0xEF;
    dd = 1;
    break;
  case '-':
    op = 0xE0;
    dd = 1;
    break;
  case '~':
    op = 0xE1;
    dd = 1;
    break;
  case '!':
    op = 0xE2;
    dd = 1;
    break;
  }
  *ss = &s[dd];
  return op;
}


x86 assembly (clang, -O0):
<OperU>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
movl   $0x0,-0x14(%rbp)
movl   $0x0,-0x18(%rbp)
mov    -0x8(%rbp),%rax
movsbl (%rax),%eax
mov    %eax,-0x1c(%rbp)
sub    $0x21,%eax
je     119e <OperU+0x9e>
jmp    1132 <OperU+0x32>
mov    -0x1c(%rbp),%eax
sub    $0x2b,%eax
je     1165 <OperU+0x65>
jmp    1143 <OperU+0x43>
mov    -0x1c(%rbp),%eax
sub    $0x2d,%eax
je     1178 <OperU+0x78>
jmp    1154 <OperU+0x54>
mov    -0x1c(%rbp),%eax
sub    $0x7e,%eax
je     118b <OperU+0x8b>
jmp    11ac <OperU+0xac>
movl   $0xef,-0x14(%rbp)
movl   $0x1,-0x18(%rbp)
jmp    11ac <OperU+0xac>
movl   $0xe0,-0x14(%rbp)
movl   $0x1,-0x18(%rbp)
jmp    11ac <OperU+0xac>
movl   $0xe1,-0x14(%rbp)
movl   $0x1,-0x18(%rbp)
jmp    11ac <OperU+0xac>
movl   $0xe2,-0x14(%rbp)
movl   $0x1,-0x18(%rbp)
mov    -0x8(%rbp),%rcx
movslq -0x18(%rbp),%rax
add    %rax,%rcx
mov    -0x10(%rbp),%rax
mov    %rcx,(%rax)
mov    -0x14(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<OperU>:
movsbl (%rdi),%edx
xor    %eax,%eax
xor    %ecx,%ecx
cmp    $0x2c,%edx
jg     1122 <OperU+0x22>
cmp    $0x21,%edx
je     1138 <OperU+0x38>
cmp    $0x2b,%edx
jne    114e <OperU+0x4e>
mov    $0x1,%ecx
mov    $0xef,%eax
jmp    114e <OperU+0x4e>
cmp    $0x2d,%edx
je     1144 <OperU+0x44>
cmp    $0x7e,%edx
jne    114e <OperU+0x4e>
mov    $0x1,%ecx
mov    $0xe1,%eax
jmp    114e <OperU+0x4e>
mov    $0x1,%ecx
mov    $0xe2,%eax
jmp    114e <OperU+0x4e>
mov    $0x1,%ecx
mov    $0xe0,%eax
add    %rcx,%rdi
mov    %rdi,(%rsi)
ret

LLVM IR (-O0):
define i32 @OperU(i8* %0, i8** %1) {
%3 = alloca i8*
%4 = alloca i8**
%5 = alloca i32
%6 = alloca i32
store i8* %0, i8** %3
store i8** %1, i8*** %4
store i32 0, i32* %5
store i32 0, i32* %6
%7 = load i8*, i8** %3
%8 = getelementptr inbounds i8, i8* %7, i64 0
%9 = load i8, i8* %8
%10 = sext i8 %9 to i32
switch i32 %10, label %15 [
i32 43, label %11
i32 45, label %12
i32 126, label %13
i32 33, label %14
]
11: ; preds = %2
store i32 239, i32* %5
store i32 1, i32* %6
br label %15
12: ; preds = %2
store i32 224, i32* %5
store i32 1, i32* %6
br label %15
13: ; preds = %2
store i32 225, i32* %5
store i32 1, i32* %6
br label %15
14: ; preds = %2
store i32 226, i32* %5
store i32 1, i32* %6
br label %15
15: ; preds = %2, %14, %13, %12, %11
%16 = load i8*, i8** %3
%17 = load i32, i32* %6
%18 = sext i32 %17 to i64
%19 = getelementptr inbounds i8, i8* %16, i64 %18
%20 = load i8**, i8*** %4
store i8* %19, i8** %20
%21 = load i32, i32* %5
ret i32 %21
}

LLVM IR (-O2):
define i32 @OperU(i8* %0, i8** nocapture writeonly %1) {
%3 = load i8, i8* %0
%4 = sext i8 %3 to i32
switch i32 %4, label %9 [
i32 43, label %5
i32 45, label %6
i32 126, label %7
i32 33, label %8
]
5: ; preds = %2
br label %9
6: ; preds = %2
br label %9
7: ; preds = %2
br label %9
8: ; preds = %2
br label %9
9: ; preds = %2, %8, %7, %6, %5
%10 = phi i32 [ 0, %2 ], [ 226, %8 ], [ 225, %7 ], [ 224, %6 ], [ 239, %5 ]
%11 = phi i64 [ 0, %2 ], [ 1, %8 ], [ 1, %7 ], [ 1, %6 ], [ 1, %5 ]
%12 = getelementptr inbounds i8, i8* %0, i64 %11
store i8* %12, i8** %1
ret i32 %10
}