#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int blender_read_reg(int, unsigned int *);
int sio_read_reg(int, unsigned long *);
int FS460_get_sync_delay(int delay_point, int *p_delay_clocks) {
  int err;
  if (!p_delay_clocks)
    return 0x1000;
  switch (delay_point) {
  case 0: {
    unsigned long reg;
    err = sio_read_reg(0x3E, &reg);
    if (err)
      return err;
    switch (0x03 & (reg >> 14)) {
    case 0:
      *p_delay_clocks = 0;
      break;
    case 1:
      *p_delay_clocks = 2;
      break;
    case 2:
      *p_delay_clocks = 1;
      break;
    case 3:
      *p_delay_clocks = 3;
      break;
    }
  } break;
  case 1: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & (reg >> 4)) {
    case 0:
      *p_delay_clocks = 1;
      break;
    case 1:
      *p_delay_clocks = 0;
      break;
    case 2:
      *p_delay_clocks = 2;
      break;
    case 3:
      *p_delay_clocks = 3;
      break;
    }
  } break;
  case 2: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & (reg >> 1)) {
    case 0:
      *p_delay_clocks = 2;
      break;
    case 1:
      *p_delay_clocks = 0;
      break;
    case 2:
      *p_delay_clocks = 1;
      break;
    case 3:
      *p_delay_clocks = 3;
      break;
    }
  } break;
  case 3: {
    unsigned int reg;
    err = blender_read_reg(0x504, &reg);
    if (err)
      return err;
    switch (0x03 & (reg >> 14)) {
    case 0:
      *p_delay_clocks = 1;
      break;
    case 1:
      *p_delay_clocks = 0;
      break;
    case 2:
      *p_delay_clocks = 2;
      break;
    case 3:
      *p_delay_clocks = 3;
      break;
    }
  } break;
  }
  return 0;
}


x86 assembly (clang, -O0):
<FS460_get_sync_delay>:
push   %rbp
mov    %rsp,%rbp
sub    $0x60,%rsp
mov    %edi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x0,-0x10(%rbp)
jne    1146 <FS460_get_sync_delay+0x26>
movl   $0x1000,-0x4(%rbp)
jmp    13a9 <FS460_get_sync_delay+0x289>
mov    -0x8(%rbp),%eax
mov    %rax,-0x38(%rbp)
sub    $0x3,%rax
ja     13a2 <FS460_get_sync_delay+0x282>
mov    -0x38(%rbp),%rax
lea    0xe9e(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    $0x3e,%edi
lea    -0x20(%rbp),%rsi
call   1040 <sio_read_reg@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     1191 <FS460_get_sync_delay+0x71>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    13a9 <FS460_get_sync_delay+0x289>
mov    -0x20(%rbp),%eax
shr    $0xe,%eax
and    $0x3,%eax
mov    %eax,%ecx
mov    %rcx,-0x40(%rbp)
sub    $0x3,%eax
ja     11f4 <FS460_get_sync_delay+0xd4>
mov    -0x40(%rbp),%rax
lea    0xe8c(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x10(%rbp),%rax
movl   $0x0,(%rax)
jmp    11f4 <FS460_get_sync_delay+0xd4>
mov    -0x10(%rbp),%rax
movl   $0x2,(%rax)
jmp    11f4 <FS460_get_sync_delay+0xd4>
mov    -0x10(%rbp),%rax
movl   $0x1,(%rax)
jmp    11f4 <FS460_get_sync_delay+0xd4>
mov    -0x10(%rbp),%rax
movl   $0x3,(%rax)
jmp    13a2 <FS460_get_sync_delay+0x282>
mov    $0x504,%edi
lea    -0x24(%rbp),%rsi
call   1030 <blender_read_reg@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     121f <FS460_get_sync_delay+0xff>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    13a9 <FS460_get_sync_delay+0x289>
mov    -0x24(%rbp),%eax
shr    $0x4,%eax
and    $0x3,%eax
mov    %eax,%ecx
mov    %rcx,-0x48(%rbp)
sub    $0x3,%eax
ja     1282 <FS460_get_sync_delay+0x162>
mov    -0x48(%rbp),%rax
lea    0xdee(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x10(%rbp),%rax
movl   $0x1,(%rax)
jmp    1282 <FS460_get_sync_delay+0x162>
mov    -0x10(%rbp),%rax
movl   $0x0,(%rax)
jmp    1282 <FS460_get_sync_delay+0x162>
mov    -0x10(%rbp),%rax
movl   $0x2,(%rax)
jmp    1282 <FS460_get_sync_delay+0x162>
mov    -0x10(%rbp),%rax
movl   $0x3,(%rax)
jmp    13a2 <FS460_get_sync_delay+0x282>
mov    $0x504,%edi
lea    -0x28(%rbp),%rsi
call   1030 <blender_read_reg@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     12ad <FS460_get_sync_delay+0x18d>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    13a9 <FS460_get_sync_delay+0x289>
mov    -0x28(%rbp),%eax
shr    %eax
and    $0x3,%eax
mov    %eax,%ecx
mov    %rcx,-0x50(%rbp)
sub    $0x3,%eax
ja     130f <FS460_get_sync_delay+0x1ef>
mov    -0x50(%rbp),%rax
lea    0xd51(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x10(%rbp),%rax
movl   $0x2,(%rax)
jmp    130f <FS460_get_sync_delay+0x1ef>
mov    -0x10(%rbp),%rax
movl   $0x0,(%rax)
jmp    130f <FS460_get_sync_delay+0x1ef>
mov    -0x10(%rbp),%rax
movl   $0x1,(%rax)
jmp    130f <FS460_get_sync_delay+0x1ef>
mov    -0x10(%rbp),%rax
movl   $0x3,(%rax)
jmp    13a2 <FS460_get_sync_delay+0x282>
mov    $0x504,%edi
lea    -0x2c(%rbp),%rsi
call   1030 <blender_read_reg@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     133a <FS460_get_sync_delay+0x21a>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    13a9 <FS460_get_sync_delay+0x289>
mov    -0x2c(%rbp),%eax
shr    $0xe,%eax
and    $0x3,%eax
mov    %eax,%ecx
mov    %rcx,-0x58(%rbp)
sub    $0x3,%eax
ja     139d <FS460_get_sync_delay+0x27d>
mov    -0x58(%rbp),%rax
lea    0xcb3(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x10(%rbp),%rax
movl   $0x1,(%rax)
jmp    139d <FS460_get_sync_delay+0x27d>
mov    -0x10(%rbp),%rax
movl   $0x0,(%rax)
jmp    139d <FS460_get_sync_delay+0x27d>
mov    -0x10(%rbp),%rax
movl   $0x2,(%rax)
jmp    139d <FS460_get_sync_delay+0x27d>
mov    -0x10(%rbp),%rax
movl   $0x3,(%rax)
jmp    13a2 <FS460_get_sync_delay+0x282>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x60,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<FS460_get_sync_delay>:
push   %rbp
push   %rbx
push   %rax
test   %rsi,%rsi
je     116d <FS460_get_sync_delay+0x4d>
xor    %ebp,%ebp
cmp    $0x3,%edi
ja     11dc <FS460_get_sync_delay+0xbc>
mov    %rsi,%rbx
mov    %edi,%eax
lea    0xec1(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    %rsp,%rsi
mov    $0x3e,%edi
call   1040 <sio_read_reg@plt>
test   %eax,%eax
jne    11c2 <FS460_get_sync_delay+0xa2>
mov    (%rsp),%rax
shr    $0xc,%rax
and    $0xc,%eax
lea    0xea5(%rip),%rcx
jmp    11d7 <FS460_get_sync_delay+0xb7>
mov    $0x1000,%ebp
jmp    11dc <FS460_get_sync_delay+0xbc>
mov    %rsp,%rsi
mov    $0x504,%edi
call   1030 <blender_read_reg@plt>
test   %eax,%eax
jne    11c2 <FS460_get_sync_delay+0xa2>
mov    (%rsp),%eax
shr    $0x2,%rax
jmp    11cd <FS460_get_sync_delay+0xad>
mov    %rsp,%rsi
mov    $0x504,%edi
call   1030 <blender_read_reg@plt>
test   %eax,%eax
jne    11c2 <FS460_get_sync_delay+0xa2>
mov    (%rsp),%eax
and    $0x6,%eax
lea    0xe74(%rip),%rcx
mov    (%rcx,%rax,2),%eax
jmp    11da <FS460_get_sync_delay+0xba>
mov    %rsp,%rsi
mov    $0x504,%edi
call   1030 <blender_read_reg@plt>
test   %eax,%eax
je     11c6 <FS460_get_sync_delay+0xa6>
mov    %eax,%ebp
jmp    11dc <FS460_get_sync_delay+0xbc>
mov    (%rsp),%eax
shr    $0xc,%rax
and    $0xc,%eax
lea    0xe59(%rip),%rcx
mov    (%rax,%rcx,1),%eax
mov    %eax,(%rbx)
mov    %ebp,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
define i32 @FS460_get_sync_delay(i32 %0, i32* %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32*
%6 = alloca i32
%7 = alloca i64
%8 = alloca i32
%9 = alloca i32
%10 = alloca i32
store i32 %0, i32* %4
store i32* %1, i32** %5
%11 = load i32*, i32** %5
%12 = icmp ne i32* %11, null
br i1 %12, label %14, label %13
13: ; preds = %2
store i32 4096, i32* %3
br label %93
14: ; preds = %2
%15 = load i32, i32* %4
switch i32 %15, label %92 [
i32 0, label %16
i32 1, label %35
i32 2, label %54
i32 3, label %73
]
16: ; preds = %14
%17 = call i32 @sio_read_reg(i32 62, i64* %7)
store i32 %17, i32* %6
%18 = load i32, i32* %6
%19 = icmp ne i32 %18, 0
br i1 %19, label %20, label %22
20: ; preds = %16
%21 = load i32, i32* %6
store i32 %21, i32* %3
br label %93
22: ; preds = %16
%23 = load i64, i64* %7
%24 = lshr i64 %23, 14
%25 = and i64 3, %24
switch i64 %25, label %34 [
i64 0, label %26
i64 1, label %28
i64 2, label %30
i64 3, label %32
]
26: ; preds = %22
%27 = load i32*, i32** %5
store i32 0, i32* %27
br label %34
28: ; preds = %22
%29 = load i32*, i32** %5
store i32 2, i32* %29
br label %34
30: ; preds = %22
%31 = load i32*, i32** %5
store i32 1, i32* %31
br label %34
32: ; preds = %22
%33 = load i32*, i32** %5
store i32 3, i32* %33
br label %34
34: ; preds = %22, %32, %30, %28, %26
br label %92
35: ; preds = %14
%36 = call i32 @blender_read_reg(i32 1284, i32* %8)
store i32 %36, i32* %6
%37 = load i32, i32* %6
%38 = icmp ne i32 %37, 0
br i1 %38, label %39, label %41
39: ; preds = %35
%40 = load i32, i32* %6
store i32 %40, i32* %3
br label %93
41: ; preds = %35
%42 = load i32, i32* %8
%43 = lshr i32 %42, 4
%44 = and i32 3, %43
switch i32 %44, label %53 [
i32 0, label %45
i32 1, label %47
i32 2, label %49
i32 3, label %51
]
45: ; preds = %41
%46 = load i32*, i32** %5
store i32 1, i32* %46
br label %53
47: ; preds = %41
%48 = load i32*, i32** %5
store i32 0, i32* %48
br label %53
49: ; preds = %41
%50 = load i32*, i32** %5
store i32 2, i32* %50
br label %53
51: ; preds = %41
%52 = load i32*, i32** %5
store i32 3, i32* %52
br label %53
53: ; preds = %41, %51, %49, %47, %45
br label %92
54: ; preds = %14
%55 = call i32 @blender_read_reg(i32 1284, i32* %9)
store i32 %55, i32* %6
%56 = load i32, i32* %6
%57 = icmp ne i32 %56, 0
br i1 %57, label %58, label %60
58: ; preds = %54
%59 = load i32, i32* %6
store i32 %59, i32* %3
br label %93
60: ; preds = %54
%61 = load i32, i32* %9
%62 = lshr i32 %61, 1
%63 = and i32 3, %62
switch i32 %63, label %72 [
i32 0, label %64
i32 1, label %66
i32 2, label %68
i32 3, label %70
]
64: ; preds = %60
%65 = load i32*, i32** %5
store i32 2, i32* %65
br label %72
66: ; preds = %60
%67 = load i32*, i32** %5
store i32 0, i32* %67
br label %72
68: ; preds = %60
%69 = load i32*, i32** %5
store i32 1, i32* %69
br label %72
70: ; preds = %60
%71 = load i32*, i32** %5
store i32 3, i32* %71
br label %72
72: ; preds = %60, %70, %68, %66, %64
br label %92
73: ; preds = %14
%74 = call i32 @blender_read_reg(i32 1284, i32* %10)
store i32 %74, i32* %6
%75 = load i32, i32* %6
%76 = icmp ne i32 %75, 0
br i1 %76, label %77, label %79
77: ; preds = %73
%78 = load i32, i32* %6
store i32 %78, i32* %3
br label %93
79: ; preds = %73
%80 = load i32, i32* %10
%81 = lshr i32 %80, 14
%82 = and i32 3, %81
switch i32 %82, label %91 [
i32 0, label %83
i32 1, label %85
i32 2, label %87
i32 3, label %89
]
83: ; preds = %79
%84 = load i32*, i32** %5
store i32 1, i32* %84
br label %91
85: ; preds = %79
%86 = load i32*, i32** %5
store i32 0, i32* %86
br label %91
87: ; preds = %79
%88 = load i32*, i32** %5
store i32 2, i32* %88
br label %91
89: ; preds = %79
%90 = load i32*, i32** %5
store i32 3, i32* %90
br label %91
91: ; preds = %79, %89, %87, %85, %83
br label %92
92: ; preds = %14, %91, %72, %53, %34
store i32 0, i32* %3
br label %93
93: ; preds = %92, %77, %58, %39, %20, %13
%94 = load i32, i32* %3
ret i32 %94
}

LLVM IR (-O2):
@switch.table.FS460_get_sync_delay = [4 x i32] [i32 0, i32 2, i32 1, i32 3]
@switch.table.FS460_get_sync_delay.2 = [4 x i32] [i32 2, i32 0, i32 1, i32 3]
@switch.table.FS460_get_sync_delay.3 = [4 x i32] [i32 1, i32 0, i32 2, i32 3]
define i32 @FS460_get_sync_delay(i32 %0, i32* writeonly %1) {
%3 = alloca i64
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = icmp eq i32* %1, null
br i1 %7, label %56, label %8
8: ; preds = %2
switch i32 %0, label %56 [
i32 0, label %9
i32 1, label %19
i32 2, label %30
i32 3, label %41
]
9: ; preds = %8
%10 = bitcast i64* %3 to i8*
%11 = call i32 @sio_read_reg(i32 62, i64* %3)
%12 = icmp eq i32 %11, 0
br i1 %12, label %13, label %52
13: ; preds = %9
%14 = load i64, i64* %3
%15 = lshr i64 %14, 14
%16 = and i64 %15, 3
%17 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.FS460_get_sync_delay, i64 0, i64 %16
%18 = load i32, i32* %17
store i32 %18, i32* %1
br label %56
19: ; preds = %8
%20 = bitcast i32* %4 to i8*
%21 = call i32 @blender_read_reg(i32 1284, i32* %4)
%22 = icmp eq i32 %21, 0
br i1 %22, label %23, label %53
23: ; preds = %19
%24 = load i32, i32* %4
%25 = lshr i32 %24, 4
%26 = and i32 %25, 3
%27 = zext i32 %26 to i64
%28 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.FS460_get_sync_delay.3, i64 0, i64 %27
%29 = load i32, i32* %28
store i32 %29, i32* %1
br label %56
30: ; preds = %8
%31 = bitcast i32* %5 to i8*
%32 = call i32 @blender_read_reg(i32 1284, i32* %5)
%33 = icmp eq i32 %32, 0
br i1 %33, label %34, label %54
34: ; preds = %30
%35 = load i32, i32* %5
%36 = lshr i32 %35, 1
%37 = and i32 %36, 3
%38 = zext i32 %37 to i64
%39 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.FS460_get_sync_delay.2, i64 0, i64 %38
%40 = load i32, i32* %39
store i32 %40, i32* %1
br label %56
41: ; preds = %8
%42 = bitcast i32* %6 to i8*
%43 = call i32 @blender_read_reg(i32 1284, i32* %6)
%44 = icmp eq i32 %43, 0
br i1 %44, label %45, label %55
45: ; preds = %41
%46 = load i32, i32* %6
%47 = lshr i32 %46, 14
%48 = and i32 %47, 3
%49 = zext i32 %48 to i64
%50 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.FS460_get_sync_delay.3, i64 0, i64 %49
%51 = load i32, i32* %50
store i32 %51, i32* %1
br label %56
52: ; preds = %9
br label %56
53: ; preds = %19
br label %56
54: ; preds = %30
br label %56
55: ; preds = %41
br label %56
56: ; preds = %8, %13, %23, %34, %45, %55, %54, %53, %52, %2
%57 = phi i32 [ 4096, %2 ], [ %11, %52 ], [ %21, %53 ], [ %32, %54 ], [ %43, %55 ], [ 0, %45 ], [ 0, %34 ], [ 0, %23 ], [ 0, %13 ], [ 0, %8 ]
ret i32 %57
}