void dbg_write(unsigned long dcc_data) {
  int len = 4;
  while (len--) {
    while ((*((volatile unsigned short *)0xE000EDF8)) & 1)
      ;
    (*((volatile unsigned short *)0xE000EDF8)) =
        (unsigned short)(((dcc_data & 0xff) << 8) | 1);
    dcc_data >>= 8;
  }
}


x86 assembly (clang, -O0):
<dbg_write>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
movl   $0x4,-0xc(%rbp)
mov    -0xc(%rbp),%eax
mov    %eax,%ecx
add    $0xffffffff,%ecx
mov    %ecx,-0xc(%rbp)
cmp    $0x0,%eax
je     1172 <dbg_write+0x72>
jmp    1128 <dbg_write+0x28>
mov    $0xe000edf8,%eax
mov    (%rax),%ax
movzwl %ax,%eax
and    $0x1,%eax
cmp    $0x0,%eax
je     1144 <dbg_write+0x44>
jmp    1128 <dbg_write+0x28>
mov    -0x8(%rbp),%rax
and    $0xff,%rax
shl    $0x8,%rax
or     $0x1,%rax
mov    %ax,%cx
mov    $0xe000edf8,%eax
mov    %cx,(%rax)
mov    -0x8(%rbp),%rax
shr    $0x8,%rax
mov    %rax,-0x8(%rbp)
jmp    110f <dbg_write+0xf>
pop    %rbp
ret

x86 assembly (clang, -O2):
<dbg_write>:
mov    $0xe000edf8,%eax
cs nopw 0x0(%rax,%rax,1)
nop
movzwl (%rax),%ecx
test   $0x1,%cl
jne    1110 <dbg_write+0x10>
mov    %edi,%ecx
shl    $0x8,%ecx
or     $0x1,%ecx
mov    %cx,(%rax)
cs nopw 0x0(%rax,%rax,1)
nopl   (%rax)
movzwl (%rax),%ecx
test   $0x1,%cl
jne    1130 <dbg_write+0x30>
mov    %edi,%ecx
and    $0xffffff00,%ecx
or     $0x1,%ecx
mov    %cx,(%rax)
cs nopw 0x0(%rax,%rax,1)
movzwl (%rax),%ecx
test   $0x1,%cl
jne    1150 <dbg_write+0x50>
mov    %rdi,%rcx
shr    $0x8,%rcx
and    $0xffffff00,%ecx
or     $0x1,%ecx
mov    %cx,(%rax)
nopl   0x0(%rax,%rax,1)
movzwl (%rax),%ecx
test   $0x1,%cl
jne    1170 <dbg_write+0x70>
shr    $0x10,%rdi
and    $0xffffff00,%edi
or     $0x1,%edi
mov    %di,(%rax)
ret

LLVM IR (-O0):
define void @dbg_write(i64 %0) {
%2 = alloca i64
%3 = alloca i32
store i64 %0, i64* %2
store i32 4, i32* %3
br label %4
4: ; preds = %15, %1
%5 = load i32, i32* %3
%6 = add nsw i32 %5, -1
store i32 %6, i32* %3
%7 = icmp ne i32 %5, 0
br i1 %7, label %8, label %23
8: ; preds = %4
br label %9
9: ; preds = %14, %8
%10 = load volatile i16, i16* inttoptr (i64 3758157304 to i16*)
%11 = zext i16 %10 to i32
%12 = and i32 %11, 1
%13 = icmp ne i32 %12, 0
br i1 %13, label %14, label %15
14: ; preds = %9
br label %9
15: ; preds = %9
%16 = load i64, i64* %2
%17 = and i64 %16, 255
%18 = shl i64 %17, 8
%19 = or i64 %18, 1
%20 = trunc i64 %19 to i16
store volatile i16 %20, i16* inttoptr (i64 3758157304 to i16*)
%21 = load i64, i64* %2
%22 = lshr i64 %21, 8
store i64 %22, i64* %2
br label %4
23: ; preds = %4
ret void
}

LLVM IR (-O2):
define void @dbg_write(i64 %0) {
br label %2
2: ; preds = %1, %2
%3 = load volatile i16, i16* inttoptr (i64 3758157304 to i16*)
%4 = and i16 %3, 1
%5 = icmp eq i16 %4, 0
br i1 %5, label %6, label %2
6: ; preds = %2
%7 = trunc i64 %0 to i16
%8 = shl i16 %7, 8
%9 = or i16 %8, 1
store volatile i16 %9, i16* inttoptr (i64 3758157304 to i16*)
br label %10
10: ; preds = %10, %6
%11 = load volatile i16, i16* inttoptr (i64 3758157304 to i16*)
%12 = and i16 %11, 1
%13 = icmp eq i16 %12, 0
br i1 %13, label %14, label %10
14: ; preds = %10
%15 = trunc i64 %0 to i16
%16 = and i16 %15, -256
%17 = or i16 %16, 1
store volatile i16 %17, i16* inttoptr (i64 3758157304 to i16*)
br label %18
18: ; preds = %18, %14
%19 = load volatile i16, i16* inttoptr (i64 3758157304 to i16*)
%20 = and i16 %19, 1
%21 = icmp eq i16 %20, 0
br i1 %21, label %22, label %18
22: ; preds = %18
%23 = lshr i64 %0, 8
%24 = trunc i64 %23 to i16
%25 = and i16 %24, -256
%26 = or i16 %25, 1
store volatile i16 %26, i16* inttoptr (i64 3758157304 to i16*)
br label %27
27: ; preds = %27, %22
%28 = load volatile i16, i16* inttoptr (i64 3758157304 to i16*)
%29 = and i16 %28, 1
%30 = icmp eq i16 %29, 0
br i1 %30, label %31, label %27
31: ; preds = %27
%32 = lshr i64 %0, 16
%33 = trunc i64 %32 to i16
%34 = and i16 %33, -256
%35 = or i16 %34, 1
store volatile i16 %35, i16* inttoptr (i64 3758157304 to i16*)
ret void
}