unsigned int _avgu4(unsigned int src1, unsigned int src2) {
  unsigned int res0 = ((src1 & 0xFF) + (src2 & 0xFF) + 1) >> 1;
  unsigned int res1 =
      (((src1 & 0xFF00) >> 8) + ((src2 & 0xFF00) >> 8) + 1) >> 1;
  unsigned int res2 =
      (((src1 & 0xFF0000) >> 16) + ((src2 & 0xFF0000) >> 16) + 1) >> 1;
  unsigned int res3 =
      (((src1 & 0xFF000000) >> 24) + ((src2 & 0xFF000000) >> 24) + 1) >> 1;
  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
}


x86 assembly (clang, -O0):
<_avgu4>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x4(%rbp),%eax
and    $0xff,%eax
mov    -0x8(%rbp),%ecx
and    $0xff,%ecx
add    %ecx,%eax
add    $0x1,%eax
shr    $0x1,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
and    $0xff00,%eax
shr    $0x8,%eax
mov    -0x8(%rbp),%ecx
and    $0xff00,%ecx
shr    $0x8,%ecx
add    %ecx,%eax
add    $0x1,%eax
shr    $0x1,%eax
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
and    $0xff0000,%eax
shr    $0x10,%eax
mov    -0x8(%rbp),%ecx
and    $0xff0000,%ecx
shr    $0x10,%ecx
add    %ecx,%eax
add    $0x1,%eax
shr    $0x1,%eax
mov    %eax,-0x14(%rbp)
mov    -0x4(%rbp),%eax
and    $0xff000000,%eax
shr    $0x18,%eax
mov    -0x8(%rbp),%ecx
and    $0xff000000,%ecx
shr    $0x18,%ecx
add    %ecx,%eax
add    $0x1,%eax
shr    $0x1,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
shl    $0x18,%eax
mov    -0x14(%rbp),%ecx
shl    $0x10,%ecx
or     %ecx,%eax
mov    -0x10(%rbp),%ecx
shl    $0x8,%ecx
or     %ecx,%eax
or     -0xc(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<_avgu4>:
push   %rbx
mov    %esi,%ebx
mov    %edi,%ecx
movzbl %cl,%eax
movzbl %bl,%edx
lea    (%rax,%rdx,1),%esi
add    $0x1,%esi
shr    %esi
movzbl %ch,%edx
movzbl %bh,%eax
add    %edx,%eax
mov    %edi,%edx
shr    $0x10,%edx
movzbl %dl,%edi
mov    %ebx,%edx
shr    $0x10,%edx
movzbl %dl,%edx
add    %edi,%edx
shr    $0x18,%ecx
shr    $0x18,%ebx
add    %ebx,%ecx
shl    $0x17,%ecx
add    $0x800000,%ecx
and    $0xff000000,%ecx
or     %esi,%ecx
shl    $0xf,%edx
add    $0x8000,%edx
and    $0x1ff0000,%edx
or     %ecx,%edx
shl    $0x7,%eax
sub    $0xffffff80,%eax
and    $0x1ff00,%eax
or     %edx,%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @_avgu4(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%9 = load i32, i32* %3
%10 = and i32 %9, 255
%11 = load i32, i32* %4
%12 = and i32 %11, 255
%13 = add i32 %10, %12
%14 = add i32 %13, 1
%15 = lshr i32 %14, 1
store i32 %15, i32* %5
%16 = load i32, i32* %3
%17 = and i32 %16, 65280
%18 = lshr i32 %17, 8
%19 = load i32, i32* %4
%20 = and i32 %19, 65280
%21 = lshr i32 %20, 8
%22 = add i32 %18, %21
%23 = add i32 %22, 1
%24 = lshr i32 %23, 1
store i32 %24, i32* %6
%25 = load i32, i32* %3
%26 = and i32 %25, 16711680
%27 = lshr i32 %26, 16
%28 = load i32, i32* %4
%29 = and i32 %28, 16711680
%30 = lshr i32 %29, 16
%31 = add i32 %27, %30
%32 = add i32 %31, 1
%33 = lshr i32 %32, 1
store i32 %33, i32* %7
%34 = load i32, i32* %3
%35 = and i32 %34, -16777216
%36 = lshr i32 %35, 24
%37 = load i32, i32* %4
%38 = and i32 %37, -16777216
%39 = lshr i32 %38, 24
%40 = add i32 %36, %39
%41 = add i32 %40, 1
%42 = lshr i32 %41, 1
store i32 %42, i32* %8
%43 = load i32, i32* %8
%44 = shl i32 %43, 24
%45 = load i32, i32* %7
%46 = shl i32 %45, 16
%47 = or i32 %44, %46
%48 = load i32, i32* %6
%49 = shl i32 %48, 8
%50 = or i32 %47, %49
%51 = load i32, i32* %5
%52 = or i32 %50, %51
ret i32 %52
}

LLVM IR (-O2):
define i32 @_avgu4(i32 %0, i32 %1) {
%3 = and i32 %0, 255
%4 = and i32 %1, 255
%5 = add nuw nsw i32 %3, 1
%6 = add nuw nsw i32 %5, %4
%7 = lshr i32 %6, 1
%8 = lshr i32 %0, 8
%9 = and i32 %8, 255
%10 = lshr i32 %1, 8
%11 = and i32 %10, 255
%12 = add nuw nsw i32 %11, %9
%13 = lshr i32 %0, 16
%14 = and i32 %13, 255
%15 = lshr i32 %1, 16
%16 = and i32 %15, 255
%17 = add nuw nsw i32 %16, %14
%18 = lshr i32 %0, 24
%19 = lshr i32 %1, 24
%20 = add nuw nsw i32 %19, %18
%21 = shl nuw i32 %20, 23
%22 = add nuw i32 %21, 8388608
%23 = and i32 %22, -16777216
%24 = shl nuw nsw i32 %17, 15
%25 = add nuw nsw i32 %24, 32768
%26 = and i32 %25, 33488896
%27 = shl nuw nsw i32 %12, 7
%28 = add nuw nsw i32 %27, 128
%29 = and i32 %28, 130816
%30 = or i32 %23, %7
%31 = or i32 %30, %26
%32 = or i32 %31, %29
ret i32 %32
}