#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
float __builtin_allegrex_round_w_s(float);
float pspFpuExp(float x) {
  union {
    float f;
    int i;
  } fi;
  float z, f;
  fi.f = x;
  fi.i &= 0x7fffffff;
  if (fi.i >= 0x42b00f34) {
    if (x != x) {
      return x;
    }
    if (fi.i < 0) {
      return 0.0;
    }
    fi.i = 0x7f800000;
    return fi.f;
  }
  f = fi.f * (float)1.4426950408889634074;
  z = __builtin_allegrex_round_w_s(f);
  f = f - z;
  fi.i = z;
  if (x < 0)
    fi.i = -fi.i;
  fi.i = (fi.i + 127) << 23;
  f = (6.0f + (float)(4.0 * 0.69314718055994530942 * 0.25) * f +
       (float)(0.9996 * 0.69314718055994530942 * 0.25 * 0.69314718055994530942 *
               0.25) *
           f * f) /
      (6.0f - (float)(2.0 * 0.69314718055994530942 * 0.25) * f);
  f *= f;
  fi.f *= f * f;
  return fi.f;
}


x86 assembly (clang, -O0):
<pspFpuExp>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
movss  %xmm0,-0x8(%rbp)
movss  -0x8(%rbp),%xmm0
movss  %xmm0,-0x10(%rbp)
mov    -0x10(%rbp),%eax
and    $0x7fffffff,%eax
mov    %eax,-0x10(%rbp)
cmpl   $0x42b00f34,-0x10(%rbp)
jl     1195 <pspFpuExp+0x85>
movss  -0x8(%rbp),%xmm0
ucomiss -0x8(%rbp),%xmm0
jne    1159 <pspFpuExp+0x49>
jp     1159 <pspFpuExp+0x49>
jmp    1168 <pspFpuExp+0x58>
movss  -0x8(%rbp),%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    1278 <pspFpuExp+0x168>
cmpl   $0x0,-0x10(%rbp)
jge    117f <pspFpuExp+0x6f>
xorps  %xmm0,%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    1278 <pspFpuExp+0x168>
movl   $0x7f800000,-0x10(%rbp)
movss  -0x10(%rbp),%xmm0
movss  %xmm0,-0x4(%rbp)
jmp    1278 <pspFpuExp+0x168>
movss  0xe63(%rip),%xmm0
mulss  -0x10(%rbp),%xmm0
movss  %xmm0,-0x18(%rbp)
movss  -0x18(%rbp),%xmm0
call   1030 <__builtin_allegrex_round_w_s@plt>
movss  %xmm0,-0x14(%rbp)
movss  -0x18(%rbp),%xmm0
subss  -0x14(%rbp),%xmm0
movss  %xmm0,-0x18(%rbp)
cvttss2si -0x14(%rbp),%eax
mov    %eax,-0x10(%rbp)
xorps  %xmm0,%xmm0
ucomiss -0x8(%rbp),%xmm0
jbe    11e2 <pspFpuExp+0xd2>
xor    %eax,%eax
sub    -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
add    $0x7f,%eax
shl    $0x17,%eax
mov    %eax,-0x10(%rbp)
movss  -0x18(%rbp),%xmm1
movss  0xe15(%rip),%xmm0
mulss  %xmm0,%xmm1
movss  0xe01(%rip),%xmm0
addss  %xmm0,%xmm1
movss  0xdf9(%rip),%xmm0
mulss  -0x18(%rbp),%xmm0
movss  -0x18(%rbp),%xmm2
mulss  %xmm2,%xmm0
addss  %xmm1,%xmm0
movss  -0x18(%rbp),%xmm1
movss  0xdd2(%rip),%xmm2
mulss  %xmm2,%xmm1
movss  0xdca(%rip),%xmm2
addss  %xmm2,%xmm1
divss  %xmm1,%xmm0
movss  %xmm0,-0x18(%rbp)
movss  -0x18(%rbp),%xmm0
mulss  -0x18(%rbp),%xmm0
movss  %xmm0,-0x18(%rbp)
movss  -0x18(%rbp),%xmm0
mulss  -0x18(%rbp),%xmm0
mulss  -0x10(%rbp),%xmm0
movss  %xmm0,-0x10(%rbp)
movss  -0x10(%rbp),%xmm0
movss  %xmm0,-0x4(%rbp)
movss  -0x4(%rbp),%xmm0
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<pspFpuExp>:
push   %rax
movdqa %xmm0,%xmm3
movd   %xmm0,%eax
and    $0x7fffffff,%eax
cmp    $0x42b00f34,%eax
jb     113b <pspFpuExp+0x2b>
ucomiss %xmm3,%xmm3
jp     11c8 <pspFpuExp+0xb8>
movss  0xede(%rip),%xmm3
jmp    11c8 <pspFpuExp+0xb8>
movd   %eax,%xmm0
mulss  0xeb9(%rip),%xmm0
movss  %xmm0,0x4(%rsp)
movd   %xmm3,(%rsp)
call   1030 <__builtin_allegrex_round_w_s@plt>
cvttss2si %xmm0,%eax
mov    %eax,%ecx
neg    %ecx
xorps  %xmm1,%xmm1
ucomiss (%rsp),%xmm1
cmovbe %eax,%ecx
movss  0x4(%rsp),%xmm4
subss  %xmm0,%xmm4
shl    $0x17,%ecx
add    $0x3f800000,%ecx
movd   %ecx,%xmm0
movss  0xe7c(%rip),%xmm1
mulss  %xmm4,%xmm1
movss  0xe74(%rip),%xmm2
addss  %xmm2,%xmm1
movss  0xe6c(%rip),%xmm3
mulss  %xmm4,%xmm3
mulss  %xmm4,%xmm3
addss  %xmm1,%xmm3
mulss  0xe5c(%rip),%xmm4
addss  %xmm2,%xmm4
divss  %xmm4,%xmm3
mulss  %xmm3,%xmm3
mulss  %xmm3,%xmm3
mulss  %xmm0,%xmm3
movaps %xmm3,%xmm0
pop    %rax
ret

LLVM IR (-O0):
%union.anon = type { float }
define float @pspFpuExp(float %0) {
%2 = alloca float
%3 = alloca float
%4 = alloca %union.anon
%5 = alloca float
%6 = alloca float
store float %0, float* %3
%7 = load float, float* %3
%8 = bitcast %union.anon* %4 to float*
store float %7, float* %8
%9 = bitcast %union.anon* %4 to i32*
%10 = load i32, i32* %9
%11 = and i32 %10, 2147483647
store i32 %11, i32* %9
%12 = bitcast %union.anon* %4 to i32*
%13 = load i32, i32* %12
%14 = icmp sge i32 %13, 1118834484
br i1 %14, label %15, label %30
15: ; preds = %1
%16 = load float, float* %3
%17 = load float, float* %3
%18 = fcmp une float %16, %17
br i1 %18, label %19, label %21
19: ; preds = %15
%20 = load float, float* %3
store float %20, float* %2
br label %75
21: ; preds = %15
%22 = bitcast %union.anon* %4 to i32*
%23 = load i32, i32* %22
%24 = icmp slt i32 %23, 0
br i1 %24, label %25, label %26
25: ; preds = %21
store float 0.000000e+00, float* %2
br label %75
26: ; preds = %21
%27 = bitcast %union.anon* %4 to i32*
store i32 2139095040, i32* %27
%28 = bitcast %union.anon* %4 to float*
%29 = load float, float* %28
store float %29, float* %2
br label %75
30: ; preds = %1
%31 = bitcast %union.anon* %4 to float*
%32 = load float, float* %31
%33 = fmul float %32, 0x3FF7154760000000
store float %33, float* %6
%34 = load float, float* %6
%35 = call float @__builtin_allegrex_round_w_s(float %34)
store float %35, float* %5
%36 = load float, float* %6
%37 = load float, float* %5
%38 = fsub float %36, %37
store float %38, float* %6
%39 = load float, float* %5
%40 = fptosi float %39 to i32
%41 = bitcast %union.anon* %4 to i32*
store i32 %40, i32* %41
%42 = load float, float* %3
%43 = fcmp olt float %42, 0.000000e+00
br i1 %43, label %44, label %49
44: ; preds = %30
%45 = bitcast %union.anon* %4 to i32*
%46 = load i32, i32* %45
%47 = sub nsw i32 0, %46
%48 = bitcast %union.anon* %4 to i32*
store i32 %47, i32* %48
br label %49
49: ; preds = %44, %30
%50 = bitcast %union.anon* %4 to i32*
%51 = load i32, i32* %50
%52 = add nsw i32 %51, 127
%53 = shl i32 %52, 23
%54 = bitcast %union.anon* %4 to i32*
store i32 %53, i32* %54
%55 = load float, float* %6
%56 = call float @llvm.fmuladd.f32(float 0x3FE62E4300000000, float %55, float 6.000000e+00)
%57 = load float, float* %6
%58 = fmul float 0x3F9EBC97E0000000, %57
%59 = load float, float* %6
%60 = call float @llvm.fmuladd.f32(float %58, float %59, float %56)
%61 = load float, float* %6
%62 = call float @llvm.fmuladd.f32(float 0xBFD62E4300000000, float %61, float 6.000000e+00)
%63 = fdiv float %60, %62
store float %63, float* %6
%64 = load float, float* %6
%65 = load float, float* %6
%66 = fmul float %65, %64
store float %66, float* %6
%67 = load float, float* %6
%68 = load float, float* %6
%69 = fmul float %67, %68
%70 = bitcast %union.anon* %4 to float*
%71 = load float, float* %70
%72 = fmul float %71, %69
store float %72, float* %70
%73 = bitcast %union.anon* %4 to float*
%74 = load float, float* %73
store float %74, float* %2
br label %75
75: ; preds = %49, %26, %25, %19
%76 = load float, float* %2
ret float %76
}

LLVM IR (-O2):
define float @pspFpuExp(float %0) {
%2 = bitcast float %0 to i32
%3 = and i32 %2, 2147483647
%4 = icmp ugt i32 %3, 1118834483
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = fcmp uno float %0, 0.000000e+00
br i1 %6, label %28, label %7
7: ; preds = %5
br label %28
8: ; preds = %1
%9 = bitcast i32 %3 to float
%10 = fmul float %9, 0x3FF7154760000000
%11 = tail call float @__builtin_allegrex_round_w_s(float %10)
%12 = fsub float %10, %11
%13 = fptosi float %11 to i32
%14 = fcmp olt float %0, 0.000000e+00
%15 = sub nsw i32 0, %13
%16 = select i1 %14, i32 %15, i32 %13
%17 = shl i32 %16, 23
%18 = add i32 %17, 1065353216
%19 = bitcast i32 %18 to float
%20 = tail call float @llvm.fmuladd.f32(float %12, float 0x3FE62E4300000000, float 6.000000e+00)
%21 = fmul float %12, 0x3F9EBC97E0000000
%22 = tail call float @llvm.fmuladd.f32(float %21, float %12, float %20)
%23 = tail call float @llvm.fmuladd.f32(float %12, float 0xBFD62E4300000000, float 6.000000e+00)
%24 = fdiv float %22, %23
%25 = fmul float %24, %24
%26 = fmul float %25, %25
%27 = fmul float %26, %19
br label %28
28: ; preds = %5, %8, %7
%29 = phi float [ 0x7FF0000000000000, %7 ], [ %27, %8 ], [ %0, %5 ]
ret float %29
}