#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ DEBUG_ASSERT(int);
void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount) {
  DEBUG_ASSERT(ulBase == 0x40080000);
  DEBUG_ASSERT(ulCount <= 3);
  while ((*((volatile unsigned long *)(ulBase + 0x00000000))) & 0x00000200) {
  }
  (*((volatile unsigned long *)(ulBase + 0x00000000))) &= ~0x00000C00;
  (*((volatile unsigned long *)(ulBase + 0x00000000))) |= (ulCount << 10);
  (*((volatile unsigned long *)(ulBase + 0x00000000))) |= 0x00000200;
}


x86 assembly (clang, -O0):
<LPCSCIAssert>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x40080000,-0x8(%rbp)
40
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <DEBUG_ASSERT@plt>
cmpq   $0x3,-0x10(%rbp)
setbe  %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <DEBUG_ASSERT@plt>
mov    -0x8(%rbp),%rax
mov    (%rax),%rax
and    $0x200,%rax
cmp    $0x0,%rax
je     1163 <LPCSCIAssert+0x53>
jmp    1147 <LPCSCIAssert+0x37>
mov    -0x8(%rbp),%rax
mov    (%rax),%rcx
and    $0xfffffffffffff3ff,%rcx
mov    %rcx,(%rax)
mov    -0x10(%rbp),%rdx
shl    $0xa,%rdx
mov    -0x8(%rbp),%rax
mov    (%rax),%rcx
or     %rdx,%rcx
mov    %rcx,(%rax)
mov    -0x8(%rbp),%rax
mov    (%rax),%rcx
or     $0x200,%rcx
mov    %rcx,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<LPCSCIAssert>:
push   %r14
push   %rbx
push   %rax
mov    %rsi,%r14
mov    %rdi,%rbx
xor    %edi,%edi
cmp    $0x40080000,%rbx
sete   %dil
call   1030 <DEBUG_ASSERT@plt>
xor    %edi,%edi
cmp    $0x4,%r14
setb   %dil
call   1030 <DEBUG_ASSERT@plt>
nopl   0x0(%rax,%rax,1)
testq  $0x200,(%rbx)
jne    1140 <LPCSCIAssert+0x30>
andq   $0xfffffffffffff3ff,(%rbx)
shl    $0xa,%r14
or     %r14,(%rbx)
orq    $0x200,(%rbx)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define void @LPCSCIAssert(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%5 = load i64, i64* %3
%6 = icmp eq i64 %5, 1074266112
%7 = zext i1 %6 to i32
%8 = call i32 @DEBUG_ASSERT(i32 %7)
%9 = load i64, i64* %4
%10 = icmp ule i64 %9, 3
%11 = zext i1 %10 to i32
%12 = call i32 @DEBUG_ASSERT(i32 %11)
br label %13
13: ; preds = %20, %2
%14 = load i64, i64* %3
%15 = add i64 %14, 0
%16 = inttoptr i64 %15 to i64*
%17 = load volatile i64, i64* %16
%18 = and i64 %17, 512
%19 = icmp ne i64 %18, 0
br i1 %19, label %20, label %21
20: ; preds = %13
br label %13
21: ; preds = %13
%22 = load i64, i64* %3
%23 = add i64 %22, 0
%24 = inttoptr i64 %23 to i64*
%25 = load volatile i64, i64* %24
%26 = and i64 %25, -3073
store volatile i64 %26, i64* %24
%27 = load i64, i64* %4
%28 = shl i64 %27, 10
%29 = load i64, i64* %3
%30 = add i64 %29, 0
%31 = inttoptr i64 %30 to i64*
%32 = load volatile i64, i64* %31
%33 = or i64 %32, %28
store volatile i64 %33, i64* %31
%34 = load i64, i64* %3
%35 = add i64 %34, 0
%36 = inttoptr i64 %35 to i64*
%37 = load volatile i64, i64* %36
%38 = or i64 %37, 512
store volatile i64 %38, i64* %36
ret void
}

LLVM IR (-O2):
define void @LPCSCIAssert(i64 %0, i64 %1) {
%3 = icmp eq i64 %0, 1074266112
%4 = zext i1 %3 to i32
%5 = tail call i32 @DEBUG_ASSERT(i32 %4)
%6 = icmp ult i64 %1, 4
%7 = zext i1 %6 to i32
%8 = tail call i32 @DEBUG_ASSERT(i32 %7)
%9 = inttoptr i64 %0 to i64*
br label %10
10: ; preds = %10, %2
%11 = load volatile i64, i64* %9
%12 = and i64 %11, 512
%13 = icmp eq i64 %12, 0
br i1 %13, label %14, label %10
14: ; preds = %10
%15 = load volatile i64, i64* %9
%16 = and i64 %15, -3073
store volatile i64 %16, i64* %9
%17 = shl i64 %1, 10
%18 = load volatile i64, i64* %9
%19 = or i64 %18, %17
store volatile i64 %19, i64* %9
%20 = load volatile i64, i64* %9
%21 = or i64 %20, 512
store volatile i64 %21, i64* %9
ret void
}