#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int /*<<< orphan*/ uint8_t;
typedef int /*<<< orphan*/ uint16_t;

/* Variables and functions */
int /*<<< orphan*/ NRF24_CE_Disable();
int /*<<< orphan*/ NRF24_CE_Enable();
int /*<<< orphan*/ NRF24_Instruction(int);
int /*<<< orphan*/ NRF24_Reg_ResetBit(int, int);
int /*<<< orphan*/ NRF24_Set_RX_Addr(int /*<<< orphan*/ *, int /*<<< orphan*/);
int /*<<< orphan*/ NRF24_Set_TX_Addr(int /*<<< orphan*/ *);
int /*<<< orphan*/ NRF24_TXFIFO_Write(int /*<<< orphan*/ const *,
                                      int /*<<< orphan*/ const);
int /*<<< orphan*/ NRF24_TXFIFO_Write_NoACK(int /*<<< orphan*/ const *,
                                            int /*<<< orphan*/ const);
int /*<<< orphan*/ NRF24_Write_Reg(int, int);
void NRF24_SendPrepare(uint8_t *mac_addr, const uint8_t *pbuff,
                       const uint16_t length, const int NoACK) {
  NRF24_CE_Disable();
  NRF24_Reg_ResetBit(0x00, 0x01);
  NRF24_Instruction(0xE1);
  NRF24_Write_Reg(0x07, (1 << 4) | (1 << 5));
  NRF24_Set_TX_Addr(mac_addr);
  if (!NoACK) {
    NRF24_TXFIFO_Write(pbuff, length);
  } else {
    NRF24_Set_RX_Addr(mac_addr, 0);
    NRF24_TXFIFO_Write_NoACK(pbuff, length);
  }
  NRF24_CE_Enable();
}


x86 assembly (clang, -O0):
<NRF24_SendPrepare>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %edx,-0x14(%rbp)
mov    %ecx,-0x18(%rbp)
mov    $0x0,%al
call   1080 <NRF24_CE_Disable@plt>
xor    %edi,%edi
mov    $0x1,%esi
call   1050 <NRF24_Reg_ResetBit@plt>
mov    $0xe1,%edi
call   1040 <NRF24_Instruction@plt>
mov    $0x7,%edi
mov    $0x30,%esi
call   1090 <NRF24_Write_Reg@plt>
mov    -0x8(%rbp),%rdi
call   10a0 <NRF24_Set_TX_Addr@plt>
cmpl   $0x0,-0x18(%rbp)
jne    11f6 <NRF24_SendPrepare+0x66>
mov    -0x10(%rbp),%rdi
mov    -0x14(%rbp),%esi
call   1060 <NRF24_TXFIFO_Write@plt>
jmp    120d <NRF24_SendPrepare+0x7d>
mov    -0x8(%rbp),%rdi
xor    %esi,%esi
call   10b0 <NRF24_Set_RX_Addr@plt>
mov    -0x10(%rbp),%rdi
mov    -0x14(%rbp),%esi
call   1030 <NRF24_TXFIFO_Write_NoACK@plt>
mov    $0x0,%al
call   1070 <NRF24_CE_Enable@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<NRF24_SendPrepare>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
mov    %ecx,%ebx
mov    %edx,%r14d
mov    %rsi,%r15
mov    %rdi,%rbp
xor    %eax,%eax
call   1080 <NRF24_CE_Disable@plt>
xor    %edi,%edi
mov    $0x1,%esi
call   1050 <NRF24_Reg_ResetBit@plt>
mov    $0xe1,%edi
call   1040 <NRF24_Instruction@plt>
mov    $0x7,%edi
mov    $0x30,%esi
call   1090 <NRF24_Write_Reg@plt>
mov    %rbp,%rdi
call   10a0 <NRF24_Set_TX_Addr@plt>
test   %ebx,%ebx
je     11f1 <NRF24_SendPrepare+0x61>
mov    %rbp,%rdi
xor    %esi,%esi
call   10b0 <NRF24_Set_RX_Addr@plt>
mov    %r15,%rdi
mov    %r14d,%esi
call   1030 <NRF24_TXFIFO_Write_NoACK@plt>
jmp    11fc <NRF24_SendPrepare+0x6c>
mov    %r15,%rdi
mov    %r14d,%esi
call   1060 <NRF24_TXFIFO_Write@plt>
xor    %eax,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
jmp    1070 <NRF24_CE_Enable@plt>

LLVM IR (-O0):
define void @NRF24_SendPrepare(i32* %0, i32* %1, i32 %2, i32 %3) {
%5 = alloca i32*
%6 = alloca i32*
%7 = alloca i32
%8 = alloca i32
store i32* %0, i32** %5
store i32* %1, i32** %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%9 = call i32 (...) @NRF24_CE_Disable()
%10 = call i32 @NRF24_Reg_ResetBit(i32 0, i32 1)
%11 = call i32 @NRF24_Instruction(i32 225)
%12 = call i32 @NRF24_Write_Reg(i32 7, i32 48)
%13 = load i32*, i32** %5
%14 = call i32 @NRF24_Set_TX_Addr(i32* %13)
%15 = load i32, i32* %8
%16 = icmp ne i32 %15, 0
br i1 %16, label %21, label %17
17: ; preds = %4
%18 = load i32*, i32** %6
%19 = load i32, i32* %7
%20 = call i32 @NRF24_TXFIFO_Write(i32* %18, i32 %19)
br label %27
21: ; preds = %4
%22 = load i32*, i32** %5
%23 = call i32 @NRF24_Set_RX_Addr(i32* %22, i32 0)
%24 = load i32*, i32** %6
%25 = load i32, i32* %7
%26 = call i32 @NRF24_TXFIFO_Write_NoACK(i32* %24, i32 %25)
br label %27
27: ; preds = %21, %17
%28 = call i32 (...) @NRF24_CE_Enable()
ret void
}

LLVM IR (-O2):
define void @NRF24_SendPrepare(i32* %0, i32* %1, i32 %2, i32 %3) {
%5 = tail call i32 (...) @NRF24_CE_Disable()
%6 = tail call i32 @NRF24_Reg_ResetBit(i32 0, i32 1)
%7 = tail call i32 @NRF24_Instruction(i32 225)
%8 = tail call i32 @NRF24_Write_Reg(i32 7, i32 48)
%9 = tail call i32 @NRF24_Set_TX_Addr(i32* %0)
%10 = icmp eq i32 %3, 0
br i1 %10, label %11, label %13
11: ; preds = %4
%12 = tail call i32 @NRF24_TXFIFO_Write(i32* %1, i32 %2)
br label %16
13: ; preds = %4
%14 = tail call i32 @NRF24_Set_RX_Addr(i32* %0, i32 0)
%15 = tail call i32 @NRF24_TXFIFO_Write_NoACK(i32* %1, i32 %2)
br label %16
16: ; preds = %13, %11
%17 = tail call i32 (...) @NRF24_CE_Enable()
ret void
}