int iw_ordered_dither(int dithersubtype, double fraction, int x, int y) {
  double threshold;
  static const float pattern[2][64] = {
      {0.5 / 64,  48.5 / 64, 12.5 / 64, 60.5 / 64, 3.5 / 64,  51.5 / 64,
       15.5 / 64, 63.5 / 64, 32.5 / 64, 16.5 / 64, 44.5 / 64, 28.5 / 64,
       35.5 / 64, 19.5 / 64, 47.5 / 64, 31.5 / 64, 8.5 / 64,  56.5 / 64,
       4.5 / 64,  52.5 / 64, 11.5 / 64, 59.5 / 64, 7.5 / 64,  55.5 / 64,
       40.5 / 64, 24.5 / 64, 36.5 / 64, 20.5 / 64, 43.5 / 64, 27.5 / 64,
       39.5 / 64, 23.5 / 64, 2.5 / 64,  50.5 / 64, 14.5 / 64, 62.5 / 64,
       1.5 / 64,  49.5 / 64, 13.5 / 64, 61.5 / 64, 34.5 / 64, 18.5 / 64,
       46.5 / 64, 30.5 / 64, 33.5 / 64, 17.5 / 64, 45.5 / 64, 29.5 / 64,
       10.5 / 64, 58.5 / 64, 6.5 / 64,  54.5 / 64, 9.5 / 64,  57.5 / 64,
       5.5 / 64,  53.5 / 64, 42.5 / 64, 26.5 / 64, 38.5 / 64, 22.5 / 64,
       41.5 / 64, 25.5 / 64, 37.5 / 64, 21.5 / 64},
      {3.5 / 64,  9.5 / 64,  17.5 / 64, 27.5 / 64, 25.5 / 64, 15.5 / 64,
       7.5 / 64,  1.5 / 64,  11.5 / 64, 29.5 / 64, 37.5 / 64, 45.5 / 64,
       43.5 / 64, 35.5 / 64, 23.5 / 64, 5.5 / 64,  19.5 / 64, 39.5 / 64,
       51.5 / 64, 57.5 / 64, 55.5 / 64, 49.5 / 64, 33.5 / 64, 13.5 / 64,
       31.5 / 64, 47.5 / 64, 59.5 / 64, 63.5 / 64, 61.5 / 64, 53.5 / 64,
       41.5 / 64, 21.5 / 64, 30.5 / 64, 46.5 / 64, 58.5 / 64, 62.5 / 64,
       60.5 / 64, 52.5 / 64, 40.5 / 64, 20.5 / 64, 18.5 / 64, 38.5 / 64,
       50.5 / 64, 56.5 / 64, 54.5 / 64, 48.5 / 64, 32.5 / 64, 12.5 / 64,
       10.5 / 64, 28.5 / 64, 36.5 / 64, 44.5 / 64, 42.5 / 64, 34.5 / 64,
       22.5 / 64, 4.5 / 64,  2.5 / 64,  8.5 / 64,  16.5 / 64, 26.5 / 64,
       24.5 / 64, 14.5 / 64, 6.5 / 64,  0.5 / 64}};
  threshold = pattern[dithersubtype][(x % 8) + 8 * (y % 8)];
  return (fraction >= threshold);
}


x86 assembly (clang, -O0):
<iw_ordered_dither>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
movsd  %xmm0,-0x10(%rbp)
mov    %esi,-0x14(%rbp)
mov    %edx,-0x18(%rbp)
movslq -0x4(%rbp),%rcx
lea    0xee3(%rip),%rax
shl    $0x8,%rcx
add    %rcx,%rax
mov    %rax,-0x30(%rbp)
mov    -0x14(%rbp),%eax
mov    $0x8,%ecx
cltd
idiv   %ecx
mov    %edx,-0x24(%rbp)
mov    -0x18(%rbp),%eax
mov    $0x8,%ecx
cltd
idiv   %ecx
mov    -0x30(%rbp),%rax
mov    %edx,%ecx
mov    -0x24(%rbp),%edx
shl    $0x3,%ecx
add    %ecx,%edx
movslq %edx,%rcx
movss  (%rax,%rcx,4),%xmm0
cvtss2sd %xmm0,%xmm0
movsd  %xmm0,-0x20(%rbp)
movsd  -0x10(%rbp),%xmm0
ucomisd -0x20(%rbp),%xmm0
setae  %al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<iw_ordered_dither>:
lea    0x7(%rsi),%eax
test   %esi,%esi
cmovns %esi,%eax
movslq %edi,%rcx
and    $0xfffffff8,%eax
sub    %eax,%esi
lea    0x7(%rdx),%eax
test   %edx,%edx
cmovns %edx,%eax
and    $0x1ffffff8,%eax
sub    %eax,%edx
lea    (%rsi,%rdx,8),%eax
cltq
shl    $0x8,%rcx
lea    0xed1(%rip),%rdx
add    %rcx,%rdx
movss  (%rdx,%rax,4),%xmm1
cvtss2sd %xmm1,%xmm1
xor    %eax,%eax
ucomisd %xmm1,%xmm0
setae  %al
ret

LLVM IR (-O0):
@iw_ordered_dither.pattern = internal constant [2 x [64 x float]] [[64 x float] [float 7.812500e-03, float 0x3FE8400000000000, float 0x3FC9000000000000, float 0x3FEE400000000000, float 5.468750e-02, float 0x3FE9C00000000000, float 0x3FCF000000000000, float 0x3FEFC00000000000, float 0x3FE0400000000000, float 0x3FD0800000000000, float 0x3FE6400000000000, float 0x3FDC800000000000, float 0x3FE1C00000000000, float 0x3FD3800000000000, float 0x3FE7C00000000000, float 0x3FDF800000000000, float 0x3FC1000000000000, float 0x3FEC400000000000, float 7.031250e-02, float 0x3FEA400000000000, float 0x3FC7000000000000, float 0x3FEDC00000000000, float 0x3FBE000000000000, float 0x3FEBC00000000000, float 0x3FE4400000000000, float 0x3FD8800000000000, float 0x3FE2400000000000, float 0x3FD4800000000000, float 0x3FE5C00000000000, float 0x3FDB800000000000, float 0x3FE3C00000000000, float 0x3FD7800000000000, float 3.906250e-02, float 0x3FE9400000000000, float 0x3FCD000000000000, float 0x3FEF400000000000, float 2.343750e-02, float 0x3FE8C00000000000, float 0x3FCB000000000000, float 0x3FEEC00000000000, float 0x3FE1400000000000, float 0x3FD2800000000000, float 0x3FE7400000000000, float 0x3FDE800000000000, float 0x3FE0C00000000000, float 0x3FD1800000000000, float 0x3FE6C00000000000, float 0x3FDD800000000000, float 0x3FC5000000000000, float 0x3FED400000000000, float 0x3FBA000000000000, float 0x3FEB400000000000, float 0x3FC3000000000000, float 0x3FECC00000000000, float 8.593750e-02, float 0x3FEAC00000000000, float 0x3FE5400000000000, float 0x3FDA800000000000, float 0x3FE3400000000000, float 0x3FD6800000000000, float 0x3FE4C00000000000, float 0x3FD9800000000000, float 0x3FE2C00000000000, float 0x3FD5800000000000], [64 x float] [float 5.468750e-02, float 0x3FC3000000000000, float 0x3FD1800000000000, float 0x3FDB800000000000, float 0x3FD9800000000000, float 0x3FCF000000000000, float 0x3FBE000000000000, float 2.343750e-02, float 0x3FC7000000000000, float 0x3FDD800000000000, float 0x3FE2C00000000000, float 0x3FE6C00000000000, float 0x3FE5C00000000000, float 0x3FE1C00000000000, float 0x3FD7800000000000, float 8.593750e-02, float 0x3FD3800000000000, float 0x3FE3C00000000000, float 0x3FE9C00000000000, float 0x3FECC00000000000, float 0x3FEBC00000000000, float 0x3FE8C00000000000, float 0x3FE0C00000000000, float 0x3FCB000000000000, float 0x3FDF800000000000, float 0x3FE7C00000000000, float 0x3FEDC00000000000, float 0x3FEFC00000000000, float 0x3FEEC00000000000, float 0x3FEAC00000000000, float 0x3FE4C00000000000, float 0x3FD5800000000000, float 0x3FDE800000000000, float 0x3FE7400000000000, float 0x3FED400000000000, float 0x3FEF400000000000, float 0x3FEE400000000000, float 0x3FEA400000000000, float 0x3FE4400000000000, float 0x3FD4800000000000, float 0x3FD2800000000000, float 0x3FE3400000000000, float 0x3FE9400000000000, float 0x3FEC400000000000, float 0x3FEB400000000000, float 0x3FE8400000000000, float 0x3FE0400000000000, float 0x3FC9000000000000, float 0x3FC5000000000000, float 0x3FDC800000000000, float 0x3FE2400000000000, float 0x3FE6400000000000, float 0x3FE5400000000000, float 0x3FE1400000000000, float 0x3FD6800000000000, float 7.031250e-02, float 3.906250e-02, float 0x3FC1000000000000, float 0x3FD0800000000000, float 0x3FDA800000000000, float 0x3FD8800000000000, float 0x3FCD000000000000, float 0x3FBA000000000000, float 7.812500e-03]]
define i32 @iw_ordered_dither(i32 %0, double %1, i32 %2, i32 %3) {
%5 = alloca i32
%6 = alloca double
%7 = alloca i32
%8 = alloca i32
%9 = alloca double
store i32 %0, i32* %5
store double %1, double* %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%10 = load i32, i32* %5
%11 = sext i32 %10 to i64
%12 = getelementptr inbounds [2 x [64 x float]], [2 x [64 x float]]* @iw_ordered_dither.pattern, i64 0, i64 %11
%13 = load i32, i32* %7
%14 = srem i32 %13, 8
%15 = load i32, i32* %8
%16 = srem i32 %15, 8
%17 = mul nsw i32 8, %16
%18 = add nsw i32 %14, %17
%19 = sext i32 %18 to i64
%20 = getelementptr inbounds [64 x float], [64 x float]* %12, i64 0, i64 %19
%21 = load float, float* %20
%22 = fpext float %21 to double
store double %22, double* %9
%23 = load double, double* %6
%24 = load double, double* %9
%25 = fcmp oge double %23, %24
%26 = zext i1 %25 to i32
ret i32 %26
}

LLVM IR (-O2):
@iw_ordered_dither.pattern = internal unnamed_addr constant [2 x [64 x float]] [[64 x float] [float 7.812500e-03, float 0x3FE8400000000000, float 0x3FC9000000000000, float 0x3FEE400000000000, float 5.468750e-02, float 0x3FE9C00000000000, float 0x3FCF000000000000, float 0x3FEFC00000000000, float 0x3FE0400000000000, float 0x3FD0800000000000, float 0x3FE6400000000000, float 0x3FDC800000000000, float 0x3FE1C00000000000, float 0x3FD3800000000000, float 0x3FE7C00000000000, float 0x3FDF800000000000, float 0x3FC1000000000000, float 0x3FEC400000000000, float 7.031250e-02, float 0x3FEA400000000000, float 0x3FC7000000000000, float 0x3FEDC00000000000, float 0x3FBE000000000000, float 0x3FEBC00000000000, float 0x3FE4400000000000, float 0x3FD8800000000000, float 0x3FE2400000000000, float 0x3FD4800000000000, float 0x3FE5C00000000000, float 0x3FDB800000000000, float 0x3FE3C00000000000, float 0x3FD7800000000000, float 3.906250e-02, float 0x3FE9400000000000, float 0x3FCD000000000000, float 0x3FEF400000000000, float 2.343750e-02, float 0x3FE8C00000000000, float 0x3FCB000000000000, float 0x3FEEC00000000000, float 0x3FE1400000000000, float 0x3FD2800000000000, float 0x3FE7400000000000, float 0x3FDE800000000000, float 0x3FE0C00000000000, float 0x3FD1800000000000, float 0x3FE6C00000000000, float 0x3FDD800000000000, float 0x3FC5000000000000, float 0x3FED400000000000, float 0x3FBA000000000000, float 0x3FEB400000000000, float 0x3FC3000000000000, float 0x3FECC00000000000, float 8.593750e-02, float 0x3FEAC00000000000, float 0x3FE5400000000000, float 0x3FDA800000000000, float 0x3FE3400000000000, float 0x3FD6800000000000, float 0x3FE4C00000000000, float 0x3FD9800000000000, float 0x3FE2C00000000000, float 0x3FD5800000000000], [64 x float] [float 5.468750e-02, float 0x3FC3000000000000, float 0x3FD1800000000000, float 0x3FDB800000000000, float 0x3FD9800000000000, float 0x3FCF000000000000, float 0x3FBE000000000000, float 2.343750e-02, float 0x3FC7000000000000, float 0x3FDD800000000000, float 0x3FE2C00000000000, float 0x3FE6C00000000000, float 0x3FE5C00000000000, float 0x3FE1C00000000000, float 0x3FD7800000000000, float 8.593750e-02, float 0x3FD3800000000000, float 0x3FE3C00000000000, float 0x3FE9C00000000000, float 0x3FECC00000000000, float 0x3FEBC00000000000, float 0x3FE8C00000000000, float 0x3FE0C00000000000, float 0x3FCB000000000000, float 0x3FDF800000000000, float 0x3FE7C00000000000, float 0x3FEDC00000000000, float 0x3FEFC00000000000, float 0x3FEEC00000000000, float 0x3FEAC00000000000, float 0x3FE4C00000000000, float 0x3FD5800000000000, float 0x3FDE800000000000, float 0x3FE7400000000000, float 0x3FED400000000000, float 0x3FEF400000000000, float 0x3FEE400000000000, float 0x3FEA400000000000, float 0x3FE4400000000000, float 0x3FD4800000000000, float 0x3FD2800000000000, float 0x3FE3400000000000, float 0x3FE9400000000000, float 0x3FEC400000000000, float 0x3FEB400000000000, float 0x3FE8400000000000, float 0x3FE0400000000000, float 0x3FC9000000000000, float 0x3FC5000000000000, float 0x3FDC800000000000, float 0x3FE2400000000000, float 0x3FE6400000000000, float 0x3FE5400000000000, float 0x3FE1400000000000, float 0x3FD6800000000000, float 7.031250e-02, float 3.906250e-02, float 0x3FC1000000000000, float 0x3FD0800000000000, float 0x3FDA800000000000, float 0x3FD8800000000000, float 0x3FCD000000000000, float 0x3FBA000000000000, float 7.812500e-03]]
define i32 @iw_ordered_dither(i32 %0, double %1, i32 %2, i32 %3) {
%5 = sext i32 %0 to i64
%6 = srem i32 %2, 8
%7 = srem i32 %3, 8
%8 = shl nsw i32 %7, 3
%9 = add nsw i32 %8, %6
%10 = sext i32 %9 to i64
%11 = getelementptr inbounds [2 x [64 x float]], [2 x [64 x float]]* @iw_ordered_dither.pattern, i64 0, i64 %5, i64 %10
%12 = load float, float* %11
%13 = fpext float %12 to double
%14 = fcmp ole double %13, %1
%15 = zext i1 %14 to i32
ret i32 %15
}