#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
unsigned int UARTOperatingModeSelect(unsigned int, unsigned int volatile);
unsigned int UARTRegConfigModeEnable(unsigned int, int);
unsigned int UARTDivisorLatchWrite(unsigned int baseAdd,
                                   unsigned int divisorValue) {
  volatile unsigned int enhanFnBitVal = 0;
  volatile unsigned int sleepMdBitVal = 0;
  volatile unsigned int lcrRegValue = 0;
  volatile unsigned int operMode = 0;
  unsigned int divRegVal = 0;
  lcrRegValue = UARTRegConfigModeEnable(baseAdd, (0x00BF));
  enhanFnBitVal =
      (*((volatile unsigned int *)(baseAdd + (0x8)))) & (0x00000010u);
  (*((volatile unsigned int *)(baseAdd + (0x8)))) |= (0x00000010u);
  UARTRegConfigModeEnable(baseAdd, (0x007F));
  sleepMdBitVal =
      (*((volatile unsigned int *)(baseAdd + (0x4)))) & (0x00000010u);
  (*((volatile unsigned int *)(baseAdd + (0x4)))) &= ~((0x00000010u));
  UARTRegConfigModeEnable(baseAdd, (0x00BF));
  divRegVal = (*((volatile unsigned int *)(baseAdd + (0x0)))) & 0xFF;
  divRegVal |= (((*((volatile unsigned int *)(baseAdd + (0x4)))) & 0x3F) << 8);
  operMode = UARTOperatingModeSelect(baseAdd, (0x7u));
  (*((volatile unsigned int *)(baseAdd + (0x0)))) = (divisorValue & 0x00FF);
  (*((volatile unsigned int *)(baseAdd + (0x4)))) =
      ((divisorValue & 0x3F00) >> 8);
  UARTOperatingModeSelect(baseAdd, operMode);
  UARTRegConfigModeEnable(baseAdd, (0x007F));
  (*((volatile unsigned int *)(baseAdd + (0x4)))) |= sleepMdBitVal;
  UARTRegConfigModeEnable(baseAdd, (0x00BF));
  (*((volatile unsigned int *)(baseAdd + (0x8)))) &= ~((0x00000010u));
  (*((volatile unsigned int *)(baseAdd + (0x8)))) |= enhanFnBitVal;
  (*((volatile unsigned int *)(baseAdd + (0xC)))) = lcrRegValue;
  return divRegVal;
}


x86 assembly (clang, -O0):
<UARTDivisorLatchWrite>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
movl   $0x0,-0x10(%rbp)
movl   $0x0,-0x14(%rbp)
movl   $0x0,-0x18(%rbp)
movl   $0x0,-0x1c(%rbp)
mov    -0x4(%rbp),%edi
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    %eax,-0x14(%rbp)
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x10,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x10,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    $0x7f,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    -0x4(%rbp),%eax
add    $0x4,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x10,%eax
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
add    $0x4,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xffffffef,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    -0x4(%rbp),%eax
add    $0x0,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0xff,%eax
mov    %eax,-0x1c(%rbp)
mov    -0x4(%rbp),%eax
add    $0x4,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x3f,%eax
shl    $0x8,%eax
or     -0x1c(%rbp),%eax
mov    %eax,-0x1c(%rbp)
mov    -0x4(%rbp),%edi
mov    $0x7,%esi
call   1030 <UARTOperatingModeSelect@plt>
mov    %eax,-0x18(%rbp)
mov    -0x8(%rbp),%ecx
and    $0xff,%ecx
mov    -0x4(%rbp),%eax
add    $0x0,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    -0x8(%rbp),%ecx
and    $0x3f00,%ecx
shr    $0x8,%ecx
mov    -0x4(%rbp),%eax
add    $0x4,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    -0x18(%rbp),%esi
call   1030 <UARTOperatingModeSelect@plt>
mov    -0x4(%rbp),%edi
mov    $0x7f,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    -0x10(%rbp),%edx
mov    -0x4(%rbp),%eax
add    $0x4,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     %edx,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xffffffef,%ecx
mov    %ecx,(%rax)
mov    -0xc(%rbp),%edx
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     %edx,%ecx
mov    %ecx,(%rax)
mov    -0x14(%rbp),%ecx
mov    -0x4(%rbp),%eax
add    $0xc,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    -0x1c(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTDivisorLatchWrite>:
push   %rbp
push   %r15
push   %r14
push   %r13
push   %r12
push   %rbx
sub    $0x18,%rsp
mov    %esi,%r14d
mov    %edi,%ebx
movl   $0x0,0x14(%rsp)
movl   $0x0,0x10(%rsp)
movl   $0x0,0xc(%rsp)
movl   $0x0,0x8(%rsp)
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    %eax,0xc(%rsp)
lea    0x8(%rbx),%r15d
mov    (%r15),%eax
and    $0x10,%eax
mov    %eax,0x14(%rsp)
orl    $0x10,(%r15)
mov    %ebx,%edi
mov    $0x7f,%esi
call   1040 <UARTRegConfigModeEnable@plt>
lea    0x4(%rbx),%r12d
mov    (%r12),%eax
and    $0x10,%eax
mov    %eax,0x10(%rsp)
andl   $0xffffffef,(%r12)
mov    %ebx,%edi
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    %ebx,%r13d
mov    0x0(%r13),%eax
movzbl %al,%eax
mov    (%r12),%ebp
and    $0x3f,%ebp
shl    $0x8,%ebp
or     %eax,%ebp
mov    %ebx,%edi
mov    $0x7,%esi
call   1030 <UARTOperatingModeSelect@plt>
mov    %eax,0x8(%rsp)
movzbl %r14b,%eax
mov    %eax,0x0(%r13)
shr    $0x8,%r14d
and    $0x3f,%r14d
mov    %r14d,(%r12)
mov    0x8(%rsp),%esi
mov    %ebx,%edi
call   1030 <UARTOperatingModeSelect@plt>
mov    %ebx,%edi
mov    $0x7f,%esi
call   1040 <UARTRegConfigModeEnable@plt>
mov    0x10(%rsp),%eax
or     %eax,(%r12)
mov    %ebx,%edi
mov    $0xbf,%esi
call   1040 <UARTRegConfigModeEnable@plt>
andl   $0xffffffef,(%r15)
mov    0x14(%rsp),%eax
or     %eax,(%r15)
mov    0xc(%rsp),%eax
add    $0xc,%ebx
mov    %eax,(%rbx)
mov    %ebp,%eax
add    $0x18,%rsp
pop    %rbx
pop    %r12
pop    %r13
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define i32 @UARTDivisorLatchWrite(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
%9 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
store volatile i32 0, i32* %5
store volatile i32 0, i32* %6
store volatile i32 0, i32* %7
store volatile i32 0, i32* %8
store i32 0, i32* %9
%10 = load i32, i32* %3
%11 = call i32 @UARTRegConfigModeEnable(i32 %10, i32 191)
store volatile i32 %11, i32* %7
%12 = load i32, i32* %3
%13 = add i32 %12, 8
%14 = zext i32 %13 to i64
%15 = inttoptr i64 %14 to i32*
%16 = load volatile i32, i32* %15
%17 = and i32 %16, 16
store volatile i32 %17, i32* %5
%18 = load i32, i32* %3
%19 = add i32 %18, 8
%20 = zext i32 %19 to i64
%21 = inttoptr i64 %20 to i32*
%22 = load volatile i32, i32* %21
%23 = or i32 %22, 16
store volatile i32 %23, i32* %21
%24 = load i32, i32* %3
%25 = call i32 @UARTRegConfigModeEnable(i32 %24, i32 127)
%26 = load i32, i32* %3
%27 = add i32 %26, 4
%28 = zext i32 %27 to i64
%29 = inttoptr i64 %28 to i32*
%30 = load volatile i32, i32* %29
%31 = and i32 %30, 16
store volatile i32 %31, i32* %6
%32 = load i32, i32* %3
%33 = add i32 %32, 4
%34 = zext i32 %33 to i64
%35 = inttoptr i64 %34 to i32*
%36 = load volatile i32, i32* %35
%37 = and i32 %36, -17
store volatile i32 %37, i32* %35
%38 = load i32, i32* %3
%39 = call i32 @UARTRegConfigModeEnable(i32 %38, i32 191)
%40 = load i32, i32* %3
%41 = add i32 %40, 0
%42 = zext i32 %41 to i64
%43 = inttoptr i64 %42 to i32*
%44 = load volatile i32, i32* %43
%45 = and i32 %44, 255
store i32 %45, i32* %9
%46 = load i32, i32* %3
%47 = add i32 %46, 4
%48 = zext i32 %47 to i64
%49 = inttoptr i64 %48 to i32*
%50 = load volatile i32, i32* %49
%51 = and i32 %50, 63
%52 = shl i32 %51, 8
%53 = load i32, i32* %9
%54 = or i32 %53, %52
store i32 %54, i32* %9
%55 = load i32, i32* %3
%56 = call i32 @UARTOperatingModeSelect(i32 %55, i32 7)
store volatile i32 %56, i32* %8
%57 = load i32, i32* %4
%58 = and i32 %57, 255
%59 = load i32, i32* %3
%60 = add i32 %59, 0
%61 = zext i32 %60 to i64
%62 = inttoptr i64 %61 to i32*
store volatile i32 %58, i32* %62
%63 = load i32, i32* %4
%64 = and i32 %63, 16128
%65 = lshr i32 %64, 8
%66 = load i32, i32* %3
%67 = add i32 %66, 4
%68 = zext i32 %67 to i64
%69 = inttoptr i64 %68 to i32*
store volatile i32 %65, i32* %69
%70 = load i32, i32* %3
%71 = load volatile i32, i32* %8
%72 = call i32 @UARTOperatingModeSelect(i32 %70, i32 %71)
%73 = load i32, i32* %3
%74 = call i32 @UARTRegConfigModeEnable(i32 %73, i32 127)
%75 = load volatile i32, i32* %6
%76 = load i32, i32* %3
%77 = add i32 %76, 4
%78 = zext i32 %77 to i64
%79 = inttoptr i64 %78 to i32*
%80 = load volatile i32, i32* %79
%81 = or i32 %80, %75
store volatile i32 %81, i32* %79
%82 = load i32, i32* %3
%83 = call i32 @UARTRegConfigModeEnable(i32 %82, i32 191)
%84 = load i32, i32* %3
%85 = add i32 %84, 8
%86 = zext i32 %85 to i64
%87 = inttoptr i64 %86 to i32*
%88 = load volatile i32, i32* %87
%89 = and i32 %88, -17
store volatile i32 %89, i32* %87
%90 = load volatile i32, i32* %5
%91 = load i32, i32* %3
%92 = add i32 %91, 8
%93 = zext i32 %92 to i64
%94 = inttoptr i64 %93 to i32*
%95 = load volatile i32, i32* %94
%96 = or i32 %95, %90
store volatile i32 %96, i32* %94
%97 = load volatile i32, i32* %7
%98 = load i32, i32* %3
%99 = add i32 %98, 12
%100 = zext i32 %99 to i64
%101 = inttoptr i64 %100 to i32*
store volatile i32 %97, i32* %101
%102 = load i32, i32* %9
ret i32 %102
}

LLVM IR (-O2):
define i32 @UARTDivisorLatchWrite(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = bitcast i32* %3 to i8*
store volatile i32 0, i32* %3
%8 = bitcast i32* %4 to i8*
store volatile i32 0, i32* %4
%9 = bitcast i32* %5 to i8*
store volatile i32 0, i32* %5
%10 = bitcast i32* %6 to i8*
store volatile i32 0, i32* %6
%11 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 191)
store volatile i32 %11, i32* %5
%12 = add i32 %0, 8
%13 = zext i32 %12 to i64
%14 = inttoptr i64 %13 to i32*
%15 = load volatile i32, i32* %14
%16 = and i32 %15, 16
store volatile i32 %16, i32* %3
%17 = load volatile i32, i32* %14
%18 = or i32 %17, 16
store volatile i32 %18, i32* %14
%19 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 127)
%20 = add i32 %0, 4
%21 = zext i32 %20 to i64
%22 = inttoptr i64 %21 to i32*
%23 = load volatile i32, i32* %22
%24 = and i32 %23, 16
store volatile i32 %24, i32* %4
%25 = load volatile i32, i32* %22
%26 = and i32 %25, -17
store volatile i32 %26, i32* %22
%27 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 191)
%28 = zext i32 %0 to i64
%29 = inttoptr i64 %28 to i32*
%30 = load volatile i32, i32* %29
%31 = and i32 %30, 255
%32 = load volatile i32, i32* %22
%33 = shl i32 %32, 8
%34 = and i32 %33, 16128
%35 = or i32 %34, %31
%36 = tail call i32 @UARTOperatingModeSelect(i32 %0, i32 7)
store volatile i32 %36, i32* %6
%37 = and i32 %1, 255
store volatile i32 %37, i32* %29
%38 = lshr i32 %1, 8
%39 = and i32 %38, 63
store volatile i32 %39, i32* %22
%40 = load volatile i32, i32* %6
%41 = tail call i32 @UARTOperatingModeSelect(i32 %0, i32 %40)
%42 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 127)
%43 = load volatile i32, i32* %4
%44 = load volatile i32, i32* %22
%45 = or i32 %44, %43
store volatile i32 %45, i32* %22
%46 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 191)
%47 = load volatile i32, i32* %14
%48 = and i32 %47, -17
store volatile i32 %48, i32* %14
%49 = load volatile i32, i32* %3
%50 = load volatile i32, i32* %14
%51 = or i32 %50, %49
store volatile i32 %51, i32* %14
%52 = load volatile i32, i32* %5
%53 = add i32 %0, 12
%54 = zext i32 %53 to i64
%55 = inttoptr i64 %54 to i32*
store volatile i32 %52, i32* %55
ret i32 %35
}