#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ assert(int);
int /*<<< orphan*/ print(char *, ...);
unsigned int get_cache_line_size() {
  unsigned int cache_line_size, vendor, family;
  unsigned int res_eax, res_ebx = 0, res_ecx = 0, res_edx = 0;
  assert((0));
  if (res_ebx == 0x756e6547) {
    vendor = 0;
    assert(res_edx == 0x49656e69 && res_ecx == 0x6c65746e);
  } else if (res_ebx == 0x68747541) {
    vendor = 1;
    assert(res_edx == 0x69746e65 && res_ecx == 0x444d4163);
  } else {
    vendor = 2;
    print("get_cache_line_size: unknown processor type");
  }
  assert((0));
  family = (res_eax & 0x00000f00) >> 8;
  if (family == 15) {
    cache_line_size = (res_ebx & 0x0000ff00) >> 5;
  } else if (vendor == 0 && (family == 6 || family == 6)) {
    cache_line_size = 32;
  } else if (vendor == 1 && family == 6) {
    cache_line_size = 64;
  } else {
    print("get_cache_line_size: unsupported processor family %d\n", family);
    cache_line_size = 32;
  }
  assert((cache_line_size & (cache_line_size - 1)) == 0);
  return cache_line_size;
}


x86 assembly (clang, -O0):
<get_cache_line_size>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
movl   $0x0,-0x14(%rbp)
movl   $0x0,-0x18(%rbp)
movl   $0x0,-0x1c(%rbp)
xor    %edi,%edi
call   1040 <assert@plt>
cmpl   $0x756e6547,-0x14(%rbp)
jne    1189 <get_cache_line_size+0x69>
movl   $0x0,-0x8(%rbp)
xor    %eax,%eax
cmpl   $0x49656e69,-0x1c(%rbp)
mov    %al,-0x1d(%rbp)
jne    1177 <get_cache_line_size+0x57>
cmpl   $0x6c65746e,-0x18(%rbp)
sete   %al
mov    %al,-0x1d(%rbp)
mov    -0x1d(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1040 <assert@plt>
jmp    11e8 <get_cache_line_size+0xc8>
cmpl   $0x68747541,-0x14(%rbp)
jne    11ce <get_cache_line_size+0xae>
movl   $0x1,-0x8(%rbp)
xor    %eax,%eax
cmpl   $0x69746e65,-0x1c(%rbp)
mov    %al,-0x1e(%rbp)
jne    11bc <get_cache_line_size+0x9c>
cmpl   $0x444d4163,-0x18(%rbp)
sete   %al
mov    %al,-0x1e(%rbp)
mov    -0x1e(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1040 <assert@plt>
jmp    11e3 <get_cache_line_size+0xc3>
movl   $0x2,-0x8(%rbp)
lea    0xe24(%rip),%rdi
mov    $0x0,%al
call   1030 <print@plt>
jmp    11e8 <get_cache_line_size+0xc8>
xor    %edi,%edi
call   1040 <assert@plt>
mov    -0x10(%rbp),%eax
and    $0xf00,%eax
shr    $0x8,%eax
mov    %eax,-0xc(%rbp)
cmpl   $0xf,-0xc(%rbp)
jne    121a <get_cache_line_size+0xfa>
mov    -0x14(%rbp),%eax
and    $0xff00,%eax
shr    $0x5,%eax
mov    %eax,-0x4(%rbp)
jmp    1286 <get_cache_line_size+0x166>
cmpl   $0x0,-0x8(%rbp)
jne    1244 <get_cache_line_size+0x124>
cmpl   $0x6,-0xc(%rbp)
je     1238 <get_cache_line_size+0x118>
cmpl   $0x6,-0xc(%rbp)
jne    1244 <get_cache_line_size+0x124>
movl   $0x20,-0x4(%rbp)
jmp    1281 <get_cache_line_size+0x161>
cmpl   $0x1,-0x8(%rbp)
jne    1264 <get_cache_line_size+0x144>
cmpl   $0x6,-0xc(%rbp)
jne    1264 <get_cache_line_size+0x144>
movl   $0x40,-0x4(%rbp)
jmp    127c <get_cache_line_size+0x15c>
mov    -0xc(%rbp),%esi
lea    0xdbe(%rip),%rdi
mov    $0x0,%al
call   1030 <print@plt>
movl   $0x20,-0x4(%rbp)
jmp    1281 <get_cache_line_size+0x161>
jmp    1286 <get_cache_line_size+0x166>
mov    -0x4(%rbp),%eax
mov    -0x4(%rbp),%ecx
sub    $0x1,%ecx
and    %ecx,%eax
cmp    $0x0,%eax
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1040 <assert@plt>
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<get_cache_line_size>:
push   %rax
xor    %edi,%edi
call   1040 <assert@plt>
lea    0xed1(%rip),%rdi
xor    %eax,%eax
call   1030 <print@plt>
xor    %edi,%edi
call   1040 <assert@plt>
lea    0xee8(%rip),%rdi
xor    %esi,%esi
xor    %eax,%eax
call   1030 <print@plt>
mov    $0x1,%edi
call   1040 <assert@plt>
mov    $0x20,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [44 x i8] c"get_cache_line_size: unknown processor type\00"
@.str.1 = [54 x i8] c"get_cache_line_size: unsupported processor family %d\0A\00"
define i32 @get_cache_line_size() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i32 0, i32* %5
store i32 0, i32* %6
store i32 0, i32* %7
%8 = call i32 @assert(i32 0)
%9 = load i32, i32* %5
%10 = icmp eq i32 %9, 1970169159
br i1 %10, label %11, label %21
11: ; preds = %0
store i32 0, i32* %2
%12 = load i32, i32* %7
%13 = icmp eq i32 %12, 1231384169
br i1 %13, label %14, label %17
14: ; preds = %11
%15 = load i32, i32* %6
%16 = icmp eq i32 %15, 1818588270
br label %17
17: ; preds = %14, %11
%18 = phi i1 [ false, %11 ], [ %16, %14 ]
%19 = zext i1 %18 to i32
%20 = call i32 @assert(i32 %19)
br label %37
21: ; preds = %0
%22 = load i32, i32* %5
%23 = icmp eq i32 %22, 1752462657
br i1 %23, label %24, label %34
24: ; preds = %21
store i32 1, i32* %2
%25 = load i32, i32* %7
%26 = icmp eq i32 %25, 1769238117
br i1 %26, label %27, label %30
27: ; preds = %24
%28 = load i32, i32* %6
%29 = icmp eq i32 %28, 1145913699
br label %30
30: ; preds = %27, %24
%31 = phi i1 [ false, %24 ], [ %29, %27 ]
%32 = zext i1 %31 to i32
%33 = call i32 @assert(i32 %32)
br label %36
34: ; preds = %21
store i32 2, i32* %2
%35 = call i32 (i8*, ...) @print(i8* getelementptr inbounds ([44 x i8], [44 x i8]* @.str, i64 0, i64 0))
br label %36
36: ; preds = %34, %30
br label %37
37: ; preds = %36, %17
%38 = call i32 @assert(i32 0)
%39 = load i32, i32* %4
%40 = and i32 %39, 3840
%41 = lshr i32 %40, 8
store i32 %41, i32* %3
%42 = load i32, i32* %3
%43 = icmp eq i32 %42, 15
br i1 %43, label %44, label %48
44: ; preds = %37
%45 = load i32, i32* %5
%46 = and i32 %45, 65280
%47 = lshr i32 %46, 5
store i32 %47, i32* %1
br label %70
48: ; preds = %37
%49 = load i32, i32* %2
%50 = icmp eq i32 %49, 0
br i1 %50, label %51, label %58
51: ; preds = %48
%52 = load i32, i32* %3
%53 = icmp eq i32 %52, 6
br i1 %53, label %57, label %54
54: ; preds = %51
%55 = load i32, i32* %3
%56 = icmp eq i32 %55, 6
br i1 %56, label %57, label %58
57: ; preds = %54, %51
store i32 32, i32* %1
br label %69
58: ; preds = %54, %48
%59 = load i32, i32* %2
%60 = icmp eq i32 %59, 1
br i1 %60, label %61, label %65
61: ; preds = %58
%62 = load i32, i32* %3
%63 = icmp eq i32 %62, 6
br i1 %63, label %64, label %65
64: ; preds = %61
store i32 64, i32* %1
br label %68
65: ; preds = %61, %58
%66 = load i32, i32* %3
%67 = call i32 (i8*, ...) @print(i8* getelementptr inbounds ([54 x i8], [54 x i8]* @.str.1, i64 0, i64 0), i32 %66)
store i32 32, i32* %1
br label %68
68: ; preds = %65, %64
br label %69
69: ; preds = %68, %57
br label %70
70: ; preds = %69, %44
%71 = load i32, i32* %1
%72 = load i32, i32* %1
%73 = sub i32 %72, 1
%74 = and i32 %71, %73
%75 = icmp eq i32 %74, 0
%76 = zext i1 %75 to i32
%77 = call i32 @assert(i32 %76)
%78 = load i32, i32* %1
ret i32 %78
}

LLVM IR (-O2):
@.str = [44 x i8] c"get_cache_line_size: unknown processor type\00"
@.str.1 = [54 x i8] c"get_cache_line_size: unsupported processor family %d\0A\00"
define i32 @get_cache_line_size() {
%1 = tail call i32 @assert(i32 0)
%2 = tail call i32 (i8*, ...) @print(i8* getelementptr inbounds ([44 x i8], [44 x i8]* @.str, i64 0, i64 0))
%3 = tail call i32 @assert(i32 0)
%4 = tail call i32 (i8*, ...) @print(i8* getelementptr inbounds ([54 x i8], [54 x i8]* @.str.1, i64 0, i64 0), i32 0)
%5 = tail call i32 @assert(i32 1)
ret i32 32
}