int arch_reg_size(int reg) {
  int size;
  size = 0;
  if (reg == 2) {
    size = 32;
  } else if ((reg >= 3) && (reg <= 10)) {
    size = 8;
  } else if ((reg >= 11) && (reg <= 18)) {
    size = 16;
  } else if ((reg >= 19) && (reg <= 26)) {
    size = 32;
  } else if (reg == 27) {
    size = 64;
  } else if (reg == 28) {
    size = 32;
  } else if ((reg >= 29) && (reg <= 36)) {
    size = 64;
  } else if ((reg >= 37) && (reg <= 44)) {
    size = 128;
  }
  return size;
}


x86 assembly (clang, -O0):
<arch_reg_size>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
movl   $0x0,-0x8(%rbp)
cmpl   $0x2,-0x4(%rbp)
jne    1124 <arch_reg_size+0x24>
movl   $0x20,-0x8(%rbp)
jmp    120e <arch_reg_size+0x10e>
cmpl   $0x3,-0x4(%rbp)
jl     1144 <arch_reg_size+0x44>
cmpl   $0xa,-0x4(%rbp)
jg     1144 <arch_reg_size+0x44>
movl   $0x8,-0x8(%rbp)
jmp    1209 <arch_reg_size+0x109>
cmpl   $0xb,-0x4(%rbp)
jl     1164 <arch_reg_size+0x64>
cmpl   $0x12,-0x4(%rbp)
jg     1164 <arch_reg_size+0x64>
movl   $0x10,-0x8(%rbp)
jmp    1204 <arch_reg_size+0x104>
cmpl   $0x13,-0x4(%rbp)
jl     1184 <arch_reg_size+0x84>
cmpl   $0x1a,-0x4(%rbp)
jg     1184 <arch_reg_size+0x84>
movl   $0x20,-0x8(%rbp)
jmp    11ff <arch_reg_size+0xff>
cmpl   $0x1b,-0x4(%rbp)
jne    119a <arch_reg_size+0x9a>
movl   $0x40,-0x8(%rbp)
jmp    11fa <arch_reg_size+0xfa>
cmpl   $0x1c,-0x4(%rbp)
jne    11b0 <arch_reg_size+0xb0>
movl   $0x20,-0x8(%rbp)
jmp    11f5 <arch_reg_size+0xf5>
cmpl   $0x1d,-0x4(%rbp)
jl     11d0 <arch_reg_size+0xd0>
cmpl   $0x24,-0x4(%rbp)
jg     11d0 <arch_reg_size+0xd0>
movl   $0x40,-0x8(%rbp)
jmp    11f0 <arch_reg_size+0xf0>
cmpl   $0x25,-0x4(%rbp)
jl     11eb <arch_reg_size+0xeb>
cmpl   $0x2c,-0x4(%rbp)
jg     11eb <arch_reg_size+0xeb>
movl   $0x80,-0x8(%rbp)
jmp    11f0 <arch_reg_size+0xf0>
jmp    11f5 <arch_reg_size+0xf5>
jmp    11fa <arch_reg_size+0xfa>
jmp    11ff <arch_reg_size+0xff>
jmp    1204 <arch_reg_size+0x104>
jmp    1209 <arch_reg_size+0x109>
jmp    120e <arch_reg_size+0x10e>
mov    -0x8(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<arch_reg_size>:
cmp    $0x2,%edi
jne    110b <arch_reg_size+0xb>
mov    $0x20,%eax
ret
lea    -0x3(%rdi),%ecx
mov    $0x8,%eax
cmp    $0x8,%ecx
jb     1125 <arch_reg_size+0x25>
lea    -0xb(%rdi),%ecx
mov    $0x10,%eax
cmp    $0x8,%ecx
jae    1126 <arch_reg_size+0x26>
ret
lea    -0x13(%rdi),%eax
cmp    $0x8,%eax
jae    1134 <arch_reg_size+0x34>
mov    $0x20,%eax
ret
mov    $0x40,%eax
cmp    $0x1b,%edi
je     1125 <arch_reg_size+0x25>
cmp    $0x1c,%edi
jne    1149 <arch_reg_size+0x49>
mov    $0x20,%eax
ret
lea    -0x1d(%rdi),%ecx
cmp    $0x8,%ecx
jb     1125 <arch_reg_size+0x25>
add    $0xffffffdb,%edi
xor    %eax,%eax
cmp    $0x8,%edi
setb   %al
shl    $0x7,%eax
ret

LLVM IR (-O0):
define i32 @arch_reg_size(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %2
store i32 0, i32* %3
%4 = load i32, i32* %2
%5 = icmp eq i32 %4, 2
br i1 %5, label %6, label %7
6: ; preds = %1
store i32 32, i32* %3
br label %57
7: ; preds = %1
%8 = load i32, i32* %2
%9 = icmp sge i32 %8, 3
br i1 %9, label %10, label %14
10: ; preds = %7
%11 = load i32, i32* %2
%12 = icmp sle i32 %11, 10
br i1 %12, label %13, label %14
13: ; preds = %10
store i32 8, i32* %3
br label %56
14: ; preds = %10, %7
%15 = load i32, i32* %2
%16 = icmp sge i32 %15, 11
br i1 %16, label %17, label %21
17: ; preds = %14
%18 = load i32, i32* %2
%19 = icmp sle i32 %18, 18
br i1 %19, label %20, label %21
20: ; preds = %17
store i32 16, i32* %3
br label %55
21: ; preds = %17, %14
%22 = load i32, i32* %2
%23 = icmp sge i32 %22, 19
br i1 %23, label %24, label %28
24: ; preds = %21
%25 = load i32, i32* %2
%26 = icmp sle i32 %25, 26
br i1 %26, label %27, label %28
27: ; preds = %24
store i32 32, i32* %3
br label %54
28: ; preds = %24, %21
%29 = load i32, i32* %2
%30 = icmp eq i32 %29, 27
br i1 %30, label %31, label %32
31: ; preds = %28
store i32 64, i32* %3
br label %53
32: ; preds = %28
%33 = load i32, i32* %2
%34 = icmp eq i32 %33, 28
br i1 %34, label %35, label %36
35: ; preds = %32
store i32 32, i32* %3
br label %52
36: ; preds = %32
%37 = load i32, i32* %2
%38 = icmp sge i32 %37, 29
br i1 %38, label %39, label %43
39: ; preds = %36
%40 = load i32, i32* %2
%41 = icmp sle i32 %40, 36
br i1 %41, label %42, label %43
42: ; preds = %39
store i32 64, i32* %3
br label %51
43: ; preds = %39, %36
%44 = load i32, i32* %2
%45 = icmp sge i32 %44, 37
br i1 %45, label %46, label %50
46: ; preds = %43
%47 = load i32, i32* %2
%48 = icmp sle i32 %47, 44
br i1 %48, label %49, label %50
49: ; preds = %46
store i32 128, i32* %3
br label %50
50: ; preds = %49, %46, %43
br label %51
51: ; preds = %50, %42
br label %52
52: ; preds = %51, %35
br label %53
53: ; preds = %52, %31
br label %54
54: ; preds = %53, %27
br label %55
55: ; preds = %54, %20
br label %56
56: ; preds = %55, %13
br label %57
57: ; preds = %56, %6
%58 = load i32, i32* %3
ret i32 %58
}

LLVM IR (-O2):
define i32 @arch_reg_size(i32 %0) {
%2 = icmp eq i32 %0, 2
br i1 %2, label %21, label %3
3: ; preds = %1
%4 = add i32 %0, -3
%5 = icmp ult i32 %4, 8
br i1 %5, label %21, label %6
6: ; preds = %3
%7 = add i32 %0, -11
%8 = icmp ult i32 %7, 8
br i1 %8, label %21, label %9
9: ; preds = %6
%10 = add i32 %0, -19
%11 = icmp ult i32 %10, 8
br i1 %11, label %21, label %12
12: ; preds = %9
switch i32 %0, label %14 [
i32 27, label %21
i32 28, label %13
]
13: ; preds = %12
br label %21
14: ; preds = %12
%15 = add i32 %0, -29
%16 = icmp ult i32 %15, 8
br i1 %16, label %21, label %17
17: ; preds = %14
%18 = add i32 %0, -37
%19 = icmp ult i32 %18, 8
%20 = select i1 %19, i32 128, i32 0
br label %21
21: ; preds = %17, %14, %12, %9, %6, %3, %1, %13
%22 = phi i32 [ 32, %13 ], [ 32, %1 ], [ 8, %3 ], [ 16, %6 ], [ 32, %9 ], [ 64, %12 ], [ 64, %14 ], [ %20, %17 ]
ret i32 %22
}