void PSC0_lPSC_enable(unsigned int PD, unsigned int LPSC_num) {
  *(unsigned int *)((0x01C10000 + 0xA00) + 4 * LPSC_num) =
      (*(unsigned int *)((0x01C10000 + 0xA00) + 4 * LPSC_num) & 0xFFFFFFE0) |
      0x0003;
  *(volatile unsigned int *)(0x01C10000 + 0x120) = 0x1 << PD;
  while ((*(volatile unsigned int *)(0x01C10000 + 0x128) & (0x1 << PD)) != 0)
    ;
  while ((*(unsigned int *)((0x01C10000 + 0x800) + 4 * LPSC_num) & 0x1F) != 0x3)
    ;
}


x86 assembly (clang, -O0):
<PSC0_lPSC_enable>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
add    $0x1c10a00,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xffffffe0,%ecx
or     $0x3,%ecx
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
add    $0x1c10a00,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    -0x4(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,%ecx
mov    $0x1c10120,%eax
mov    %ecx,(%rax)
mov    $0x1c10128,%eax
mov    (%rax),%eax
mov    -0x4(%rbp),%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
and    %ecx,%eax
cmp    $0x0,%eax
je     1164 <PSC0_lPSC_enable+0x64>
jmp    1141 <PSC0_lPSC_enable+0x41>
jmp    1169 <PSC0_lPSC_enable+0x69>
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
add    $0x1c10800,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x1f,%eax
cmp    $0x3,%eax
je     1189 <PSC0_lPSC_enable+0x89>
jmp    1169 <PSC0_lPSC_enable+0x69>
pop    %rbp
ret

x86 assembly (clang, -O2):
<PSC0_lPSC_enable>:
mov    %edi,%ecx
lea    0x1c10a00(,%rsi,4),%eax
shl    $0x2,%esi
mov    (%rax),%edx
and    $0xffffffe0,%edx
or     $0x3,%edx
mov    %edx,(%rax)
mov    $0x1,%eax
shl    %cl,%eax
mov    %eax,0x1c10120
cs nopw 0x0(%rax,%rax,1)
xchg   %ax,%ax
mov    0x1c10128,%ecx
and    %eax,%ecx
jne    1130 <PSC0_lPSC_enable+0x30>
add    $0x1c10800,%esi
mov    (%rsi),%eax
and    $0x1f,%eax
cmp    $0x3,%eax
jne    1150 <PSC0_lPSC_enable+0x50>
ret
nopl   0x0(%rax)
jmp    1150 <PSC0_lPSC_enable+0x50>

LLVM IR (-O0):
define void @PSC0_lPSC_enable(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %4
%6 = mul i32 4, %5
%7 = add i32 29428224, %6
%8 = zext i32 %7 to i64
%9 = inttoptr i64 %8 to i32*
%10 = load i32, i32* %9
%11 = and i32 %10, -32
%12 = or i32 %11, 3
%13 = load i32, i32* %4
%14 = mul i32 4, %13
%15 = add i32 29428224, %14
%16 = zext i32 %15 to i64
%17 = inttoptr i64 %16 to i32*
store i32 %12, i32* %17
%18 = load i32, i32* %3
%19 = shl i32 1, %18
store volatile i32 %19, i32* inttoptr (i64 29425952 to i32*)
br label %20
20: ; preds = %26, %2
%21 = load volatile i32, i32* inttoptr (i64 29425960 to i32*)
%22 = load i32, i32* %3
%23 = shl i32 1, %22
%24 = and i32 %21, %23
%25 = icmp ne i32 %24, 0
br i1 %25, label %26, label %27
26: ; preds = %20
br label %20
27: ; preds = %20
br label %28
28: ; preds = %37, %27
%29 = load i32, i32* %4
%30 = mul i32 4, %29
%31 = add i32 29427712, %30
%32 = zext i32 %31 to i64
%33 = inttoptr i64 %32 to i32*
%34 = load i32, i32* %33
%35 = and i32 %34, 31
%36 = icmp ne i32 %35, 3
br i1 %36, label %37, label %38
37: ; preds = %28
br label %28
38: ; preds = %28
ret void
}

LLVM IR (-O2):
define void @PSC0_lPSC_enable(i32 %0, i32 %1) {
%3 = shl i32 %1, 2
%4 = add i32 %3, 29428224
%5 = zext i32 %4 to i64
%6 = inttoptr i64 %5 to i32*
%7 = load i32, i32* %6
%8 = and i32 %7, -32
%9 = or i32 %8, 3
store i32 %9, i32* %6
%10 = shl nuw i32 1, %0
store volatile i32 %10, i32* inttoptr (i64 29425952 to i32*)
br label %11
11: ; preds = %11, %2
%12 = load volatile i32, i32* inttoptr (i64 29425960 to i32*)
%13 = and i32 %12, %10
%14 = icmp eq i32 %13, 0
br i1 %14, label %15, label %11
15: ; preds = %11
%16 = add i32 %3, 29427712
%17 = zext i32 %16 to i64
%18 = inttoptr i64 %17 to i32*
%19 = load i32, i32* %18
%20 = and i32 %19, 31
%21 = icmp eq i32 %20, 3
br i1 %21, label %23, label %22
22: ; preds = %15, %22
br label %22
23: ; preds = %15
ret void
}