const char *mce_bank_name(int id) {
  static char *optbank[] = {"data cache", "instruction cache", "bus unit",
                            "load/store unit", "northbridge"};
  static char *optthreshold[] = {"MC0_MISC threshold", "MC1_MISC threshold",
                                 "MC2_MISC threshold", "MC3_MISC threshold",
                                 "MC4_MISC DRAM errors threshold"};
  if (id >= 0 && id < 5)
    return optbank[id];
  if (id >= (128 + 1) && id <= ((128 + 1) + 4))
    return optthreshold[id - (128 + 1)];
  return "unknown";
}


x86 assembly (clang, -O0):
<mce_bank_name>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0xc(%rbp)
cmpl   $0x0,-0xc(%rbp)
jl     1133 <mce_bank_name+0x33>
cmpl   $0x5,-0xc(%rbp)
jge    1133 <mce_bank_name+0x33>
movslq -0xc(%rbp),%rcx
lea    0x2f0a(%rip),%rax
mov    (%rax,%rcx,8),%rax
mov    %rax,-0x8(%rbp)
jmp    1177 <mce_bank_name+0x77>
cmpl   $0x81,-0xc(%rbp)
jl     116c <mce_bank_name+0x6c>
cmpl   $0x85,-0xc(%rbp)
jg     116c <mce_bank_name+0x6c>
mov    -0xc(%rbp),%eax
sub    $0x81,%eax
movslq %eax,%rcx
lea    0x2f01(%rip),%rax
mov    (%rax,%rcx,8),%rax
mov    %rax,-0x8(%rbp)
jmp    1177 <mce_bank_name+0x77>
lea    0xf3a(%rip),%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<mce_bank_name>:
cmp    $0x5,%edi
jae    110e <mce_bank_name+0xe>
lea    0x2ce4(%rip),%rax
jmp    1120 <mce_bank_name+0x20>
add    $0xffffff7f,%edi
cmp    $0x4,%edi
ja     1127 <mce_bank_name+0x27>
lea    0x2d00(%rip),%rax
mov    %edi,%ecx
mov    (%rax,%rcx,8),%rax
ret
lea    0xf7f(%rip),%rax
ret

LLVM IR (-O0):
@mce_bank_name.optbank = internal global [5 x i8*] [i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str.1, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str.3, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.4, i32 0, i32 0)]
@.str = [11 x i8] c"data cache\00"
@.str.1 = [18 x i8] c"instruction cache\00"
@.str.2 = [9 x i8] c"bus unit\00"
@.str.3 = [16 x i8] c"load/store unit\00"
@.str.4 = [12 x i8] c"northbridge\00"
@mce_bank_name.optthreshold = internal global [5 x i8*] [i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.5, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.6, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.7, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.8, i32 0, i32 0), i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str.9, i32 0, i32 0)]
@.str.5 = [19 x i8] c"MC0_MISC threshold\00"
@.str.6 = [19 x i8] c"MC1_MISC threshold\00"
@.str.7 = [19 x i8] c"MC2_MISC threshold\00"
@.str.8 = [19 x i8] c"MC3_MISC threshold\00"
@.str.9 = [31 x i8] c"MC4_MISC DRAM errors threshold\00"
@.str.10 = [8 x i8] c"unknown\00"
define i8* @mce_bank_name(i32 %0) {
%2 = alloca i8*
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp sge i32 %4, 0
br i1 %5, label %6, label %14
6: ; preds = %1
%7 = load i32, i32* %3
%8 = icmp slt i32 %7, 5
br i1 %8, label %9, label %14
9: ; preds = %6
%10 = load i32, i32* %3
%11 = sext i32 %10 to i64
%12 = getelementptr inbounds [5 x i8*], [5 x i8*]* @mce_bank_name.optbank, i64 0, i64 %11
%13 = load i8*, i8** %12
store i8* %13, i8** %2
br label %27
14: ; preds = %6, %1
%15 = load i32, i32* %3
%16 = icmp sge i32 %15, 129
br i1 %16, label %17, label %26
17: ; preds = %14
%18 = load i32, i32* %3
%19 = icmp sle i32 %18, 133
br i1 %19, label %20, label %26
20: ; preds = %17
%21 = load i32, i32* %3
%22 = sub nsw i32 %21, 129
%23 = sext i32 %22 to i64
%24 = getelementptr inbounds [5 x i8*], [5 x i8*]* @mce_bank_name.optthreshold, i64 0, i64 %23
%25 = load i8*, i8** %24
store i8* %25, i8** %2
br label %27
26: ; preds = %17, %14
store i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.10, i64 0, i64 0), i8** %2
br label %27
27: ; preds = %26, %20, %9
%28 = load i8*, i8** %2
ret i8* %28
}

LLVM IR (-O2):
@mce_bank_name.optbank = internal unnamed_addr constant [5 x i8*] [i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str.1, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str.3, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.4, i32 0, i32 0)]
@.str = [11 x i8] c"data cache\00"
@.str.1 = [18 x i8] c"instruction cache\00"
@.str.2 = [9 x i8] c"bus unit\00"
@.str.3 = [16 x i8] c"load/store unit\00"
@.str.4 = [12 x i8] c"northbridge\00"
@mce_bank_name.optthreshold = internal unnamed_addr constant [5 x i8*] [i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.5, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.6, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.7, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8], [19 x i8]* @.str.8, i32 0, i32 0), i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str.9, i32 0, i32 0)]
@.str.5 = [19 x i8] c"MC0_MISC threshold\00"
@.str.6 = [19 x i8] c"MC1_MISC threshold\00"
@.str.7 = [19 x i8] c"MC2_MISC threshold\00"
@.str.8 = [19 x i8] c"MC3_MISC threshold\00"
@.str.9 = [31 x i8] c"MC4_MISC DRAM errors threshold\00"
@.str.10 = [8 x i8] c"unknown\00"
define i8* @mce_bank_name(i32 %0) {
%2 = icmp ult i32 %0, 5
br i1 %2, label %6, label %3
3: ; preds = %1
%4 = add i32 %0, -129
%5 = icmp ult i32 %4, 5
br i1 %5, label %6, label %12
6: ; preds = %3, %1
%7 = phi i32 [ %0, %1 ], [ %4, %3 ]
%8 = phi [5 x i8*]* [ @mce_bank_name.optbank, %1 ], [ @mce_bank_name.optthreshold, %3 ]
%9 = zext i32 %7 to i64
%10 = getelementptr inbounds [5 x i8*], [5 x i8*]* %8, i64 0, i64 %9
%11 = load i8*, i8** %10
br label %12
12: ; preds = %6, %3
%13 = phi i8* [ getelementptr inbounds ([8 x i8], [8 x i8]* @.str.10, i64 0, i64 0), %3 ], [ %11, %6 ]
ret i8* %13
}