unsigned char Alog(unsigned char BForAlog) {
  int a = 0, b = 0, c = 0, d = 0, iRt;
  a = BForAlog;
  c = a;
  d = a;
  c &= 0x40;
  b = a;
  d >>= 2;
  c |= d;
  d = a;
  c >>= 2;
  d &= 0x20;
  c |= d;
  d = a;
  c >>= 2;
  d &= 0x10;
  c |= d;
  d = a;
  d &= 2;
  b <<= 2;
  d |= b;
  b = a;
  d <<= 2;
  b &= 4;
  a &= 8;
  d |= b;
  d <<= 2;
  d |= a;
  c >>= 1;
  d <<= 1;
  c |= d;
  iRt = (~c) & 0xff;
  return iRt;
}


x86 assembly (clang, -O0):
<Alog>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x1(%rbp)
movl   $0x0,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
movl   $0x0,-0x10(%rbp)
movl   $0x0,-0x14(%rbp)
movzbl -0x1(%rbp),%eax
mov    %eax,-0x8(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
and    $0x40,%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0x14(%rbp),%eax
sar    $0x2,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
or     -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
sar    $0x2,%eax
mov    %eax,-0x10(%rbp)
mov    -0x14(%rbp),%eax
and    $0x20,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
or     -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
sar    $0x2,%eax
mov    %eax,-0x10(%rbp)
mov    -0x14(%rbp),%eax
and    $0x10,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
or     -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
and    $0x2,%eax
mov    %eax,-0x14(%rbp)
mov    -0xc(%rbp),%eax
shl    $0x2,%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
or     -0x14(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0x14(%rbp),%eax
shl    $0x2,%eax
mov    %eax,-0x14(%rbp)
mov    -0xc(%rbp),%eax
and    $0x4,%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%eax
and    $0x8,%eax
mov    %eax,-0x8(%rbp)
mov    -0xc(%rbp),%eax
or     -0x14(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
shl    $0x2,%eax
mov    %eax,-0x14(%rbp)
mov    -0x8(%rbp),%eax
or     -0x14(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
sar    $0x1,%eax
mov    %eax,-0x10(%rbp)
mov    -0x14(%rbp),%eax
shl    $0x1,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
or     -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
xor    $0xffffffff,%eax
and    $0xff,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<Alog>:
rol    $0x4,%dil
mov    %edi,%eax
and    $0x33,%al
shl    $0x2,%al
shr    $0x2,%dil
and    $0x33,%dil
or     %dil,%al
mov    %eax,%ecx
and    $0x55,%cl
add    %cl,%cl
shr    %al
and    $0x55,%al
or     %cl,%al
not    %al
ret

LLVM IR (-O0):
define zeroext i8 @Alog(i8 zeroext %0) {
%2 = alloca i8
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i8 %0, i8* %2
store i32 0, i32* %3
store i32 0, i32* %4
store i32 0, i32* %5
store i32 0, i32* %6
%8 = load i8, i8* %2
%9 = zext i8 %8 to i32
store i32 %9, i32* %3
%10 = load i32, i32* %3
store i32 %10, i32* %5
%11 = load i32, i32* %3
store i32 %11, i32* %6
%12 = load i32, i32* %5
%13 = and i32 %12, 64
store i32 %13, i32* %5
%14 = load i32, i32* %3
store i32 %14, i32* %4
%15 = load i32, i32* %6
%16 = ashr i32 %15, 2
store i32 %16, i32* %6
%17 = load i32, i32* %6
%18 = load i32, i32* %5
%19 = or i32 %18, %17
store i32 %19, i32* %5
%20 = load i32, i32* %3
store i32 %20, i32* %6
%21 = load i32, i32* %5
%22 = ashr i32 %21, 2
store i32 %22, i32* %5
%23 = load i32, i32* %6
%24 = and i32 %23, 32
store i32 %24, i32* %6
%25 = load i32, i32* %6
%26 = load i32, i32* %5
%27 = or i32 %26, %25
store i32 %27, i32* %5
%28 = load i32, i32* %3
store i32 %28, i32* %6
%29 = load i32, i32* %5
%30 = ashr i32 %29, 2
store i32 %30, i32* %5
%31 = load i32, i32* %6
%32 = and i32 %31, 16
store i32 %32, i32* %6
%33 = load i32, i32* %6
%34 = load i32, i32* %5
%35 = or i32 %34, %33
store i32 %35, i32* %5
%36 = load i32, i32* %3
store i32 %36, i32* %6
%37 = load i32, i32* %6
%38 = and i32 %37, 2
store i32 %38, i32* %6
%39 = load i32, i32* %4
%40 = shl i32 %39, 2
store i32 %40, i32* %4
%41 = load i32, i32* %4
%42 = load i32, i32* %6
%43 = or i32 %42, %41
store i32 %43, i32* %6
%44 = load i32, i32* %3
store i32 %44, i32* %4
%45 = load i32, i32* %6
%46 = shl i32 %45, 2
store i32 %46, i32* %6
%47 = load i32, i32* %4
%48 = and i32 %47, 4
store i32 %48, i32* %4
%49 = load i32, i32* %3
%50 = and i32 %49, 8
store i32 %50, i32* %3
%51 = load i32, i32* %4
%52 = load i32, i32* %6
%53 = or i32 %52, %51
store i32 %53, i32* %6
%54 = load i32, i32* %6
%55 = shl i32 %54, 2
store i32 %55, i32* %6
%56 = load i32, i32* %3
%57 = load i32, i32* %6
%58 = or i32 %57, %56
store i32 %58, i32* %6
%59 = load i32, i32* %5
%60 = ashr i32 %59, 1
store i32 %60, i32* %5
%61 = load i32, i32* %6
%62 = shl i32 %61, 1
store i32 %62, i32* %6
%63 = load i32, i32* %6
%64 = load i32, i32* %5
%65 = or i32 %64, %63
store i32 %65, i32* %5
%66 = load i32, i32* %5
%67 = xor i32 %66, -1
%68 = and i32 %67, 255
store i32 %68, i32* %7
%69 = load i32, i32* %7
%70 = trunc i32 %69 to i8
ret i8 %70
}

LLVM IR (-O2):
define zeroext i8 @Alog(i8 zeroext %0) {
%2 = tail call i8 @llvm.bitreverse.i8(i8 %0)
%3 = xor i8 %2, -1
ret i8 %3
}