int main() {
  unsigned short int usi;
  signed short int ssi;
  usi = 0xFFFF;
  usi = usi >> 1;
  usi = 0;
  usi = 0x0000;
  usi = usi >> 1;
  usi = 0;
  usi = 0x0001;
  usi = usi >> 1;
  usi = 0;
  usi = 0x8000;
  usi = usi >> 1;
  usi = 0;
  usi = 0xAAAA;
  usi = usi >> 1;
  usi = 0;
  usi = 0x03C0;
  usi = usi >> 2;
  usi = 0;
  ssi = 0xFFFF;
  ssi = ssi >> 1;
  ssi = 0;
  ssi = 0x0000;
  ssi = ssi >> 1;
  ssi = 0;
  ssi = 0x0001;
  ssi = ssi >> 1;
  ssi = 0;
  ssi = 0x8000;
  ssi = ssi >> 1;
  ssi = 0;
  ssi = 0xAAAA;
  ssi = ssi >> 1;
  ssi = 0;
  ssi = 0x03C0;
  ssi = ssi >> 2;
  ssi = 0;
  usi = 0xFFFF;
  usi = usi << 1;
  usi = 0;
  usi = 0x0000;
  usi = usi << 1;
  usi = 0;
  usi = 0x0001;
  usi = usi << 1;
  usi = 0;
  usi = 0x8000;
  usi = usi << 1;
  usi = 0;
  usi = 0xAAAA;
  usi = usi << 1;
  usi = 0;
  usi = 0x03C0;
  usi = usi << 2;
  usi = 0;
  ssi = 0xFFFF;
  ssi = ssi << 1;
  ssi = 0;
  ssi = 0x0000;
  ssi = ssi << 1;
  ssi = 0;
  ssi = 0x0001;
  ssi = ssi << 1;
  ssi = 0;
  ssi = 0x8000;
  ssi = ssi << 1;
  ssi = 0;
  ssi = 0xAAAA;
  ssi = ssi << 1;
  ssi = 0;
  ssi = 0x03C0;
  ssi = ssi << 2;
  ssi = 0;
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
movl   $0x0,-0x4(%rbp)
movw   $0xffff,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x1,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x8000,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0xaaaa,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x3c0,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
sar    $0x2,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0xffff,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x1,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x8000,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0xaaaa,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x3c0,-0x8(%rbp)
movswl -0x8(%rbp),%eax
sar    $0x2,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0xffff,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x1,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x8000,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0xaaaa,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0x3c0,-0x6(%rbp)
movzwl -0x6(%rbp),%eax
shl    $0x2,%eax
mov    %ax,-0x6(%rbp)
movw   $0x0,-0x6(%rbp)
movw   $0xffff,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x1,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x8000,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0xaaaa,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x1,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
movw   $0x3c0,-0x8(%rbp)
movswl -0x8(%rbp),%eax
shl    $0x2,%eax
mov    %ax,-0x8(%rbp)
movw   $0x0,-0x8(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca i16
%3 = alloca i16
store i32 0, i32* %1
store i16 -1, i16* %2
%4 = load i16, i16* %2
%5 = zext i16 %4 to i32
%6 = ashr i32 %5, 1
%7 = trunc i32 %6 to i16
store i16 %7, i16* %2
store i16 0, i16* %2
store i16 0, i16* %2
%8 = load i16, i16* %2
%9 = zext i16 %8 to i32
%10 = ashr i32 %9, 1
%11 = trunc i32 %10 to i16
store i16 %11, i16* %2
store i16 0, i16* %2
store i16 1, i16* %2
%12 = load i16, i16* %2
%13 = zext i16 %12 to i32
%14 = ashr i32 %13, 1
%15 = trunc i32 %14 to i16
store i16 %15, i16* %2
store i16 0, i16* %2
store i16 -32768, i16* %2
%16 = load i16, i16* %2
%17 = zext i16 %16 to i32
%18 = ashr i32 %17, 1
%19 = trunc i32 %18 to i16
store i16 %19, i16* %2
store i16 0, i16* %2
store i16 -21846, i16* %2
%20 = load i16, i16* %2
%21 = zext i16 %20 to i32
%22 = ashr i32 %21, 1
%23 = trunc i32 %22 to i16
store i16 %23, i16* %2
store i16 0, i16* %2
store i16 960, i16* %2
%24 = load i16, i16* %2
%25 = zext i16 %24 to i32
%26 = ashr i32 %25, 2
%27 = trunc i32 %26 to i16
store i16 %27, i16* %2
store i16 0, i16* %2
store i16 -1, i16* %3
%28 = load i16, i16* %3
%29 = sext i16 %28 to i32
%30 = ashr i32 %29, 1
%31 = trunc i32 %30 to i16
store i16 %31, i16* %3
store i16 0, i16* %3
store i16 0, i16* %3
%32 = load i16, i16* %3
%33 = sext i16 %32 to i32
%34 = ashr i32 %33, 1
%35 = trunc i32 %34 to i16
store i16 %35, i16* %3
store i16 0, i16* %3
store i16 1, i16* %3
%36 = load i16, i16* %3
%37 = sext i16 %36 to i32
%38 = ashr i32 %37, 1
%39 = trunc i32 %38 to i16
store i16 %39, i16* %3
store i16 0, i16* %3
store i16 -32768, i16* %3
%40 = load i16, i16* %3
%41 = sext i16 %40 to i32
%42 = ashr i32 %41, 1
%43 = trunc i32 %42 to i16
store i16 %43, i16* %3
store i16 0, i16* %3
store i16 -21846, i16* %3
%44 = load i16, i16* %3
%45 = sext i16 %44 to i32
%46 = ashr i32 %45, 1
%47 = trunc i32 %46 to i16
store i16 %47, i16* %3
store i16 0, i16* %3
store i16 960, i16* %3
%48 = load i16, i16* %3
%49 = sext i16 %48 to i32
%50 = ashr i32 %49, 2
%51 = trunc i32 %50 to i16
store i16 %51, i16* %3
store i16 0, i16* %3
store i16 -1, i16* %2
%52 = load i16, i16* %2
%53 = zext i16 %52 to i32
%54 = shl i32 %53, 1
%55 = trunc i32 %54 to i16
store i16 %55, i16* %2
store i16 0, i16* %2
store i16 0, i16* %2
%56 = load i16, i16* %2
%57 = zext i16 %56 to i32
%58 = shl i32 %57, 1
%59 = trunc i32 %58 to i16
store i16 %59, i16* %2
store i16 0, i16* %2
store i16 1, i16* %2
%60 = load i16, i16* %2
%61 = zext i16 %60 to i32
%62 = shl i32 %61, 1
%63 = trunc i32 %62 to i16
store i16 %63, i16* %2
store i16 0, i16* %2
store i16 -32768, i16* %2
%64 = load i16, i16* %2
%65 = zext i16 %64 to i32
%66 = shl i32 %65, 1
%67 = trunc i32 %66 to i16
store i16 %67, i16* %2
store i16 0, i16* %2
store i16 -21846, i16* %2
%68 = load i16, i16* %2
%69 = zext i16 %68 to i32
%70 = shl i32 %69, 1
%71 = trunc i32 %70 to i16
store i16 %71, i16* %2
store i16 0, i16* %2
store i16 960, i16* %2
%72 = load i16, i16* %2
%73 = zext i16 %72 to i32
%74 = shl i32 %73, 2
%75 = trunc i32 %74 to i16
store i16 %75, i16* %2
store i16 0, i16* %2
store i16 -1, i16* %3
%76 = load i16, i16* %3
%77 = sext i16 %76 to i32
%78 = shl i32 %77, 1
%79 = trunc i32 %78 to i16
store i16 %79, i16* %3
store i16 0, i16* %3
store i16 0, i16* %3
%80 = load i16, i16* %3
%81 = sext i16 %80 to i32
%82 = shl i32 %81, 1
%83 = trunc i32 %82 to i16
store i16 %83, i16* %3
store i16 0, i16* %3
store i16 1, i16* %3
%84 = load i16, i16* %3
%85 = sext i16 %84 to i32
%86 = shl i32 %85, 1
%87 = trunc i32 %86 to i16
store i16 %87, i16* %3
store i16 0, i16* %3
store i16 -32768, i16* %3
%88 = load i16, i16* %3
%89 = sext i16 %88 to i32
%90 = shl i32 %89, 1
%91 = trunc i32 %90 to i16
store i16 %91, i16* %3
store i16 0, i16* %3
store i16 -21846, i16* %3
%92 = load i16, i16* %3
%93 = sext i16 %92 to i32
%94 = shl i32 %93, 1
%95 = trunc i32 %94 to i16
store i16 %95, i16* %3
store i16 0, i16* %3
store i16 960, i16* %3
%96 = load i16, i16* %3
%97 = sext i16 %96 to i32
%98 = shl i32 %97, 2
%99 = trunc i32 %98 to i16
store i16 %99, i16* %3
store i16 0, i16* %3
ret i32 0
}

LLVM IR (-O2):
define i32 @main() {
ret i32 0
}