unsigned short blend_dodge16(unsigned short color1, unsigned short color2) {
  int r = (((color2 >> 11)) * (0x20) / ((0x20) - ((color1 >> 11))));
  int g = ((((color2 & 0x7E0) >> 5)) * (0x40) /
           ((0x40) - (((color1 & 0x7E0) >> 5))));
  int b = (((color2 & 0x1F)) * (0x20) / ((0x20) - ((color1 & 0x1F))));
  if (r > 0x1F)
    r = 0x1F;
  if (g > 0x3F)
    g = 0x3F;
  if (b > 0x1F)
    b = 0x1F;
  return (((r) << 11) | ((g) << 5) | b);
}


x86 assembly (clang, -O0):
<blend_dodge16>:
push   %rbp
mov    %rsp,%rbp
mov    %si,%ax
mov    %di,%cx
mov    %cx,-0x2(%rbp)
mov    %ax,-0x4(%rbp)
movzwl -0x4(%rbp),%eax
sar    $0xb,%eax
shl    $0x5,%eax
movzwl -0x2(%rbp),%edx
sar    $0xb,%edx
mov    $0x20,%ecx
sub    %edx,%ecx
cltd
idiv   %ecx
mov    %eax,-0x8(%rbp)
movzwl -0x4(%rbp),%eax
and    $0x7e0,%eax
sar    $0x5,%eax
shl    $0x6,%eax
movzwl -0x2(%rbp),%edx
and    $0x7e0,%edx
sar    $0x5,%edx
mov    $0x40,%ecx
sub    %edx,%ecx
cltd
idiv   %ecx
mov    %eax,-0xc(%rbp)
movzwl -0x4(%rbp),%eax
and    $0x1f,%eax
shl    $0x5,%eax
movzwl -0x2(%rbp),%edx
and    $0x1f,%edx
mov    $0x20,%ecx
sub    %edx,%ecx
cltd
idiv   %ecx
mov    %eax,-0x10(%rbp)
cmpl   $0x1f,-0x8(%rbp)
jle    1188 <blend_dodge16+0x88>
movl   $0x1f,-0x8(%rbp)
cmpl   $0x3f,-0xc(%rbp)
jle    1199 <blend_dodge16+0x99>
movl   $0x3f,-0xc(%rbp)
cmpl   $0x1f,-0x10(%rbp)
jle    11aa <blend_dodge16+0xaa>
movl   $0x1f,-0x10(%rbp)
mov    -0x8(%rbp),%eax
shl    $0xb,%eax
mov    -0xc(%rbp),%ecx
shl    $0x5,%ecx
or     %ecx,%eax
or     -0x10(%rbp),%eax
movzwl %ax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<blend_dodge16>:
mov    %esi,%r11d
mov    %esi,%eax
shr    $0x6,%eax
and    $0xffffffe0,%eax
mov    %edi,%edx
shr    $0xb,%edx
mov    $0x20,%r10d
mov    $0x20,%ecx
sub    %edx,%ecx
xor    %edx,%edx
div    %cx
mov    %eax,%r8d
lea    (%r11,%r11,1),%eax
and    $0xfc0,%eax
mov    %edi,%ecx
shr    $0x5,%ecx
and    $0x3f,%ecx
mov    $0x40,%esi
sub    %ecx,%esi
xor    %edx,%edx
div    %si
mov    %eax,%r9d
and    $0x1f,%r11d
shl    $0x5,%r11d
and    $0x1f,%edi
sub    %edi,%r10d
mov    %r11d,%eax
xor    %edx,%edx
div    %r10w
cmp    $0x1f,%ax
mov    $0x1f,%ecx
cmovae %ecx,%eax
mov    %r8d,%ecx
shl    $0xb,%ecx
cmp    $0x1f,%r8w
mov    $0xf800,%edx
cmovb  %ecx,%edx
mov    %r9d,%ecx
shl    $0x5,%ecx
cmp    $0x3f,%r9w
mov    $0x7e0,%esi
cmovb  %ecx,%esi
or     %edx,%eax
or     %esi,%eax
ret

LLVM IR (-O0):
define zeroext i16 @blend_dodge16(i16 zeroext %0, i16 zeroext %1) {
%3 = alloca i16
%4 = alloca i16
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i16 %0, i16* %3
store i16 %1, i16* %4
%8 = load i16, i16* %4
%9 = zext i16 %8 to i32
%10 = ashr i32 %9, 11
%11 = mul nsw i32 %10, 32
%12 = load i16, i16* %3
%13 = zext i16 %12 to i32
%14 = ashr i32 %13, 11
%15 = sub nsw i32 32, %14
%16 = sdiv i32 %11, %15
store i32 %16, i32* %5
%17 = load i16, i16* %4
%18 = zext i16 %17 to i32
%19 = and i32 %18, 2016
%20 = ashr i32 %19, 5
%21 = mul nsw i32 %20, 64
%22 = load i16, i16* %3
%23 = zext i16 %22 to i32
%24 = and i32 %23, 2016
%25 = ashr i32 %24, 5
%26 = sub nsw i32 64, %25
%27 = sdiv i32 %21, %26
store i32 %27, i32* %6
%28 = load i16, i16* %4
%29 = zext i16 %28 to i32
%30 = and i32 %29, 31
%31 = mul nsw i32 %30, 32
%32 = load i16, i16* %3
%33 = zext i16 %32 to i32
%34 = and i32 %33, 31
%35 = sub nsw i32 32, %34
%36 = sdiv i32 %31, %35
store i32 %36, i32* %7
%37 = load i32, i32* %5
%38 = icmp sgt i32 %37, 31
br i1 %38, label %39, label %40
39: ; preds = %2
store i32 31, i32* %5
br label %40
40: ; preds = %39, %2
%41 = load i32, i32* %6
%42 = icmp sgt i32 %41, 63
br i1 %42, label %43, label %44
43: ; preds = %40
store i32 63, i32* %6
br label %44
44: ; preds = %43, %40
%45 = load i32, i32* %7
%46 = icmp sgt i32 %45, 31
br i1 %46, label %47, label %48
47: ; preds = %44
store i32 31, i32* %7
br label %48
48: ; preds = %47, %44
%49 = load i32, i32* %5
%50 = shl i32 %49, 11
%51 = load i32, i32* %6
%52 = shl i32 %51, 5
%53 = or i32 %50, %52
%54 = load i32, i32* %7
%55 = or i32 %53, %54
%56 = trunc i32 %55 to i16
ret i16 %56
}

LLVM IR (-O2):
define zeroext i16 @blend_dodge16(i16 zeroext %0, i16 zeroext %1) {
%3 = lshr i16 %1, 6
%4 = and i16 %3, 992
%5 = lshr i16 %0, 11
%6 = sub nuw nsw i16 32, %5
%7 = udiv i16 %4, %6
%8 = shl i16 %1, 1
%9 = and i16 %8, 4032
%10 = lshr i16 %0, 5
%11 = and i16 %10, 63
%12 = sub nuw nsw i16 64, %11
%13 = udiv i16 %9, %12
%14 = shl i16 %1, 5
%15 = and i16 %14, 992
%16 = and i16 %0, 31
%17 = sub nuw nsw i16 32, %16
%18 = udiv i16 %15, %17
%19 = icmp ult i16 %7, 31
%20 = icmp ult i16 %13, 63
%21 = icmp ult i16 %18, 31
%22 = select i1 %21, i16 %18, i16 31
%23 = shl i16 %7, 11
%24 = select i1 %19, i16 %23, i16 -2048
%25 = shl i16 %13, 5
%26 = select i1 %20, i16 %25, i16 2016
%27 = or i16 %26, %24
%28 = or i16 %27, %22
ret i16 %28
}