#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;
typedef int int32_t;

/* Variables and functions */
__attribute__((always_)) uint32_t __UHSUB8(uint32_t x, uint32_t y) {
  int32_t r, s, t, u;
  r = ((((x << 24) >> 24) - ((y << 24) >> 24)) >> 1) & 0x000000FF;
  s = ((((x << 16) >> 24) - ((y << 16) >> 24)) >> 1) & 0x000000FF;
  t = ((((x << 8) >> 24) - ((y << 8) >> 24)) >> 1) & 0x000000FF;
  u = ((((x) >> 24) - ((y) >> 24)) >> 1) & 0x000000FF;
  return ((u << 24) | (t << 16) | (s << 8) | (r));
}


x86 assembly (clang, -O0):
<__UHSUB8>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x4(%rbp),%eax
shl    $0x18,%eax
sar    $0x18,%eax
mov    -0x8(%rbp),%ecx
shl    $0x18,%ecx
sar    $0x18,%ecx
sub    %ecx,%eax
sar    $0x1,%eax
and    $0xff,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
shl    $0x10,%eax
sar    $0x18,%eax
mov    -0x8(%rbp),%ecx
shl    $0x10,%ecx
sar    $0x18,%ecx
sub    %ecx,%eax
sar    $0x1,%eax
and    $0xff,%eax
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
shl    $0x8,%eax
sar    $0x18,%eax
mov    -0x8(%rbp),%ecx
shl    $0x8,%ecx
sar    $0x18,%ecx
sub    %ecx,%eax
sar    $0x1,%eax
and    $0xff,%eax
mov    %eax,-0x14(%rbp)
mov    -0x4(%rbp),%eax
sar    $0x18,%eax
mov    -0x8(%rbp),%ecx
sar    $0x18,%ecx
sub    %ecx,%eax
sar    $0x1,%eax
and    $0xff,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
shl    $0x18,%eax
mov    -0x14(%rbp),%ecx
shl    $0x10,%ecx
or     %ecx,%eax
mov    -0x10(%rbp),%ecx
shl    $0x8,%ecx
or     %ecx,%eax
or     -0xc(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<__UHSUB8>:
movsbl %dil,%eax
movsbl %sil,%ecx
sub    %ecx,%eax
shr    %eax
movzbl %al,%r8d
mov    %edi,%eax
shr    $0x8,%eax
movsbl %al,%eax
mov    %esi,%edx
shr    $0x8,%edx
movsbl %dl,%edx
sub    %edx,%eax
mov    %edi,%edx
shr    $0x10,%edx
movsbl %dl,%edx
mov    %esi,%ecx
shr    $0x10,%ecx
movsbl %cl,%ecx
sub    %ecx,%edx
sar    $0x18,%edi
sar    $0x18,%esi
sub    %esi,%edi
and    $0xfffffffe,%edi
shl    $0x17,%edi
shl    $0xf,%edx
and    $0xff0000,%edx
or     %edi,%edx
shl    $0x7,%eax
and    $0xff00,%eax
or     %edx,%eax
or     %r8d,%eax
ret

LLVM IR (-O0):
define i32 @__UHSUB8(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%9 = load i32, i32* %3
%10 = shl i32 %9, 24
%11 = ashr i32 %10, 24
%12 = load i32, i32* %4
%13 = shl i32 %12, 24
%14 = ashr i32 %13, 24
%15 = sub nsw i32 %11, %14
%16 = ashr i32 %15, 1
%17 = and i32 %16, 255
store i32 %17, i32* %5
%18 = load i32, i32* %3
%19 = shl i32 %18, 16
%20 = ashr i32 %19, 24
%21 = load i32, i32* %4
%22 = shl i32 %21, 16
%23 = ashr i32 %22, 24
%24 = sub nsw i32 %20, %23
%25 = ashr i32 %24, 1
%26 = and i32 %25, 255
store i32 %26, i32* %6
%27 = load i32, i32* %3
%28 = shl i32 %27, 8
%29 = ashr i32 %28, 24
%30 = load i32, i32* %4
%31 = shl i32 %30, 8
%32 = ashr i32 %31, 24
%33 = sub nsw i32 %29, %32
%34 = ashr i32 %33, 1
%35 = and i32 %34, 255
store i32 %35, i32* %7
%36 = load i32, i32* %3
%37 = ashr i32 %36, 24
%38 = load i32, i32* %4
%39 = ashr i32 %38, 24
%40 = sub nsw i32 %37, %39
%41 = ashr i32 %40, 1
%42 = and i32 %41, 255
store i32 %42, i32* %8
%43 = load i32, i32* %8
%44 = shl i32 %43, 24
%45 = load i32, i32* %7
%46 = shl i32 %45, 16
%47 = or i32 %44, %46
%48 = load i32, i32* %6
%49 = shl i32 %48, 8
%50 = or i32 %47, %49
%51 = load i32, i32* %5
%52 = or i32 %50, %51
ret i32 %52
}

LLVM IR (-O2):
define i32 @__UHSUB8(i32 %0, i32 %1) {
%3 = shl i32 %0, 24
%4 = ashr exact i32 %3, 24
%5 = shl i32 %1, 24
%6 = ashr exact i32 %5, 24
%7 = sub nsw i32 %4, %6
%8 = lshr i32 %7, 1
%9 = and i32 %8, 255
%10 = shl i32 %0, 16
%11 = ashr i32 %10, 24
%12 = shl i32 %1, 16
%13 = ashr i32 %12, 24
%14 = sub nsw i32 %11, %13
%15 = shl i32 %0, 8
%16 = ashr i32 %15, 24
%17 = shl i32 %1, 8
%18 = ashr i32 %17, 24
%19 = sub nsw i32 %16, %18
%20 = ashr i32 %0, 24
%21 = ashr i32 %1, 24
%22 = sub nsw i32 %20, %21
%23 = shl nsw i32 %22, 23
%24 = and i32 %23, -16777216
%25 = shl nsw i32 %19, 15
%26 = and i32 %25, 16711680
%27 = or i32 %26, %24
%28 = shl nsw i32 %14, 7
%29 = and i32 %28, 65280
%30 = or i32 %27, %29
%31 = or i32 %30, %9
ret i32 %31
}