const char *ctype_str(unsigned val) {
  switch (val) {
  case 0:
    return "no cache";
  case 1:
    return "Icache only";
  case 2:
    return "Dcache only";
  case 3:
    return "Separate Icache, Dcache";
  case 4:
    return "Unified cache";
  }
  return "-";
}


x86 assembly (clang, -O0):
<ctype_str>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0xc(%rbp)
mov    -0xc(%rbp),%eax
mov    %rax,-0x18(%rbp)
sub    $0x4,%rax
ja     117c <ctype_str+0x7c>
mov    -0x18(%rbp),%rax
lea    0xedd(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
lea    0xee1(%rip),%rax
mov    %rax,-0x8(%rbp)
jmp    1187 <ctype_str+0x87>
lea    0xeda(%rip),%rax
mov    %rax,-0x8(%rbp)
jmp    1187 <ctype_str+0x87>
lea    0xed6(%rip),%rax
mov    %rax,-0x8(%rbp)
jmp    1187 <ctype_str+0x87>
lea    0xed2(%rip),%rax
mov    %rax,-0x8(%rbp)
jmp    1187 <ctype_str+0x87>
lea    0xeda(%rip),%rax
mov    %rax,-0x8(%rbp)
jmp    1187 <ctype_str+0x87>
lea    0xed8(%rip),%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ctype_str>:
cmp    $0x4,%edi
ja     1117 <ctype_str+0x17>
movslq %edi,%rax
lea    0xf3d(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
ret
lea    0xf29(%rip),%rax
ret

LLVM IR (-O0):
@.str = [9 x i8] c"no cache\00"
@.str.1 = [12 x i8] c"Icache only\00"
@.str.2 = [12 x i8] c"Dcache only\00"
@.str.3 = [24 x i8] c"Separate Icache, Dcache\00"
@.str.4 = [14 x i8] c"Unified cache\00"
@.str.5 = [2 x i8] c"-\00"
define i8* @ctype_str(i32 %0) {
%2 = alloca i8*
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
switch i32 %4, label %10 [
i32 0, label %5
i32 1, label %6
i32 2, label %7
i32 3, label %8
i32 4, label %9
]
5: ; preds = %1
store i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i64 0, i64 0), i8** %2
br label %11
6: ; preds = %1
store i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.1, i64 0, i64 0), i8** %2
br label %11
7: ; preds = %1
store i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.2, i64 0, i64 0), i8** %2
br label %11
8: ; preds = %1
store i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str.3, i64 0, i64 0), i8** %2
br label %11
9: ; preds = %1
store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.4, i64 0, i64 0), i8** %2
br label %11
10: ; preds = %1
store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.5, i64 0, i64 0), i8** %2
br label %11
11: ; preds = %10, %9, %8, %7, %6, %5
%12 = load i8*, i8** %2
ret i8* %12
}

LLVM IR (-O2):
@.str = [9 x i8] c"no cache\00"
@.str.1 = [12 x i8] c"Icache only\00"
@.str.2 = [12 x i8] c"Dcache only\00"
@.str.3 = [24 x i8] c"Separate Icache, Dcache\00"
@.str.4 = [14 x i8] c"Unified cache\00"
@.str.5 = [2 x i8] c"-\00"
@reltable.ctype_str = [5 x i32] [i32 trunc (i64 sub (i64 ptrtoint ([9 x i8]* @.str to i64), i64 ptrtoint ([5 x i32]* @reltable.ctype_str to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([12 x i8]* @.str.1 to i64), i64 ptrtoint ([5 x i32]* @reltable.ctype_str to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([12 x i8]* @.str.2 to i64), i64 ptrtoint ([5 x i32]* @reltable.ctype_str to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([24 x i8]* @.str.3 to i64), i64 ptrtoint ([5 x i32]* @reltable.ctype_str to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([14 x i8]* @.str.4 to i64), i64 ptrtoint ([5 x i32]* @reltable.ctype_str to i64)) to i32)]
define i8* @ctype_str(i32 %0) {
%2 = icmp ult i32 %0, 5
br i1 %2, label %3, label %7
3: ; preds = %1
%4 = sext i32 %0 to i64
%5 = shl i64 %4, 2
%6 = call i8* @llvm.load.relative.i64(i8* bitcast ([5 x i32]* @reltable.ctype_str to i8*), i64 %5)
br label %7
7: ; preds = %1, %3
%8 = phi i8* [ %6, %3 ], [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str.5, i64 0, i64 0), %1 ]
ret i8* %8
}