#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
char *calloc(int, int);
int /*<<< orphan*/ free(char *);
char *regalloc(char *);
int /*<<< orphan*/ register_call_signal_tree(char *, char *, int /*<<< orphan*/,
                                             int, int /*<<< orphan*/);
int /*<<< orphan*/ sprintf(char *, char *, char *, char *);
int /*<<< orphan*/ strcat(char *, char *);
int /*<<< orphan*/ strcmp(char *, char *);
int /*<<< orphan*/ strcpy(char *, char *);
int create_verilog_call_result(char *name, char *reg, char *type, char *buf,
                               int is_call) {
  char *temp;
  char *str;
  int width;
  temp = calloc(1024, 1);
  strcpy(buf, "");
  str = regalloc(reg);
  sprintf(temp, "\t\t\t%s <= __call_%s_result;\n", str, name);
  free(str);
  strcat(buf, temp);
  if (!strcmp(type, "i8")) {
    width = 8;
  } else if (!strcmp(type, "i16")) {
    width = 16;
  } else if (!strcmp(type, "i32") || !strcmp(type, "i8*") ||
             !strcmp(type, "i16*") || !strcmp(type, "i32*")) {
    width = 32;
  } else {
    width = 32;
  }
  if (!is_call)
    register_call_signal_tree(name, "result", 0, width, 0);
  free(temp);
  return 0;
}


x86 assembly (clang, -O0):
<create_verilog_call_result>:
push   %rbp
mov    %rsp,%rbp
sub    $0x40,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8d,-0x24(%rbp)
mov    $0x400,%edi
mov    $0x1,%esi
call   1060 <calloc@plt>
mov    %rax,-0x30(%rbp)
mov    -0x20(%rbp),%rdi
lea    0xe61(%rip),%rsi
call   1050 <strcpy@plt>
mov    -0x10(%rbp),%rdi
call   1030 <regalloc@plt>
mov    %rax,-0x38(%rbp)
mov    -0x30(%rbp),%rdi
mov    -0x38(%rbp),%rdx
mov    -0x8(%rbp),%rcx
lea    0xe21(%rip),%rsi
call   10a0 <sprintf@plt>
mov    -0x38(%rbp),%rdi
call   1040 <free@plt>
mov    -0x20(%rbp),%rdi
mov    -0x30(%rbp),%rsi
call   1090 <strcat@plt>
mov    -0x18(%rbp),%rdi
lea    0xe17(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
jne    121f <create_verilog_call_result+0x9f>
movl   $0x8,-0x3c(%rbp)
jmp    12c5 <create_verilog_call_result+0x145>
mov    -0x18(%rbp),%rdi
lea    0xdf5(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
jne    1244 <create_verilog_call_result+0xc4>
movl   $0x10,-0x3c(%rbp)
jmp    12c0 <create_verilog_call_result+0x140>
mov    -0x18(%rbp),%rdi
lea    0xdd4(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
je     12a8 <create_verilog_call_result+0x128>
mov    -0x18(%rbp),%rdi
lea    0xdbf(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
je     12a8 <create_verilog_call_result+0x128>
mov    -0x18(%rbp),%rdi
lea    0xdaa(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
je     12a8 <create_verilog_call_result+0x128>
mov    -0x18(%rbp),%rdi
lea    0xd96(%rip),%rsi
call   1070 <strcmp@plt>
cmp    $0x0,%eax
jne    12b4 <create_verilog_call_result+0x134>
movl   $0x20,-0x3c(%rbp)
jmp    12bb <create_verilog_call_result+0x13b>
movl   $0x20,-0x3c(%rbp)
jmp    12c0 <create_verilog_call_result+0x140>
jmp    12c5 <create_verilog_call_result+0x145>
cmpl   $0x0,-0x24(%rbp)
jne    12e8 <create_verilog_call_result+0x168>
mov    -0x8(%rbp),%rdi
mov    -0x3c(%rbp),%ecx
lea    0xd58(%rip),%rsi
xor    %r8d,%r8d
mov    %r8d,%edx
call   1080 <register_call_signal_tree@plt>
mov    -0x30(%rbp),%rdi
call   1040 <free@plt>
xor    %eax,%eax
add    $0x40,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<create_verilog_call_result>:
push   %rbp
push   %r15
push   %r14
push   %r13
push   %r12
push   %rbx
push   %rax
mov    %r8d,%r15d
mov    %rcx,%rbp
mov    %rdx,%r12
mov    %rsi,%rbx
mov    %rdi,%r14
mov    $0x400,%edi
mov    $0x1,%esi
call   1060 <calloc@plt>
mov    %rax,%r13
lea    0xe68(%rip),%rsi
mov    %rbp,%rdi
call   1050 <strcpy@plt>
mov    %rbx,%rdi
call   1030 <regalloc@plt>
mov    %rax,%rbx
lea    0xe33(%rip),%rsi
mov    %r13,%rdi
mov    %rax,%rdx
mov    %r14,%rcx
call   10a0 <sprintf@plt>
mov    %rbx,%rdi
call   1040 <free@plt>
mov    %rbp,%rdi
mov    %r13,%rsi
call   1090 <strcat@plt>
lea    0xe27(%rip),%rsi
mov    %r12,%rdi
call   1070 <strcmp@plt>
test   %eax,%eax
je     124f <create_verilog_call_result+0xcf>
lea    0xe17(%rip),%rsi
mov    %r12,%rdi
call   1070 <strcmp@plt>
xor    %ecx,%ecx
test   %eax,%eax
setne  %cl
shl    $0x4,%ecx
add    $0x10,%ecx
test   %r15d,%r15d
jne    1236 <create_verilog_call_result+0xb6>
lea    0xdfa(%rip),%rsi
mov    %r14,%rdi
xor    %edx,%edx
xor    %r8d,%r8d
call   1080 <register_call_signal_tree@plt>
mov    %r13,%rdi
call   1040 <free@plt>
xor    %eax,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r13
pop    %r14
pop    %r15
pop    %rbp
ret
mov    $0x8,%ecx
test   %r15d,%r15d
jne    1236 <create_verilog_call_result+0xb6>
jmp    1222 <create_verilog_call_result+0xa2>

LLVM IR (-O0):
@.str = [1 x i8] zeroinitializer
@.str.1 = [28 x i8] c"\09\09\09%s <= __call_%s_result;\0A\00"
@.str.2 = [3 x i8] c"i8\00"
@.str.3 = [4 x i8] c"i16\00"
@.str.4 = [4 x i8] c"i32\00"
@.str.5 = [4 x i8] c"i8*\00"
@.str.6 = [5 x i8] c"i16*\00"
@.str.7 = [5 x i8] c"i32*\00"
@.str.8 = [7 x i8] c"result\00"
define i32 @create_verilog_call_result(i8* %0, i8* %1, i8* %2, i8* %3, i32 %4) {
%6 = alloca i8*
%7 = alloca i8*
%8 = alloca i8*
%9 = alloca i8*
%10 = alloca i32
%11 = alloca i8*
%12 = alloca i8*
%13 = alloca i32
store i8* %0, i8** %6
store i8* %1, i8** %7
store i8* %2, i8** %8
store i8* %3, i8** %9
store i32 %4, i32* %10
%14 = call i8* @calloc(i32 1024, i32 1)
store i8* %14, i8** %11
%15 = load i8*, i8** %9
%16 = call i32 @strcpy(i8* %15, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0))
%17 = load i8*, i8** %7
%18 = call i8* @regalloc(i8* %17)
store i8* %18, i8** %12
%19 = load i8*, i8** %11
%20 = load i8*, i8** %12
%21 = load i8*, i8** %6
%22 = call i32 @sprintf(i8* %19, i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i64 0, i64 0), i8* %20, i8* %21)
%23 = load i8*, i8** %12
%24 = call i32 @free(i8* %23)
%25 = load i8*, i8** %9
%26 = load i8*, i8** %11
%27 = call i32 @strcat(i8* %25, i8* %26)
%28 = load i8*, i8** %8
%29 = call i32 @strcmp(i8* %28, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.2, i64 0, i64 0))
%30 = icmp ne i32 %29, 0
br i1 %30, label %32, label %31
31: ; preds = %5
store i32 8, i32* %13
br label %57
32: ; preds = %5
%33 = load i8*, i8** %8
%34 = call i32 @strcmp(i8* %33, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.3, i64 0, i64 0))
%35 = icmp ne i32 %34, 0
br i1 %35, label %37, label %36
36: ; preds = %32
store i32 16, i32* %13
br label %56
37: ; preds = %32
%38 = load i8*, i8** %8
%39 = call i32 @strcmp(i8* %38, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.4, i64 0, i64 0))
%40 = icmp ne i32 %39, 0
br i1 %40, label %41, label %53
41: ; preds = %37
%42 = load i8*, i8** %8
%43 = call i32 @strcmp(i8* %42, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.5, i64 0, i64 0))
%44 = icmp ne i32 %43, 0
br i1 %44, label %45, label %53
45: ; preds = %41
%46 = load i8*, i8** %8
%47 = call i32 @strcmp(i8* %46, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.6, i64 0, i64 0))
%48 = icmp ne i32 %47, 0
br i1 %48, label %49, label %53
49: ; preds = %45
%50 = load i8*, i8** %8
%51 = call i32 @strcmp(i8* %50, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.7, i64 0, i64 0))
%52 = icmp ne i32 %51, 0
br i1 %52, label %54, label %53
53: ; preds = %49, %45, %41, %37
store i32 32, i32* %13
br label %55
54: ; preds = %49
store i32 32, i32* %13
br label %55
55: ; preds = %54, %53
br label %56
56: ; preds = %55, %36
br label %57
57: ; preds = %56, %31
%58 = load i32, i32* %10
%59 = icmp ne i32 %58, 0
br i1 %59, label %64, label %60
60: ; preds = %57
%61 = load i8*, i8** %6
%62 = load i32, i32* %13
%63 = call i32 @register_call_signal_tree(i8* %61, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.8, i64 0, i64 0), i32 0, i32 %62, i32 0)
br label %64
64: ; preds = %60, %57
%65 = load i8*, i8** %11
%66 = call i32 @free(i8* %65)
ret i32 0
}

LLVM IR (-O2):
@.str = [1 x i8] zeroinitializer
@.str.1 = [28 x i8] c"\09\09\09%s <= __call_%s_result;\0A\00"
@.str.2 = [3 x i8] c"i8\00"
@.str.3 = [4 x i8] c"i16\00"
@.str.8 = [7 x i8] c"result\00"
define i32 @create_verilog_call_result(i8* %0, i8* %1, i8* nocapture %2, i8* %3, i32 %4) {
%6 = tail call dereferenceable_or_null(1024) i8* @calloc(i32 1024, i32 1)
%7 = tail call i32 @strcpy(i8* %3, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0))
%8 = tail call i8* @regalloc(i8* %1)
%9 = tail call i32 @sprintf(i8* dereferenceable(1) %6, i8* dereferenceable(1) getelementptr inbounds ([28 x i8], [28 x i8]* @.str.1, i64 0, i64 0), i8* %8, i8* %0)
%10 = tail call i32 @free(i8* %8)
%11 = tail call i32 @strcat(i8* %3, i8* %6)
%12 = tail call i32 @strcmp(i8* dereferenceable(1) %2, i8* dereferenceable(3) getelementptr inbounds ([3 x i8], [3 x i8]* @.str.2, i64 0, i64 0))
%13 = icmp eq i32 %12, 0
br i1 %13, label %18, label %14
14: ; preds = %5
%15 = tail call i32 @strcmp(i8* dereferenceable(1) %2, i8* dereferenceable(4) getelementptr inbounds ([4 x i8], [4 x i8]* @.str.3, i64 0, i64 0))
%16 = icmp eq i32 %15, 0
%17 = select i1 %16, i32 16, i32 32
br label %18
18: ; preds = %14, %5
%19 = phi i32 [ 8, %5 ], [ %17, %14 ]
%20 = icmp eq i32 %4, 0
br i1 %20, label %21, label %23
21: ; preds = %18
%22 = tail call i32 @register_call_signal_tree(i8* %0, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.8, i64 0, i64 0), i32 0, i32 %19, i32 0)
br label %23
23: ; preds = %21, %18
%24 = tail call i32 @free(i8* %6)
ret i32 0
}