void IntDisable(unsigned long ulInterrupt) {
  ;
  if (ulInterrupt == 4) {
    (*((volatile unsigned long *)(0xE000ED24))) &= ~(0x00010000);
  } else if (ulInterrupt == 5) {
    (*((volatile unsigned long *)(0xE000ED24))) &= ~(0x00020000);
  } else if (ulInterrupt == 6) {
    (*((volatile unsigned long *)(0xE000ED24))) &= ~(0x00040000);
  } else if (ulInterrupt == 15) {
    (*((volatile unsigned long *)(0xE000E010))) &= ~(0x00000002);
  } else if ((ulInterrupt >= 16) && (ulInterrupt <= 47)) {
    (*((volatile unsigned long *)(0xE000E180))) = 1 << (ulInterrupt - 16);
  } else if ((ulInterrupt >= 48) && (ulInterrupt <= 79)) {
    (*((volatile unsigned long *)(0xE000E184))) = 1 << (ulInterrupt - 48);
  } else if (ulInterrupt >= 80) {
    (*((volatile unsigned long *)(0xE000E188))) = 1 << (ulInterrupt - 80);
  }
}


x86 assembly (clang, -O0):
<IntDisable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
cmpq   $0x4,-0x8(%rbp)
jne    112f <IntDisable+0x2f>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
and    $0xfffffffffffeffff,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    1254 <IntDisable+0x154>
cmpq   $0x5,-0x8(%rbp)
jne    1156 <IntDisable+0x56>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
and    $0xfffffffffffdffff,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    124f <IntDisable+0x14f>
cmpq   $0x6,-0x8(%rbp)
jne    117d <IntDisable+0x7d>
mov    $0xe000ed24,%eax
mov    (%rax),%rcx
and    $0xfffffffffffbffff,%rcx
mov    $0xe000ed24,%eax
mov    %rcx,(%rax)
jmp    124a <IntDisable+0x14a>
cmpq   $0xf,-0x8(%rbp)
jne    11a1 <IntDisable+0xa1>
mov    $0xe000e010,%eax
mov    (%rax),%rcx
and    $0xfffffffffffffffd,%rcx
mov    $0xe000e010,%eax
mov    %rcx,(%rax)
jmp    1245 <IntDisable+0x145>
cmpq   $0x10,-0x8(%rbp)
jb     11d8 <IntDisable+0xd8>
cmpq   $0x2f,-0x8(%rbp)
ja     11d8 <IntDisable+0xd8>
mov    -0x8(%rbp),%rax
sub    $0x10,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0xe000e180,%eax
mov    %rcx,(%rax)
jmp    1240 <IntDisable+0x140>
cmpq   $0x30,-0x8(%rbp)
jb     120f <IntDisable+0x10f>
cmpq   $0x4f,-0x8(%rbp)
ja     120f <IntDisable+0x10f>
mov    -0x8(%rbp),%rax
sub    $0x30,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0xe000e184,%eax
mov    %rcx,(%rax)
jmp    123b <IntDisable+0x13b>
cmpq   $0x50,-0x8(%rbp)
jb     1236 <IntDisable+0x136>
mov    -0x8(%rbp),%rax
sub    $0x50,%rax
mov    %eax,%ecx
mov    $0x1,%eax
shl    %cl,%eax
movslq %eax,%rcx
mov    $0xe000e188,%eax
mov    %rcx,(%rax)
jmp    123b <IntDisable+0x13b>
jmp    1240 <IntDisable+0x140>
jmp    1245 <IntDisable+0x145>
jmp    124a <IntDisable+0x14a>
jmp    124f <IntDisable+0x14f>
jmp    1254 <IntDisable+0x154>
pop    %rbp
ret

x86 assembly (clang, -O2):
<IntDisable>:
lea    -0x4(%rdi),%rax
cmp    $0xb,%rax
ja     114f <IntDisable+0x4f>
lea    0xeef(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    $0xe000ed24,%eax
andq   $0xfffffffffffeffff,(%rax)
ret
mov    $0xe000ed24,%eax
andq   $0xfffffffffffdffff,(%rax)
ret
mov    $0xe000ed24,%eax
andq   $0xfffffffffffbffff,(%rax)
ret
mov    $0xe000ed24,%eax
andq   $0xfffffffffffffffd,-0xd14(%rax)
fd
ret
lea    -0x10(%rdi),%rax
cmp    $0x1f,%rax
ja     1175 <IntDisable+0x75>
add    $0xf0,%dil
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
cltq
mov    $0xe000ed24,%ecx
mov    %rax,-0xba4(%rcx)
ret
lea    -0x30(%rdi),%rax
cmp    $0x1f,%rax
ja     119b <IntDisable+0x9b>
add    $0xd0,%dil
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
cltq
mov    $0xe000ed24,%ecx
mov    %rax,-0xba0(%rcx)
ret
cmp    $0x50,%rdi
jb     11bc <IntDisable+0xbc>
add    $0xb0,%dil
mov    $0x1,%eax
mov    %edi,%ecx
shl    %cl,%eax
cltq
mov    $0xe000ed24,%ecx
mov    %rax,-0xb9c(%rcx)
ret

LLVM IR (-O0):
define void @IntDisable(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = icmp eq i64 %3, 4
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%7 = and i64 %6, -65537
store volatile i64 %7, i64* inttoptr (i64 3758157092 to i64*)
br label %65
8: ; preds = %1
%9 = load i64, i64* %2
%10 = icmp eq i64 %9, 5
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%13 = and i64 %12, -131073
store volatile i64 %13, i64* inttoptr (i64 3758157092 to i64*)
br label %64
14: ; preds = %8
%15 = load i64, i64* %2
%16 = icmp eq i64 %15, 6
br i1 %16, label %17, label %20
17: ; preds = %14
%18 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%19 = and i64 %18, -262145
store volatile i64 %19, i64* inttoptr (i64 3758157092 to i64*)
br label %63
20: ; preds = %14
%21 = load i64, i64* %2
%22 = icmp eq i64 %21, 15
br i1 %22, label %23, label %26
23: ; preds = %20
%24 = load volatile i64, i64* inttoptr (i64 3758153744 to i64*)
%25 = and i64 %24, -3
store volatile i64 %25, i64* inttoptr (i64 3758153744 to i64*)
br label %62
26: ; preds = %20
%27 = load i64, i64* %2
%28 = icmp uge i64 %27, 16
br i1 %28, label %29, label %38
29: ; preds = %26
%30 = load i64, i64* %2
%31 = icmp ule i64 %30, 47
br i1 %31, label %32, label %38
32: ; preds = %29
%33 = load i64, i64* %2
%34 = sub i64 %33, 16
%35 = trunc i64 %34 to i32
%36 = shl i32 1, %35
%37 = sext i32 %36 to i64
store volatile i64 %37, i64* inttoptr (i64 3758154112 to i64*)
br label %61
38: ; preds = %29, %26
%39 = load i64, i64* %2
%40 = icmp uge i64 %39, 48
br i1 %40, label %41, label %50
41: ; preds = %38
%42 = load i64, i64* %2
%43 = icmp ule i64 %42, 79
br i1 %43, label %44, label %50
44: ; preds = %41
%45 = load i64, i64* %2
%46 = sub i64 %45, 48
%47 = trunc i64 %46 to i32
%48 = shl i32 1, %47
%49 = sext i32 %48 to i64
store volatile i64 %49, i64* inttoptr (i64 3758154116 to i64*)
br label %60
50: ; preds = %41, %38
%51 = load i64, i64* %2
%52 = icmp uge i64 %51, 80
br i1 %52, label %53, label %59
53: ; preds = %50
%54 = load i64, i64* %2
%55 = sub i64 %54, 80
%56 = trunc i64 %55 to i32
%57 = shl i32 1, %56
%58 = sext i32 %57 to i64
store volatile i64 %58, i64* inttoptr (i64 3758154120 to i64*)
br label %59
59: ; preds = %53, %50
br label %60
60: ; preds = %59, %44
br label %61
61: ; preds = %60, %32
br label %62
62: ; preds = %61, %23
br label %63
63: ; preds = %62, %17
br label %64
64: ; preds = %63, %11
br label %65
65: ; preds = %64, %5
ret void
}

LLVM IR (-O2):
define void @IntDisable(i64 %0) {
switch i64 %0, label %14 [
i64 4, label %2
i64 5, label %5
i64 6, label %8
i64 15, label %11
]
2: ; preds = %1
%3 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%4 = and i64 %3, -65537
store volatile i64 %4, i64* inttoptr (i64 3758157092 to i64*)
br label %37
5: ; preds = %1
%6 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%7 = and i64 %6, -131073
store volatile i64 %7, i64* inttoptr (i64 3758157092 to i64*)
br label %37
8: ; preds = %1
%9 = load volatile i64, i64* inttoptr (i64 3758157092 to i64*)
%10 = and i64 %9, -262145
store volatile i64 %10, i64* inttoptr (i64 3758157092 to i64*)
br label %37
11: ; preds = %1
%12 = load volatile i64, i64* inttoptr (i64 3758153744 to i64*)
%13 = and i64 %12, -3
store volatile i64 %13, i64* inttoptr (i64 3758153744 to i64*)
br label %37
14: ; preds = %1
%15 = add i64 %0, -16
%16 = icmp ult i64 %15, 32
br i1 %16, label %17, label %22
17: ; preds = %14
%18 = trunc i64 %0 to i32
%19 = add nsw i32 %18, -16
%20 = shl nuw i32 1, %19
%21 = sext i32 %20 to i64
store volatile i64 %21, i64* inttoptr (i64 3758154112 to i64*)
br label %37
22: ; preds = %14
%23 = add i64 %0, -48
%24 = icmp ult i64 %23, 32
br i1 %24, label %25, label %30
25: ; preds = %22
%26 = trunc i64 %0 to i32
%27 = add nsw i32 %26, -48
%28 = shl nuw i32 1, %27
%29 = sext i32 %28 to i64
store volatile i64 %29, i64* inttoptr (i64 3758154116 to i64*)
br label %37
30: ; preds = %22
%31 = icmp ugt i64 %0, 79
br i1 %31, label %32, label %37
32: ; preds = %30
%33 = trunc i64 %0 to i32
%34 = add i32 %33, -80
%35 = shl nuw i32 1, %34
%36 = sext i32 %35 to i64
store volatile i64 %36, i64* inttoptr (i64 3758154120 to i64*)
br label %37
37: ; preds = %5, %11, %25, %32, %30, %17, %8, %2
ret void
}