unsigned short VIM_HIF_GetReg16(unsigned long adr) {
  unsigned short uTemp;
  if ((adr & 0x1) == 0) {
    ;
    *(volatile unsigned short *)(0x8000000) = (unsigned short)adr;
    ;
    uTemp = (unsigned short)(*(volatile unsigned short *)(0x8000100));
  } else {
    ;
    *(volatile unsigned short *)(0x8000000) = (unsigned short)adr - 0x01;
    ;
    uTemp = (0xff &
             ((unsigned short)(*(volatile unsigned short *)(0x8000100)) >> 8));
    ;
    *(volatile unsigned short *)(0x8000000) = (unsigned short)adr + 0x01;
    ;
    uTemp |= ((unsigned short)(*(volatile unsigned short *)(0x8000100)) << 8);
  }
  return uTemp;
}


x86 assembly (clang, -O0):
<VIM_HIF_GetReg16>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
and    $0x1,%rax
cmp    $0x0,%rax
jne    113a <VIM_HIF_GetReg16+0x3a>
mov    -0x8(%rbp),%rax
mov    %ax,%cx
mov    $0x8000000,%eax
mov    %cx,(%rax)
mov    $0x8000100,%eax
mov    (%rax),%ax
mov    %ax,-0xa(%rbp)
jmp    1193 <VIM_HIF_GetReg16+0x93>
mov    -0x8(%rbp),%rax
movzwl %ax,%eax
sub    $0x1,%eax
mov    %ax,%cx
mov    $0x8000000,%eax
mov    %cx,(%rax)
mov    $0x8000100,%eax
mov    (%rax),%ax
movzwl %ax,%eax
sar    $0x8,%eax
and    $0xff,%eax
mov    %ax,-0xa(%rbp)
mov    -0x8(%rbp),%rax
movzwl %ax,%eax
add    $0x1,%eax
mov    %ax,%cx
mov    $0x8000000,%eax
mov    %cx,(%rax)
mov    $0x8000100,%eax
mov    (%rax),%ax
movzwl %ax,%ecx
shl    $0x8,%ecx
movzwl -0xa(%rbp),%eax
or     %ecx,%eax
mov    %ax,-0xa(%rbp)
movzwl -0xa(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<VIM_HIF_GetReg16>:
test   $0x1,%dil
jne    1117 <VIM_HIF_GetReg16+0x17>
mov    %di,0x8000000
08
movzwl 0x8000100,%eax
08
ret
lea    -0x1(%rdi),%eax
mov    %ax,0x8000000
08
movzwl 0x8000100,%ecx
08
add    $0x1,%edi
mov    %di,0x8000000
08
movzwl 0x8000100,%eax
08
shld   $0x8,%cx,%ax
ret

LLVM IR (-O0):
define zeroext i16 @VIM_HIF_GetReg16(i64 %0) {
%2 = alloca i64
%3 = alloca i16
store i64 %0, i64* %2
%4 = load i64, i64* %2
%5 = and i64 %4, 1
%6 = icmp eq i64 %5, 0
br i1 %6, label %7, label %11
7: ; preds = %1
%8 = load i64, i64* %2
%9 = trunc i64 %8 to i16
store volatile i16 %9, i16* inttoptr (i64 134217728 to i16*)
%10 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
store i16 %10, i16* %3
br label %34
11: ; preds = %1
%12 = load i64, i64* %2
%13 = trunc i64 %12 to i16
%14 = zext i16 %13 to i32
%15 = sub nsw i32 %14, 1
%16 = trunc i32 %15 to i16
store volatile i16 %16, i16* inttoptr (i64 134217728 to i16*)
%17 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
%18 = zext i16 %17 to i32
%19 = ashr i32 %18, 8
%20 = and i32 255, %19
%21 = trunc i32 %20 to i16
store i16 %21, i16* %3
%22 = load i64, i64* %2
%23 = trunc i64 %22 to i16
%24 = zext i16 %23 to i32
%25 = add nsw i32 %24, 1
%26 = trunc i32 %25 to i16
store volatile i16 %26, i16* inttoptr (i64 134217728 to i16*)
%27 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
%28 = zext i16 %27 to i32
%29 = shl i32 %28, 8
%30 = load i16, i16* %3
%31 = zext i16 %30 to i32
%32 = or i32 %31, %29
%33 = trunc i32 %32 to i16
store i16 %33, i16* %3
br label %34
34: ; preds = %11, %7
%35 = load i16, i16* %3
ret i16 %35
}

LLVM IR (-O2):
define zeroext i16 @VIM_HIF_GetReg16(i64 %0) {
%2 = and i64 %0, 1
%3 = icmp eq i64 %2, 0
%4 = trunc i64 %0 to i16
br i1 %3, label %5, label %7
5: ; preds = %1
store volatile i16 %4, i16* inttoptr (i64 134217728 to i16*)
%6 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
br label %13
7: ; preds = %1
%8 = add i16 %4, -1
store volatile i16 %8, i16* inttoptr (i64 134217728 to i16*)
%9 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
%10 = add i16 %4, 1
store volatile i16 %10, i16* inttoptr (i64 134217728 to i16*)
%11 = load volatile i16, i16* inttoptr (i64 134217984 to i16*)
%12 = tail call i16 @llvm.fshl.i16(i16 %11, i16 %9, i16 8)
br label %13
13: ; preds = %7, %5
%14 = phi i16 [ %6, %5 ], [ %12, %7 ]
ret i16 %14
}