int dot11_to_ratecode(int dot11) {
  switch (dot11) {
  case 12:
    return 11;
  case 18:
    return 15;
  case 24:
    return 10;
  case 36:
    return 14;
  case 48:
    return 9;
  case 72:
    return 13;
  case 96:
    return 8;
  case 108:
    return 12;
  case 2:
    return 0x1b;
  case 4:
    return 0x1e;
  case 11:
    return 0x1d;
  case 22:
    return 0x1c;
  }
  return 0;
}


x86 assembly (clang, -O0):
<dot11_to_ratecode>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
add    $0xfffffffe,%eax
mov    %eax,%ecx
mov    %rcx,-0x10(%rbp)
sub    $0x6a,%eax
ja     11c0 <dot11_to_ratecode+0xc0>
mov    -0x10(%rbp),%rax
lea    0xed9(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0xb,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0xf,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0xa,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0xe,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x9,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0xd,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x8,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0xc,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x1b,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x1e,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x1d,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x1c,-0x4(%rbp)
jmp    11c7 <dot11_to_ratecode+0xc7>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<dot11_to_ratecode>:
add    $0xfffffffe,%edi
cmp    $0x6a,%edi
ja     1123 <dot11_to_ratecode+0x23>
mov    $0xb,%eax
lea    0xeec(%rip),%rcx
movslq (%rcx,%rdi,4),%rdx
add    %rcx,%rdx
jmp    *%rdx
mov    $0x1b,%eax
ret
xor    %eax,%eax
ret
mov    $0x1e,%eax
ret
mov    $0x1d,%eax
ret
mov    $0xf,%eax
ret
mov    $0x1c,%eax
ret
mov    $0xa,%eax
ret
mov    $0xe,%eax
ret
mov    $0x9,%eax
ret
mov    $0xd,%eax
ret
mov    $0x8,%eax
ret
mov    $0xc,%eax
ret

LLVM IR (-O0):
define i32 @dot11_to_ratecode(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
switch i32 %4, label %17 [
i32 12, label %5
i32 18, label %6
i32 24, label %7
i32 36, label %8
i32 48, label %9
i32 72, label %10
i32 96, label %11
i32 108, label %12
i32 2, label %13
i32 4, label %14
i32 11, label %15
i32 22, label %16
]
5: ; preds = %1
store i32 11, i32* %2
br label %18
6: ; preds = %1
store i32 15, i32* %2
br label %18
7: ; preds = %1
store i32 10, i32* %2
br label %18
8: ; preds = %1
store i32 14, i32* %2
br label %18
9: ; preds = %1
store i32 9, i32* %2
br label %18
10: ; preds = %1
store i32 13, i32* %2
br label %18
11: ; preds = %1
store i32 8, i32* %2
br label %18
12: ; preds = %1
store i32 12, i32* %2
br label %18
13: ; preds = %1
store i32 27, i32* %2
br label %18
14: ; preds = %1
store i32 30, i32* %2
br label %18
15: ; preds = %1
store i32 29, i32* %2
br label %18
16: ; preds = %1
store i32 28, i32* %2
br label %18
17: ; preds = %1
store i32 0, i32* %2
br label %18
18: ; preds = %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5
%19 = load i32, i32* %2
ret i32 %19
}

LLVM IR (-O2):
define i32 @dot11_to_ratecode(i32 %0) {
switch i32 %0, label %13 [
i32 12, label %14
i32 18, label %2
i32 24, label %3
i32 36, label %4
i32 48, label %5
i32 72, label %6
i32 96, label %7
i32 108, label %8
i32 2, label %9
i32 4, label %10
i32 11, label %11
i32 22, label %12
]
2: ; preds = %1
br label %14
3: ; preds = %1
br label %14
4: ; preds = %1
br label %14
5: ; preds = %1
br label %14
6: ; preds = %1
br label %14
7: ; preds = %1
br label %14
8: ; preds = %1
br label %14
9: ; preds = %1
br label %14
10: ; preds = %1
br label %14
11: ; preds = %1
br label %14
12: ; preds = %1
br label %14
13: ; preds = %1
br label %14
14: ; preds = %1, %13, %12, %11, %10, %9, %8, %7, %6, %5, %4, %3, %2
%15 = phi i32 [ 0, %13 ], [ 28, %12 ], [ 29, %11 ], [ 30, %10 ], [ 27, %9 ], [ 12, %8 ], [ 8, %7 ], [ 13, %6 ], [ 9, %5 ], [ 14, %4 ], [ 10, %3 ], [ 15, %2 ], [ 11, %1 ]
ret i32 %15
}