void GPMCIntEnable(unsigned int baseAddr, unsigned int flag) {
  switch (flag) {
  case (0):
    (*((volatile unsigned int *)(baseAddr + (0x1C)))) |= (0x00000001u);
    break;
  case (1):
    (*((volatile unsigned int *)(baseAddr + (0x1C)))) |= ((0x00000002u));
    break;
  case (2):
    (*((volatile unsigned int *)(baseAddr + (0x1C)))) |= ((0x00000100u));
    break;
  case (3):
    (*((volatile unsigned int *)(baseAddr + (0x1C)))) |= ((0x00000200u));
    break;
  }
}


x86 assembly (clang, -O0):
<GPMCIntEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
mov    %rax,-0x10(%rbp)
sub    $0x3,%rax
ja     1180 <GPMCIntEnable+0x80>
mov    -0x10(%rbp),%rax
lea    0xeda(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x1,%ecx
mov    %ecx,(%rax)
jmp    1180 <GPMCIntEnable+0x80>
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    %ecx,(%rax)
jmp    1180 <GPMCIntEnable+0x80>
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x100,%ecx
mov    %ecx,(%rax)
jmp    1180 <GPMCIntEnable+0x80>
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x200,%ecx
mov    %ecx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<GPMCIntEnable>:
cmp    $0x3,%esi
ja     1117 <GPMCIntEnable+0x17>
movslq %esi,%rax
lea    0xef1(%rip),%rcx
mov    (%rcx,%rax,4),%eax
add    $0x1c,%edi
or     %eax,(%rdi)
ret

LLVM IR (-O0):
define void @GPMCIntEnable(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %4
switch i32 %5, label %34 [
i32 0, label %6
i32 1, label %13
i32 2, label %20
i32 3, label %27
]
6: ; preds = %2
%7 = load i32, i32* %3
%8 = add i32 %7, 28
%9 = zext i32 %8 to i64
%10 = inttoptr i64 %9 to i32*
%11 = load volatile i32, i32* %10
%12 = or i32 %11, 1
store volatile i32 %12, i32* %10
br label %34
13: ; preds = %2
%14 = load i32, i32* %3
%15 = add i32 %14, 28
%16 = zext i32 %15 to i64
%17 = inttoptr i64 %16 to i32*
%18 = load volatile i32, i32* %17
%19 = or i32 %18, 2
store volatile i32 %19, i32* %17
br label %34
20: ; preds = %2
%21 = load i32, i32* %3
%22 = add i32 %21, 28
%23 = zext i32 %22 to i64
%24 = inttoptr i64 %23 to i32*
%25 = load volatile i32, i32* %24
%26 = or i32 %25, 256
store volatile i32 %26, i32* %24
br label %34
27: ; preds = %2
%28 = load i32, i32* %3
%29 = add i32 %28, 28
%30 = zext i32 %29 to i64
%31 = inttoptr i64 %30 to i32*
%32 = load volatile i32, i32* %31
%33 = or i32 %32, 512
store volatile i32 %33, i32* %31
br label %34
34: ; preds = %2, %27, %20, %13, %6
ret void
}

LLVM IR (-O2):
@switch.table.GPMCIntEnable = [4 x i32] [i32 1, i32 2, i32 256, i32 512]
define void @GPMCIntEnable(i32 %0, i32 %1) {
%3 = icmp ult i32 %1, 4
br i1 %3, label %4, label %13
4: ; preds = %2
%5 = sext i32 %1 to i64
%6 = getelementptr inbounds [4 x i32], [4 x i32]* @switch.table.GPMCIntEnable, i64 0, i64 %5
%7 = load i32, i32* %6
%8 = add i32 %0, 28
%9 = zext i32 %8 to i64
%10 = inttoptr i64 %9 to i32*
%11 = load volatile i32, i32* %10
%12 = or i32 %11, %7
store volatile i32 %12, i32* %10
br label %13
13: ; preds = %2, %4
ret void
}