#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ NOROM_CPUcpsid();
int /*<<< orphan*/ NOROM_CPUcpsie();
uint32_t AuxAdiDdiSafeRead(uint32_t nAddr, uint32_t nSize) {
  uint32_t nRet;
  bool bIrqEnabled = !NOROM_CPUcpsid();
  while (!(*((volatile unsigned long *)(0x400C8000 + 0x00000000))))
    ;
  switch (nSize) {
  case 1:
    nRet = (*((volatile unsigned char *)(nAddr)));
    break;
  case 2:
    nRet = (*((volatile unsigned short *)(nAddr)));
    break;
  case 4:
  default:
    nRet = (*((volatile unsigned long *)(nAddr)));
    break;
  }
  (*((volatile unsigned long *)(0x400C8000 + 0x00000000))) = 1;
  if (bIrqEnabled) {
    NOROM_CPUcpsie();
  }
  return nRet;
}


x86 assembly (clang, -O0):
<AuxAdiDdiSafeRead>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    $0x0,%al
call   1040 <NOROM_CPUcpsid@plt>
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
and    $0x1,%al
movzbl %al,%eax
mov    %eax,-0x10(%rbp)
mov    $0x400c8000,%eax
mov    (%rax),%rax
cmp    $0x0,%rax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    1163 <AuxAdiDdiSafeRead+0x43>
jmp    1168 <AuxAdiDdiSafeRead+0x48>
jmp    1145 <AuxAdiDdiSafeRead+0x25>
mov    -0x8(%rbp),%eax
mov    %eax,-0x14(%rbp)
sub    $0x1,%eax
je     119e <AuxAdiDdiSafeRead+0x7e>
jmp    117c <AuxAdiDdiSafeRead+0x5c>
mov    -0x14(%rbp),%eax
sub    $0x2,%eax
je     11af <AuxAdiDdiSafeRead+0x8f>
jmp    118d <AuxAdiDdiSafeRead+0x6d>
mov    -0x14(%rbp),%eax
sub    $0x4,%eax
je     11c1 <AuxAdiDdiSafeRead+0xa1>
jmp    11c6 <AuxAdiDdiSafeRead+0xa6>
movslq -0x4(%rbp),%rax
mov    (%rax),%al
movzbl %al,%eax
mov    %eax,-0xc(%rbp)
jmp    11d0 <AuxAdiDdiSafeRead+0xb0>
movslq -0x4(%rbp),%rax
mov    (%rax),%ax
movzwl %ax,%eax
mov    %eax,-0xc(%rbp)
jmp    11d0 <AuxAdiDdiSafeRead+0xb0>
jmp    11c6 <AuxAdiDdiSafeRead+0xa6>
movslq -0x4(%rbp),%rax
mov    (%rax),%rax
mov    %eax,-0xc(%rbp)
mov    $0x400c8000,%eax
movq   $0x1,(%rax)
cmpl   $0x0,-0x10(%rbp)
je     11ed <AuxAdiDdiSafeRead+0xcd>
mov    $0x0,%al
call   1030 <NOROM_CPUcpsie@plt>
mov    -0xc(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<AuxAdiDdiSafeRead>:
push   %rbp
push   %rbx
push   %rax
mov    %esi,%ebp
mov    %edi,%ebx
xor    %eax,%eax
call   1040 <NOROM_CPUcpsid@plt>
xchg   %ax,%ax
cmpq   $0x0,0x400c8000
je     1130 <AuxAdiDdiSafeRead+0x10>
movslq %ebx,%rcx
cmp    $0x2,%ebp
je     114d <AuxAdiDdiSafeRead+0x2d>
cmp    $0x1,%ebp
jne    1152 <AuxAdiDdiSafeRead+0x32>
movzbl (%rcx),%ebx
jmp    1155 <AuxAdiDdiSafeRead+0x35>
movzwl (%rcx),%ebx
jmp    1155 <AuxAdiDdiSafeRead+0x35>
mov    (%rcx),%rbx
movq   $0x1,0x400c8000
test   %eax,%eax
jne    116c <AuxAdiDdiSafeRead+0x4c>
xor    %eax,%eax
call   1030 <NOROM_CPUcpsie@plt>
mov    %ebx,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
define i32 @AuxAdiDdiSafeRead(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%7 = call i32 (...) @NOROM_CPUcpsid()
%8 = icmp ne i32 %7, 0
%9 = xor i1 %8, true
%10 = zext i1 %9 to i32
store i32 %10, i32* %6
br label %11
11: ; preds = %15, %2
%12 = load volatile i64, i64* inttoptr (i64 1074561024 to i64*)
%13 = icmp ne i64 %12, 0
%14 = xor i1 %13, true
br i1 %14, label %15, label %16
15: ; preds = %11
br label %11
16: ; preds = %11
%17 = load i32, i32* %4
switch i32 %17, label %31 [
i32 1, label %18
i32 2, label %24
i32 4, label %30
]
18: ; preds = %16
%19 = load i32, i32* %3
%20 = sext i32 %19 to i64
%21 = inttoptr i64 %20 to i8*
%22 = load volatile i8, i8* %21
%23 = zext i8 %22 to i32
store i32 %23, i32* %5
br label %37
24: ; preds = %16
%25 = load i32, i32* %3
%26 = sext i32 %25 to i64
%27 = inttoptr i64 %26 to i16*
%28 = load volatile i16, i16* %27
%29 = zext i16 %28 to i32
store i32 %29, i32* %5
br label %37
30: ; preds = %16
br label %31
31: ; preds = %16, %30
%32 = load i32, i32* %3
%33 = sext i32 %32 to i64
%34 = inttoptr i64 %33 to i64*
%35 = load volatile i64, i64* %34
%36 = trunc i64 %35 to i32
store i32 %36, i32* %5
br label %37
37: ; preds = %31, %24, %18
store volatile i64 1, i64* inttoptr (i64 1074561024 to i64*)
%38 = load i32, i32* %6
%39 = icmp ne i32 %38, 0
br i1 %39, label %40, label %42
40: ; preds = %37
%41 = call i32 (...) @NOROM_CPUcpsie()
br label %42
42: ; preds = %40, %37
%43 = load i32, i32* %5
ret i32 %43
}

LLVM IR (-O2):
define i32 @AuxAdiDdiSafeRead(i32 %0, i32 %1) {
%3 = tail call i32 (...) @NOROM_CPUcpsid()
br label %4
4: ; preds = %4, %2
%5 = load volatile i64, i64* inttoptr (i64 1074561024 to i64*)
%6 = icmp eq i64 %5, 0
br i1 %6, label %4, label %7
7: ; preds = %4
%8 = icmp eq i32 %3, 0
switch i32 %1, label %19 [
i32 1, label %9
i32 2, label %14
]
9: ; preds = %7
%10 = sext i32 %0 to i64
%11 = inttoptr i64 %10 to i8*
%12 = load volatile i8, i8* %11
%13 = zext i8 %12 to i32
br label %24
14: ; preds = %7
%15 = sext i32 %0 to i64
%16 = inttoptr i64 %15 to i16*
%17 = load volatile i16, i16* %16
%18 = zext i16 %17 to i32
br label %24
19: ; preds = %7
%20 = sext i32 %0 to i64
%21 = inttoptr i64 %20 to i64*
%22 = load volatile i64, i64* %21
%23 = trunc i64 %22 to i32
br label %24
24: ; preds = %19, %14, %9
%25 = phi i32 [ %23, %19 ], [ %18, %14 ], [ %13, %9 ]
store volatile i64 1, i64* inttoptr (i64 1074561024 to i64*)
br i1 %8, label %26, label %28
26: ; preds = %24
%27 = tail call i32 (...) @NOROM_CPUcpsie()
br label %28
28: ; preds = %26, %24
ret i32 %25
}