xunge/DecIR huggingface dataset:
/* Type definitions */
typedef int uint32_t;
struct usbcan_msg {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ printf(char *, int, int, int);
void usbcandump_null_callback(uint32_t dev, uint32_t bus,
                              struct usbcan_msg *msgs, uint32_t n, void *arg) {
#pragma unused(msgs)
#pragma unused(arg)
  printf("Received unexpected callback with %u messages %u/%u\n", n, dev, bus);
}


x86 assembly (clang, -O0):
<usbcandump_null_callback>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %rdx,-0x10(%rbp)
mov    %ecx,-0x14(%rbp)
mov    %r8,-0x20(%rbp)
mov    -0x14(%rbp),%esi
mov    -0x4(%rbp),%edx
mov    -0x8(%rbp),%ecx
lea    0xec7(%rip),%rdi
call   1030 <printf@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<usbcandump_null_callback>:
mov    %esi,%eax
mov    %edi,%edx
lea    0xee5(%rip),%rdi
mov    %ecx,%esi
mov    %eax,%ecx
jmp    1030 <printf@plt>

LLVM IR (-O0):
%struct.usbcan_msg = type { i32 }
@.str = [53 x i8] c"Received unexpected callback with %u messages %u/%u\0A\00"
define void @usbcandump_null_callback(i32 %0, i32 %1, %struct.usbcan_msg* %2, i32 %3, i8* %4) {
%6 = alloca i32
%7 = alloca i32
%8 = alloca %struct.usbcan_msg*
%9 = alloca i32
%10 = alloca i8*
store i32 %0, i32* %6
store i32 %1, i32* %7
store %struct.usbcan_msg* %2, %struct.usbcan_msg** %8
store i32 %3, i32* %9
store i8* %4, i8** %10
%11 = load i32, i32* %9
%12 = load i32, i32* %6
%13 = load i32, i32* %7
%14 = call i32 @printf(i8* getelementptr inbounds ([53 x i8], [53 x i8]* @.str, i64 0, i64 0), i32 %11, i32 %12, i32 %13)
ret void
}

LLVM IR (-O2):
%struct.usbcan_msg = type { i32 }
@.str = [53 x i8] c"Received unexpected callback with %u messages %u/%u\0A\00"
define void @usbcandump_null_callback(i32 %0, i32 %1, %struct.usbcan_msg* nocapture readnone %2, i32 %3, i8* nocapture readnone %4) {
%6 = tail call i32 @printf(i8* getelementptr inbounds ([53 x i8], [53 x i8]* @.str, i64 0, i64 0), i32 %3, i32 %0, i32 %1)
ret void
}
int ft_is_wht_spc(const char c) {
  if (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v')
    return (1);
  return (0);
}


x86 assembly (clang, -O0):
<ft_is_wht_spc>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x5(%rbp)
movsbl -0x5(%rbp),%eax
cmp    $0x20,%eax
je     1158 <ft_is_wht_spc+0x58>
movsbl -0x5(%rbp),%eax
cmp    $0xc,%eax
je     1158 <ft_is_wht_spc+0x58>
movsbl -0x5(%rbp),%eax
cmp    $0xa,%eax
je     1158 <ft_is_wht_spc+0x58>
movsbl -0x5(%rbp),%eax
cmp    $0xd,%eax
je     1158 <ft_is_wht_spc+0x58>
movsbl -0x5(%rbp),%eax
cmp    $0x9,%eax
je     1158 <ft_is_wht_spc+0x58>
movsbl -0x5(%rbp),%eax
cmp    $0xb,%eax
jne    1164 <ft_is_wht_spc+0x64>
movl   $0x1,-0x4(%rbp)
jmp    116b <ft_is_wht_spc+0x6b>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ft_is_wht_spc>:
mov    $0x1,%eax
lea    -0x9(%rdi),%ecx
cmp    $0x5,%cl
jae    110e <ft_is_wht_spc+0xe>
ret
cmp    $0x20,%dil
je     110d <ft_is_wht_spc+0xd>
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @ft_is_wht_spc(i8 signext %0) {
%2 = alloca i32
%3 = alloca i8
store i8 %0, i8* %3
%4 = load i8, i8* %3
%5 = sext i8 %4 to i32
%6 = icmp eq i32 %5, 32
br i1 %6, label %27, label %7
7: ; preds = %1
%8 = load i8, i8* %3
%9 = sext i8 %8 to i32
%10 = icmp eq i32 %9, 12
br i1 %10, label %27, label %11
11: ; preds = %7
%12 = load i8, i8* %3
%13 = sext i8 %12 to i32
%14 = icmp eq i32 %13, 10
br i1 %14, label %27, label %15
15: ; preds = %11
%16 = load i8, i8* %3
%17 = sext i8 %16 to i32
%18 = icmp eq i32 %17, 13
br i1 %18, label %27, label %19
19: ; preds = %15
%20 = load i8, i8* %3
%21 = sext i8 %20 to i32
%22 = icmp eq i32 %21, 9
br i1 %22, label %27, label %23
23: ; preds = %19
%24 = load i8, i8* %3
%25 = sext i8 %24 to i32
%26 = icmp eq i32 %25, 11
br i1 %26, label %27, label %28
27: ; preds = %23, %19, %15, %11, %7, %1
store i32 1, i32* %2
br label %29
28: ; preds = %23
store i32 0, i32* %2
br label %29
29: ; preds = %28, %27
%30 = load i32, i32* %2
ret i32 %30
}

LLVM IR (-O2):
define i32 @ft_is_wht_spc(i8 signext %0) {
switch i8 %0, label %2 [
i8 32, label %3
i8 13, label %3
i8 12, label %3
i8 11, label %3
i8 10, label %3
i8 9, label %3
]
2: ; preds = %1
br label %3
3: ; preds = %1, %1, %1, %1, %1, %1, %2
%4 = phi i32 [ 0, %2 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ]
ret i32 %4
}
const struct typ *typ_generic_functor_const(const struct typ *t) {
  return typ_generic_functor(__builtin_choose_expr(
      __builtin_types_compatible_p(__typeof__(t), const struct node *),
      (struct node *)(t),
      __builtin_choose_expr(
          __builtin_types_compatible_p(__typeof__(t), const struct module *),
          (struct module *)(t),
          __builtin_choose_expr(
              __builtin_types_compatible_p(__typeof__(t), const struct typ *),
              (struct typ *)(t),
              __builtin_choose_expr(
                  __builtin_types_compatible_p(__typeof__(t),
                                               const struct toplevel *),
                  (struct toplevel *)(t),
                  __builtin_choose_expr(
                      __builtin_types_compatible_p(__typeof__(t),
                                                   const struct scope *),
                      (struct scope *)(t),
                      __builtin_choose_expr(
                          __builtin_types_compatible_p(__typeof__(t),
                                                       const struct typset *),
                          (struct typset *)(t),
                          __builtin_choose_expr(
                              __builtin_types_compatible_p(
                                  __typeof__(t), const struct constraint *),
                              (struct constraint *)(t),
                              __builtin_choose_expr(
                                  __builtin_types_compatible_p(
                                      __typeof__(t),
                                      const struct vecancestor *),
                                  (struct vecancestor *)(t), (t))))))))));
}


x86 assembly (clang, -O0):
<typ_generic_functor_const>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
mov    $0x0,%al
call   1030 <typ_generic_functor@plt>
cltq
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<typ_generic_functor_const>:
push   %rax
xor    %eax,%eax
call   1030 <typ_generic_functor@plt>
cltq
pop    %rcx
ret

LLVM IR (-O0):
%struct.typ = type opaque
define %struct.typ* @typ_generic_functor_const(%struct.typ* %0) {
%2 = alloca %struct.typ*
store %struct.typ* %0, %struct.typ** %2
%3 = load %struct.typ*, %struct.typ** %2
%4 = call i32 (%struct.typ*, ...) bitcast (i32 (...)* @typ_generic_functor to i32 (%struct.typ*, ...)*)(%struct.typ* %3)
%5 = sext i32 %4 to i64
%6 = inttoptr i64 %5 to %struct.typ*
ret %struct.typ* %6
}

LLVM IR (-O2):
%struct.typ = type opaque
define %struct.typ* @typ_generic_functor_const(%struct.typ* %0) {
%2 = tail call i32 (%struct.typ*, ...) bitcast (i32 (...)* @typ_generic_functor to i32 (%struct.typ*, ...)*)(%struct.typ* %0)
%3 = sext i32 %2 to i64
%4 = inttoptr i64 %3 to %struct.typ*
ret %struct.typ* %4
}
int test_imm_1Fuint32_reg(unsigned int val) {
  return ((val) & (0x1F << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_1Fuint32_reg>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edx
and    $0x1f,%edx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%edx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_1Fuint32_reg>:
test   $0x1f,%dil
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_1Fuint32_reg(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = and i32 %3, 31
%5 = icmp ne i32 %4, 0
%6 = zext i1 %5 to i64
%7 = select i1 %5, i32 -20, i32 -40
ret i32 %7
}

LLVM IR (-O2):
define i32 @test_imm_1Fuint32_reg(i32 %0) {
%2 = and i32 %0, 31
%3 = icmp eq i32 %2, 0
%4 = select i1 %3, i32 -40, i32 -20
ret i32 %4
}
void test97_Test_bar__E() {}


x86 assembly (clang, -O0):
<test97_Test_bar__E>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<test97_Test_bar__E>:
ret

LLVM IR (-O0):
define void @test97_Test_bar__E() {
ret void
}

LLVM IR (-O2):
define void @test97_Test_bar__E() {
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ regex_t;

/* Variables and functions */
int /*<<< orphan*/ free(void *);
int /*<<< orphan*/ regfree(int /*<<< orphan*/ *);
void c_regfree(void *preg) {
  if (preg != NULL) {
    regfree((regex_t *)preg);
    free(preg);
  }
}


x86 assembly (clang, -O0):
<c_regfree>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
cmpq   $0x0,-0x8(%rbp)
je     1149 <c_regfree+0x29>
mov    -0x8(%rbp),%rdi
call   1040 <regfree@plt>
mov    -0x8(%rbp),%rdi
call   1030 <free@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<c_regfree>:
test   %rdi,%rdi
je     1137 <c_regfree+0x17>
push   %rbx
mov    %rdi,%rbx
call   1040 <regfree@plt>
mov    %rbx,%rdi
pop    %rbx
jmp    1030 <free@plt>
ret

LLVM IR (-O0):
define void @c_regfree(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = icmp ne i8* %3, null
br i1 %4, label %5, label %11
5: ; preds = %1
%6 = load i8*, i8** %2
%7 = bitcast i8* %6 to i32*
%8 = call i32 @regfree(i32* %7)
%9 = load i8*, i8** %2
%10 = call i32 @free(i8* %9)
br label %11
11: ; preds = %5, %1
ret void
}

LLVM IR (-O2):
define void @c_regfree(i8* %0) {
%2 = icmp eq i8* %0, null
br i1 %2, label %7, label %3
3: ; preds = %1
%4 = bitcast i8* %0 to i32*
%5 = tail call i32 @regfree(i32* %4)
%6 = tail call i32 @free(i8* %0)
br label %7
7: ; preds = %3, %1
ret void
}
mysmpte(hr, mn, se, fr, ff) int hr, mn, se, fr, ff;
{
  prtime();
  printf("SMPTE %d %d %d %d %d\n", hr, mn, se, fr, ff);
}


x86 assembly (clang, -O0):
<mysmpte>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %edx,-0x10(%rbp)
mov    %ecx,-0x14(%rbp)
mov    %r8d,-0x18(%rbp)
mov    $0x0,%al
call   1040 <prtime@plt>
mov    -0x8(%rbp),%esi
mov    -0xc(%rbp),%edx
mov    -0x10(%rbp),%ecx
mov    -0x14(%rbp),%r8d
mov    -0x18(%rbp),%r9d
lea    0xea9(%rip),%rdi
mov    $0x0,%al
call   1030 <printf@plt>
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<mysmpte>:
push   %rbp
push   %r15
push   %r14
push   %r12
push   %rbx
mov    %r8d,%r14d
mov    %ecx,%r15d
mov    %edx,%r12d
mov    %esi,%ebp
mov    %edi,%ebx
xor    %eax,%eax
call   1040 <prtime@plt>
lea    0xebd(%rip),%rdi
mov    %ebx,%esi
mov    %ebp,%edx
mov    %r12d,%ecx
mov    %r15d,%r8d
mov    %r14d,%r9d
xor    %eax,%eax
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
pop    %rbp
jmp    1030 <printf@plt>

LLVM IR (-O0):
@.str = [22 x i8] c"SMPTE %d %d %d %d %d\0A\00"
define i32 @mysmpte(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) {
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
%9 = alloca i32
%10 = alloca i32
%11 = alloca i32
store i32 %0, i32* %7
store i32 %1, i32* %8
store i32 %2, i32* %9
store i32 %3, i32* %10
store i32 %4, i32* %11
%12 = call i32 (...) @prtime()
%13 = load i32, i32* %7
%14 = load i32, i32* %8
%15 = load i32, i32* %9
%16 = load i32, i32* %10
%17 = load i32, i32* %11
%18 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i64 0, i64 0), i32 %13, i32 %14, i32 %15, i32 %16, i32 %17)
%19 = load i32, i32* %6
ret i32 %19
}

LLVM IR (-O2):
@.str = [22 x i8] c"SMPTE %d %d %d %d %d\0A\00"
define i32 @mysmpte(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) {
%6 = tail call i32 (...) @prtime()
%7 = tail call i32 (i8*, ...) @printf(i8* dereferenceable(1) getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i64 0, i64 0), i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
ret i32 undef
}
/* Type definitions */
struct usernewkey_cmdline_parser_params {
  int dummy;
};
struct usernewkey_args_info {
  int dummy;
};

/* Variables and functions */
int usernewkey_cmdline_parser_internal(
    int, char **, struct usernewkey_args_info *,
    struct usernewkey_cmdline_parser_params *, int /*<<< orphan*/);
int usernewkey_cmdline_parser_ext(
    int argc, char **argv, struct usernewkey_args_info *args_info,
    struct usernewkey_cmdline_parser_params *params) {
  int result;
  result = usernewkey_cmdline_parser_internal(argc, argv, args_info, params, 0);
  return result;
}


x86 assembly (clang, -O0):
<usernewkey_cmdline_parser_ext>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    -0x4(%rbp),%edi
mov    -0x10(%rbp),%rsi
mov    -0x18(%rbp),%rdx
mov    -0x20(%rbp),%rcx
xor    %r8d,%r8d
call   1030 <usernewkey_cmdline_parser_internal@plt>
mov    %eax,-0x24(%rbp)
mov    -0x24(%rbp),%eax
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<usernewkey_cmdline_parser_ext>:
xor    %r8d,%r8d
jmp    1030 <usernewkey_cmdline_parser_internal@plt>

LLVM IR (-O0):
%struct.usernewkey_args_info = type { i32 }
%struct.usernewkey_cmdline_parser_params = type { i32 }
define i32 @usernewkey_cmdline_parser_ext(i32 %0, i8** %1, %struct.usernewkey_args_info* %2, %struct.usernewkey_cmdline_parser_params* %3) {
%5 = alloca i32
%6 = alloca i8**
%7 = alloca %struct.usernewkey_args_info*
%8 = alloca %struct.usernewkey_cmdline_parser_params*
%9 = alloca i32
store i32 %0, i32* %5
store i8** %1, i8*** %6
store %struct.usernewkey_args_info* %2, %struct.usernewkey_args_info** %7
store %struct.usernewkey_cmdline_parser_params* %3, %struct.usernewkey_cmdline_parser_params** %8
%10 = load i32, i32* %5
%11 = load i8**, i8*** %6
%12 = load %struct.usernewkey_args_info*, %struct.usernewkey_args_info** %7
%13 = load %struct.usernewkey_cmdline_parser_params*, %struct.usernewkey_cmdline_parser_params** %8
%14 = call i32 @usernewkey_cmdline_parser_internal(i32 %10, i8** %11, %struct.usernewkey_args_info* %12, %struct.usernewkey_cmdline_parser_params* %13, i32 0)
store i32 %14, i32* %9
%15 = load i32, i32* %9
ret i32 %15
}

LLVM IR (-O2):
%struct.usernewkey_args_info = type { i32 }
%struct.usernewkey_cmdline_parser_params = type { i32 }
define i32 @usernewkey_cmdline_parser_ext(i32 %0, i8** %1, %struct.usernewkey_args_info* %2, %struct.usernewkey_cmdline_parser_params* %3) {
%5 = tail call i32 @usernewkey_cmdline_parser_internal(i32 %0, i8** %1, %struct.usernewkey_args_info* %2, %struct.usernewkey_cmdline_parser_params* %3, i32 0)
ret i32 %5
}
/* Variables and functions */
void membar_producer(void) {}


x86 assembly (clang, -O0):
<membar_producer>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<membar_producer>:
ret

LLVM IR (-O0):
define void @membar_producer() {
ret void
}

LLVM IR (-O2):
define void @membar_producer() {
ret void
}
int nr_lines_in_text(cp)
register char *cp;
{
  register int n = 0;
  while (*cp) {
    if (*cp == '\n')
      ++n;
    ++cp;
  }
  return n;
}


x86 assembly (clang, -O0):
<nr_lines_in_text>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
mov    -0x8(%rbp),%rax
cmpb   $0x0,(%rax)
je     1146 <nr_lines_in_text+0x46>
mov    -0x8(%rbp),%rax
movsbl (%rax),%eax
cmp    $0xa,%eax
jne    1135 <nr_lines_in_text+0x35>
mov    -0xc(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    110f <nr_lines_in_text+0xf>
mov    -0xc(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<nr_lines_in_text>:
xor    %eax,%eax
jmp    1117 <nr_lines_in_text+0x17>
cs nopw 0x0(%rax,%rax,1)
xchg   %ax,%ax
add    $0x1,%eax
add    $0x1,%rdi
movzbl (%rdi),%ecx
cmp    $0xa,%cl
je     1110 <nr_lines_in_text+0x10>
test   %cl,%cl
jne    1113 <nr_lines_in_text+0x13>
ret

LLVM IR (-O0):
define i32 @nr_lines_in_text(i8* %0) {
%2 = alloca i8*
%3 = alloca i32
store i8* %0, i8** %2
store i32 0, i32* %3
br label %4
4: ; preds = %16, %1
%5 = load i8*, i8** %2
%6 = load i8, i8* %5
%7 = icmp ne i8 %6, 0
br i1 %7, label %8, label %19
8: ; preds = %4
%9 = load i8*, i8** %2
%10 = load i8, i8* %9
%11 = sext i8 %10 to i32
%12 = icmp eq i32 %11, 10
br i1 %12, label %13, label %16
13: ; preds = %8
%14 = load i32, i32* %3
%15 = add nsw i32 %14, 1
store i32 %15, i32* %3
br label %16
16: ; preds = %13, %8
%17 = load i8*, i8** %2
%18 = getelementptr inbounds i8, i8* %17, i32 1
store i8* %18, i8** %2
br label %4
19: ; preds = %4
%20 = load i32, i32* %3
ret i32 %20
}

LLVM IR (-O2):
define i32 @nr_lines_in_text(i8* nocapture %0) {
br label %2
2: ; preds = %8, %1
%3 = phi i8* [ %0, %1 ], [ %10, %8 ]
%4 = phi i32 [ 0, %1 ], [ %9, %8 ]
%5 = load i8, i8* %3
switch i8 %5, label %8 [
i8 0, label %11
i8 10, label %6
]
6: ; preds = %2
%7 = add nsw i32 %4, 1
br label %8
8: ; preds = %2, %6
%9 = phi i32 [ %7, %6 ], [ %4, %2 ]
%10 = getelementptr inbounds i8, i8* %3, i64 1
br label %2
11: ; preds = %2
ret i32 %4
}
/* Variables and functions */
int putchar(char);
int puts(char *s) {
  int c;
  while ((c = *s++) != '\0')
    putchar(c);
  return putchar('\n');
}


x86 assembly (clang, -O0):
<puts>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,%rcx
add    $0x1,%rcx
mov    %rcx,-0x8(%rbp)
movsbl (%rax),%eax
mov    %eax,-0xc(%rbp)
cmp    $0x0,%eax
je     114a <puts+0x3a>
mov    -0xc(%rbp),%eax
movsbl %al,%edi
call   1030 <putchar@plt>
jmp    111c <puts+0xc>
mov    $0xa,%edi
call   1030 <putchar@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<puts>:
push   %rbx
mov    (%rdi),%al
test   %al,%al
je     1133 <puts+0x23>
mov    %rdi,%rbx
add    $0x1,%rbx
xchg   %ax,%ax
movsbl %al,%edi
call   1030 <putchar@plt>
movzbl (%rbx),%eax
add    $0x1,%rbx
test   %al,%al
jne    1120 <puts+0x10>
mov    $0xa,%edi
pop    %rbx
jmp    1030 <putchar@plt>

LLVM IR (-O0):
define i32 @puts(i8* %0) {
%2 = alloca i8*
%3 = alloca i32
store i8* %0, i8** %2
br label %4
4: ; preds = %10, %1
%5 = load i8*, i8** %2
%6 = getelementptr inbounds i8, i8* %5, i32 1
store i8* %6, i8** %2
%7 = load i8, i8* %5
%8 = sext i8 %7 to i32
store i32 %8, i32* %3
%9 = icmp ne i32 %8, 0
br i1 %9, label %10, label %14
10: ; preds = %4
%11 = load i32, i32* %3
%12 = trunc i32 %11 to i8
%13 = call i32 @putchar(i8 signext %12)
br label %4
14: ; preds = %4
%15 = call i32 @putchar(i8 signext 10)
ret i32 %15
}

LLVM IR (-O2):
define i32 @puts(i8* nocapture %0) {
%2 = load i8, i8* %0
%3 = icmp eq i8 %2, 0
br i1 %3, label %11, label %4
4: ; preds = %1, %4
%5 = phi i8 [ %9, %4 ], [ %2, %1 ]
%6 = phi i8* [ %7, %4 ], [ %0, %1 ]
%7 = getelementptr inbounds i8, i8* %6, i64 1
%8 = tail call i32 @putchar(i8 signext %5)
%9 = load i8, i8* %7
%10 = icmp eq i8 %9, 0
br i1 %10, label %11, label %4
11: ; preds = %4, %1
%12 = tail call i32 @putchar(i8 signext 10)
ret i32 %12
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *);
void printSomething() {
  printf("URL:");
http:
  return;
}


x86 assembly (clang, -O0):
<printSomething>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <printf@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<printSomething>:
lea    0xee9(%rip),%rdi
jmp    1030 <printf@plt>

LLVM IR (-O0):
@.str = [5 x i8] c"URL:\00"
define void @printSomething() {
%1 = call i32 @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0))
br label %2
2: ; preds = %0
ret void
}

LLVM IR (-O2):
@.str = [5 x i8] c"URL:\00"
define void @printSomething() {
%1 = tail call i32 @printf(i8* dereferenceable(1) getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0))
ret void
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *, int);
int /*<<< orphan*/ scanf(char *, int *, int *);
int main(int argc, char *argv[]) {
  int i, j;
  scanf("%i %i", &i, &j);
  printf("%i", i + j);
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
movl   $0x0,-0x4(%rbp)
mov    %edi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
lea    0xec3(%rip),%rdi
lea    -0x14(%rbp),%rsi
lea    -0x18(%rbp),%rdx
call   1040 <scanf@plt>
mov    -0x14(%rbp),%esi
add    -0x18(%rbp),%esi
lea    0xeac(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rax
lea    0xed8(%rip),%rdi
lea    0x4(%rsp),%rsi
mov    %rsp,%rdx
call   1040 <scanf@plt>
mov    (%rsp),%esi
add    0x4(%rsp),%esi
lea    0xec0(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [6 x i8] c"%i %i\00"
@.str.1 = [3 x i8] c"%i\00"
define i32 @main(i32 %0, i8** %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i8**
%6 = alloca i32
%7 = alloca i32
store i32 0, i32* %3
store i32 %0, i32* %4
store i8** %1, i8*** %5
%8 = call i32 @scanf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i32* %6, i32* %7)
%9 = load i32, i32* %6
%10 = load i32, i32* %7
%11 = add nsw i32 %9, %10
%12 = call i32 @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.1, i64 0, i64 0), i32 %11)
ret i32 0
}

LLVM IR (-O2):
@.str = [6 x i8] c"%i %i\00"
@.str.1 = [3 x i8] c"%i\00"
define i32 @main(i32 %0, i8** nocapture readnone %1) {
%3 = alloca i32
%4 = alloca i32
%5 = bitcast i32* %3 to i8*
%6 = bitcast i32* %4 to i8*
%7 = call i32 @scanf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0), i32* %3, i32* %4)
%8 = load i32, i32* %3
%9 = load i32, i32* %4
%10 = add nsw i32 %9, %8
%11 = call i32 @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.1, i64 0, i64 0), i32 %10)
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ VIM_SIF_I2cReadByte(int /*<<< orphan*/, unsigned char *);
unsigned char CheckId_HV7131GP(void) {
  unsigned char temp;
  VIM_SIF_I2cReadByte(0, &temp);
  if (temp == 0x40)
    return 1;
  else
    return 0;
}


x86 assembly (clang, -O0):
<CheckId_HV7131GP>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
xor    %edi,%edi
lea    -0x2(%rbp),%rsi
call   1030 <VIM_SIF_I2cReadByte@plt>
movzbl -0x2(%rbp),%eax
cmp    $0x40,%eax
jne    1139 <CheckId_HV7131GP+0x29>
movb   $0x1,-0x1(%rbp)
jmp    113d <CheckId_HV7131GP+0x2d>
movb   $0x0,-0x1(%rbp)
movzbl -0x1(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<CheckId_HV7131GP>:
push   %rax
lea    0x7(%rsp),%rsi
xor    %edi,%edi
call   1030 <VIM_SIF_I2cReadByte@plt>
cmpb   $0x40,0x7(%rsp)
sete   %al
pop    %rcx
ret

LLVM IR (-O0):
define zeroext i8 @CheckId_HV7131GP() {
%1 = alloca i8
%2 = alloca i8
%3 = call i32 @VIM_SIF_I2cReadByte(i32 0, i8* %2)
%4 = load i8, i8* %2
%5 = zext i8 %4 to i32
%6 = icmp eq i32 %5, 64
br i1 %6, label %7, label %8
7: ; preds = %0
store i8 1, i8* %1
br label %9
8: ; preds = %0
store i8 0, i8* %1
br label %9
9: ; preds = %8, %7
%10 = load i8, i8* %1
ret i8 %10
}

LLVM IR (-O2):
define zeroext i8 @CheckId_HV7131GP() {
%1 = alloca i8
%2 = call i32 @VIM_SIF_I2cReadByte(i32 0, i8* %1)
%3 = load i8, i8* %1
%4 = icmp eq i8 %3, 64
%5 = zext i1 %4 to i8
ret i8 %5
}
/* Type definitions */
struct RNAeval_args_info {
  int dummy;
};

/* Variables and functions */
int RNAeval_cmdline_parser2(int, char **, struct RNAeval_args_info *,
                            int /*<<< orphan*/, int, int);
int RNAeval_cmdline_parser(int argc, char **argv,
                           struct RNAeval_args_info *args_info) {
  return RNAeval_cmdline_parser2(argc, argv, args_info, 0, 1, 1);
}


x86 assembly (clang, -O0):
<RNAeval_cmdline_parser>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    -0x4(%rbp),%edi
mov    -0x10(%rbp),%rsi
mov    -0x18(%rbp),%rdx
xor    %ecx,%ecx
mov    $0x1,%r9d
mov    %r9d,%r8d
call   1030 <RNAeval_cmdline_parser2@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<RNAeval_cmdline_parser>:
xor    %ecx,%ecx
mov    $0x1,%r8d
mov    $0x1,%r9d
jmp    1030 <RNAeval_cmdline_parser2@plt>

LLVM IR (-O0):
%struct.RNAeval_args_info = type { i32 }
define i32 @RNAeval_cmdline_parser(i32 %0, i8** %1, %struct.RNAeval_args_info* %2) {
%4 = alloca i32
%5 = alloca i8**
%6 = alloca %struct.RNAeval_args_info*
store i32 %0, i32* %4
store i8** %1, i8*** %5
store %struct.RNAeval_args_info* %2, %struct.RNAeval_args_info** %6
%7 = load i32, i32* %4
%8 = load i8**, i8*** %5
%9 = load %struct.RNAeval_args_info*, %struct.RNAeval_args_info** %6
%10 = call i32 @RNAeval_cmdline_parser2(i32 %7, i8** %8, %struct.RNAeval_args_info* %9, i32 0, i32 1, i32 1)
ret i32 %10
}

LLVM IR (-O2):
%struct.RNAeval_args_info = type { i32 }
define i32 @RNAeval_cmdline_parser(i32 %0, i8** %1, %struct.RNAeval_args_info* %2) {
%4 = tail call i32 @RNAeval_cmdline_parser2(i32 %0, i8** %1, %struct.RNAeval_args_info* %2, i32 0, i32 1, i32 1)
ret i32 %4
}
/* Type definitions */
typedef int /*<<< orphan*/ time_t;
struct tm {
  int dummy;
};

/* Variables and functions */
struct tm *gmtime_r(int /*<<< orphan*/ const *, struct tm *);
struct tm *Parrot_gmtime_r(const time_t *t, struct tm *tm) {
  return gmtime_r(t, tm);
}


x86 assembly (clang, -O0):
<Parrot_gmtime_r>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
call   1030 <gmtime_r@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<Parrot_gmtime_r>:
jmp    1030 <gmtime_r@plt>

LLVM IR (-O0):
%struct.tm = type { i32 }
define %struct.tm* @Parrot_gmtime_r(i32* %0, %struct.tm* %1) {
%3 = alloca i32*
%4 = alloca %struct.tm*
store i32* %0, i32** %3
store %struct.tm* %1, %struct.tm** %4
%5 = load i32*, i32** %3
%6 = load %struct.tm*, %struct.tm** %4
%7 = call %struct.tm* @gmtime_r(i32* %5, %struct.tm* %6)
ret %struct.tm* %7
}

LLVM IR (-O2):
%struct.tm = type { i32 }
define %struct.tm* @Parrot_gmtime_r(i32* %0, %struct.tm* %1) {
%3 = tail call %struct.tm* @gmtime_r(i32* %0, %struct.tm* %1)
ret %struct.tm* %3
}
/* Variables and functions */
int /*<<< orphan*/ free(void *);
void *malloc(int);
void malloc_stub(void) {
  void *p = malloc(1);
  free(p);
}


x86 assembly (clang, -O0):
<malloc_stub>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    $0x1,%edi
call   1040 <malloc@plt>
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <free@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<malloc_stub>:
push   %rax
mov    $0x1,%edi
call   1040 <malloc@plt>
mov    %rax,%rdi
pop    %rax
jmp    1030 <free@plt>

LLVM IR (-O0):
define void @malloc_stub() {
%1 = alloca i8*
%2 = call i8* @malloc(i32 1)
store i8* %2, i8** %1
%3 = load i8*, i8** %1
%4 = call i32 @free(i8* %3)
ret void
}

LLVM IR (-O2):
define void @malloc_stub() {
%1 = tail call dereferenceable_or_null(1) i8* @malloc(i32 1)
%2 = tail call i32 @free(i8* %1)
ret void
}
float phi3(float mu, float psi) { return (1.0 - mu) * psi; }


x86 assembly (clang, -O0):
<phi3>:
push   %rbp
mov    %rsp,%rbp
movss  %xmm0,-0x4(%rbp)
movss  %xmm1,-0x8(%rbp)
movss  -0x4(%rbp),%xmm0
cvtss2sd %xmm0,%xmm1
movsd  0xee1(%rip),%xmm0
subsd  %xmm1,%xmm0
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
mulsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<phi3>:
cvtss2sd %xmm0,%xmm0
movsd  0xef4(%rip),%xmm2
subsd  %xmm0,%xmm2
xorps  %xmm0,%xmm0
cvtss2sd %xmm1,%xmm0
mulsd  %xmm2,%xmm0
cvtsd2ss %xmm0,%xmm0
ret

LLVM IR (-O0):
define float @phi3(float %0, float %1) {
%3 = alloca float
%4 = alloca float
store float %0, float* %3
store float %1, float* %4
%5 = load float, float* %3
%6 = fpext float %5 to double
%7 = fsub double 1.000000e+00, %6
%8 = load float, float* %4
%9 = fpext float %8 to double
%10 = fmul double %7, %9
%11 = fptrunc double %10 to float
ret float %11
}

LLVM IR (-O2):
define float @phi3(float %0, float %1) {
%3 = fpext float %0 to double
%4 = fsub double 1.000000e+00, %3
%5 = fpext float %1 to double
%6 = fmul double %4, %5
%7 = fptrunc double %6 to float
ret float %7
}
int syncint_decode(int value) {
  unsigned int a, b, c, d, result = 0x0;
  a = value & 0xFF;
  b = (value >> 8) & 0xFF;
  c = (value >> 16) & 0xFF;
  d = (value >> 24) & 0xFF;
  result = result | a;
  result = result | (b << 7);
  result = result | (c << 14);
  result = result | (d << 21);
  return result;
}


x86 assembly (clang, -O0):
<syncint_decode>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
movl   $0x0,-0x18(%rbp)
mov    -0x4(%rbp),%eax
and    $0xff,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%eax
sar    $0x8,%eax
and    $0xff,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
sar    $0x10,%eax
and    $0xff,%eax
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
sar    $0x18,%eax
and    $0xff,%eax
mov    %eax,-0x14(%rbp)
mov    -0x18(%rbp),%eax
or     -0x8(%rbp),%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
mov    -0xc(%rbp),%ecx
shl    $0x7,%ecx
or     %ecx,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
mov    -0x10(%rbp),%ecx
shl    $0xe,%ecx
or     %ecx,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
mov    -0x14(%rbp),%ecx
shl    $0x15,%ecx
or     %ecx,%eax
mov    %eax,-0x18(%rbp)
mov    -0x18(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<syncint_decode>:
movzbl %dil,%eax
mov    %edi,%ecx
shr    %ecx
and    $0x7f80,%ecx
or     %eax,%ecx
mov    %edi,%eax
shr    $0x2,%eax
and    $0x3fc000,%eax
shr    $0x3,%edi
and    $0x1fe00000,%edi
or     %edi,%eax
or     %ecx,%eax
ret

LLVM IR (-O0):
define i32 @syncint_decode(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i32 %0, i32* %2
store i32 0, i32* %7
%8 = load i32, i32* %2
%9 = and i32 %8, 255
store i32 %9, i32* %3
%10 = load i32, i32* %2
%11 = ashr i32 %10, 8
%12 = and i32 %11, 255
store i32 %12, i32* %4
%13 = load i32, i32* %2
%14 = ashr i32 %13, 16
%15 = and i32 %14, 255
store i32 %15, i32* %5
%16 = load i32, i32* %2
%17 = ashr i32 %16, 24
%18 = and i32 %17, 255
store i32 %18, i32* %6
%19 = load i32, i32* %7
%20 = load i32, i32* %3
%21 = or i32 %19, %20
store i32 %21, i32* %7
%22 = load i32, i32* %7
%23 = load i32, i32* %4
%24 = shl i32 %23, 7
%25 = or i32 %22, %24
store i32 %25, i32* %7
%26 = load i32, i32* %7
%27 = load i32, i32* %5
%28 = shl i32 %27, 14
%29 = or i32 %26, %28
store i32 %29, i32* %7
%30 = load i32, i32* %7
%31 = load i32, i32* %6
%32 = shl i32 %31, 21
%33 = or i32 %30, %32
store i32 %33, i32* %7
%34 = load i32, i32* %7
ret i32 %34
}

LLVM IR (-O2):
define i32 @syncint_decode(i32 %0) {
%2 = and i32 %0, 255
%3 = lshr i32 %0, 1
%4 = and i32 %3, 32640
%5 = or i32 %4, %2
%6 = lshr i32 %0, 2
%7 = and i32 %6, 4177920
%8 = or i32 %5, %7
%9 = lshr i32 %0, 3
%10 = and i32 %9, 534773760
%11 = or i32 %8, %10
ret i32 %11
}
double f(double x) {
  double y;
  y = (x - 1) * (x - 1) * (x - 1);
  return y;
}


x86 assembly (clang, -O0):
<f>:
push   %rbp
mov    %rsp,%rbp
movsd  %xmm0,-0x8(%rbp)
movsd  -0x8(%rbp),%xmm0
movsd  0xeea(%rip),%xmm1
subsd  %xmm1,%xmm0
movsd  -0x8(%rbp),%xmm1
movsd  0xed9(%rip),%xmm2
subsd  %xmm2,%xmm1
mulsd  %xmm1,%xmm0
movsd  -0x8(%rbp),%xmm1
movsd  0xec4(%rip),%xmm2
subsd  %xmm2,%xmm1
mulsd  %xmm1,%xmm0
movsd  %xmm0,-0x10(%rbp)
movsd  -0x10(%rbp),%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<f>:
addsd  0xef8(%rip),%xmm0
movapd %xmm0,%xmm1
mulsd  %xmm0,%xmm1
mulsd  %xmm1,%xmm0
ret

LLVM IR (-O0):
define double @f(double %0) {
%2 = alloca double
%3 = alloca double
store double %0, double* %2
%4 = load double, double* %2
%5 = fsub double %4, 1.000000e+00
%6 = load double, double* %2
%7 = fsub double %6, 1.000000e+00
%8 = fmul double %5, %7
%9 = load double, double* %2
%10 = fsub double %9, 1.000000e+00
%11 = fmul double %8, %10
store double %11, double* %3
%12 = load double, double* %3
ret double %12
}

LLVM IR (-O2):
define double @f(double %0) {
%2 = fadd double %0, -1.000000e+00
%3 = fmul double %2, %2
%4 = fmul double %2, %3
ret double %4
}
/* Variables and functions */
int _ada_use_c2phc(int, int *, int *, double *);
int solcon_clear_standard_solutions(void) {
  int *a, *b, fail;
  double *c;
  fail = _ada_use_c2phc(37, a, b, c);
  return fail;
}


x86 assembly (clang, -O0):
<solcon_clear_standard_solutions>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    -0x8(%rbp),%rsi
mov    -0x10(%rbp),%rdx
mov    -0x20(%rbp),%rcx
mov    $0x25,%edi
call   1030 <_ada_use_c2phc@plt>
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<solcon_clear_standard_solutions>:
mov    $0x25,%edi
jmp    1030 <_ada_use_c2phc@plt>

LLVM IR (-O0):
define i32 @solcon_clear_standard_solutions() {
%1 = alloca i32*
%2 = alloca i32*
%3 = alloca i32
%4 = alloca double*
%5 = load i32*, i32** %1
%6 = load i32*, i32** %2
%7 = load double*, double** %4
%8 = call i32 @_ada_use_c2phc(i32 37, i32* %5, i32* %6, double* %7)
store i32 %8, i32* %3
%9 = load i32, i32* %3
ret i32 %9
}

LLVM IR (-O2):
define i32 @solcon_clear_standard_solutions() {
%1 = tail call i32 @_ada_use_c2phc(i32 37, i32* undef, i32* undef, double* undef)
ret i32 %1
}
/* Variables and functions */
int printf(char *, int, int);
extern int printRange(int min, int max) {
  int ret =
      printf("Scheduling policy valid priority ranges: %d-%d\n", min, max);
  return ret;
}


x86 assembly (clang, -O0):
<printRange>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x4(%rbp),%esi
mov    -0x8(%rbp),%edx
lea    0xed5(%rip),%rdi
call   1030 <printf@plt>
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<printRange>:
mov    %esi,%edx
mov    %edi,%esi
lea    0xee5(%rip),%rdi
jmp    1030 <printf@plt>

LLVM IR (-O0):
@.str = [48 x i8] c"Scheduling policy valid priority ranges: %d-%d\0A\00"
define i32 @printRange(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%6 = load i32, i32* %3
%7 = load i32, i32* %4
%8 = call i32 @printf(i8* getelementptr inbounds ([48 x i8], [48 x i8]* @.str, i64 0, i64 0), i32 %6, i32 %7)
store i32 %8, i32* %5
%9 = load i32, i32* %5
ret i32 %9
}

LLVM IR (-O2):
@.str = [48 x i8] c"Scheduling policy valid priority ranges: %d-%d\0A\00"
define i32 @printRange(i32 %0, i32 %1) {
%3 = tail call i32 @printf(i8* getelementptr inbounds ([48 x i8], [48 x i8]* @.str, i64 0, i64 0), i32 %0, i32 %1)
ret i32 %3
}
/* Variables and functions */
void *__coverity_alloc__(int);
int /*<<< orphan*/ __coverity_mark_as_afm_allocated__(void *, char *);
void *H5Gcreate(void *loc_id, const char *name, void *lcpl_id, void *gcpl_id,
                void *gapl_id) {
  void *id = __coverity_alloc__(10);
  __coverity_mark_as_afm_allocated__(id, "H5Gclose");
  return id;
}


x86 assembly (clang, -O0):
<H5Gcreate>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8,-0x28(%rbp)
mov    $0xa,%edi
call   1040 <__coverity_alloc__@plt>
mov    %rax,-0x30(%rbp)
mov    -0x30(%rbp),%rdi
lea    0xeab(%rip),%rsi
call   1030 <__coverity_mark_as_afm_allocated__@plt>
mov    -0x30(%rbp),%rax
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<H5Gcreate>:
push   %rbx
mov    $0xa,%edi
call   1040 <__coverity_alloc__@plt>
mov    %rax,%rbx
lea    0xecb(%rip),%rsi
mov    %rax,%rdi
call   1030 <__coverity_mark_as_afm_allocated__@plt>
mov    %rbx,%rax
pop    %rbx
ret

LLVM IR (-O0):
@.str = [9 x i8] c"H5Gclose\00"
define i8* @H5Gcreate(i8* %0, i8* %1, i8* %2, i8* %3, i8* %4) {
%6 = alloca i8*
%7 = alloca i8*
%8 = alloca i8*
%9 = alloca i8*
%10 = alloca i8*
%11 = alloca i8*
store i8* %0, i8** %6
store i8* %1, i8** %7
store i8* %2, i8** %8
store i8* %3, i8** %9
store i8* %4, i8** %10
%12 = call i8* @__coverity_alloc__(i32 10)
store i8* %12, i8** %11
%13 = load i8*, i8** %11
%14 = call i32 @__coverity_mark_as_afm_allocated__(i8* %13, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i64 0, i64 0))
%15 = load i8*, i8** %11
ret i8* %15
}

LLVM IR (-O2):
@.str = [9 x i8] c"H5Gclose\00"
define i8* @H5Gcreate(i8* nocapture readnone %0, i8* nocapture readnone %1, i8* nocapture readnone %2, i8* nocapture readnone %3, i8* nocapture readnone %4) {
%6 = tail call i8* @__coverity_alloc__(i32 10)
%7 = tail call i32 @__coverity_mark_as_afm_allocated__(i8* %6, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i64 0, i64 0))
ret i8* %6
}
/* Variables and functions */
double RAND_MAX;
scalar_t__ rand();
double rand_range(double low, double high) {
  double range = high - low;
  double root = ((double)rand()) / RAND_MAX;
  double expanded = root * range;
  double shifted = expanded + low;
  return shifted;
}


x86 assembly (clang, -O0):
<rand_range>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
movsd  %xmm0,-0x8(%rbp)
movsd  %xmm1,-0x10(%rbp)
movsd  -0x10(%rbp),%xmm0
subsd  -0x8(%rbp),%xmm0
movsd  %xmm0,-0x18(%rbp)
mov    $0x0,%al
call   1030 <rand@plt>
cvtsi2sd %rax,%xmm0
mov    0x2ea4(%rip),%rax
divsd  (%rax),%xmm0
movsd  %xmm0,-0x20(%rbp)
movsd  -0x20(%rbp),%xmm0
mulsd  -0x18(%rbp),%xmm0
movsd  %xmm0,-0x28(%rbp)
movsd  -0x28(%rbp),%xmm0
addsd  -0x8(%rbp),%xmm0
movsd  %xmm0,-0x30(%rbp)
movsd  -0x30(%rbp),%xmm0
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<rand_range>:
sub    $0x18,%rsp
movsd  %xmm0,0x10(%rsp)
subsd  %xmm0,%xmm1
movsd  %xmm1,0x8(%rsp)
xor    %eax,%eax
call   1030 <rand@plt>
xorps  %xmm0,%xmm0
cvtsi2sd %rax,%xmm0
mov    0x2eae(%rip),%rax
divsd  (%rax),%xmm0
mulsd  0x8(%rsp),%xmm0
addsd  0x10(%rsp),%xmm0
add    $0x18,%rsp
ret

LLVM IR (-O0):
@RAND_MAX = global double 0.000000e+00
define double @rand_range(double %0, double %1) {
%3 = alloca double
%4 = alloca double
%5 = alloca double
%6 = alloca double
%7 = alloca double
%8 = alloca double
store double %0, double* %3
store double %1, double* %4
%9 = load double, double* %4
%10 = load double, double* %3
%11 = fsub double %9, %10
store double %11, double* %5
%12 = call i64 (...) @rand()
%13 = sitofp i64 %12 to double
%14 = load double, double* @RAND_MAX
%15 = fdiv double %13, %14
store double %15, double* %6
%16 = load double, double* %6
%17 = load double, double* %5
%18 = fmul double %16, %17
store double %18, double* %7
%19 = load double, double* %7
%20 = load double, double* %3
%21 = fadd double %19, %20
store double %21, double* %8
%22 = load double, double* %8
ret double %22
}

LLVM IR (-O2):
@RAND_MAX = global double 0.000000e+00
define double @rand_range(double %0, double %1) {
%3 = fsub double %1, %0
%4 = tail call i64 (...) @rand()
%5 = sitofp i64 %4 to double
%6 = load double, double* @RAND_MAX
%7 = fdiv double %5, %6
%8 = fmul double %3, %7
%9 = fadd double %8, %0
ret double %9
}
void init_p() {}


x86 assembly (clang, -O0):
<init_p>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<init_p>:
ret

LLVM IR (-O0):
define void @init_p() {
ret void
}

LLVM IR (-O2):
define void @init_p() {
ret void
}
/* Variables and functions */
scalar_t__ isdigit(char const);
int strnumcount(const char *str) {
  int count = 0;
  for (; *str; str++)
    if (isdigit(*str))
      count++;
  return count;
}


x86 assembly (clang, -O0):
<strnumcount>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
mov    -0x8(%rbp),%rax
cmpb   $0x0,(%rax)
je     1165 <strnumcount+0x55>
mov    -0x8(%rbp),%rax
movsbl (%rax),%edi
call   1030 <isdigit@plt>
cmp    $0x0,%rax
je     114f <strnumcount+0x3f>
mov    -0xc(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0xc(%rbp)
jmp    1154 <strnumcount+0x44>
mov    -0x8(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    1123 <strnumcount+0x13>
mov    -0xc(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<strnumcount>:
push   %rbp
push   %rbx
push   %rax
mov    (%rdi),%al
test   %al,%al
je     114c <strnumcount+0x3c>
mov    %rdi,%rbx
add    $0x1,%rbx
xor    %ebp,%ebp
cs nopw 0x0(%rax,%rax,1)
nopl   0x0(%rax)
movsbl %al,%edi
call   1030 <isdigit@plt>
cmp    $0x1,%rax
sbb    $0xffffffff,%ebp
movzbl (%rbx),%eax
add    $0x1,%rbx
test   %al,%al
jne    1130 <strnumcount+0x20>
jmp    114e <strnumcount+0x3e>
xor    %ebp,%ebp
mov    %ebp,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
define i32 @strnumcount(i8* %0) {
%2 = alloca i8*
%3 = alloca i32
store i8* %0, i8** %2
store i32 0, i32* %3
br label %4
4: ; preds = %17, %1
%5 = load i8*, i8** %2
%6 = load i8, i8* %5
%7 = icmp ne i8 %6, 0
br i1 %7, label %8, label %20
8: ; preds = %4
%9 = load i8*, i8** %2
%10 = load i8, i8* %9
%11 = call i64 @isdigit(i8 signext %10)
%12 = icmp ne i64 %11, 0
br i1 %12, label %13, label %16
13: ; preds = %8
%14 = load i32, i32* %3
%15 = add nsw i32 %14, 1
store i32 %15, i32* %3
br label %16
16: ; preds = %13, %8
br label %17
17: ; preds = %16
%18 = load i8*, i8** %2
%19 = getelementptr inbounds i8, i8* %18, i32 1
store i8* %19, i8** %2
br label %4
20: ; preds = %4
%21 = load i32, i32* %3
ret i32 %21
}

LLVM IR (-O2):
define i32 @strnumcount(i8* nocapture %0) {
%2 = load i8, i8* %0
%3 = icmp eq i8 %2, 0
br i1 %3, label %15, label %4
4: ; preds = %1, %4
%5 = phi i8 [ %13, %4 ], [ %2, %1 ]
%6 = phi i32 [ %11, %4 ], [ 0, %1 ]
%7 = phi i8* [ %12, %4 ], [ %0, %1 ]
%8 = tail call i64 @isdigit(i8 signext %5)
%9 = icmp ne i64 %8, 0
%10 = zext i1 %9 to i32
%11 = add nuw nsw i32 %6, %10
%12 = getelementptr inbounds i8, i8* %7, i64 1
%13 = load i8, i8* %12
%14 = icmp eq i8 %13, 0
br i1 %14, label %15, label %4
15: ; preds = %4, %1
%16 = phi i32 [ 0, %1 ], [ %11, %4 ]
ret i32 %16
}
int is_comma(char c) { return c == ','; }


x86 assembly (clang, -O0):
<is_comma>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x1(%rbp)
movsbl -0x1(%rbp),%eax
cmp    $0x2c,%eax
sete   %al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<is_comma>:
xor    %eax,%eax
cmp    $0x2c,%dil
sete   %al
ret

LLVM IR (-O0):
define i32 @is_comma(i8 signext %0) {
%2 = alloca i8
store i8 %0, i8* %2
%3 = load i8, i8* %2
%4 = sext i8 %3 to i32
%5 = icmp eq i32 %4, 44
%6 = zext i1 %5 to i32
ret i32 %6
}

LLVM IR (-O2):
define i32 @is_comma(i8 signext %0) {
%2 = icmp eq i8 %0, 44
%3 = zext i1 %2 to i32
ret i32 %3
}
/* Variables and functions */
int /*<<< orphan*/ F_GETFL;
int /*<<< orphan*/ F_SETFL;
int O_NONBLOCK;
int fcntl(int, int /*<<< orphan*/, ...);
int nsock_unblock_socket(int sd) {
  int options;
  options = O_NONBLOCK | fcntl(sd, F_GETFL);
  fcntl(sd, F_SETFL, options);
  return 1;
}


x86 assembly (clang, -O0):
<nsock_unblock_socket>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    0x2ec6(%rip),%rax
mov    (%rax),%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%edi
mov    0x2e9f(%rip),%rax
mov    (%rax),%esi
mov    $0x0,%al
call   1030 <fcntl@plt>
mov    %eax,%ecx
mov    -0xc(%rbp),%eax
or     %ecx,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%edi
mov    0x2e8a(%rip),%rax
mov    (%rax),%esi
mov    -0x8(%rbp),%edx
mov    $0x0,%al
call   1030 <fcntl@plt>
mov    $0x1,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<nsock_unblock_socket>:
push   %rbp
push   %rbx
push   %rax
mov    %edi,%ebx
mov    0x2ecc(%rip),%rax
mov    (%rax),%ebp
mov    0x2eab(%rip),%rax
mov    (%rax),%esi
xor    %eax,%eax
call   1030 <fcntl@plt>
or     %eax,%ebp
mov    0x2ea1(%rip),%rax
mov    (%rax),%esi
mov    %ebx,%edi
mov    %ebp,%edx
xor    %eax,%eax
call   1030 <fcntl@plt>
mov    $0x1,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
@O_NONBLOCK = global i32 0
@F_GETFL = global i32 0
@F_SETFL = global i32 0
define i32 @nsock_unblock_socket(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %2
%4 = load i32, i32* @O_NONBLOCK
%5 = load i32, i32* %2
%6 = load i32, i32* @F_GETFL
%7 = call i32 (i32, i32, ...) @fcntl(i32 %5, i32 %6)
%8 = or i32 %4, %7
store i32 %8, i32* %3
%9 = load i32, i32* %2
%10 = load i32, i32* @F_SETFL
%11 = load i32, i32* %3
%12 = call i32 (i32, i32, ...) @fcntl(i32 %9, i32 %10, i32 %11)
ret i32 1
}

LLVM IR (-O2):
@O_NONBLOCK = global i32 0
@F_GETFL = global i32 0
@F_SETFL = global i32 0
define i32 @nsock_unblock_socket(i32 %0) {
%2 = load i32, i32* @O_NONBLOCK
%3 = load i32, i32* @F_GETFL
%4 = tail call i32 (i32, i32, ...) @fcntl(i32 %0, i32 %3)
%5 = or i32 %4, %2
%6 = load i32, i32* @F_SETFL
%7 = tail call i32 (i32, i32, ...) @fcntl(i32 %0, i32 %6, i32 %5)
ret i32 1
}
unsigned long read_cr0(void) {
  unsigned long val;
  asm volatile("mov %%cr0, %0" : "=r"(val) : : "memory");
  return val;
}


x86 assembly (clang, -O0):
<read_cr0>:
push   %rbp
mov    %rsp,%rbp
mov    %cr0,%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<read_cr0>:
mov    %cr0,%rax
ret

LLVM IR (-O0):
define i64 @read_cr0() {
%1 = alloca i64
%2 = call i64 asm sideeffect "mov %cr0, $0", "=r,~{memory},~{dirflag},~{fpsr},~{flags}"()
store i64 %2, i64* %1
%3 = load i64, i64* %1
ret i64 %3
}

LLVM IR (-O2):
define i64 @read_cr0() {
%1 = tail call i64 asm sideeffect "mov %cr0, $0", "=r,~{memory},~{dirflag},~{fpsr},~{flags}"()
ret i64 %1
}
/* Type definitions */
union sigval {
  scalar_t__ sival_int;
};
typedef int /*<<< orphan*/ pid_t;

/* Variables and functions */
int /*<<< orphan*/ SIGALRM;
int /*<<< orphan*/ getpid();
int sigqueue(int /*<<< orphan*/ const, int /*<<< orphan*/, union sigval);
int main(void) {
  const pid_t pid = getpid();
  union sigval value;
  value.sival_int = 0;
  return sigqueue(pid, SIGALRM, value);
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x4(%rbp)
mov    $0x0,%al
call   1030 <getpid@plt>
mov    %eax,-0x8(%rbp)
movq   $0x0,-0x10(%rbp)
mov    -0x8(%rbp),%edi
mov    0x2e9d(%rip),%rax
mov    (%rax),%esi
mov    -0x10(%rbp),%rdx
call   1040 <sigqueue@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rax
xor    %eax,%eax
call   1030 <getpid@plt>
mov    0x2eb9(%rip),%rcx
mov    (%rcx),%esi
mov    %eax,%edi
xor    %edx,%edx
pop    %rax
jmp    1040 <sigqueue@plt>

LLVM IR (-O0):
%union.sigval = type { i64 }
@SIGALRM = global i32 0
define i32 @main() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca %union.sigval
store i32 0, i32* %1
%4 = call i32 (...) @getpid()
store i32 %4, i32* %2
%5 = bitcast %union.sigval* %3 to i64*
store i64 0, i64* %5
%6 = load i32, i32* %2
%7 = load i32, i32* @SIGALRM
%8 = getelementptr inbounds %union.sigval, %union.sigval* %3, i32 0, i32 0
%9 = load i64, i64* %8
%10 = call i32 @sigqueue(i32 %6, i32 %7, i64 %9)
ret i32 %10
}

LLVM IR (-O2):
@SIGALRM = global i32 0
define i32 @main() {
%1 = tail call i32 (...) @getpid()
%2 = load i32, i32* @SIGALRM
%3 = tail call i32 @sigqueue(i32 %1, i32 %2, i64 0)
ret i32 %3
}
/* Type definitions */
struct uwsgi_buffer {
  int dummy;
};

/* Variables and functions */
scalar_t__ uwsgi_buffer_append(struct uwsgi_buffer *, char *, int);
int uwsgi_webdav_multistatus_propstat_new(struct uwsgi_buffer *ub) {
  if (uwsgi_buffer_append(ub, "<D:propstat>\n", 13))
    return -1;
  return 0;
}


x86 assembly (clang, -O0):
<uwsgi_webdav_multistatus_propstat_new>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x10(%rbp)
mov    -0x10(%rbp),%rdi
lea    0xed9(%rip),%rsi
mov    $0xd,%edx
call   1030 <uwsgi_buffer_append@plt>
cmp    $0x0,%rax
je     1147 <uwsgi_webdav_multistatus_propstat_new+0x37>
movl   $0xffffffff,-0x4(%rbp)
jmp    114e <uwsgi_webdav_multistatus_propstat_new+0x3e>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<uwsgi_webdav_multistatus_propstat_new>:
push   %rax
lea    0xee8(%rip),%rsi
mov    $0xd,%edx
call   1030 <uwsgi_buffer_append@plt>
neg    %rax
sbb    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
%struct.uwsgi_buffer = type { i32 }
@.str = [14 x i8] c"<D:propstat>\0A\00"
define i32 @uwsgi_webdav_multistatus_propstat_new(%struct.uwsgi_buffer* %0) {
%2 = alloca i32
%3 = alloca %struct.uwsgi_buffer*
store %struct.uwsgi_buffer* %0, %struct.uwsgi_buffer** %3
%4 = load %struct.uwsgi_buffer*, %struct.uwsgi_buffer** %3
%5 = call i64 @uwsgi_buffer_append(%struct.uwsgi_buffer* %4, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i64 0, i64 0), i32 13)
%6 = icmp ne i64 %5, 0
br i1 %6, label %7, label %8
7: ; preds = %1
store i32 -1, i32* %2
br label %9
8: ; preds = %1
store i32 0, i32* %2
br label %9
9: ; preds = %8, %7
%10 = load i32, i32* %2
ret i32 %10
}

LLVM IR (-O2):
%struct.uwsgi_buffer = type { i32 }
@.str = [14 x i8] c"<D:propstat>\0A\00"
define i32 @uwsgi_webdav_multistatus_propstat_new(%struct.uwsgi_buffer* %0) {
%2 = tail call i64 @uwsgi_buffer_append(%struct.uwsgi_buffer* %0, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i64 0, i64 0), i32 13)
%3 = icmp ne i64 %2, 0
%4 = sext i1 %3 to i32
ret i32 %4
}