#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ AssertFailure(char *, int);
int /*<<< orphan*/ UARTBaseValid(unsigned long);
int /*<<< orphan*/ UARTDisable(unsigned long);
int /*<<< orphan*/ UARTEnable(unsigned long);
void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
                         unsigned long ulBaud, unsigned long ulConfig) {
  unsigned long ulDiv;
  {
    if (!(UARTBaseValid(ulBase))) {
      AssertFailure(
          "/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/"
          "2022-01-22/02-19-57/repos/AmesianX/OpenBLT/refs/heads/master/Target/"
          "Demo/ARMCM3_LM3S_EK_LM3S8962_Crossworks/Boot/lib/driverlib/"
          "uartlib.c",
          269);
    }
  };
  {
    if (!(ulBaud != 0)) {
      AssertFailure(
          "/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/"
          "2022-01-22/02-19-57/repos/AmesianX/OpenBLT/refs/heads/master/Target/"
          "Demo/ARMCM3_LM3S_EK_LM3S8962_Crossworks/Boot/lib/driverlib/"
          "uartlib.c",
          270);
    }
  };
  {
    if (!(ulUARTClk >=
          (ulBaud *
           ((((((*((volatile unsigned long *)(0x400FE000))) & 0x70000000) ==
               0x00000000) ||
              (((*((volatile unsigned long *)(0x400FE000))) &
                (0x70000000 | 0x00FF0000)) == (0x10000000 | 0x00000000))) ||
             ((((*((volatile unsigned long *)(0x400FE000))) &
                (0x70000000 | 0x00FF0000)) == (0x10000000 | 0x00010000)) &&
              (((*((volatile unsigned long *)(0x400FE000))) &
                (0x0000FF00 | 0x000000FF)) == (0x00000000 | 0x00000002))) ||
             ((((*((volatile unsigned long *)(0x400FE000))) &
                (0x70000000 | 0x00FF0000)) == (0x10000000 | 0x00030000)) &&
              (((*((volatile unsigned long *)(0x400FE000))) &
                (0x0000FF00 | 0x000000FF)) == (0x00000000 | 0x00000000))))
                ? 16
                : 8)))) {
      AssertFailure(
          "/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/"
          "2022-01-22/02-19-57/repos/AmesianX/OpenBLT/refs/heads/master/Target/"
          "Demo/ARMCM3_LM3S_EK_LM3S8962_Crossworks/Boot/lib/driverlib/"
          "uartlib.c",
          271);
    }
  };
  UARTDisable(ulBase);
  if ((ulBaud * 16) > ulUARTClk) {
    (*((volatile unsigned long *)(ulBase + 0x00000030))) |= 0x00000020;
    ulBaud /= 2;
  } else {
    (*((volatile unsigned long *)(ulBase + 0x00000030))) &= ~(0x00000020);
  }
  ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
  (*((volatile unsigned long *)(ulBase + 0x00000024))) = ulDiv / 64;
  (*((volatile unsigned long *)(ulBase + 0x00000028))) = ulDiv % 64;
  (*((volatile unsigned long *)(ulBase + 0x0000002C))) = ulConfig;
  (*((volatile unsigned long *)(ulBase + 0x00000018))) = 0;
  UARTEnable(ulBase);
}


x86 assembly (clang, -O0):
<UARTConfigSetExpClk>:
push   %rbp
mov    %rsp,%rbp
sub    $0x50,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    -0x8(%rbp),%rdi
call   1050 <UARTBaseValid@plt>
cmp    $0x0,%eax
jne    117b <UARTConfigSetExpClk+0x3b>
lea    0xe8f(%rip),%rdi
mov    $0x10d,%esi
call   1030 <AssertFailure@plt>
cmpq   $0x0,-0x18(%rbp)
jne    1197 <UARTConfigSetExpClk+0x57>
lea    0xe73(%rip),%rdi
mov    $0x10e,%esi
call   1030 <AssertFailure@plt>
mov    -0x10(%rbp),%rax
mov    %rax,-0x40(%rbp)
mov    -0x18(%rbp),%rax
mov    %rax,-0x38(%rbp)
mov    $0x400fe000,%eax
mov    (%rax),%rcx
and    $0x70000000,%rcx
mov    $0x1,%al
cmp    $0x0,%rcx
mov    %al,-0x29(%rbp)
je     125d <UARTConfigSetExpClk+0x11d>
mov    $0x400fe000,%eax
mov    (%rax),%rcx
and    $0x70ff0000,%rcx
mov    $0x1,%al
cmp    $0x10000000,%rcx
mov    %al,-0x29(%rbp)
je     125d <UARTConfigSetExpClk+0x11d>
mov    $0x400fe000,%eax
mov    (%rax),%rax
and    $0x70ff0000,%rax
cmp    $0x10010000,%rax
jne    121e <UARTConfigSetExpClk+0xde>
mov    $0x400fe000,%eax
mov    (%rax),%rcx
and    $0xffff,%rcx
mov    $0x1,%al
cmp    $0x2,%rcx
mov    %al,-0x29(%rbp)
je     125d <UARTConfigSetExpClk+0x11d>
mov    $0x400fe000,%eax
mov    (%rax),%rcx
and    $0x70ff0000,%rcx
xor    %eax,%eax
cmp    $0x10030000,%rcx
mov    %al,-0x41(%rbp)
jne    1257 <UARTConfigSetExpClk+0x117>
mov    $0x400fe000,%eax
mov    (%rax),%rax
and    $0xffff,%rax
cmp    $0x0,%rax
sete   %al
mov    %al,-0x41(%rbp)
mov    -0x41(%rbp),%al
mov    %al,-0x29(%rbp)
mov    -0x40(%rbp),%rax
mov    -0x38(%rbp),%rcx
mov    -0x29(%rbp),%dil
mov    $0x8,%edx
mov    $0x10,%esi
test   $0x1,%dil
cmovne %esi,%edx
movslq %edx,%rdx
imul   %rdx,%rcx
cmp    %rcx,%rax
jae    129b <UARTConfigSetExpClk+0x15b>
lea    0xd6f(%rip),%rdi
mov    $0x10f,%esi
call   1030 <AssertFailure@plt>
mov    -0x8(%rbp),%rdi
call   1040 <UARTDisable@plt>
mov    -0x18(%rbp),%rax
shl    $0x4,%rax
cmp    -0x10(%rbp),%rax
jbe    12d7 <UARTConfigSetExpClk+0x197>
mov    -0x8(%rbp),%rax
mov    0x30(%rax),%rcx
or     $0x20,%rcx
mov    %rcx,0x30(%rax)
mov    -0x18(%rbp),%rax
shr    $0x1,%rax
mov    %rax,-0x18(%rbp)
jmp    12e7 <UARTConfigSetExpClk+0x1a7>
mov    -0x8(%rbp),%rax
mov    0x30(%rax),%rcx
and    $0xffffffffffffffdf,%rcx
mov    %rcx,0x30(%rax)
mov    -0x10(%rbp),%rax
shl    $0x3,%rax
xor    %ecx,%ecx
mov    %ecx,%edx
divq   -0x18(%rbp)
add    $0x1,%rax
shr    $0x1,%rax
mov    %rax,-0x28(%rbp)
mov    -0x28(%rbp),%rcx
shr    $0x6,%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x24(%rax)
mov    -0x28(%rbp),%rcx
and    $0x3f,%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x28(%rax)
mov    -0x20(%rbp),%rcx
mov    -0x8(%rbp),%rax
mov    %rcx,0x2c(%rax)
mov    -0x8(%rbp),%rax
movq   $0x0,0x18(%rax)
mov    -0x8(%rbp),%rdi
call   1060 <UARTEnable@plt>
add    $0x50,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTConfigSetExpClk>:
push   %r15
push   %r14
push   %r12
push   %rbx
push   %rax
mov    %rcx,%r14
mov    %rdx,%r15
mov    %rsi,%r12
mov    %rdi,%rbx
call   1050 <UARTBaseValid@plt>
test   %eax,%eax
je     124b <UARTConfigSetExpClk+0x10b>
test   %r15,%r15
je     1265 <UARTConfigSetExpClk+0x125>
mov    $0x10,%eax
testq  $0x70000000,0x400fe000
je     11ea <UARTConfigSetExpClk+0xaa>
mov    0x400fe000,%rcx
40
and    $0x70ff0000,%ecx
cmp    $0x10000000,%ecx
je     11ea <UARTConfigSetExpClk+0xaa>
mov    0x400fe000,%rcx
40
and    $0x70ff0000,%ecx
cmp    $0x10010000,%ecx
jne    11b7 <UARTConfigSetExpClk+0x77>
mov    0x400fe000,%rcx
40
cmp    $0x2,%cx
je     11ea <UARTConfigSetExpClk+0xaa>
mov    0x400fe000,%rcx
40
and    $0x70ff0000,%ecx
mov    $0x8,%eax
cmp    $0x10030000,%ecx
jne    11ea <UARTConfigSetExpClk+0xaa>
mov    0x400fe000,%rax
40
xor    %ecx,%ecx
test   %ax,%ax
sete   %cl
lea    0x8(,%rcx,8),%rax
imul   %r15,%rax
cmp    %r12,%rax
jbe    1204 <UARTConfigSetExpClk+0xc4>
lea    0xe06(%rip),%rdi
mov    $0x10f,%esi
call   1030 <AssertFailure@plt>
mov    %rbx,%rdi
call   1040 <UARTDisable@plt>
mov    %r15,%rcx
shl    $0x4,%rcx
mov    0x30(%rbx),%rax
cmp    %r12,%rcx
jbe    1229 <UARTConfigSetExpClk+0xe9>
or     $0x20,%rax
mov    %rax,0x30(%rbx)
shr    %r15
jmp    1231 <UARTConfigSetExpClk+0xf1>
and    $0xffffffffffffffdf,%rax
mov    %rax,0x30(%rbx)
shl    $0x3,%r12
mov    %r12,%rax
or     %r15,%rax
shr    $0x20,%rax
je     127b <UARTConfigSetExpClk+0x13b>
mov    %r12,%rax
xor    %edx,%edx
div    %r15
jmp    1283 <UARTConfigSetExpClk+0x143>
lea    0xdae(%rip),%rdi
mov    $0x10d,%esi
call   1030 <AssertFailure@plt>
test   %r15,%r15
jne    116a <UARTConfigSetExpClk+0x2a>
lea    0xd94(%rip),%rdi
mov    $0x10e,%esi
call   1030 <AssertFailure@plt>
jmp    116a <UARTConfigSetExpClk+0x2a>
mov    %r12d,%eax
xor    %edx,%edx
div    %r15d
add    $0x1,%rax
mov    %eax,%ecx
shr    %ecx
and    $0x3f,%ecx
shr    $0x7,%rax
mov    %rax,0x24(%rbx)
mov    %rcx,0x28(%rbx)
mov    %r14,0x2c(%rbx)
movq   $0x0,0x18(%rbx)
mov    %rbx,%rdi
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
jmp    1060 <UARTEnable@plt>

LLVM IR (-O0):
@.str = [201 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/AmesianX/OpenBLT/refs/heads/master/Target/Demo/ARMCM3_LM3S_EK_LM3S8962_Crossworks/Boot/lib/driverlib/uartlib.c\00"
define void @UARTConfigSetExpClk(i64 %0, i64 %1, i64 %2, i64 %3) {
%5 = alloca i64
%6 = alloca i64
%7 = alloca i64
%8 = alloca i64
%9 = alloca i64
store i64 %0, i64* %5
store i64 %1, i64* %6
store i64 %2, i64* %7
store i64 %3, i64* %8
%10 = load i64, i64* %5
%11 = call i32 @UARTBaseValid(i64 %10)
%12 = icmp ne i32 %11, 0
br i1 %12, label %15, label %13
13: ; preds = %4
%14 = call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 269)
br label %15
15: ; preds = %13, %4
%16 = load i64, i64* %7
%17 = icmp ne i64 %16, 0
br i1 %17, label %20, label %18
18: ; preds = %15
%19 = call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 270)
br label %20
20: ; preds = %18, %15
%21 = load i64, i64* %6
%22 = load i64, i64* %7
%23 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%24 = and i64 %23, 1879048192
%25 = icmp eq i64 %24, 0
br i1 %25, label %48, label %26
26: ; preds = %20
%27 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%28 = and i64 %27, 1895759872
%29 = icmp eq i64 %28, 268435456
br i1 %29, label %48, label %30
30: ; preds = %26
%31 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%32 = and i64 %31, 1895759872
%33 = icmp eq i64 %32, 268500992
br i1 %33, label %34, label %38
34: ; preds = %30
%35 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%36 = and i64 %35, 65535
%37 = icmp eq i64 %36, 2
br i1 %37, label %48, label %38
38: ; preds = %34, %30
%39 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%40 = and i64 %39, 1895759872
%41 = icmp eq i64 %40, 268632064
br i1 %41, label %42, label %46
42: ; preds = %38
%43 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%44 = and i64 %43, 65535
%45 = icmp eq i64 %44, 0
br label %46
46: ; preds = %42, %38
%47 = phi i1 [ false, %38 ], [ %45, %42 ]
br label %48
48: ; preds = %46, %34, %26, %20
%49 = phi i1 [ true, %34 ], [ true, %26 ], [ true, %20 ], [ %47, %46 ]
%50 = zext i1 %49 to i64
%51 = select i1 %49, i32 16, i32 8
%52 = sext i32 %51 to i64
%53 = mul i64 %22, %52
%54 = icmp uge i64 %21, %53
br i1 %54, label %57, label %55
55: ; preds = %48
%56 = call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 271)
br label %57
57: ; preds = %55, %48
%58 = load i64, i64* %5
%59 = call i32 @UARTDisable(i64 %58)
%60 = load i64, i64* %7
%61 = mul i64 %60, 16
%62 = load i64, i64* %6
%63 = icmp ugt i64 %61, %62
br i1 %63, label %64, label %72
64: ; preds = %57
%65 = load i64, i64* %5
%66 = add i64 %65, 48
%67 = inttoptr i64 %66 to i64*
%68 = load volatile i64, i64* %67
%69 = or i64 %68, 32
store volatile i64 %69, i64* %67
%70 = load i64, i64* %7
%71 = udiv i64 %70, 2
store i64 %71, i64* %7
br label %78
72: ; preds = %57
%73 = load i64, i64* %5
%74 = add i64 %73, 48
%75 = inttoptr i64 %74 to i64*
%76 = load volatile i64, i64* %75
%77 = and i64 %76, -33
store volatile i64 %77, i64* %75
br label %78
78: ; preds = %72, %64
%79 = load i64, i64* %6
%80 = mul i64 %79, 8
%81 = load i64, i64* %7
%82 = udiv i64 %80, %81
%83 = add i64 %82, 1
%84 = udiv i64 %83, 2
store i64 %84, i64* %9
%85 = load i64, i64* %9
%86 = udiv i64 %85, 64
%87 = load i64, i64* %5
%88 = add i64 %87, 36
%89 = inttoptr i64 %88 to i64*
store volatile i64 %86, i64* %89
%90 = load i64, i64* %9
%91 = urem i64 %90, 64
%92 = load i64, i64* %5
%93 = add i64 %92, 40
%94 = inttoptr i64 %93 to i64*
store volatile i64 %91, i64* %94
%95 = load i64, i64* %8
%96 = load i64, i64* %5
%97 = add i64 %96, 44
%98 = inttoptr i64 %97 to i64*
store volatile i64 %95, i64* %98
%99 = load i64, i64* %5
%100 = add i64 %99, 24
%101 = inttoptr i64 %100 to i64*
store volatile i64 0, i64* %101
%102 = load i64, i64* %5
%103 = call i32 @UARTEnable(i64 %102)
ret void
}

LLVM IR (-O2):
@.str = [201 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/AmesianX/OpenBLT/refs/heads/master/Target/Demo/ARMCM3_LM3S_EK_LM3S8962_Crossworks/Boot/lib/driverlib/uartlib.c\00"
define void @UARTConfigSetExpClk(i64 %0, i64 %1, i64 %2, i64 %3) {
%5 = tail call i32 @UARTBaseValid(i64 %0)
%6 = icmp eq i32 %5, 0
br i1 %6, label %7, label %9
7: ; preds = %4
%8 = tail call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 269)
br label %9
9: ; preds = %7, %4
%10 = icmp eq i64 %2, 0
br i1 %10, label %11, label %13
11: ; preds = %9
%12 = tail call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 270)
br label %13
13: ; preds = %11, %9
%14 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%15 = and i64 %14, 1879048192
%16 = icmp eq i64 %15, 0
br i1 %16, label %38, label %17
17: ; preds = %13
%18 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%19 = and i64 %18, 1895759872
%20 = icmp eq i64 %19, 268435456
br i1 %20, label %38, label %21
21: ; preds = %17
%22 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%23 = and i64 %22, 1895759872
%24 = icmp eq i64 %23, 268500992
br i1 %24, label %25, label %29
25: ; preds = %21
%26 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%27 = and i64 %26, 65535
%28 = icmp eq i64 %27, 2
br i1 %28, label %38, label %29
29: ; preds = %25, %21
%30 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%31 = and i64 %30, 1895759872
%32 = icmp eq i64 %31, 268632064
br i1 %32, label %33, label %38
33: ; preds = %29
%34 = load volatile i64, i64* inttoptr (i64 1074782208 to i64*)
%35 = and i64 %34, 65535
%36 = icmp eq i64 %35, 0
%37 = select i1 %36, i64 16, i64 8
br label %38
38: ; preds = %29, %33, %25, %17, %13
%39 = phi i64 [ 16, %25 ], [ 16, %17 ], [ 16, %13 ], [ 8, %29 ], [ %37, %33 ]
%40 = mul i64 %39, %2
%41 = icmp ugt i64 %40, %1
br i1 %41, label %42, label %44
42: ; preds = %38
%43 = tail call i32 @AssertFailure(i8* getelementptr inbounds ([201 x i8], [201 x i8]* @.str, i64 0, i64 0), i32 271)
br label %44
44: ; preds = %42, %38
%45 = tail call i32 @UARTDisable(i64 %0)
%46 = shl i64 %2, 4
%47 = icmp ugt i64 %46, %1
%48 = add i64 %0, 48
%49 = inttoptr i64 %48 to i64*
%50 = load volatile i64, i64* %49
br i1 %47, label %51, label %54
51: ; preds = %44
%52 = or i64 %50, 32
store volatile i64 %52, i64* %49
%53 = lshr i64 %2, 1
br label %56
54: ; preds = %44
%55 = and i64 %50, -33
store volatile i64 %55, i64* %49
br label %56
56: ; preds = %54, %51
%57 = phi i64 [ %53, %51 ], [ %2, %54 ]
%58 = shl i64 %1, 3
%59 = udiv i64 %58, %57
%60 = add nuw i64 %59, 1
%61 = lshr i64 %60, 1
%62 = lshr i64 %60, 7
%63 = add i64 %0, 36
%64 = inttoptr i64 %63 to i64*
store volatile i64 %62, i64* %64
%65 = and i64 %61, 63
%66 = add i64 %0, 40
%67 = inttoptr i64 %66 to i64*
store volatile i64 %65, i64* %67
%68 = add i64 %0, 44
%69 = inttoptr i64 %68 to i64*
store volatile i64 %3, i64* %69
%70 = add i64 %0, 24
%71 = inttoptr i64 %70 to i64*
store volatile i64 0, i64* %71
%72 = tail call i32 @UARTEnable(i64 %0)
ret void
}