char fs_bit_mask_get(short nbit) {
  if (nbit == 0)
    return 0x80;
  else if (nbit == 1)
    return 0x40;
  else if (nbit == 2)
    return 0x20;
  else if (nbit == 3)
    return 0x10;
  else if (nbit == 4)
    return 0x08;
  else if (nbit == 5)
    return 0x04;
  else if (nbit == 6)
    return 0x02;
  else if (nbit == 7)
    return 0x01;
  return 0x00;
}


x86 assembly (clang, -O0):
<fs_bit_mask_get>:
push   %rbp
mov    %rsp,%rbp
mov    %di,%ax
mov    %ax,-0x4(%rbp)
movswl -0x4(%rbp),%eax
cmp    $0x0,%eax
jne    1121 <fs_bit_mask_get+0x21>
movb   $0x80,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x1,%eax
jne    1137 <fs_bit_mask_get+0x37>
movb   $0x40,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x2,%eax
jne    114d <fs_bit_mask_get+0x4d>
movb   $0x20,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x3,%eax
jne    1163 <fs_bit_mask_get+0x63>
movb   $0x10,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x4,%eax
jne    1179 <fs_bit_mask_get+0x79>
movb   $0x8,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x5,%eax
jne    118f <fs_bit_mask_get+0x8f>
movb   $0x4,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x6,%eax
jne    11a5 <fs_bit_mask_get+0xa5>
movb   $0x2,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
movswl -0x4(%rbp),%eax
cmp    $0x7,%eax
jne    11bb <fs_bit_mask_get+0xbb>
movb   $0x1,-0x1(%rbp)
jmp    11e2 <fs_bit_mask_get+0xe2>
jmp    11c0 <fs_bit_mask_get+0xc0>
jmp    11c5 <fs_bit_mask_get+0xc5>
jmp    11ca <fs_bit_mask_get+0xca>
jmp    11cf <fs_bit_mask_get+0xcf>
jmp    11d4 <fs_bit_mask_get+0xd4>
jmp    11d9 <fs_bit_mask_get+0xd9>
jmp    11de <fs_bit_mask_get+0xde>
movb   $0x0,-0x1(%rbp)
movsbl -0x1(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<fs_bit_mask_get>:
lea    0x0(,%rdi,8),%ecx
movabs $0x102040810204080,%rax
04 02 01
shr    %cl,%rax
xor    %ecx,%ecx
cmp    $0x8,%di
cmovae %ecx,%eax
ret

LLVM IR (-O0):
define signext i8 @fs_bit_mask_get(i16 signext %0) {
%2 = alloca i8
%3 = alloca i16
store i16 %0, i16* %3
%4 = load i16, i16* %3
%5 = sext i16 %4 to i32
%6 = icmp eq i32 %5, 0
br i1 %6, label %7, label %8
7: ; preds = %1
store i8 -128, i8* %2
br label %51
8: ; preds = %1
%9 = load i16, i16* %3
%10 = sext i16 %9 to i32
%11 = icmp eq i32 %10, 1
br i1 %11, label %12, label %13
12: ; preds = %8
store i8 64, i8* %2
br label %51
13: ; preds = %8
%14 = load i16, i16* %3
%15 = sext i16 %14 to i32
%16 = icmp eq i32 %15, 2
br i1 %16, label %17, label %18
17: ; preds = %13
store i8 32, i8* %2
br label %51
18: ; preds = %13
%19 = load i16, i16* %3
%20 = sext i16 %19 to i32
%21 = icmp eq i32 %20, 3
br i1 %21, label %22, label %23
22: ; preds = %18
store i8 16, i8* %2
br label %51
23: ; preds = %18
%24 = load i16, i16* %3
%25 = sext i16 %24 to i32
%26 = icmp eq i32 %25, 4
br i1 %26, label %27, label %28
27: ; preds = %23
store i8 8, i8* %2
br label %51
28: ; preds = %23
%29 = load i16, i16* %3
%30 = sext i16 %29 to i32
%31 = icmp eq i32 %30, 5
br i1 %31, label %32, label %33
32: ; preds = %28
store i8 4, i8* %2
br label %51
33: ; preds = %28
%34 = load i16, i16* %3
%35 = sext i16 %34 to i32
%36 = icmp eq i32 %35, 6
br i1 %36, label %37, label %38
37: ; preds = %33
store i8 2, i8* %2
br label %51
38: ; preds = %33
%39 = load i16, i16* %3
%40 = sext i16 %39 to i32
%41 = icmp eq i32 %40, 7
br i1 %41, label %42, label %43
42: ; preds = %38
store i8 1, i8* %2
br label %51
43: ; preds = %38
br label %44
44: ; preds = %43
br label %45
45: ; preds = %44
br label %46
46: ; preds = %45
br label %47
47: ; preds = %46
br label %48
48: ; preds = %47
br label %49
49: ; preds = %48
br label %50
50: ; preds = %49
store i8 0, i8* %2
br label %51
51: ; preds = %50, %42, %37, %32, %27, %22, %17, %12, %7
%52 = load i8, i8* %2
ret i8 %52
}

LLVM IR (-O2):
define signext i8 @fs_bit_mask_get(i16 signext %0) {
%2 = icmp ult i16 %0, 8
%3 = zext i16 %0 to i64
%4 = shl nuw nsw i64 %3, 3
%5 = lshr i64 72624976668147840, %4
%6 = trunc i64 %5 to i8
%7 = select i1 %2, i8 %6, i8 0
ret i8 %7
}