#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int ffs(int);
int /*<<< orphan*/ snprintf(char *, int, char *, char const *, char const *,
                            char const *, char const *, int, int, char const *,
                            int);
void ironlake_debug_pch_dpll(char *result, int len, int reg, uint32_t val,
                             uint32_t devid) {
  const char *enable = val & (1 << 31) ? "enable" : "disable";
  const char *highspeed = val & (1 << 30) ? "yes" : "no";
  const char *mode = NULL;
  const char *p2 = NULL;
  int fpa0_p1, fpa1_p1;
  const char *refclk = NULL;
  int sdvo_mul;
  if ((val & (2 << 26)) == (2 << 26)) {
    mode = "LVDS";
    if (val & (1 << 24))
      p2 = "Div 7";
    else
      p2 = "Div 14";
  } else if ((val & (2 << 26)) == (1 << 26)) {
    mode = "Non-LVDS";
    if (val & (1 << 24))
      p2 = "Div 5";
    else
      p2 = "Div 10";
  }
  fpa0_p1 = ffs((val & 0x00ff0000) >> 16);
  fpa1_p1 = ffs((val & 0xff));
  switch (val & (3 << 13)) {
  case (0 << 13):
    refclk = "default 120Mhz";
    break;
  case (1 << 13):
    refclk = "SuperSSC 120Mhz";
    break;
  case (2 << 13):
    refclk = "SDVO TVClkIn";
    break;
  case (3 << 13):
    refclk = "SSC";
    break;
  case (5 << 13):
    refclk = "DMI RefCLK";
    break;
  }
  sdvo_mul = ((val & (7 << 9)) >> 9) + 1;
  snprintf(result, len,
           "%s, sdvo high speed %s, mode %s, p2 %s, "
           "FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d",
           enable, highspeed, mode, p2, fpa0_p1, fpa1_p1, refclk, sdvo_mul);
}


x86 assembly (clang, -O0):
<ironlake_debug_pch_dpll>:
push   %rbp
mov    %rsp,%rbp
push   %r14
push   %rbx
sub    $0x80,%rsp
mov    %rdi,-0x18(%rbp)
mov    %esi,-0x1c(%rbp)
mov    %edx,-0x20(%rbp)
mov    %ecx,-0x24(%rbp)
mov    %r8d,-0x28(%rbp)
mov    -0x24(%rbp),%edx
and    $0x80000000,%edx
lea    0xeb8(%rip),%rax
lea    0xeaa(%rip),%rcx
cmp    $0x0,%edx
cmovne %rcx,%rax
mov    %rax,-0x30(%rbp)
mov    -0x24(%rbp),%edx
and    $0x40000000,%edx
lea    0xea2(%rip),%rax
lea    0xe97(%rip),%rcx
cmp    $0x0,%edx
cmovne %rcx,%rax
mov    %rax,-0x38(%rbp)
movq   $0x0,-0x40(%rbp)
movq   $0x0,-0x48(%rbp)
movq   $0x0,-0x58(%rbp)
mov    -0x24(%rbp),%eax
and    $0x8000000,%eax
cmp    $0x8000000,%eax
jne    11ea <ironlake_debug_pch_dpll+0xca>
lea    0xe72(%rip),%rax
mov    %rax,-0x40(%rbp)
mov    -0x24(%rbp),%eax
and    $0x1000000,%eax
cmp    $0x0,%eax
je     11da <ironlake_debug_pch_dpll+0xba>
lea    0xe45(%rip),%rax
mov    %rax,-0x48(%rbp)
jmp    11e5 <ironlake_debug_pch_dpll+0xc5>
lea    0xe3b(%rip),%rax
mov    %rax,-0x48(%rbp)
jmp    123e <ironlake_debug_pch_dpll+0x11e>
mov    -0x24(%rbp),%eax
and    $0x8000000,%eax
cmp    $0x4000000,%eax
jne    1239 <ironlake_debug_pch_dpll+0x119>
lea    0xe1f(%rip),%rax
mov    %rax,-0x40(%rbp)
mov    -0x24(%rbp),%eax
and    $0x1000000,%eax
cmp    $0x0,%eax
je     1229 <ironlake_debug_pch_dpll+0x109>
lea    0xe0c(%rip),%rax
mov    %rax,-0x48(%rbp)
jmp    1234 <ironlake_debug_pch_dpll+0x114>
lea    0xe02(%rip),%rax
mov    %rax,-0x48(%rbp)
jmp    1239 <ironlake_debug_pch_dpll+0x119>
jmp    123e <ironlake_debug_pch_dpll+0x11e>
movzbl -0x22(%rbp),%edi
call   1040 <ffs@plt>
mov    %eax,-0x4c(%rbp)
movzbl -0x24(%rbp),%edi
call   1040 <ffs@plt>
mov    %eax,-0x50(%rbp)
mov    -0x24(%rbp),%eax
and    $0x6000,%eax
mov    %eax,-0x60(%rbp)
je     12b8 <ironlake_debug_pch_dpll+0x198>
jmp    126c <ironlake_debug_pch_dpll+0x14c>
mov    -0x60(%rbp),%eax
sub    $0x2000,%eax
je     12c8 <ironlake_debug_pch_dpll+0x1a8>
jmp    127f <ironlake_debug_pch_dpll+0x15f>
mov    -0x60(%rbp),%eax
sub    $0x4000,%eax
je     12d8 <ironlake_debug_pch_dpll+0x1b8>
jmp    1292 <ironlake_debug_pch_dpll+0x172>
mov    -0x60(%rbp),%eax
sub    $0x6000,%eax
je     12e8 <ironlake_debug_pch_dpll+0x1c8>
jmp    12a5 <ironlake_debug_pch_dpll+0x185>
mov    -0x60(%rbp),%eax
sub    $0xa000,%eax
je     12f8 <ironlake_debug_pch_dpll+0x1d8>
jmp    1303 <ironlake_debug_pch_dpll+0x1e3>
lea    0xd7a(%rip),%rax
mov    %rax,-0x58(%rbp)
jmp    1303 <ironlake_debug_pch_dpll+0x1e3>
lea    0xd79(%rip),%rax
mov    %rax,-0x58(%rbp)
jmp    1303 <ironlake_debug_pch_dpll+0x1e3>
lea    0xd79(%rip),%rax
mov    %rax,-0x58(%rbp)
jmp    1303 <ironlake_debug_pch_dpll+0x1e3>
lea    0xd76(%rip),%rax
mov    %rax,-0x58(%rbp)
jmp    1303 <ironlake_debug_pch_dpll+0x1e3>
lea    0xd6a(%rip),%rax
mov    %rax,-0x58(%rbp)
mov    -0x24(%rbp),%eax
and    $0xe00,%eax
sar    $0x9,%eax
add    $0x1,%eax
mov    %eax,-0x5c(%rbp)
mov    -0x18(%rbp),%rdi
mov    -0x1c(%rbp),%esi
mov    -0x30(%rbp),%rcx
mov    -0x38(%rbp),%r8
mov    -0x40(%rbp),%r9
mov    -0x48(%rbp),%r14
mov    -0x4c(%rbp),%ebx
mov    -0x50(%rbp),%r11d
mov    -0x58(%rbp),%r10
mov    -0x5c(%rbp),%eax
lea    0xd34(%rip),%rdx
mov    %r14,(%rsp)
mov    %ebx,0x8(%rsp)
mov    %r11d,0x10(%rsp)
mov    %r10,0x18(%rsp)
mov    %eax,0x20(%rsp)
call   1030 <snprintf@plt>
add    $0x80,%rsp
pop    %rbx
pop    %r14
pop    %rbp
ret

x86 assembly (clang, -O2):
<ironlake_debug_pch_dpll>:
push   %r14
push   %rbx
push   %rax
mov    %ecx,%eax
shr    $0x10,%ecx
mov    %eax,%edx
shr    $0xd,%edx
and    $0x3,%edx
lea    0xf8c(%rip),%rbx
movslq (%rbx,%rdx,4),%r11
add    %rbx,%r11
test   $0x1000000,%eax
lea    0xee6(%rip),%rdx
lea    0xed9(%rip),%r10
cmove  %rdx,%r10
xor    %edx,%edx
test   $0x8000000,%eax
movzbl %cl,%ecx
movzbl %al,%ebx
lea    0xebc(%rip),%r9
cmove  %rdx,%r9
cmove  %rdx,%r10
bsf    %ebx,%r14d
mov    $0xffffffff,%edx
cmove  %edx,%r14d
add    $0x1,%r14d
bsf    %ecx,%ebx
cmove  %edx,%ebx
add    $0x1,%ebx
test   $0x40000000,%eax
lea    0xe8b(%rip),%rcx
lea    0xe80(%rip),%r8
cmove  %rcx,%r8
test   %eax,%eax
lea    0xe6b(%rip),%rdx
lea    0xe5d(%rip),%rcx
cmovns %rdx,%rcx
shr    $0x9,%eax
and    $0x7,%eax
add    $0x1,%eax
sub    $0x8,%rsp
lea    0xe9d(%rip),%rdx
push   %rax
push   %r11
push   %r14
push   %rbx
push   %r10
call   1030 <snprintf@plt>
add    $0x38,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
@.str = [7 x i8] c"enable\00"
@.str.1 = [8 x i8] c"disable\00"
@.str.2 = [4 x i8] c"yes\00"
@.str.3 = [3 x i8] c"no\00"
@.str.4 = [5 x i8] c"LVDS\00"
@.str.5 = [6 x i8] c"Div 7\00"
@.str.6 = [7 x i8] c"Div 14\00"
@.str.7 = [9 x i8] c"Non-LVDS\00"
@.str.8 = [6 x i8] c"Div 5\00"
@.str.9 = [7 x i8] c"Div 10\00"
@.str.10 = [15 x i8] c"default 120Mhz\00"
@.str.11 = [16 x i8] c"SuperSSC 120Mhz\00"
@.str.12 = [13 x i8] c"SDVO TVClkIn\00"
@.str.13 = [4 x i8] c"SSC\00"
@.str.14 = [11 x i8] c"DMI RefCLK\00"
@.str.15 = [92 x i8] c"%s, sdvo high speed %s, mode %s, p2 %s, FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d\00"
define void @ironlake_debug_pch_dpll(i8* %0, i32 %1, i32 %2, i32 %3, i32 %4) {
%6 = alloca i8*
%7 = alloca i32
%8 = alloca i32
%9 = alloca i32
%10 = alloca i32
%11 = alloca i8*
%12 = alloca i8*
%13 = alloca i8*
%14 = alloca i8*
%15 = alloca i32
%16 = alloca i32
%17 = alloca i8*
%18 = alloca i32
store i8* %0, i8** %6
store i32 %1, i32* %7
store i32 %2, i32* %8
store i32 %3, i32* %9
store i32 %4, i32* %10
%19 = load i32, i32* %9
%20 = and i32 %19, -2147483648
%21 = icmp ne i32 %20, 0
%22 = zext i1 %21 to i64
%23 = select i1 %21, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.1, i64 0, i64 0)
store i8* %23, i8** %11
%24 = load i32, i32* %9
%25 = and i32 %24, 1073741824
%26 = icmp ne i32 %25, 0
%27 = zext i1 %26 to i64
%28 = select i1 %26, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.2, i64 0, i64 0), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.3, i64 0, i64 0)
store i8* %28, i8** %12
store i8* null, i8** %13
store i8* null, i8** %14
store i8* null, i8** %17
%29 = load i32, i32* %9
%30 = and i32 %29, 134217728
%31 = icmp eq i32 %30, 134217728
br i1 %31, label %32, label %39
32: ; preds = %5
store i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.4, i64 0, i64 0), i8** %13
%33 = load i32, i32* %9
%34 = and i32 %33, 16777216
%35 = icmp ne i32 %34, 0
br i1 %35, label %36, label %37
36: ; preds = %32
store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.5, i64 0, i64 0), i8** %14
br label %38
37: ; preds = %32
store i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.6, i64 0, i64 0), i8** %14
br label %38
38: ; preds = %37, %36
br label %51
39: ; preds = %5
%40 = load i32, i32* %9
%41 = and i32 %40, 134217728
%42 = icmp eq i32 %41, 67108864
br i1 %42, label %43, label %50
43: ; preds = %39
store i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.7, i64 0, i64 0), i8** %13
%44 = load i32, i32* %9
%45 = and i32 %44, 16777216
%46 = icmp ne i32 %45, 0
br i1 %46, label %47, label %48
47: ; preds = %43
store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.8, i64 0, i64 0), i8** %14
br label %49
48: ; preds = %43
store i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.9, i64 0, i64 0), i8** %14
br label %49
49: ; preds = %48, %47
br label %50
50: ; preds = %49, %39
br label %51
51: ; preds = %50, %38
%52 = load i32, i32* %9
%53 = and i32 %52, 16711680
%54 = ashr i32 %53, 16
%55 = call i32 @ffs(i32 %54)
store i32 %55, i32* %15
%56 = load i32, i32* %9
%57 = and i32 %56, 255
%58 = call i32 @ffs(i32 %57)
store i32 %58, i32* %16
%59 = load i32, i32* %9
%60 = and i32 %59, 24576
switch i32 %60, label %66 [
i32 0, label %61
i32 8192, label %62
i32 16384, label %63
i32 24576, label %64
i32 40960, label %65
]
61: ; preds = %51
store i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str.10, i64 0, i64 0), i8** %17
br label %66
62: ; preds = %51
store i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str.11, i64 0, i64 0), i8** %17
br label %66
63: ; preds = %51
store i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.12, i64 0, i64 0), i8** %17
br label %66
64: ; preds = %51
store i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.13, i64 0, i64 0), i8** %17
br label %66
65: ; preds = %51
store i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str.14, i64 0, i64 0), i8** %17
br label %66
66: ; preds = %51, %65, %64, %63, %62, %61
%67 = load i32, i32* %9
%68 = and i32 %67, 3584
%69 = ashr i32 %68, 9
%70 = add nsw i32 %69, 1
store i32 %70, i32* %18
%71 = load i8*, i8** %6
%72 = load i32, i32* %7
%73 = load i8*, i8** %11
%74 = load i8*, i8** %12
%75 = load i8*, i8** %13
%76 = load i8*, i8** %14
%77 = load i32, i32* %15
%78 = load i32, i32* %16
%79 = load i8*, i8** %17
%80 = load i32, i32* %18
%81 = call i32 @snprintf(i8* %71, i32 %72, i8* getelementptr inbounds ([92 x i8], [92 x i8]* @.str.15, i64 0, i64 0), i8* %73, i8* %74, i8* %75, i8* %76, i32 %77, i32 %78, i8* %79, i32 %80)
ret void
}

LLVM IR (-O2):
@.str = [7 x i8] c"enable\00"
@.str.1 = [8 x i8] c"disable\00"
@.str.2 = [4 x i8] c"yes\00"
@.str.3 = [3 x i8] c"no\00"
@.str.4 = [5 x i8] c"LVDS\00"
@.str.5 = [6 x i8] c"Div 7\00"
@.str.6 = [7 x i8] c"Div 14\00"
@.str.10 = [15 x i8] c"default 120Mhz\00"
@.str.11 = [16 x i8] c"SuperSSC 120Mhz\00"
@.str.12 = [13 x i8] c"SDVO TVClkIn\00"
@.str.13 = [4 x i8] c"SSC\00"
@.str.15 = [92 x i8] c"%s, sdvo high speed %s, mode %s, p2 %s, FPA0 P1 %d, FPA1 P1 %d, refclk %s, sdvo/hdmi mul %d\00"
@reltable.ironlake_debug_pch_dpll = [4 x i32] [i32 trunc (i64 sub (i64 ptrtoint ([15 x i8]* @.str.10 to i64), i64 ptrtoint ([4 x i32]* @reltable.ironlake_debug_pch_dpll to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([16 x i8]* @.str.11 to i64), i64 ptrtoint ([4 x i32]* @reltable.ironlake_debug_pch_dpll to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([13 x i8]* @.str.12 to i64), i64 ptrtoint ([4 x i32]* @reltable.ironlake_debug_pch_dpll to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint ([4 x i8]* @.str.13 to i64), i64 ptrtoint ([4 x i32]* @reltable.ironlake_debug_pch_dpll to i64)) to i32)]
define void @ironlake_debug_pch_dpll(i8* %0, i32 %1, i32 %2, i32 %3, i32 %4) {
%6 = and i32 %3, 134217728
%7 = icmp eq i32 %6, 0
%8 = lshr i32 %3, 16
%9 = and i32 %8, 255
%10 = and i32 %3, 255
%11 = lshr i32 %3, 13
%12 = and i32 %11, 3
%13 = zext i32 %12 to i64
%14 = shl i64 %13, 2
%15 = call i8* @llvm.load.relative.i64(i8* bitcast ([4 x i32]* @reltable.ironlake_debug_pch_dpll to i8*), i64 %14)
%16 = select i1 %7, i8* null, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.4, i64 0, i64 0)
%17 = and i32 %3, 16777216
%18 = icmp eq i32 %17, 0
%19 = select i1 %18, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.6, i64 0, i64 0), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.5, i64 0, i64 0)
%20 = select i1 %7, i8* null, i8* %19
%21 = icmp eq i32 %10, 0
%22 = tail call i32 @llvm.cttz.i32(i32 %10, i1 true)
%23 = add nuw nsw i32 %22, 1
%24 = select i1 %21, i32 0, i32 %23
%25 = icmp eq i32 %9, 0
%26 = tail call i32 @llvm.cttz.i32(i32 %9, i1 true)
%27 = add nuw nsw i32 %26, 1
%28 = select i1 %25, i32 0, i32 %27
%29 = and i32 %3, 1073741824
%30 = icmp eq i32 %29, 0
%31 = select i1 %30, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.3, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.2, i64 0, i64 0)
%32 = icmp sgt i32 %3, -1
%33 = select i1 %32, i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.1, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i64 0, i64 0)
%34 = lshr i32 %3, 9
%35 = and i32 %34, 7
%36 = add nuw nsw i32 %35, 1
%37 = tail call i32 @snprintf(i8* %0, i32 %1, i8* getelementptr inbounds ([92 x i8], [92 x i8]* @.str.15, i64 0, i64 0), i8* %33, i8* %31, i8* %16, i8* %20, i32 %28, i32 %24, i8* %15, i32 %36)
ret void
}