#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
float expf(float);
void neuralops_logistic_fwd(size_t batch_sz, size_t dim, const float *in_buf,
                            float *out_buf) {
#pragma omp parallel for
  for (size_t p = 0; p < batch_sz * dim; p += 1) {
    float x = in_buf[p];
    out_buf[p] = 1.0f / (1.0f + expf(-x));
  }
}


x86 assembly (clang, -O0):
<neuralops_logistic_fwd>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
movq   $0x0,-0x28(%rbp)
mov    -0x28(%rbp),%rax
mov    -0x8(%rbp),%rcx
imul   -0x10(%rbp),%rcx
cmp    %rcx,%rax
jae    11a5 <neuralops_logistic_fwd+0x95>
mov    -0x18(%rbp),%rax
mov    -0x28(%rbp),%rcx
movss  (%rax,%rcx,4),%xmm0
movss  %xmm0,-0x2c(%rbp)
movss  -0x2c(%rbp),%xmm0
movd   %xmm0,%eax
xor    $0x80000000,%eax
movd   %eax,%xmm0
call   1030 <expf@plt>
movss  0xe89(%rip),%xmm1
addss  %xmm0,%xmm1
movss  0xe7d(%rip),%xmm0
divss  %xmm1,%xmm0
mov    -0x20(%rbp),%rax
mov    -0x28(%rbp),%rcx
movss  %xmm0,(%rax,%rcx,4)
mov    -0x28(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x28(%rbp)
jmp    1130 <neuralops_logistic_fwd+0x20>
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<neuralops_logistic_fwd>:
push   %r15
push   %r14
push   %r12
push   %rbx
push   %rax
mov    %rdi,%r12
imul   %rsi,%r12
test   %r12,%r12
je     1161 <neuralops_logistic_fwd+0x51>
mov    %rcx,%r14
mov    %rdx,%r15
xor    %ebx,%ebx
nopl   0x0(%rax)
movss  (%r15,%rbx,4),%xmm0
xorps  0xec3(%rip),%xmm0
call   1030 <expf@plt>
movss  0xec6(%rip),%xmm1
addss  %xmm1,%xmm0
divss  %xmm0,%xmm1
movss  %xmm1,(%r14,%rbx,4)
add    $0x1,%rbx
cmp    %rbx,%r12
jne    1130 <neuralops_logistic_fwd+0x20>
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define void @neuralops_logistic_fwd(i64 %0, i64 %1, float* %2, float* %3) {
%5 = alloca i64
%6 = alloca i64
%7 = alloca float*
%8 = alloca float*
%9 = alloca i64
%10 = alloca float
store i64 %0, i64* %5
store i64 %1, i64* %6
store float* %2, float** %7
store float* %3, float** %8
store i64 0, i64* %9
br label %11
11: ; preds = %30, %4
%12 = load i64, i64* %9
%13 = load i64, i64* %5
%14 = load i64, i64* %6
%15 = mul i64 %13, %14
%16 = icmp ult i64 %12, %15
br i1 %16, label %17, label %33
17: ; preds = %11
%18 = load float*, float** %7
%19 = load i64, i64* %9
%20 = getelementptr inbounds float, float* %18, i64 %19
%21 = load float, float* %20
store float %21, float* %10
%22 = load float, float* %10
%23 = fneg float %22
%24 = call float @expf(float %23)
%25 = fadd float 1.000000e+00, %24
%26 = fdiv float 1.000000e+00, %25
%27 = load float*, float** %8
%28 = load i64, i64* %9
%29 = getelementptr inbounds float, float* %27, i64 %28
store float %26, float* %29
br label %30
30: ; preds = %17
%31 = load i64, i64* %9
%32 = add i64 %31, 1
store i64 %32, i64* %9
br label %11
33: ; preds = %11
ret void
}

LLVM IR (-O2):
define void @neuralops_logistic_fwd(i64 %0, i64 %1, float* nocapture %2, float* nocapture writeonly %3) {
%5 = mul i64 %1, %0
%6 = icmp eq i64 %5, 0
br i1 %6, label %7, label %8
7: ; preds = %8, %4
ret void
8: ; preds = %4, %8
%9 = phi i64 [ %17, %8 ], [ 0, %4 ]
%10 = getelementptr inbounds float, float* %2, i64 %9
%11 = load float, float* %10
%12 = fneg float %11
%13 = tail call float @expf(float %12)
%14 = fadd float %13, 1.000000e+00
%15 = fdiv float 1.000000e+00, %14
%16 = getelementptr inbounds float, float* %3, i64 %9
store float %15, float* %16
%17 = add nuw i64 %9, 1
%18 = icmp eq i64 %17, %5
br i1 %18, label %7, label %8
}