int error_simgen_getvalue(void *gen, unsigned int mode, unsigned int PID,
                          unsigned int *A, unsigned int *B, unsigned int *C,
                          unsigned int *D) {
  if (0x00 == PID) {
    *A = 0x80;
    *B = 0x00;
    *C = 0x00;
    *D = 0x00;
    return 4;
  }
  if (0x01 == PID) {
    *A = 0x83;
    *B = 0x00;
    *C = 0x00;
    *D = 0x00;
    return 4;
  }
  return 0;
}


x86 assembly (clang, -O0):
<error_simgen_getvalue>:
push   %rbp
mov    %rsp,%rbp
mov    0x10(%rbp),%rax
mov    %rdi,-0x10(%rbp)
mov    %esi,-0x14(%rbp)
mov    %edx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8,-0x28(%rbp)
mov    %r9,-0x30(%rbp)
xor    %eax,%eax
cmp    -0x18(%rbp),%eax
jne    115d <error_simgen_getvalue+0x5d>
mov    -0x20(%rbp),%rax
movl   $0x80,(%rax)
mov    -0x28(%rbp),%rax
movl   $0x0,(%rax)
mov    -0x30(%rbp),%rax
movl   $0x0,(%rax)
mov    0x10(%rbp),%rax
movl   $0x0,(%rax)
movl   $0x4,-0x4(%rbp)
jmp    11a6 <error_simgen_getvalue+0xa6>
mov    $0x1,%eax
cmp    -0x18(%rbp),%eax
jne    119f <error_simgen_getvalue+0x9f>
mov    -0x20(%rbp),%rax
movl   $0x83,(%rax)
mov    -0x28(%rbp),%rax
movl   $0x0,(%rax)
mov    -0x30(%rbp),%rax
movl   $0x0,(%rax)
mov    0x10(%rbp),%rax
movl   $0x0,(%rax)
movl   $0x4,-0x4(%rbp)
jmp    11a6 <error_simgen_getvalue+0xa6>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<error_simgen_getvalue>:
test   %edx,%edx
je     1112 <error_simgen_getvalue+0x12>
xor    %eax,%eax
cmp    $0x1,%edx
jne    1137 <error_simgen_getvalue+0x37>
mov    $0x83,%eax
jmp    1117 <error_simgen_getvalue+0x17>
mov    $0x80,%eax
mov    0x8(%rsp),%rdx
mov    %eax,(%rcx)
movl   $0x0,(%r8)
movl   $0x0,(%r9)
movl   $0x0,(%rdx)
mov    $0x4,%eax
ret

LLVM IR (-O0):
define i32 @error_simgen_getvalue(i8* %0, i32 %1, i32 %2, i32* %3, i32* %4, i32* %5, i32* %6) {
%8 = alloca i32
%9 = alloca i8*
%10 = alloca i32
%11 = alloca i32
%12 = alloca i32*
%13 = alloca i32*
%14 = alloca i32*
%15 = alloca i32*
store i8* %0, i8** %9
store i32 %1, i32* %10
store i32 %2, i32* %11
store i32* %3, i32** %12
store i32* %4, i32** %13
store i32* %5, i32** %14
store i32* %6, i32** %15
%16 = load i32, i32* %11
%17 = icmp eq i32 0, %16
br i1 %17, label %18, label %23
18: ; preds = %7
%19 = load i32*, i32** %12
store i32 128, i32* %19
%20 = load i32*, i32** %13
store i32 0, i32* %20
%21 = load i32*, i32** %14
store i32 0, i32* %21
%22 = load i32*, i32** %15
store i32 0, i32* %22
store i32 4, i32* %8
br label %32
23: ; preds = %7
%24 = load i32, i32* %11
%25 = icmp eq i32 1, %24
br i1 %25, label %26, label %31
26: ; preds = %23
%27 = load i32*, i32** %12
store i32 131, i32* %27
%28 = load i32*, i32** %13
store i32 0, i32* %28
%29 = load i32*, i32** %14
store i32 0, i32* %29
%30 = load i32*, i32** %15
store i32 0, i32* %30
store i32 4, i32* %8
br label %32
31: ; preds = %23
store i32 0, i32* %8
br label %32
32: ; preds = %31, %26, %18
%33 = load i32, i32* %8
ret i32 %33
}

LLVM IR (-O2):
define i32 @error_simgen_getvalue(i8* nocapture readnone %0, i32 %1, i32 %2, i32* nocapture writeonly %3, i32* nocapture writeonly %4, i32* nocapture writeonly %5, i32* nocapture writeonly %6) {
switch i32 %2, label %11 [
i32 0, label %9
i32 1, label %8
]
8: ; preds = %7
br label %9
9: ; preds = %7, %8
%10 = phi i32 [ 131, %8 ], [ 128, %7 ]
store i32 %10, i32* %3
store i32 0, i32* %4
store i32 0, i32* %5
store i32 0, i32* %6
br label %11
11: ; preds = %9, %7
%12 = phi i32 [ 0, %7 ], [ 4, %9 ]
ret i32 %12
}