#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int sio_read_reg(int, unsigned long *);
int sio_write_reg(int, unsigned long);
int FS460_set_sync_mode(int channel, int sync_mode) {
  int err;
  unsigned long mux1, mux2;
  err = sio_read_reg(0x3C, &mux1);
  if (err)
    return err;
  err = sio_read_reg(0x3E, &mux2);
  if (err)
    return err;
  switch (channel) {
  default:
    return 0x1000;
  case 1: {
    switch (sync_mode) {
    default:
      return 0x1000;
    case 0: {
      mux1 &= ~(1 << 2);
      mux1 &= ~(1 << 3);
      mux2 &= ~(1 << 8);
    } break;
    case 1: {
      mux1 |= (1 << 2);
      mux1 &= ~(1 << 3);
      mux2 &= ~(1 << 8);
    } break;
    case 2: {
      mux1 &= ~(1 << 2);
      mux1 |= (1 << 3);
      mux2 &= ~(1 << 8);
    } break;
    case 3: {
      mux1 &= ~(1 << 2);
      mux1 |= (1 << 3);
      mux2 |= (1 << 8);
    } break;
    }
  } break;
  case 3: {
    switch (sync_mode) {
    default:
      return 0x1000;
    case 1: {
      mux1 &= ~(1 << 4);
    } break;
    case 2: {
      mux1 |= (1 << 4);
    } break;
    }
  } break;
  }
  err = sio_write_reg(0x3C, mux1);
  if (err)
    return err;
  err = sio_write_reg(0x3E, mux2);
  if (err)
    return err;
  return 0;
}


x86 assembly (clang, -O0):
<FS460_set_sync_mode>:
push   %rbp
mov    %rsp,%rbp
sub    $0x40,%rsp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    $0x3c,%edi
lea    -0x18(%rbp),%rsi
call   1040 <sio_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1154 <FS460_set_sync_mode+0x34>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    $0x3e,%edi
lea    -0x20(%rbp),%rsi
call   1040 <sio_read_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     117a <FS460_set_sync_mode+0x5a>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    -0x8(%rbp),%eax
mov    %eax,-0x24(%rbp)
sub    $0x1,%eax
je     11ab <FS460_set_sync_mode+0x8b>
jmp    118e <FS460_set_sync_mode+0x6e>
mov    -0x24(%rbp),%eax
sub    $0x3,%eax
je     1288 <FS460_set_sync_mode+0x168>
jmp    119f <FS460_set_sync_mode+0x7f>
movl   $0x1000,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    -0xc(%rbp),%eax
mov    %rax,-0x30(%rbp)
sub    $0x3,%rax
ja     11d0 <FS460_set_sync_mode+0xb0>
mov    -0x30(%rbp),%rax
lea    0xe39(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x1000,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    -0x18(%rbp),%rax
and    $0xfffffffffffffffb,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rax
and    $0xfffffffffffffff7,%rax
mov    %rax,-0x18(%rbp)
mov    -0x20(%rbp),%rax
and    $0xfffffffffffffeff,%rax
mov    %rax,-0x20(%rbp)
jmp    1283 <FS460_set_sync_mode+0x163>
mov    -0x18(%rbp),%rax
or     $0x4,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rax
and    $0xfffffffffffffff7,%rax
mov    %rax,-0x18(%rbp)
mov    -0x20(%rbp),%rax
and    $0xfffffffffffffeff,%rax
mov    %rax,-0x20(%rbp)
jmp    1283 <FS460_set_sync_mode+0x163>
mov    -0x18(%rbp),%rax
and    $0xfffffffffffffffb,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rax
or     $0x8,%rax
mov    %rax,-0x18(%rbp)
mov    -0x20(%rbp),%rax
and    $0xfffffffffffffeff,%rax
mov    %rax,-0x20(%rbp)
jmp    1283 <FS460_set_sync_mode+0x163>
mov    -0x18(%rbp),%rax
and    $0xfffffffffffffffb,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rax
or     $0x8,%rax
mov    %rax,-0x18(%rbp)
mov    -0x20(%rbp),%rax
or     $0x100,%rax
mov    %rax,-0x20(%rbp)
jmp    12db <FS460_set_sync_mode+0x1bb>
mov    -0xc(%rbp),%eax
mov    %eax,-0x34(%rbp)
sub    $0x1,%eax
je     12b9 <FS460_set_sync_mode+0x199>
jmp    129c <FS460_set_sync_mode+0x17c>
mov    -0x34(%rbp),%eax
sub    $0x2,%eax
je     12ca <FS460_set_sync_mode+0x1aa>
jmp    12ad <FS460_set_sync_mode+0x18d>
movl   $0x1000,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    -0x18(%rbp),%rax
and    $0xffffffffffffffef,%rax
mov    %rax,-0x18(%rbp)
jmp    12d6 <FS460_set_sync_mode+0x1b6>
mov    -0x18(%rbp),%rax
or     $0x10,%rax
mov    %rax,-0x18(%rbp)
jmp    12db <FS460_set_sync_mode+0x1bb>
mov    -0x18(%rbp),%rsi
mov    $0x3c,%edi
call   1030 <sio_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1301 <FS460_set_sync_mode+0x1e1>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
mov    -0x20(%rbp),%rsi
mov    $0x3e,%edi
call   1030 <sio_write_reg@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
je     1327 <FS460_set_sync_mode+0x207>
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    132e <FS460_set_sync_mode+0x20e>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x40,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<FS460_set_sync_mode>:
push   %rbp
push   %rbx
sub    $0x18,%rsp
mov    %esi,%ebx
mov    %edi,%ebp
lea    0x8(%rsp),%rsi
mov    $0x3c,%edi
call   1040 <sio_read_reg@plt>
test   %eax,%eax
jne    1150 <FS460_set_sync_mode+0x30>
lea    0x10(%rsp),%rsi
mov    $0x3e,%edi
call   1040 <sio_read_reg@plt>
test   %eax,%eax
je     1157 <FS460_set_sync_mode+0x37>
add    $0x18,%rsp
pop    %rbx
pop    %rbp
ret
mov    $0x1000,%eax
cmp    $0x3,%ebp
je     1188 <FS460_set_sync_mode+0x68>
cmp    $0x1,%ebp
jne    1150 <FS460_set_sync_mode+0x30>
cmp    $0x3,%ebx
ja     1150 <FS460_set_sync_mode+0x30>
mov    %ebx,%eax
lea    0xe8c(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    0x8(%rsp),%rsi
and    $0xfffffffffffffff3,%rsi
jmp    11c9 <FS460_set_sync_mode+0xa9>
cmp    $0x2,%ebx
je     119d <FS460_set_sync_mode+0x7d>
cmp    $0x1,%ebx
jne    1150 <FS460_set_sync_mode+0x30>
mov    0x8(%rsp),%rsi
and    $0xffffffffffffffef,%rsi
jmp    11a6 <FS460_set_sync_mode+0x86>
mov    0x8(%rsp),%rsi
or     $0x10,%rsi
mov    %rsi,0x8(%rsp)
jmp    11ec <FS460_set_sync_mode+0xcc>
mov    0x8(%rsp),%rsi
and    $0xfffffffffffffff3,%rsi
or     $0x4,%rsi
jmp    11c9 <FS460_set_sync_mode+0xa9>
mov    0x8(%rsp),%rsi
and    $0xfffffffffffffff3,%rsi
or     $0x8,%rsi
mov    %rsi,0x8(%rsp)
andb   $0xfe,0x11(%rsp)
jmp    11ec <FS460_set_sync_mode+0xcc>
mov    0x8(%rsp),%rsi
and    $0xfffffffffffffff3,%rsi
or     $0x8,%rsi
mov    %rsi,0x8(%rsp)
orb    $0x1,0x11(%rsp)
mov    $0x3c,%edi
call   1030 <sio_write_reg@plt>
test   %eax,%eax
jne    1150 <FS460_set_sync_mode+0x30>
mov    0x10(%rsp),%rsi
mov    $0x3e,%edi
call   1030 <sio_write_reg@plt>
jmp    1150 <FS460_set_sync_mode+0x30>

LLVM IR (-O0):
define i32 @FS460_set_sync_mode(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i64
%8 = alloca i64
store i32 %0, i32* %4
store i32 %1, i32* %5
%9 = call i32 @sio_read_reg(i32 60, i64* %7)
store i32 %9, i32* %6
%10 = load i32, i32* %6
%11 = icmp ne i32 %10, 0
br i1 %11, label %12, label %14
12: ; preds = %2
%13 = load i32, i32* %6
store i32 %13, i32* %3
br label %80
14: ; preds = %2
%15 = call i32 @sio_read_reg(i32 62, i64* %8)
store i32 %15, i32* %6
%16 = load i32, i32* %6
%17 = icmp ne i32 %16, 0
br i1 %17, label %18, label %20
18: ; preds = %14
%19 = load i32, i32* %6
store i32 %19, i32* %3
br label %80
20: ; preds = %14
%21 = load i32, i32* %4
switch i32 %21, label %22 [
i32 1, label %23
i32 3, label %55
]
22: ; preds = %20
store i32 4096, i32* %3
br label %80
23: ; preds = %20
%24 = load i32, i32* %5
switch i32 %24, label %25 [
i32 0, label %26
i32 1, label %33
i32 2, label %40
i32 3, label %47
]
25: ; preds = %23
store i32 4096, i32* %3
br label %80
26: ; preds = %23
%27 = load i64, i64* %7
%28 = and i64 %27, -5
store i64 %28, i64* %7
%29 = load i64, i64* %7
%30 = and i64 %29, -9
store i64 %30, i64* %7
%31 = load i64, i64* %8
%32 = and i64 %31, -257
store i64 %32, i64* %8
br label %54
33: ; preds = %23
%34 = load i64, i64* %7
%35 = or i64 %34, 4
store i64 %35, i64* %7
%36 = load i64, i64* %7
%37 = and i64 %36, -9
store i64 %37, i64* %7
%38 = load i64, i64* %8
%39 = and i64 %38, -257
store i64 %39, i64* %8
br label %54
40: ; preds = %23
%41 = load i64, i64* %7
%42 = and i64 %41, -5
store i64 %42, i64* %7
%43 = load i64, i64* %7
%44 = or i64 %43, 8
store i64 %44, i64* %7
%45 = load i64, i64* %8
%46 = and i64 %45, -257
store i64 %46, i64* %8
br label %54
47: ; preds = %23
%48 = load i64, i64* %7
%49 = and i64 %48, -5
store i64 %49, i64* %7
%50 = load i64, i64* %7
%51 = or i64 %50, 8
store i64 %51, i64* %7
%52 = load i64, i64* %8
%53 = or i64 %52, 256
store i64 %53, i64* %8
br label %54
54: ; preds = %47, %40, %33, %26
br label %65
55: ; preds = %20
%56 = load i32, i32* %5
switch i32 %56, label %57 [
i32 1, label %58
i32 2, label %61
]
57: ; preds = %55
store i32 4096, i32* %3
br label %80
58: ; preds = %55
%59 = load i64, i64* %7
%60 = and i64 %59, -17
store i64 %60, i64* %7
br label %64
61: ; preds = %55
%62 = load i64, i64* %7
%63 = or i64 %62, 16
store i64 %63, i64* %7
br label %64
64: ; preds = %61, %58
br label %65
65: ; preds = %64, %54
%66 = load i64, i64* %7
%67 = call i32 @sio_write_reg(i32 60, i64 %66)
store i32 %67, i32* %6
%68 = load i32, i32* %6
%69 = icmp ne i32 %68, 0
br i1 %69, label %70, label %72
70: ; preds = %65
%71 = load i32, i32* %6
store i32 %71, i32* %3
br label %80
72: ; preds = %65
%73 = load i64, i64* %8
%74 = call i32 @sio_write_reg(i32 62, i64 %73)
store i32 %74, i32* %6
%75 = load i32, i32* %6
%76 = icmp ne i32 %75, 0
br i1 %76, label %77, label %79
77: ; preds = %72
%78 = load i32, i32* %6
store i32 %78, i32* %3
br label %80
79: ; preds = %72
store i32 0, i32* %3
br label %80
80: ; preds = %79, %77, %70, %57, %25, %22, %18, %12
%81 = load i32, i32* %3
ret i32 %81
}

LLVM IR (-O2):
define i32 @FS460_set_sync_mode(i32 %0, i32 %1) {
%3 = alloca i64
%4 = alloca i64
%5 = bitcast i64* %3 to i8*
%6 = bitcast i64* %4 to i8*
%7 = call i32 @sio_read_reg(i32 60, i64* %3)
%8 = icmp eq i32 %7, 0
br i1 %8, label %9, label %51
9: ; preds = %2
%10 = call i32 @sio_read_reg(i32 62, i64* %4)
%11 = icmp eq i32 %10, 0
br i1 %11, label %12, label %51
12: ; preds = %9
switch i32 %0, label %51 [
i32 1, label %13
i32 3, label %37
]
13: ; preds = %12
switch i32 %1, label %51 [
i32 0, label %14
i32 1, label %19
i32 2, label %25
i32 3, label %31
]
14: ; preds = %13
%15 = load i64, i64* %3
%16 = and i64 %15, -13
store i64 %16, i64* %3
%17 = load i64, i64* %4
%18 = and i64 %17, -257
store i64 %18, i64* %4
br label %44
19: ; preds = %13
%20 = load i64, i64* %3
%21 = and i64 %20, -13
%22 = or i64 %21, 4
store i64 %22, i64* %3
%23 = load i64, i64* %4
%24 = and i64 %23, -257
store i64 %24, i64* %4
br label %44
25: ; preds = %13
%26 = load i64, i64* %3
%27 = and i64 %26, -13
%28 = or i64 %27, 8
store i64 %28, i64* %3
%29 = load i64, i64* %4
%30 = and i64 %29, -257
store i64 %30, i64* %4
br label %44
31: ; preds = %13
%32 = load i64, i64* %3
%33 = and i64 %32, -13
%34 = or i64 %33, 8
store i64 %34, i64* %3
%35 = load i64, i64* %4
%36 = or i64 %35, 256
store i64 %36, i64* %4
br label %44
37: ; preds = %12
switch i32 %1, label %51 [
i32 1, label %38
i32 2, label %41
]
38: ; preds = %37
%39 = load i64, i64* %3
%40 = and i64 %39, -17
store i64 %40, i64* %3
br label %44
41: ; preds = %37
%42 = load i64, i64* %3
%43 = or i64 %42, 16
store i64 %43, i64* %3
br label %44
44: ; preds = %38, %41, %14, %19, %25, %31
%45 = phi i64 [ %40, %38 ], [ %43, %41 ], [ %16, %14 ], [ %22, %19 ], [ %28, %25 ], [ %34, %31 ]
%46 = call i32 @sio_write_reg(i32 60, i64 %45)
%47 = icmp eq i32 %46, 0
br i1 %47, label %48, label %51
48: ; preds = %44
%49 = load i64, i64* %4
%50 = call i32 @sio_write_reg(i32 62, i64 %49)
br label %51
51: ; preds = %48, %44, %37, %13, %12, %9, %2
%52 = phi i32 [ %7, %2 ], [ %10, %9 ], [ 4096, %12 ], [ 4096, %13 ], [ 4096, %37 ], [ %46, %44 ], [ %50, %48 ]
ret i32 %52
}