xunge/DecIR huggingface dataset:
/* Variables and functions */
int /*<<< orphan*/ notify_pvcall(char *);
int pvEnableSingleROI(char byBoardNum, short wX1, short wY1, short wX2,
                      short wY2) {
  notify_pvcall("f");
  return (0);
}


x86 assembly (clang, -O0):
<pvEnableSingleROI>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %r8w,%ax
mov    %dil,-0x1(%rbp)
mov    %si,-0x4(%rbp)
mov    %dx,-0x6(%rbp)
mov    %cx,-0x8(%rbp)
mov    %ax,-0xa(%rbp)
lea    0xec9(%rip),%rdi
call   1030 <notify_pvcall@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<pvEnableSingleROI>:
push   %rax
lea    0xee8(%rip),%rdi
call   1030 <notify_pvcall@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [2 x i8] c"f\00"
define i32 @pvEnableSingleROI(i8 signext %0, i16 signext %1, i16 signext %2, i16 signext %3, i16 signext %4) {
%6 = alloca i8
%7 = alloca i16
%8 = alloca i16
%9 = alloca i16
%10 = alloca i16
store i8 %0, i8* %6
store i16 %1, i16* %7
store i16 %2, i16* %8
store i16 %3, i16* %9
store i16 %4, i16* %10
%11 = call i32 @notify_pvcall(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
ret i32 0
}

LLVM IR (-O2):
@.str = [2 x i8] c"f\00"
define i32 @pvEnableSingleROI(i8 signext %0, i16 signext %1, i16 signext %2, i16 signext %3, i16 signext %4) {
%6 = tail call i32 @notify_pvcall(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
ret i32 0
}
/* Variables and functions */
int rand();
int alea() {
  int min;
  int max;
  int a;
  int b;
  min = 0;
  max = 10;
  a = min;
  b = max + 1;
  return rand() % (b - a) + a;
}


x86 assembly (clang, -O0):
<alea>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x4(%rbp)
movl   $0xa,-0x8(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x10(%rbp)
mov    $0x0,%al
call   1030 <rand@plt>
mov    -0x10(%rbp),%ecx
sub    -0xc(%rbp),%ecx
cltd
idiv   %ecx
mov    %edx,%eax
add    -0xc(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<alea>:
push   %rax
xor    %eax,%eax
call   1030 <rand@plt>
cltq
imul   $0x2e8ba2e9,%rax,%rcx
mov    %rcx,%rdx
shr    $0x3f,%rdx
sar    $0x21,%rcx
add    %edx,%ecx
lea    (%rcx,%rcx,4),%edx
lea    (%rcx,%rdx,2),%ecx
sub    %ecx,%eax
pop    %rcx
ret

LLVM IR (-O0):
define i32 @alea() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
store i32 0, i32* %1
store i32 10, i32* %2
%5 = load i32, i32* %1
store i32 %5, i32* %3
%6 = load i32, i32* %2
%7 = add nsw i32 %6, 1
store i32 %7, i32* %4
%8 = call i32 (...) @rand()
%9 = load i32, i32* %4
%10 = load i32, i32* %3
%11 = sub nsw i32 %9, %10
%12 = srem i32 %8, %11
%13 = load i32, i32* %3
%14 = add nsw i32 %12, %13
ret i32 %14
}

LLVM IR (-O2):
define i32 @alea() {
%1 = tail call i32 (...) @rand()
%2 = srem i32 %1, 11
ret i32 %2
}
/* Variables and functions */
char *strrchr(char *, char);
char *extractTaskName(char *fullname) {
  char *c = strrchr(fullname, '/');
  if (c != NULL)
    return c + 1;
  return fullname;
}


x86 assembly (clang, -O0):
<extractTaskName>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    -0x10(%rbp),%rdi
mov    $0x2f,%esi
call   1030 <strrchr@plt>
mov    %rax,-0x18(%rbp)
cmpq   $0x0,-0x18(%rbp)
je     114a <extractTaskName+0x3a>
mov    -0x18(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    1152 <extractTaskName+0x42>
mov    -0x10(%rbp),%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<extractTaskName>:
push   %rbx
mov    %rdi,%rbx
mov    $0x2f,%esi
call   1030 <strrchr@plt>
lea    0x1(%rax),%rcx
test   %rax,%rax
cmove  %rbx,%rcx
mov    %rcx,%rax
pop    %rbx
ret

LLVM IR (-O0):
define i8* @extractTaskName(i8* %0) {
%2 = alloca i8*
%3 = alloca i8*
%4 = alloca i8*
store i8* %0, i8** %3
%5 = load i8*, i8** %3
%6 = call i8* @strrchr(i8* %5, i8 signext 47)
store i8* %6, i8** %4
%7 = load i8*, i8** %4
%8 = icmp ne i8* %7, null
br i1 %8, label %9, label %12
9: ; preds = %1
%10 = load i8*, i8** %4
%11 = getelementptr inbounds i8, i8* %10, i64 1
store i8* %11, i8** %2
br label %14
12: ; preds = %1
%13 = load i8*, i8** %3
store i8* %13, i8** %2
br label %14
14: ; preds = %12, %9
%15 = load i8*, i8** %2
ret i8* %15
}

LLVM IR (-O2):
define i8* @extractTaskName(i8* %0) {
%2 = tail call i8* @strrchr(i8* dereferenceable(1) %0, i8 signext 47)
%3 = icmp eq i8* %2, null
%4 = getelementptr inbounds i8, i8* %2, i64 1
%5 = select i1 %3, i8* %0, i8* %4
ret i8* %5
}
/* Variables and functions */
int __VERIFIER_nondet_int();
int /*<<< orphan*/ f(int, int);
int main() {
  int a = __VERIFIER_nondet_int();
  int b = __VERIFIER_nondet_int();
  if (a >= 0 && b >= 0) {
    f(a, b);
  }
  return 0;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0x0,-0x4(%rbp)
mov    $0x0,%al
call   1040 <__VERIFIER_nondet_int@plt>
mov    %eax,-0x8(%rbp)
mov    $0x0,%al
call   1040 <__VERIFIER_nondet_int@plt>
mov    %eax,-0xc(%rbp)
cmpl   $0x0,-0x8(%rbp)
jl     1162 <main+0x42>
cmpl   $0x0,-0xc(%rbp)
jl     1162 <main+0x42>
mov    -0x8(%rbp),%edi
mov    -0xc(%rbp),%esi
call   1030 <f@plt>
xor    %eax,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
push   %rbx
xor    %eax,%eax
call   1040 <__VERIFIER_nondet_int@plt>
mov    %eax,%ebx
xor    %eax,%eax
call   1040 <__VERIFIER_nondet_int@plt>
test   %ebx,%ebx
js     1142 <main+0x22>
test   %eax,%eax
js     1142 <main+0x22>
mov    %ebx,%edi
mov    %eax,%esi
call   1030 <f@plt>
xor    %eax,%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca i32
store i32 0, i32* %1
%4 = call i32 (...) @__VERIFIER_nondet_int()
store i32 %4, i32* %2
%5 = call i32 (...) @__VERIFIER_nondet_int()
store i32 %5, i32* %3
%6 = load i32, i32* %2
%7 = icmp sge i32 %6, 0
br i1 %7, label %8, label %15
8: ; preds = %0
%9 = load i32, i32* %3
%10 = icmp sge i32 %9, 0
br i1 %10, label %11, label %15
11: ; preds = %8
%12 = load i32, i32* %2
%13 = load i32, i32* %3
%14 = call i32 @f(i32 %12, i32 %13)
br label %15
15: ; preds = %11, %8, %0
ret i32 0
}

LLVM IR (-O2):
define i32 @main() {
%1 = tail call i32 (...) @__VERIFIER_nondet_int()
%2 = tail call i32 (...) @__VERIFIER_nondet_int()
%3 = icmp sgt i32 %1, -1
%4 = icmp sgt i32 %2, -1
%5 = select i1 %3, i1 %4, i1 false
br i1 %5, label %6, label %8
6: ; preds = %0
%7 = tail call i32 @f(i32 %1, i32 %2)
br label %8
8: ; preds = %6, %0
ret i32 0
}
/* Type definitions */
typedef int /*<<< orphan*/ uint32_t;

/* Variables and functions */
int /*<<< orphan*/ printf(char *);
uint32_t mach_reply_port() {
  printf(" .... Hello from mach_reply_port()!\n");
  return 0;
}


x86 assembly (clang, -O0):
<mach_reply_port>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <printf@plt>
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<mach_reply_port>:
push   %rax
lea    0xee8(%rip),%rdi
call   1030 <puts@plt>
xor    %eax,%eax
pop    %rcx
ret

LLVM IR (-O0):
@.str = [37 x i8] c" .... Hello from mach_reply_port()!\0A\00"
define i32 @mach_reply_port() {
%1 = call i32 @printf(i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str, i64 0, i64 0))
ret i32 0
}

LLVM IR (-O2):
@str = [36 x i8] c" .... Hello from mach_reply_port()!\00"
define i32 @mach_reply_port() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([36 x i8], [36 x i8]* @str, i64 0, i64 0))
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *, int, int, int, int);
void main() {
  int num1 = 895647, num2 = 3487, num3, num4;
  num3 = num1 % num2;
  num4 = num1 / num2;
  printf("Dividendo: %d\n"
         "Divisor: %d\n"
         "Quociente: %d\n"
         "Resto: %d\n",
         num1, num2, num4, num3);
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movl   $0xdaa9f,-0x4(%rbp)
movl   $0xd9f,-0x8(%rbp)
mov    -0x4(%rbp),%eax
cltd
idivl  -0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    -0x4(%rbp),%eax
cltd
idivl  -0x8(%rbp)
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%esi
mov    -0x8(%rbp),%edx
mov    -0x10(%rbp),%ecx
mov    -0xc(%rbp),%r8d
lea    0xeb2(%rip),%rdi
call   1030 <printf@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
lea    0xee9(%rip),%rdi
mov    $0xdaa9f,%esi
mov    $0xd9f,%edx
mov    $0x100,%ecx
mov    $0xb9f,%r8d
jmp    1030 <printf@plt>

LLVM IR (-O0):
@.str = [51 x i8] c"Dividendo: %d\0ADivisor: %d\0AQuociente: %d\0AResto: %d\0A\00"
define void @main() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
store i32 895647, i32* %1
store i32 3487, i32* %2
%5 = load i32, i32* %1
%6 = load i32, i32* %2
%7 = srem i32 %5, %6
store i32 %7, i32* %3
%8 = load i32, i32* %1
%9 = load i32, i32* %2
%10 = sdiv i32 %8, %9
store i32 %10, i32* %4
%11 = load i32, i32* %1
%12 = load i32, i32* %2
%13 = load i32, i32* %4
%14 = load i32, i32* %3
%15 = call i32 @printf(i8* getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0), i32 %11, i32 %12, i32 %13, i32 %14)
ret void
}

LLVM IR (-O2):
@.str = [51 x i8] c"Dividendo: %d\0ADivisor: %d\0AQuociente: %d\0AResto: %d\0A\00"
define void @main() {
%1 = tail call i32 @printf(i8* getelementptr inbounds ([51 x i8], [51 x i8]* @.str, i64 0, i64 0), i32 895647, i32 3487, i32 256, i32 2975)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *, ...);
void clar_print_init(int test_count, int suite_count, const char *suite_names) {
  (void)test_count;
  printf("Loaded %d suites: %s\n", (int)suite_count, suite_names);
  printf("Started (test status codes: OK='.' FAILURE='F' SKIPPED='S')\n");
}


x86 assembly (clang, -O0):
<clar_print_init>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %rdx,-0x10(%rbp)
mov    -0x8(%rbp),%esi
mov    -0x10(%rbp),%rdx
lea    0xed0(%rip),%rdi
mov    $0x0,%al
call   1030 <printf@plt>
lea    0xed8(%rip),%rdi
mov    $0x0,%al
call   1030 <printf@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<clar_print_init>:
push   %rax
lea    0xed8(%rip),%rdi
xor    %eax,%eax
call   1040 <printf@plt>
lea    0xee0(%rip),%rdi
pop    %rax
jmp    1030 <puts@plt>

LLVM IR (-O0):
@.str = [22 x i8] c"Loaded %d suites: %s\0A\00"
@.str.1 = [61 x i8] c"Started (test status codes: OK='.' FAILURE='F' SKIPPED='S')\0A\00"
define void @clar_print_init(i32 %0, i32 %1, i8* %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i8*
store i32 %0, i32* %4
store i32 %1, i32* %5
store i8* %2, i8** %6
%7 = load i32, i32* %4
%8 = load i32, i32* %5
%9 = load i8*, i8** %6
%10 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i64 0, i64 0), i32 %8, i8* %9)
%11 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([61 x i8], [61 x i8]* @.str.1, i64 0, i64 0))
ret void
}

LLVM IR (-O2):
@.str = [22 x i8] c"Loaded %d suites: %s\0A\00"
@str = [60 x i8] c"Started (test status codes: OK='.' FAILURE='F' SKIPPED='S')\00"
define void @clar_print_init(i32 %0, i32 %1, i8* %2) {
%4 = tail call i32 (i8*, ...) @printf(i8* dereferenceable(1) getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i64 0, i64 0), i32 %1, i8* %2)
%5 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([60 x i8], [60 x i8]* @str, i64 0, i64 0))
ret void
}
/* Type definitions */
typedef int uint8_t;
typedef int /*<<< orphan*/ int8_t;

/* Variables and functions */
int /*<<< orphan*/ hd44780_ll_instruction_write(int);
int8_t hd44780_entry_mode_set(uint8_t do_increment, uint8_t do_shift) {
  uint8_t data = 0x04;
  if (do_increment) {
    data = data | 0x02;
  }
  if (do_shift) {
    data = data | 0x01;
  }
  return (hd44780_ll_instruction_write(data));
}


x86 assembly (clang, -O0):
<hd44780_entry_mode_set>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
movl   $0x4,-0xc(%rbp)
cmpl   $0x0,-0x4(%rbp)
je     1138 <hd44780_entry_mode_set+0x28>
mov    -0xc(%rbp),%eax
or     $0x2,%eax
mov    %eax,-0xc(%rbp)
cmpl   $0x0,-0x8(%rbp)
je     114b <hd44780_entry_mode_set+0x3b>
mov    -0xc(%rbp),%eax
or     $0x1,%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%edi
call   1030 <hd44780_ll_instruction_write@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<hd44780_entry_mode_set>:
xor    %eax,%eax
test   %edi,%edi
setne  %al
xor    %ecx,%ecx
test   %esi,%esi
setne  %cl
lea    (%rcx,%rax,2),%edi
add    $0x4,%edi
jmp    1030 <hd44780_ll_instruction_write@plt>

LLVM IR (-O0):
define i32 @hd44780_entry_mode_set(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
store i32 4, i32* %5
%6 = load i32, i32* %3
%7 = icmp ne i32 %6, 0
br i1 %7, label %8, label %11
8: ; preds = %2
%9 = load i32, i32* %5
%10 = or i32 %9, 2
store i32 %10, i32* %5
br label %11
11: ; preds = %8, %2
%12 = load i32, i32* %4
%13 = icmp ne i32 %12, 0
br i1 %13, label %14, label %17
14: ; preds = %11
%15 = load i32, i32* %5
%16 = or i32 %15, 1
store i32 %16, i32* %5
br label %17
17: ; preds = %14, %11
%18 = load i32, i32* %5
%19 = call i32 @hd44780_ll_instruction_write(i32 %18)
ret i32 %19
}

LLVM IR (-O2):
define i32 @hd44780_entry_mode_set(i32 %0, i32 %1) {
%3 = icmp eq i32 %0, 0
%4 = select i1 %3, i32 4, i32 6
%5 = icmp ne i32 %1, 0
%6 = zext i1 %5 to i32
%7 = or i32 %4, %6
%8 = tail call i32 @hd44780_ll_instruction_write(i32 %7)
ret i32 %8
}
int wrapc_signbitl(long double r) { return 0; }


x86 assembly (clang, -O0):
<wrapc_signbitl>:
push   %rbp
mov    %rsp,%rbp
fldt   0x10(%rbp)
fstpt  -0x10(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<wrapc_signbitl>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @wrapc_signbitl(x86_fp80 %0) {
%2 = alloca x86_fp80
store x86_fp80 %0, x86_fp80* %2
ret i32 0
}

LLVM IR (-O2):
define i32 @wrapc_signbitl(x86_fp80 %0) {
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ handle_RETRACT(int /*<<< orphan*/);
int gen_RETRACT() { handle_RETRACT(0); }


x86 assembly (clang, -O0):
<gen_RETRACT>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
xor    %edi,%edi
call   1030 <handle_RETRACT@plt>
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gen_RETRACT>:
xor    %edi,%edi
jmp    1030 <handle_RETRACT@plt>

LLVM IR (-O0):
define i32 @gen_RETRACT() {
%1 = alloca i32
%2 = call i32 @handle_RETRACT(i32 0)
%3 = load i32, i32* %1
ret i32 %3
}

LLVM IR (-O2):
define i32 @gen_RETRACT() {
%1 = tail call i32 @handle_RETRACT(i32 0)
ret i32 undef
}
int buzzlex_isspace(char c) { return (c == ' ') || (c == '\t') || (c == '\r'); }


x86 assembly (clang, -O0):
<buzzlex_isspace>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x1(%rbp)
movsbl -0x1(%rbp),%ecx
mov    $0x1,%al
cmp    $0x20,%ecx
mov    %al,-0x2(%rbp)
je     113b <buzzlex_isspace+0x3b>
movsbl -0x1(%rbp),%ecx
mov    $0x1,%al
cmp    $0x9,%ecx
mov    %al,-0x2(%rbp)
je     113b <buzzlex_isspace+0x3b>
movsbl -0x1(%rbp),%eax
cmp    $0xd,%eax
sete   %al
mov    %al,-0x2(%rbp)
mov    -0x2(%rbp),%al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<buzzlex_isspace>:
mov    $0x1,%eax
cmp    $0x9,%dil
je     1111 <buzzlex_isspace+0x11>
cmp    $0x20,%dil
jne    1112 <buzzlex_isspace+0x12>
ret
xor    %eax,%eax
cmp    $0xd,%dil
sete   %al
ret

LLVM IR (-O0):
define i32 @buzzlex_isspace(i8 signext %0) {
%2 = alloca i8
store i8 %0, i8* %2
%3 = load i8, i8* %2
%4 = sext i8 %3 to i32
%5 = icmp eq i32 %4, 32
br i1 %5, label %14, label %6
6: ; preds = %1
%7 = load i8, i8* %2
%8 = sext i8 %7 to i32
%9 = icmp eq i32 %8, 9
br i1 %9, label %14, label %10
10: ; preds = %6
%11 = load i8, i8* %2
%12 = sext i8 %11 to i32
%13 = icmp eq i32 %12, 13
br label %14
14: ; preds = %10, %6, %1
%15 = phi i1 [ true, %6 ], [ true, %1 ], [ %13, %10 ]
%16 = zext i1 %15 to i32
ret i32 %16
}

LLVM IR (-O2):
define i32 @buzzlex_isspace(i8 signext %0) {
switch i8 %0, label %2 [
i8 32, label %5
i8 9, label %5
]
2: ; preds = %1
%3 = icmp eq i8 %0, 13
%4 = zext i1 %3 to i32
br label %5
5: ; preds = %1, %1, %2
%6 = phi i32 [ 1, %1 ], [ %4, %2 ], [ 1, %1 ]
ret i32 %6
}
/* Variables and functions */
int random();
int /*<<< orphan*/ srand(int /*<<< orphan*/);
int /*<<< orphan*/ time(int /*<<< orphan*/ *);
void randomize_region(unsigned char *ptr, size_t len) {
  size_t i;
  srand(time(NULL));
  for (i = 0; i < len; ++i) {
    ptr[i] = random() % 256;
  }
}


x86 assembly (clang, -O0):
<randomize_region>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
xor    %eax,%eax
mov    %eax,%edi
call   1040 <time@plt>
mov    %eax,%edi
call   1030 <srand@plt>
movq   $0x0,-0x18(%rbp)
mov    -0x18(%rbp),%rax
cmp    -0x10(%rbp),%rax
jae    1191 <randomize_region+0x61>
mov    $0x0,%al
call   1050 <random@plt>
mov    $0x100,%ecx
cltd
idiv   %ecx
mov    -0x8(%rbp),%rax
mov    -0x18(%rbp),%rcx
mov    %dl,(%rax,%rcx,1)
mov    -0x18(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x18(%rbp)
jmp    1158 <randomize_region+0x28>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<randomize_region>:
push   %r15
push   %r14
push   %rbx
mov    %rsi,%r15
mov    %rdi,%r14
xor    %edi,%edi
call   1040 <time@plt>
mov    %eax,%edi
call   1030 <srand@plt>
test   %r15,%r15
je     1164 <randomize_region+0x34>
xor    %ebx,%ebx
xor    %eax,%eax
call   1050 <random@plt>
mov    %al,(%r14,%rbx,1)
add    $0x1,%rbx
cmp    %rbx,%r15
jne    1150 <randomize_region+0x20>
pop    %rbx
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define void @randomize_region(i8* %0, i64 %1) {
%3 = alloca i8*
%4 = alloca i64
%5 = alloca i64
store i8* %0, i8** %3
store i64 %1, i64* %4
%6 = call i32 @time(i32* null)
%7 = call i32 @srand(i32 %6)
store i64 0, i64* %5
br label %8
8: ; preds = %19, %2
%9 = load i64, i64* %5
%10 = load i64, i64* %4
%11 = icmp ult i64 %9, %10
br i1 %11, label %12, label %22
12: ; preds = %8
%13 = call i32 (...) @random()
%14 = srem i32 %13, 256
%15 = trunc i32 %14 to i8
%16 = load i8*, i8** %3
%17 = load i64, i64* %5
%18 = getelementptr inbounds i8, i8* %16, i64 %17
store i8 %15, i8* %18
br label %19
19: ; preds = %12
%20 = load i64, i64* %5
%21 = add i64 %20, 1
store i64 %21, i64* %5
br label %8
22: ; preds = %8
ret void
}

LLVM IR (-O2):
define void @randomize_region(i8* nocapture writeonly %0, i64 %1) {
%3 = tail call i32 @time(i32* null)
%4 = tail call i32 @srand(i32 %3)
%5 = icmp eq i64 %1, 0
br i1 %5, label %13, label %6
6: ; preds = %2, %6
%7 = phi i64 [ %11, %6 ], [ 0, %2 ]
%8 = tail call i32 (...) @random()
%9 = trunc i32 %8 to i8
%10 = getelementptr inbounds i8, i8* %0, i64 %7
store i8 %9, i8* %10
%11 = add nuw i64 %7, 1
%12 = icmp eq i64 %11, %1
br i1 %12, label %13, label %6
13: ; preds = %6, %2
ret void
}
int analogRead(int pin) { return 0; }


x86 assembly (clang, -O0):
<analogRead>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<analogRead>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @analogRead(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
ret i32 0
}

LLVM IR (-O2):
define i32 @analogRead(i32 %0) {
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ perr(char *, char *);
scalar_t__ strcmp(char const *, char *);
scalar_t__ strtok(int /*<<< orphan*/, char *);
int noarg(const char *str, char *op) {
  if (strcmp(str, op))
    return 0;
  if (strtok(0, " "))
    perr("argument after '%s'", op);
  return 1;
}


x86 assembly (clang, -O0):
<noarg>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
call   1040 <strcmp@plt>
cmp    $0x0,%rax
je     1163 <noarg+0x33>
movl   $0x0,-0x4(%rbp)
jmp    1192 <noarg+0x62>
xor    %edi,%edi
lea    0xe94(%rip),%rsi
call   1050 <strtok@plt>
cmp    $0x0,%rax
je     118b <noarg+0x5b>
mov    -0x18(%rbp),%rsi
lea    0xe7c(%rip),%rdi
call   1030 <perr@plt>
movl   $0x1,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<noarg>:
push   %rbp
push   %rbx
push   %rax
mov    %rsi,%rbx
call   1040 <strcmp@plt>
xor    %ebp,%ebp
test   %rax,%rax
jne    1169 <noarg+0x39>
lea    0xeb7(%rip),%rsi
xor    %edi,%edi
call   1050 <strtok@plt>
mov    $0x1,%ebp
test   %rax,%rax
je     1169 <noarg+0x39>
lea    0xea1(%rip),%rdi
mov    %rbx,%rsi
call   1030 <perr@plt>
mov    %ebp,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
@.str = [2 x i8] c" \00"
@.str.1 = [20 x i8] c"argument after '%s'\00"
define i32 @noarg(i8* %0, i8* %1) {
%3 = alloca i32
%4 = alloca i8*
%5 = alloca i8*
store i8* %0, i8** %4
store i8* %1, i8** %5
%6 = load i8*, i8** %4
%7 = load i8*, i8** %5
%8 = call i64 @strcmp(i8* %6, i8* %7)
%9 = icmp ne i64 %8, 0
br i1 %9, label %10, label %11
10: ; preds = %2
store i32 0, i32* %3
br label %18
11: ; preds = %2
%12 = call i64 @strtok(i32 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
%13 = icmp ne i64 %12, 0
br i1 %13, label %14, label %17
14: ; preds = %11
%15 = load i8*, i8** %5
%16 = call i32 @perr(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str.1, i64 0, i64 0), i8* %15)
br label %17
17: ; preds = %14, %11
store i32 1, i32* %3
br label %18
18: ; preds = %17, %10
%19 = load i32, i32* %3
ret i32 %19
}

LLVM IR (-O2):
@.str = [2 x i8] c" \00"
@.str.1 = [20 x i8] c"argument after '%s'\00"
define i32 @noarg(i8* %0, i8* %1) {
%3 = tail call i64 @strcmp(i8* %0, i8* %1)
%4 = icmp eq i64 %3, 0
br i1 %4, label %5, label %10
5: ; preds = %2
%6 = tail call i64 @strtok(i32 0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0))
%7 = icmp eq i64 %6, 0
br i1 %7, label %10, label %8
8: ; preds = %5
%9 = tail call i32 @perr(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str.1, i64 0, i64 0), i8* %1)
br label %10
10: ; preds = %5, %8, %2
%11 = phi i32 [ 0, %2 ], [ 1, %8 ], [ 1, %5 ]
ret i32 %11
}
/* Variables and functions */
int /*<<< orphan*/ WARN_ON_ONCE(int);
unsigned int SCD_QUEUE_WRPTR(unsigned int chnl) {
  if (chnl < 20)
    return ((0x00000) + 0xa02c00) + 0x18 + chnl * 4;
  WARN_ON_ONCE(chnl >= 32);
  return ((0x00000) + 0xa02c00) + 0x284 + (chnl - 20) * 4;
}


x86 assembly (clang, -O0):
<SCD_QUEUE_WRPTR>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x8(%rbp)
cmpl   $0x14,-0x8(%rbp)
jae    1138 <SCD_QUEUE_WRPTR+0x28>
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
add    $0xa02c18,%eax
mov    %eax,-0x4(%rbp)
jmp    115a <SCD_QUEUE_WRPTR+0x4a>
cmpl   $0x20,-0x8(%rbp)
setae  %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <WARN_ON_ONCE@plt>
mov    -0x8(%rbp),%eax
sub    $0x14,%eax
shl    $0x2,%eax
add    $0xa02e84,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<SCD_QUEUE_WRPTR>:
push   %rbx
mov    %edi,%ebx
mov    $0xa02c18,%eax
cmp    $0x14,%edi
jb     1130 <SCD_QUEUE_WRPTR+0x20>
xor    %edi,%edi
cmp    $0x20,%ebx
setae  %dil
call   1030 <WARN_ON_ONCE@plt>
mov    $0xa02e34,%eax
lea    (%rax,%rbx,4),%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @SCD_QUEUE_WRPTR(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
%5 = icmp ult i32 %4, 20
br i1 %5, label %6, label %10
6: ; preds = %1
%7 = load i32, i32* %3
%8 = mul i32 %7, 4
%9 = add i32 10497048, %8
store i32 %9, i32* %2
br label %19
10: ; preds = %1
%11 = load i32, i32* %3
%12 = icmp uge i32 %11, 32
%13 = zext i1 %12 to i32
%14 = call i32 @WARN_ON_ONCE(i32 %13)
%15 = load i32, i32* %3
%16 = sub i32 %15, 20
%17 = mul i32 %16, 4
%18 = add i32 10497668, %17
store i32 %18, i32* %2
br label %19
19: ; preds = %10, %6
%20 = load i32, i32* %2
ret i32 %20
}

LLVM IR (-O2):
define i32 @SCD_QUEUE_WRPTR(i32 %0) {
%2 = icmp ult i32 %0, 20
br i1 %2, label %7, label %3
3: ; preds = %1
%4 = icmp ugt i32 %0, 31
%5 = zext i1 %4 to i32
%6 = tail call i32 @WARN_ON_ONCE(i32 %5)
br label %7
7: ; preds = %1, %3
%8 = phi i32 [ 10497588, %3 ], [ 10497048, %1 ]
%9 = shl i32 %0, 2
%10 = add i32 %9, %8
ret i32 %10
}
/* Type definitions */
typedef unsigned long volatile uint32_t;

/* Variables and functions */
void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) {
  ;
  (*((volatile unsigned long *)(ui32Base + 0x00000038))) &= ~(ui32IntFlags);
}


x86 assembly (clang, -O0):
<UARTIntDisable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x10(%rbp),%rdx
xor    $0xffffffffffffffff,%rdx
mov    -0x8(%rbp),%rax
mov    0x38(%rax),%rcx
and    %rdx,%rcx
mov    %rcx,0x38(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTIntDisable>:
mov    %rdi,-0x8(%rsp)
mov    %rsi,-0x10(%rsp)
mov    -0x10(%rsp),%rax
not    %rax
mov    -0x8(%rsp),%rcx
and    %rax,0x38(%rcx)
ret

LLVM IR (-O0):
define void @UARTIntDisable(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store volatile i64 %0, i64* %3
store volatile i64 %1, i64* %4
%5 = load volatile i64, i64* %4
%6 = xor i64 %5, -1
%7 = load volatile i64, i64* %3
%8 = add i64 %7, 56
%9 = inttoptr i64 %8 to i64*
%10 = load volatile i64, i64* %9
%11 = and i64 %10, %6
store volatile i64 %11, i64* %9
ret void
}

LLVM IR (-O2):
define void @UARTIntDisable(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store volatile i64 %0, i64* %3
store volatile i64 %1, i64* %4
%5 = load volatile i64, i64* %4
%6 = xor i64 %5, -1
%7 = load volatile i64, i64* %3
%8 = add i64 %7, 56
%9 = inttoptr i64 %8 to i64*
%10 = load volatile i64, i64* %9
%11 = and i64 %10, %6
store volatile i64 %11, i64* %9
ret void
}
/* Variables and functions */
int /*<<< orphan*/ max_heapify(int *, int, int);
void build_max_heap(int *nums, int numsSize) {
  for (int i = numsSize / 2; i >= 0; i--) {
    max_heapify(nums, numsSize, i);
  }
}


x86 assembly (clang, -O0):
<build_max_heap>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0xc(%rbp),%eax
mov    $0x2,%ecx
cltd
idiv   %ecx
mov    %eax,-0x10(%rbp)
cmpl   $0x0,-0x10(%rbp)
jl     1154 <build_max_heap+0x44>
mov    -0x8(%rbp),%rdi
mov    -0xc(%rbp),%esi
mov    -0x10(%rbp),%edx
call   1030 <max_heapify@plt>
mov    -0x10(%rbp),%eax
add    $0xffffffff,%eax
mov    %eax,-0x10(%rbp)
jmp    112d <build_max_heap+0x1d>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<build_max_heap>:
push   %rbp
push   %r14
push   %rbx
cmp    $0xffffffff,%esi
jl     1141 <build_max_heap+0x31>
mov    %esi,%ebx
mov    %rdi,%r14
mov    %esi,%ebp
shr    $0x1f,%ebp
add    %esi,%ebp
sar    %ebp
nopw   0x0(%rax,%rax,1)
mov    %r14,%rdi
mov    %ebx,%esi
mov    %ebp,%edx
call   1030 <max_heapify@plt>
add    $0xffffffff,%ebp
jb     1130 <build_max_heap+0x20>
pop    %rbx
pop    %r14
pop    %rbp
ret

LLVM IR (-O0):
define void @build_max_heap(i32* %0, i32 %1) {
%3 = alloca i32*
%4 = alloca i32
%5 = alloca i32
store i32* %0, i32** %3
store i32 %1, i32* %4
%6 = load i32, i32* %4
%7 = sdiv i32 %6, 2
store i32 %7, i32* %5
br label %8
8: ; preds = %16, %2
%9 = load i32, i32* %5
%10 = icmp sge i32 %9, 0
br i1 %10, label %11, label %19
11: ; preds = %8
%12 = load i32*, i32** %3
%13 = load i32, i32* %4
%14 = load i32, i32* %5
%15 = call i32 @max_heapify(i32* %12, i32 %13, i32 %14)
br label %16
16: ; preds = %11
%17 = load i32, i32* %5
%18 = add nsw i32 %17, -1
store i32 %18, i32* %5
br label %8
19: ; preds = %8
ret void
}

LLVM IR (-O2):
define void @build_max_heap(i32* %0, i32 %1) {
%3 = icmp sgt i32 %1, -2
br i1 %3, label %4, label %6
4: ; preds = %2
%5 = sdiv i32 %1, 2
br label %7
6: ; preds = %7, %2
ret void
7: ; preds = %4, %7
%8 = phi i32 [ %10, %7 ], [ %5, %4 ]
%9 = tail call i32 @max_heapify(i32* %0, i32 %1, i32 %8)
%10 = add nsw i32 %8, -1
%11 = icmp eq i32 %8, 0
br i1 %11, label %6, label %7
}
/* Variables and functions */
int /*<<< orphan*/ delay(int);
int /*<<< orphan*/ mbus_remote_register_write(int, int, int);
void reset_pmu_solar_short() {
  mbus_remote_register_write(
      0x6, 0x0E, ((1 << 10) | (1 << 9) | (0 << 8) | (1 << 4) | (0)));
  delay(100);
  mbus_remote_register_write(
      0x6, 0x0E, ((1 << 10) | (1 << 9) | (0 << 8) | (1 << 4) | (0)));
  delay(100);
  mbus_remote_register_write(
      0x6, 0x0E, ((1 << 10) | (0 << 9) | (0 << 8) | (1 << 4) | (0)));
  delay(100);
}


x86 assembly (clang, -O0):
<reset_pmu_solar_short>:
push   %rbp
mov    %rsp,%rbp
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x610,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
call   1030 <delay@plt>
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x610,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
call   1030 <delay@plt>
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x410,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
call   1030 <delay@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<reset_pmu_solar_short>:
push   %rax
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x610,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
call   1030 <delay@plt>
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x610,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
call   1030 <delay@plt>
mov    $0x6,%edi
mov    $0xe,%esi
mov    $0x410,%edx
call   1040 <mbus_remote_register_write@plt>
mov    $0x64,%edi
pop    %rax
jmp    1030 <delay@plt>

LLVM IR (-O0):
define void @reset_pmu_solar_short() {
%1 = call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1552)
%2 = call i32 @delay(i32 100)
%3 = call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1552)
%4 = call i32 @delay(i32 100)
%5 = call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1040)
%6 = call i32 @delay(i32 100)
ret void
}

LLVM IR (-O2):
define void @reset_pmu_solar_short() {
%1 = tail call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1552)
%2 = tail call i32 @delay(i32 100)
%3 = tail call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1552)
%4 = tail call i32 @delay(i32 100)
%5 = tail call i32 @mbus_remote_register_write(i32 6, i32 14, i32 1040)
%6 = tail call i32 @delay(i32 100)
ret void
}
/* Variables and functions */
unsigned int f19(unsigned int);
unsigned int f20(unsigned int a) { return f19(f19(a)); }


x86 assembly (clang, -O0):
<f20>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
call   1030 <f19@plt>
mov    %eax,%edi
call   1030 <f19@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<f20>:
push   %rax
call   1030 <f19@plt>
mov    %eax,%edi
pop    %rax
jmp    1030 <f19@plt>

LLVM IR (-O0):
define i32 @f20(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i32 @f19(i32 %3)
%5 = call i32 @f19(i32 %4)
ret i32 %5
}

LLVM IR (-O2):
define i32 @f20(i32 %0) {
%2 = tail call i32 @f19(i32 %0)
%3 = tail call i32 @f19(i32 %2)
ret i32 %3
}
/* Type definitions */
typedef int /*<<< orphan*/ FILE;

/* Variables and functions */
unsigned char *haval192_file(unsigned char *, int /*<<< orphan*/ *);
unsigned char *hash_file_haval192(unsigned char *out, FILE *fp) {
  return haval192_file(out, fp);
}


x86 assembly (clang, -O0):
<hash_file_haval192>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
call   1030 <haval192_file@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<hash_file_haval192>:
jmp    1030 <haval192_file@plt>

LLVM IR (-O0):
define i8* @hash_file_haval192(i8* %0, i32* %1) {
%3 = alloca i8*
%4 = alloca i32*
store i8* %0, i8** %3
store i32* %1, i32** %4
%5 = load i8*, i8** %3
%6 = load i32*, i32** %4
%7 = call i8* @haval192_file(i8* %5, i32* %6)
ret i8* %7
}

LLVM IR (-O2):
define i8* @hash_file_haval192(i8* %0, i32* %1) {
%3 = tail call i8* @haval192_file(i8* %0, i32* %1)
ret i8* %3
}
void gtk_action_set_accel_group() {}


x86 assembly (clang, -O0):
<gtk_action_set_accel_group>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gtk_action_set_accel_group>:
ret

LLVM IR (-O0):
define void @gtk_action_set_accel_group() {
ret void
}

LLVM IR (-O2):
define void @gtk_action_set_accel_group() {
ret void
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *, int);
void Check() {
  static int c = 0;
  printf("%d\t", c);
  c += 5;
}


x86 assembly (clang, -O0):
<Check>:
push   %rbp
mov    %rsp,%rbp
mov    0x2f12(%rip),%esi
lea    0xedf(%rip),%rdi
call   1030 <printf@plt>
mov    0x2f00(%rip),%eax
add    $0x5,%eax
mov    %eax,0x2ef7(%rip)
pop    %rbp
ret

x86 assembly (clang, -O2):
<Check>:
push   %rax
mov    0x2f15(%rip),%esi
lea    0xee2(%rip),%rdi
call   1030 <printf@plt>
addl   $0x5,0x2f02(%rip)
pop    %rax
ret

LLVM IR (-O0):
@Check.c = internal global i32 0
@.str = [4 x i8] c"%d\09\00"
define void @Check() {
%1 = load i32, i32* @Check.c
%2 = call i32 @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %1)
%3 = load i32, i32* @Check.c
%4 = add nsw i32 %3, 5
store i32 %4, i32* @Check.c
ret void
}

LLVM IR (-O2):
@Check.c = internal unnamed_addr global i32 0
@.str = [4 x i8] c"%d\09\00"
define void @Check() {
%1 = load i32, i32* @Check.c
%2 = tail call i32 @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %1)
%3 = load i32, i32* @Check.c
%4 = add nsw i32 %3, 5
store i32 %4, i32* @Check.c
ret void
}
INSTRUCTION(lf_itof_s) {}


x86 assembly (clang, -O0):
<INSTRUCTION>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<INSTRUCTION>:
ret

LLVM IR (-O0):
define i32 @INSTRUCTION(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %2
ret i32 %4
}

LLVM IR (-O2):
define i32 @INSTRUCTION(i32 %0) {
ret i32 undef
}
int minj(int i, int n_ann) {
  if (i < n_ann)
    return 0;
  return i - n_ann;
}


x86 assembly (clang, -O0):
<minj>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0x8(%rbp),%eax
cmp    -0xc(%rbp),%eax
jge    1122 <minj+0x22>
movl   $0x0,-0x4(%rbp)
jmp    112b <minj+0x2b>
mov    -0x8(%rbp),%eax
sub    -0xc(%rbp),%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<minj>:
xor    %eax,%eax
sub    %esi,%edi
cmovge %edi,%eax
ret

LLVM IR (-O0):
define i32 @minj(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
%6 = load i32, i32* %4
%7 = load i32, i32* %5
%8 = icmp slt i32 %6, %7
br i1 %8, label %9, label %10
9: ; preds = %2
store i32 0, i32* %3
br label %14
10: ; preds = %2
%11 = load i32, i32* %4
%12 = load i32, i32* %5
%13 = sub nsw i32 %11, %12
store i32 %13, i32* %3
br label %14
14: ; preds = %10, %9
%15 = load i32, i32* %3
ret i32 %15
}

LLVM IR (-O2):
define i32 @minj(i32 %0, i32 %1) {
%3 = icmp slt i32 %0, %1
%4 = sub nsw i32 %0, %1
%5 = select i1 %3, i32 0, i32 %4
ret i32 %5
}
unsigned int GPIOPinIntStatus(unsigned int baseAdd, unsigned int intLine,
                              unsigned int pinNumber) {
  unsigned int intStatus = 0;
  if ((0x0) == intLine) {
    intStatus = ((*((volatile unsigned int *)(baseAdd + (0x2C + (0 * 4))))) &
                 (1 << pinNumber));
  } else {
    intStatus = ((*((volatile unsigned int *)(baseAdd + (0x2C + (1 * 4))))) &
                 (1 << pinNumber));
  }
  return intStatus;
}


x86 assembly (clang, -O0):
<GPIOPinIntStatus>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
movl   $0x0,-0x10(%rbp)
xor    %eax,%eax
cmp    -0x8(%rbp),%eax
jne    113f <GPIOPinIntStatus+0x3f>
mov    -0x4(%rbp),%eax
add    $0x2c,%eax
mov    %eax,%eax
mov    (%rax),%eax
mov    -0xc(%rbp),%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
and    %ecx,%eax
mov    %eax,-0x10(%rbp)
jmp    115a <GPIOPinIntStatus+0x5a>
mov    -0x4(%rbp),%eax
add    $0x30,%eax
mov    %eax,%eax
mov    (%rax),%eax
mov    -0xc(%rbp),%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
and    %ecx,%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<GPIOPinIntStatus>:
mov    %edx,%ecx
xor    %edx,%edx
test   %esi,%esi
setne  %dl
mov    $0x1,%eax
shl    %cl,%eax
lea    (%rdi,%rdx,4),%ecx
add    $0x2c,%ecx
and    (%rcx),%eax
ret

LLVM IR (-O0):
define i32 @GPIOPinIntStatus(i32 %0, i32 %1, i32 %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
store i32 %2, i32* %6
store i32 0, i32* %7
%8 = load i32, i32* %5
%9 = icmp eq i32 0, %8
br i1 %9, label %10, label %19
10: ; preds = %3
%11 = load i32, i32* %4
%12 = add i32 %11, 44
%13 = zext i32 %12 to i64
%14 = inttoptr i64 %13 to i32*
%15 = load volatile i32, i32* %14
%16 = load i32, i32* %6
%17 = shl i32 1, %16
%18 = and i32 %15, %17
store i32 %18, i32* %7
br label %28
19: ; preds = %3
%20 = load i32, i32* %4
%21 = add i32 %20, 48
%22 = zext i32 %21 to i64
%23 = inttoptr i64 %22 to i32*
%24 = load volatile i32, i32* %23
%25 = load i32, i32* %6
%26 = shl i32 1, %25
%27 = and i32 %24, %26
store i32 %27, i32* %7
br label %28
28: ; preds = %19, %10
%29 = load i32, i32* %7
ret i32 %29
}

LLVM IR (-O2):
define i32 @GPIOPinIntStatus(i32 %0, i32 %1, i32 %2) {
%4 = icmp eq i32 %1, 0
%5 = select i1 %4, i32 44, i32 48
%6 = add i32 %5, %0
%7 = zext i32 %6 to i64
%8 = inttoptr i64 %7 to i32*
%9 = load volatile i32, i32* %8
%10 = shl nuw i32 1, %2
%11 = and i32 %9, %10
ret i32 %11
}
int ehnlc_ispunct(int c) {
  return ((c >= 33 && c <= 47) || (c >= 58 && c <= 64) ||
          (c >= 91 && c <= 96) || (c >= 123 && c <= 126))
             ? 4
             : 0;
}


x86 assembly (clang, -O0):
<ehnlc_ispunct>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
cmpl   $0x21,-0x4(%rbp)
jl     1120 <ehnlc_ispunct+0x20>
mov    $0x1,%al
cmpl   $0x2f,-0x4(%rbp)
mov    %al,-0x5(%rbp)
jle    1171 <ehnlc_ispunct+0x71>
cmpl   $0x3a,-0x4(%rbp)
jl     1139 <ehnlc_ispunct+0x39>
mov    $0x1,%al
cmpl   $0x40,-0x4(%rbp)
mov    %al,-0x5(%rbp)
jle    1171 <ehnlc_ispunct+0x71>
cmpl   $0x5b,-0x4(%rbp)
jl     1152 <ehnlc_ispunct+0x52>
mov    $0x1,%al
cmpl   $0x60,-0x4(%rbp)
mov    %al,-0x5(%rbp)
jle    1171 <ehnlc_ispunct+0x71>
xor    %eax,%eax
cmpl   $0x7b,-0x4(%rbp)
mov    %al,-0x6(%rbp)
jl     116b <ehnlc_ispunct+0x6b>
cmpl   $0x7e,-0x4(%rbp)
setle  %al
mov    %al,-0x6(%rbp)
mov    -0x6(%rbp),%al
mov    %al,-0x5(%rbp)
mov    -0x5(%rbp),%dl
xor    %eax,%eax
mov    $0x4,%ecx
test   $0x1,%dl
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ehnlc_ispunct>:
movd   %edi,%xmm0
pshufd $0x0,%xmm0,%xmm0
paddd  0xeef(%rip),%xmm0
pxor   0xef7(%rip),%xmm0
movdqa 0xeff(%rip),%xmm1
pcmpgtd %xmm0,%xmm1
movmskps %xmm1,%ecx
xor    %eax,%eax
test   %ecx,%ecx
setne  %al
shl    $0x2,%eax
ret

LLVM IR (-O0):
define i32 @ehnlc_ispunct(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = icmp sge i32 %3, 33
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load i32, i32* %2
%7 = icmp sle i32 %6, 47
br i1 %7, label %28, label %8
8: ; preds = %5, %1
%9 = load i32, i32* %2
%10 = icmp sge i32 %9, 58
br i1 %10, label %11, label %14
11: ; preds = %8
%12 = load i32, i32* %2
%13 = icmp sle i32 %12, 64
br i1 %13, label %28, label %14
14: ; preds = %11, %8
%15 = load i32, i32* %2
%16 = icmp sge i32 %15, 91
br i1 %16, label %17, label %20
17: ; preds = %14
%18 = load i32, i32* %2
%19 = icmp sle i32 %18, 96
br i1 %19, label %28, label %20
20: ; preds = %17, %14
%21 = load i32, i32* %2
%22 = icmp sge i32 %21, 123
br i1 %22, label %23, label %26
23: ; preds = %20
%24 = load i32, i32* %2
%25 = icmp sle i32 %24, 126
br label %26
26: ; preds = %23, %20
%27 = phi i1 [ false, %20 ], [ %25, %23 ]
br label %28
28: ; preds = %26, %17, %11, %5
%29 = phi i1 [ true, %17 ], [ true, %11 ], [ true, %5 ], [ %27, %26 ]
%30 = zext i1 %29 to i64
%31 = select i1 %29, i32 4, i32 0
ret i32 %31
}

LLVM IR (-O2):
define i32 @ehnlc_ispunct(i32 %0) {
%2 = insertelement <4 x i32> poison, i32 %0, i64 0
%3 = shufflevector <4 x i32> %2, <4 x i32> poison, <4 x i32> zeroinitializer
%4 = add <4 x i32> %3, <i32 -123, i32 -91, i32 -33, i32 -58>
%5 = icmp ult <4 x i32> %4, <i32 4, i32 6, i32 15, i32 7>
%6 = bitcast <4 x i1> %5 to i4
%7 = icmp eq i4 %6, 0
%8 = select i1 %7, i32 0, i32 4
ret i32 %8
}
__attribute__((always_)) int
__test_and_clear_bit(int nr, volatile unsigned long *addr) {
  int oldbit;
  __asm__("btrl %2,%1\n\tsbbl %0,%0"
          : "=r"(oldbit), "=m"((*(volatile long *)addr))
          : "Ir"(nr));
  return oldbit;
}


x86 assembly (clang, -O0):
<__test_and_clear_bit>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x10(%rbp),%rax
mov    -0x4(%rbp),%ecx
btr    %ecx,(%rax)
sbb    %eax,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<__test_and_clear_bit>:
btr    %edi,(%rsi)
sbb    %eax,%eax
ret

LLVM IR (-O0):
define i32 @__test_and_clear_bit(i32 %0, i64* %1) {
%3 = alloca i32
%4 = alloca i64*
%5 = alloca i32
store i32 %0, i32* %3
store i64* %1, i64** %4
%6 = load i64*, i64** %4
%7 = load i32, i32* %3
%8 = call i32 asm "btrl $2,$1\0A\09sbbl $0,$0", "=r,=*m,Ir,~{dirflag},~{fpsr},~{flags}"(i64* elementtype(i64) %6, i32 %7)
store i32 %8, i32* %5
%9 = load i32, i32* %5
ret i32 %9
}

LLVM IR (-O2):
define i32 @__test_and_clear_bit(i32 %0, i64* %1) {
%3 = tail call i32 asm "btrl $2,$1\0A\09sbbl $0,$0", "=r,=*m,Ir,~{dirflag},~{fpsr},~{flags}"(i64* elementtype(i64) %1, i32 %0)
ret i32 %3
}
/* Variables and functions */
scalar_t__ memmem2(char const *, int /*<<< orphan*/, char const *,
                   int /*<<< orphan*/, int);
int /*<<< orphan*/ strlen(char const *);
char *strcasestr2(const char *str, const char *search) {
  if (!(*search))
    return (char *)str;
  return (char *)memmem2(str, strlen(str), search, strlen(search), (1 << 11));
}


x86 assembly (clang, -O0):
<strcasestr2>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    -0x18(%rbp),%rax
cmpb   $0x0,(%rax)
jne    114a <strcasestr2+0x2a>
mov    -0x10(%rbp),%rax
mov    %rax,-0x8(%rbp)
jmp    118b <strcasestr2+0x6b>
mov    -0x10(%rbp),%rax
mov    %rax,-0x30(%rbp)
mov    -0x10(%rbp),%rdi
call   1030 <strlen@plt>
mov    %eax,-0x24(%rbp)
mov    -0x18(%rbp),%rax
mov    %rax,-0x20(%rbp)
mov    -0x18(%rbp),%rdi
call   1030 <strlen@plt>
mov    -0x30(%rbp),%rdi
mov    -0x24(%rbp),%esi
mov    -0x20(%rbp),%rdx
mov    %eax,%ecx
mov    $0x800,%r8d
call   1040 <memmem2@plt>
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<strcasestr2>:
push   %rbp
push   %r14
push   %rbx
mov    %rdi,%rbx
cmpb   $0x0,(%rsi)
je     1159 <strcasestr2+0x39>
mov    %rsi,%r14
mov    %rbx,%rdi
call   1030 <strlen@plt>
mov    %eax,%ebp
mov    %r14,%rdi
call   1030 <strlen@plt>
mov    %rbx,%rdi
mov    %ebp,%esi
mov    %r14,%rdx
mov    %eax,%ecx
mov    $0x800,%r8d
call   1040 <memmem2@plt>
mov    %rax,%rbx
mov    %rbx,%rax
pop    %rbx
pop    %r14
pop    %rbp
ret

LLVM IR (-O0):
define i8* @strcasestr2(i8* %0, i8* %1) {
%3 = alloca i8*
%4 = alloca i8*
%5 = alloca i8*
store i8* %0, i8** %4
store i8* %1, i8** %5
%6 = load i8*, i8** %5
%7 = load i8, i8* %6
%8 = icmp ne i8 %7, 0
br i1 %8, label %11, label %9
9: ; preds = %2
%10 = load i8*, i8** %4
store i8* %10, i8** %3
br label %20
11: ; preds = %2
%12 = load i8*, i8** %4
%13 = load i8*, i8** %4
%14 = call i32 @strlen(i8* %13)
%15 = load i8*, i8** %5
%16 = load i8*, i8** %5
%17 = call i32 @strlen(i8* %16)
%18 = call i64 @memmem2(i8* %12, i32 %14, i8* %15, i32 %17, i32 2048)
%19 = inttoptr i64 %18 to i8*
store i8* %19, i8** %3
br label %20
20: ; preds = %11, %9
%21 = load i8*, i8** %3
ret i8* %21
}

LLVM IR (-O2):
define i8* @strcasestr2(i8* %0, i8* %1) {
%3 = load i8, i8* %1
%4 = icmp eq i8 %3, 0
br i1 %4, label %10, label %5
5: ; preds = %2
%6 = tail call i32 @strlen(i8* %0)
%7 = tail call i32 @strlen(i8* %1)
%8 = tail call i64 @memmem2(i8* %0, i32 %6, i8* %1, i32 %7, i32 2048)
%9 = inttoptr i64 %8 to i8*
br label %10
10: ; preds = %2, %5
%11 = phi i8* [ %9, %5 ], [ %0, %2 ]
ret i8* %11
}
/* Variables and functions */
scalar_t__ strncmp(char const *, char const *, int);
int check_option(const char *s_option, const char *s_short_opt,
                 const char *s_long_opt) {
  if (0 == strncmp(s_option, s_short_opt, 512) ||
      0 == strncmp(s_option, s_long_opt, 512))
    return 1;
  return 0;
}


x86 assembly (clang, -O0):
<check_option>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    %rdx,-0x20(%rbp)
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
mov    $0x200,%edx
call   1030 <strncmp@plt>
mov    %rax,%rcx
xor    %eax,%eax
cmp    %rcx,%rax
je     1164 <check_option+0x54>
mov    -0x10(%rbp),%rdi
mov    -0x20(%rbp),%rsi
mov    $0x200,%edx
call   1030 <strncmp@plt>
mov    %rax,%rcx
xor    %eax,%eax
cmp    %rcx,%rax
jne    1170 <check_option+0x60>
movl   $0x1,-0x4(%rbp)
jmp    1177 <check_option+0x67>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<check_option>:
push   %r14
push   %rbx
push   %rax
mov    %rdx,%r14
mov    %rdi,%rbx
mov    $0x200,%edx
call   1030 <strncmp@plt>
test   %rax,%rax
je     1146 <check_option+0x36>
mov    %rbx,%rdi
mov    %r14,%rsi
mov    $0x200,%edx
call   1030 <strncmp@plt>
mov    %rax,%rcx
xor    %eax,%eax
test   %rcx,%rcx
sete   %al
jmp    114b <check_option+0x3b>
mov    $0x1,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define i32 @check_option(i8* %0, i8* %1, i8* %2) {
%4 = alloca i32
%5 = alloca i8*
%6 = alloca i8*
%7 = alloca i8*
store i8* %0, i8** %5
store i8* %1, i8** %6
store i8* %2, i8** %7
%8 = load i8*, i8** %5
%9 = load i8*, i8** %6
%10 = call i64 @strncmp(i8* %8, i8* %9, i32 512)
%11 = icmp eq i64 0, %10
br i1 %11, label %17, label %12
12: ; preds = %3
%13 = load i8*, i8** %5
%14 = load i8*, i8** %7
%15 = call i64 @strncmp(i8* %13, i8* %14, i32 512)
%16 = icmp eq i64 0, %15
br i1 %16, label %17, label %18
17: ; preds = %12, %3
store i32 1, i32* %4
br label %19
18: ; preds = %12
store i32 0, i32* %4
br label %19
19: ; preds = %18, %17
%20 = load i32, i32* %4
ret i32 %20
}

LLVM IR (-O2):
define i32 @check_option(i8* %0, i8* %1, i8* %2) {
%4 = tail call i64 @strncmp(i8* %0, i8* %1, i32 512)
%5 = icmp eq i64 %4, 0
br i1 %5, label %10, label %6
6: ; preds = %3
%7 = tail call i64 @strncmp(i8* %0, i8* %2, i32 512)
%8 = icmp eq i64 %7, 0
%9 = zext i1 %8 to i32
br label %10
10: ; preds = %6, %3
%11 = phi i32 [ 1, %3 ], [ %9, %6 ]
ret i32 %11
}
/* Variables and functions */
int ERANGE;
int lookup_symbol_attrs(unsigned long addr, unsigned long *size,
                        unsigned long *offset, char *modname, char *name) {
  return -ERANGE;
}


x86 assembly (clang, -O0):
<lookup_symbol_attrs>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8,-0x28(%rbp)
xor    %eax,%eax
mov    0x2ec7(%rip),%rcx
sub    (%rcx),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<lookup_symbol_attrs>:
mov    0x2ee1(%rip),%rcx
xor    %eax,%eax
sub    (%rcx),%eax
ret

LLVM IR (-O0):
@ERANGE = global i32 0
define i32 @lookup_symbol_attrs(i64 %0, i64* %1, i64* %2, i8* %3, i8* %4) {
%6 = alloca i64
%7 = alloca i64*
%8 = alloca i64*
%9 = alloca i8*
%10 = alloca i8*
store i64 %0, i64* %6
store i64* %1, i64** %7
store i64* %2, i64** %8
store i8* %3, i8** %9
store i8* %4, i8** %10
%11 = load i32, i32* @ERANGE
%12 = sub nsw i32 0, %11
ret i32 %12
}

LLVM IR (-O2):
@ERANGE = global i32 0
define i32 @lookup_symbol_attrs(i64 %0, i64* nocapture readnone %1, i64* nocapture readnone %2, i8* nocapture readnone %3, i8* nocapture readnone %4) {
%6 = load i32, i32* @ERANGE
%7 = sub nsw i32 0, %6
ret i32 %7
}