int FenPiece(int nArg) {
  switch (nArg) {
  case 'K':
    return 0;
  case 'G':
  case 'A':
    return 1;
  case 'B':
  case 'E':
    return 2;
  case 'N':
  case 'H':
    return 3;
  case 'R':
    return 4;
  case 'C':
    return 5;
  case 'P':
    return 6;
  case 'k':
    return 7;
  case 'g':
  case 'a':
    return 8;
  case 'b':
  case 'e':
    return 9;
  case 'h':
  case 'n':
    return 10;
  case 'r':
    return 11;
  case 'c':
    return 12;
  case 'p':
    return 13;
  default:
    return 14;
  }
}


x86 assembly (clang, -O0):
<FenPiece>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
add    $0xffffffbf,%eax
mov    %eax,%ecx
mov    %rcx,-0x10(%rbp)
sub    $0x31,%eax
ja     11d8 <FenPiece+0xd8>
mov    -0x10(%rbp),%rax
lea    0xed9(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x0,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x1,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x2,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x3,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x4,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x5,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x6,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x7,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x8,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0x9,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0xa,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0xb,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0xc,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0xd,-0x4(%rbp)
jmp    11df <FenPiece+0xdf>
movl   $0xe,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<FenPiece>:
add    $0xffffffbf,%edi
mov    $0xe,%eax
cmp    $0x31,%edi
ja     111a <FenPiece+0x1a>
movslq %edi,%rax
lea    0xee9(%rip),%rcx
mov    (%rcx,%rax,4),%eax
ret

LLVM IR (-O0):
define i32 @FenPiece(i32 %0) {
%2 = alloca i32
%3 = alloca i32
store i32 %0, i32* %3
%4 = load i32, i32* %3
switch i32 %4, label %19 [
i32 75, label %5
i32 71, label %6
i32 65, label %6
i32 66, label %7
i32 69, label %7
i32 78, label %8
i32 72, label %8
i32 82, label %9
i32 67, label %10
i32 80, label %11
i32 107, label %12
i32 103, label %13
i32 97, label %13
i32 98, label %14
i32 101, label %14
i32 104, label %15
i32 110, label %15
i32 114, label %16
i32 99, label %17
i32 112, label %18
]
5: ; preds = %1
store i32 0, i32* %2
br label %20
6: ; preds = %1, %1
store i32 1, i32* %2
br label %20
7: ; preds = %1, %1
store i32 2, i32* %2
br label %20
8: ; preds = %1, %1
store i32 3, i32* %2
br label %20
9: ; preds = %1
store i32 4, i32* %2
br label %20
10: ; preds = %1
store i32 5, i32* %2
br label %20
11: ; preds = %1
store i32 6, i32* %2
br label %20
12: ; preds = %1
store i32 7, i32* %2
br label %20
13: ; preds = %1, %1
store i32 8, i32* %2
br label %20
14: ; preds = %1, %1
store i32 9, i32* %2
br label %20
15: ; preds = %1, %1
store i32 10, i32* %2
br label %20
16: ; preds = %1
store i32 11, i32* %2
br label %20
17: ; preds = %1
store i32 12, i32* %2
br label %20
18: ; preds = %1
store i32 13, i32* %2
br label %20
19: ; preds = %1
store i32 14, i32* %2
br label %20
20: ; preds = %19, %18, %17, %16, %15, %14, %13, %12, %11, %10, %9, %8, %7, %6, %5
%21 = load i32, i32* %2
ret i32 %21
}

LLVM IR (-O2):
@switch.table.FenPiece = [50 x i32] [i32 1, i32 2, i32 5, i32 14, i32 2, i32 14, i32 1, i32 3, i32 14, i32 14, i32 0, i32 14, i32 14, i32 3, i32 14, i32 6, i32 14, i32 4, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 8, i32 9, i32 12, i32 14, i32 9, i32 14, i32 8, i32 10, i32 14, i32 14, i32 7, i32 14, i32 14, i32 10, i32 14, i32 13, i32 14, i32 11]
define i32 @FenPiece(i32 %0) {
%2 = add i32 %0, -65
%3 = icmp ult i32 %2, 50
br i1 %3, label %4, label %8
4: ; preds = %1
%5 = sext i32 %2 to i64
%6 = getelementptr inbounds [50 x i32], [50 x i32]* @switch.table.FenPiece, i64 0, i64 %5
%7 = load i32, i32* %6
br label %8
8: ; preds = %1, %4
%9 = phi i32 [ %7, %4 ], [ 14, %1 ]
ret i32 %9
}