#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
void EPIPSRAMConfigRegRead(uint32_t ui32Base, uint32_t ui32CS) {
  uint32_t ui32Offset;
  ASSERT(ui32Base == 0x400D0000);
  ASSERT(ui32CS < 4);
  if (ui32CS < 2) {
    ui32Offset = 0x00000010 + (ui32CS << 2);
  } else {
    ui32Offset = 0x00000308 + ((ui32CS - 2) << 2);
  }
  (*((volatile uint32_t *)(ui32Base + ui32Offset))) |= 0x00020000;
}


x86 assembly (clang, -O0):
<EPIPSRAMConfigRegRead>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
cmpl   $0x400d0000,-0x4(%rbp)
sete   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x4,-0x8(%rbp)
setl   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x2,-0x8(%rbp)
jge    115e <EPIPSRAMConfigRegRead+0x4e>
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
add    $0x10,%eax
mov    %eax,-0xc(%rbp)
jmp    116f <EPIPSRAMConfigRegRead+0x5f>
mov    -0x8(%rbp),%eax
sub    $0x2,%eax
shl    $0x2,%eax
add    $0x308,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
add    -0xc(%rbp),%eax
cltq
mov    (%rax),%ecx
or     $0x20000,%ecx
mov    %ecx,(%rax)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<EPIPSRAMConfigRegRead>:
push   %r14
push   %rbx
push   %rax
mov    %esi,%ebx
mov    %edi,%r14d
xor    %edi,%edi
cmp    $0x400d0000,%r14d
sete   %dil
call   1030 <ASSERT@plt>
xor    %edi,%edi
cmp    $0x4,%ebx
setl   %dil
call   1030 <ASSERT@plt>
cmp    $0x2,%ebx
lea    0x10(%r14,%rbx,4),%eax
lea    0x300(%r14,%rbx,4),%ecx
cmovl  %eax,%ecx
movslq %ecx,%rax
orl    $0x20000,(%rax)
add    $0x8,%rsp
pop    %rbx
pop    %r14
ret

LLVM IR (-O0):
define void @EPIPSRAMConfigRegRead(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%6 = load i32, i32* %3
%7 = icmp eq i32 %6, 1074593792
%8 = zext i1 %7 to i32
%9 = call i32 @ASSERT(i32 %8)
%10 = load i32, i32* %4
%11 = icmp slt i32 %10, 4
%12 = zext i1 %11 to i32
%13 = call i32 @ASSERT(i32 %12)
%14 = load i32, i32* %4
%15 = icmp slt i32 %14, 2
br i1 %15, label %16, label %20
16: ; preds = %2
%17 = load i32, i32* %4
%18 = shl i32 %17, 2
%19 = add nsw i32 16, %18
store i32 %19, i32* %5
br label %25
20: ; preds = %2
%21 = load i32, i32* %4
%22 = sub nsw i32 %21, 2
%23 = shl i32 %22, 2
%24 = add nsw i32 776, %23
store i32 %24, i32* %5
br label %25
25: ; preds = %20, %16
%26 = load i32, i32* %3
%27 = load i32, i32* %5
%28 = add nsw i32 %26, %27
%29 = sext i32 %28 to i64
%30 = inttoptr i64 %29 to i32*
%31 = load volatile i32, i32* %30
%32 = or i32 %31, 131072
store volatile i32 %32, i32* %30
ret void
}

LLVM IR (-O2):
define void @EPIPSRAMConfigRegRead(i32 %0, i32 %1) {
%3 = icmp eq i32 %0, 1074593792
%4 = zext i1 %3 to i32
%5 = tail call i32 @ASSERT(i32 %4)
%6 = icmp slt i32 %1, 4
%7 = zext i1 %6 to i32
%8 = tail call i32 @ASSERT(i32 %7)
%9 = icmp slt i32 %1, 2
%10 = shl i32 %1, 2
%11 = select i1 %9, i32 16, i32 768
%12 = add i32 %10, %0
%13 = add i32 %12, %11
%14 = sext i32 %13 to i64
%15 = inttoptr i64 %14 to i32*
%16 = load volatile i32, i32* %15
%17 = or i32 %16, 131072
store volatile i32 %17, i32* %15
ret void
}