unsigned int ADC1Read(unsigned char channelNum) {
  unsigned int regVal;
  unsigned int ADC_Data;
  if (channelNum >= 8) {
    channelNum = 0;
  }
  (*(volatile unsigned long *)(0xE0060000 + 0x00)) &= 0xFFFFFF00;
  (*(volatile unsigned long *)(0xE0060000 + 0x00)) |=
      (1 << 24) | (1 << channelNum);
  while (1) {
    regVal = *(volatile unsigned long *)(0xE0060000 + 0x10 + 4 * channelNum);
    if (regVal & 0x80000000) {
      break;
    }
  }
  (*(volatile unsigned long *)(0xE0060000 + 0x00)) &= 0xF8FFFFFF;
  if (regVal & 0x40000000) {
    return (0);
  }
  ADC_Data = (regVal >> 6) & 0x3FF;
  return (ADC_Data);
}


x86 assembly (clang, -O0):
<ADC1Read>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x5(%rbp)
movzbl -0x5(%rbp),%eax
cmp    $0x8,%eax
jl     111b <ADC1Read+0x1b>
movb   $0x0,-0x5(%rbp)
mov    $0xe0060000,%eax
mov    (%rax),%rcx
movabs $0xffffff00,%rax
and    %rax,%rcx
mov    $0xe0060000,%eax
mov    %rcx,(%rax)
movzbl -0x5(%rbp),%ecx
mov    $0x1,%eax
shl    %cl,%eax
or     $0x1000000,%eax
cltq
mov    $0xe0060000,%ecx
mov    (%rcx),%rcx
or     %rax,%rcx
mov    $0xe0060000,%eax
mov    %rcx,(%rax)
movzbl -0x5(%rbp),%eax
shl    $0x2,%eax
add    $0xe0060010,%eax
mov    %eax,%eax
mov    (%rax),%rax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
and    $0x80000000,%eax
cmp    $0x0,%eax
je     1187 <ADC1Read+0x87>
jmp    118c <ADC1Read+0x8c>
jmp    115d <ADC1Read+0x5d>
mov    $0xe0060000,%eax
mov    (%rax),%rcx
movabs $0xf8ffffff,%rax
and    %rax,%rcx
mov    $0xe0060000,%eax
mov    %rcx,(%rax)
mov    -0xc(%rbp),%eax
and    $0x40000000,%eax
cmp    $0x0,%eax
je     11c6 <ADC1Read+0xc6>
movl   $0x0,-0x4(%rbp)
jmp    11da <ADC1Read+0xda>
mov    -0xc(%rbp),%eax
shr    $0x6,%eax
and    $0x3ff,%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADC1Read>:
mov    $0xe0060000,%eax
xor    %ecx,%ecx
cmp    $0x8,%dil
cmovb  %edi,%ecx
mov    $0xffffff00,%edx
and    %rdx,(%rax)
mov    $0x1000000,%edx
bts    %ecx,%edx
movslq %edx,%rdx
or     %rdx,(%rax)
mov    $0xe0060010,%esi
nopl   0x0(%rax)
mov    (%rsi,%rcx,4),%rdx
test   $0x80000000,%edx
je     1130 <ADC1Read+0x30>
mov    $0xf8ffffff,%ecx
and    %rcx,(%rax)
mov    %edx,%ecx
shr    $0x6,%ecx
and    $0x3ff,%ecx
xor    %eax,%eax
test   $0x40000000,%edx
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @ADC1Read(i8 zeroext %0) {
%2 = alloca i32
%3 = alloca i8
%4 = alloca i32
%5 = alloca i32
store i8 %0, i8* %3
%6 = load i8, i8* %3
%7 = zext i8 %6 to i32
%8 = icmp sge i32 %7, 8
br i1 %8, label %9, label %10
9: ; preds = %1
store i8 0, i8* %3
br label %10
10: ; preds = %9, %1
%11 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%12 = and i64 %11, 4294967040
store volatile i64 %12, i64* inttoptr (i64 3758489600 to i64*)
%13 = load i8, i8* %3
%14 = zext i8 %13 to i32
%15 = shl i32 1, %14
%16 = or i32 16777216, %15
%17 = sext i32 %16 to i64
%18 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%19 = or i64 %18, %17
store volatile i64 %19, i64* inttoptr (i64 3758489600 to i64*)
br label %20
20: ; preds = %10, %33
%21 = load i8, i8* %3
%22 = zext i8 %21 to i32
%23 = mul nsw i32 4, %22
%24 = add i32 -536477680, %23
%25 = zext i32 %24 to i64
%26 = inttoptr i64 %25 to i64*
%27 = load volatile i64, i64* %26
%28 = trunc i64 %27 to i32
store i32 %28, i32* %4
%29 = load i32, i32* %4
%30 = and i32 %29, -2147483648
%31 = icmp ne i32 %30, 0
br i1 %31, label %32, label %33
32: ; preds = %20
br label %34
33: ; preds = %20
br label %20
34: ; preds = %32
%35 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%36 = and i64 %35, 4177526783
store volatile i64 %36, i64* inttoptr (i64 3758489600 to i64*)
%37 = load i32, i32* %4
%38 = and i32 %37, 1073741824
%39 = icmp ne i32 %38, 0
br i1 %39, label %40, label %41
40: ; preds = %34
store i32 0, i32* %2
br label %46
41: ; preds = %34
%42 = load i32, i32* %4
%43 = lshr i32 %42, 6
%44 = and i32 %43, 1023
store i32 %44, i32* %5
%45 = load i32, i32* %5
store i32 %45, i32* %2
br label %46
46: ; preds = %41, %40
%47 = load i32, i32* %2
ret i32 %47
}

LLVM IR (-O2):
define i32 @ADC1Read(i8 zeroext %0) {
%2 = icmp ugt i8 %0, 7
%3 = select i1 %2, i8 0, i8 %0
%4 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%5 = and i64 %4, 4294967040
store volatile i64 %5, i64* inttoptr (i64 3758489600 to i64*)
%6 = zext i8 %3 to i32
%7 = shl nuw nsw i32 1, %6
%8 = or i32 %7, 16777216
%9 = sext i32 %8 to i64
%10 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%11 = or i64 %10, %9
store volatile i64 %11, i64* inttoptr (i64 3758489600 to i64*)
%12 = shl nuw nsw i32 %6, 2
%13 = add nuw nsw i32 %12, -536477680
%14 = zext i32 %13 to i64
%15 = inttoptr i64 %14 to i64*
br label %16
16: ; preds = %16, %1
%17 = load volatile i64, i64* %15
%18 = and i64 %17, 2147483648
%19 = icmp eq i64 %18, 0
br i1 %19, label %16, label %20
20: ; preds = %16
%21 = trunc i64 %17 to i32
%22 = load volatile i64, i64* inttoptr (i64 3758489600 to i64*)
%23 = and i64 %22, 4177526783
store volatile i64 %23, i64* inttoptr (i64 3758489600 to i64*)
%24 = and i32 %21, 1073741824
%25 = icmp eq i32 %24, 0
%26 = lshr i32 %21, 6
%27 = and i32 %26, 1023
%28 = select i1 %25, i32 %27, i32 0
ret i32 %28
}