unsigned char cst_short_to_ulaw(short sample) {
  static const int exp_lut[256] = {
      0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,
      4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
      5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
  int sign, exponent, mantissa;
  unsigned char ulawbyte;
  sign = (sample >> 8) & 0x80;
  if (sign != 0)
    sample = -sample;
  if (sample > 32635)
    sample = 32635;
  sample = sample + 0x84;
  exponent = exp_lut[(sample >> 7) & 0xFF];
  mantissa = (sample >> (exponent + 3)) & 0x0F;
  ulawbyte = ~(sign | (exponent << 4) | mantissa);
  if (ulawbyte == 0)
    ulawbyte = 0x02;
  return ulawbyte;
}


x86 assembly (clang, -O0):
<cst_short_to_ulaw>:
push   %rbp
mov    %rsp,%rbp
mov    %di,%ax
mov    %ax,-0x2(%rbp)
movswl -0x2(%rbp),%eax
sar    $0x8,%eax
and    $0x80,%eax
mov    %eax,-0x8(%rbp)
cmpl   $0x0,-0x8(%rbp)
je     1130 <cst_short_to_ulaw+0x30>
movswl -0x2(%rbp),%ecx
xor    %eax,%eax
sub    %ecx,%eax
mov    %ax,-0x2(%rbp)
movswl -0x2(%rbp),%eax
cmp    $0x7f7b,%eax
jle    1145 <cst_short_to_ulaw+0x45>
movw   $0x7f7b,-0x2(%rbp)
movswl -0x2(%rbp),%eax
add    $0x84,%eax
mov    %ax,-0x2(%rbp)
movswl -0x2(%rbp),%eax
sar    $0x7,%eax
and    $0xff,%eax
movslq %eax,%rcx
lea    0xe98(%rip),%rax
mov    (%rax,%rcx,4),%eax
mov    %eax,-0xc(%rbp)
movswl -0x2(%rbp),%eax
mov    -0xc(%rbp),%ecx
add    $0x3,%ecx
sar    %cl,%eax
and    $0xf,%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    -0xc(%rbp),%ecx
shl    $0x4,%ecx
or     %ecx,%eax
or     -0x10(%rbp),%eax
xor    $0xffffffff,%eax
mov    %al,-0x11(%rbp)
movzbl -0x11(%rbp),%eax
cmp    $0x0,%eax
jne    11a5 <cst_short_to_ulaw+0xa5>
movb   $0x2,-0x11(%rbp)
movzbl -0x11(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<cst_short_to_ulaw>:
mov    %edi,%eax
shr    $0x8,%eax
and    $0x80,%eax
mov    %edi,%ecx
neg    %ecx
test   %eax,%eax
cmove  %edi,%ecx
movswl %cx,%edx
cmp    $0x7f7b,%edx
mov    $0x7f7b,%edx
cmovl  %ecx,%edx
add    $0x84,%edx
movswl %dx,%edx
mov    %edx,%ecx
shr    $0x7,%ecx
movzbl %cl,%ecx
lea    0xec4(%rip),%rsi
mov    (%rsi,%rcx,4),%esi
lea    0x3(%rsi),%ecx
sar    %cl,%edx
and    $0xf,%edx
shl    $0x4,%esi
or     %eax,%esi
or     %edx,%esi
cmp    $0xff,%sil
not    %sil
movzbl %sil,%ecx
mov    $0x2,%eax
cmovne %ecx,%eax
ret

LLVM IR (-O0):
@cst_short_to_ulaw.exp_lut = internal constant [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @cst_short_to_ulaw(i16 signext %0) {
%2 = alloca i16
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i8
store i16 %0, i16* %2
%7 = load i16, i16* %2
%8 = sext i16 %7 to i32
%9 = ashr i32 %8, 8
%10 = and i32 %9, 128
store i32 %10, i32* %3
%11 = load i32, i32* %3
%12 = icmp ne i32 %11, 0
br i1 %12, label %13, label %18
13: ; preds = %1
%14 = load i16, i16* %2
%15 = sext i16 %14 to i32
%16 = sub nsw i32 0, %15
%17 = trunc i32 %16 to i16
store i16 %17, i16* %2
br label %18
18: ; preds = %13, %1
%19 = load i16, i16* %2
%20 = sext i16 %19 to i32
%21 = icmp sgt i32 %20, 32635
br i1 %21, label %22, label %23
22: ; preds = %18
store i16 32635, i16* %2
br label %23
23: ; preds = %22, %18
%24 = load i16, i16* %2
%25 = sext i16 %24 to i32
%26 = add nsw i32 %25, 132
%27 = trunc i32 %26 to i16
store i16 %27, i16* %2
%28 = load i16, i16* %2
%29 = sext i16 %28 to i32
%30 = ashr i32 %29, 7
%31 = and i32 %30, 255
%32 = sext i32 %31 to i64
%33 = getelementptr inbounds [256 x i32], [256 x i32]* @cst_short_to_ulaw.exp_lut, i64 0, i64 %32
%34 = load i32, i32* %33
store i32 %34, i32* %4
%35 = load i16, i16* %2
%36 = sext i16 %35 to i32
%37 = load i32, i32* %4
%38 = add nsw i32 %37, 3
%39 = ashr i32 %36, %38
%40 = and i32 %39, 15
store i32 %40, i32* %5
%41 = load i32, i32* %3
%42 = load i32, i32* %4
%43 = shl i32 %42, 4
%44 = or i32 %41, %43
%45 = load i32, i32* %5
%46 = or i32 %44, %45
%47 = xor i32 %46, -1
%48 = trunc i32 %47 to i8
store i8 %48, i8* %6
%49 = load i8, i8* %6
%50 = zext i8 %49 to i32
%51 = icmp eq i32 %50, 0
br i1 %51, label %52, label %53
52: ; preds = %23
store i8 2, i8* %6
br label %53
53: ; preds = %52, %23
%54 = load i8, i8* %6
ret i8 %54
}

LLVM IR (-O2):
@cst_short_to_ulaw.exp_lut = internal unnamed_addr constant [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @cst_short_to_ulaw(i16 signext %0) {
%2 = lshr i16 %0, 8
%3 = and i16 %2, 128
%4 = icmp eq i16 %3, 0
%5 = sub i16 0, %0
%6 = select i1 %4, i16 %0, i16 %5
%7 = zext i16 %3 to i32
%8 = icmp slt i16 %6, 32635
%9 = select i1 %8, i16 %6, i16 32635
%10 = add nsw i16 %9, 132
%11 = sext i16 %10 to i32
%12 = lshr i32 %11, 7
%13 = and i32 %12, 255
%14 = zext i32 %13 to i64
%15 = getelementptr inbounds [256 x i32], [256 x i32]* @cst_short_to_ulaw.exp_lut, i64 0, i64 %14
%16 = load i32, i32* %15
%17 = add nsw i32 %16, 3
%18 = ashr i32 %11, %17
%19 = and i32 %18, 15
%20 = shl i32 %16, 4
%21 = or i32 %20, %7
%22 = or i32 %21, %19
%23 = trunc i32 %22 to i8
%24 = xor i8 %23, -1
%25 = icmp eq i8 %23, -1
%26 = select i1 %25, i8 2, i8 %24
ret i8 %26
}