void UART0ModuleClkConfig(void) {
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) |= (0x2u);
  while ((0x2u) != ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) &
                    (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) |= (0x2u);
  while ((0x2u) != ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) &
                    (0x00000003u)))
    ;
  while (((0x0u) << (0x00000010u)) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) &
          (0x00030000u)))
    ;
  while (((0x0u) << (0x00000010u)) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) &
          (0x00030000u)))
    ;
  while ((0x00000010u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) &
          (0x00000010u)))
    ;
  while ((0x00000010u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) &
          (0x00000010u)))
    ;
  while ((0x00000008u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) &
          (0x00000008u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x4)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x4)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x0)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x0)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x18)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x18)))) &
          (0x00000003u)))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0xb4)))) |= (0x2u);
  while ((0x2u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0xb4)))) &
          (0x00000003u)))
    ;
  while (((0x0u) << (0x00000010u)) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x4)))) &
          (0x00030000u)))
    ;
  while ((0x00000008u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x18)))) &
          (0x00000008u)))
    ;
  while (((0x0u) << (0x00000010u)) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0xc)))) &
          (0x00030000u)))
    ;
  while ((0x00000004u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x0)))) &
          (0x00000004u)))
    ;
  while ((0x00000004u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0xcc)))) &
          (0x00000004u)))
    ;
  while ((0x00001000u) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0x0)))) &
          (0x00001000u)))
    ;
  while (((0x0u) << (0x00000010u)) !=
         ((*((volatile unsigned int *)(((0x44E00000) + 0x400) + (0xb4)))) &
          (0x00030000u)))
    ;
}


x86 assembly (clang, -O0):
<UART0ModuleClkConfig>:
push   %rbp
mov    %rsp,%rbp
mov    $0x44e000e0,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e000e0,%eax
mov    %ecx,(%rax)
mov    $0x44e000e0,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     1131 <UART0ModuleClkConfig+0x31>
jmp    1115 <UART0ModuleClkConfig+0x15>
mov    $0x44e000dc,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e000dc,%eax
mov    %ecx,(%rax)
mov    $0x44e000dc,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     115e <UART0ModuleClkConfig+0x5e>
jmp    1142 <UART0ModuleClkConfig+0x42>
mov    $0x44e0000c,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e0000c,%eax
mov    %ecx,(%rax)
mov    $0x44e0000c,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     118b <UART0ModuleClkConfig+0x8b>
jmp    116f <UART0ModuleClkConfig+0x6f>
mov    $0x44e0012c,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e0012c,%eax
mov    %ecx,(%rax)
mov    $0x44e0012c,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     11b8 <UART0ModuleClkConfig+0xb8>
jmp    119c <UART0ModuleClkConfig+0x9c>
mov    $0x44e00004,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00004,%eax
mov    %ecx,(%rax)
mov    $0x44e00004,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     11e5 <UART0ModuleClkConfig+0xe5>
jmp    11c9 <UART0ModuleClkConfig+0xc9>
jmp    11ea <UART0ModuleClkConfig+0xea>
mov    $0x44e000e0,%eax
mov    (%rax),%ecx
and    $0x30000,%ecx
xor    %eax,%eax
cmp    %ecx,%eax
je     1206 <UART0ModuleClkConfig+0x106>
jmp    11ea <UART0ModuleClkConfig+0xea>
jmp    120b <UART0ModuleClkConfig+0x10b>
mov    $0x44e000dc,%eax
mov    (%rax),%ecx
and    $0x30000,%ecx
xor    %eax,%eax
cmp    %ecx,%eax
je     1227 <UART0ModuleClkConfig+0x127>
jmp    120b <UART0ModuleClkConfig+0x10b>
jmp    122c <UART0ModuleClkConfig+0x12c>
mov    $0x44e0000c,%eax
mov    (%rax),%ecx
and    $0x10,%ecx
mov    $0x10,%eax
cmp    %ecx,%eax
je     1248 <UART0ModuleClkConfig+0x148>
jmp    122c <UART0ModuleClkConfig+0x12c>
jmp    124d <UART0ModuleClkConfig+0x14d>
mov    $0x44e0012c,%eax
mov    (%rax),%ecx
and    $0x10,%ecx
mov    $0x10,%eax
cmp    %ecx,%eax
je     1269 <UART0ModuleClkConfig+0x169>
jmp    124d <UART0ModuleClkConfig+0x14d>
jmp    126e <UART0ModuleClkConfig+0x16e>
mov    $0x44e00004,%eax
mov    (%rax),%ecx
and    $0x8,%ecx
mov    $0x8,%eax
cmp    %ecx,%eax
je     128a <UART0ModuleClkConfig+0x18a>
jmp    126e <UART0ModuleClkConfig+0x16e>
mov    $0x44e00404,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00404,%eax
mov    %ecx,(%rax)
mov    $0x44e00404,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     12b7 <UART0ModuleClkConfig+0x1b7>
jmp    129b <UART0ModuleClkConfig+0x19b>
mov    $0x44e00400,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00400,%eax
mov    %ecx,(%rax)
mov    $0x44e00400,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     12e4 <UART0ModuleClkConfig+0x1e4>
jmp    12c8 <UART0ModuleClkConfig+0x1c8>
mov    $0x44e00418,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e00418,%eax
mov    %ecx,(%rax)
mov    $0x44e00418,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     1311 <UART0ModuleClkConfig+0x211>
jmp    12f5 <UART0ModuleClkConfig+0x1f5>
mov    $0x44e004b4,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e004b4,%eax
mov    %ecx,(%rax)
mov    $0x44e004b4,%eax
mov    (%rax),%ecx
and    $0x3,%ecx
mov    $0x2,%eax
cmp    %ecx,%eax
je     133e <UART0ModuleClkConfig+0x23e>
jmp    1322 <UART0ModuleClkConfig+0x222>
jmp    1343 <UART0ModuleClkConfig+0x243>
mov    $0x44e00404,%eax
mov    (%rax),%ecx
and    $0x30000,%ecx
xor    %eax,%eax
cmp    %ecx,%eax
je     135f <UART0ModuleClkConfig+0x25f>
jmp    1343 <UART0ModuleClkConfig+0x243>
jmp    1364 <UART0ModuleClkConfig+0x264>
mov    $0x44e00418,%eax
mov    (%rax),%ecx
and    $0x8,%ecx
mov    $0x8,%eax
cmp    %ecx,%eax
je     1380 <UART0ModuleClkConfig+0x280>
jmp    1364 <UART0ModuleClkConfig+0x264>
jmp    1385 <UART0ModuleClkConfig+0x285>
mov    $0x44e0040c,%eax
mov    (%rax),%ecx
and    $0x30000,%ecx
xor    %eax,%eax
cmp    %ecx,%eax
je     13a1 <UART0ModuleClkConfig+0x2a1>
jmp    1385 <UART0ModuleClkConfig+0x285>
jmp    13a6 <UART0ModuleClkConfig+0x2a6>
mov    $0x44e00400,%eax
mov    (%rax),%ecx
and    $0x4,%ecx
mov    $0x4,%eax
cmp    %ecx,%eax
je     13c2 <UART0ModuleClkConfig+0x2c2>
jmp    13a6 <UART0ModuleClkConfig+0x2a6>
jmp    13c7 <UART0ModuleClkConfig+0x2c7>
mov    $0x44e004cc,%eax
mov    (%rax),%ecx
and    $0x4,%ecx
mov    $0x4,%eax
cmp    %ecx,%eax
je     13e3 <UART0ModuleClkConfig+0x2e3>
jmp    13c7 <UART0ModuleClkConfig+0x2c7>
jmp    13e8 <UART0ModuleClkConfig+0x2e8>
mov    $0x44e00400,%eax
mov    (%rax),%ecx
and    $0x1000,%ecx
mov    $0x1000,%eax
cmp    %ecx,%eax
je     1407 <UART0ModuleClkConfig+0x307>
jmp    13e8 <UART0ModuleClkConfig+0x2e8>
jmp    140c <UART0ModuleClkConfig+0x30c>
mov    $0x44e004b4,%eax
mov    (%rax),%ecx
and    $0x30000,%ecx
xor    %eax,%eax
cmp    %ecx,%eax
je     1428 <UART0ModuleClkConfig+0x328>
jmp    140c <UART0ModuleClkConfig+0x30c>
pop    %rbp
ret

x86 assembly (clang, -O2):
<UART0ModuleClkConfig>:
orl    $0x2,0x44e000e0
02
nopl   0x0(%rax,%rax,1)
mov    0x44e000e0,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1110 <UART0ModuleClkConfig+0x10>
orl    $0x2,0x44e000dc
02
nopw   0x0(%rax,%rax,1)
mov    0x44e000dc,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1130 <UART0ModuleClkConfig+0x30>
orl    $0x2,0x44e0000c
02
nopw   0x0(%rax,%rax,1)
mov    0x44e0000c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1150 <UART0ModuleClkConfig+0x50>
orl    $0x2,0x44e0012c
02
nopw   0x0(%rax,%rax,1)
mov    0x44e0012c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1170 <UART0ModuleClkConfig+0x70>
orl    $0x2,0x44e00004
02
nopw   0x0(%rax,%rax,1)
mov    0x44e00004,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1190 <UART0ModuleClkConfig+0x90>
nop
testl  $0x30000,0x44e000e0
jne    11a0 <UART0ModuleClkConfig+0xa0>
nopl   (%rax)
testl  $0x30000,0x44e000dc
jne    11b0 <UART0ModuleClkConfig+0xb0>
nopl   (%rax)
testl  $0x10,0x44e0000c
je     11c0 <UART0ModuleClkConfig+0xc0>
nopl   (%rax)
testl  $0x10,0x44e0012c
je     11d0 <UART0ModuleClkConfig+0xd0>
nopl   (%rax)
testl  $0x8,0x44e00004
je     11e0 <UART0ModuleClkConfig+0xe0>
orl    $0x2,0x44e00404
02
cs nopw 0x0(%rax,%rax,1)
nop
mov    0x44e00404,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1200 <UART0ModuleClkConfig+0x100>
orl    $0x2,0x44e00400
02
nopw   0x0(%rax,%rax,1)
mov    0x44e00400,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1220 <UART0ModuleClkConfig+0x120>
orl    $0x2,0x44e00418
02
nopw   0x0(%rax,%rax,1)
mov    0x44e00418,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1240 <UART0ModuleClkConfig+0x140>
orl    $0x2,0x44e004b4
02
nopw   0x0(%rax,%rax,1)
mov    0x44e004b4,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1260 <UART0ModuleClkConfig+0x160>
nop
testl  $0x30000,0x44e00404
jne    1270 <UART0ModuleClkConfig+0x170>
nopl   (%rax)
testl  $0x8,0x44e00418
je     1280 <UART0ModuleClkConfig+0x180>
nopl   (%rax)
testl  $0x30000,0x44e0040c
jne    1290 <UART0ModuleClkConfig+0x190>
nopl   (%rax)
testl  $0x4,0x44e00400
je     12a0 <UART0ModuleClkConfig+0x1a0>
nopl   (%rax)
testl  $0x4,0x44e004cc
je     12b0 <UART0ModuleClkConfig+0x1b0>
nopl   (%rax)
testl  $0x1000,0x44e00400
je     12c0 <UART0ModuleClkConfig+0x1c0>
nopl   (%rax)
testl  $0x30000,0x44e004b4
jne    12d0 <UART0ModuleClkConfig+0x1d0>
ret

LLVM IR (-O0):
define void @UART0ModuleClkConfig() {
%1 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%2 = or i32 %1, 2
store volatile i32 %2, i32* inttoptr (i64 1155530976 to i32*)
br label %3
3: ; preds = %7, %0
%4 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%5 = and i32 %4, 3
%6 = icmp ne i32 2, %5
br i1 %6, label %7, label %8
7: ; preds = %3
br label %3
8: ; preds = %3
%9 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%10 = or i32 %9, 2
store volatile i32 %10, i32* inttoptr (i64 1155530972 to i32*)
br label %11
11: ; preds = %15, %8
%12 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%13 = and i32 %12, 3
%14 = icmp ne i32 2, %13
br i1 %14, label %15, label %16
15: ; preds = %11
br label %11
16: ; preds = %11
%17 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%18 = or i32 %17, 2
store volatile i32 %18, i32* inttoptr (i64 1155530764 to i32*)
br label %19
19: ; preds = %23, %16
%20 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%21 = and i32 %20, 3
%22 = icmp ne i32 2, %21
br i1 %22, label %23, label %24
23: ; preds = %19
br label %19
24: ; preds = %19
%25 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%26 = or i32 %25, 2
store volatile i32 %26, i32* inttoptr (i64 1155531052 to i32*)
br label %27
27: ; preds = %31, %24
%28 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%29 = and i32 %28, 3
%30 = icmp ne i32 2, %29
br i1 %30, label %31, label %32
31: ; preds = %27
br label %27
32: ; preds = %27
%33 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%34 = or i32 %33, 2
store volatile i32 %34, i32* inttoptr (i64 1155530756 to i32*)
br label %35
35: ; preds = %39, %32
%36 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%37 = and i32 %36, 3
%38 = icmp ne i32 2, %37
br i1 %38, label %39, label %40
39: ; preds = %35
br label %35
40: ; preds = %35
br label %41
41: ; preds = %45, %40
%42 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%43 = and i32 %42, 196608
%44 = icmp ne i32 0, %43
br i1 %44, label %45, label %46
45: ; preds = %41
br label %41
46: ; preds = %41
br label %47
47: ; preds = %51, %46
%48 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%49 = and i32 %48, 196608
%50 = icmp ne i32 0, %49
br i1 %50, label %51, label %52
51: ; preds = %47
br label %47
52: ; preds = %47
br label %53
53: ; preds = %57, %52
%54 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%55 = and i32 %54, 16
%56 = icmp ne i32 16, %55
br i1 %56, label %57, label %58
57: ; preds = %53
br label %53
58: ; preds = %53
br label %59
59: ; preds = %63, %58
%60 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%61 = and i32 %60, 16
%62 = icmp ne i32 16, %61
br i1 %62, label %63, label %64
63: ; preds = %59
br label %59
64: ; preds = %59
br label %65
65: ; preds = %69, %64
%66 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%67 = and i32 %66, 8
%68 = icmp ne i32 8, %67
br i1 %68, label %69, label %70
69: ; preds = %65
br label %65
70: ; preds = %65
%71 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%72 = or i32 %71, 2
store volatile i32 %72, i32* inttoptr (i64 1155531780 to i32*)
br label %73
73: ; preds = %77, %70
%74 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%75 = and i32 %74, 3
%76 = icmp ne i32 2, %75
br i1 %76, label %77, label %78
77: ; preds = %73
br label %73
78: ; preds = %73
%79 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%80 = or i32 %79, 2
store volatile i32 %80, i32* inttoptr (i64 1155531776 to i32*)
br label %81
81: ; preds = %85, %78
%82 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%83 = and i32 %82, 3
%84 = icmp ne i32 2, %83
br i1 %84, label %85, label %86
85: ; preds = %81
br label %81
86: ; preds = %81
%87 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%88 = or i32 %87, 2
store volatile i32 %88, i32* inttoptr (i64 1155531800 to i32*)
br label %89
89: ; preds = %93, %86
%90 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%91 = and i32 %90, 3
%92 = icmp ne i32 2, %91
br i1 %92, label %93, label %94
93: ; preds = %89
br label %89
94: ; preds = %89
%95 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%96 = or i32 %95, 2
store volatile i32 %96, i32* inttoptr (i64 1155531956 to i32*)
br label %97
97: ; preds = %101, %94
%98 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%99 = and i32 %98, 3
%100 = icmp ne i32 2, %99
br i1 %100, label %101, label %102
101: ; preds = %97
br label %97
102: ; preds = %97
br label %103
103: ; preds = %107, %102
%104 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%105 = and i32 %104, 196608
%106 = icmp ne i32 0, %105
br i1 %106, label %107, label %108
107: ; preds = %103
br label %103
108: ; preds = %103
br label %109
109: ; preds = %113, %108
%110 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%111 = and i32 %110, 8
%112 = icmp ne i32 8, %111
br i1 %112, label %113, label %114
113: ; preds = %109
br label %109
114: ; preds = %109
br label %115
115: ; preds = %119, %114
%116 = load volatile i32, i32* inttoptr (i64 1155531788 to i32*)
%117 = and i32 %116, 196608
%118 = icmp ne i32 0, %117
br i1 %118, label %119, label %120
119: ; preds = %115
br label %115
120: ; preds = %115
br label %121
121: ; preds = %125, %120
%122 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%123 = and i32 %122, 4
%124 = icmp ne i32 4, %123
br i1 %124, label %125, label %126
125: ; preds = %121
br label %121
126: ; preds = %121
br label %127
127: ; preds = %131, %126
%128 = load volatile i32, i32* inttoptr (i64 1155531980 to i32*)
%129 = and i32 %128, 4
%130 = icmp ne i32 4, %129
br i1 %130, label %131, label %132
131: ; preds = %127
br label %127
132: ; preds = %127
br label %133
133: ; preds = %137, %132
%134 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%135 = and i32 %134, 4096
%136 = icmp ne i32 4096, %135
br i1 %136, label %137, label %138
137: ; preds = %133
br label %133
138: ; preds = %133
br label %139
139: ; preds = %143, %138
%140 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%141 = and i32 %140, 196608
%142 = icmp ne i32 0, %141
br i1 %142, label %143, label %144
143: ; preds = %139
br label %139
144: ; preds = %139
ret void
}

LLVM IR (-O2):
define void @UART0ModuleClkConfig() {
%1 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%2 = or i32 %1, 2
store volatile i32 %2, i32* inttoptr (i64 1155530976 to i32*)
br label %3
3: ; preds = %3, %0
%4 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%5 = and i32 %4, 3
%6 = icmp eq i32 %5, 2
br i1 %6, label %7, label %3
7: ; preds = %3
%8 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%9 = or i32 %8, 2
store volatile i32 %9, i32* inttoptr (i64 1155530972 to i32*)
br label %10
10: ; preds = %10, %7
%11 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%12 = and i32 %11, 3
%13 = icmp eq i32 %12, 2
br i1 %13, label %14, label %10
14: ; preds = %10
%15 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%16 = or i32 %15, 2
store volatile i32 %16, i32* inttoptr (i64 1155530764 to i32*)
br label %17
17: ; preds = %17, %14
%18 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%19 = and i32 %18, 3
%20 = icmp eq i32 %19, 2
br i1 %20, label %21, label %17
21: ; preds = %17
%22 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%23 = or i32 %22, 2
store volatile i32 %23, i32* inttoptr (i64 1155531052 to i32*)
br label %24
24: ; preds = %24, %21
%25 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%26 = and i32 %25, 3
%27 = icmp eq i32 %26, 2
br i1 %27, label %28, label %24
28: ; preds = %24
%29 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%30 = or i32 %29, 2
store volatile i32 %30, i32* inttoptr (i64 1155530756 to i32*)
br label %31
31: ; preds = %31, %28
%32 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%33 = and i32 %32, 3
%34 = icmp eq i32 %33, 2
br i1 %34, label %35, label %31
35: ; preds = %31, %35
%36 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%37 = and i32 %36, 196608
%38 = icmp eq i32 %37, 0
br i1 %38, label %39, label %35
39: ; preds = %35, %39
%40 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%41 = and i32 %40, 196608
%42 = icmp eq i32 %41, 0
br i1 %42, label %43, label %39
43: ; preds = %39, %43
%44 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%45 = and i32 %44, 16
%46 = icmp eq i32 %45, 0
br i1 %46, label %43, label %47
47: ; preds = %43, %47
%48 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%49 = and i32 %48, 16
%50 = icmp eq i32 %49, 0
br i1 %50, label %47, label %51
51: ; preds = %47, %51
%52 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%53 = and i32 %52, 8
%54 = icmp eq i32 %53, 0
br i1 %54, label %51, label %55
55: ; preds = %51
%56 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%57 = or i32 %56, 2
store volatile i32 %57, i32* inttoptr (i64 1155531780 to i32*)
br label %58
58: ; preds = %58, %55
%59 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%60 = and i32 %59, 3
%61 = icmp eq i32 %60, 2
br i1 %61, label %62, label %58
62: ; preds = %58
%63 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%64 = or i32 %63, 2
store volatile i32 %64, i32* inttoptr (i64 1155531776 to i32*)
br label %65
65: ; preds = %65, %62
%66 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%67 = and i32 %66, 3
%68 = icmp eq i32 %67, 2
br i1 %68, label %69, label %65
69: ; preds = %65
%70 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%71 = or i32 %70, 2
store volatile i32 %71, i32* inttoptr (i64 1155531800 to i32*)
br label %72
72: ; preds = %72, %69
%73 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%74 = and i32 %73, 3
%75 = icmp eq i32 %74, 2
br i1 %75, label %76, label %72
76: ; preds = %72
%77 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%78 = or i32 %77, 2
store volatile i32 %78, i32* inttoptr (i64 1155531956 to i32*)
br label %79
79: ; preds = %79, %76
%80 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%81 = and i32 %80, 3
%82 = icmp eq i32 %81, 2
br i1 %82, label %83, label %79
83: ; preds = %79, %83
%84 = load volatile i32, i32* inttoptr (i64 1155531780 to i32*)
%85 = and i32 %84, 196608
%86 = icmp eq i32 %85, 0
br i1 %86, label %87, label %83
87: ; preds = %83, %87
%88 = load volatile i32, i32* inttoptr (i64 1155531800 to i32*)
%89 = and i32 %88, 8
%90 = icmp eq i32 %89, 0
br i1 %90, label %87, label %91
91: ; preds = %87, %91
%92 = load volatile i32, i32* inttoptr (i64 1155531788 to i32*)
%93 = and i32 %92, 196608
%94 = icmp eq i32 %93, 0
br i1 %94, label %95, label %91
95: ; preds = %91, %95
%96 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%97 = and i32 %96, 4
%98 = icmp eq i32 %97, 0
br i1 %98, label %95, label %99
99: ; preds = %95, %99
%100 = load volatile i32, i32* inttoptr (i64 1155531980 to i32*)
%101 = and i32 %100, 4
%102 = icmp eq i32 %101, 0
br i1 %102, label %99, label %103
103: ; preds = %99, %103
%104 = load volatile i32, i32* inttoptr (i64 1155531776 to i32*)
%105 = and i32 %104, 4096
%106 = icmp eq i32 %105, 0
br i1 %106, label %103, label %107
107: ; preds = %103, %107
%108 = load volatile i32, i32* inttoptr (i64 1155531956 to i32*)
%109 = and i32 %108, 196608
%110 = icmp eq i32 %109, 0
br i1 %110, label %111, label %107
111: ; preds = %107
ret void
}