void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
                     unsigned long ulConfig) {
  ;
  ;
  ulGen = ((ulBase) + (ulGen));
  (*((volatile unsigned long *)(ulGen + 0x00000000))) =
      (((*((volatile unsigned long *)(ulGen + 0x00000000))) &
        ~(0x00000002 | 0x00000004 | 0x00040000 | 0x00020000 | 0x00010000 |
          0x0000C000 | 0x00003000 | 0x00000C00 | 0x00000300 | 0x000000C0 |
          0x00000008 | 0x00000010 | 0x00000020)) |
       ulConfig);
  if (ulConfig & 0x00000002) {
    (*((volatile unsigned long *)(ulGen + 0x00000020))) =
        (0x00000030 | 0x00000080);
    (*((volatile unsigned long *)(ulGen + 0x00000024))) =
        (0x00000300 | 0x00000800);
  } else {
    (*((volatile unsigned long *)(ulGen + 0x00000020))) =
        (0x0000000C | 0x00000080);
    (*((volatile unsigned long *)(ulGen + 0x00000024))) =
        (0x0000000C | 0x00000800);
  }
}


x86 assembly (clang, -O0):
<PWMGenConfigure>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    -0x8(%rbp),%rax
add    -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rax
mov    (%rax),%rcx
and    $0xfffffffffff80001,%rcx
or     -0x18(%rbp),%rcx
mov    -0x10(%rbp),%rax
mov    %rcx,(%rax)
mov    -0x18(%rbp),%rax
and    $0x2,%rax
cmp    $0x0,%rax
je     1164 <PWMGenConfigure+0x64>
mov    -0x10(%rbp),%rax
movq   $0xb0,0x20(%rax)
mov    -0x10(%rbp),%rax
movq   $0xb00,0x24(%rax)
jmp    117c <PWMGenConfigure+0x7c>
mov    -0x10(%rbp),%rax
movq   $0x8c,0x20(%rax)
mov    -0x10(%rbp),%rax
movq   $0x80c,0x24(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<PWMGenConfigure>:
mov    $0xfffffffffff80001,%rax
and    (%rsi,%rdi,1),%rax
or     %rdx,%rax
mov    %rax,(%rsi,%rdi,1)
test   $0x2,%dl
mov    $0x8c,%eax
mov    $0xb0,%ecx
cmove  %rax,%rcx
mov    $0x80c,%eax
mov    $0xb00,%edx
cmove  %rax,%rdx
mov    %rcx,0x20(%rsi,%rdi,1)
mov    %rdx,0x24(%rsi,%rdi,1)
ret

LLVM IR (-O0):
define void @PWMGenConfigure(i64 %0, i64 %1, i64 %2) {
%4 = alloca i64
%5 = alloca i64
%6 = alloca i64
store i64 %0, i64* %4
store i64 %1, i64* %5
store i64 %2, i64* %6
%7 = load i64, i64* %4
%8 = load i64, i64* %5
%9 = add i64 %7, %8
store i64 %9, i64* %5
%10 = load i64, i64* %5
%11 = add i64 %10, 0
%12 = inttoptr i64 %11 to i64*
%13 = load volatile i64, i64* %12
%14 = and i64 %13, -524287
%15 = load i64, i64* %6
%16 = or i64 %14, %15
%17 = load i64, i64* %5
%18 = add i64 %17, 0
%19 = inttoptr i64 %18 to i64*
store volatile i64 %16, i64* %19
%20 = load i64, i64* %6
%21 = and i64 %20, 2
%22 = icmp ne i64 %21, 0
br i1 %22, label %23, label %30
23: ; preds = %3
%24 = load i64, i64* %5
%25 = add i64 %24, 32
%26 = inttoptr i64 %25 to i64*
store volatile i64 176, i64* %26
%27 = load i64, i64* %5
%28 = add i64 %27, 36
%29 = inttoptr i64 %28 to i64*
store volatile i64 2816, i64* %29
br label %37
30: ; preds = %3
%31 = load i64, i64* %5
%32 = add i64 %31, 32
%33 = inttoptr i64 %32 to i64*
store volatile i64 140, i64* %33
%34 = load i64, i64* %5
%35 = add i64 %34, 36
%36 = inttoptr i64 %35 to i64*
store volatile i64 2060, i64* %36
br label %37
37: ; preds = %30, %23
ret void
}

LLVM IR (-O2):
define void @PWMGenConfigure(i64 %0, i64 %1, i64 %2) {
%4 = add i64 %1, %0
%5 = inttoptr i64 %4 to i64*
%6 = load volatile i64, i64* %5
%7 = and i64 %6, -524287
%8 = or i64 %7, %2
store volatile i64 %8, i64* %5
%9 = and i64 %2, 2
%10 = icmp eq i64 %9, 0
%11 = add i64 %4, 32
%12 = inttoptr i64 %11 to i64*
%13 = select i1 %10, i64 140, i64 176
%14 = select i1 %10, i64 2060, i64 2816
store volatile i64 %13, i64* %12
%15 = add i64 %4, 36
%16 = inttoptr i64 %15 to i64*
store volatile i64 %14, i64* %16
ret void
}