#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int /*<<< orphan*/ ASSERT(int);
void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
                          uint32_t ui32Trigger, uint32_t ui32Priority) {
  uint32_t ui32Gen;
  ASSERT((ui32Base == 0x40038000) || (ui32Base == 0x40039000));
  ASSERT(ui32SequenceNum < 4);
  ASSERT(((ui32Trigger & 0xF) == 0x00000000) ||
         ((ui32Trigger & 0xF) == 0x00000001) ||
         ((ui32Trigger & 0xF) == 0x00000002) ||
         ((ui32Trigger & 0xF) == 0x00000003) ||
         ((ui32Trigger & 0xF) == 0x00000004) ||
         ((ui32Trigger & 0xF) == 0x00000005) ||
         ((ui32Trigger & 0xF) == 0x00000006) ||
         ((ui32Trigger & 0xF) == 0x00000007) ||
         ((ui32Trigger & 0xF) == 0x00000008) ||
         ((ui32Trigger & 0xF) == 0x00000009) ||
         ((ui32Trigger & 0xF) == 0x0000000F) ||
         ((ui32Trigger & 0x30) == 0x00000000) ||
         ((ui32Trigger & 0x30) == 0x00000010));
  ASSERT(ui32Priority < 4);
  ui32SequenceNum *= 4;
  (*((volatile uint32_t *)(ui32Base + 0x00000014))) =
      (((*((volatile uint32_t *)(ui32Base + 0x00000014))) &
        ~(0xf << ui32SequenceNum)) |
       ((ui32Trigger & 0xf) << ui32SequenceNum));
  (*((volatile uint32_t *)(ui32Base + 0x00000020))) =
      (((*((volatile uint32_t *)(ui32Base + 0x00000020))) &
        ~(0xf << ui32SequenceNum)) |
       ((ui32Priority & 0x3) << ui32SequenceNum));
  ui32Gen = ui32Trigger & 0x0f;
  if (ui32Gen >= 0x00000006 && ui32Gen <= 0x00000009) {
    ui32Gen = (ui32Gen - 0x00000006) * 8;
    (*((volatile uint32_t *)(ui32Base + 0x0000001C))) =
        (((*((volatile uint32_t *)(ui32Base + 0x0000001C))) &
          ~(0x30 << ui32Gen)) |
         ((ui32Trigger & 0x30) << ui32Gen));
  }
}


x86 assembly (clang, -O0):
<ADCSequenceConfigure>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    %edx,-0xc(%rbp)
mov    %ecx,-0x10(%rbp)
mov    $0x1,%al
cmpl   $0x40038000,-0x4(%rbp)
mov    %al,-0x15(%rbp)
je     1143 <ADCSequenceConfigure+0x33>
cmpl   $0x40039000,-0x4(%rbp)
sete   %al
mov    %al,-0x15(%rbp)
mov    -0x15(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x4,-0x8(%rbp)
setl   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x0,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x1,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x2,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x3,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x4,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x5,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x6,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x7,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x8,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0x9,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0xf,%ecx
mov    $0x1,%al
cmp    $0xf,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%ecx
and    $0x30,%ecx
mov    $0x1,%al
cmp    $0x0,%ecx
mov    %al,-0x16(%rbp)
je     1260 <ADCSequenceConfigure+0x150>
mov    -0xc(%rbp),%eax
and    $0x30,%eax
cmp    $0x10,%eax
sete   %al
mov    %al,-0x16(%rbp)
mov    -0x16(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
cmpl   $0x4,-0x10(%rbp)
setl   %al
and    $0x1,%al
movzbl %al,%edi
call   1030 <ASSERT@plt>
mov    -0x8(%rbp),%eax
shl    $0x2,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%eax
add    $0x14,%eax
cltq
mov    (%rax),%eax
mov    -0x8(%rbp),%ecx
mov    $0xf,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x20(%rbp)
mov    -0xc(%rbp),%eax
and    $0xf,%eax
mov    -0x8(%rbp),%ecx
shl    %cl,%eax
mov    -0x20(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x14,%eax
cltq
mov    %ecx,(%rax)
mov    -0x4(%rbp),%eax
add    $0x20,%eax
cltq
mov    (%rax),%eax
mov    -0x8(%rbp),%ecx
mov    $0xf,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x1c(%rbp)
mov    -0x10(%rbp),%eax
and    $0x3,%eax
mov    -0x8(%rbp),%ecx
shl    %cl,%eax
mov    -0x1c(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x20,%eax
cltq
mov    %ecx,(%rax)
mov    -0xc(%rbp),%eax
and    $0xf,%eax
mov    %eax,-0x14(%rbp)
cmpl   $0x6,-0x14(%rbp)
jl     1358 <ADCSequenceConfigure+0x248>
cmpl   $0x9,-0x14(%rbp)
jg     1358 <ADCSequenceConfigure+0x248>
mov    -0x14(%rbp),%eax
sub    $0x6,%eax
shl    $0x3,%eax
mov    %eax,-0x14(%rbp)
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
cltq
mov    (%rax),%eax
mov    -0x14(%rbp),%ecx
mov    $0x30,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
mov    %eax,-0x24(%rbp)
mov    -0xc(%rbp),%eax
and    $0x30,%eax
mov    -0x14(%rbp),%ecx
shl    %cl,%eax
mov    -0x24(%rbp),%ecx
or     %eax,%ecx
mov    -0x4(%rbp),%eax
add    $0x1c,%eax
cltq
mov    %ecx,(%rax)
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCSequenceConfigure>:
push   %rbp
push   %r15
push   %r14
push   %r12
push   %rbx
mov    %ecx,%ebp
mov    %edx,%r14d
mov    %esi,%r15d
mov    %edi,%r12d
mov    %edi,%eax
and    $0xffffefff,%eax
xor    %edi,%edi
cmp    $0x40038000,%eax
sete   %dil
call   1030 <ASSERT@plt>
xor    %edi,%edi
cmp    $0x4,%r15d
setl   %dil
call   1030 <ASSERT@plt>
mov    %r14d,%ebx
and    $0xf,%ebx
mov    $0x1,%edi
mov    $0x83ff,%eax
bt     %ebx,%eax
jb     116f <ADCSequenceConfigure+0x5f>
mov    %r14d,%eax
and    $0x30,%eax
je     116f <ADCSequenceConfigure+0x5f>
xor    %edi,%edi
cmp    $0x10,%eax
sete   %dil
call   1030 <ASSERT@plt>
xor    %edi,%edi
cmp    $0x4,%ebp
setl   %dil
call   1030 <ASSERT@plt>
shl    $0x2,%r15d
mov    $0xf,%edx
mov    %r15d,%ecx
shl    %cl,%edx
movslq %r12d,%rax
not    %edx
mov    0x14(%rax),%esi
and    %edx,%esi
mov    %ebx,%edi
shl    %cl,%edi
or     %esi,%edi
mov    %edi,0x14(%rax)
and    0x20(%rax),%edx
and    $0x3,%ebp
shl    %cl,%ebp
or     %edx,%ebp
mov    %ebp,0x20(%rax)
lea    -0x6(%rbx),%ecx
cmp    $0x3,%ecx
ja     11da <ADCSequenceConfigure+0xca>
shl    $0x3,%ebx
add    $0xd0,%bl
mov    $0x30,%edx
mov    %ebx,%ecx
shl    %cl,%edx
not    %edx
and    $0x30,%r14d
shl    %cl,%r14d
and    0x1c(%rax),%edx
or     %edx,%r14d
mov    %r14d,0x1c(%rax)
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define void @ADCSequenceConfigure(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
%8 = alloca i32
%9 = alloca i32
store i32 %0, i32* %5
store i32 %1, i32* %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%10 = load i32, i32* %5
%11 = icmp eq i32 %10, 1073971200
br i1 %11, label %15, label %12
12: ; preds = %4
%13 = load i32, i32* %5
%14 = icmp eq i32 %13, 1073975296
br label %15
15: ; preds = %12, %4
%16 = phi i1 [ true, %4 ], [ %14, %12 ]
%17 = zext i1 %16 to i32
%18 = call i32 @ASSERT(i32 %17)
%19 = load i32, i32* %6
%20 = icmp slt i32 %19, 4
%21 = zext i1 %20 to i32
%22 = call i32 @ASSERT(i32 %21)
%23 = load i32, i32* %7
%24 = and i32 %23, 15
%25 = icmp eq i32 %24, 0
br i1 %25, label %74, label %26
26: ; preds = %15
%27 = load i32, i32* %7
%28 = and i32 %27, 15
%29 = icmp eq i32 %28, 1
br i1 %29, label %74, label %30
30: ; preds = %26
%31 = load i32, i32* %7
%32 = and i32 %31, 15
%33 = icmp eq i32 %32, 2
br i1 %33, label %74, label %34
34: ; preds = %30
%35 = load i32, i32* %7
%36 = and i32 %35, 15
%37 = icmp eq i32 %36, 3
br i1 %37, label %74, label %38
38: ; preds = %34
%39 = load i32, i32* %7
%40 = and i32 %39, 15
%41 = icmp eq i32 %40, 4
br i1 %41, label %74, label %42
42: ; preds = %38
%43 = load i32, i32* %7
%44 = and i32 %43, 15
%45 = icmp eq i32 %44, 5
br i1 %45, label %74, label %46
46: ; preds = %42
%47 = load i32, i32* %7
%48 = and i32 %47, 15
%49 = icmp eq i32 %48, 6
br i1 %49, label %74, label %50
50: ; preds = %46
%51 = load i32, i32* %7
%52 = and i32 %51, 15
%53 = icmp eq i32 %52, 7
br i1 %53, label %74, label %54
54: ; preds = %50
%55 = load i32, i32* %7
%56 = and i32 %55, 15
%57 = icmp eq i32 %56, 8
br i1 %57, label %74, label %58
58: ; preds = %54
%59 = load i32, i32* %7
%60 = and i32 %59, 15
%61 = icmp eq i32 %60, 9
br i1 %61, label %74, label %62
62: ; preds = %58
%63 = load i32, i32* %7
%64 = and i32 %63, 15
%65 = icmp eq i32 %64, 15
br i1 %65, label %74, label %66
66: ; preds = %62
%67 = load i32, i32* %7
%68 = and i32 %67, 48
%69 = icmp eq i32 %68, 0
br i1 %69, label %74, label %70
70: ; preds = %66
%71 = load i32, i32* %7
%72 = and i32 %71, 48
%73 = icmp eq i32 %72, 16
br label %74
74: ; preds = %70, %66, %62, %58, %54, %50, %46, %42, %38, %34, %30, %26, %15
%75 = phi i1 [ true, %66 ], [ true, %62 ], [ true, %58 ], [ true, %54 ], [ true, %50 ], [ true, %46 ], [ true, %42 ], [ true, %38 ], [ true, %34 ], [ true, %30 ], [ true, %26 ], [ true, %15 ], [ %73, %70 ]
%76 = zext i1 %75 to i32
%77 = call i32 @ASSERT(i32 %76)
%78 = load i32, i32* %8
%79 = icmp slt i32 %78, 4
%80 = zext i1 %79 to i32
%81 = call i32 @ASSERT(i32 %80)
%82 = load i32, i32* %6
%83 = mul nsw i32 %82, 4
store i32 %83, i32* %6
%84 = load i32, i32* %5
%85 = add nsw i32 %84, 20
%86 = sext i32 %85 to i64
%87 = inttoptr i64 %86 to i32*
%88 = load volatile i32, i32* %87
%89 = load i32, i32* %6
%90 = shl i32 15, %89
%91 = xor i32 %90, -1
%92 = and i32 %88, %91
%93 = load i32, i32* %7
%94 = and i32 %93, 15
%95 = load i32, i32* %6
%96 = shl i32 %94, %95
%97 = or i32 %92, %96
%98 = load i32, i32* %5
%99 = add nsw i32 %98, 20
%100 = sext i32 %99 to i64
%101 = inttoptr i64 %100 to i32*
store volatile i32 %97, i32* %101
%102 = load i32, i32* %5
%103 = add nsw i32 %102, 32
%104 = sext i32 %103 to i64
%105 = inttoptr i64 %104 to i32*
%106 = load volatile i32, i32* %105
%107 = load i32, i32* %6
%108 = shl i32 15, %107
%109 = xor i32 %108, -1
%110 = and i32 %106, %109
%111 = load i32, i32* %8
%112 = and i32 %111, 3
%113 = load i32, i32* %6
%114 = shl i32 %112, %113
%115 = or i32 %110, %114
%116 = load i32, i32* %5
%117 = add nsw i32 %116, 32
%118 = sext i32 %117 to i64
%119 = inttoptr i64 %118 to i32*
store volatile i32 %115, i32* %119
%120 = load i32, i32* %7
%121 = and i32 %120, 15
store i32 %121, i32* %9
%122 = load i32, i32* %9
%123 = icmp sge i32 %122, 6
br i1 %123, label %124, label %149
124: ; preds = %74
%125 = load i32, i32* %9
%126 = icmp sle i32 %125, 9
br i1 %126, label %127, label %149
127: ; preds = %124
%128 = load i32, i32* %9
%129 = sub nsw i32 %128, 6
%130 = mul nsw i32 %129, 8
store i32 %130, i32* %9
%131 = load i32, i32* %5
%132 = add nsw i32 %131, 28
%133 = sext i32 %132 to i64
%134 = inttoptr i64 %133 to i32*
%135 = load volatile i32, i32* %134
%136 = load i32, i32* %9
%137 = shl i32 48, %136
%138 = xor i32 %137, -1
%139 = and i32 %135, %138
%140 = load i32, i32* %7
%141 = and i32 %140, 48
%142 = load i32, i32* %9
%143 = shl i32 %141, %142
%144 = or i32 %139, %143
%145 = load i32, i32* %5
%146 = add nsw i32 %145, 28
%147 = sext i32 %146 to i64
%148 = inttoptr i64 %147 to i32*
store volatile i32 %144, i32* %148
br label %149
149: ; preds = %127, %124, %74
ret void
}

LLVM IR (-O2):
define void @ADCSequenceConfigure(i32 %0, i32 %1, i32 %2, i32 %3) {
%5 = and i32 %0, -4097
%6 = icmp eq i32 %5, 1073971200
%7 = zext i1 %6 to i32
%8 = tail call i32 @ASSERT(i32 %7)
%9 = icmp slt i32 %1, 4
%10 = zext i1 %9 to i32
%11 = tail call i32 @ASSERT(i32 %10)
%12 = and i32 %2, 15
%13 = trunc i32 %12 to i16
%14 = lshr i16 -31745, %13
%15 = and i16 %14, 1
%16 = icmp eq i16 %15, 0
br i1 %16, label %17, label %23
17: ; preds = %4
%18 = and i32 %2, 48
%19 = icmp eq i32 %18, 0
br i1 %19, label %23, label %20
20: ; preds = %17
%21 = icmp eq i32 %18, 16
%22 = zext i1 %21 to i32
br label %23
23: ; preds = %4, %20, %17
%24 = phi i32 [ 1, %17 ], [ %22, %20 ], [ 1, %4 ]
%25 = tail call i32 @ASSERT(i32 %24)
%26 = icmp slt i32 %3, 4
%27 = zext i1 %26 to i32
%28 = tail call i32 @ASSERT(i32 %27)
%29 = shl nsw i32 %1, 2
%30 = add nsw i32 %0, 20
%31 = sext i32 %30 to i64
%32 = inttoptr i64 %31 to i32*
%33 = load volatile i32, i32* %32
%34 = shl i32 15, %29
%35 = xor i32 %34, -1
%36 = and i32 %33, %35
%37 = shl i32 %12, %29
%38 = or i32 %36, %37
store volatile i32 %38, i32* %32
%39 = add nsw i32 %0, 32
%40 = sext i32 %39 to i64
%41 = inttoptr i64 %40 to i32*
%42 = load volatile i32, i32* %41
%43 = and i32 %42, %35
%44 = and i32 %3, 3
%45 = shl i32 %44, %29
%46 = or i32 %43, %45
store volatile i32 %46, i32* %41
%47 = add nsw i32 %12, -6
%48 = icmp ult i32 %47, 4
br i1 %48, label %49, label %62
49: ; preds = %23
%50 = shl nuw nsw i32 %12, 3
%51 = add nsw i32 %50, -48
%52 = add nsw i32 %0, 28
%53 = sext i32 %52 to i64
%54 = inttoptr i64 %53 to i32*
%55 = load volatile i32, i32* %54
%56 = shl nuw nsw i32 48, %51
%57 = xor i32 %56, -1
%58 = and i32 %55, %57
%59 = and i32 %2, 48
%60 = shl nuw nsw i32 %59, %51
%61 = or i32 %58, %60
store volatile i32 %61, i32* %54
br label %62
62: ; preds = %49, %23
ret void
}