void RAMMReqSharedMemAccess(unsigned long ulMask, unsigned short usMaster) {
  static unsigned long ulMWRAllow;
  ulMWRAllow = (*((volatile unsigned long *)(0x400FB980)));
  (*((volatile unsigned long *)(0x400FB980))) = 0xA5A5A5A5;
  if (usMaster == 0x0000) {
    (*((volatile unsigned long *)(0x400FB200 + 0x00000010))) &= ~ulMask;
  } else if (usMaster == 0x0001) {
    (*((volatile unsigned long *)(0x400FB200 + 0x00000010))) |= ulMask;
  }
  (*((volatile unsigned long *)(0x400FB980))) = ulMWRAllow;
}


x86 assembly (clang, -O0):
<RAMMReqSharedMemAccess>:
push   %rbp
mov    %rsp,%rbp
mov    %si,%ax
mov    %rdi,-0x8(%rbp)
mov    %ax,-0xa(%rbp)
mov    $0x400fb980,%eax
mov    (%rax),%rax
mov    %rax,0x2f0a(%rip)
mov    $0x400fb980,%eax
mov    $0xa5a5a5a5,%ecx
mov    %rcx,(%rax)
movzwl -0xa(%rbp),%eax
cmp    $0x0,%eax
jne    1158 <RAMMReqSharedMemAccess+0x58>
mov    -0x8(%rbp),%rax
xor    $0xffffffffffffffff,%rax
mov    $0x400fb210,%ecx
mov    (%rcx),%rcx
and    %rax,%rcx
mov    $0x400fb210,%eax
mov    %rcx,(%rax)
jmp    1181 <RAMMReqSharedMemAccess+0x81>
movzwl -0xa(%rbp),%eax
cmp    $0x1,%eax
jne    117c <RAMMReqSharedMemAccess+0x7c>
mov    -0x8(%rbp),%rax
mov    $0x400fb210,%ecx
mov    (%rcx),%rcx
or     %rax,%rcx
mov    $0x400fb210,%eax
mov    %rcx,(%rax)
jmp    1181 <RAMMReqSharedMemAccess+0x81>
mov    0x2ea0(%rip),%rcx
mov    $0x400fb980,%eax
mov    %rcx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<RAMMReqSharedMemAccess>:
movq   $0x0,-0x8(%rsp)
mov    0x400fb980,%rax
40
mov    %rax,-0x8(%rsp)
mov    $0xa5a5a5a5,%eax
mov    %rax,0x400fb980
40
cmp    $0x1,%si
je     113b <RAMMReqSharedMemAccess+0x3b>
test   %si,%si
jne    114b <RAMMReqSharedMemAccess+0x4b>
not    %rdi
and    0x400fb210,%rdi
40
jmp    1143 <RAMMReqSharedMemAccess+0x43>
or     0x400fb210,%rdi
40
mov    %rdi,0x400fb210
40
mov    -0x8(%rsp),%rax
mov    %rax,0x400fb980
40
ret

LLVM IR (-O0):
@RAMMReqSharedMemAccess.ulMWRAllow = internal global i64 0
define void @RAMMReqSharedMemAccess(i64 %0, i16 zeroext %1) {
%3 = alloca i64
%4 = alloca i16
store i64 %0, i64* %3
store i16 %1, i16* %4
%5 = load volatile i64, i64* inttoptr (i64 1074772352 to i64*)
store i64 %5, i64* @RAMMReqSharedMemAccess.ulMWRAllow
store volatile i64 2779096485, i64* inttoptr (i64 1074772352 to i64*)
%6 = load i16, i16* %4
%7 = zext i16 %6 to i32
%8 = icmp eq i32 %7, 0
br i1 %8, label %9, label %14
9: ; preds = %2
%10 = load i64, i64* %3
%11 = xor i64 %10, -1
%12 = load volatile i64, i64* inttoptr (i64 1074770448 to i64*)
%13 = and i64 %12, %11
store volatile i64 %13, i64* inttoptr (i64 1074770448 to i64*)
br label %23
14: ; preds = %2
%15 = load i16, i16* %4
%16 = zext i16 %15 to i32
%17 = icmp eq i32 %16, 1
br i1 %17, label %18, label %22
18: ; preds = %14
%19 = load i64, i64* %3
%20 = load volatile i64, i64* inttoptr (i64 1074770448 to i64*)
%21 = or i64 %20, %19
store volatile i64 %21, i64* inttoptr (i64 1074770448 to i64*)
br label %22
22: ; preds = %18, %14
br label %23
23: ; preds = %22, %9
%24 = load i64, i64* @RAMMReqSharedMemAccess.ulMWRAllow
store volatile i64 %24, i64* inttoptr (i64 1074772352 to i64*)
ret void
}

LLVM IR (-O2):
define void @RAMMReqSharedMemAccess(i64 %0, i16 zeroext %1) {
%3 = alloca i64
store i64 0, i64* %3
%4 = load volatile i64, i64* inttoptr (i64 1074772352 to i64*)
store i64 %4, i64* %3
store volatile i64 2779096485, i64* inttoptr (i64 1074772352 to i64*)
switch i16 %1, label %14 [
i16 0, label %5
i16 1, label %9
]
5: ; preds = %2
%6 = xor i64 %0, -1
%7 = load volatile i64, i64* inttoptr (i64 1074770448 to i64*)
%8 = and i64 %7, %6
br label %12
9: ; preds = %2
%10 = load volatile i64, i64* inttoptr (i64 1074770448 to i64*)
%11 = or i64 %10, %0
br label %12
12: ; preds = %5, %9
%13 = phi i64 [ %11, %9 ], [ %8, %5 ]
store volatile i64 %13, i64* inttoptr (i64 1074770448 to i64*)
br label %14
14: ; preds = %12, %2
%15 = load i64, i64* %3
store volatile i64 %15, i64* inttoptr (i64 1074772352 to i64*)
ret void
}