#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
bool EPIPSRAMConfigRegGetNonBlocking(uint32_t ui32Base, uint32_t ui32CS,
                                     uint32_t *pui32CR) {
  uint32_t ui32Offset;
  ;
  ;
  if (ui32CS < 2) {
    ui32Offset = 0x00000010 + (ui32CS << 2);
  } else {
    ui32Offset = 0x00000308 + ((ui32CS - 2) << 2);
  }
  if ((*((volatile uint32_t *)(ui32Base + ui32Offset))) & 0x00020000) {
    return (false);
  }
  *pui32CR = (*((volatile uint32_t *)(ui32Base + 0x00000360))) & 0xffff;
  return (true);
}


x86 assembly (clang, -O0):
<EPIPSRAMConfigRegGetNonBlocking>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %rdx,-0x18(%rbp)
cmpl   $0x2,-0xc(%rbp)
jge    1129 <EPIPSRAMConfigRegGetNonBlocking+0x29>
mov    -0xc(%rbp),%eax
shl    $0x2,%eax
add    $0x10,%eax
mov    %eax,-0x1c(%rbp)
jmp    113a <EPIPSRAMConfigRegGetNonBlocking+0x3a>
mov    -0xc(%rbp),%eax
sub    $0x2,%eax
shl    $0x2,%eax
add    $0x308,%eax
mov    %eax,-0x1c(%rbp)
mov    -0x8(%rbp),%eax
add    -0x1c(%rbp),%eax
cltq
mov    (%rax),%eax
and    $0x20000,%eax
cmp    $0x0,%eax
je     115e <EPIPSRAMConfigRegGetNonBlocking+0x5e>
movl   $0x0,-0x4(%rbp)
jmp    117d <EPIPSRAMConfigRegGetNonBlocking+0x7d>
mov    -0x8(%rbp),%eax
add    $0x360,%eax
cltq
mov    (%rax),%ecx
and    $0xffff,%ecx
mov    -0x18(%rbp),%rax
mov    %ecx,(%rax)
movl   $0x1,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<EPIPSRAMConfigRegGetNonBlocking>:
cmp    $0x2,%esi
lea    0x10(%rdi,%rsi,4),%eax
lea    0x300(%rdi,%rsi,4),%ecx
cmovl  %eax,%ecx
movslq %ecx,%rcx
xor    %eax,%eax
testl  $0x20000,(%rcx)
jne    1131 <EPIPSRAMConfigRegGetNonBlocking+0x31>
movslq %edi,%rax
mov    0x360(%rax),%eax
movzwl %ax,%eax
mov    %eax,(%rdx)
mov    $0x1,%eax
ret

LLVM IR (-O0):
define i32 @EPIPSRAMConfigRegGetNonBlocking(i32 %0, i32 %1, i32* %2) {
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32*
%8 = alloca i32
store i32 %0, i32* %5
store i32 %1, i32* %6
store i32* %2, i32** %7
%9 = load i32, i32* %6
%10 = icmp slt i32 %9, 2
br i1 %10, label %11, label %15
11: ; preds = %3
%12 = load i32, i32* %6
%13 = shl i32 %12, 2
%14 = add nsw i32 16, %13
store i32 %14, i32* %8
br label %20
15: ; preds = %3
%16 = load i32, i32* %6
%17 = sub nsw i32 %16, 2
%18 = shl i32 %17, 2
%19 = add nsw i32 776, %18
store i32 %19, i32* %8
br label %20
20: ; preds = %15, %11
%21 = load i32, i32* %5
%22 = load i32, i32* %8
%23 = add nsw i32 %21, %22
%24 = sext i32 %23 to i64
%25 = inttoptr i64 %24 to i32*
%26 = load volatile i32, i32* %25
%27 = and i32 %26, 131072
%28 = icmp ne i32 %27, 0
br i1 %28, label %29, label %30
29: ; preds = %20
store i32 0, i32* %4
br label %38
30: ; preds = %20
%31 = load i32, i32* %5
%32 = add nsw i32 %31, 864
%33 = sext i32 %32 to i64
%34 = inttoptr i64 %33 to i32*
%35 = load volatile i32, i32* %34
%36 = and i32 %35, 65535
%37 = load i32*, i32** %7
store i32 %36, i32* %37
store i32 1, i32* %4
br label %38
38: ; preds = %30, %29
%39 = load i32, i32* %4
ret i32 %39
}

LLVM IR (-O2):
define i32 @EPIPSRAMConfigRegGetNonBlocking(i32 %0, i32 %1, i32* nocapture writeonly %2) {
%4 = icmp slt i32 %1, 2
%5 = shl i32 %1, 2
%6 = select i1 %4, i32 16, i32 768
%7 = add i32 %5, %0
%8 = add i32 %7, %6
%9 = sext i32 %8 to i64
%10 = inttoptr i64 %9 to i32*
%11 = load volatile i32, i32* %10
%12 = and i32 %11, 131072
%13 = icmp eq i32 %12, 0
br i1 %13, label %14, label %20
14: ; preds = %3
%15 = add nsw i32 %0, 864
%16 = sext i32 %15 to i64
%17 = inttoptr i64 %16 to i32*
%18 = load volatile i32, i32* %17
%19 = and i32 %18, 65535
store i32 %19, i32* %2
br label %20
20: ; preds = %3, %14
%21 = phi i32 [ 1, %14 ], [ 0, %3 ]
ret i32 %21
}