unsigned int UARTRegConfigModeEnable(unsigned int baseAdd,
                                     unsigned int modeFlag) {
  unsigned int lcrRegValue = 0;
  lcrRegValue = (*((volatile unsigned int *)(baseAdd + (0xC))));
  switch (modeFlag) {
  case (0x0080):
  case (0x00BF):
    (*((volatile unsigned int *)(baseAdd + (0xC)))) = (modeFlag & 0xFF);
    break;
  case (0x007F):
    (*((volatile unsigned int *)(baseAdd + (0xC)))) &= 0x7F;
    break;
  default:
    break;
  }
  return lcrRegValue;
}


x86 assembly (clang, -O0):
<UARTRegConfigModeEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
mov    -0x4(%rbp),%eax
add    $0xc,%eax
mov    (%rax),%eax
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x10(%rbp)
sub    $0x7f,%eax
je     116e <UARTRegConfigModeEnable+0x6e>
jmp    1130 <UARTRegConfigModeEnable+0x30>
mov    -0x10(%rbp),%eax
sub    $0x80,%eax
je     1156 <UARTRegConfigModeEnable+0x56>
jmp    1143 <UARTRegConfigModeEnable+0x43>
mov    -0x10(%rbp),%eax
sub    $0xbf,%eax
jne    1182 <UARTRegConfigModeEnable+0x82>
jmp    1156 <UARTRegConfigModeEnable+0x56>
mov    -0x8(%rbp),%ecx
and    $0xff,%ecx
mov    -0x4(%rbp),%eax
add    $0xc,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
jmp    1187 <UARTRegConfigModeEnable+0x87>
mov    -0x4(%rbp),%eax
add    $0xc,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0x7f,%ecx
mov    %ecx,(%rax)
jmp    1187 <UARTRegConfigModeEnable+0x87>
jmp    1187 <UARTRegConfigModeEnable+0x87>
mov    -0xc(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTRegConfigModeEnable>:
add    $0xc,%edi
mov    (%rdi),%eax
cmp    $0xbf,%esi
je     111f <UARTRegConfigModeEnable+0x1f>
cmp    $0x80,%esi
je     111f <UARTRegConfigModeEnable+0x1f>
cmp    $0x7f,%esi
jne    1121 <UARTRegConfigModeEnable+0x21>
mov    (%rdi),%esi
and    $0x7f,%esi
mov    %esi,(%rdi)
ret

LLVM IR (-O0):
define i32 @UARTRegConfigModeEnable(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
store i32 0, i32* %5
%6 = load i32, i32* %3
%7 = add i32 %6, 12
%8 = zext i32 %7 to i64
%9 = inttoptr i64 %8 to i32*
%10 = load volatile i32, i32* %9
store i32 %10, i32* %5
%11 = load i32, i32* %4
switch i32 %11, label %26 [
i32 128, label %12
i32 191, label %12
i32 127, label %19
]
12: ; preds = %2, %2
%13 = load i32, i32* %4
%14 = and i32 %13, 255
%15 = load i32, i32* %3
%16 = add i32 %15, 12
%17 = zext i32 %16 to i64
%18 = inttoptr i64 %17 to i32*
store volatile i32 %14, i32* %18
br label %27
19: ; preds = %2
%20 = load i32, i32* %3
%21 = add i32 %20, 12
%22 = zext i32 %21 to i64
%23 = inttoptr i64 %22 to i32*
%24 = load volatile i32, i32* %23
%25 = and i32 %24, 127
store volatile i32 %25, i32* %23
br label %27
26: ; preds = %2
br label %27
27: ; preds = %26, %19, %12
%28 = load i32, i32* %5
ret i32 %28
}

LLVM IR (-O2):
define i32 @UARTRegConfigModeEnable(i32 %0, i32 %1) {
%3 = add i32 %0, 12
%4 = zext i32 %3 to i64
%5 = inttoptr i64 %4 to i32*
%6 = load volatile i32, i32* %5
switch i32 %1, label %12 [
i32 128, label %10
i32 191, label %10
i32 127, label %7
]
7: ; preds = %2
%8 = load volatile i32, i32* %5
%9 = and i32 %8, 127
br label %10
10: ; preds = %2, %2, %7
%11 = phi i32 [ %9, %7 ], [ %1, %2 ], [ %1, %2 ]
store volatile i32 %11, i32* %5
br label %12
12: ; preds = %10, %2
ret i32 %6
}