float asin_core(const float x) {
  float x8, x4, x2;
  x2 = x * x;
  x4 = x2 * x2;
  x8 = x4 * x4;
  return (((4.5334220547132049e-2 * x2 - 1.1226216762576600e-2) * x4 +
           (2.6334281471361822e-2 * x2 + 2.0596336163223834e-2)) *
              x8 +
          (3.0582043602875735e-2 * x2 + 4.4630538556294605e-2) * x4 +
          (7.5000364034134126e-2 * x2 + 1.6666666300567365e-1)) *
             x2 * x +
         x;
}


x86 assembly (clang, -O0):
<asin_core>:
push   %rbp
mov    %rsp,%rbp
movss  %xmm0,-0x4(%rbp)
movss  -0x4(%rbp),%xmm0
mulss  -0x4(%rbp),%xmm0
movss  %xmm0,-0x10(%rbp)
movss  -0x10(%rbp),%xmm0
mulss  -0x10(%rbp),%xmm0
movss  %xmm0,-0xc(%rbp)
movss  -0xc(%rbp),%xmm0
mulss  -0xc(%rbp),%xmm0
movss  %xmm0,-0x8(%rbp)
movss  -0x10(%rbp),%xmm0
cvtss2sd %xmm0,%xmm0
movsd  0xee9(%rip),%xmm1
mulsd  %xmm1,%xmm0
movsd  0xee5(%rip),%xmm1
addsd  %xmm1,%xmm0
movss  -0xc(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x10(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
movsd  0xeaf(%rip),%xmm3
mulsd  %xmm3,%xmm1
movsd  0xeab(%rip),%xmm3
addsd  %xmm3,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movss  -0x8(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x10(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
movsd  0xe6d(%rip),%xmm3
mulsd  %xmm3,%xmm1
movsd  0xe69(%rip),%xmm3
addsd  %xmm3,%xmm1
movss  -0xc(%rbp),%xmm3
cvtss2sd %xmm3,%xmm3
mulsd  %xmm3,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
movss  -0x10(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
movsd  0xe27(%rip),%xmm2
mulsd  %xmm2,%xmm1
movsd  0xe23(%rip),%xmm2
addsd  %xmm2,%xmm1
addsd  %xmm1,%xmm0
movss  -0x10(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
mulsd  %xmm1,%xmm0
movss  -0x4(%rbp),%xmm1
cvtss2sd %xmm1,%xmm2
movss  -0x4(%rbp),%xmm1
cvtss2sd %xmm1,%xmm1
mulsd  %xmm2,%xmm0
addsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<asin_core>:
cvtss2sd %xmm0,%xmm1
mulss  %xmm0,%xmm0
cvtss2sd %xmm0,%xmm2
mulss  %xmm0,%xmm0
movsd  0xee8(%rip),%xmm3
mulsd  %xmm2,%xmm3
addsd  0xee4(%rip),%xmm3
cvtss2sd %xmm0,%xmm4
mulss  %xmm0,%xmm0
movsd  0xedc(%rip),%xmm5
mulsd  %xmm2,%xmm5
addsd  0xed8(%rip),%xmm5
mulsd  %xmm4,%xmm3
addsd  %xmm5,%xmm3
cvtss2sd %xmm0,%xmm0
mulsd  %xmm3,%xmm0
movsd  0xec8(%rip),%xmm3
mulsd  %xmm2,%xmm3
addsd  0xec4(%rip),%xmm3
mulsd  %xmm4,%xmm3
addsd  %xmm0,%xmm3
movsd  0xebc(%rip),%xmm0
mulsd  %xmm2,%xmm0
addsd  0xeb8(%rip),%xmm0
addsd  %xmm3,%xmm0
mulsd  %xmm2,%xmm0
mulsd  %xmm1,%xmm0
addsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
ret

LLVM IR (-O0):
define float @asin_core(float %0) {
%2 = alloca float
%3 = alloca float
%4 = alloca float
%5 = alloca float
store float %0, float* %2
%6 = load float, float* %2
%7 = load float, float* %2
%8 = fmul float %6, %7
store float %8, float* %5
%9 = load float, float* %5
%10 = load float, float* %5
%11 = fmul float %9, %10
store float %11, float* %4
%12 = load float, float* %4
%13 = load float, float* %4
%14 = fmul float %12, %13
store float %14, float* %3
%15 = load float, float* %5
%16 = fpext float %15 to double
%17 = call double @llvm.fmuladd.f64(double 0x3FA7360C05477779, double %16, double 0xBF86FDC54ED31832)
%18 = load float, float* %4
%19 = fpext float %18 to double
%20 = load float, float* %5
%21 = fpext float %20 to double
%22 = call double @llvm.fmuladd.f64(double 0x3F9AF75FB6BB8DB7, double %21, double 0x3F951734B8F43115)
%23 = call double @llvm.fmuladd.f64(double %17, double %19, double %22)
%24 = load float, float* %3
%25 = fpext float %24 to double
%26 = load float, float* %5
%27 = fpext float %26 to double
%28 = call double @llvm.fmuladd.f64(double 0x3F9F50E6347A0EDB, double %27, double 0x3FA6D9D05F011A1E)
%29 = load float, float* %4
%30 = fpext float %29 to double
%31 = fmul double %28, %30
%32 = call double @llvm.fmuladd.f64(double %23, double %25, double %31)
%33 = load float, float* %5
%34 = fpext float %33 to double
%35 = call double @llvm.fmuladd.f64(double 0x3FB333394EB6F6A0, double %34, double 0x3FC555554D78AE5F)
%36 = fadd double %32, %35
%37 = load float, float* %5
%38 = fpext float %37 to double
%39 = fmul double %36, %38
%40 = load float, float* %2
%41 = fpext float %40 to double
%42 = load float, float* %2
%43 = fpext float %42 to double
%44 = call double @llvm.fmuladd.f64(double %39, double %41, double %43)
%45 = fptrunc double %44 to float
ret float %45
}

LLVM IR (-O2):
define float @asin_core(float %0) {
%2 = fmul float %0, %0
%3 = fmul float %2, %2
%4 = fmul float %3, %3
%5 = fpext float %2 to double
%6 = tail call double @llvm.fmuladd.f64(double %5, double 0x3FA7360C05477779, double 0xBF86FDC54ED31832)
%7 = fpext float %3 to double
%8 = tail call double @llvm.fmuladd.f64(double %5, double 0x3F9AF75FB6BB8DB7, double 0x3F951734B8F43115)
%9 = tail call double @llvm.fmuladd.f64(double %6, double %7, double %8)
%10 = fpext float %4 to double
%11 = tail call double @llvm.fmuladd.f64(double %5, double 0x3F9F50E6347A0EDB, double 0x3FA6D9D05F011A1E)
%12 = fmul double %11, %7
%13 = tail call double @llvm.fmuladd.f64(double %9, double %10, double %12)
%14 = tail call double @llvm.fmuladd.f64(double %5, double 0x3FB333394EB6F6A0, double 0x3FC555554D78AE5F)
%15 = fadd double %14, %13
%16 = fmul double %15, %5
%17 = fpext float %0 to double
%18 = tail call double @llvm.fmuladd.f64(double %16, double %17, double %17)
%19 = fptrunc double %18 to float
ret float %19
}