#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
uint32_t riva128_pfifo_cache1_next(uint32_t ptr) {
  int bits = 5;
  uint32_t tmp = ptr >> 2;
  if (tmp == (1 << (bits - 1)))
    return 0;
  for (int bit = bits - 1; bit > 0; bit--) {
    if (tmp == (1 << (bit - 1)))
      return ptr ^ (1 << (2 + bit));
    if (tmp & (1 << bit))
      tmp ^= 3 << (bit - 1);
  }
  return ptr ^ 4;
}


x86 assembly (clang, -O0):
<riva128_pfifo_cache1_next>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
movl   $0x5,-0xc(%rbp)
mov    -0x8(%rbp),%eax
sar    $0x2,%eax
mov    %eax,-0x10(%rbp)
mov    -0x10(%rbp),%eax
mov    -0xc(%rbp),%ecx
sub    $0x1,%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
cmp    %ecx,%eax
jne    113d <riva128_pfifo_cache1_next+0x3d>
movl   $0x0,-0x4(%rbp)
jmp    11cf <riva128_pfifo_cache1_next+0xcf>
mov    -0xc(%rbp),%eax
sub    $0x1,%eax
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
jle    11c6 <riva128_pfifo_cache1_next+0xc6>
mov    -0x10(%rbp),%eax
mov    -0x14(%rbp),%ecx
sub    $0x1,%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
cmp    %ecx,%eax
jne    1186 <riva128_pfifo_cache1_next+0x86>
mov    -0x8(%rbp),%eax
mov    -0x14(%rbp),%ecx
add    $0x2,%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
xor    %ecx,%eax
mov    %eax,-0x4(%rbp)
jmp    11cf <riva128_pfifo_cache1_next+0xcf>
mov    -0x10(%rbp),%eax
mov    -0x14(%rbp),%ecx
mov    $0x1,%edx
shl    %cl,%edx
mov    %edx,%ecx
and    %ecx,%eax
cmp    $0x0,%eax
je     11b3 <riva128_pfifo_cache1_next+0xb3>
mov    -0x14(%rbp),%ecx
sub    $0x1,%ecx
mov    $0x3,%eax
shl    %cl,%eax
xor    -0x10(%rbp),%eax
mov    %eax,-0x10(%rbp)
jmp    11b8 <riva128_pfifo_cache1_next+0xb8>
mov    -0x14(%rbp),%eax
add    $0xffffffff,%eax
mov    %eax,-0x14(%rbp)
jmp    1146 <riva128_pfifo_cache1_next+0x46>
mov    -0x8(%rbp),%eax
xor    $0x4,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<riva128_pfifo_cache1_next>:
mov    %edi,%edx
sar    $0x2,%edx
cmp    $0x8,%edx
je     115b <riva128_pfifo_cache1_next+0x5b>
xor    %eax,%eax
cmp    $0x10,%edx
je     1165 <riva128_pfifo_cache1_next+0x65>
mov    %edi,%ecx
shl    $0x19,%ecx
sar    $0x1f,%ecx
and    $0x18,%ecx
xor    %edx,%ecx
mov    $0x5,%eax
cmp    $0x4,%ecx
je     1160 <riva128_pfifo_cache1_next+0x60>
mov    %ecx,%edx
shl    $0x1c,%edx
sar    $0x1f,%edx
and    $0xc,%edx
xor    %ecx,%edx
mov    $0x4,%eax
cmp    $0x2,%edx
je     1160 <riva128_pfifo_cache1_next+0x60>
mov    %edx,%ecx
shl    $0x1d,%ecx
sar    $0x1f,%ecx
and    $0x6,%ecx
xor    %edx,%ecx
mov    $0x3,%eax
cmp    $0x1,%ecx
je     1160 <riva128_pfifo_cache1_next+0x60>
xor    $0x4,%edi
jmp    1163 <riva128_pfifo_cache1_next+0x63>
mov    $0x6,%eax
btc    %eax,%edi
mov    %edi,%eax
ret

LLVM IR (-O0):
define i32 @riva128_pfifo_cache1_next(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
store i32 %0, i32* %3
store i32 5, i32* %4
%7 = load i32, i32* %3
%8 = ashr i32 %7, 2
store i32 %8, i32* %5
%9 = load i32, i32* %5
%10 = load i32, i32* %4
%11 = sub nsw i32 %10, 1
%12 = shl i32 1, %11
%13 = icmp eq i32 %9, %12
br i1 %13, label %14, label %15
14: ; preds = %1
store i32 0, i32* %2
br label %52
15: ; preds = %1
%16 = load i32, i32* %4
%17 = sub nsw i32 %16, 1
store i32 %17, i32* %6
br label %18
18: ; preds = %46, %15
%19 = load i32, i32* %6
%20 = icmp sgt i32 %19, 0
br i1 %20, label %21, label %49
21: ; preds = %18
%22 = load i32, i32* %5
%23 = load i32, i32* %6
%24 = sub nsw i32 %23, 1
%25 = shl i32 1, %24
%26 = icmp eq i32 %22, %25
br i1 %26, label %27, label %33
27: ; preds = %21
%28 = load i32, i32* %3
%29 = load i32, i32* %6
%30 = add nsw i32 2, %29
%31 = shl i32 1, %30
%32 = xor i32 %28, %31
store i32 %32, i32* %2
br label %52
33: ; preds = %21
%34 = load i32, i32* %5
%35 = load i32, i32* %6
%36 = shl i32 1, %35
%37 = and i32 %34, %36
%38 = icmp ne i32 %37, 0
br i1 %38, label %39, label %45
39: ; preds = %33
%40 = load i32, i32* %6
%41 = sub nsw i32 %40, 1
%42 = shl i32 3, %41
%43 = load i32, i32* %5
%44 = xor i32 %43, %42
store i32 %44, i32* %5
br label %45
45: ; preds = %39, %33
br label %46
46: ; preds = %45
%47 = load i32, i32* %6
%48 = add nsw i32 %47, -1
store i32 %48, i32* %6
br label %18
49: ; preds = %18
%50 = load i32, i32* %3
%51 = xor i32 %50, 4
store i32 %51, i32* %2
br label %52
52: ; preds = %49, %27, %14
%53 = load i32, i32* %2
ret i32 %53
}

LLVM IR (-O2):
define i32 @riva128_pfifo_cache1_next(i32 %0) {
%2 = ashr i32 %0, 2
switch i32 %2, label %3 [
i32 16, label %27
i32 8, label %23
]
3: ; preds = %1
%4 = and i32 %0, 64
%5 = icmp eq i32 %4, 0
%6 = select i1 %5, i32 0, i32 24
%7 = xor i32 %6, %2
%8 = icmp eq i32 %7, 4
br i1 %8, label %23, label %9
9: ; preds = %3
%10 = and i32 %7, 8
%11 = icmp eq i32 %10, 0
%12 = select i1 %11, i32 0, i32 12
%13 = xor i32 %12, %7
%14 = icmp eq i32 %13, 2
br i1 %14, label %23, label %15
15: ; preds = %9
%16 = and i32 %13, 4
%17 = icmp eq i32 %16, 0
%18 = select i1 %17, i32 0, i32 6
%19 = xor i32 %18, %13
%20 = icmp eq i32 %19, 1
br i1 %20, label %23, label %21
21: ; preds = %15
%22 = xor i32 %0, 4
br label %27
23: ; preds = %1, %3, %9, %15
%24 = phi i32 [ 5, %3 ], [ 4, %9 ], [ 3, %15 ], [ 6, %1 ]
%25 = shl nuw nsw i32 1, %24
%26 = xor i32 %25, %0
br label %27
27: ; preds = %1, %23, %21
%28 = phi i32 [ 0, %1 ], [ %26, %23 ], [ %22, %21 ]
ret i32 %28
}