int special_field_exponent_bits(unsigned long dword1) {
  unsigned long g_field_specials;
  int left_two_bits;
  int right_three_bits;
  g_field_specials = (dword1 & 0x7c00000000000000UL) >> 58;
  left_two_bits = (g_field_specials & 0x18) >> 3;
  right_three_bits = g_field_specials & 0x07;
  if (left_two_bits < 3) {
    return (left_two_bits);
  }
  switch (right_three_bits) {
  case 0:
  case 1:
    return 0x0;
  case 2:
  case 3:
    return 0x1;
  case 4:
  case 5:
    return 0x2;
  case 6:
    return 0x0;
  case 7:
    return 0x0;
  }
  return -1;
}


x86 assembly (clang, -O0):
<special_field_exponent_bits>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x10(%rbp)
movabs $0x7c00000000000000,%rax
and    -0x10(%rbp),%rax
shr    $0x3a,%rax
mov    %rax,-0x18(%rbp)
mov    -0x18(%rbp),%rax
and    $0x18,%rax
shr    $0x3,%rax
mov    %eax,-0x1c(%rbp)
mov    -0x18(%rbp),%rax
and    $0x7,%rax
mov    %eax,-0x20(%rbp)
cmpl   $0x3,-0x1c(%rbp)
jge    114d <special_field_exponent_bits+0x4d>
mov    -0x1c(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
mov    -0x20(%rbp),%eax
mov    %rax,-0x28(%rbp)
sub    $0x7,%rax
ja     11ae <special_field_exponent_bits+0xae>
mov    -0x28(%rbp),%rax
lea    0xe97(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movl   $0x0,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
movl   $0x1,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
movl   $0x2,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
movl   $0x0,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
movl   $0x0,-0x4(%rbp)
jmp    11b5 <special_field_exponent_bits+0xb5>
movl   $0xffffffff,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<special_field_exponent_bits>:
mov    %rdi,%rax
shr    $0x3d,%rax
and    $0x3,%eax
cmp    $0x3,%eax
jne    1120 <special_field_exponent_bits+0x20>
shr    $0x38,%rdi
and    $0x1c,%edi
lea    0xee3(%rip),%rax
mov    (%rdi,%rax,1),%eax
ret

LLVM IR (-O0):
define i32 @special_field_exponent_bits(i64 %0) {
%2 = alloca i32
%3 = alloca i64
%4 = alloca i64
%5 = alloca i32
%6 = alloca i32
store i64 %0, i64* %3
%7 = load i64, i64* %3
%8 = and i64 %7, 8935141660703064064
%9 = lshr i64 %8, 58
store i64 %9, i64* %4
%10 = load i64, i64* %4
%11 = and i64 %10, 24
%12 = lshr i64 %11, 3
%13 = trunc i64 %12 to i32
store i32 %13, i32* %5
%14 = load i64, i64* %4
%15 = and i64 %14, 7
%16 = trunc i64 %15 to i32
store i32 %16, i32* %6
%17 = load i32, i32* %5
%18 = icmp slt i32 %17, 3
br i1 %18, label %19, label %21
19: ; preds = %1
%20 = load i32, i32* %5
store i32 %20, i32* %2
br label %29
21: ; preds = %1
%22 = load i32, i32* %6
switch i32 %22, label %28 [
i32 0, label %23
i32 1, label %23
i32 2, label %24
i32 3, label %24
i32 4, label %25
i32 5, label %25
i32 6, label %26
i32 7, label %27
]
23: ; preds = %21, %21
store i32 0, i32* %2
br label %29
24: ; preds = %21, %21
store i32 1, i32* %2
br label %29
25: ; preds = %21, %21
store i32 2, i32* %2
br label %29
26: ; preds = %21
store i32 0, i32* %2
br label %29
27: ; preds = %21
store i32 0, i32* %2
br label %29
28: ; preds = %21
store i32 -1, i32* %2
br label %29
29: ; preds = %28, %27, %26, %25, %24, %23, %19
%30 = load i32, i32* %2
ret i32 %30
}

LLVM IR (-O2):
@switch.table.special_field_exponent_bits = [8 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 0, i32 0]
define i32 @special_field_exponent_bits(i64 %0) {
%2 = lshr i64 %0, 61
%3 = trunc i64 %2 to i32
%4 = and i32 %3, 3
%5 = icmp eq i32 %4, 3
br i1 %5, label %6, label %11
6: ; preds = %1
%7 = lshr i64 %0, 58
%8 = and i64 %7, 7
%9 = getelementptr inbounds [8 x i32], [8 x i32]* @switch.table.special_field_exponent_bits, i64 0, i64 %8
%10 = load i32, i32* %9
br label %11
11: ; preds = %6, %1
%12 = phi i32 [ %4, %1 ], [ %10, %6 ]
ret i32 %12
}