#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef scalar_t__ data;
typedef scalar_t__ addr;

/* Variables and functions */
scalar_t__ efuse_reg_addr(int);
int /*<<< orphan*/ udelay(int);
void __efuse_write_byte(unsigned long addr, unsigned long data) {
  unsigned long auto_wr_is_enabled = 0;
  if ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) & (1 << 12)) {
    auto_wr_is_enabled = 1;
  } else {
    (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
         ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
          ~(((1L << (1)) - 1) << (12))) |
         ((unsigned)((1) & ((1L << (1)) - 1)) << (12)));
  }
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (10)) - 1) << (0))) |
       ((unsigned)((addr) & ((1L << (10)) - 1)) << (0)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (1)) - 1) << (11))) |
       ((unsigned)((1) & ((1L << (1)) - 1)) << (11)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (1)) - 1) << (11))) |
       ((unsigned)((0) & ((1L << (1)) - 1)) << (11)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (8)) - 1) << (16))) |
       ((unsigned)((data) & ((1L << (8)) - 1)) << (16)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (1)) - 1) << (13))) |
       ((unsigned)((1) & ((1L << (1)) - 1)) << (13)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
       ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
        ~(((1L << (1)) - 1) << (13))) |
       ((unsigned)((0) & ((1L << (1)) - 1)) << (13)));
  (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))));
  while ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) & (1 << 14)) {
    udelay(1);
  }
  if (auto_wr_is_enabled == 0) {
    (*((volatile unsigned *)efuse_reg_addr((0x2159 << 2))) =
         ((*((volatile unsigned *)efuse_reg_addr((0x2159 << 2)))) &
          ~(((1L << (1)) - 1) << (12))) |
         ((unsigned)((0) & ((1L << (1)) - 1)) << (12)));
  }
}


x86 assembly (clang, -O0):
<__efuse_write_byte>:
push   %rbp
mov    %rsp,%rbp
sub    $0x40,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
movq   $0x0,-0x18(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
and    $0x1000,%eax
cmp    $0x0,%eax
je     115f <__efuse_write_byte+0x3f>
movq   $0x1,-0x18(%rbp)
jmp    118b <__efuse_write_byte+0x6b>
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xffffffffffffefff,%rax
or     $0x1000,%rax
mov    %eax,-0x1c(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x1c(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xfffffffffffffc00,%rax
mov    -0x8(%rbp),%rcx
and    $0x3ff,%rcx
shl    $0x0,%ecx
mov    %ecx,%ecx
or     %rcx,%rax
mov    %eax,-0x34(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x34(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xfffffffffffff7ff,%rax
or     $0x800,%rax
mov    %eax,-0x30(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x30(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xfffffffffffff7ff,%rax
or     $0x0,%rax
mov    %eax,-0x2c(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x2c(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xffffffffff00ffff,%rax
mov    -0x10(%rbp),%rcx
and    $0xff,%rcx
shl    $0x10,%ecx
mov    %ecx,%ecx
or     %rcx,%rax
mov    %eax,-0x28(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x28(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xffffffffffffdfff,%rax
or     $0x2000,%rax
mov    %eax,-0x24(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x24(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xffffffffffffdfff,%rax
or     $0x0,%rax
mov    %eax,-0x20(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x20(%rbp),%ecx
mov    %ecx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
and    $0x4000,%eax
cmp    $0x0,%eax
je     12de <__efuse_write_byte+0x1be>
mov    $0x1,%edi
call   1040 <udelay@plt>
jmp    12b5 <__efuse_write_byte+0x195>
cmpq   $0x0,-0x18(%rbp)
jne    1313 <__efuse_write_byte+0x1f3>
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
mov    %eax,%eax
and    $0xffffffffffffefff,%rax
or     $0x0,%rax
mov    %eax,-0x38(%rbp)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    -0x38(%rbp),%ecx
mov    %ecx,(%rax)
add    $0x40,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<__efuse_write_byte>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
mov    %rsi,%r14
mov    %rdi,%rbx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%r15d
test   $0x1000,%r15d
jne    1160 <__efuse_write_byte+0x40>
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0x1000,%ebp
or     (%rax),%ebp
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebp,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0xfffffc00,%ecx
and    (%rax),%ecx
and    $0x3ff,%ebx
or     %ecx,%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0x800,%ebx
or     (%rax),%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0xfffff7ff,%ebx
and    (%rax),%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0xff00ffff,%ecx
and    (%rax),%ecx
movzbl %r14b,%ebx
shl    $0x10,%ebx
or     %ecx,%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0x2000,%ebx
or     (%rax),%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0xffffdfff,%ebx
and    (%rax),%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    (%rax),%eax
nopl   0x0(%rax,%rax,1)
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
testl  $0x4000,(%rax)
je     124e <__efuse_write_byte+0x12e>
mov    $0x1,%edi
call   1040 <udelay@plt>
jmp    1230 <__efuse_write_byte+0x110>
test   $0x1000,%r15d
jne    1274 <__efuse_write_byte+0x154>
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    $0xffffefff,%ebx
and    (%rax),%ebx
mov    $0x8564,%edi
call   1030 <efuse_reg_addr@plt>
mov    %ebx,(%rax)
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define void @__efuse_write_byte(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
%5 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
store i64 0, i64* %5
%6 = call i64 @efuse_reg_addr(i32 34148)
%7 = inttoptr i64 %6 to i32*
%8 = load volatile i32, i32* %7
%9 = and i32 %8, 4096
%10 = icmp ne i32 %9, 0
br i1 %10, label %11, label %12
11: ; preds = %2
store i64 1, i64* %5
br label %22
12: ; preds = %2
%13 = call i64 @efuse_reg_addr(i32 34148)
%14 = inttoptr i64 %13 to i32*
%15 = load volatile i32, i32* %14
%16 = zext i32 %15 to i64
%17 = and i64 %16, -4097
%18 = or i64 %17, 4096
%19 = trunc i64 %18 to i32
%20 = call i64 @efuse_reg_addr(i32 34148)
%21 = inttoptr i64 %20 to i32*
store volatile i32 %19, i32* %21
br label %22
22: ; preds = %12, %11
%23 = call i64 @efuse_reg_addr(i32 34148)
%24 = inttoptr i64 %23 to i32*
%25 = load volatile i32, i32* %24
%26 = zext i32 %25 to i64
%27 = and i64 %26, -1024
%28 = load i64, i64* %3
%29 = and i64 %28, 1023
%30 = trunc i64 %29 to i32
%31 = shl i32 %30, 0
%32 = zext i32 %31 to i64
%33 = or i64 %27, %32
%34 = trunc i64 %33 to i32
%35 = call i64 @efuse_reg_addr(i32 34148)
%36 = inttoptr i64 %35 to i32*
store volatile i32 %34, i32* %36
%37 = call i64 @efuse_reg_addr(i32 34148)
%38 = inttoptr i64 %37 to i32*
%39 = load volatile i32, i32* %38
%40 = zext i32 %39 to i64
%41 = and i64 %40, -2049
%42 = or i64 %41, 2048
%43 = trunc i64 %42 to i32
%44 = call i64 @efuse_reg_addr(i32 34148)
%45 = inttoptr i64 %44 to i32*
store volatile i32 %43, i32* %45
%46 = call i64 @efuse_reg_addr(i32 34148)
%47 = inttoptr i64 %46 to i32*
%48 = load volatile i32, i32* %47
%49 = zext i32 %48 to i64
%50 = and i64 %49, -2049
%51 = or i64 %50, 0
%52 = trunc i64 %51 to i32
%53 = call i64 @efuse_reg_addr(i32 34148)
%54 = inttoptr i64 %53 to i32*
store volatile i32 %52, i32* %54
%55 = call i64 @efuse_reg_addr(i32 34148)
%56 = inttoptr i64 %55 to i32*
%57 = load volatile i32, i32* %56
%58 = zext i32 %57 to i64
%59 = and i64 %58, -16711681
%60 = load i64, i64* %4
%61 = and i64 %60, 255
%62 = trunc i64 %61 to i32
%63 = shl i32 %62, 16
%64 = zext i32 %63 to i64
%65 = or i64 %59, %64
%66 = trunc i64 %65 to i32
%67 = call i64 @efuse_reg_addr(i32 34148)
%68 = inttoptr i64 %67 to i32*
store volatile i32 %66, i32* %68
%69 = call i64 @efuse_reg_addr(i32 34148)
%70 = inttoptr i64 %69 to i32*
%71 = load volatile i32, i32* %70
%72 = zext i32 %71 to i64
%73 = and i64 %72, -8193
%74 = or i64 %73, 8192
%75 = trunc i64 %74 to i32
%76 = call i64 @efuse_reg_addr(i32 34148)
%77 = inttoptr i64 %76 to i32*
store volatile i32 %75, i32* %77
%78 = call i64 @efuse_reg_addr(i32 34148)
%79 = inttoptr i64 %78 to i32*
%80 = load volatile i32, i32* %79
%81 = zext i32 %80 to i64
%82 = and i64 %81, -8193
%83 = or i64 %82, 0
%84 = trunc i64 %83 to i32
%85 = call i64 @efuse_reg_addr(i32 34148)
%86 = inttoptr i64 %85 to i32*
store volatile i32 %84, i32* %86
%87 = call i64 @efuse_reg_addr(i32 34148)
%88 = inttoptr i64 %87 to i32*
%89 = load volatile i32, i32* %88
br label %90
90: ; preds = %96, %22
%91 = call i64 @efuse_reg_addr(i32 34148)
%92 = inttoptr i64 %91 to i32*
%93 = load volatile i32, i32* %92
%94 = and i32 %93, 16384
%95 = icmp ne i32 %94, 0
br i1 %95, label %96, label %98
96: ; preds = %90
%97 = call i32 @udelay(i32 1)
br label %90
98: ; preds = %90
%99 = load i64, i64* %5
%100 = icmp eq i64 %99, 0
br i1 %100, label %101, label %111
101: ; preds = %98
%102 = call i64 @efuse_reg_addr(i32 34148)
%103 = inttoptr i64 %102 to i32*
%104 = load volatile i32, i32* %103
%105 = zext i32 %104 to i64
%106 = and i64 %105, -4097
%107 = or i64 %106, 0
%108 = trunc i64 %107 to i32
%109 = call i64 @efuse_reg_addr(i32 34148)
%110 = inttoptr i64 %109 to i32*
store volatile i32 %108, i32* %110
br label %111
111: ; preds = %101, %98
ret void
}

LLVM IR (-O2):
define void @__efuse_write_byte(i64 %0, i64 %1) {
%3 = tail call i64 @efuse_reg_addr(i32 34148)
%4 = inttoptr i64 %3 to i32*
%5 = load volatile i32, i32* %4
%6 = and i32 %5, 4096
%7 = icmp eq i32 %6, 0
br i1 %7, label %8, label %15
8: ; preds = %2
%9 = tail call i64 @efuse_reg_addr(i32 34148)
%10 = inttoptr i64 %9 to i32*
%11 = load volatile i32, i32* %10
%12 = or i32 %11, 4096
%13 = tail call i64 @efuse_reg_addr(i32 34148)
%14 = inttoptr i64 %13 to i32*
store volatile i32 %12, i32* %14
br label %15
15: ; preds = %2, %8
%16 = tail call i64 @efuse_reg_addr(i32 34148)
%17 = inttoptr i64 %16 to i32*
%18 = load volatile i32, i32* %17
%19 = and i32 %18, -1024
%20 = trunc i64 %0 to i32
%21 = and i32 %20, 1023
%22 = or i32 %19, %21
%23 = tail call i64 @efuse_reg_addr(i32 34148)
%24 = inttoptr i64 %23 to i32*
store volatile i32 %22, i32* %24
%25 = tail call i64 @efuse_reg_addr(i32 34148)
%26 = inttoptr i64 %25 to i32*
%27 = load volatile i32, i32* %26
%28 = or i32 %27, 2048
%29 = tail call i64 @efuse_reg_addr(i32 34148)
%30 = inttoptr i64 %29 to i32*
store volatile i32 %28, i32* %30
%31 = tail call i64 @efuse_reg_addr(i32 34148)
%32 = inttoptr i64 %31 to i32*
%33 = load volatile i32, i32* %32
%34 = and i32 %33, -2049
%35 = tail call i64 @efuse_reg_addr(i32 34148)
%36 = inttoptr i64 %35 to i32*
store volatile i32 %34, i32* %36
%37 = tail call i64 @efuse_reg_addr(i32 34148)
%38 = inttoptr i64 %37 to i32*
%39 = load volatile i32, i32* %38
%40 = and i32 %39, -16711681
%41 = trunc i64 %1 to i32
%42 = shl i32 %41, 16
%43 = and i32 %42, 16711680
%44 = or i32 %40, %43
%45 = tail call i64 @efuse_reg_addr(i32 34148)
%46 = inttoptr i64 %45 to i32*
store volatile i32 %44, i32* %46
%47 = tail call i64 @efuse_reg_addr(i32 34148)
%48 = inttoptr i64 %47 to i32*
%49 = load volatile i32, i32* %48
%50 = or i32 %49, 8192
%51 = tail call i64 @efuse_reg_addr(i32 34148)
%52 = inttoptr i64 %51 to i32*
store volatile i32 %50, i32* %52
%53 = tail call i64 @efuse_reg_addr(i32 34148)
%54 = inttoptr i64 %53 to i32*
%55 = load volatile i32, i32* %54
%56 = and i32 %55, -8193
%57 = tail call i64 @efuse_reg_addr(i32 34148)
%58 = inttoptr i64 %57 to i32*
store volatile i32 %56, i32* %58
%59 = tail call i64 @efuse_reg_addr(i32 34148)
%60 = inttoptr i64 %59 to i32*
%61 = load volatile i32, i32* %60
%62 = tail call i64 @efuse_reg_addr(i32 34148)
%63 = inttoptr i64 %62 to i32*
%64 = load volatile i32, i32* %63
%65 = and i32 %64, 16384
%66 = icmp eq i32 %65, 0
br i1 %66, label %74, label %67
67: ; preds = %15, %67
%68 = tail call i32 @udelay(i32 1)
%69 = tail call i64 @efuse_reg_addr(i32 34148)
%70 = inttoptr i64 %69 to i32*
%71 = load volatile i32, i32* %70
%72 = and i32 %71, 16384
%73 = icmp eq i32 %72, 0
br i1 %73, label %74, label %67
74: ; preds = %67, %15
br i1 %7, label %75, label %82
75: ; preds = %74
%76 = tail call i64 @efuse_reg_addr(i32 34148)
%77 = inttoptr i64 %76 to i32*
%78 = load volatile i32, i32* %77
%79 = and i32 %78, -4097
%80 = tail call i64 @efuse_reg_addr(i32 34148)
%81 = inttoptr i64 %80 to i32*
store volatile i32 %79, i32* %81
br label %82
82: ; preds = %75, %74
ret void
}