void DMTimer7ModuleClkConfig(void) {
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x0)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x60)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x60)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0x500) + (0x4)))) &=
      ~((0x00000003u));
  (*((volatile unsigned int *)(((0x44E00000) + 0x500) + (0x4)))) |= (0x1u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0x500) + (0x4)))) &
          (0x00000003u)) != (0x1u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x7c)))) |= (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x7c)))) &
          (0x00000003u)) != (0x2u))
    ;
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x7c)))) &
          (0x00030000u)) != (0x0u))
    ;
  while (!((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) &
           (0x00000008u)))
    ;
  while (!((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) &
           (0x00000010u)))
    ;
  while (!((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) &
           ((0x00000010u) | (0x00000020u))))
    ;
  while (!((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x0)))) &
           ((0x00000100u) | (0x00002000u))))
    ;
}


x86 assembly (clang, -O0):
<DMTimer7ModuleClkConfig>:
push   %rbp
mov    %rsp,%rbp
mov    $0x44e00004,%eax
movl   $0x2,(%rax)
mov    $0x44e00004,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1127 <DMTimer7ModuleClkConfig+0x27>
jmp    110f <DMTimer7ModuleClkConfig+0xf>
mov    $0x44e0000c,%eax
movl   $0x2,(%rax)
mov    $0x44e0000c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     114a <DMTimer7ModuleClkConfig+0x4a>
jmp    1132 <DMTimer7ModuleClkConfig+0x32>
mov    $0x44e000dc,%eax
movl   $0x2,(%rax)
mov    $0x44e000dc,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     116d <DMTimer7ModuleClkConfig+0x6d>
jmp    1155 <DMTimer7ModuleClkConfig+0x55>
mov    $0x44e000e0,%eax
movl   $0x2,(%rax)
mov    $0x44e000e0,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1190 <DMTimer7ModuleClkConfig+0x90>
jmp    1178 <DMTimer7ModuleClkConfig+0x78>
mov    $0x44e0012c,%eax
movl   $0x2,(%rax)
mov    $0x44e0012c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11b3 <DMTimer7ModuleClkConfig+0xb3>
jmp    119b <DMTimer7ModuleClkConfig+0x9b>
mov    $0x44e00000,%eax
movl   $0x2,(%rax)
mov    $0x44e00000,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11d6 <DMTimer7ModuleClkConfig+0xd6>
jmp    11be <DMTimer7ModuleClkConfig+0xbe>
mov    $0x44e00060,%eax
movl   $0x2,(%rax)
mov    $0x44e00060,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11f9 <DMTimer7ModuleClkConfig+0xf9>
jmp    11e1 <DMTimer7ModuleClkConfig+0xe1>
mov    $0x44e00504,%eax
mov    (%rax),%ecx
and    $0xfffffffc,%ecx
mov    $0x44e00504,%eax
mov    %ecx,(%rax)
mov    $0x44e00504,%eax
mov    (%rax),%ecx
or     $0x1,%ecx
mov    $0x44e00504,%eax
mov    %ecx,(%rax)
mov    $0x44e00504,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x1,%eax
je     1233 <DMTimer7ModuleClkConfig+0x133>
jmp    121b <DMTimer7ModuleClkConfig+0x11b>
mov    $0x44e0007c,%eax
mov    (%rax),%ecx
or     $0x2,%ecx
mov    $0x44e0007c,%eax
mov    %ecx,(%rax)
mov    $0x44e0007c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     125c <DMTimer7ModuleClkConfig+0x15c>
jmp    1244 <DMTimer7ModuleClkConfig+0x144>
jmp    1261 <DMTimer7ModuleClkConfig+0x161>
mov    $0x44e0007c,%eax
mov    (%rax),%eax
and    $0x30000,%eax
cmp    $0x0,%eax
je     127b <DMTimer7ModuleClkConfig+0x17b>
jmp    1261 <DMTimer7ModuleClkConfig+0x161>
jmp    1280 <DMTimer7ModuleClkConfig+0x180>
mov    $0x44e00004,%eax
mov    (%rax),%eax
and    $0x8,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    129f <DMTimer7ModuleClkConfig+0x19f>
jmp    12a4 <DMTimer7ModuleClkConfig+0x1a4>
jmp    1280 <DMTimer7ModuleClkConfig+0x180>
jmp    12a9 <DMTimer7ModuleClkConfig+0x1a9>
mov    $0x44e0000c,%eax
mov    (%rax),%eax
and    $0x10,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    12c8 <DMTimer7ModuleClkConfig+0x1c8>
jmp    12cd <DMTimer7ModuleClkConfig+0x1cd>
jmp    12a9 <DMTimer7ModuleClkConfig+0x1a9>
jmp    12d2 <DMTimer7ModuleClkConfig+0x1d2>
mov    $0x44e0012c,%eax
mov    (%rax),%eax
and    $0x30,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    12f1 <DMTimer7ModuleClkConfig+0x1f1>
jmp    12f6 <DMTimer7ModuleClkConfig+0x1f6>
jmp    12d2 <DMTimer7ModuleClkConfig+0x1d2>
jmp    12fb <DMTimer7ModuleClkConfig+0x1fb>
mov    $0x44e00000,%eax
mov    (%rax),%eax
and    $0x2100,%eax
cmp    $0x0,%eax
setne  %al
xor    $0xff,%al
test   $0x1,%al
jne    131c <DMTimer7ModuleClkConfig+0x21c>
jmp    1321 <DMTimer7ModuleClkConfig+0x221>
jmp    12fb <DMTimer7ModuleClkConfig+0x1fb>
pop    %rbp
ret

x86 assembly (clang, -O2):
<DMTimer7ModuleClkConfig>:
movl   $0x2,0x44e00004
nopl   0x0(%rax,%rax,1)
mov    0x44e00004,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1110 <DMTimer7ModuleClkConfig+0x10>
movl   $0x2,0x44e0000c
nopw   0x0(%rax,%rax,1)
mov    0x44e0000c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1130 <DMTimer7ModuleClkConfig+0x30>
movl   $0x2,0x44e000dc
nopw   0x0(%rax,%rax,1)
mov    0x44e000dc,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1150 <DMTimer7ModuleClkConfig+0x50>
movl   $0x2,0x44e000e0
nopw   0x0(%rax,%rax,1)
mov    0x44e000e0,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1170 <DMTimer7ModuleClkConfig+0x70>
movl   $0x2,0x44e0012c
nopw   0x0(%rax,%rax,1)
mov    0x44e0012c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1190 <DMTimer7ModuleClkConfig+0x90>
movl   $0x2,0x44e00000
nopw   0x0(%rax,%rax,1)
mov    0x44e00000,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11b0 <DMTimer7ModuleClkConfig+0xb0>
movl   $0x2,0x44e00060
nopw   0x0(%rax,%rax,1)
mov    0x44e00060,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11d0 <DMTimer7ModuleClkConfig+0xd0>
andl   $0xfffffffc,0x44e00504
fc
orl    $0x1,0x44e00504
01
nop
mov    0x44e00504,%eax
and    $0x3,%eax
cmp    $0x1,%eax
jne    11f0 <DMTimer7ModuleClkConfig+0xf0>
orl    $0x2,0x44e0007c
02
nopw   0x0(%rax,%rax,1)
mov    0x44e0007c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1210 <DMTimer7ModuleClkConfig+0x110>
nop
testl  $0x30000,0x44e0007c
jne    1220 <DMTimer7ModuleClkConfig+0x120>
nopl   (%rax)
testl  $0x8,0x44e00004
je     1230 <DMTimer7ModuleClkConfig+0x130>
nopl   (%rax)
testl  $0x10,0x44e0000c
je     1240 <DMTimer7ModuleClkConfig+0x140>
nopl   (%rax)
testl  $0x30,0x44e0012c
je     1250 <DMTimer7ModuleClkConfig+0x150>
nopl   (%rax)
testl  $0x2100,0x44e00000
je     1260 <DMTimer7ModuleClkConfig+0x160>
ret

LLVM IR (-O0):
define void @DMTimer7ModuleClkConfig() {
store volatile i32 2, i32* inttoptr (i64 1155530756 to i32*)
br label %1
1: ; preds = %5, %0
%2 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%3 = and i32 %2, 3
%4 = icmp ne i32 %3, 2
br i1 %4, label %5, label %6
5: ; preds = %1
br label %1
6: ; preds = %1
store volatile i32 2, i32* inttoptr (i64 1155530764 to i32*)
br label %7
7: ; preds = %11, %6
%8 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%9 = and i32 %8, 3
%10 = icmp ne i32 %9, 2
br i1 %10, label %11, label %12
11: ; preds = %7
br label %7
12: ; preds = %7
store volatile i32 2, i32* inttoptr (i64 1155530972 to i32*)
br label %13
13: ; preds = %17, %12
%14 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%15 = and i32 %14, 3
%16 = icmp ne i32 %15, 2
br i1 %16, label %17, label %18
17: ; preds = %13
br label %13
18: ; preds = %13
store volatile i32 2, i32* inttoptr (i64 1155530976 to i32*)
br label %19
19: ; preds = %23, %18
%20 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%21 = and i32 %20, 3
%22 = icmp ne i32 %21, 2
br i1 %22, label %23, label %24
23: ; preds = %19
br label %19
24: ; preds = %19
store volatile i32 2, i32* inttoptr (i64 1155531052 to i32*)
br label %25
25: ; preds = %29, %24
%26 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%27 = and i32 %26, 3
%28 = icmp ne i32 %27, 2
br i1 %28, label %29, label %30
29: ; preds = %25
br label %25
30: ; preds = %25
store volatile i32 2, i32* inttoptr (i64 1155530752 to i32*)
br label %31
31: ; preds = %35, %30
%32 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%33 = and i32 %32, 3
%34 = icmp ne i32 %33, 2
br i1 %34, label %35, label %36
35: ; preds = %31
br label %31
36: ; preds = %31
store volatile i32 2, i32* inttoptr (i64 1155530848 to i32*)
br label %37
37: ; preds = %41, %36
%38 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%39 = and i32 %38, 3
%40 = icmp ne i32 %39, 2
br i1 %40, label %41, label %42
41: ; preds = %37
br label %37
42: ; preds = %37
%43 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%44 = and i32 %43, -4
store volatile i32 %44, i32* inttoptr (i64 1155532036 to i32*)
%45 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%46 = or i32 %45, 1
store volatile i32 %46, i32* inttoptr (i64 1155532036 to i32*)
br label %47
47: ; preds = %51, %42
%48 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%49 = and i32 %48, 3
%50 = icmp ne i32 %49, 1
br i1 %50, label %51, label %52
51: ; preds = %47
br label %47
52: ; preds = %47
%53 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%54 = or i32 %53, 2
store volatile i32 %54, i32* inttoptr (i64 1155530876 to i32*)
br label %55
55: ; preds = %59, %52
%56 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%57 = and i32 %56, 3
%58 = icmp ne i32 %57, 2
br i1 %58, label %59, label %60
59: ; preds = %55
br label %55
60: ; preds = %55
br label %61
61: ; preds = %65, %60
%62 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%63 = and i32 %62, 196608
%64 = icmp ne i32 %63, 0
br i1 %64, label %65, label %66
65: ; preds = %61
br label %61
66: ; preds = %61
br label %67
67: ; preds = %72, %66
%68 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%69 = and i32 %68, 8
%70 = icmp ne i32 %69, 0
%71 = xor i1 %70, true
br i1 %71, label %72, label %73
72: ; preds = %67
br label %67
73: ; preds = %67
br label %74
74: ; preds = %79, %73
%75 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%76 = and i32 %75, 16
%77 = icmp ne i32 %76, 0
%78 = xor i1 %77, true
br i1 %78, label %79, label %80
79: ; preds = %74
br label %74
80: ; preds = %74
br label %81
81: ; preds = %86, %80
%82 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%83 = and i32 %82, 48
%84 = icmp ne i32 %83, 0
%85 = xor i1 %84, true
br i1 %85, label %86, label %87
86: ; preds = %81
br label %81
87: ; preds = %81
br label %88
88: ; preds = %93, %87
%89 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%90 = and i32 %89, 8448
%91 = icmp ne i32 %90, 0
%92 = xor i1 %91, true
br i1 %92, label %93, label %94
93: ; preds = %88
br label %88
94: ; preds = %88
ret void
}

LLVM IR (-O2):
define void @DMTimer7ModuleClkConfig() {
store volatile i32 2, i32* inttoptr (i64 1155530756 to i32*)
br label %1
1: ; preds = %1, %0
%2 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%3 = and i32 %2, 3
%4 = icmp eq i32 %3, 2
br i1 %4, label %5, label %1
5: ; preds = %1
store volatile i32 2, i32* inttoptr (i64 1155530764 to i32*)
br label %6
6: ; preds = %6, %5
%7 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%8 = and i32 %7, 3
%9 = icmp eq i32 %8, 2
br i1 %9, label %10, label %6
10: ; preds = %6
store volatile i32 2, i32* inttoptr (i64 1155530972 to i32*)
br label %11
11: ; preds = %11, %10
%12 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%13 = and i32 %12, 3
%14 = icmp eq i32 %13, 2
br i1 %14, label %15, label %11
15: ; preds = %11
store volatile i32 2, i32* inttoptr (i64 1155530976 to i32*)
br label %16
16: ; preds = %16, %15
%17 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%18 = and i32 %17, 3
%19 = icmp eq i32 %18, 2
br i1 %19, label %20, label %16
20: ; preds = %16
store volatile i32 2, i32* inttoptr (i64 1155531052 to i32*)
br label %21
21: ; preds = %21, %20
%22 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%23 = and i32 %22, 3
%24 = icmp eq i32 %23, 2
br i1 %24, label %25, label %21
25: ; preds = %21
store volatile i32 2, i32* inttoptr (i64 1155530752 to i32*)
br label %26
26: ; preds = %26, %25
%27 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%28 = and i32 %27, 3
%29 = icmp eq i32 %28, 2
br i1 %29, label %30, label %26
30: ; preds = %26
store volatile i32 2, i32* inttoptr (i64 1155530848 to i32*)
br label %31
31: ; preds = %31, %30
%32 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%33 = and i32 %32, 3
%34 = icmp eq i32 %33, 2
br i1 %34, label %35, label %31
35: ; preds = %31
%36 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%37 = and i32 %36, -4
store volatile i32 %37, i32* inttoptr (i64 1155532036 to i32*)
%38 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%39 = or i32 %38, 1
store volatile i32 %39, i32* inttoptr (i64 1155532036 to i32*)
br label %40
40: ; preds = %40, %35
%41 = load volatile i32, i32* inttoptr (i64 1155532036 to i32*)
%42 = and i32 %41, 3
%43 = icmp eq i32 %42, 1
br i1 %43, label %44, label %40
44: ; preds = %40
%45 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%46 = or i32 %45, 2
store volatile i32 %46, i32* inttoptr (i64 1155530876 to i32*)
br label %47
47: ; preds = %47, %44
%48 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%49 = and i32 %48, 3
%50 = icmp eq i32 %49, 2
br i1 %50, label %51, label %47
51: ; preds = %47, %51
%52 = load volatile i32, i32* inttoptr (i64 1155530876 to i32*)
%53 = and i32 %52, 196608
%54 = icmp eq i32 %53, 0
br i1 %54, label %55, label %51
55: ; preds = %51, %55
%56 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%57 = and i32 %56, 8
%58 = icmp eq i32 %57, 0
br i1 %58, label %55, label %59
59: ; preds = %55, %59
%60 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%61 = and i32 %60, 16
%62 = icmp eq i32 %61, 0
br i1 %62, label %59, label %63
63: ; preds = %59, %63
%64 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%65 = and i32 %64, 48
%66 = icmp eq i32 %65, 0
br i1 %66, label %63, label %67
67: ; preds = %63, %67
%68 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%69 = and i32 %68, 8448
%70 = icmp eq i32 %69, 0
br i1 %70, label %67, label %71
71: ; preds = %67
ret void
}