#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
unsigned char Diss_Index_Get8BitRegCount(unsigned char);
int /*<<< orphan*/ Diss_Index_IsReg8Bit(unsigned char);
int /*<<< orphan*/ Diss_Index_IsRegIndex(unsigned char);
unsigned char Z80_RD_MEM(int);
int Diss_Index_GetOpcodeCountForInstruction(int DisAddr) {
  unsigned char Opcode;
  Opcode = Z80_RD_MEM(DisAddr);
  DisAddr++;
  switch (Opcode) {
  case 0x0dd:
  case 0x0fd:
  case 0x0ed:
    return 1;
  case 0x0cb:
    return 4;
  default: {
    switch (Opcode & 0x0c0) {
    case 0x000: {
      switch (Opcode & 0x07) {
      case 1: {
        if ((Opcode & 0x08) != 0) {
          return 2;
        } else {
          if (Diss_Index_IsRegIndex((Opcode >> 4) & 0x03)) {
            return 4;
          }
        }
      } break;
      case 2: {
        switch ((Opcode >> 4) & 0x03) {
        case 2:
          return 4;
        default:
          break;
        }
      } break;
      case 3: {
        if (Diss_Index_IsRegIndex((Opcode >> 4) & 0x03))
          return 2;
      } break;
      case 4:
      case 5: {
        unsigned char OpcodeIndex;
        OpcodeIndex = ((Opcode >> 3) & 0x07);
        if (Diss_Index_IsReg8Bit(OpcodeIndex))
          return Diss_Index_Get8BitRegCount(OpcodeIndex) + 1;
      } break;
      case 6: {
        unsigned char OpcodeIndex;
        OpcodeIndex = (Opcode >> 3) & 0x07;
        if (Diss_Index_IsReg8Bit(OpcodeIndex))
          return Diss_Index_Get8BitRegCount(OpcodeIndex) + 2;
      } break;
      default:
        break;
      }
    } break;
    case 0x040: {
      if (Opcode != 0x076) {
        unsigned char Reg1, Reg2;
        Reg1 = (Opcode >> 3) & 0x07;
        Reg2 = Opcode & 0x07;
        if (Diss_Index_IsReg8Bit(Reg1) || Diss_Index_IsReg8Bit(Reg2)) {
          unsigned char Length1, Length2;
          Length1 = Diss_Index_Get8BitRegCount(Reg1);
          Length2 = Diss_Index_Get8BitRegCount(Reg2);
          if (Length1 < Length2) {
            return Length2 + 1;
          }
          return Length1 + 1;
        }
      }
    } break;
    case 0x080: {
      unsigned char OpcodeIndex;
      OpcodeIndex = (Opcode & 0x07);
      if (Diss_Index_IsReg8Bit(OpcodeIndex))
        return Diss_Index_Get8BitRegCount(OpcodeIndex) + 1;
    } break;
    case 0x0c0: {
      switch (Opcode & 0x07) {
      case 1: {
        if ((Opcode & (1 << 3)) == 0) {
          if (Diss_Index_IsRegIndex((Opcode >> 4) & 0x03))
            return 2;
        } else {
          if ((Opcode == 0x0f9) || (Opcode == 0x0e9))
            return 2;
        }
      } break;
      case 3: {
        if ((Opcode & (3 << 4)) == (1 << 4)) {
        } else if (Opcode == 0x0c3) {
        } else {
          if (Opcode == 0x0e3)
            return 2;
        }
      } break;
      case 5: {
        if ((Opcode & (1 << 3)) == 0) {
          if (Diss_Index_IsRegIndex((Opcode >> 4) & 0x03))
            return 2;
        }
      } break;
      default:
        break;
      }
    } break;
    }
  } break;
  }
  return 1;
}


x86 assembly (clang, -O0):
<Diss_Index_GetOpcodeCountForInstruction>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x8(%rbp)
mov    -0x8(%rbp),%edi
call   1060 <Z80_RD_MEM@plt>
mov    %al,-0x9(%rbp)
mov    -0x8(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x8(%rbp)
movzbl -0x9(%rbp),%eax
mov    %eax,-0x14(%rbp)
sub    $0xcb,%eax
je     11bb <Diss_Index_GetOpcodeCountForInstruction+0x7b>
jmp    1176 <Diss_Index_GetOpcodeCountForInstruction+0x36>
mov    -0x14(%rbp),%eax
sub    $0xdd,%eax
je     11af <Diss_Index_GetOpcodeCountForInstruction+0x6f>
jmp    1189 <Diss_Index_GetOpcodeCountForInstruction+0x49>
mov    -0x14(%rbp),%eax
sub    $0xed,%eax
je     11af <Diss_Index_GetOpcodeCountForInstruction+0x6f>
jmp    119c <Diss_Index_GetOpcodeCountForInstruction+0x5c>
mov    -0x14(%rbp),%eax
sub    $0xfd,%eax
jne    11c7 <Diss_Index_GetOpcodeCountForInstruction+0x87>
jmp    11af <Diss_Index_GetOpcodeCountForInstruction+0x6f>
movl   $0x1,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
movl   $0x4,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
movzbl -0x9(%rbp),%eax
and    $0xc0,%eax
mov    %eax,-0x18(%rbp)
je     1215 <Diss_Index_GetOpcodeCountForInstruction+0xd5>
jmp    11de <Diss_Index_GetOpcodeCountForInstruction+0x9e>
mov    -0x18(%rbp),%eax
sub    $0x40,%eax
je     1369 <Diss_Index_GetOpcodeCountForInstruction+0x229>
jmp    11ef <Diss_Index_GetOpcodeCountForInstruction+0xaf>
mov    -0x18(%rbp),%eax
sub    $0x80,%eax
je     1401 <Diss_Index_GetOpcodeCountForInstruction+0x2c1>
jmp    1202 <Diss_Index_GetOpcodeCountForInstruction+0xc2>
mov    -0x18(%rbp),%eax
sub    $0xc0,%eax
je     1439 <Diss_Index_GetOpcodeCountForInstruction+0x2f9>
jmp    1581 <Diss_Index_GetOpcodeCountForInstruction+0x441>
movzbl -0x9(%rbp),%eax
and    $0x7,%eax
add    $0xffffffff,%eax
mov    %eax,%ecx
mov    %rcx,-0x20(%rbp)
sub    $0x5,%eax
ja     135f <Diss_Index_GetOpcodeCountForInstruction+0x21f>
mov    -0x20(%rbp),%rax
lea    0xdc7(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
movzbl -0x9(%rbp),%eax
and    $0x8,%eax
cmp    $0x0,%eax
je     125e <Diss_Index_GetOpcodeCountForInstruction+0x11e>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
movzbl -0x9(%rbp),%eax
sar    $0x4,%eax
and    $0x3,%eax
movzbl %al,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
cmp    $0x0,%eax
je     1285 <Diss_Index_GetOpcodeCountForInstruction+0x145>
movl   $0x4,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    128a <Diss_Index_GetOpcodeCountForInstruction+0x14a>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
movzbl -0x9(%rbp),%eax
shr    $0x4,%eax
and    $0x3,%eax
sub    $0x2,%eax
jne    12b3 <Diss_Index_GetOpcodeCountForInstruction+0x173>
jmp    12a7 <Diss_Index_GetOpcodeCountForInstruction+0x167>
movl   $0x4,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    12b8 <Diss_Index_GetOpcodeCountForInstruction+0x178>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
movzbl -0x9(%rbp),%eax
sar    $0x4,%eax
and    $0x3,%eax
movzbl %al,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
cmp    $0x0,%eax
je     12e4 <Diss_Index_GetOpcodeCountForInstruction+0x1a4>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
movzbl -0x9(%rbp),%eax
sar    $0x3,%eax
and    $0x7,%eax
mov    %al,-0xa(%rbp)
movzbl -0xa(%rbp),%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
cmp    $0x0,%eax
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
movzbl -0xa(%rbp),%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
movzbl %al,%eax
add    $0x1,%eax
mov    %eax,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
movzbl -0x9(%rbp),%eax
sar    $0x3,%eax
and    $0x7,%eax
mov    %al,-0xb(%rbp)
movzbl -0xb(%rbp),%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
cmp    $0x0,%eax
je     135a <Diss_Index_GetOpcodeCountForInstruction+0x21a>
movzbl -0xb(%rbp),%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
movzbl %al,%eax
add    $0x2,%eax
mov    %eax,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
jmp    1364 <Diss_Index_GetOpcodeCountForInstruction+0x224>
jmp    1581 <Diss_Index_GetOpcodeCountForInstruction+0x441>
movzbl -0x9(%rbp),%eax
cmp    $0x76,%eax
je     13fc <Diss_Index_GetOpcodeCountForInstruction+0x2bc>
movzbl -0x9(%rbp),%eax
sar    $0x3,%eax
and    $0x7,%eax
mov    %al,-0xc(%rbp)
movzbl -0x9(%rbp),%eax
and    $0x7,%eax
mov    %al,-0xd(%rbp)
movzbl -0xc(%rbp),%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
cmp    $0x0,%eax
jne    13b1 <Diss_Index_GetOpcodeCountForInstruction+0x271>
movzbl -0xd(%rbp),%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
cmp    $0x0,%eax
je     13f7 <Diss_Index_GetOpcodeCountForInstruction+0x2b7>
movzbl -0xc(%rbp),%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
mov    %al,-0xe(%rbp)
movzbl -0xd(%rbp),%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
mov    %al,-0xf(%rbp)
movzbl -0xe(%rbp),%eax
movzbl -0xf(%rbp),%ecx
cmp    %ecx,%eax
jge    13e8 <Diss_Index_GetOpcodeCountForInstruction+0x2a8>
movzbl -0xf(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
movzbl -0xe(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    13fc <Diss_Index_GetOpcodeCountForInstruction+0x2bc>
jmp    1581 <Diss_Index_GetOpcodeCountForInstruction+0x441>
movzbl -0x9(%rbp),%eax
and    $0x7,%eax
mov    %al,-0x10(%rbp)
movzbl -0x10(%rbp),%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
cmp    $0x0,%eax
je     1434 <Diss_Index_GetOpcodeCountForInstruction+0x2f4>
movzbl -0x10(%rbp),%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
movzbl %al,%eax
add    $0x1,%eax
mov    %eax,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    1581 <Diss_Index_GetOpcodeCountForInstruction+0x441>
movzbl -0x9(%rbp),%eax
and    $0x7,%eax
mov    %eax,-0x24(%rbp)
sub    $0x1,%eax
je     1473 <Diss_Index_GetOpcodeCountForInstruction+0x333>
jmp    1451 <Diss_Index_GetOpcodeCountForInstruction+0x311>
mov    -0x24(%rbp),%eax
sub    $0x3,%eax
je     14e3 <Diss_Index_GetOpcodeCountForInstruction+0x3a3>
jmp    1462 <Diss_Index_GetOpcodeCountForInstruction+0x322>
mov    -0x24(%rbp),%eax
sub    $0x5,%eax
je     1536 <Diss_Index_GetOpcodeCountForInstruction+0x3f6>
jmp    1577 <Diss_Index_GetOpcodeCountForInstruction+0x437>
movzbl -0x9(%rbp),%eax
and    $0x8,%eax
cmp    $0x0,%eax
jne    14af <Diss_Index_GetOpcodeCountForInstruction+0x36f>
movzbl -0x9(%rbp),%eax
sar    $0x4,%eax
and    $0x3,%eax
movzbl %al,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
cmp    $0x0,%eax
je     14aa <Diss_Index_GetOpcodeCountForInstruction+0x36a>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    14de <Diss_Index_GetOpcodeCountForInstruction+0x39e>
movzbl -0x9(%rbp),%eax
cmp    $0xf9,%eax
je     14cd <Diss_Index_GetOpcodeCountForInstruction+0x38d>
movzbl -0x9(%rbp),%eax
cmp    $0xe9,%eax
jne    14d9 <Diss_Index_GetOpcodeCountForInstruction+0x399>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    14de <Diss_Index_GetOpcodeCountForInstruction+0x39e>
jmp    157c <Diss_Index_GetOpcodeCountForInstruction+0x43c>
movzbl -0x9(%rbp),%eax
and    $0x30,%eax
cmp    $0x10,%eax
jne    14f8 <Diss_Index_GetOpcodeCountForInstruction+0x3b8>
jmp    1531 <Diss_Index_GetOpcodeCountForInstruction+0x3f1>
movzbl -0x9(%rbp),%eax
cmp    $0xc3,%eax
jne    150c <Diss_Index_GetOpcodeCountForInstruction+0x3cc>
jmp    152c <Diss_Index_GetOpcodeCountForInstruction+0x3ec>
movzbl -0x9(%rbp),%eax
cmp    $0xe3,%eax
jne    1527 <Diss_Index_GetOpcodeCountForInstruction+0x3e7>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    152c <Diss_Index_GetOpcodeCountForInstruction+0x3ec>
jmp    1531 <Diss_Index_GetOpcodeCountForInstruction+0x3f1>
jmp    157c <Diss_Index_GetOpcodeCountForInstruction+0x43c>
movzbl -0x9(%rbp),%eax
and    $0x8,%eax
cmp    $0x0,%eax
jne    1572 <Diss_Index_GetOpcodeCountForInstruction+0x432>
movzbl -0x9(%rbp),%eax
sar    $0x4,%eax
and    $0x3,%eax
movzbl %al,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
cmp    $0x0,%eax
je     156d <Diss_Index_GetOpcodeCountForInstruction+0x42d>
movl   $0x2,-0x4(%rbp)
jmp    158d <Diss_Index_GetOpcodeCountForInstruction+0x44d>
jmp    1572 <Diss_Index_GetOpcodeCountForInstruction+0x432>
jmp    157c <Diss_Index_GetOpcodeCountForInstruction+0x43c>
jmp    157c <Diss_Index_GetOpcodeCountForInstruction+0x43c>
jmp    1581 <Diss_Index_GetOpcodeCountForInstruction+0x441>
jmp    1586 <Diss_Index_GetOpcodeCountForInstruction+0x446>
movl   $0x1,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<Diss_Index_GetOpcodeCountForInstruction>:
push   %rbp
push   %r14
push   %rbx
call   1060 <Z80_RD_MEM@plt>
mov    %eax,%ebx
mov    $0x1,%eax
cmp    $0xec,%bl
jg     1165 <Diss_Index_GetOpcodeCountForInstruction+0x25>
cmp    $0xcb,%bl
je     11cc <Diss_Index_GetOpcodeCountForInstruction+0x8c>
cmp    $0xdd,%bl
je     1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
jmp    1177 <Diss_Index_GetOpcodeCountForInstruction+0x37>
cmp    $0xed,%bl
je     1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
cmp    $0xfd,%bl
je     1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
movzbl %bl,%edi
mov    %edi,%eax
shr    $0x6,%eax
lea    0xe7a(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    %edi,%eax
and    $0x7,%eax
add    $0xffffffff,%eax
cmp    $0x5,%eax
ja     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
lea    0xe69(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
shr    $0x3,%bl
and    $0x7,%bl
movzbl %bl,%ebx
mov    %ebx,%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
test   %eax,%eax
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    %ebx,%edi
jmp    1248 <Diss_Index_GetOpcodeCountForInstruction+0x108>
mov    $0x4,%eax
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
cmp    $0x76,%bl
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    %ebx,%eax
shr    $0x3,%al
and    $0x7,%al
and    $0x7,%bl
movzbl %al,%ebp
mov    %ebp,%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
movzbl %bl,%r14d
test   %eax,%eax
jne    120b <Diss_Index_GetOpcodeCountForInstruction+0xcb>
mov    %r14d,%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
test   %eax,%eax
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    %ebp,%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
mov    %eax,%ebx
mov    %r14d,%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
cmp    %al,%bl
movzbl %bl,%ecx
movzbl %al,%eax
cmovae %ecx,%eax
movzbl %al,%eax
add    $0x1,%eax
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
and    $0x7,%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
test   %eax,%eax
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
and    $0x7,%bl
movzbl %bl,%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
movzbl %al,%eax
add    $0x1,%eax
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
mov    %edi,%eax
and    $0x7,%eax
cmp    $0x5,%eax
je     128b <Diss_Index_GetOpcodeCountForInstruction+0x14b>
cmp    $0x3,%eax
je     12af <Diss_Index_GetOpcodeCountForInstruction+0x16f>
cmp    $0x1,%eax
jne    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
test   $0x8,%bl
je     1294 <Diss_Index_GetOpcodeCountForInstruction+0x154>
and    $0xef,%bl
mov    $0x2,%eax
cmp    $0xe9,%bl
jne    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
test   $0x8,%bl
jne    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
shr    $0x4,%bl
and    $0x3,%bl
movzbl %bl,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
mov    %eax,%ecx
mov    $0x2,%eax
test   %ecx,%ecx
jne    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
jmp    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
and    $0x30,%edi
cmp    $0x10,%edi
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
cmp    $0xc3,%bl
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    $0x2,%eax
cmp    $0xe3,%bl
je     1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
jmp    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    $0x2,%eax
test   $0x8,%bl
jne    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
shr    $0x4,%bl
and    $0x3,%bl
movzbl %bl,%edi
call   1040 <Diss_Index_IsRegIndex@plt>
mov    %eax,%ecx
mov    $0x4,%eax
test   %ecx,%ecx
jne    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
jmp    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
and    $0x30,%edi
mov    $0x4,%eax
cmp    $0x20,%edi
jne    131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
shr    $0x3,%bl
and    $0x7,%bl
movzbl %bl,%ebx
mov    %ebx,%edi
call   1030 <Diss_Index_IsReg8Bit@plt>
test   %eax,%eax
je     131f <Diss_Index_GetOpcodeCountForInstruction+0x1df>
mov    %ebx,%edi
call   1050 <Diss_Index_Get8BitRegCount@plt>
movzbl %al,%eax
add    $0x2,%eax
jmp    1324 <Diss_Index_GetOpcodeCountForInstruction+0x1e4>
mov    $0x1,%eax
pop    %rbx
pop    %r14
pop    %rbp
ret

LLVM IR (-O0):
define i32 @Diss_Index_GetOpcodeCountForInstruction(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i8
%5 = alloca i8
%6 = alloca i8
%7 = alloca i8
%8 = alloca i8
%9 = alloca i8
%10 = alloca i8
%11 = alloca i8
store i32 %0, i32* %3
%12 = load i32, i32* %3
%13 = call zeroext i8 @Z80_RD_MEM(i32 %12)
store i8 %13, i8* %4
%14 = load i32, i32* %3
%15 = add nsw i32 %14, 1
store i32 %15, i32* %3
%16 = load i8, i8* %4
%17 = zext i8 %16 to i32
switch i32 %17, label %20 [
i32 221, label %18
i32 253, label %18
i32 237, label %18
i32 203, label %19
]
18: ; preds = %1, %1, %1
store i32 1, i32* %2
br label %219
19: ; preds = %1
store i32 4, i32* %2
br label %219
20: ; preds = %1
%21 = load i8, i8* %4
%22 = zext i8 %21 to i32
%23 = and i32 %22, 192
switch i32 %23, label %217 [
i32 0, label %24
i32 64, label %95
i32 128, label %136
i32 192, label %150
]
24: ; preds = %20
%25 = load i8, i8* %4
%26 = zext i8 %25 to i32
%27 = and i32 %26, 7
switch i32 %27, label %93 [
i32 1, label %28
i32 2, label %45
i32 3, label %53
i32 4, label %63
i32 5, label %63
i32 6, label %78
]
28: ; preds = %24
%29 = load i8, i8* %4
%30 = zext i8 %29 to i32
%31 = and i32 %30, 8
%32 = icmp ne i32 %31, 0
br i1 %32, label %33, label %34
33: ; preds = %28
store i32 2, i32* %2
br label %219
34: ; preds = %28
%35 = load i8, i8* %4
%36 = zext i8 %35 to i32
%37 = ashr i32 %36, 4
%38 = and i32 %37, 3
%39 = trunc i32 %38 to i8
%40 = call i32 @Diss_Index_IsRegIndex(i8 zeroext %39)
%41 = icmp ne i32 %40, 0
br i1 %41, label %42, label %43
42: ; preds = %34
store i32 4, i32* %2
br label %219
43: ; preds = %34
br label %44
44: ; preds = %43
br label %94
45: ; preds = %24
%46 = load i8, i8* %4
%47 = zext i8 %46 to i32
%48 = ashr i32 %47, 4
%49 = and i32 %48, 3
switch i32 %49, label %51 [
i32 2, label %50
]
50: ; preds = %45
store i32 4, i32* %2
br label %219
51: ; preds = %45
br label %52
52: ; preds = %51
br label %94
53: ; preds = %24
%54 = load i8, i8* %4
%55 = zext i8 %54 to i32
%56 = ashr i32 %55, 4
%57 = and i32 %56, 3
%58 = trunc i32 %57 to i8
%59 = call i32 @Diss_Index_IsRegIndex(i8 zeroext %58)
%60 = icmp ne i32 %59, 0
br i1 %60, label %61, label %62
61: ; preds = %53
store i32 2, i32* %2
br label %219
62: ; preds = %53
br label %94
63: ; preds = %24, %24
%64 = load i8, i8* %4
%65 = zext i8 %64 to i32
%66 = ashr i32 %65, 3
%67 = and i32 %66, 7
%68 = trunc i32 %67 to i8
store i8 %68, i8* %5
%69 = load i8, i8* %5
%70 = call i32 @Diss_Index_IsReg8Bit(i8 zeroext %69)
%71 = icmp ne i32 %70, 0
br i1 %71, label %72, label %77
72: ; preds = %63
%73 = load i8, i8* %5
%74 = call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %73)
%75 = zext i8 %74 to i32
%76 = add nsw i32 %75, 1
store i32 %76, i32* %2
br label %219
77: ; preds = %63
br label %94
78: ; preds = %24
%79 = load i8, i8* %4
%80 = zext i8 %79 to i32
%81 = ashr i32 %80, 3
%82 = and i32 %81, 7
%83 = trunc i32 %82 to i8
store i8 %83, i8* %6
%84 = load i8, i8* %6
%85 = call i32 @Diss_Index_IsReg8Bit(i8 zeroext %84)
%86 = icmp ne i32 %85, 0
br i1 %86, label %87, label %92
87: ; preds = %78
%88 = load i8, i8* %6
%89 = call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %88)
%90 = zext i8 %89 to i32
%91 = add nsw i32 %90, 2
store i32 %91, i32* %2
br label %219
92: ; preds = %78
br label %94
93: ; preds = %24
br label %94
94: ; preds = %93, %92, %77, %62, %52, %44
br label %217
95: ; preds = %20
%96 = load i8, i8* %4
%97 = zext i8 %96 to i32
%98 = icmp ne i32 %97, 118
br i1 %98, label %99, label %135
99: ; preds = %95
%100 = load i8, i8* %4
%101 = zext i8 %100 to i32
%102 = ashr i32 %101, 3
%103 = and i32 %102, 7
%104 = trunc i32 %103 to i8
store i8 %104, i8* %7
%105 = load i8, i8* %4
%106 = zext i8 %105 to i32
%107 = and i32 %106, 7
%108 = trunc i32 %107 to i8
store i8 %108, i8* %8
%109 = load i8, i8* %7
%110 = call i32 @Diss_Index_IsReg8Bit(i8 zeroext %109)
%111 = icmp ne i32 %110, 0
br i1 %111, label %116, label %112
112: ; preds = %99
%113 = load i8, i8* %8
%114 = call i32 @Diss_Index_IsReg8Bit(i8 zeroext %113)
%115 = icmp ne i32 %114, 0
br i1 %115, label %116, label %134
116: ; preds = %112, %99
%117 = load i8, i8* %7
%118 = call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %117)
store i8 %118, i8* %9
%119 = load i8, i8* %8
%120 = call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %119)
store i8 %120, i8* %10
%121 = load i8, i8* %9
%122 = zext i8 %121 to i32
%123 = load i8, i8* %10
%124 = zext i8 %123 to i32
%125 = icmp slt i32 %122, %124
br i1 %125, label %126, label %130
126: ; preds = %116
%127 = load i8, i8* %10
%128 = zext i8 %127 to i32
%129 = add nsw i32 %128, 1
store i32 %129, i32* %2
br label %219
130: ; preds = %116
%131 = load i8, i8* %9
%132 = zext i8 %131 to i32
%133 = add nsw i32 %132, 1
store i32 %133, i32* %2
br label %219
134: ; preds = %112
br label %135
135: ; preds = %134, %95
br label %217
136: ; preds = %20
%137 = load i8, i8* %4
%138 = zext i8 %137 to i32
%139 = and i32 %138, 7
%140 = trunc i32 %139 to i8
store i8 %140, i8* %11
%141 = load i8, i8* %11
%142 = call i32 @Diss_Index_IsReg8Bit(i8 zeroext %141)
%143 = icmp ne i32 %142, 0
br i1 %143, label %144, label %149
144: ; preds = %136
%145 = load i8, i8* %11
%146 = call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %145)
%147 = zext i8 %146 to i32
%148 = add nsw i32 %147, 1
store i32 %148, i32* %2
br label %219
149: ; preds = %136
br label %217
150: ; preds = %20
%151 = load i8, i8* %4
%152 = zext i8 %151 to i32
%153 = and i32 %152, 7
switch i32 %153, label %215 [
i32 1, label %154
i32 3, label %180
i32 5, label %199
]
154: ; preds = %150
%155 = load i8, i8* %4
%156 = zext i8 %155 to i32
%157 = and i32 %156, 8
%158 = icmp eq i32 %157, 0
br i1 %158, label %159, label %169
159: ; preds = %154
%160 = load i8, i8* %4
%161 = zext i8 %160 to i32
%162 = ashr i32 %161, 4
%163 = and i32 %162, 3
%164 = trunc i32 %163 to i8
%165 = call i32 @Diss_Index_IsRegIndex(i8 zeroext %164)
%166 = icmp ne i32 %165, 0
br i1 %166, label %167, label %168
167: ; preds = %159
store i32 2, i32* %2
br label %219
168: ; preds = %159
br label %179
169: ; preds = %154
%170 = load i8, i8* %4
%171 = zext i8 %170 to i32
%172 = icmp eq i32 %171, 249
br i1 %172, label %177, label %173
173: ; preds = %169
%174 = load i8, i8* %4
%175 = zext i8 %174 to i32
%176 = icmp eq i32 %175, 233
br i1 %176, label %177, label %178
177: ; preds = %173, %169
store i32 2, i32* %2
br label %219
178: ; preds = %173
br label %179
179: ; preds = %178, %168
br label %216
180: ; preds = %150
%181 = load i8, i8* %4
%182 = zext i8 %181 to i32
%183 = and i32 %182, 48
%184 = icmp eq i32 %183, 16
br i1 %184, label %185, label %186
185: ; preds = %180
br label %198
186: ; preds = %180
%187 = load i8, i8* %4
%188 = zext i8 %187 to i32
%189 = icmp eq i32 %188, 195
br i1 %189, label %190, label %191
190: ; preds = %186
br label %197
191: ; preds = %186
%192 = load i8, i8* %4
%193 = zext i8 %192 to i32
%194 = icmp eq i32 %193, 227
br i1 %194, label %195, label %196
195: ; preds = %191
store i32 2, i32* %2
br label %219
196: ; preds = %191
br label %197
197: ; preds = %196, %190
br label %198
198: ; preds = %197, %185
br label %216
199: ; preds = %150
%200 = load i8, i8* %4
%201 = zext i8 %200 to i32
%202 = and i32 %201, 8
%203 = icmp eq i32 %202, 0
br i1 %203, label %204, label %214
204: ; preds = %199
%205 = load i8, i8* %4
%206 = zext i8 %205 to i32
%207 = ashr i32 %206, 4
%208 = and i32 %207, 3
%209 = trunc i32 %208 to i8
%210 = call i32 @Diss_Index_IsRegIndex(i8 zeroext %209)
%211 = icmp ne i32 %210, 0
br i1 %211, label %212, label %213
212: ; preds = %204
store i32 2, i32* %2
br label %219
213: ; preds = %204
br label %214
214: ; preds = %213, %199
br label %216
215: ; preds = %150
br label %216
216: ; preds = %215, %214, %198, %179
br label %217
217: ; preds = %20, %216, %149, %135, %94
br label %218
218: ; preds = %217
store i32 1, i32* %2
br label %219
219: ; preds = %218, %212, %195, %177, %167, %144, %130, %126, %87, %72, %61, %50, %42, %33, %19, %18
%220 = load i32, i32* %2
ret i32 %220
}

LLVM IR (-O2):
define i32 @Diss_Index_GetOpcodeCountForInstruction(i32 %0) {
%2 = tail call zeroext i8 @Z80_RD_MEM(i32 %0)
%3 = zext i8 %2 to i32
switch i8 %2, label %5 [
i8 -35, label %99
i8 -3, label %99
i8 -19, label %99
i8 -53, label %4
]
4: ; preds = %1
br label %99
5: ; preds = %1
%6 = lshr i32 %3, 6
switch i32 %6, label %97 [
i32 0, label %7
i32 1, label %43
i32 2, label %61
i32 3, label %69
]
7: ; preds = %5
%8 = and i32 %3, 7
switch i32 %8, label %98 [
i32 1, label %9
i32 2, label %17
i32 3, label %20
i32 4, label %25
i32 5, label %25
i32 6, label %34
]
9: ; preds = %7
%10 = and i32 %3, 8
%11 = icmp eq i32 %10, 0
br i1 %11, label %12, label %99
12: ; preds = %9
%13 = lshr i8 %2, 4
%14 = and i8 %13, 3
%15 = tail call i32 @Diss_Index_IsRegIndex(i8 zeroext %14)
%16 = icmp eq i32 %15, 0
br i1 %16, label %98, label %99
17: ; preds = %7
%18 = and i32 %3, 48
%19 = icmp eq i32 %18, 32
br i1 %19, label %99, label %98
20: ; preds = %7
%21 = lshr i8 %2, 4
%22 = and i8 %21, 3
%23 = tail call i32 @Diss_Index_IsRegIndex(i8 zeroext %22)
%24 = icmp eq i32 %23, 0
br i1 %24, label %98, label %99
25: ; preds = %7, %7
%26 = lshr i8 %2, 3
%27 = and i8 %26, 7
%28 = tail call i32 @Diss_Index_IsReg8Bit(i8 zeroext %27)
%29 = icmp eq i32 %28, 0
br i1 %29, label %98, label %30
30: ; preds = %25
%31 = tail call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %27)
%32 = zext i8 %31 to i32
%33 = add nuw nsw i32 %32, 1
br label %99
34: ; preds = %7
%35 = lshr i8 %2, 3
%36 = and i8 %35, 7
%37 = tail call i32 @Diss_Index_IsReg8Bit(i8 zeroext %36)
%38 = icmp eq i32 %37, 0
br i1 %38, label %98, label %39
39: ; preds = %34
%40 = tail call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %36)
%41 = zext i8 %40 to i32
%42 = add nuw nsw i32 %41, 2
br label %99
43: ; preds = %5
%44 = icmp eq i8 %2, 118
br i1 %44, label %98, label %45
45: ; preds = %43
%46 = lshr i8 %2, 3
%47 = and i8 %46, 7
%48 = and i8 %2, 7
%49 = tail call i32 @Diss_Index_IsReg8Bit(i8 zeroext %47)
%50 = icmp eq i32 %49, 0
br i1 %50, label %51, label %54
51: ; preds = %45
%52 = tail call i32 @Diss_Index_IsReg8Bit(i8 zeroext %48)
%53 = icmp eq i32 %52, 0
br i1 %53, label %98, label %54
54: ; preds = %45, %51
%55 = tail call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %47)
%56 = tail call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %48)
%57 = icmp ult i8 %55, %56
%58 = select i1 %57, i8 %56, i8 %55
%59 = zext i8 %58 to i32
%60 = add nuw nsw i32 %59, 1
br label %99
61: ; preds = %5
%62 = and i8 %2, 7
%63 = tail call i32 @Diss_Index_IsReg8Bit(i8 zeroext %62)
%64 = icmp eq i32 %63, 0
br i1 %64, label %98, label %65
65: ; preds = %61
%66 = tail call zeroext i8 @Diss_Index_Get8BitRegCount(i8 zeroext %62)
%67 = zext i8 %66 to i32
%68 = add nuw nsw i32 %67, 1
br label %99
69: ; preds = %5
%70 = and i32 %3, 7
switch i32 %70, label %98 [
i32 1, label %71
i32 3, label %82
i32 5, label %89
]
71: ; preds = %69
%72 = and i32 %3, 8
%73 = icmp eq i32 %72, 0
br i1 %73, label %74, label %79
74: ; preds = %71
%75 = lshr i8 %2, 4
%76 = and i8 %75, 3
%77 = tail call i32 @Diss_Index_IsRegIndex(i8 zeroext %76)
%78 = icmp eq i32 %77, 0
br i1 %78, label %98, label %99
79: ; preds = %71
%80 = and i8 %2, -17
%81 = icmp eq i8 %80, -23
br i1 %81, label %99, label %98
82: ; preds = %69
%83 = and i32 %3, 48
%84 = icmp ne i32 %83, 16
%85 = icmp ne i8 %2, -61
%86 = select i1 %84, i1 %85, i1 false
%87 = icmp eq i8 %2, -29
%88 = select i1 %86, i1 %87, i1 false
br i1 %88, label %99, label %98
89: ; preds = %69
%90 = and i32 %3, 8
%91 = icmp eq i32 %90, 0
br i1 %91, label %92, label %98
92: ; preds = %89
%93 = lshr i8 %2, 4
%94 = and i8 %93, 3
%95 = tail call i32 @Diss_Index_IsRegIndex(i8 zeroext %94)
%96 = icmp eq i32 %95, 0
br i1 %96, label %98, label %99
97: ; preds = %5
unreachable
98: ; preds = %61, %51, %34, %25, %7, %20, %17, %12, %43, %69, %89, %92, %82, %74, %79
br label %99
99: ; preds = %65, %54, %39, %30, %92, %82, %79, %74, %20, %17, %12, %9, %1, %1, %1, %98, %4
%100 = phi i32 [ 1, %98 ], [ %68, %65 ], [ %60, %54 ], [ %42, %39 ], [ %33, %30 ], [ 4, %4 ], [ 1, %1 ], [ 1, %1 ], [ 1, %1 ], [ 2, %9 ], [ 4, %12 ], [ 4, %17 ], [ 2, %20 ], [ 2, %74 ], [ 2, %79 ], [ 2, %82 ], [ 2, %92 ]
ret i32 %100
}