#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int DM_out_8(unsigned short, unsigned char);
int /*<<< orphan*/ OS_disable_interrupts(unsigned long *);
int /*<<< orphan*/ OS_enable_interrupts(unsigned long);
scalar_t__ PL_lpc_base_address();
int lpc_write_reg(unsigned int reg, unsigned long value) {
  int err;
  unsigned long ie;
  unsigned int k;
  OS_disable_interrupts(&ie);
  for (k = 0; k < 4; k++) {
    if ((reg + k) != 5) {
      err = DM_out_8((unsigned short)(PL_lpc_base_address() + reg + k),
                     (unsigned char)(value & 0xff));
      if (err) {
        OS_enable_interrupts(ie);
        return err;
      }
    }
    value >>= 8;
  }
  OS_enable_interrupts(ie);
  return 0;
}


x86 assembly (clang, -O0):
<lpc_write_reg>:
push   %rbp
mov    %rsp,%rbp
sub    $0x30,%rsp
mov    %edi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
lea    -0x20(%rbp),%rdi
call   1050 <OS_disable_interrupts@plt>
movl   $0x0,-0x24(%rbp)
cmpl   $0x4,-0x24(%rbp)
jae    11e3 <lpc_write_reg+0xa3>
mov    -0x8(%rbp),%eax
add    -0x24(%rbp),%eax
cmp    $0x5,%eax
je     11c9 <lpc_write_reg+0x89>
mov    $0x0,%al
call   1060 <PL_lpc_base_address@plt>
mov    -0x8(%rbp),%ecx
add    %rcx,%rax
mov    -0x24(%rbp),%ecx
add    %rcx,%rax
mov    %ax,%cx
mov    -0x10(%rbp),%rax
and    $0xff,%rax
movzwl %cx,%edi
movzbl %al,%esi
call   1040 <DM_out_8@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     11c4 <lpc_write_reg+0x84>
mov    -0x20(%rbp),%rdi
call   1030 <OS_enable_interrupts@plt>
mov    -0x14(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    11f3 <lpc_write_reg+0xb3>
jmp    11c9 <lpc_write_reg+0x89>
mov    -0x10(%rbp),%rax
shr    $0x8,%rax
mov    %rax,-0x10(%rbp)
mov    -0x24(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x24(%rbp)
jmp    115f <lpc_write_reg+0x1f>
mov    -0x20(%rbp),%rdi
call   1030 <OS_enable_interrupts@plt>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x30,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<lpc_write_reg>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
mov    %rsi,%r15
mov    %edi,%ebx
mov    %rsp,%rdi
call   1050 <OS_disable_interrupts@plt>
mov    %ebx,%r14d
cmp    $0x5,%ebx
jne    1184 <lpc_write_reg+0x44>
xor    %eax,%eax
call   1060 <PL_lpc_base_address@plt>
add    %r14d,%eax
add    $0x1,%eax
movzwl %ax,%edi
mov    %r15,%rax
movzbl %ah,%esi
call   1040 <DM_out_8@plt>
mov    %eax,%ebp
test   %eax,%eax
jne    11f4 <lpc_write_reg+0xb4>
cmp    $0x3,%ebx
jne    11a7 <lpc_write_reg+0x67>
jmp    11d0 <lpc_write_reg+0x90>
xor    %eax,%eax
call   1060 <PL_lpc_base_address@plt>
add    %r14d,%eax
movzwl %ax,%edi
mov    %r15,%rax
movzbl %al,%esi
call   1040 <DM_out_8@plt>
mov    %eax,%ebp
test   %eax,%eax
jne    11f4 <lpc_write_reg+0xb4>
cmp    $0x4,%ebx
jne    115c <lpc_write_reg+0x1c>
xor    %eax,%eax
call   1060 <PL_lpc_base_address@plt>
add    %r14d,%eax
add    $0x2,%eax
movzwl %ax,%edi
mov    %r15,%rax
shr    $0x10,%eax
movzbl %al,%esi
call   1040 <DM_out_8@plt>
mov    %eax,%ebp
test   %eax,%eax
jne    11f4 <lpc_write_reg+0xb4>
cmp    $0x2,%ebx
je     11f2 <lpc_write_reg+0xb2>
xor    %eax,%eax
call   1060 <PL_lpc_base_address@plt>
add    %r14d,%eax
add    $0x3,%eax
movzwl %ax,%edi
shr    $0x18,%r15d
mov    %r15d,%esi
call   1040 <DM_out_8@plt>
mov    %eax,%ebp
test   %eax,%eax
jne    11f4 <lpc_write_reg+0xb4>
xor    %ebp,%ebp
mov    (%rsp),%rdi
call   1030 <OS_enable_interrupts@plt>
mov    %ebp,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define i32 @lpc_write_reg(i32 %0, i64 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i64
%6 = alloca i32
%7 = alloca i64
%8 = alloca i32
store i32 %0, i32* %4
store i64 %1, i64* %5
%9 = call i32 @OS_disable_interrupts(i64* %7)
store i32 0, i32* %8
br label %10
10: ; preds = %41, %2
%11 = load i32, i32* %8
%12 = icmp ult i32 %11, 4
br i1 %12, label %13, label %44
13: ; preds = %10
%14 = load i32, i32* %4
%15 = load i32, i32* %8
%16 = add i32 %14, %15
%17 = icmp ne i32 %16, 5
br i1 %17, label %18, label %38
18: ; preds = %13
%19 = call i64 (...) @PL_lpc_base_address()
%20 = load i32, i32* %4
%21 = zext i32 %20 to i64
%22 = add nsw i64 %19, %21
%23 = load i32, i32* %8
%24 = zext i32 %23 to i64
%25 = add nsw i64 %22, %24
%26 = trunc i64 %25 to i16
%27 = load i64, i64* %5
%28 = and i64 %27, 255
%29 = trunc i64 %28 to i8
%30 = call i32 @DM_out_8(i16 zeroext %26, i8 zeroext %29)
store i32 %30, i32* %6
%31 = load i32, i32* %6
%32 = icmp ne i32 %31, 0
br i1 %32, label %33, label %37
33: ; preds = %18
%34 = load i64, i64* %7
%35 = call i32 @OS_enable_interrupts(i64 %34)
%36 = load i32, i32* %6
store i32 %36, i32* %3
br label %47
37: ; preds = %18
br label %38
38: ; preds = %37, %13
%39 = load i64, i64* %5
%40 = lshr i64 %39, 8
store i64 %40, i64* %5
br label %41
41: ; preds = %38
%42 = load i32, i32* %8
%43 = add i32 %42, 1
store i32 %43, i32* %8
br label %10
44: ; preds = %10
%45 = load i64, i64* %7
%46 = call i32 @OS_enable_interrupts(i64 %45)
store i32 0, i32* %3
br label %47
47: ; preds = %44, %33
%48 = load i32, i32* %3
ret i32 %48
}

LLVM IR (-O2):
define i32 @lpc_write_reg(i32 %0, i64 %1) {
%3 = alloca i64
%4 = bitcast i64* %3 to i8*
%5 = call i32 @OS_disable_interrupts(i64* %3)
%6 = zext i32 %0 to i64
%7 = icmp eq i32 %0, 5
br i1 %7, label %17, label %8
8: ; preds = %2
%9 = call i64 (...) @PL_lpc_base_address()
%10 = add i64 %9, %6
%11 = trunc i64 %10 to i16
%12 = trunc i64 %1 to i8
%13 = call i32 @DM_out_8(i16 zeroext %11, i8 zeroext %12)
%14 = icmp eq i32 %13, 0
br i1 %14, label %15, label %49
15: ; preds = %8
%16 = icmp eq i32 %0, 4
br i1 %16, label %28, label %17
17: ; preds = %2, %15
%18 = lshr i64 %1, 8
%19 = call i64 (...) @PL_lpc_base_address()
%20 = add nuw nsw i64 %6, 1
%21 = add i64 %20, %19
%22 = trunc i64 %21 to i16
%23 = trunc i64 %18 to i8
%24 = call i32 @DM_out_8(i16 zeroext %22, i8 zeroext %23)
%25 = icmp eq i32 %24, 0
br i1 %25, label %26, label %49
26: ; preds = %17
%27 = icmp eq i32 %0, 3
br i1 %27, label %39, label %28
28: ; preds = %15, %26
%29 = lshr i64 %1, 16
%30 = call i64 (...) @PL_lpc_base_address()
%31 = add nuw nsw i64 %6, 2
%32 = add i64 %31, %30
%33 = trunc i64 %32 to i16
%34 = trunc i64 %29 to i8
%35 = call i32 @DM_out_8(i16 zeroext %33, i8 zeroext %34)
%36 = icmp eq i32 %35, 0
br i1 %36, label %37, label %49
37: ; preds = %28
%38 = icmp eq i32 %0, 2
br i1 %38, label %48, label %39
39: ; preds = %26, %37
%40 = lshr i64 %1, 24
%41 = call i64 (...) @PL_lpc_base_address()
%42 = add nuw nsw i64 %6, 3
%43 = add i64 %42, %41
%44 = trunc i64 %43 to i16
%45 = trunc i64 %40 to i8
%46 = call i32 @DM_out_8(i16 zeroext %44, i8 zeroext %45)
%47 = icmp eq i32 %46, 0
br i1 %47, label %48, label %49
48: ; preds = %39, %37
br label %49
49: ; preds = %8, %17, %28, %39, %48
%50 = phi i32 [ 0, %48 ], [ %13, %8 ], [ %24, %17 ], [ %35, %28 ], [ %46, %39 ]
%51 = load i64, i64* %3
%52 = call i32 @OS_enable_interrupts(i64 %51)
ret i32 %50
}