int Checkcondition(int code, unsigned int flags) {
  unsigned int cond, temp;
  switch (code & 0x0E) {
  case 0:
    cond = flags & 0x0800;
    break;
  case 2:
    cond = flags & 0x0001;
    break;
  case 4:
    cond = flags & 0x0040;
    break;
  case 6:
    cond = flags & 0x0041;
    break;
  case 8:
    cond = flags & 0x0080;
    break;
  case 10:
    cond = flags & 0x0004;
    break;
  case 12:
    temp = flags & 0x0880;
    cond = (temp == 0x0800 || temp == 0x0080);
    break;
  case 14:
    temp = flags & 0x0880;
    cond = (temp == 0x0800 || temp == 0x0080 || (flags & 0x0040) != 0);
    break;
  default:
    return -1;
  };
  if ((code & 0x01) == 0)
    return (cond != 0);
  else
    return (cond == 0);
}


x86 assembly (clang, -O0):
<Checkcondition>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0x8(%rbp),%eax
and    $0xe,%eax
mov    %rax,-0x20(%rbp)
sub    $0xe,%eax
ja     1211 <Checkcondition+0x111>
mov    -0x20(%rbp),%rax
lea    0xed8(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
mov    -0xc(%rbp),%eax
and    $0x800,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x1,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x40,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x41,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x80,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x4,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x880,%eax
mov    %eax,-0x14(%rbp)
mov    $0x1,%al
cmpl   $0x800,-0x14(%rbp)
mov    %al,-0x21(%rbp)
je     11b3 <Checkcondition+0xb3>
cmpl   $0x80,-0x14(%rbp)
sete   %al
mov    %al,-0x21(%rbp)
mov    -0x21(%rbp),%al
and    $0x1,%al
movzbl %al,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
mov    -0xc(%rbp),%eax
and    $0x880,%eax
mov    %eax,-0x14(%rbp)
mov    $0x1,%al
cmpl   $0x800,-0x14(%rbp)
mov    %al,-0x22(%rbp)
je     1201 <Checkcondition+0x101>
mov    $0x1,%al
cmpl   $0x80,-0x14(%rbp)
mov    %al,-0x22(%rbp)
je     1201 <Checkcondition+0x101>
mov    -0xc(%rbp),%eax
and    $0x40,%eax
cmp    $0x0,%eax
setne  %al
mov    %al,-0x22(%rbp)
mov    -0x22(%rbp),%al
and    $0x1,%al
movzbl %al,%eax
mov    %eax,-0x10(%rbp)
jmp    121d <Checkcondition+0x11d>
movl   $0xffffffff,-0x4(%rbp)
jmp    124f <Checkcondition+0x14f>
mov    -0x8(%rbp),%eax
and    $0x1,%eax
cmp    $0x0,%eax
jne    1240 <Checkcondition+0x140>
cmpl   $0x0,-0x10(%rbp)
setne  %al
and    $0x1,%al
movzbl %al,%eax
mov    %eax,-0x4(%rbp)
jmp    124f <Checkcondition+0x14f>
cmpl   $0x0,-0x10(%rbp)
sete   %al
and    $0x1,%al
movzbl %al,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<Checkcondition>:
mov    %edi,%eax
and    $0xe,%eax
lea    0xef4(%rip),%rcx
movslq (%rcx,%rax,4),%rax
add    %rcx,%rax
jmp    *%rax
and    $0x800,%esi
jmp    1157 <Checkcondition+0x57>
and    $0x41,%esi
jmp    1157 <Checkcondition+0x57>
mov    %esi,%ecx
and    $0x880,%ecx
mov    $0x1,%eax
cmp    $0x80,%ecx
je     1159 <Checkcondition+0x59>
cmp    $0x800,%ecx
je     1159 <Checkcondition+0x59>
shr    $0x6,%esi
and    $0x1,%esi
jmp    1157 <Checkcondition+0x57>
and    $0x40,%esi
jmp    1157 <Checkcondition+0x57>
and    $0x80,%esi
jmp    1157 <Checkcondition+0x57>
and    $0x4,%esi
mov    %esi,%eax
xor    %ecx,%ecx
xor    %edx,%edx
test   %eax,%eax
setne  %cl
sete   %dl
test   $0x1,%dil
cmove  %ecx,%edx
movzbl %dl,%eax
ret
and    $0x880,%esi
cmp    $0x800,%esi
sete   %al
cmp    $0x80,%esi
sete   %cl
or     %al,%cl
movzbl %cl,%eax
jmp    1159 <Checkcondition+0x59>

LLVM IR (-O0):
define i32 @Checkcondition(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
%8 = load i32, i32* %4
%9 = and i32 %8, 14
switch i32 %9, label %54 [
i32 0, label %10
i32 2, label %13
i32 4, label %16
i32 6, label %19
i32 8, label %22
i32 10, label %25
i32 12, label %28
i32 14, label %39
]
10: ; preds = %2
%11 = load i32, i32* %5
%12 = and i32 %11, 2048
store i32 %12, i32* %6
br label %55
13: ; preds = %2
%14 = load i32, i32* %5
%15 = and i32 %14, 1
store i32 %15, i32* %6
br label %55
16: ; preds = %2
%17 = load i32, i32* %5
%18 = and i32 %17, 64
store i32 %18, i32* %6
br label %55
19: ; preds = %2
%20 = load i32, i32* %5
%21 = and i32 %20, 65
store i32 %21, i32* %6
br label %55
22: ; preds = %2
%23 = load i32, i32* %5
%24 = and i32 %23, 128
store i32 %24, i32* %6
br label %55
25: ; preds = %2
%26 = load i32, i32* %5
%27 = and i32 %26, 4
store i32 %27, i32* %6
br label %55
28: ; preds = %2
%29 = load i32, i32* %5
%30 = and i32 %29, 2176
store i32 %30, i32* %7
%31 = load i32, i32* %7
%32 = icmp eq i32 %31, 2048
br i1 %32, label %36, label %33
33: ; preds = %28
%34 = load i32, i32* %7
%35 = icmp eq i32 %34, 128
br label %36
36: ; preds = %33, %28
%37 = phi i1 [ true, %28 ], [ %35, %33 ]
%38 = zext i1 %37 to i32
store i32 %38, i32* %6
br label %55
39: ; preds = %2
%40 = load i32, i32* %5
%41 = and i32 %40, 2176
store i32 %41, i32* %7
%42 = load i32, i32* %7
%43 = icmp eq i32 %42, 2048
br i1 %43, label %51, label %44
44: ; preds = %39
%45 = load i32, i32* %7
%46 = icmp eq i32 %45, 128
br i1 %46, label %51, label %47
47: ; preds = %44
%48 = load i32, i32* %5
%49 = and i32 %48, 64
%50 = icmp ne i32 %49, 0
br label %51
51: ; preds = %47, %44, %39
%52 = phi i1 [ true, %44 ], [ true, %39 ], [ %50, %47 ]
%53 = zext i1 %52 to i32
store i32 %53, i32* %6
br label %55
54: ; preds = %2
store i32 -1, i32* %3
br label %67
55: ; preds = %51, %36, %25, %22, %19, %16, %13, %10
%56 = load i32, i32* %4
%57 = and i32 %56, 1
%58 = icmp eq i32 %57, 0
br i1 %58, label %59, label %63
59: ; preds = %55
%60 = load i32, i32* %6
%61 = icmp ne i32 %60, 0
%62 = zext i1 %61 to i32
store i32 %62, i32* %3
br label %67
63: ; preds = %55
%64 = load i32, i32* %6
%65 = icmp eq i32 %64, 0
%66 = zext i1 %65 to i32
store i32 %66, i32* %3
br label %67
67: ; preds = %63, %59, %54
%68 = load i32, i32* %3
ret i32 %68
}

LLVM IR (-O2):
define i32 @Checkcondition(i32 %0, i32 %1) {
%3 = and i32 %0, 14
switch i32 %3, label %27 [
i32 0, label %4
i32 2, label %6
i32 4, label %8
i32 6, label %10
i32 8, label %12
i32 10, label %14
i32 12, label %16
i32 14, label %22
]
4: ; preds = %2
%5 = and i32 %1, 2048
br label %28
6: ; preds = %2
%7 = and i32 %1, 1
br label %28
8: ; preds = %2
%9 = and i32 %1, 64
br label %28
10: ; preds = %2
%11 = and i32 %1, 65
br label %28
12: ; preds = %2
%13 = and i32 %1, 128
br label %28
14: ; preds = %2
%15 = and i32 %1, 4
br label %28
16: ; preds = %2
%17 = and i32 %1, 2176
%18 = icmp eq i32 %17, 2048
%19 = icmp eq i32 %17, 128
%20 = or i1 %18, %19
%21 = zext i1 %20 to i32
br label %28
22: ; preds = %2
%23 = and i32 %1, 2176
switch i32 %23, label %24 [
i32 2048, label %28
i32 128, label %28
]
24: ; preds = %22
%25 = lshr i32 %1, 6
%26 = and i32 %25, 1
br label %28
27: ; preds = %2
unreachable
28: ; preds = %24, %22, %22, %16, %14, %12, %10, %8, %6, %4
%29 = phi i32 [ %21, %16 ], [ %15, %14 ], [ %13, %12 ], [ %11, %10 ], [ %9, %8 ], [ %7, %6 ], [ %5, %4 ], [ 1, %22 ], [ %26, %24 ], [ 1, %22 ]
%30 = and i32 %0, 1
%31 = icmp eq i32 %30, 0
%32 = icmp ne i32 %29, 0
%33 = icmp eq i32 %29, 0
%34 = select i1 %31, i1 %32, i1 %33
%35 = zext i1 %34 to i32
ret i32 %35
}