void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) {
  ;
  if (ulIntFlags == 0x00400040) {
    (*((volatile unsigned long *)(ulBase + 0x0000000C))) &= ~0x00000040;
  } else if (ulIntFlags == 0x00010100) {
    (*((volatile unsigned long *)(ulBase + 0x0000000C))) &= ~0x00000100;
  } else if (ulIntFlags == 0x00800080) {
    (*((volatile unsigned long *)(ulBase + 0x0000000C))) &= ~0x00000080;
  } else if (ulIntFlags == 0x00200020) {
    (*((volatile unsigned long *)(ulBase + 0x0000000C))) &= ~0x00000020;
  } else if (ulIntFlags == 0x00100010) {
    (*((volatile unsigned long *)(ulBase + 0x0000000C))) &= ~0x00000010;
  } else if (ulIntFlags == 0x01001020) {
    (*((volatile unsigned long *)(ulBase + 0x00000010))) &= ~0x00000040;
  } else if (ulIntFlags == 0x000E2001) {
    (*((volatile unsigned long *)(ulBase + 0x00000014))) &= ~0x00000001;
  } else {
    (*((volatile unsigned long *)(ulBase + 0x00000014))) &= ~0x00000400;
  }
}


x86 assembly (clang, -O0):
<UARTIntDisable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x400040,-0x10(%rbp)
jne    112f <UARTIntDisable+0x2f>
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
and    $0xffffffffffffffbf,%rcx
mov    %rcx,0xc(%rax)
jmp    1238 <UARTIntDisable+0x138>
cmpq   $0x10100,-0x10(%rbp)
jne    1155 <UARTIntDisable+0x55>
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
and    $0xfffffffffffffeff,%rcx
mov    %rcx,0xc(%rax)
jmp    1233 <UARTIntDisable+0x133>
cmpq   $0x800080,-0x10(%rbp)
jne    117b <UARTIntDisable+0x7b>
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
and    $0xffffffffffffff7f,%rcx
mov    %rcx,0xc(%rax)
jmp    122e <UARTIntDisable+0x12e>
cmpq   $0x200020,-0x10(%rbp)
jne    119e <UARTIntDisable+0x9e>
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
and    $0xffffffffffffffdf,%rcx
mov    %rcx,0xc(%rax)
jmp    1229 <UARTIntDisable+0x129>
cmpq   $0x100010,-0x10(%rbp)
jne    11c1 <UARTIntDisable+0xc1>
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
and    $0xffffffffffffffef,%rcx
mov    %rcx,0xc(%rax)
jmp    1224 <UARTIntDisable+0x124>
cmpq   $0x1001020,-0x10(%rbp)
01
jne    11e4 <UARTIntDisable+0xe4>
mov    -0x8(%rbp),%rax
mov    0x10(%rax),%rcx
and    $0xffffffffffffffbf,%rcx
mov    %rcx,0x10(%rax)
jmp    121f <UARTIntDisable+0x11f>
cmpq   $0xe2001,-0x10(%rbp)
jne    1207 <UARTIntDisable+0x107>
mov    -0x8(%rbp),%rax
mov    0x14(%rax),%rcx
and    $0xfffffffffffffffe,%rcx
mov    %rcx,0x14(%rax)
jmp    121a <UARTIntDisable+0x11a>
mov    -0x8(%rbp),%rax
mov    0x14(%rax),%rcx
and    $0xfffffffffffffbff,%rcx
mov    %rcx,0x14(%rax)
jmp    121f <UARTIntDisable+0x11f>
jmp    1224 <UARTIntDisable+0x124>
jmp    1229 <UARTIntDisable+0x129>
jmp    122e <UARTIntDisable+0x12e>
jmp    1233 <UARTIntDisable+0x133>
jmp    1238 <UARTIntDisable+0x138>
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTIntDisable>:
mov    $0xc,%eax
cmp    $0x20001f,%rsi
jle    1135 <UARTIntDisable+0x35>
mov    $0xffffffffffffffbf,%rcx
cmp    $0x80007f,%rsi
jg     115c <UARTIntDisable+0x5c>
cmp    $0x200020,%rsi
je     1178 <UARTIntDisable+0x78>
cmp    $0x400040,%rsi
jne    119c <UARTIntDisable+0x9c>
and    %rcx,(%rax,%rdi,1)
ret
cmp    $0x10100,%rsi
je     1184 <UARTIntDisable+0x84>
cmp    $0xe2001,%rsi
je     11a5 <UARTIntDisable+0xa5>
cmp    $0x100010,%rsi
jne    119c <UARTIntDisable+0x9c>
mov    $0xffffffffffffffef,%rcx
and    %rcx,(%rax,%rdi,1)
ret
cmp    $0x800080,%rsi
je     1190 <UARTIntDisable+0x90>
cmp    $0x1001020,%rsi
jne    119c <UARTIntDisable+0x9c>
mov    $0x10,%eax
and    %rcx,(%rax,%rdi,1)
ret
mov    $0xffffffffffffffdf,%rcx
and    %rcx,(%rax,%rdi,1)
ret
mov    $0xfffffffffffffeff,%rcx
and    %rcx,(%rax,%rdi,1)
ret
mov    $0xffffffffffffff7f,%rcx
and    %rcx,(%rax,%rdi,1)
ret
mov    $0xfffffffffffffbff,%rcx
jmp    11ac <UARTIntDisable+0xac>
mov    $0xfffffffffffffffe,%rcx
mov    $0x14,%eax
and    %rcx,(%rax,%rdi,1)
ret

LLVM IR (-O0):
define void @UARTIntDisable(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%5 = load i64, i64* %4
%6 = icmp eq i64 %5, 4194368
br i1 %6, label %7, label %13
7: ; preds = %2
%8 = load i64, i64* %3
%9 = add i64 %8, 12
%10 = inttoptr i64 %9 to i64*
%11 = load volatile i64, i64* %10
%12 = and i64 %11, -65
store volatile i64 %12, i64* %10
br label %79
13: ; preds = %2
%14 = load i64, i64* %4
%15 = icmp eq i64 %14, 65792
br i1 %15, label %16, label %22
16: ; preds = %13
%17 = load i64, i64* %3
%18 = add i64 %17, 12
%19 = inttoptr i64 %18 to i64*
%20 = load volatile i64, i64* %19
%21 = and i64 %20, -257
store volatile i64 %21, i64* %19
br label %78
22: ; preds = %13
%23 = load i64, i64* %4
%24 = icmp eq i64 %23, 8388736
br i1 %24, label %25, label %31
25: ; preds = %22
%26 = load i64, i64* %3
%27 = add i64 %26, 12
%28 = inttoptr i64 %27 to i64*
%29 = load volatile i64, i64* %28
%30 = and i64 %29, -129
store volatile i64 %30, i64* %28
br label %77
31: ; preds = %22
%32 = load i64, i64* %4
%33 = icmp eq i64 %32, 2097184
br i1 %33, label %34, label %40
34: ; preds = %31
%35 = load i64, i64* %3
%36 = add i64 %35, 12
%37 = inttoptr i64 %36 to i64*
%38 = load volatile i64, i64* %37
%39 = and i64 %38, -33
store volatile i64 %39, i64* %37
br label %76
40: ; preds = %31
%41 = load i64, i64* %4
%42 = icmp eq i64 %41, 1048592
br i1 %42, label %43, label %49
43: ; preds = %40
%44 = load i64, i64* %3
%45 = add i64 %44, 12
%46 = inttoptr i64 %45 to i64*
%47 = load volatile i64, i64* %46
%48 = and i64 %47, -17
store volatile i64 %48, i64* %46
br label %75
49: ; preds = %40
%50 = load i64, i64* %4
%51 = icmp eq i64 %50, 16781344
br i1 %51, label %52, label %58
52: ; preds = %49
%53 = load i64, i64* %3
%54 = add i64 %53, 16
%55 = inttoptr i64 %54 to i64*
%56 = load volatile i64, i64* %55
%57 = and i64 %56, -65
store volatile i64 %57, i64* %55
br label %74
58: ; preds = %49
%59 = load i64, i64* %4
%60 = icmp eq i64 %59, 925697
br i1 %60, label %61, label %67
61: ; preds = %58
%62 = load i64, i64* %3
%63 = add i64 %62, 20
%64 = inttoptr i64 %63 to i64*
%65 = load volatile i64, i64* %64
%66 = and i64 %65, -2
store volatile i64 %66, i64* %64
br label %73
67: ; preds = %58
%68 = load i64, i64* %3
%69 = add i64 %68, 20
%70 = inttoptr i64 %69 to i64*
%71 = load volatile i64, i64* %70
%72 = and i64 %71, -1025
store volatile i64 %72, i64* %70
br label %73
73: ; preds = %67, %61
br label %74
74: ; preds = %73, %52
br label %75
75: ; preds = %74, %43
br label %76
76: ; preds = %75, %34
br label %77
77: ; preds = %76, %25
br label %78
78: ; preds = %77, %16
br label %79
79: ; preds = %78, %7
ret void
}

LLVM IR (-O2):
define void @UARTIntDisable(i64 %0, i64 %1) {
switch i64 %1, label %9 [
i64 4194368, label %10
i64 65792, label %3
i64 8388736, label %4
i64 2097184, label %5
i64 1048592, label %6
i64 16781344, label %7
i64 925697, label %8
]
3: ; preds = %2
br label %10
4: ; preds = %2
br label %10
5: ; preds = %2
br label %10
6: ; preds = %2
br label %10
7: ; preds = %2
br label %10
8: ; preds = %2
br label %10
9: ; preds = %2
br label %10
10: ; preds = %2, %3, %5, %7, %9, %8, %6, %4
%11 = phi i64 [ 12, %3 ], [ 12, %5 ], [ 16, %7 ], [ 20, %9 ], [ 20, %8 ], [ 12, %6 ], [ 12, %4 ], [ 12, %2 ]
%12 = phi i64 [ -257, %3 ], [ -33, %5 ], [ -65, %7 ], [ -1025, %9 ], [ -2, %8 ], [ -17, %6 ], [ -129, %4 ], [ -65, %2 ]
%13 = add i64 %11, %0
%14 = inttoptr i64 %13 to i64*
%15 = load volatile i64, i64* %14
%16 = and i64 %15, %12
store volatile i64 %16, i64* %14
ret void
}