void testsignifd_(int *pn) {
  int n;
  volatile double b, t;
  n = 0;
  b = 1;
  do {
    n++;
    b += b;
    t = b + 1;
    t -= b;
    t -= 1;
  } while (t == 0);
  *pn = n;
}


x86 assembly (clang, -O0):
<testsignifd_>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
movsd  0xee9(%rip),%xmm0
movsd  %xmm0,-0x18(%rbp)
mov    -0xc(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0xc(%rbp)
movsd  -0x18(%rbp),%xmm1
movsd  -0x18(%rbp),%xmm0
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x18(%rbp)
movsd  -0x18(%rbp),%xmm0
movsd  0xebb(%rip),%xmm1
addsd  %xmm1,%xmm0
movsd  %xmm0,-0x20(%rbp)
movsd  -0x18(%rbp),%xmm1
movsd  -0x20(%rbp),%xmm0
subsd  %xmm1,%xmm0
movsd  %xmm0,-0x20(%rbp)
movsd  -0x20(%rbp),%xmm0
movsd  0xe92(%rip),%xmm1
subsd  %xmm1,%xmm0
movsd  %xmm0,-0x20(%rbp)
movsd  -0x20(%rbp),%xmm0
xorps  %xmm1,%xmm1
ucomisd %xmm1,%xmm0
jne    1194 <testsignifd_+0x94>
jp     1194 <testsignifd_+0x94>
jmp    111c <testsignifd_+0x1c>
mov    -0xc(%rbp),%ecx
mov    -0x8(%rbp),%rax
mov    %ecx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<testsignifd_>:
movabs $0x3ff0000000000000,%rax
mov    %rax,-0x8(%rsp)
xor    %eax,%eax
movsd  0xee7(%rip),%xmm0
movsd  0xee7(%rip),%xmm1
xorpd  %xmm2,%xmm2
cs nopw 0x0(%rax,%rax,1)
nop
movsd  -0x8(%rsp),%xmm3
addsd  -0x8(%rsp),%xmm3
movsd  %xmm3,-0x8(%rsp)
movsd  -0x8(%rsp),%xmm3
addsd  %xmm0,%xmm3
movsd  %xmm3,-0x10(%rsp)
movsd  -0x8(%rsp),%xmm3
movsd  -0x10(%rsp),%xmm4
subsd  %xmm3,%xmm4
movsd  %xmm4,-0x10(%rsp)
movsd  -0x10(%rsp),%xmm3
addsd  %xmm1,%xmm3
add    $0x1,%eax
movsd  %xmm3,-0x10(%rsp)
movsd  -0x10(%rsp),%xmm3
ucomisd %xmm2,%xmm3
jne    1189 <testsignifd_+0x89>
jnp    1130 <testsignifd_+0x30>
mov    %eax,(%rdi)
ret

LLVM IR (-O0):
define void @testsignifd_(i32* %0) {
%2 = alloca i32*
%3 = alloca i32
%4 = alloca double
%5 = alloca double
store i32* %0, i32** %2
store i32 0, i32* %3
store volatile double 1.000000e+00, double* %4
br label %6
6: ; preds = %19, %1
%7 = load i32, i32* %3
%8 = add nsw i32 %7, 1
store i32 %8, i32* %3
%9 = load volatile double, double* %4
%10 = load volatile double, double* %4
%11 = fadd double %10, %9
store volatile double %11, double* %4
%12 = load volatile double, double* %4
%13 = fadd double %12, 1.000000e+00
store volatile double %13, double* %5
%14 = load volatile double, double* %4
%15 = load volatile double, double* %5
%16 = fsub double %15, %14
store volatile double %16, double* %5
%17 = load volatile double, double* %5
%18 = fsub double %17, 1.000000e+00
store volatile double %18, double* %5
br label %19
19: ; preds = %6
%20 = load volatile double, double* %5
%21 = fcmp oeq double %20, 0.000000e+00
br i1 %21, label %6, label %22
22: ; preds = %19
%23 = load i32, i32* %3
%24 = load i32*, i32** %2
store i32 %23, i32* %24
ret void
}

LLVM IR (-O2):
define void @testsignifd_(i32* nocapture writeonly %0) {
%2 = alloca double
%3 = alloca double
%4 = bitcast double* %2 to i8*
%5 = bitcast double* %3 to i8*
store volatile double 1.000000e+00, double* %2
br label %6
6: ; preds = %6, %1
%7 = phi i32 [ 0, %1 ], [ %8, %6 ]
%8 = add nuw nsw i32 %7, 1
%9 = load volatile double, double* %2
%10 = load volatile double, double* %2
%11 = fadd double %9, %10
store volatile double %11, double* %2
%12 = load volatile double, double* %2
%13 = fadd double %12, 1.000000e+00
store volatile double %13, double* %3
%14 = load volatile double, double* %2
%15 = load volatile double, double* %3
%16 = fsub double %15, %14
store volatile double %16, double* %3
%17 = load volatile double, double* %3
%18 = fadd double %17, -1.000000e+00
store volatile double %18, double* %3
%19 = load volatile double, double* %3
%20 = fcmp oeq double %19, 0.000000e+00
br i1 %20, label %6, label %21
21: ; preds = %6
store i32 %8, i32* %0
ret void
}