xunge/DecIR huggingface dataset:
/* Variables and functions */
scalar_t__ isempty(char const *);
const char *empty_to_dash(const char *str) { return isempty(str) ? "-" : str; }


x86 assembly (clang, -O0):
<empty_to_dash>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <isempty@plt>
cmp    $0x0,%rax
je     113f <empty_to_dash+0x2f>
lea    0xeca(%rip),%rax
mov    %rax,-0x10(%rbp)
jmp    1147 <empty_to_dash+0x37>
mov    -0x8(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<empty_to_dash>:
push   %rbx
mov    %rdi,%rbx
call   1030 <isempty@plt>
test   %rax,%rax
lea    0xedd(%rip),%rax
cmove  %rbx,%rax
pop    %rbx
ret

LLVM IR (-O0):
@.str = [2 x i8] c"-\00"
define i8* @empty_to_dash(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = call i64 @isempty(i8* %3)
%5 = icmp ne i64 %4, 0
br i1 %5, label %6, label %7
6: ; preds = %1
br label %9
7: ; preds = %1
%8 = load i8*, i8** %2
br label %9
9: ; preds = %7, %6
%10 = phi i8* [ getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0), %6 ], [ %8, %7 ]
ret i8* %10
}

LLVM IR (-O2):
@.str = [2 x i8] c"-\00"
define i8* @empty_to_dash(i8* %0) {
%2 = tail call i64 @isempty(i8* %0)
%3 = icmp eq i64 %2, 0
%4 = select i1 %3, i8* %0, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i64 0, i64 0)
ret i8* %4
}
/* Variables and functions */
float pow(double, float);
float R2_logDepthDecode(const float z, const float depth_coefficient) {
  float half_co = depth_coefficient * 0.5;
  float exponent = z / half_co;
  return pow(2.0, exponent) - 1.0;
}


x86 assembly (clang, -O0):
<R2_logDepthDecode>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movss  %xmm0,-0x4(%rbp)
movss  %xmm1,-0x8(%rbp)
movss  -0x8(%rbp),%xmm0
cvtss2sd %xmm0,%xmm0
movsd  0xedd(%rip),%xmm1
mulsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
movss  %xmm0,-0xc(%rbp)
movss  -0x4(%rbp),%xmm0
divss  -0xc(%rbp),%xmm0
movss  %xmm0,-0x10(%rbp)
movss  -0x10(%rbp),%xmm1
movsd  0xeac(%rip),%xmm0
call   1030 <pow@plt>
cvtss2sd %xmm0,%xmm0
movsd  0xe93(%rip),%xmm1
subsd  %xmm1,%xmm0
cvtsd2ss %xmm0,%xmm0
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<R2_logDepthDecode>:
push   %rax
movaps %xmm0,%xmm2
mulss  0xee4(%rip),%xmm1
divss  %xmm1,%xmm2
movsd  0xee0(%rip),%xmm0
movaps %xmm2,%xmm1
call   1030 <pow@plt>
addss  0xecc(%rip),%xmm0
pop    %rax
ret

LLVM IR (-O0):
define float @R2_logDepthDecode(float %0, float %1) {
%3 = alloca float
%4 = alloca float
%5 = alloca float
%6 = alloca float
store float %0, float* %3
store float %1, float* %4
%7 = load float, float* %4
%8 = fpext float %7 to double
%9 = fmul double %8, 5.000000e-01
%10 = fptrunc double %9 to float
store float %10, float* %5
%11 = load float, float* %3
%12 = load float, float* %5
%13 = fdiv float %11, %12
store float %13, float* %6
%14 = load float, float* %6
%15 = call float @pow(double 2.000000e+00, float %14)
%16 = fpext float %15 to double
%17 = fsub double %16, 1.000000e+00
%18 = fptrunc double %17 to float
ret float %18
}

LLVM IR (-O2):
define float @R2_logDepthDecode(float %0, float %1) {
%3 = fmul float %1, 5.000000e-01
%4 = fdiv float %0, %3
%5 = tail call float @pow(double 2.000000e+00, float %4)
%6 = fadd float %5, -1.000000e+00
ret float %6
}
/* Variables and functions */
int /*<<< orphan*/ AirspeedStateHandle();
int /*<<< orphan*/ UAVObjLogging(int /*<<< orphan*/);
void AirspeedStateLogging() { UAVObjLogging(AirspeedStateHandle()); }


x86 assembly (clang, -O0):
<AirspeedStateLogging>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1040 <AirspeedStateHandle@plt>
mov    %eax,%edi
call   1030 <UAVObjLogging@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<AirspeedStateLogging>:
push   %rax
xor    %eax,%eax
call   1040 <AirspeedStateHandle@plt>
mov    %eax,%edi
pop    %rax
jmp    1030 <UAVObjLogging@plt>

LLVM IR (-O0):
define void @AirspeedStateLogging() {
%1 = call i32 (...) @AirspeedStateHandle()
%2 = call i32 @UAVObjLogging(i32 %1)
ret void
}

LLVM IR (-O2):
define void @AirspeedStateLogging() {
%1 = tail call i32 (...) @AirspeedStateHandle()
%2 = tail call i32 @UAVObjLogging(i32 %1)
ret void
}
/* Variables and functions */
void *realloc(void *, size_t);
void stub1(int, char *, int);
void *km_realloc_(void *data, size_t size, void (*onerr)(int, char *, int),
                  char *file, int line) {
  void *ret = realloc(data, size);
  if (ret == NULL) {
    (*onerr)(1, file, line);
    return NULL;
  } else {
    return ret;
  }
}


x86 assembly (clang, -O0):
<km_realloc_>:
push   %rbp
mov    %rsp,%rbp
sub    $0x40,%rsp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    %rdx,-0x20(%rbp)
mov    %rcx,-0x28(%rbp)
mov    %r8d,-0x2c(%rbp)
mov    -0x10(%rbp),%rdi
mov    -0x18(%rbp),%rsi
call   1030 <realloc@plt>
mov    %rax,-0x38(%rbp)
cmpq   $0x0,-0x38(%rbp)
jne    1167 <km_realloc_+0x57>
mov    -0x20(%rbp),%rax
mov    -0x28(%rbp),%rsi
mov    -0x2c(%rbp),%edx
mov    $0x1,%edi
call   *%rax
movq   $0x0,-0x8(%rbp)
jmp    116f <km_realloc_+0x5f>
mov    -0x38(%rbp),%rax
mov    %rax,-0x8(%rbp)
mov    -0x8(%rbp),%rax
add    $0x40,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<km_realloc_>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
mov    %r8d,%r14d
mov    %rcx,%rbp
mov    %rdx,%r15
call   1030 <realloc@plt>
mov    %rax,%rbx
test   %rax,%rax
jne    113b <km_realloc_+0x2b>
mov    $0x1,%edi
mov    %rbp,%rsi
mov    %r14d,%edx
call   *%r15
mov    %rbx,%rax
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define i8* @km_realloc_(i8* %0, i64 %1, void (i32, i8*, i32)* %2, i8* %3, i32 %4) {
%6 = alloca i8*
%7 = alloca i8*
%8 = alloca i64
%9 = alloca void (i32, i8*, i32)*
%10 = alloca i8*
%11 = alloca i32
%12 = alloca i8*
store i8* %0, i8** %7
store i64 %1, i64* %8
store void (i32, i8*, i32)* %2, void (i32, i8*, i32)** %9
store i8* %3, i8** %10
store i32 %4, i32* %11
%13 = load i8*, i8** %7
%14 = load i64, i64* %8
%15 = call i8* @realloc(i8* %13, i64 %14)
store i8* %15, i8** %12
%16 = load i8*, i8** %12
%17 = icmp eq i8* %16, null
br i1 %17, label %18, label %22
18: ; preds = %5
%19 = load void (i32, i8*, i32)*, void (i32, i8*, i32)** %9
%20 = load i8*, i8** %10
%21 = load i32, i32* %11
store i8* null, i8** %6
br label %24
22: ; preds = %5
%23 = load i8*, i8** %12
store i8* %23, i8** %6
br label %24
24: ; preds = %22, %18
%25 = load i8*, i8** %6
ret i8* %25
}

LLVM IR (-O2):
define i8* @km_realloc_(i8* nocapture %0, i64 %1, void (i32, i8*, i32)* nocapture %2, i8* %3, i32 %4) {
%6 = tail call i8* @realloc(i8* %0, i64 %1)
%7 = icmp eq i8* %6, null
br i1 %7, label %8, label %9
8: ; preds = %5
tail call void %2(i32 1, i8* %3, i32 %4)
br label %9
9: ; preds = %5, %8
ret i8* %6
}
/* Type definitions */
typedef unsigned long volatile uint32_t;

/* Variables and functions */
void RFCHwIntDisable(uint32_t ui32Mask) {
  (*((volatile unsigned long *)(0x40041000 + 0x0000000C))) &= ~ui32Mask;
}


x86 assembly (clang, -O0):
<RFCHwIntDisable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
xor    $0xffffffffffffffff,%rax
mov    $0x4004100c,%ecx
mov    (%rcx),%rcx
and    %rax,%rcx
mov    $0x4004100c,%eax
mov    %rcx,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<RFCHwIntDisable>:
mov    %rdi,-0x8(%rsp)
mov    -0x8(%rsp),%rax
not    %rax
and    %rax,0x4004100c
40
ret

LLVM IR (-O0):
define void @RFCHwIntDisable(i64 %0) {
%2 = alloca i64
store volatile i64 %0, i64* %2
%3 = load volatile i64, i64* %2
%4 = xor i64 %3, -1
%5 = load volatile i64, i64* inttoptr (i64 1074008076 to i64*)
%6 = and i64 %5, %4
store volatile i64 %6, i64* inttoptr (i64 1074008076 to i64*)
ret void
}

LLVM IR (-O2):
define void @RFCHwIntDisable(i64 %0) {
%2 = alloca i64
store volatile i64 %0, i64* %2
%3 = load volatile i64, i64* %2
%4 = xor i64 %3, -1
%5 = load volatile i64, i64* inttoptr (i64 1074008076 to i64*)
%6 = and i64 %5, %4
store volatile i64 %6, i64* inttoptr (i64 1074008076 to i64*)
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ FILE;

/* Variables and functions */
void ReadDummy(FILE *f) {}


x86 assembly (clang, -O0):
<ReadDummy>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<ReadDummy>:
ret

LLVM IR (-O0):
define void @ReadDummy(i32* %0) {
%2 = alloca i32*
store i32* %0, i32** %2
ret void
}

LLVM IR (-O2):
define void @ReadDummy(i32* nocapture %0) {
ret void
}
unsigned int mem_hash(ptr) void **ptr;
{
  long long lp = (long long)ptr;
  return (lp % 509);
}


x86 assembly (clang, -O0):
<mem_hash>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x10(%rbp),%rax
mov    $0x1fd,%ecx
cqto
idiv   %rcx
mov    %edx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<mem_hash>:
movabs $0x10182436517a3753,%rcx
24 18 10
mov    %rdi,%rax
imul   %rcx
mov    %rdx,%rax
shr    $0x3f,%rax
shr    $0x5,%rdx
add    %eax,%edx
imul   $0x1fd,%edx,%eax
sub    %eax,%edi
mov    %edi,%eax
ret

LLVM IR (-O0):
define i32 @mem_hash(i8** %0) {
%2 = alloca i8**
%3 = alloca i64
store i8** %0, i8*** %2
%4 = load i8**, i8*** %2
%5 = ptrtoint i8** %4 to i64
store i64 %5, i64* %3
%6 = load i64, i64* %3
%7 = srem i64 %6, 509
%8 = trunc i64 %7 to i32
ret i32 %8
}

LLVM IR (-O2):
define i32 @mem_hash(i8** %0) {
%2 = ptrtoint i8** %0 to i64
%3 = srem i64 %2, 509
%4 = trunc i64 %3 to i32
ret i32 %4
}
/* Type definitions */
struct b_tonegen {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ setMIDIDrawBar(struct b_tonegen *, int, unsigned char);
void setDrawbar18(void *d, unsigned char v) {
  setMIDIDrawBar((struct b_tonegen *)d, 18, v);
}


x86 assembly (clang, -O0):
<setDrawbar18>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %sil,%al
mov    %rdi,-0x8(%rbp)
mov    %al,-0x9(%rbp)
mov    -0x8(%rbp),%rdi
mov    $0x12,%esi
movzbl -0x9(%rbp),%edx
call   1030 <setMIDIDrawBar@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<setDrawbar18>:
mov    %esi,%edx
mov    $0x12,%esi
jmp    1030 <setMIDIDrawBar@plt>

LLVM IR (-O0):
%struct.b_tonegen = type { i32 }
define void @setDrawbar18(i8* %0, i8 zeroext %1) {
%3 = alloca i8*
%4 = alloca i8
store i8* %0, i8** %3
store i8 %1, i8* %4
%5 = load i8*, i8** %3
%6 = bitcast i8* %5 to %struct.b_tonegen*
%7 = load i8, i8* %4
%8 = call i32 @setMIDIDrawBar(%struct.b_tonegen* %6, i32 18, i8 zeroext %7)
ret void
}

LLVM IR (-O2):
%struct.b_tonegen = type { i32 }
define void @setDrawbar18(i8* %0, i8 zeroext %1) {
%3 = bitcast i8* %0 to %struct.b_tonegen*
%4 = tail call i32 @setMIDIDrawBar(%struct.b_tonegen* %3, i32 18, i8 zeroext %1)
ret void
}
int main() {
  char array[16 * 1024];
  register int loop;
  register int solution = 0;
  for (loop = 0; loop < 1000000; loop++) {
    solution += array[0] + array[8202];
  }
  return solution;
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
sub    $0x3fa0,%rsp
movl   $0x0,-0x4(%rbp)
movl   $0x0,-0x4018(%rbp)
movl   $0x0,-0x4014(%rbp)
cmpl   $0xf4240,-0x4014(%rbp)
jge    1166 <main+0x66>
movsbl -0x4010(%rbp),%eax
movsbl -0x2006(%rbp),%ecx
add    %ecx,%eax
add    -0x4018(%rbp),%eax
mov    %eax,-0x4018(%rbp)
mov    -0x4014(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x4014(%rbp)
jmp    1126 <main+0x26>
mov    -0x4018(%rbp),%eax
add    $0x3fa0,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca [16384 x i8]
%3 = alloca i32
%4 = alloca i32
store i32 0, i32* %1
store i32 0, i32* %4
store i32 0, i32* %3
br label %5
5: ; preds = %18, %0
%6 = load i32, i32* %3
%7 = icmp slt i32 %6, 1000000
br i1 %7, label %8, label %21
8: ; preds = %5
%9 = getelementptr inbounds [16384 x i8], [16384 x i8]* %2, i64 0, i64 0
%10 = load i8, i8* %9
%11 = sext i8 %10 to i32
%12 = getelementptr inbounds [16384 x i8], [16384 x i8]* %2, i64 0, i64 8202
%13 = load i8, i8* %12
%14 = sext i8 %13 to i32
%15 = add nsw i32 %11, %14
%16 = load i32, i32* %4
%17 = add nsw i32 %16, %15
store i32 %17, i32* %4
br label %18
18: ; preds = %8
%19 = load i32, i32* %3
%20 = add nsw i32 %19, 1
store i32 %20, i32* %3
br label %5
21: ; preds = %5
%22 = load i32, i32* %4
ret i32 %22
}

LLVM IR (-O2):
define i32 @main() {
ret i32 0
}
/* Variables and functions */
int /*<<< orphan*/ sampwm_(double *, int *, double *, int *, double *, double *,
                           int *);
void csampwm(double *x, int n, double *xmom, int nmom, double a, double b,
             int kind) {
  sampwm_(x, &n, xmom, &nmom, &a, &b, &kind);
}


x86 assembly (clang, -O0):
<csampwm>:
push   %rbp
mov    %rsp,%rbp
sub    $0x40,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %ecx,-0x1c(%rbp)
movsd  %xmm0,-0x28(%rbp)
movsd  %xmm1,-0x30(%rbp)
mov    %r8d,-0x34(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x18(%rbp),%rdx
lea    -0xc(%rbp),%rsi
lea    -0x1c(%rbp),%rcx
lea    -0x28(%rbp),%r8
lea    -0x30(%rbp),%r9
lea    -0x34(%rbp),%rax
mov    %rax,(%rsp)
call   1030 <sampwm_@plt>
add    $0x40,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<csampwm>:
sub    $0x28,%rsp
mov    %esi,0x14(%rsp)
mov    %ecx,0x10(%rsp)
movsd  %xmm0,0x20(%rsp)
movsd  %xmm1,0x18(%rsp)
mov    %r8d,0xc(%rsp)
lea    0xc(%rsp),%rax
mov    %rax,(%rsp)
lea    0x14(%rsp),%rsi
lea    0x10(%rsp),%rcx
lea    0x20(%rsp),%r8
lea    0x18(%rsp),%r9
call   1030 <sampwm_@plt>
add    $0x28,%rsp
ret

LLVM IR (-O0):
define void @csampwm(double* %0, i32 %1, double* %2, i32 %3, double %4, double %5, i32 %6) {
%8 = alloca double*
%9 = alloca i32
%10 = alloca double*
%11 = alloca i32
%12 = alloca double
%13 = alloca double
%14 = alloca i32
store double* %0, double** %8
store i32 %1, i32* %9
store double* %2, double** %10
store i32 %3, i32* %11
store double %4, double* %12
store double %5, double* %13
store i32 %6, i32* %14
%15 = load double*, double** %8
%16 = load double*, double** %10
%17 = call i32 @sampwm_(double* %15, i32* %9, double* %16, i32* %11, double* %12, double* %13, i32* %14)
ret void
}

LLVM IR (-O2):
define void @csampwm(double* %0, i32 %1, double* %2, i32 %3, double %4, double %5, i32 %6) {
%8 = alloca i32
%9 = alloca i32
%10 = alloca double
%11 = alloca double
%12 = alloca i32
store i32 %1, i32* %8
store i32 %3, i32* %9
store double %4, double* %10
store double %5, double* %11
store i32 %6, i32* %12
%13 = call i32 @sampwm_(double* %0, i32* %8, double* %2, i32* %9, double* %10, double* %11, i32* %12)
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ FILE;

/* Variables and functions */
int /*<<< orphan*/ fclose(int /*<<< orphan*/ *);
int endmntent(FILE *stream) {
  if (stream)
    fclose(stream);
  return 1;
}


x86 assembly (clang, -O0):
<endmntent>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
cmpq   $0x0,-0x8(%rbp)
je     1130 <endmntent+0x20>
mov    -0x8(%rbp),%rdi
call   1030 <fclose@plt>
mov    $0x1,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<endmntent>:
test   %rdi,%rdi
je     111f <endmntent+0xf>
push   %rax
call   1030 <fclose@plt>
add    $0x8,%rsp
mov    $0x1,%eax
ret

LLVM IR (-O0):
define i32 @endmntent(i32* %0) {
%2 = alloca i32*
store i32* %0, i32** %2
%3 = load i32*, i32** %2
%4 = icmp ne i32* %3, null
br i1 %4, label %5, label %8
5: ; preds = %1
%6 = load i32*, i32** %2
%7 = call i32 @fclose(i32* %6)
br label %8
8: ; preds = %5, %1
ret i32 1
}

LLVM IR (-O2):
define i32 @endmntent(i32* %0) {
%2 = icmp eq i32* %0, null
br i1 %2, label %5, label %3
3: ; preds = %1
%4 = tail call i32 @fclose(i32* %0)
br label %5
5: ; preds = %3, %1
ret i32 1
}
int test_imm_19int64_midword_reg(long long val) {
  return ((val >> 16) & (0x19 << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_19int64_midword_reg>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdx
sar    $0x10,%rdx
and    $0x19,%rdx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%rdx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_19int64_midword_reg>:
test   $0x190000,%edi
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_19int64_midword_reg(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = ashr i64 %3, 16
%5 = and i64 %4, 25
%6 = icmp ne i64 %5, 0
%7 = zext i1 %6 to i64
%8 = select i1 %6, i32 -20, i32 -40
ret i32 %8
}

LLVM IR (-O2):
define i32 @test_imm_19int64_midword_reg(i64 %0) {
%2 = and i64 %0, 1638400
%3 = icmp eq i64 %2, 0
%4 = select i1 %3, i32 -40, i32 -20
ret i32 %4
}
void list_link(int *first, int *next, int head, int node) {
  next[node] = first[head];
  first[head] = node;
}


x86 assembly (clang, -O0):
<list_link>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %edx,-0x14(%rbp)
mov    %ecx,-0x18(%rbp)
mov    -0x8(%rbp),%rax
movslq -0x14(%rbp),%rcx
mov    (%rax,%rcx,4),%edx
mov    -0x10(%rbp),%rax
movslq -0x18(%rbp),%rcx
mov    %edx,(%rax,%rcx,4)
mov    -0x18(%rbp),%edx
mov    -0x8(%rbp),%rax
movslq -0x14(%rbp),%rcx
mov    %edx,(%rax,%rcx,4)
pop    %rbp
ret

x86 assembly (clang, -O2):
<list_link>:
movslq %edx,%rax
mov    (%rdi,%rax,4),%edx
movslq %ecx,%rcx
mov    %edx,(%rsi,%rcx,4)
mov    %ecx,(%rdi,%rax,4)
ret

LLVM IR (-O0):
define void @list_link(i32* %0, i32* %1, i32 %2, i32 %3) {
%5 = alloca i32*
%6 = alloca i32*
%7 = alloca i32
%8 = alloca i32
store i32* %0, i32** %5
store i32* %1, i32** %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%9 = load i32*, i32** %5
%10 = load i32, i32* %7
%11 = sext i32 %10 to i64
%12 = getelementptr inbounds i32, i32* %9, i64 %11
%13 = load i32, i32* %12
%14 = load i32*, i32** %6
%15 = load i32, i32* %8
%16 = sext i32 %15 to i64
%17 = getelementptr inbounds i32, i32* %14, i64 %16
store i32 %13, i32* %17
%18 = load i32, i32* %8
%19 = load i32*, i32** %5
%20 = load i32, i32* %7
%21 = sext i32 %20 to i64
%22 = getelementptr inbounds i32, i32* %19, i64 %21
store i32 %18, i32* %22
ret void
}

LLVM IR (-O2):
define void @list_link(i32* nocapture %0, i32* nocapture writeonly %1, i32 %2, i32 %3) {
%5 = sext i32 %2 to i64
%6 = getelementptr inbounds i32, i32* %0, i64 %5
%7 = load i32, i32* %6
%8 = sext i32 %3 to i64
%9 = getelementptr inbounds i32, i32* %1, i64 %8
store i32 %7, i32* %9
store i32 %3, i32* %6
ret void
}
/* Variables and functions */
int /*<<< orphan*/ HplAtm128InterruptPinP__5__IrqSignal__fired();
void HplAtm128InterruptSigP__IntSig5__fired(void) {
  HplAtm128InterruptPinP__5__IrqSignal__fired();
}


x86 assembly (clang, -O0):
<HplAtm128InterruptSigP__IntSig5__fired>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <HplAtm128InterruptPinP__5__IrqSignal__fired@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<HplAtm128InterruptSigP__IntSig5__fired>:
xor    %eax,%eax
jmp    1030 <HplAtm128InterruptPinP__5__IrqSignal__fired@plt>

LLVM IR (-O0):
define void @HplAtm128InterruptSigP__IntSig5__fired() {
%1 = call i32 (...) @HplAtm128InterruptPinP__5__IrqSignal__fired()
ret void
}

LLVM IR (-O2):
define void @HplAtm128InterruptSigP__IntSig5__fired() {
%1 = tail call i32 (...) @HplAtm128InterruptPinP__5__IrqSignal__fired()
ret void
}
/* Type definitions */
typedef int /*<<< orphan*/ uint8_t;
typedef int /*<<< orphan*/ ptrdiff_t;

/* Variables and functions */
int /*<<< orphan*/ ff_bfin_z_put_pixels16_xy2(int /*<<< orphan*/ *,
                                              int /*<<< orphan*/ const *,
                                              int /*<<< orphan*/,
                                              int /*<<< orphan*/, int);
void bfin_put_pixels16_xy2(uint8_t *block, const uint8_t *s0,
                           ptrdiff_t line_size, int h) {
  ff_bfin_z_put_pixels16_xy2(block, s0, line_size, line_size, h);
}


x86 assembly (clang, -O0):
<bfin_put_pixels16_xy2>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %edx,-0x14(%rbp)
mov    %ecx,-0x18(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
mov    -0x14(%rbp),%edx
mov    -0x14(%rbp),%ecx
mov    -0x18(%rbp),%r8d
call   1030 <ff_bfin_z_put_pixels16_xy2@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<bfin_put_pixels16_xy2>:
mov    %ecx,%r8d
mov    %edx,%ecx
jmp    1030 <ff_bfin_z_put_pixels16_xy2@plt>

LLVM IR (-O0):
define void @bfin_put_pixels16_xy2(i32* %0, i32* %1, i32 %2, i32 %3) {
%5 = alloca i32*
%6 = alloca i32*
%7 = alloca i32
%8 = alloca i32
store i32* %0, i32** %5
store i32* %1, i32** %6
store i32 %2, i32* %7
store i32 %3, i32* %8
%9 = load i32*, i32** %5
%10 = load i32*, i32** %6
%11 = load i32, i32* %7
%12 = load i32, i32* %7
%13 = load i32, i32* %8
%14 = call i32 @ff_bfin_z_put_pixels16_xy2(i32* %9, i32* %10, i32 %11, i32 %12, i32 %13)
ret void
}

LLVM IR (-O2):
define void @bfin_put_pixels16_xy2(i32* %0, i32* %1, i32 %2, i32 %3) {
%5 = tail call i32 @ff_bfin_z_put_pixels16_xy2(i32* %0, i32* %1, i32 %2, i32 %2, i32 %3)
ret void
}
/* Type definitions */
struct flashctx {
  int dummy;
};

/* Variables and functions */
int printlock_regspace2_uniform_64k(struct flashctx *);
int printlock_w39_common(struct flashctx *, int);
int printlock_w39v040fc(struct flashctx *flash) {
  int ret = 0;
  ret = printlock_w39_common(flash, 0x7fff2);
  ret |= printlock_regspace2_uniform_64k(flash);
  return ret;
}


x86 assembly (clang, -O0):
<printlock_w39v040fc>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
mov    -0x8(%rbp),%rdi
mov    $0x7fff2,%esi
call   1040 <printlock_w39_common@plt>
mov    %eax,-0xc(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <printlock_regspace2_uniform_64k@plt>
or     -0xc(%rbp),%eax
mov    %eax,-0xc(%rbp)
mov    -0xc(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<printlock_w39v040fc>:
push   %rbp
push   %rbx
push   %rax
mov    %rdi,%rbx
mov    $0x7fff2,%esi
call   1040 <printlock_w39_common@plt>
mov    %eax,%ebp
mov    %rbx,%rdi
call   1030 <printlock_regspace2_uniform_64k@plt>
or     %ebp,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
%struct.flashctx = type { i32 }
define i32 @printlock_w39v040fc(%struct.flashctx* %0) {
%2 = alloca %struct.flashctx*
%3 = alloca i32
store %struct.flashctx* %0, %struct.flashctx** %2
store i32 0, i32* %3
%4 = load %struct.flashctx*, %struct.flashctx** %2
%5 = call i32 @printlock_w39_common(%struct.flashctx* %4, i32 524274)
store i32 %5, i32* %3
%6 = load %struct.flashctx*, %struct.flashctx** %2
%7 = call i32 @printlock_regspace2_uniform_64k(%struct.flashctx* %6)
%8 = load i32, i32* %3
%9 = or i32 %8, %7
store i32 %9, i32* %3
%10 = load i32, i32* %3
ret i32 %10
}

LLVM IR (-O2):
%struct.flashctx = type { i32 }
define i32 @printlock_w39v040fc(%struct.flashctx* %0) {
%2 = tail call i32 @printlock_w39_common(%struct.flashctx* %0, i32 524274)
%3 = tail call i32 @printlock_regspace2_uniform_64k(%struct.flashctx* %0)
%4 = or i32 %3, %2
ret i32 %4
}
void finn_vec2_mul(float *result, float *lhs, float scalar) {
  result[0] = lhs[0] * scalar;
  result[1] = lhs[1] * scalar;
}


x86 assembly (clang, -O0):
<finn_vec2_mul>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
movss  %xmm0,-0x14(%rbp)
mov    -0x10(%rbp),%rax
movss  (%rax),%xmm0
mulss  -0x14(%rbp),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,(%rax)
mov    -0x10(%rbp),%rax
movss  0x4(%rax),%xmm0
mulss  -0x14(%rbp),%xmm0
mov    -0x8(%rbp),%rax
movss  %xmm0,0x4(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<finn_vec2_mul>:
movss  (%rsi),%xmm1
mulss  %xmm0,%xmm1
movss  %xmm1,(%rdi)
mulss  0x4(%rsi),%xmm0
movss  %xmm0,0x4(%rdi)
ret

LLVM IR (-O0):
define void @finn_vec2_mul(float* %0, float* %1, float %2) {
%4 = alloca float*
%5 = alloca float*
%6 = alloca float
store float* %0, float** %4
store float* %1, float** %5
store float %2, float* %6
%7 = load float*, float** %5
%8 = getelementptr inbounds float, float* %7, i64 0
%9 = load float, float* %8
%10 = load float, float* %6
%11 = fmul float %9, %10
%12 = load float*, float** %4
%13 = getelementptr inbounds float, float* %12, i64 0
store float %11, float* %13
%14 = load float*, float** %5
%15 = getelementptr inbounds float, float* %14, i64 1
%16 = load float, float* %15
%17 = load float, float* %6
%18 = fmul float %16, %17
%19 = load float*, float** %4
%20 = getelementptr inbounds float, float* %19, i64 1
store float %18, float* %20
ret void
}

LLVM IR (-O2):
define void @finn_vec2_mul(float* nocapture writeonly %0, float* nocapture %1, float %2) {
%4 = load float, float* %1
%5 = fmul float %4, %2
store float %5, float* %0
%6 = getelementptr inbounds float, float* %1, i64 1
%7 = load float, float* %6
%8 = fmul float %7, %2
%9 = getelementptr inbounds float, float* %0, i64 1
store float %8, float* %9
ret void
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *);
void printftest() { printf("blah\n"); }


x86 assembly (clang, -O0):
<printftest>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <printf@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<printftest>:
lea    0xee9(%rip),%rdi
jmp    1030 <puts@plt>

LLVM IR (-O0):
@.str = [6 x i8] c"blah\0A\00"
define void @printftest() {
%1 = call i32 @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0))
ret void
}

LLVM IR (-O2):
@str = [5 x i8] c"blah\00"
define void @printftest() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([5 x i8], [5 x i8]* @str, i64 0, i64 0))
ret void
}
unsigned short char_to_int(char c) {
  if ((c <= '9') && (c >= '0'))
    return c - '0';
  if ((c <= 'A') && (c >= 'F'))
    return c - 'A' + 10;
  return 0;
}


x86 assembly (clang, -O0):
<char_to_int>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x3(%rbp)
movsbl -0x3(%rbp),%eax
cmp    $0x39,%eax
jg     1134 <char_to_int+0x34>
movsbl -0x3(%rbp),%eax
cmp    $0x30,%eax
jl     1134 <char_to_int+0x34>
movsbl -0x3(%rbp),%eax
sub    $0x30,%eax
mov    %ax,-0x2(%rbp)
jmp    1167 <char_to_int+0x67>
movsbl -0x3(%rbp),%eax
cmp    $0x41,%eax
jg     1161 <char_to_int+0x61>
movsbl -0x3(%rbp),%eax
cmp    $0x46,%eax
jl     1161 <char_to_int+0x61>
movsbl -0x3(%rbp),%eax
sub    $0x41,%eax
add    $0xa,%eax
mov    %ax,-0x2(%rbp)
jmp    1167 <char_to_int+0x67>
movw   $0x0,-0x2(%rbp)
movzwl -0x2(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<char_to_int>:
lea    -0x30(%rdi),%ecx
lea    -0x30(%rdi),%edx
xor    %eax,%eax
cmp    $0xa,%cl
cmovb  %edx,%eax
ret

LLVM IR (-O0):
define zeroext i16 @char_to_int(i8 signext %0) {
%2 = alloca i16
%3 = alloca i8
store i8 %0, i8* %3
%4 = load i8, i8* %3
%5 = sext i8 %4 to i32
%6 = icmp sle i32 %5, 57
br i1 %6, label %7, label %16
7: ; preds = %1
%8 = load i8, i8* %3
%9 = sext i8 %8 to i32
%10 = icmp sge i32 %9, 48
br i1 %10, label %11, label %16
11: ; preds = %7
%12 = load i8, i8* %3
%13 = sext i8 %12 to i32
%14 = sub nsw i32 %13, 48
%15 = trunc i32 %14 to i16
store i16 %15, i16* %2
br label %31
16: ; preds = %7, %1
%17 = load i8, i8* %3
%18 = sext i8 %17 to i32
%19 = icmp sle i32 %18, 65
br i1 %19, label %20, label %30
20: ; preds = %16
%21 = load i8, i8* %3
%22 = sext i8 %21 to i32
%23 = icmp sge i32 %22, 70
br i1 %23, label %24, label %30
24: ; preds = %20
%25 = load i8, i8* %3
%26 = sext i8 %25 to i32
%27 = sub nsw i32 %26, 65
%28 = add nsw i32 %27, 10
%29 = trunc i32 %28 to i16
store i16 %29, i16* %2
br label %31
30: ; preds = %20, %16
store i16 0, i16* %2
br label %31
31: ; preds = %30, %24, %11
%32 = load i16, i16* %2
ret i16 %32
}

LLVM IR (-O2):
define zeroext i16 @char_to_int(i8 signext %0) {
%2 = add i8 %0, -48
%3 = icmp ult i8 %2, 10
%4 = sext i8 %0 to i16
%5 = add nsw i16 %4, -48
%6 = select i1 %3, i16 %5, i16 0
ret i16 %6
}
/* Variables and functions */
int /*<<< orphan*/ Assert_real(int, char *, int, char *);
scalar_t__ isalpha(int);
void t_isalpha_0xa2() {
  Assert_real((isalpha(162) == 0),
              "/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/"
              "2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/"
              "dg/z88dk/test/suites/ctype/test_isalpha.c",
              815, ("isalpha should be 0 for 0xa2"));
}


x86 assembly (clang, -O0):
<t_isalpha_0xa2>:
push   %rbp
mov    %rsp,%rbp
mov    $0xa2,%edi
call   1030 <isalpha@plt>
cmp    $0x0,%rax
sete   %al
and    $0x1,%al
movzbl %al,%edi
lea    0xebf(%rip),%rsi
mov    $0x32f,%edx
lea    0xf5b(%rip),%rcx
call   1040 <Assert_real@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<t_isalpha_0xa2>:
push   %rax
mov    $0xa2,%edi
call   1030 <isalpha@plt>
xor    %edi,%edi
test   %rax,%rax
sete   %dil
lea    0xec5(%rip),%rsi
lea    0xf66(%rip),%rcx
mov    $0x32f,%edx
pop    %rax
jmp    1040 <Assert_real@plt>

LLVM IR (-O0):
@.str = [168 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/dg/z88dk/test/suites/ctype/test_isalpha.c\00"
@.str.1 = [29 x i8] c"isalpha should be 0 for 0xa2\00"
define void @t_isalpha_0xa2() {
%1 = call i64 @isalpha(i32 162)
%2 = icmp eq i64 %1, 0
%3 = zext i1 %2 to i32
%4 = call i32 @Assert_real(i32 %3, i8* getelementptr inbounds ([168 x i8], [168 x i8]* @.str, i64 0, i64 0), i32 815, i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str.1, i64 0, i64 0))
ret void
}

LLVM IR (-O2):
@.str = [168 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/dg/z88dk/test/suites/ctype/test_isalpha.c\00"
@.str.1 = [29 x i8] c"isalpha should be 0 for 0xa2\00"
define void @t_isalpha_0xa2() {
%1 = tail call i64 @isalpha(i32 162)
%2 = icmp eq i64 %1, 0
%3 = zext i1 %2 to i32
%4 = tail call i32 @Assert_real(i32 %3, i8* getelementptr inbounds ([168 x i8], [168 x i8]* @.str, i64 0, i64 0), i32 815, i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str.1, i64 0, i64 0))
ret void
}
void avio_w8() {}


x86 assembly (clang, -O0):
<avio_w8>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<avio_w8>:
ret

LLVM IR (-O0):
define void @avio_w8() {
ret void
}

LLVM IR (-O2):
define void @avio_w8() {
ret void
}
/* Variables and functions */
scalar_t__ INT_MAX;
int INT_MIN;
f2() {
  int b = INT_MIN + 1;
  return b >= (unsigned)(INT_MAX + 2);
}


x86 assembly (clang, -O0):
<f2>:
push   %rbp
mov    %rsp,%rbp
mov    0x2ed5(%rip),%rax
mov    (%rax),%eax
add    $0x1,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    0x2ecb(%rip),%rcx
mov    (%rcx),%rcx
add    $0x2,%rcx
cmp    %ecx,%eax
setae  %al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<f2>:
mov    0x2ed9(%rip),%rax
mov    (%rax),%ecx
add    $0x1,%ecx
mov    0x2ed5(%rip),%rax
mov    (%rax),%edx
add    $0x2,%edx
xor    %eax,%eax
cmp    %edx,%ecx
setae  %al
ret

LLVM IR (-O0):
@INT_MIN = global i32 0
@INT_MAX = global i64 0
define i32 @f2() {
%1 = alloca i32
%2 = load i32, i32* @INT_MIN
%3 = add nsw i32 %2, 1
store i32 %3, i32* %1
%4 = load i32, i32* %1
%5 = load i64, i64* @INT_MAX
%6 = add nsw i64 %5, 2
%7 = trunc i64 %6 to i32
%8 = icmp uge i32 %4, %7
%9 = zext i1 %8 to i32
ret i32 %9
}

LLVM IR (-O2):
@INT_MIN = global i32 0
@INT_MAX = global i64 0
define i32 @f2() {
%1 = load i32, i32* @INT_MIN
%2 = add nsw i32 %1, 1
%3 = load i64, i64* @INT_MAX
%4 = trunc i64 %3 to i32
%5 = add i32 %4, 2
%6 = icmp uge i32 %2, %5
%7 = zext i1 %6 to i32
ret i32 %7
}
/* Type definitions */
struct eh_buffer {
  int dummy;
};
typedef int /*<<< orphan*/ ssize_t;

/* Variables and functions */
int /*<<< orphan*/ assert(int /*<<< orphan*/);
int /*<<< orphan*/ eh_buffer_append(struct eh_buffer *, char const *,
                                    int /*<<< orphan*/);
int /*<<< orphan*/ strlen(char const *);
ssize_t eh_buffer_appendz(struct eh_buffer *self, const char *str) {
  assert(str != NULL);
  return eh_buffer_append(self, str, strlen(str));
}


x86 assembly (clang, -O0):
<eh_buffer_appendz>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
cmpq   $0x0,-0x10(%rbp)
setne  %al
and    $0x1,%al
movzbl %al,%edi
call   1050 <assert@plt>
mov    -0x8(%rbp),%rax
mov    %rax,-0x20(%rbp)
mov    -0x10(%rbp),%rax
mov    %rax,-0x18(%rbp)
mov    -0x10(%rbp),%rdi
call   1030 <strlen@plt>
mov    -0x20(%rbp),%rdi
mov    -0x18(%rbp),%rsi
mov    %eax,%edx
call   1040 <eh_buffer_append@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<eh_buffer_appendz>:
push   %r14
push   %rbx
push   %rax
mov    %rsi,%rbx
mov    %rdi,%r14
xor    %edi,%edi
test   %rsi,%rsi
setne  %dil
call   1050 <assert@plt>
mov    %rbx,%rdi
call   1030 <strlen@plt>
mov    %r14,%rdi
mov    %rbx,%rsi
mov    %eax,%edx
add    $0x8,%rsp
pop    %rbx
pop    %r14
jmp    1040 <eh_buffer_append@plt>

LLVM IR (-O0):
%struct.eh_buffer = type { i32 }
define i32 @eh_buffer_appendz(%struct.eh_buffer* %0, i8* %1) {
%3 = alloca %struct.eh_buffer*
%4 = alloca i8*
store %struct.eh_buffer* %0, %struct.eh_buffer** %3
store i8* %1, i8** %4
%5 = load i8*, i8** %4
%6 = icmp ne i8* %5, null
%7 = zext i1 %6 to i32
%8 = call i32 @assert(i32 %7)
%9 = load %struct.eh_buffer*, %struct.eh_buffer** %3
%10 = load i8*, i8** %4
%11 = load i8*, i8** %4
%12 = call i32 @strlen(i8* %11)
%13 = call i32 @eh_buffer_append(%struct.eh_buffer* %9, i8* %10, i32 %12)
ret i32 %13
}

LLVM IR (-O2):
%struct.eh_buffer = type { i32 }
define i32 @eh_buffer_appendz(%struct.eh_buffer* %0, i8* %1) {
%3 = icmp ne i8* %1, null
%4 = zext i1 %3 to i32
%5 = tail call i32 @assert(i32 %4)
%6 = tail call i32 @strlen(i8* %1)
%7 = tail call i32 @eh_buffer_append(%struct.eh_buffer* %0, i8* %1, i32 %6)
ret i32 %7
}
int main(void) {
  int d = 42;
  return sizeof(d);
}


x86 assembly (clang, -O0):
<main>:
push   %rbp
mov    %rsp,%rbp
movl   $0x0,-0x4(%rbp)
movl   $0x2a,-0x8(%rbp)
mov    $0x4,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<main>:
mov    $0x4,%eax
ret

LLVM IR (-O0):
define i32 @main() {
%1 = alloca i32
%2 = alloca i32
store i32 0, i32* %1
store i32 42, i32* %2
ret i32 4
}

LLVM IR (-O2):
define i32 @main() {
ret i32 4
}
void foo629(int p) {}


x86 assembly (clang, -O0):
<foo629>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
pop    %rbp
ret

x86 assembly (clang, -O2):
<foo629>:
ret

LLVM IR (-O0):
define void @foo629(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
ret void
}

LLVM IR (-O2):
define void @foo629(i32 %0) {
ret void
}
unsigned mount_gdi_session_count(struct mount *mount) { return 1; }


x86 assembly (clang, -O0):
<mount_gdi_session_count>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    $0x1,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<mount_gdi_session_count>:
mov    $0x1,%eax
ret

LLVM IR (-O0):
%struct.mount = type opaque
define i32 @mount_gdi_session_count(%struct.mount* %0) {
%2 = alloca %struct.mount*
store %struct.mount* %0, %struct.mount** %2
ret i32 1
}

LLVM IR (-O2):
%struct.mount = type opaque
define i32 @mount_gdi_session_count(%struct.mount* nocapture readnone %0) {
ret i32 1
}
/* Variables and functions */
int /*<<< orphan*/ hd44780_extif_pin_e(int);
int /*<<< orphan*/ hd44780_extif_wait_1us(int);
void hd44780_ll_enable_pulse(void) {
  hd44780_extif_pin_e(1);
  hd44780_extif_wait_1us(1);
  hd44780_extif_pin_e(0);
}


x86 assembly (clang, -O0):
<hd44780_ll_enable_pulse>:
push   %rbp
mov    %rsp,%rbp
mov    $0x1,%edi
call   1030 <hd44780_extif_pin_e@plt>
mov    $0x1,%edi
call   1040 <hd44780_extif_wait_1us@plt>
xor    %edi,%edi
call   1030 <hd44780_extif_pin_e@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<hd44780_ll_enable_pulse>:
push   %rax
mov    $0x1,%edi
call   1030 <hd44780_extif_pin_e@plt>
mov    $0x1,%edi
call   1040 <hd44780_extif_wait_1us@plt>
xor    %edi,%edi
pop    %rax
jmp    1030 <hd44780_extif_pin_e@plt>

LLVM IR (-O0):
define void @hd44780_ll_enable_pulse() {
%1 = call i32 @hd44780_extif_pin_e(i32 1)
%2 = call i32 @hd44780_extif_wait_1us(i32 1)
%3 = call i32 @hd44780_extif_pin_e(i32 0)
ret void
}

LLVM IR (-O2):
define void @hd44780_ll_enable_pulse() {
%1 = tail call i32 @hd44780_extif_pin_e(i32 1)
%2 = tail call i32 @hd44780_extif_wait_1us(i32 1)
%3 = tail call i32 @hd44780_extif_pin_e(i32 0)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ device_set_flags(char const *, short);
int /*<<< orphan*/ strlen(char *);
int /*<<< orphan*/ strncmp(char *, char const *, int /*<<< orphan*/);
void device_leave_promiscuous_mode(const char *ifname, short oldflags) {
  if (!strncmp("any", ifname, strlen("any")))
    return;
  device_set_flags(ifname, oldflags);
}


x86 assembly (clang, -O0):
<device_leave_promiscuous_mode>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %si,%ax
mov    %rdi,-0x8(%rbp)
mov    %ax,-0xa(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,-0x18(%rbp)
lea    0xeae(%rip),%rdi
call   1040 <strlen@plt>
mov    -0x18(%rbp),%rsi
mov    %eax,%edx
lea    0xe9c(%rip),%rdi
call   1030 <strncmp@plt>
cmp    $0x0,%eax
jne    1177 <device_leave_promiscuous_mode+0x47>
jmp    1184 <device_leave_promiscuous_mode+0x54>
mov    -0x8(%rbp),%rdi
movswl -0xa(%rbp),%esi
call   1050 <device_set_flags@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<device_leave_promiscuous_mode>:
push   %rbp
push   %r14
push   %rbx
mov    %esi,%r14d
mov    %rdi,%rbx
lea    0xebf(%rip),%rbp
mov    %rbp,%rdi
call   1040 <strlen@plt>
mov    %rbp,%rdi
mov    %rbx,%rsi
mov    %eax,%edx
call   1030 <strncmp@plt>
test   %eax,%eax
je     116a <device_leave_promiscuous_mode+0x3a>
movswl %r14w,%esi
mov    %rbx,%rdi
pop    %rbx
pop    %r14
pop    %rbp
jmp    1050 <device_set_flags@plt>
pop    %rbx
pop    %r14
pop    %rbp
ret

LLVM IR (-O0):
@.str = [4 x i8] c"any\00"
define void @device_leave_promiscuous_mode(i8* %0, i16 signext %1) {
%3 = alloca i8*
%4 = alloca i16
store i8* %0, i8** %3
store i16 %1, i16* %4
%5 = load i8*, i8** %3
%6 = call i32 @strlen(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0))
%7 = call i32 @strncmp(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* %5, i32 %6)
%8 = icmp ne i32 %7, 0
br i1 %8, label %10, label %9
9: ; preds = %2
br label %14
10: ; preds = %2
%11 = load i8*, i8** %3
%12 = load i16, i16* %4
%13 = call i32 @device_set_flags(i8* %11, i16 signext %12)
br label %14
14: ; preds = %10, %9
ret void
}

LLVM IR (-O2):
@.str = [4 x i8] c"any\00"
define void @device_leave_promiscuous_mode(i8* %0, i16 signext %1) {
%3 = tail call i32 @strlen(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0))
%4 = tail call i32 @strncmp(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i8* %0, i32 %3)
%5 = icmp eq i32 %4, 0
br i1 %5, label %8, label %6
6: ; preds = %2
%7 = tail call i32 @device_set_flags(i8* %0, i16 signext %1)
br label %8
8: ; preds = %2, %6
ret void
}
int f2(int x, int y) { return (x >= 0) == (y >= 0); }


x86 assembly (clang, -O0):
<f2>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
cmpl   $0x0,-0x4(%rbp)
setge  %al
and    $0x1,%al
movzbl %al,%eax
cmpl   $0x0,-0x8(%rbp)
setge  %cl
and    $0x1,%cl
movzbl %cl,%ecx
cmp    %ecx,%eax
sete   %al
and    $0x1,%al
movzbl %al,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<f2>:
mov    %edi,%eax
xor    %esi,%eax
not    %eax
shr    $0x1f,%eax
ret

LLVM IR (-O0):
define i32 @f2(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
store i32 %0, i32* %3
store i32 %1, i32* %4
%5 = load i32, i32* %3
%6 = icmp sge i32 %5, 0
%7 = zext i1 %6 to i32
%8 = load i32, i32* %4
%9 = icmp sge i32 %8, 0
%10 = zext i1 %9 to i32
%11 = icmp eq i32 %7, %10
%12 = zext i1 %11 to i32
ret i32 %12
}

LLVM IR (-O2):
define i32 @f2(i32 %0, i32 %1) {
%3 = xor i32 %0, %1
%4 = xor i32 %3, -1
%5 = lshr i32 %4, 31
ret i32 %5
}
double limite_valeur(double x, double limite) {
  if (x > 0) {
    if (x > limite) {
      x = limite;
    }
  } else {
    if (x < -limite) {
      x = -limite;
    }
  }
  return x;
}


x86 assembly (clang, -O0):
<limite_valeur>:
push   %rbp
mov    %rsp,%rbp
movsd  %xmm0,-0x8(%rbp)
movsd  %xmm1,-0x10(%rbp)
movsd  -0x8(%rbp),%xmm0
xorps  %xmm1,%xmm1
ucomisd %xmm1,%xmm0
jbe    113f <limite_valeur+0x3f>
movsd  -0x8(%rbp),%xmm0
ucomisd -0x10(%rbp),%xmm0
jbe    113a <limite_valeur+0x3a>
movsd  -0x10(%rbp),%xmm0
movsd  %xmm0,-0x8(%rbp)
jmp    1190 <limite_valeur+0x90>
movsd  -0x8(%rbp),%xmm1
movsd  -0x10(%rbp),%xmm0
movq   %xmm0,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm0
ucomisd %xmm1,%xmm0
jbe    118b <limite_valeur+0x8b>
movsd  -0x10(%rbp),%xmm0
movq   %xmm0,%rax
movabs $0x8000000000000000,%rcx
xor    %rcx,%rax
movq   %rax,%xmm0
movsd  %xmm0,-0x8(%rbp)
jmp    1190 <limite_valeur+0x90>
movsd  -0x8(%rbp),%xmm0
pop    %rbp
ret

x86 assembly (clang, -O2):
<limite_valeur>:
xorpd  %xmm2,%xmm2
ucomisd %xmm2,%xmm0
jbe    1112 <limite_valeur+0x12>
ucomisd %xmm1,%xmm0
ja     1120 <limite_valeur+0x20>
jmp    1124 <limite_valeur+0x24>
xorpd  0xee6(%rip),%xmm1
ucomisd %xmm0,%xmm1
jbe    1124 <limite_valeur+0x24>
movapd %xmm1,%xmm0
ret

LLVM IR (-O0):
define double @limite_valeur(double %0, double %1) {
%3 = alloca double
%4 = alloca double
store double %0, double* %3
store double %1, double* %4
%5 = load double, double* %3
%6 = fcmp ogt double %5, 0.000000e+00
br i1 %6, label %7, label %14
7: ; preds = %2
%8 = load double, double* %3
%9 = load double, double* %4
%10 = fcmp ogt double %8, %9
br i1 %10, label %11, label %13
11: ; preds = %7
%12 = load double, double* %4
store double %12, double* %3
br label %13
13: ; preds = %11, %7
br label %23
14: ; preds = %2
%15 = load double, double* %3
%16 = load double, double* %4
%17 = fneg double %16
%18 = fcmp olt double %15, %17
br i1 %18, label %19, label %22
19: ; preds = %14
%20 = load double, double* %4
%21 = fneg double %20
store double %21, double* %3
br label %22
22: ; preds = %19, %14
br label %23
23: ; preds = %22, %13
%24 = load double, double* %3
ret double %24
}

LLVM IR (-O2):
define double @limite_valeur(double %0, double %1) {
%3 = fcmp ogt double %0, 0.000000e+00
br i1 %3, label %4, label %7
4: ; preds = %2
%5 = fcmp ogt double %0, %1
br i1 %5, label %6, label %11
6: ; preds = %4
br label %11
7: ; preds = %2
%8 = fneg double %1
%9 = fcmp ogt double %8, %0
br i1 %9, label %10, label %11
10: ; preds = %7
br label %11
11: ; preds = %7, %10, %4, %6
%12 = phi double [ %1, %6 ], [ %0, %4 ], [ %8, %10 ], [ %0, %7 ]
ret double %12
}
int ti_rocr_start(double const *options) { return (int)options[0]; }


x86 assembly (clang, -O0):
<ti_rocr_start>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
cvttsd2si (%rax),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<ti_rocr_start>:
cvttsd2si (%rdi),%eax
ret

LLVM IR (-O0):
define i32 @ti_rocr_start(double* %0) {
%2 = alloca double*
store double* %0, double** %2
%3 = load double*, double** %2
%4 = getelementptr inbounds double, double* %3, i64 0
%5 = load double, double* %4
%6 = fptosi double %5 to i32
ret i32 %6
}

LLVM IR (-O2):
define i32 @ti_rocr_start(double* nocapture %0) {
%2 = load double, double* %0
%3 = fptosi double %2 to i32
ret i32 %3
}
/* Type definitions */
typedef int __le16;

/* Variables and functions */
int cpu_to_le16(int);
__le16 ieee802154_daddr_mode(__le16 fc) { return fc & cpu_to_le16(0x0c00); }


x86 assembly (clang, -O0):
<ieee802154_daddr_mode>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
mov    %eax,-0x8(%rbp)
mov    $0xc00,%edi
call   1030 <cpu_to_le16@plt>
mov    %eax,%ecx
mov    -0x8(%rbp),%eax
and    %ecx,%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<ieee802154_daddr_mode>:
push   %rbx
mov    %edi,%ebx
mov    $0xc00,%edi
call   1030 <cpu_to_le16@plt>
and    %ebx,%eax
pop    %rbx
ret

LLVM IR (-O0):
define i32 @ieee802154_daddr_mode(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i32 @cpu_to_le16(i32 3072)
%5 = and i32 %3, %4
ret i32 %5
}

LLVM IR (-O2):
define i32 @ieee802154_daddr_mode(i32 %0) {
%2 = tail call i32 @cpu_to_le16(i32 3072)
%3 = and i32 %2, %0
ret i32 %3
}
void intr_off(void) { asm volatile("cli"); }


x86 assembly (clang, -O0):
<intr_off>:
push   %rbp
mov    %rsp,%rbp
cli
pop    %rbp
ret

x86 assembly (clang, -O2):
<intr_off>:
cli
ret

LLVM IR (-O0):
define void @intr_off() {
ret void
}

LLVM IR (-O2):
define void @intr_off() {
tail call void asm sideeffect "cli", "~{dirflag},~{fpsr},~{flags}"()
ret void
}
/* Variables and functions */
int /*<<< orphan*/ NedAccelHandle();
int /*<<< orphan*/ UAVObjRequestUpdate(int /*<<< orphan*/);
void NedAccelRequestUpdate() { UAVObjRequestUpdate(NedAccelHandle()); }


x86 assembly (clang, -O0):
<NedAccelRequestUpdate>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <NedAccelHandle@plt>
mov    %eax,%edi
call   1040 <UAVObjRequestUpdate@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<NedAccelRequestUpdate>:
push   %rax
xor    %eax,%eax
call   1030 <NedAccelHandle@plt>
mov    %eax,%edi
pop    %rax
jmp    1040 <UAVObjRequestUpdate@plt>

LLVM IR (-O0):
define void @NedAccelRequestUpdate() {
%1 = call i32 (...) @NedAccelHandle()
%2 = call i32 @UAVObjRequestUpdate(i32 %1)
ret void
}

LLVM IR (-O2):
define void @NedAccelRequestUpdate() {
%1 = tail call i32 (...) @NedAccelHandle()
%2 = tail call i32 @UAVObjRequestUpdate(i32 %1)
ret void
}
void func5(void) {}


x86 assembly (clang, -O0):
<func5>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<func5>:
ret

LLVM IR (-O0):
define void @func5() {
ret void
}

LLVM IR (-O2):
define void @func5() {
ret void
}
/* Variables and functions */
char *U_WMRCORENONE_set(char *);
char *U_WMR7E_set(void) { return U_WMRCORENONE_set("U_WMR7E"); }


x86 assembly (clang, -O0):
<U_WMR7E_set>:
push   %rbp
mov    %rsp,%rbp
lea    0xee5(%rip),%rdi
call   1030 <U_WMRCORENONE_set@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<U_WMR7E_set>:
lea    0xee9(%rip),%rdi
jmp    1030 <U_WMRCORENONE_set@plt>

LLVM IR (-O0):
@.str = [8 x i8] c"U_WMR7E\00"
define i8* @U_WMR7E_set() {
%1 = call i8* @U_WMRCORENONE_set(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0))
ret i8* %1
}

LLVM IR (-O2):
@.str = [8 x i8] c"U_WMR7E\00"
define i8* @U_WMR7E_set() {
%1 = tail call i8* @U_WMRCORENONE_set(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0))
ret i8* %1
}
/* Type definitions */
typedef int /*<<< orphan*/ PROXY_CERT_INFO_EXTENSION;
typedef int /*<<< orphan*/ ASN1_VALUE;

/* Variables and functions */
int /*<<< orphan*/ ASN1_item_free(int /*<<< orphan*/ *, int /*<<< orphan*/ *);
int /*<<< orphan*/ PROXY_CERT_INFO_EXTENSION_it;
void PROXY_CERT_INFO_EXTENSION_free(PROXY_CERT_INFO_EXTENSION *a) {
  ASN1_item_free((ASN1_VALUE *)a, &PROXY_CERT_INFO_EXTENSION_it);
}


x86 assembly (clang, -O0):
<PROXY_CERT_INFO_EXTENSION_free>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
mov    0x2ec1(%rip),%rsi
call   1030 <ASN1_item_free@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<PROXY_CERT_INFO_EXTENSION_free>:
mov    0x2ed1(%rip),%rsi
jmp    1030 <ASN1_item_free@plt>

LLVM IR (-O0):
@PROXY_CERT_INFO_EXTENSION_it = global i32 0
define void @PROXY_CERT_INFO_EXTENSION_free(i32* %0) {
%2 = alloca i32*
store i32* %0, i32** %2
%3 = load i32*, i32** %2
%4 = call i32 @ASN1_item_free(i32* %3, i32* @PROXY_CERT_INFO_EXTENSION_it)
ret void
}

LLVM IR (-O2):
@PROXY_CERT_INFO_EXTENSION_it = global i32 0
define void @PROXY_CERT_INFO_EXTENSION_free(i32* %0) {
%2 = tail call i32 @ASN1_item_free(i32* %0, i32* @PROXY_CERT_INFO_EXTENSION_it)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ atanf(float);
long double tanl(int /*<<< orphan*/);
long double tanatanf(float x) { return (tanl(atanf(x))); }


x86 assembly (clang, -O0):
<tanatanf>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movss  %xmm0,-0x4(%rbp)
movss  -0x4(%rbp),%xmm0
call   1030 <atanf@plt>
mov    %eax,%edi
call   1040 <tanl@plt>
fld    %st(0)
fstp   %st(0)
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<tanatanf>:
push   %rax
call   1030 <atanf@plt>
mov    %eax,%edi
pop    %rax
jmp    1040 <tanl@plt>

LLVM IR (-O0):
define x86_fp80 @tanatanf(float %0) {
%2 = alloca float
store float %0, float* %2
%3 = load float, float* %2
%4 = call i32 @atanf(float %3)
%5 = call x86_fp80 @tanl(i32 %4)
ret x86_fp80 %5
}

LLVM IR (-O2):
define x86_fp80 @tanatanf(float %0) {
%2 = tail call i32 @atanf(float %0)
%3 = tail call x86_fp80 @tanl(i32 %2)
ret x86_fp80 %3
}
void gtk_widget_push_composite_child() {}


x86 assembly (clang, -O0):
<gtk_widget_push_composite_child>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gtk_widget_push_composite_child>:
ret

LLVM IR (-O0):
define void @gtk_widget_push_composite_child() {
ret void
}

LLVM IR (-O2):
define void @gtk_widget_push_composite_child() {
ret void
}