float call_float26(float (*f)(float, float, float, float, float, float, float,
                              float, float, float, float, float, float, float,
                              float, float, float, float, float, float, float,
                              float, float, float, float, float)) {
  return f(5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0,
           5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0);
}


x86 assembly (clang, -O0):
<call_float26>:
push   %rbp
mov    %rsp,%rbp
sub    $0xa0,%rsp
mov    %rdi,-0x8(%rbp)
movss  0xee8(%rip),%xmm8
movaps %xmm8,%xmm0
movaps %xmm8,%xmm1
movaps %xmm8,%xmm2
movaps %xmm8,%xmm3
movaps %xmm8,%xmm4
movaps %xmm8,%xmm5
movaps %xmm8,%xmm6
movaps %xmm8,%xmm7
movss  %xmm8,(%rsp)
movss  %xmm8,0x8(%rsp)
movss  %xmm8,0x10(%rsp)
movss  %xmm8,0x18(%rsp)
movss  %xmm8,0x20(%rsp)
movss  %xmm8,0x28(%rsp)
movss  %xmm8,0x30(%rsp)
movss  %xmm8,0x38(%rsp)
movss  %xmm8,0x40(%rsp)
movss  %xmm8,0x48(%rsp)
movss  %xmm8,0x50(%rsp)
movss  %xmm8,0x58(%rsp)
movss  %xmm8,0x60(%rsp)
movss  %xmm8,0x68(%rsp)
movss  %xmm8,0x70(%rsp)
movss  %xmm8,0x78(%rsp)
movss  %xmm8,0x80(%rsp)
movss  %xmm8,0x88(%rsp)
call   *-0x8(%rbp)
add    $0xa0,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<call_float26>:
push   %rax
movss  0xef7(%rip),%xmm0
movaps %xmm0,%xmm1
movaps %xmm0,%xmm2
movaps %xmm0,%xmm3
movaps %xmm0,%xmm4
movaps %xmm0,%xmm5
movaps %xmm0,%xmm6
movaps %xmm0,%xmm7
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
push   $0x40a00000
call   *%rdi
add    $0x90,%rsp
pop    %rax
ret

LLVM IR (-O0):
define float @call_float26(float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)* %0) {
%2 = alloca float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)*
store float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)* %0, float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)** %2
%3 = load float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)*, float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)** %2
%4 = call float %3(float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00)
ret float %4
}

LLVM IR (-O2):
define float @call_float26(float (float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float)* nocapture %0) {
%2 = tail call float %0(float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00, float 5.000000e+00)
ret float %2
}