#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */
typedef int uint32_t;

/* Variables and functions */
int mmio_read(int);
int /*<<< orphan*/ mmio_write(int, int);
int /*<<< orphan*/ printf(char *, int);
int sd_get_clock_divider(int, int);
int /*<<< orphan*/ usleep(int);
int sd_switch_clock_rate(uint32_t base_clock, uint32_t target_rate) {
  uint32_t divider = sd_get_clock_divider(base_clock, target_rate);
  if (divider == 0xffffffff) {
    printf("EMMC: couldn't get a valid divider for target rate %lu Hz\n",
           target_rate);
    return -1;
  }
  while (mmio_read(0x20300000 + 0x24) & 0x3)
    usleep(1000);
  uint32_t control1 = mmio_read(0x20300000 + 0x2C);
  control1 &= ~(1 << 2);
  mmio_write(0x20300000 + 0x2C, control1);
  usleep(2000);
  control1 &= ~0xffe0;
  control1 |= divider;
  mmio_write(0x20300000 + 0x2C, control1);
  usleep(2000);
  control1 |= (1 << 2);
  mmio_write(0x20300000 + 0x2C, control1);
  usleep(2000);
  return 0;
}


x86 assembly (clang, -O0):
<sd_switch_clock_rate>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    -0x8(%rbp),%edi
mov    -0xc(%rbp),%esi
call   1050 <sd_get_clock_divider@plt>
mov    %eax,-0x10(%rbp)
cmpl   $0xffffffff,-0x10(%rbp)
jne    1191 <sd_switch_clock_rate+0x41>
mov    -0xc(%rbp),%esi
lea    0xe80(%rip),%rdi
call   1030 <printf@plt>
movl   $0xffffffff,-0x4(%rbp)
jmp    123a <sd_switch_clock_rate+0xea>
jmp    1196 <sd_switch_clock_rate+0x46>
mov    $0x20300024,%edi
call   1040 <mmio_read@plt>
and    $0x3,%eax
cmp    $0x0,%eax
je     11bb <sd_switch_clock_rate+0x6b>
mov    $0x3e8,%edi
call   1070 <usleep@plt>
jmp    1196 <sd_switch_clock_rate+0x46>
mov    $0x2030002c,%edi
call   1040 <mmio_read@plt>
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
and    $0xfffffffb,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%esi
mov    $0x2030002c,%edi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
mov    -0x14(%rbp),%eax
and    $0xffff001f,%eax
mov    %eax,-0x14(%rbp)
mov    -0x10(%rbp),%eax
or     -0x14(%rbp),%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%esi
mov    $0x2030002c,%edi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
mov    -0x14(%rbp),%eax
or     $0x4,%eax
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%esi
mov    $0x2030002c,%edi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sd_switch_clock_rate>:
push   %rbp
push   %rbx
push   %rax
mov    %esi,%ebp
call   1050 <sd_get_clock_divider@plt>
cmp    $0xffffffff,%eax
je     11ea <sd_switch_clock_rate+0x9a>
mov    %eax,%ebx
cs nopw 0x0(%rax,%rax,1)
nop
mov    $0x20300024,%edi
call   1040 <mmio_read@plt>
test   $0x3,%al
je     118a <sd_switch_clock_rate+0x3a>
mov    $0x3e8,%edi
call   1070 <usleep@plt>
jmp    1170 <sd_switch_clock_rate+0x20>
mov    $0x2030002c,%edi
call   1040 <mmio_read@plt>
mov    %eax,%ebp
mov    %eax,%esi
and    $0xfffffffb,%esi
mov    $0x2030002c,%edi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
and    $0xffff001b,%ebp
or     %ebx,%ebp
mov    $0x2030002c,%edi
mov    %ebp,%esi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
or     $0x4,%ebp
mov    $0x2030002c,%edi
mov    %ebp,%esi
call   1060 <mmio_write@plt>
mov    $0x7d0,%edi
call   1070 <usleep@plt>
xor    %eax,%eax
jmp    11fd <sd_switch_clock_rate+0xad>
lea    0xe0f(%rip),%rdi
mov    %ebp,%esi
call   1030 <printf@plt>
mov    $0xffffffff,%eax
add    $0x8,%rsp
pop    %rbx
pop    %rbp
ret

LLVM IR (-O0):
@.str = [59 x i8] c"EMMC: couldn't get a valid divider for target rate %lu Hz\0A\00"
define i32 @sd_switch_clock_rate(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
%8 = load i32, i32* %4
%9 = load i32, i32* %5
%10 = call i32 @sd_get_clock_divider(i32 %8, i32 %9)
store i32 %10, i32* %6
%11 = load i32, i32* %6
%12 = icmp eq i32 %11, -1
br i1 %12, label %13, label %16
13: ; preds = %2
%14 = load i32, i32* %5
%15 = call i32 @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str, i64 0, i64 0), i32 %14)
store i32 -1, i32* %3
br label %43
16: ; preds = %2
br label %17
17: ; preds = %21, %16
%18 = call i32 @mmio_read(i32 540016676)
%19 = and i32 %18, 3
%20 = icmp ne i32 %19, 0
br i1 %20, label %21, label %23
21: ; preds = %17
%22 = call i32 @usleep(i32 1000)
br label %17
23: ; preds = %17
%24 = call i32 @mmio_read(i32 540016684)
store i32 %24, i32* %7
%25 = load i32, i32* %7
%26 = and i32 %25, -5
store i32 %26, i32* %7
%27 = load i32, i32* %7
%28 = call i32 @mmio_write(i32 540016684, i32 %27)
%29 = call i32 @usleep(i32 2000)
%30 = load i32, i32* %7
%31 = and i32 %30, -65505
store i32 %31, i32* %7
%32 = load i32, i32* %6
%33 = load i32, i32* %7
%34 = or i32 %33, %32
store i32 %34, i32* %7
%35 = load i32, i32* %7
%36 = call i32 @mmio_write(i32 540016684, i32 %35)
%37 = call i32 @usleep(i32 2000)
%38 = load i32, i32* %7
%39 = or i32 %38, 4
store i32 %39, i32* %7
%40 = load i32, i32* %7
%41 = call i32 @mmio_write(i32 540016684, i32 %40)
%42 = call i32 @usleep(i32 2000)
store i32 0, i32* %3
br label %43
43: ; preds = %23, %13
%44 = load i32, i32* %3
ret i32 %44
}

LLVM IR (-O2):
@.str = [59 x i8] c"EMMC: couldn't get a valid divider for target rate %lu Hz\0A\00"
define i32 @sd_switch_clock_rate(i32 %0, i32 %1) {
%3 = tail call i32 @sd_get_clock_divider(i32 %0, i32 %1)
%4 = icmp eq i32 %3, -1
br i1 %4, label %9, label %5
5: ; preds = %2
%6 = tail call i32 @mmio_read(i32 540016676)
%7 = and i32 %6, 3
%8 = icmp eq i32 %7, 0
br i1 %8, label %16, label %11
9: ; preds = %2
%10 = tail call i32 @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str, i64 0, i64 0), i32 %1)
br label %28
11: ; preds = %5, %11
%12 = tail call i32 @usleep(i32 1000)
%13 = tail call i32 @mmio_read(i32 540016676)
%14 = and i32 %13, 3
%15 = icmp eq i32 %14, 0
br i1 %15, label %16, label %11
16: ; preds = %11, %5
%17 = tail call i32 @mmio_read(i32 540016684)
%18 = and i32 %17, -5
%19 = tail call i32 @mmio_write(i32 540016684, i32 %18)
%20 = tail call i32 @usleep(i32 2000)
%21 = and i32 %17, -65509
%22 = or i32 %21, %3
%23 = tail call i32 @mmio_write(i32 540016684, i32 %22)
%24 = tail call i32 @usleep(i32 2000)
%25 = or i32 %22, 4
%26 = tail call i32 @mmio_write(i32 540016684, i32 %25)
%27 = tail call i32 @usleep(i32 2000)
br label %28
28: ; preds = %16, %9
%29 = phi i32 [ -1, %9 ], [ 0, %16 ]
ret i32 %29
}