char fs_bit_mask_set(short nbit, short value) {
  if (value)
    return 0xFF;
  if (nbit == 0)
    return 0x7F;
  else if (nbit == 1)
    return 0xBF;
  else if (nbit == 2)
    return 0xDF;
  else if (nbit == 3)
    return 0xEF;
  else if (nbit == 4)
    return 0xF7;
  else if (nbit == 5)
    return 0xFB;
  else if (nbit == 6)
    return 0xFD;
  else if (nbit == 7)
    return 0xFE;
  return 0xFF;
}


x86 assembly (clang, -O0):
<fs_bit_mask_set>:
push   %rbp
mov    %rsp,%rbp
mov    %si,%ax
mov    %di,%cx
mov    %cx,-0x4(%rbp)
mov    %ax,-0x6(%rbp)
cmpw   $0x0,-0x6(%rbp)
je     1126 <fs_bit_mask_set+0x26>
movb   $0xff,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x0,%eax
jne    113c <fs_bit_mask_set+0x3c>
movb   $0x7f,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x1,%eax
jne    1152 <fs_bit_mask_set+0x52>
movb   $0xbf,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x2,%eax
jne    1168 <fs_bit_mask_set+0x68>
movb   $0xdf,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x3,%eax
jne    117e <fs_bit_mask_set+0x7e>
movb   $0xef,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x4,%eax
jne    1194 <fs_bit_mask_set+0x94>
movb   $0xf7,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x5,%eax
jne    11aa <fs_bit_mask_set+0xaa>
movb   $0xfb,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x6,%eax
jne    11c0 <fs_bit_mask_set+0xc0>
movb   $0xfd,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
movswl -0x4(%rbp),%eax
cmp    $0x7,%eax
jne    11d6 <fs_bit_mask_set+0xd6>
movb   $0xfe,-0x1(%rbp)
jmp    11fd <fs_bit_mask_set+0xfd>
jmp    11db <fs_bit_mask_set+0xdb>
jmp    11e0 <fs_bit_mask_set+0xe0>
jmp    11e5 <fs_bit_mask_set+0xe5>
jmp    11ea <fs_bit_mask_set+0xea>
jmp    11ef <fs_bit_mask_set+0xef>
jmp    11f4 <fs_bit_mask_set+0xf4>
jmp    11f9 <fs_bit_mask_set+0xf9>
movb   $0xff,-0x1(%rbp)
movsbl -0x1(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<fs_bit_mask_set>:
lea    0x0(,%rdi,8),%ecx
movabs $0xfefdfbf7efdfbf7f,%rax
fb fd fe
shr    %cl,%rax
cmp    $0x8,%di
mov    $0xff,%ecx
cmovb  %eax,%ecx
neg    %si
sbb    %eax,%eax
or     %cl,%al
ret

LLVM IR (-O0):
define signext i8 @fs_bit_mask_set(i16 signext %0, i16 signext %1) {
%3 = alloca i8
%4 = alloca i16
%5 = alloca i16
store i16 %0, i16* %4
store i16 %1, i16* %5
%6 = load i16, i16* %5
%7 = icmp ne i16 %6, 0
br i1 %7, label %8, label %9
8: ; preds = %2
store i8 -1, i8* %3
br label %57
9: ; preds = %2
%10 = load i16, i16* %4
%11 = sext i16 %10 to i32
%12 = icmp eq i32 %11, 0
br i1 %12, label %13, label %14
13: ; preds = %9
store i8 127, i8* %3
br label %57
14: ; preds = %9
%15 = load i16, i16* %4
%16 = sext i16 %15 to i32
%17 = icmp eq i32 %16, 1
br i1 %17, label %18, label %19
18: ; preds = %14
store i8 -65, i8* %3
br label %57
19: ; preds = %14
%20 = load i16, i16* %4
%21 = sext i16 %20 to i32
%22 = icmp eq i32 %21, 2
br i1 %22, label %23, label %24
23: ; preds = %19
store i8 -33, i8* %3
br label %57
24: ; preds = %19
%25 = load i16, i16* %4
%26 = sext i16 %25 to i32
%27 = icmp eq i32 %26, 3
br i1 %27, label %28, label %29
28: ; preds = %24
store i8 -17, i8* %3
br label %57
29: ; preds = %24
%30 = load i16, i16* %4
%31 = sext i16 %30 to i32
%32 = icmp eq i32 %31, 4
br i1 %32, label %33, label %34
33: ; preds = %29
store i8 -9, i8* %3
br label %57
34: ; preds = %29
%35 = load i16, i16* %4
%36 = sext i16 %35 to i32
%37 = icmp eq i32 %36, 5
br i1 %37, label %38, label %39
38: ; preds = %34
store i8 -5, i8* %3
br label %57
39: ; preds = %34
%40 = load i16, i16* %4
%41 = sext i16 %40 to i32
%42 = icmp eq i32 %41, 6
br i1 %42, label %43, label %44
43: ; preds = %39
store i8 -3, i8* %3
br label %57
44: ; preds = %39
%45 = load i16, i16* %4
%46 = sext i16 %45 to i32
%47 = icmp eq i32 %46, 7
br i1 %47, label %48, label %49
48: ; preds = %44
store i8 -2, i8* %3
br label %57
49: ; preds = %44
br label %50
50: ; preds = %49
br label %51
51: ; preds = %50
br label %52
52: ; preds = %51
br label %53
53: ; preds = %52
br label %54
54: ; preds = %53
br label %55
55: ; preds = %54
br label %56
56: ; preds = %55
store i8 -1, i8* %3
br label %57
57: ; preds = %56, %48, %43, %38, %33, %28, %23, %18, %13, %8
%58 = load i8, i8* %3
ret i8 %58
}

LLVM IR (-O2):
define signext i8 @fs_bit_mask_set(i16 signext %0, i16 signext %1) {
%3 = icmp eq i16 %1, 0
%4 = icmp ult i16 %0, 8
%5 = and i1 %3, %4
%6 = zext i16 %0 to i64
%7 = shl nuw nsw i64 %6, 3
%8 = lshr i64 -72624976668147841, %7
%9 = trunc i64 %8 to i8
%10 = select i1 %5, i8 %9, i8 -1
ret i8 %10
}