void sdram_set_registers(void) {
  static const unsigned int register_values[] = {
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x44) & 0xFF)),
      0x0000f8f8,
      0x003f0000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x4C) & 0xFF)),
      0x0000f8f8,
      0x00000001,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x54) & 0xFF)),
      0x0000f8f8,
      0x00000002,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x5C) & 0xFF)),
      0x0000f8f8,
      0x00000003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x64) & 0xFF)),
      0x0000f8f8,
      0x00000004,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x6C) & 0xFF)),
      0x0000f8f8,
      0x00000005,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x74) & 0xFF)),
      0x0000f8f8,
      0x00000006,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x7C) & 0xFF)),
      0x0000f8f8,
      0x00000007,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x40) & 0xFF)),
      0x0000f8fc,
      0x00000003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x48) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x50) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x58) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x60) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x68) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x70) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x78) & 0xFF)),
      0x0000f8fc,
      0x00400000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x84) & 0xFF)),
      0x00000048,
      0x00e1ff00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x8C) & 0xFF)),
      0x00000048,
      0x00dfff00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x94) & 0xFF)),
      0x00000048,
      0x00e3ff00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x9C) & 0xFF)),
      0x00000048,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xA4) & 0xFF)),
      0x00000048,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xAC) & 0xFF)),
      0x00000048,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xB4) & 0xFF)),
      0x00000048,
      0x00000b00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xBC) & 0xFF)),
      0x00000048,
      0x00fe0b00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x80) & 0xFF)),
      0x000000f0,
      0x00e00003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x88) & 0xFF)),
      0x000000f0,
      0x00d80003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x90) & 0xFF)),
      0x000000f0,
      0x00e20003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0x98) & 0xFF)),
      0x000000f0,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xA0) & 0xFF)),
      0x000000f0,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xA8) & 0xFF)),
      0x000000f0,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xB0) & 0xFF)),
      0x000000f0,
      0x00000a03,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xB8) & 0xFF)),
      0x000000f0,
      0x00400003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xC4) & 0xFF)),
      0xFE000FC8,
      0x0000d000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xCC) & 0xFF)),
      0xFE000FC8,
      0x000ff000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xD4) & 0xFF)),
      0xFE000FC8,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xDC) & 0xFF)),
      0xFE000FC8,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xC0) & 0xFF)),
      0xFE000FCC,
      0x0000d003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xC8) & 0xFF)),
      0xFE000FCC,
      0x00001013,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xD0) & 0xFF)),
      0xFE000FCC,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xD8) & 0xFF)),
      0xFE000FCC,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xE0) & 0xFF)),
      0x0000FC88,
      0xff000003,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xE4) & 0xFF)),
      0x0000FC88,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xE8) & 0xFF)),
      0x0000FC88,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) |
       ((0xEC) & 0xFF)),
      0x0000FC88,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x40) & 0xFF)),
      0x001f01fe,
      0x00000001,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x44) & 0xFF)),
      0x001f01fe,
      0x01000001,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x48) & 0xFF)),
      0x001f01fe,
      0x02000001,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x4C) & 0xFF)),
      0x001f01fe,
      0x03000001,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x50) & 0xFF)),
      0x001f01fe,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x54) & 0xFF)),
      0x001f01fe,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x58) & 0xFF)),
      0x001f01fe,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x5C) & 0xFF)),
      0x001f01fe,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x60) & 0xFF)),
      0xC01f01ff,
      0x00e0fe00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x64) & 0xFF)),
      0xC01f01ff,
      0x00e0fe00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x68) & 0xFF)),
      0xC01f01ff,
      0x00e0fe00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x6C) & 0xFF)),
      0xC01f01ff,
      0x00e0fe00,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x70) & 0xFF)),
      0xC01f01ff,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x74) & 0xFF)),
      0xC01f01ff,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x78) & 0xFF)),
      0xC01f01ff,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x7C) & 0xFF)),
      0xC01f01ff,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x80) & 0xFF)),
      0xffff8888,
      0x00000033,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x88) & 0xFF)),
      0xe8088008,
      0x03623125,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x8c) & 0xFF)),
      0xff8fe08e,
      0x00000930,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x90) & 0xFF)),
      0xf0000000,
      (4 << 25) | (0 << 24) | (0 << 23) | (0 << 22) | (0 << 21) | (0 << 20) |
          (1 << 19) | (1 << 18) | (0 << 17) | (0 << 16) | (2 << 14) |
          (0 << 13) | (0 << 12) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
          (0 << 3) | (0 << 1) | (0 << 0),
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x94) & 0xFF)),
      0xc180f0f0,
      0x0e2b0a05,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) |
       ((0x98) & 0xFF)),
      0xfc00ffff,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) |
       ((0x58) & 0xFF)),
      0xffe0e0e0,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) |
       ((0x5C) & 0xFF)),
      0x0000003e,
      0x00000000,
      ((((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((3) & 0x07) << 8) |
       ((0x60) & 0xFF)),
      0xffffff00,
      0x00000000,
  };
  int i;
  int max;
  print_debug("setting up CPU0 northbridge registers\r\n");
  max = sizeof(register_values) / sizeof(register_values[0]);
  for (i = 0; i < max; i += 3) {
    unsigned long reg;
    reg = pci_read_config32(register_values[i]);
    reg &= register_values[i + 1];
    reg |= register_values[i + 2];
    pci_write_config32(register_values[i], reg);
  }
  print_debug("done.\r\n");
}


x86 assembly (clang, -O0):
<sdram_set_registers>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
lea    0x11fd(%rip),%rdi
mov    $0x0,%al
call   1050 <print_debug@plt>
movl   $0xcf,-0x8(%rbp)
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
cmp    -0x8(%rbp),%eax
jge    11d8 <sdram_set_registers+0xa8>
movslq -0x4(%rbp),%rcx
lea    0xe95(%rip),%rax
mov    (%rax,%rcx,4),%edi
mov    $0x0,%al
call   1030 <pci_read_config32@plt>
cltq
mov    %rax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
add    $0x1,%eax
movslq %eax,%rcx
lea    0xe75(%rip),%rax
mov    (%rax,%rcx,4),%eax
and    -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
add    $0x2,%eax
movslq %eax,%rcx
lea    0xe5a(%rip),%rax
mov    (%rax,%rcx,4),%eax
or     -0x10(%rbp),%rax
mov    %rax,-0x10(%rbp)
movslq -0x4(%rbp),%rcx
lea    0xe44(%rip),%rax
mov    (%rax,%rcx,4),%edi
mov    -0x10(%rbp),%rsi
mov    $0x0,%al
call   1040 <pci_write_config32@plt>
mov    -0x4(%rbp),%eax
add    $0x3,%eax
mov    %eax,-0x4(%rbp)
jmp    1154 <sdram_set_registers+0x24>
lea    0x1185(%rip),%rdi
mov    $0x0,%al
call   1050 <print_debug@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sdram_set_registers>:
push   %rbp
push   %r15
push   %r14
push   %rbx
push   %rax
lea    0x11fe(%rip),%rdi
xor    %eax,%eax
call   1050 <print_debug@plt>
mov    $0xfffffffffffffffd,%rbp
lea    0xead(%rip),%r15
cs nopw 0x0(%rax,%rax,1)
nopl   (%rax)
mov    0xc(%r15,%rbp,4),%r14d
mov    0x14(%r15,%rbp,4),%ebx
mov    %r14d,%edi
xor    %eax,%eax
call   1030 <pci_read_config32@plt>
and    0x10(%r15,%rbp,4),%eax
or     %rax,%rbx
mov    %r14d,%edi
mov    %rbx,%rsi
xor    %eax,%eax
call   1040 <pci_write_config32@plt>
add    $0x3,%rbp
cmp    $0xcc,%rbp
jb     1160 <sdram_set_registers+0x30>
lea    0x11c7(%rip),%rdi
xor    %eax,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r14
pop    %r15
pop    %rbp
jmp    1050 <print_debug@plt>

LLVM IR (-O0):
@sdram_set_registers.register_values = internal constant [207 x i32] [i32 49476, i32 63736, i32 4128768, i32 49484, i32 63736, i32 1, i32 49492, i32 63736, i32 2, i32 49500, i32 63736, i32 3, i32 49508, i32 63736, i32 4, i32 49516, i32 63736, i32 5, i32 49524, i32 63736, i32 6, i32 49532, i32 63736, i32 7, i32 49472, i32 63740, i32 3, i32 49480, i32 63740, i32 4194304, i32 49488, i32 63740, i32 4194304, i32 49496, i32 63740, i32 4194304, i32 49504, i32 63740, i32 4194304, i32 49512, i32 63740, i32 4194304, i32 49520, i32 63740, i32 4194304, i32 49528, i32 63740, i32 4194304, i32 49540, i32 72, i32 14810880, i32 49548, i32 72, i32 14679808, i32 49556, i32 72, i32 14941952, i32 49564, i32 72, i32 0, i32 49572, i32 72, i32 0, i32 49580, i32 72, i32 0, i32 49588, i32 72, i32 2816, i32 49596, i32 72, i32 16648960, i32 49536, i32 240, i32 14680067, i32 49544, i32 240, i32 14155779, i32 49552, i32 240, i32 14811139, i32 49560, i32 240, i32 0, i32 49568, i32 240, i32 0, i32 49576, i32 240, i32 0, i32 49584, i32 240, i32 2563, i32 49592, i32 240, i32 4194307, i32 49604, i32 -33550392, i32 53248, i32 49612, i32 -33550392, i32 1044480, i32 49620, i32 -33550392, i32 0, i32 49628, i32 -33550392, i32 0, i32 49600, i32 -33550388, i32 53251, i32 49608, i32 -33550388, i32 4115, i32 49616, i32 -33550388, i32 0, i32 49624, i32 -33550388, i32 0, i32 49632, i32 64648, i32 -16777213, i32 49636, i32 64648, i32 0, i32 49640, i32 64648, i32 0, i32 49644, i32 64648, i32 0, i32 49728, i32 2032126, i32 1, i32 49732, i32 2032126, i32 16777217, i32 49736, i32 2032126, i32 33554433, i32 49740, i32 2032126, i32 50331649, i32 49744, i32 2032126, i32 0, i32 49748, i32 2032126, i32 0, i32 49752, i32 2032126, i32 0, i32 49756, i32 2032126, i32 0, i32 49760, i32 -1071709697, i32 14745088, i32 49764, i32 -1071709697, i32 14745088, i32 49768, i32 -1071709697, i32 14745088, i32 49772, i32 -1071709697, i32 14745088, i32 49776, i32 -1071709697, i32 0, i32 49780, i32 -1071709697, i32 0, i32 49784, i32 -1071709697, i32 0, i32 49788, i32 -1071709697, i32 0, i32 49792, i32 -30584, i32 51, i32 49800, i32 -402096120, i32 56766757, i32 49804, i32 -7348082, i32 2352, i32 49808, i32 -268435456, i32 135036928, i32 49812, i32 -1048514320, i32 237701637, i32 49816, i32 -67043329, i32 0, i32 50008, i32 -2039584, i32 0, i32 50012, i32 62, i32 0, i32 50016, i32 -256, i32 0]
@.str = [40 x i8] c"setting up CPU0 northbridge registers\0D\0A\00"
@.str.1 = [8 x i8] c"done.\0D\0A\00"
define void @sdram_set_registers() {
%1 = alloca i32
%2 = alloca i32
%3 = alloca i64
%4 = call i32 (i8*, ...) bitcast (i32 (...)* @print_debug to i32 (i8*, ...)*)(i8* getelementptr inbounds ([40 x i8], [40 x i8]* @.str, i64 0, i64 0))
store i32 207, i32* %2
store i32 0, i32* %1
br label %5
5: ; preds = %38, %0
%6 = load i32, i32* %1
%7 = load i32, i32* %2
%8 = icmp slt i32 %6, %7
br i1 %8, label %9, label %41
9: ; preds = %5
%10 = load i32, i32* %1
%11 = sext i32 %10 to i64
%12 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %11
%13 = load i32, i32* %12
%14 = call i32 (i32, ...) bitcast (i32 (...)* @pci_read_config32 to i32 (i32, ...)*)(i32 %13)
%15 = sext i32 %14 to i64
store i64 %15, i64* %3
%16 = load i32, i32* %1
%17 = add nsw i32 %16, 1
%18 = sext i32 %17 to i64
%19 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %18
%20 = load i32, i32* %19
%21 = zext i32 %20 to i64
%22 = load i64, i64* %3
%23 = and i64 %22, %21
store i64 %23, i64* %3
%24 = load i32, i32* %1
%25 = add nsw i32 %24, 2
%26 = sext i32 %25 to i64
%27 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %26
%28 = load i32, i32* %27
%29 = zext i32 %28 to i64
%30 = load i64, i64* %3
%31 = or i64 %30, %29
store i64 %31, i64* %3
%32 = load i32, i32* %1
%33 = sext i32 %32 to i64
%34 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %33
%35 = load i32, i32* %34
%36 = load i64, i64* %3
%37 = call i32 (i32, i64, ...) bitcast (i32 (...)* @pci_write_config32 to i32 (i32, i64, ...)*)(i32 %35, i64 %36)
br label %38
38: ; preds = %9
%39 = load i32, i32* %1
%40 = add nsw i32 %39, 3
store i32 %40, i32* %1
br label %5
41: ; preds = %5
%42 = call i32 (i8*, ...) bitcast (i32 (...)* @print_debug to i32 (i8*, ...)*)(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.1, i64 0, i64 0))
ret void
}

LLVM IR (-O2):
@sdram_set_registers.register_values = internal unnamed_addr constant [207 x i32] [i32 49476, i32 63736, i32 4128768, i32 49484, i32 63736, i32 1, i32 49492, i32 63736, i32 2, i32 49500, i32 63736, i32 3, i32 49508, i32 63736, i32 4, i32 49516, i32 63736, i32 5, i32 49524, i32 63736, i32 6, i32 49532, i32 63736, i32 7, i32 49472, i32 63740, i32 3, i32 49480, i32 63740, i32 4194304, i32 49488, i32 63740, i32 4194304, i32 49496, i32 63740, i32 4194304, i32 49504, i32 63740, i32 4194304, i32 49512, i32 63740, i32 4194304, i32 49520, i32 63740, i32 4194304, i32 49528, i32 63740, i32 4194304, i32 49540, i32 72, i32 14810880, i32 49548, i32 72, i32 14679808, i32 49556, i32 72, i32 14941952, i32 49564, i32 72, i32 0, i32 49572, i32 72, i32 0, i32 49580, i32 72, i32 0, i32 49588, i32 72, i32 2816, i32 49596, i32 72, i32 16648960, i32 49536, i32 240, i32 14680067, i32 49544, i32 240, i32 14155779, i32 49552, i32 240, i32 14811139, i32 49560, i32 240, i32 0, i32 49568, i32 240, i32 0, i32 49576, i32 240, i32 0, i32 49584, i32 240, i32 2563, i32 49592, i32 240, i32 4194307, i32 49604, i32 -33550392, i32 53248, i32 49612, i32 -33550392, i32 1044480, i32 49620, i32 -33550392, i32 0, i32 49628, i32 -33550392, i32 0, i32 49600, i32 -33550388, i32 53251, i32 49608, i32 -33550388, i32 4115, i32 49616, i32 -33550388, i32 0, i32 49624, i32 -33550388, i32 0, i32 49632, i32 64648, i32 -16777213, i32 49636, i32 64648, i32 0, i32 49640, i32 64648, i32 0, i32 49644, i32 64648, i32 0, i32 49728, i32 2032126, i32 1, i32 49732, i32 2032126, i32 16777217, i32 49736, i32 2032126, i32 33554433, i32 49740, i32 2032126, i32 50331649, i32 49744, i32 2032126, i32 0, i32 49748, i32 2032126, i32 0, i32 49752, i32 2032126, i32 0, i32 49756, i32 2032126, i32 0, i32 49760, i32 -1071709697, i32 14745088, i32 49764, i32 -1071709697, i32 14745088, i32 49768, i32 -1071709697, i32 14745088, i32 49772, i32 -1071709697, i32 14745088, i32 49776, i32 -1071709697, i32 0, i32 49780, i32 -1071709697, i32 0, i32 49784, i32 -1071709697, i32 0, i32 49788, i32 -1071709697, i32 0, i32 49792, i32 -30584, i32 51, i32 49800, i32 -402096120, i32 56766757, i32 49804, i32 -7348082, i32 2352, i32 49808, i32 -268435456, i32 135036928, i32 49812, i32 -1048514320, i32 237701637, i32 49816, i32 -67043329, i32 0, i32 50008, i32 -2039584, i32 0, i32 50012, i32 62, i32 0, i32 50016, i32 -256, i32 0]
@.str = [40 x i8] c"setting up CPU0 northbridge registers\0D\0A\00"
@.str.1 = [8 x i8] c"done.\0D\0A\00"
define void @sdram_set_registers() {
%1 = tail call i32 (i8*, ...) bitcast (i32 (...)* @print_debug to i32 (i8*, ...)*)(i8* getelementptr inbounds ([40 x i8], [40 x i8]* @.str, i64 0, i64 0))
br label %2
2: ; preds = %0, %2
%3 = phi i64 [ 0, %0 ], [ %17, %2 ]
%4 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %3
%5 = load i32, i32* %4
%6 = tail call i32 (i32, ...) bitcast (i32 (...)* @pci_read_config32 to i32 (i32, ...)*)(i32 %5)
%7 = add nuw nsw i64 %3, 1
%8 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %7
%9 = load i32, i32* %8
%10 = and i32 %9, %6
%11 = add nuw nsw i64 %3, 2
%12 = getelementptr inbounds [207 x i32], [207 x i32]* @sdram_set_registers.register_values, i64 0, i64 %11
%13 = load i32, i32* %12
%14 = or i32 %10, %13
%15 = zext i32 %14 to i64
%16 = tail call i32 (i32, i64, ...) bitcast (i32 (...)* @pci_write_config32 to i32 (i32, i64, ...)*)(i32 %5, i64 %15)
%17 = add nuw nsw i64 %3, 3
%18 = icmp ult i64 %3, 204
br i1 %18, label %2, label %19
19: ; preds = %2
%20 = tail call i32 (i8*, ...) bitcast (i32 (...)* @print_debug to i32 (i8*, ...)*)(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str.1, i64 0, i64 0))
ret void
}