xunge/DecIR huggingface dataset:
/* Type definitions */
typedef int /*<<< orphan*/ FILE;

/* Variables and functions */
int read_char(int /*<<< orphan*/ *);
int parse_eol(FILE *f) {
  int c = read_char(f);
  while (c != -1 && c != '\n') {
    c = read_char(f);
  }
  return c == -1 ? c : read_char(f);
}


x86 assembly (clang, -O0):
<parse_eol>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rdi
call   1030 <read_char@plt>
mov    %eax,-0xc(%rbp)
xor    %eax,%eax
cmpl   $0xffffffff,-0xc(%rbp)
mov    %al,-0xd(%rbp)
je     1141 <parse_eol+0x31>
cmpl   $0xa,-0xc(%rbp)
setne  %al
mov    %al,-0xd(%rbp)
mov    -0xd(%rbp),%al
test   $0x1,%al
jne    1151 <parse_eol+0x41>
jmp    1162 <parse_eol+0x52>
mov    -0x8(%rbp),%rdi
call   1030 <read_char@plt>
mov    %eax,-0xc(%rbp)
jmp    1128 <parse_eol+0x18>
cmpl   $0xffffffff,-0xc(%rbp)
jne    1177 <parse_eol+0x67>
mov    -0xc(%rbp),%eax
mov    %eax,-0x14(%rbp)
jmp    1183 <parse_eol+0x73>
mov    -0x8(%rbp),%rdi
call   1030 <read_char@plt>
mov    %eax,-0x14(%rbp)
mov    -0x14(%rbp),%eax
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<parse_eol>:
push   %rbx
mov    %rdi,%rbx
cs nopw 0x0(%rax,%rax,1)
xchg   %ax,%ax
mov    %rbx,%rdi
call   1030 <read_char@plt>
cmp    $0xffffffff,%eax
je     113b <parse_eol+0x2b>
cmp    $0xa,%eax
jne    1120 <parse_eol+0x10>
mov    %rbx,%rdi
pop    %rbx
jmp    1030 <read_char@plt>
pop    %rbx
ret

LLVM IR (-O0):
define i32 @parse_eol(i32* %0) {
%2 = alloca i32*
%3 = alloca i32
store i32* %0, i32** %2
%4 = load i32*, i32** %2
%5 = call i32 @read_char(i32* %4)
store i32 %5, i32* %3
br label %6
6: ; preds = %14, %1
%7 = load i32, i32* %3
%8 = icmp ne i32 %7, -1
br i1 %8, label %9, label %12
9: ; preds = %6
%10 = load i32, i32* %3
%11 = icmp ne i32 %10, 10
br label %12
12: ; preds = %9, %6
%13 = phi i1 [ false, %6 ], [ %11, %9 ]
br i1 %13, label %14, label %17
14: ; preds = %12
%15 = load i32*, i32** %2
%16 = call i32 @read_char(i32* %15)
store i32 %16, i32* %3
br label %6
17: ; preds = %12
%18 = load i32, i32* %3
%19 = icmp eq i32 %18, -1
br i1 %19, label %20, label %22
20: ; preds = %17
%21 = load i32, i32* %3
br label %25
22: ; preds = %17
%23 = load i32*, i32** %2
%24 = call i32 @read_char(i32* %23)
br label %25
25: ; preds = %22, %20
%26 = phi i32 [ %21, %20 ], [ %24, %22 ]
ret i32 %26
}

LLVM IR (-O2):
define i32 @parse_eol(i32* %0) {
br label %2
2: ; preds = %2, %1
%3 = tail call i32 @read_char(i32* %0)
switch i32 %3, label %2 [
i32 -1, label %6
i32 10, label %4
]
4: ; preds = %2
%5 = tail call i32 @read_char(i32* %0)
br label %6
6: ; preds = %2, %4
%7 = phi i32 [ %5, %4 ], [ %3, %2 ]
ret i32 %7
}
/* Type definitions */
struct sline {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ sline_reset(struct sline *);
int /*<<< orphan*/ sline_setbuf(struct sline *, char *, int);
void sline_init(struct sline *sl, char *buffer, int bufcap) {
  sline_setbuf(sl, buffer, bufcap);
  sline_reset(sl);
}


x86 assembly (clang, -O0):
<sline_init>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %edx,-0x14(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
mov    -0x14(%rbp),%edx
call   1030 <sline_setbuf@plt>
mov    -0x8(%rbp),%rdi
call   1040 <sline_reset@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sline_init>:
push   %rbx
mov    %rdi,%rbx
call   1030 <sline_setbuf@plt>
mov    %rbx,%rdi
pop    %rbx
jmp    1040 <sline_reset@plt>

LLVM IR (-O0):
%struct.sline = type { i32 }
define void @sline_init(%struct.sline* %0, i8* %1, i32 %2) {
%4 = alloca %struct.sline*
%5 = alloca i8*
%6 = alloca i32
store %struct.sline* %0, %struct.sline** %4
store i8* %1, i8** %5
store i32 %2, i32* %6
%7 = load %struct.sline*, %struct.sline** %4
%8 = load i8*, i8** %5
%9 = load i32, i32* %6
%10 = call i32 @sline_setbuf(%struct.sline* %7, i8* %8, i32 %9)
%11 = load %struct.sline*, %struct.sline** %4
%12 = call i32 @sline_reset(%struct.sline* %11)
ret void
}

LLVM IR (-O2):
%struct.sline = type { i32 }
define void @sline_init(%struct.sline* %0, i8* %1, i32 %2) {
%4 = tail call i32 @sline_setbuf(%struct.sline* %0, i8* %1, i32 %2)
%5 = tail call i32 @sline_reset(%struct.sline* %0)
ret void
}
/* Variables and functions */
double roundRoot(double);
void roundRoots(double *r, unsigned int _r_high, unsigned int n) {
  unsigned int i;
  i = 0;
  while (i < n) {
    r[i] = roundRoot(r[i]);
    i += 1;
  }
}


x86 assembly (clang, -O0):
<roundRoots>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
mov    %edx,-0x10(%rbp)
movl   $0x0,-0x14(%rbp)
mov    -0x14(%rbp),%eax
cmp    -0x10(%rbp),%eax
jae    1160 <roundRoots+0x50>
mov    -0x8(%rbp),%rax
mov    -0x14(%rbp),%ecx
movsd  (%rax,%rcx,8),%xmm0
call   1030 <roundRoot@plt>
mov    -0x8(%rbp),%rax
mov    -0x14(%rbp),%ecx
movsd  %xmm0,(%rax,%rcx,8)
mov    -0x14(%rbp),%eax
add    $0x1,%eax
mov    %eax,-0x14(%rbp)
jmp    1129 <roundRoots+0x19>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<roundRoots>:
push   %r15
push   %r14
push   %rbx
test   %edx,%edx
je     114a <roundRoots+0x3a>
mov    %rdi,%r15
mov    %edx,%r14d
xor    %ebx,%ebx
cs nopw 0x0(%rax,%rax,1)
nopl   0x0(%rax,%rax,1)
movsd  (%r15,%rbx,8),%xmm0
call   1030 <roundRoot@plt>
movsd  %xmm0,(%r15,%rbx,8)
add    $0x1,%rbx
cmp    %rbx,%r14
jne    1130 <roundRoots+0x20>
pop    %rbx
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define void @roundRoots(double* %0, i32 %1, i32 %2) {
%4 = alloca double*
%5 = alloca i32
%6 = alloca i32
%7 = alloca i32
store double* %0, double** %4
store i32 %1, i32* %5
store i32 %2, i32* %6
store i32 0, i32* %7
br label %8
8: ; preds = %12, %3
%9 = load i32, i32* %7
%10 = load i32, i32* %6
%11 = icmp ult i32 %9, %10
br i1 %11, label %12, label %25
12: ; preds = %8
%13 = load double*, double** %4
%14 = load i32, i32* %7
%15 = zext i32 %14 to i64
%16 = getelementptr inbounds double, double* %13, i64 %15
%17 = load double, double* %16
%18 = call double @roundRoot(double %17)
%19 = load double*, double** %4
%20 = load i32, i32* %7
%21 = zext i32 %20 to i64
%22 = getelementptr inbounds double, double* %19, i64 %21
store double %18, double* %22
%23 = load i32, i32* %7
%24 = add i32 %23, 1
store i32 %24, i32* %7
br label %8
25: ; preds = %8
ret void
}

LLVM IR (-O2):
define void @roundRoots(double* nocapture %0, i32 %1, i32 %2) {
%4 = icmp eq i32 %2, 0
br i1 %4, label %14, label %5
5: ; preds = %3
%6 = zext i32 %2 to i64
br label %7
7: ; preds = %5, %7
%8 = phi i64 [ 0, %5 ], [ %12, %7 ]
%9 = getelementptr inbounds double, double* %0, i64 %8
%10 = load double, double* %9
%11 = tail call double @roundRoot(double %10)
store double %11, double* %9
%12 = add nuw nsw i64 %8, 1
%13 = icmp eq i64 %12, %6
br i1 %13, label %14, label %7
14: ; preds = %7, %3
ret void
}
/* Variables and functions */
int /*<<< orphan*/ rk29sdk_wifi_set_carddetect(unsigned int);
void sif_platform_rescan_card(unsigned insert) {
  rk29sdk_wifi_set_carddetect(insert);
}


x86 assembly (clang, -O0):
<sif_platform_rescan_card>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%edi
call   1030 <rk29sdk_wifi_set_carddetect@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<sif_platform_rescan_card>:
jmp    1030 <rk29sdk_wifi_set_carddetect@plt>

LLVM IR (-O0):
define void @sif_platform_rescan_card(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = call i32 @rk29sdk_wifi_set_carddetect(i32 %3)
ret void
}

LLVM IR (-O2):
define void @sif_platform_rescan_card(i32 %0) {
%2 = tail call i32 @rk29sdk_wifi_set_carddetect(i32 %0)
ret void
}
long stub_syscall4(long syscall, long arg1, long arg2, long arg3, long arg4) {
  long ret;
  __asm__ volatile("int $0x80"
                   : "=a"(ret)
                   : "0"(syscall), "b"(arg1), "c"(arg2), "d"(arg3), "S"(arg4));
  return ret;
}


x86 assembly (clang, -O0):
<stub_syscall4>:
push   %rbp
mov    %rsp,%rbp
push   %rbx
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
mov    %rdx,-0x20(%rbp)
mov    %rcx,-0x28(%rbp)
mov    %r8,-0x30(%rbp)
mov    -0x10(%rbp),%rax
mov    -0x18(%rbp),%rbx
mov    -0x20(%rbp),%rcx
mov    -0x28(%rbp),%rdx
mov    -0x30(%rbp),%rsi
int    $0x80
mov    %rax,-0x38(%rbp)
mov    -0x38(%rbp),%rax
pop    %rbx
pop    %rbp
ret

x86 assembly (clang, -O2):
<stub_syscall4>:
push   %rbx
mov    %rcx,%rax
mov    %rdx,%rcx
mov    %rsi,%rbx
mov    %rax,%rdx
mov    %r8,%rsi
mov    %rdi,%rax
int    $0x80
pop    %rbx
ret

LLVM IR (-O0):
define i64 @stub_syscall4(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4) {
%6 = alloca i64
%7 = alloca i64
%8 = alloca i64
%9 = alloca i64
%10 = alloca i64
%11 = alloca i64
store i64 %0, i64* %6
store i64 %1, i64* %7
store i64 %2, i64* %8
store i64 %3, i64* %9
store i64 %4, i64* %10
%12 = load i64, i64* %6
%13 = load i64, i64* %7
%14 = load i64, i64* %8
%15 = load i64, i64* %9
%16 = load i64, i64* %10
%17 = call i64 asm sideeffect "int $$0x80", "={ax},0,{bx},{cx},{dx},{si},~{dirflag},~{fpsr},~{flags}"(i64 %12, i64 %13, i64 %14, i64 %15, i64 %16)
store i64 %17, i64* %11
%18 = load i64, i64* %11
ret i64 %18
}

LLVM IR (-O2):
define i64 @stub_syscall4(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4) {
%6 = tail call i64 asm sideeffect "int $$0x80", "={ax},0,{bx},{cx},{dx},{si},~{dirflag},~{fpsr},~{flags}"(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4)
ret i64 %6
}
int Read_Keypad() {
  int keypad_val = 1;
  return keypad_val;
}


x86 assembly (clang, -O0):
<Read_Keypad>:
push   %rbp
mov    %rsp,%rbp
movl   $0x1,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<Read_Keypad>:
mov    $0x1,%eax
ret

LLVM IR (-O0):
define i32 @Read_Keypad() {
%1 = alloca i32
store i32 1, i32* %1
%2 = load i32, i32* %1
ret i32 %2
}

LLVM IR (-O2):
define i32 @Read_Keypad() {
ret i32 1
}
void serial_out(char *str) {
  while (*str) {
    *(char *)0xffffffffb80003f8 = *str++;
  }
}


x86 assembly (clang, -O0):
<serial_out>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
cmpb   $0x0,(%rax)
je     1134 <serial_out+0x34>
mov    -0x8(%rbp),%rax
mov    %rax,%rcx
add    $0x1,%rcx
mov    %rcx,-0x8(%rbp)
mov    (%rax),%cl
mov    $0xffffffffb80003f8,%rax
mov    %cl,(%rax)
jmp    1108 <serial_out+0x8>
pop    %rbp
ret

x86 assembly (clang, -O2):
<serial_out>:
mov    (%rdi),%al
test   %al,%al
je     1122 <serial_out+0x22>
add    $0x1,%rdi
nopw   0x0(%rax,%rax,1)
mov    %al,0xffffffffb80003f8
movzbl (%rdi),%eax
add    $0x1,%rdi
test   %al,%al
jne    1110 <serial_out+0x10>
ret

LLVM IR (-O0):
define void @serial_out(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
br label %3
3: ; preds = %7, %1
%4 = load i8*, i8** %2
%5 = load i8, i8* %4
%6 = icmp ne i8 %5, 0
br i1 %6, label %7, label %11
7: ; preds = %3
%8 = load i8*, i8** %2
%9 = getelementptr inbounds i8, i8* %8, i32 1
store i8* %9, i8** %2
%10 = load i8, i8* %8
store i8 %10, i8* inttoptr (i64 -1207958536 to i8*)
br label %3
11: ; preds = %3
ret void
}

LLVM IR (-O2):
define void @serial_out(i8* nocapture %0) {
%2 = load i8, i8* %0
%3 = icmp eq i8 %2, 0
br i1 %3, label %10, label %4
4: ; preds = %1, %4
%5 = phi i8 [ %8, %4 ], [ %2, %1 ]
%6 = phi i8* [ %7, %4 ], [ %0, %1 ]
%7 = getelementptr inbounds i8, i8* %6, i64 1
store i8 %5, i8* inttoptr (i64 -1207958536 to i8*)
%8 = load i8, i8* %7
%9 = icmp eq i8 %8, 0
br i1 %9, label %10, label %4
10: ; preds = %4, %1
ret void
}
/* Variables and functions */
int /*<<< orphan*/ unimplemented();
void stii_dir(void) { unimplemented(); }


x86 assembly (clang, -O0):
<stii_dir>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1030 <unimplemented@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<stii_dir>:
xor    %eax,%eax
jmp    1030 <unimplemented@plt>

LLVM IR (-O0):
define void @stii_dir() {
%1 = call i32 (...) @unimplemented()
ret void
}

LLVM IR (-O2):
define void @stii_dir() {
%1 = tail call i32 (...) @unimplemented()
ret void
}
/* Type definitions */
struct sembuf {
  int sem_num;
  int sem_op;
  scalar_t__ sem_flg;
};

/* Variables and functions */
int /*<<< orphan*/ semop(int, struct sembuf *, int);
void mutex_wait(int semid, int sem_num) {
  struct sembuf op;
  op.sem_num = sem_num;
  op.sem_op = -1;
  op.sem_flg = 0;
  semop(semid, &op, 1);
}


x86 assembly (clang, -O0):
<mutex_wait>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %esi,-0x8(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,-0x18(%rbp)
movl   $0xffffffff,-0x14(%rbp)
movq   $0x0,-0x10(%rbp)
mov    -0x4(%rbp),%edi
lea    -0x18(%rbp),%rsi
mov    $0x1,%edx
call   1030 <semop@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<mutex_wait>:
sub    $0x18,%rsp
mov    %esi,0x8(%rsp)
movl   $0xffffffff,0xc(%rsp)
ff
movq   $0x0,0x10(%rsp)
lea    0x8(%rsp),%rsi
mov    $0x1,%edx
call   1030 <semop@plt>
add    $0x18,%rsp
ret

LLVM IR (-O0):
%struct.sembuf = type { i32, i32, i64 }
define void @mutex_wait(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca %struct.sembuf
store i32 %0, i32* %3
store i32 %1, i32* %4
%6 = load i32, i32* %4
%7 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %5, i32 0, i32 0
store i32 %6, i32* %7
%8 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %5, i32 0, i32 1
store i32 -1, i32* %8
%9 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %5, i32 0, i32 2
store i64 0, i64* %9
%10 = load i32, i32* %3
%11 = call i32 @semop(i32 %10, %struct.sembuf* %5, i32 1)
ret void
}

LLVM IR (-O2):
%struct.sembuf = type { i32, i32, i64 }
define void @mutex_wait(i32 %0, i32 %1) {
%3 = alloca %struct.sembuf
%4 = bitcast %struct.sembuf* %3 to i8*
%5 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %3, i64 0, i32 0
store i32 %1, i32* %5
%6 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %3, i64 0, i32 1
store i32 -1, i32* %6
%7 = getelementptr inbounds %struct.sembuf, %struct.sembuf* %3, i64 0, i32 2
store i64 0, i64* %7
%8 = call i32 @semop(i32 %0, %struct.sembuf* %3, i32 1)
ret void
}
unsigned char galois_mul2(unsigned char value) {
  if (value >> 7) {
    value = value << 1;
    return (value ^ 0x1b);
  } else
    return value << 1;
}


x86 assembly (clang, -O0):
<galois_mul2>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x2(%rbp)
movzbl -0x2(%rbp),%eax
sar    $0x7,%eax
cmp    $0x0,%eax
je     1133 <galois_mul2+0x33>
movzbl -0x2(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x2(%rbp)
movzbl -0x2(%rbp),%eax
xor    $0x1b,%eax
mov    %al,-0x1(%rbp)
jmp    113d <galois_mul2+0x3d>
movzbl -0x2(%rbp),%eax
shl    $0x1,%eax
mov    %al,-0x1(%rbp)
movzbl -0x1(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<galois_mul2>:
lea    (%rdi,%rdi,1),%eax
movzbl %al,%ecx
xor    $0x1b,%al
test   %dil,%dil
movzbl %al,%eax
cmovns %ecx,%eax
ret

LLVM IR (-O0):
define zeroext i8 @galois_mul2(i8 zeroext %0) {
%2 = alloca i8
%3 = alloca i8
store i8 %0, i8* %3
%4 = load i8, i8* %3
%5 = zext i8 %4 to i32
%6 = ashr i32 %5, 7
%7 = icmp ne i32 %6, 0
br i1 %7, label %8, label %17
8: ; preds = %1
%9 = load i8, i8* %3
%10 = zext i8 %9 to i32
%11 = shl i32 %10, 1
%12 = trunc i32 %11 to i8
store i8 %12, i8* %3
%13 = load i8, i8* %3
%14 = zext i8 %13 to i32
%15 = xor i32 %14, 27
%16 = trunc i32 %15 to i8
store i8 %16, i8* %2
br label %22
17: ; preds = %1
%18 = load i8, i8* %3
%19 = zext i8 %18 to i32
%20 = shl i32 %19, 1
%21 = trunc i32 %20 to i8
store i8 %21, i8* %2
br label %22
22: ; preds = %17, %8
%23 = load i8, i8* %2
ret i8 %23
}

LLVM IR (-O2):
define zeroext i8 @galois_mul2(i8 zeroext %0) {
%2 = icmp sgt i8 %0, -1
%3 = shl i8 %0, 1
%4 = xor i8 %3, 27
%5 = select i1 %2, i8 %3, i8 %4
ret i8 %5
}
void opcode_dcx(unsigned char *upper, unsigned char *lower) {
  unsigned short int temp = ((*upper << 8) | *lower);
  temp--;
  *upper = temp >> 8;
  *lower = temp & 0xFF;
}


x86 assembly (clang, -O0):
<opcode_dcx>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rax
movzbl (%rax),%eax
shl    $0x8,%eax
mov    -0x10(%rbp),%rcx
movzbl (%rcx),%ecx
or     %ecx,%eax
mov    %ax,-0x12(%rbp)
mov    -0x12(%rbp),%ax
add    $0xffff,%ax
mov    %ax,-0x12(%rbp)
movzwl -0x12(%rbp),%eax
sar    $0x8,%eax
mov    %al,%cl
mov    -0x8(%rbp),%rax
mov    %cl,(%rax)
movzwl -0x12(%rbp),%eax
and    $0xff,%eax
mov    %al,%cl
mov    -0x10(%rbp),%rax
mov    %cl,(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<opcode_dcx>:
movzbl (%rdi),%eax
shl    $0x8,%eax
movzbl (%rsi),%ecx
add    %ecx,%eax
add    $0xffff,%eax
mov    %ah,(%rdi)
mov    %al,(%rsi)
ret

LLVM IR (-O0):
define void @opcode_dcx(i8* %0, i8* %1) {
%3 = alloca i8*
%4 = alloca i8*
%5 = alloca i16
store i8* %0, i8** %3
store i8* %1, i8** %4
%6 = load i8*, i8** %3
%7 = load i8, i8* %6
%8 = zext i8 %7 to i32
%9 = shl i32 %8, 8
%10 = load i8*, i8** %4
%11 = load i8, i8* %10
%12 = zext i8 %11 to i32
%13 = or i32 %9, %12
%14 = trunc i32 %13 to i16
store i16 %14, i16* %5
%15 = load i16, i16* %5
%16 = add i16 %15, -1
store i16 %16, i16* %5
%17 = load i16, i16* %5
%18 = zext i16 %17 to i32
%19 = ashr i32 %18, 8
%20 = trunc i32 %19 to i8
%21 = load i8*, i8** %3
store i8 %20, i8* %21
%22 = load i16, i16* %5
%23 = zext i16 %22 to i32
%24 = and i32 %23, 255
%25 = trunc i32 %24 to i8
%26 = load i8*, i8** %4
store i8 %25, i8* %26
ret void
}

LLVM IR (-O2):
define void @opcode_dcx(i8* nocapture %0, i8* nocapture %1) {
%3 = load i8, i8* %0
%4 = zext i8 %3 to i32
%5 = shl nuw nsw i32 %4, 8
%6 = load i8, i8* %1
%7 = zext i8 %6 to i32
%8 = or i32 %5, %7
%9 = add nuw nsw i32 %8, 65535
%10 = lshr i32 %9, 8
%11 = trunc i32 %10 to i8
store i8 %11, i8* %0
%12 = trunc i32 %9 to i8
store i8 %12, i8* %1
ret void
}
/* Type definitions */
struct in6_prefix {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ in6_prefix_apply(struct in6_prefix *);
int /*<<< orphan*/ in6_prefix_copy(struct in6_prefix *,
                                   struct in6_prefix const *);
struct in6_prefix *in6_prefix_copy_applied(struct in6_prefix *dest,
                                           const struct in6_prefix *src) {
  in6_prefix_copy(dest, src);
  in6_prefix_apply(dest);
  return dest;
}


x86 assembly (clang, -O0):
<in6_prefix_copy_applied>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
mov    -0x10(%rbp),%rsi
call   1040 <in6_prefix_copy@plt>
mov    -0x8(%rbp),%rdi
call   1030 <in6_prefix_apply@plt>
mov    -0x8(%rbp),%rax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<in6_prefix_copy_applied>:
push   %rbx
mov    %rdi,%rbx
call   1040 <in6_prefix_copy@plt>
mov    %rbx,%rdi
call   1030 <in6_prefix_apply@plt>
mov    %rbx,%rax
pop    %rbx
ret

LLVM IR (-O0):
%struct.in6_prefix = type { i32 }
define %struct.in6_prefix* @in6_prefix_copy_applied(%struct.in6_prefix* %0, %struct.in6_prefix* %1) {
%3 = alloca %struct.in6_prefix*
%4 = alloca %struct.in6_prefix*
store %struct.in6_prefix* %0, %struct.in6_prefix** %3
store %struct.in6_prefix* %1, %struct.in6_prefix** %4
%5 = load %struct.in6_prefix*, %struct.in6_prefix** %3
%6 = load %struct.in6_prefix*, %struct.in6_prefix** %4
%7 = call i32 @in6_prefix_copy(%struct.in6_prefix* %5, %struct.in6_prefix* %6)
%8 = load %struct.in6_prefix*, %struct.in6_prefix** %3
%9 = call i32 @in6_prefix_apply(%struct.in6_prefix* %8)
%10 = load %struct.in6_prefix*, %struct.in6_prefix** %3
ret %struct.in6_prefix* %10
}

LLVM IR (-O2):
%struct.in6_prefix = type { i32 }
define %struct.in6_prefix* @in6_prefix_copy_applied(%struct.in6_prefix* returned %0, %struct.in6_prefix* %1) {
%3 = tail call i32 @in6_prefix_copy(%struct.in6_prefix* %0, %struct.in6_prefix* %1)
%4 = tail call i32 @in6_prefix_apply(%struct.in6_prefix* %0)
ret %struct.in6_prefix* %0
}
/* Variables and functions */
int /*<<< orphan*/ WARN_ON(int);
void radix__local_flush_tlb_lpid_guest(unsigned int lpid) { WARN_ON(1); }


x86 assembly (clang, -O0):
<radix__local_flush_tlb_lpid_guest>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
mov    $0x1,%edi
call   1030 <WARN_ON@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<radix__local_flush_tlb_lpid_guest>:
mov    $0x1,%edi
jmp    1030 <WARN_ON@plt>

LLVM IR (-O0):
define void @radix__local_flush_tlb_lpid_guest(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = call i32 @WARN_ON(i32 1)
ret void
}

LLVM IR (-O2):
define void @radix__local_flush_tlb_lpid_guest(i32 %0) {
%2 = tail call i32 @WARN_ON(i32 1)
ret void
}
/* Variables and functions */
int /*<<< orphan*/ MSG_PrioritiseEntitystateFields();
int /*<<< orphan*/ MSG_PrioritisePlayerStateFields();
void SV_FieldInfo_f(void) {
  MSG_PrioritiseEntitystateFields();
  MSG_PrioritisePlayerStateFields();
}


x86 assembly (clang, -O0):
<SV_FieldInfo_f>:
push   %rbp
mov    %rsp,%rbp
mov    $0x0,%al
call   1040 <MSG_PrioritiseEntitystateFields@plt>
mov    $0x0,%al
call   1030 <MSG_PrioritisePlayerStateFields@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<SV_FieldInfo_f>:
push   %rax
xor    %eax,%eax
call   1040 <MSG_PrioritiseEntitystateFields@plt>
xor    %eax,%eax
pop    %rcx
jmp    1030 <MSG_PrioritisePlayerStateFields@plt>

LLVM IR (-O0):
define void @SV_FieldInfo_f() {
%1 = call i32 (...) @MSG_PrioritiseEntitystateFields()
%2 = call i32 (...) @MSG_PrioritisePlayerStateFields()
ret void
}

LLVM IR (-O2):
define void @SV_FieldInfo_f() {
%1 = tail call i32 (...) @MSG_PrioritiseEntitystateFields()
%2 = tail call i32 (...) @MSG_PrioritisePlayerStateFields()
ret void
}
/* Type definitions */
struct kvm_regs {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ KVM_GET_REGS;
int /*<<< orphan*/ exit(int);
int ioctl(int, int /*<<< orphan*/, struct kvm_regs *);
int /*<<< orphan*/ printf(char *);
void getRegs(int vcpufd, struct kvm_regs *regs) {
  int res = ioctl(vcpufd, KVM_GET_REGS, regs);
  if (res != 0) {
    printf("Can't GET_REGS from VCPU\n");
    exit(1);
  }
}


x86 assembly (clang, -O0):
<getRegs>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %edi,-0x4(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x4(%rbp),%edi
mov    0x2eaf(%rip),%rax
mov    (%rax),%esi
mov    -0x10(%rbp),%rdx
call   1040 <ioctl@plt>
mov    %eax,-0x14(%rbp)
cmpl   $0x0,-0x14(%rbp)
je     1177 <getRegs+0x47>
lea    0xe98(%rip),%rdi
call   1030 <printf@plt>
mov    $0x1,%edi
call   1050 <exit@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<getRegs>:
push   %rax
mov    %rsi,%rdx
mov    0x2ebd(%rip),%rax
mov    (%rax),%esi
call   1040 <ioctl@plt>
test   %eax,%eax
jne    1148 <getRegs+0x18>
pop    %rax
ret
lea    0xeb1(%rip),%rdi
call   1030 <puts@plt>
mov    $0x1,%edi
call   1050 <exit@plt>

LLVM IR (-O0):
%struct.kvm_regs = type { i32 }
@KVM_GET_REGS = global i32 0
@.str = [26 x i8] c"Can't GET_REGS from VCPU\0A\00"
define void @getRegs(i32 %0, %struct.kvm_regs* %1) {
%3 = alloca i32
%4 = alloca %struct.kvm_regs*
%5 = alloca i32
store i32 %0, i32* %3
store %struct.kvm_regs* %1, %struct.kvm_regs** %4
%6 = load i32, i32* %3
%7 = load i32, i32* @KVM_GET_REGS
%8 = load %struct.kvm_regs*, %struct.kvm_regs** %4
%9 = call i32 @ioctl(i32 %6, i32 %7, %struct.kvm_regs* %8)
store i32 %9, i32* %5
%10 = load i32, i32* %5
%11 = icmp ne i32 %10, 0
br i1 %11, label %12, label %15
12: ; preds = %2
%13 = call i32 @printf(i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str, i64 0, i64 0))
%14 = call i32 @exit(i32 1)
unreachable
15: ; preds = %2
ret void
}

LLVM IR (-O2):
%struct.kvm_regs = type { i32 }
@KVM_GET_REGS = global i32 0
@str = [25 x i8] c"Can't GET_REGS from VCPU\00"
define void @getRegs(i32 %0, %struct.kvm_regs* %1) {
%3 = load i32, i32* @KVM_GET_REGS
%4 = tail call i32 @ioctl(i32 %0, i32 %3, %struct.kvm_regs* %1)
%5 = icmp eq i32 %4, 0
br i1 %5, label %9, label %6
6: ; preds = %2
%7 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([25 x i8], [25 x i8]* @str, i64 0, i64 0))
%8 = tail call i32 @exit(i32 1)
unreachable
9: ; preds = %2
ret void
}
int parseFloat2(char **token, float *value) {
  float sign = 1;
  switch (**token) {
  case '-':
    sign = -1;
  case '+':
    ++*token;
  }
  switch (**token) {}
}


x86 assembly (clang, -O0):
<parseFloat2>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x10(%rbp)
mov    %rsi,-0x18(%rbp)
movl   $0x3f800000,-0x1c(%rbp)
mov    -0x10(%rbp),%rax
mov    (%rax),%rax
movsbl (%rax),%eax
mov    %eax,-0x20(%rbp)
sub    $0x2b,%eax
je     114c <parseFloat2+0x4c>
jmp    112e <parseFloat2+0x2e>
mov    -0x20(%rbp),%eax
sub    $0x2d,%eax
jne    115a <parseFloat2+0x5a>
jmp    113f <parseFloat2+0x3f>
movss  0xeb9(%rip),%xmm0
movss  %xmm0,-0x1c(%rbp)
mov    -0x10(%rbp),%rax
mov    (%rax),%rcx
add    $0x1,%rcx
mov    %rcx,(%rax)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<parseFloat2>:
mov    (%rdi),%rax
movsbl (%rax),%ecx
cmp    $0x2d,%ecx
je     1110 <parseFloat2+0x10>
cmp    $0x2b,%ecx
jne    1117 <parseFloat2+0x17>
add    $0x1,%rax
mov    %rax,(%rdi)
ret

LLVM IR (-O0):
define i32 @parseFloat2(i8** %0, float* %1) {
%3 = alloca i32
%4 = alloca i8**
%5 = alloca float*
%6 = alloca float
store i8** %0, i8*** %4
store float* %1, float** %5
store float 1.000000e+00, float* %6
%7 = load i8**, i8*** %4
%8 = load i8*, i8** %7
%9 = load i8, i8* %8
%10 = sext i8 %9 to i32
switch i32 %10, label %16 [
i32 45, label %11
i32 43, label %12
]
11: ; preds = %2
store float -1.000000e+00, float* %6
br label %12
12: ; preds = %2, %11
%13 = load i8**, i8*** %4
%14 = load i8*, i8** %13
%15 = getelementptr inbounds i8, i8* %14, i32 1
store i8* %15, i8** %13
br label %16
16: ; preds = %12, %2
%17 = load i8**, i8*** %4
%18 = load i8*, i8** %17
%19 = load i8, i8* %18
%20 = sext i8 %19 to i32
switch i32 %20, label %21 [
]
21: ; preds = %16
%22 = load i32, i32* %3
ret i32 %22
}

LLVM IR (-O2):
define i32 @parseFloat2(i8** nocapture %0, float* nocapture readnone %1) {
%3 = load i8*, i8** %0
%4 = load i8, i8* %3
%5 = sext i8 %4 to i32
switch i32 %5, label %8 [
i32 45, label %6
i32 43, label %6
]
6: ; preds = %2, %2
%7 = getelementptr inbounds i8, i8* %3, i64 1
store i8* %7, i8** %0
br label %8
8: ; preds = %2, %6
ret i32 undef
}
void foo740() {}


x86 assembly (clang, -O0):
<foo740>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<foo740>:
ret

LLVM IR (-O0):
define void @foo740() {
ret void
}

LLVM IR (-O2):
define void @foo740() {
ret void
}
unsigned int UARTModemControlGet(unsigned int baseAdd) {
  return (*((volatile unsigned int *)(baseAdd + (0x10)))) &
         ((0x00000020u) | (0x00000002u));
}


x86 assembly (clang, -O0):
<UARTModemControlGet>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x22,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTModemControlGet>:
add    $0x10,%edi
mov    (%rdi),%eax
and    $0x22,%eax
ret

LLVM IR (-O0):
define i32 @UARTModemControlGet(i32 %0) {
%2 = alloca i32
store i32 %0, i32* %2
%3 = load i32, i32* %2
%4 = add i32 %3, 16
%5 = zext i32 %4 to i64
%6 = inttoptr i64 %5 to i32*
%7 = load volatile i32, i32* %6
%8 = and i32 %7, 34
ret i32 %8
}

LLVM IR (-O2):
define i32 @UARTModemControlGet(i32 %0) {
%2 = add i32 %0, 16
%3 = zext i32 %2 to i64
%4 = inttoptr i64 %3 to i32*
%5 = load volatile i32, i32* %4
%6 = and i32 %5, 34
ret i32 %6
}
/* Variables and functions */
scalar_t__ isspace(int);
char *skipblanks(const char *s) {
  while (isspace((int)*s))
    s++;
  return (char *)s;
}


x86 assembly (clang, -O0):
<skipblanks>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
movsbl (%rax),%edi
call   1030 <isspace@plt>
cmp    $0x0,%rax
je     1143 <skipblanks+0x33>
mov    -0x8(%rbp),%rax
add    $0x1,%rax
mov    %rax,-0x8(%rbp)
jmp    111c <skipblanks+0xc>
mov    -0x8(%rbp),%rax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<skipblanks>:
push   %rbx
mov    %rdi,%rbx
add    $0xffffffffffffffff,%rbx
nopl   0x0(%rax,%rax,1)
movsbl 0x1(%rbx),%edi
add    $0x1,%rbx
call   1030 <isspace@plt>
test   %rax,%rax
jne    1120 <skipblanks+0x10>
mov    %rbx,%rax
pop    %rbx
ret

LLVM IR (-O0):
define i8* @skipblanks(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
br label %3
3: ; preds = %9, %1
%4 = load i8*, i8** %2
%5 = load i8, i8* %4
%6 = sext i8 %5 to i32
%7 = call i64 @isspace(i32 %6)
%8 = icmp ne i64 %7, 0
br i1 %8, label %9, label %12
9: ; preds = %3
%10 = load i8*, i8** %2
%11 = getelementptr inbounds i8, i8* %10, i32 1
store i8* %11, i8** %2
br label %3
12: ; preds = %3
%13 = load i8*, i8** %2
ret i8* %13
}

LLVM IR (-O2):
define i8* @skipblanks(i8* %0) {
br label %2
2: ; preds = %2, %1
%3 = phi i8* [ %0, %1 ], [ %8, %2 ]
%4 = load i8, i8* %3
%5 = sext i8 %4 to i32
%6 = tail call i64 @isspace(i32 %5)
%7 = icmp eq i64 %6, 0
%8 = getelementptr inbounds i8, i8* %3, i64 1
br i1 %7, label %9, label %2
9: ; preds = %2
ret i8* %3
}
/* Variables and functions */
scalar_t__ CLOCKS_PER_SEC;
scalar_t__ clock();
unsigned long get_cputime(void) {
  return (unsigned long)((double)clock() / ((double)CLOCKS_PER_SEC / 1e6));
}


x86 assembly (clang, -O0):
<get_cputime>:
push   %rbp
mov    %rsp,%rbp
xor    %eax,%eax
call   1030 <clock@plt>
cvtsi2sd %rax,%xmm0
mov    0x2ec1(%rip),%rax
cvtsi2sdq (%rax),%xmm1
movsd  0xecc(%rip),%xmm2
divsd  %xmm2,%xmm1
divsd  %xmm1,%xmm0
movaps %xmm0,%xmm1
cvttsd2si %xmm1,%rax
mov    %rax,%rdx
sar    $0x3f,%rdx
movsd  0xeb5(%rip),%xmm1
subsd  %xmm1,%xmm0
cvttsd2si %xmm0,%rcx
and    %rdx,%rcx
or     %rcx,%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<get_cputime>:
push   %rax
xor    %eax,%eax
call   1030 <clock@plt>
cvtsi2sd %rax,%xmm0
mov    0x2ec4(%rip),%rax
cvtsi2sdq (%rax),%xmm1
divsd  0xecf(%rip),%xmm1
divsd  %xmm1,%xmm0
cvttsd2si %xmm0,%rcx
mov    %rcx,%rdx
sar    $0x3f,%rdx
subsd  0xebf(%rip),%xmm0
cvttsd2si %xmm0,%rax
and    %rdx,%rax
or     %rcx,%rax
pop    %rcx
ret

LLVM IR (-O0):
@CLOCKS_PER_SEC = global i64 0
define i64 @get_cputime() {
%1 = call i64 (...) @clock()
%2 = sitofp i64 %1 to double
%3 = load i64, i64* @CLOCKS_PER_SEC
%4 = sitofp i64 %3 to double
%5 = fdiv double %4, 1.000000e+06
%6 = fdiv double %2, %5
%7 = fptoui double %6 to i64
ret i64 %7
}

LLVM IR (-O2):
@CLOCKS_PER_SEC = global i64 0
define i64 @get_cputime() {
%1 = tail call i64 (...) @clock()
%2 = sitofp i64 %1 to double
%3 = load i64, i64* @CLOCKS_PER_SEC
%4 = sitofp i64 %3 to double
%5 = fdiv double %4, 1.000000e+06
%6 = fdiv double %2, %5
%7 = fptoui double %6 to i64
ret i64 %7
}
/* Type definitions */
struct aiocb {
  int dummy;
};

/* Variables and functions */
int /*<<< orphan*/ EINVAL;
int /*<<< orphan*/ ENOSYS;
int O_DSYNC;
int O_SYNC;
int /*<<< orphan*/ __set_errno(int /*<<< orphan*/);
int aio_fsync(int op, struct aiocb *aiocbp) {
  if (op != O_SYNC && op != O_DSYNC) {
    __set_errno(EINVAL);
    return -1;
  }
  __set_errno(ENOSYS);
  return -1;
}


x86 assembly (clang, -O0):
<aio_fsync>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    0x2ebf(%rip),%rcx
cmp    (%rcx),%eax
je     115d <aio_fsync+0x4d>
mov    -0x8(%rbp),%eax
mov    0x2e95(%rip),%rcx
cmp    (%rcx),%eax
je     115d <aio_fsync+0x4d>
mov    0x2e7e(%rip),%rax
mov    (%rax),%edi
call   1030 <__set_errno@plt>
movl   $0xffffffff,-0x4(%rbp)
jmp    1172 <aio_fsync+0x62>
mov    0x2e7c(%rip),%rax
mov    (%rax),%edi
call   1030 <__set_errno@plt>
movl   $0xffffffff,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<aio_fsync>:
push   %rax
mov    0x2ed0(%rip),%rax
mov    (%rax),%eax
mov    0x2eaf(%rip),%rsi
mov    0x2eb8(%rip),%rcx
mov    %rcx,%rdx
cmp    %edi,(%rsi)
je     1136 <aio_fsync+0x26>
mov    0x2e92(%rip),%rdx
cmp    %edi,%eax
cmove  %rcx,%rdx
mov    (%rdx),%edi
call   1030 <__set_errno@plt>
mov    $0xffffffff,%eax
pop    %rcx
ret

LLVM IR (-O0):
%struct.aiocb = type { i32 }
@O_SYNC = global i32 0
@O_DSYNC = global i32 0
@EINVAL = global i32 0
@ENOSYS = global i32 0
define i32 @aio_fsync(i32 %0, %struct.aiocb* %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca %struct.aiocb*
store i32 %0, i32* %4
store %struct.aiocb* %1, %struct.aiocb** %5
%6 = load i32, i32* %4
%7 = load i32, i32* @O_SYNC
%8 = icmp ne i32 %6, %7
br i1 %8, label %9, label %16
9: ; preds = %2
%10 = load i32, i32* %4
%11 = load i32, i32* @O_DSYNC
%12 = icmp ne i32 %10, %11
br i1 %12, label %13, label %16
13: ; preds = %9
%14 = load i32, i32* @EINVAL
%15 = call i32 @__set_errno(i32 %14)
store i32 -1, i32* %3
br label %19
16: ; preds = %9, %2
%17 = load i32, i32* @ENOSYS
%18 = call i32 @__set_errno(i32 %17)
store i32 -1, i32* %3
br label %19
19: ; preds = %16, %13
%20 = load i32, i32* %3
ret i32 %20
}

LLVM IR (-O2):
%struct.aiocb = type { i32 }
@O_SYNC = global i32 0
@O_DSYNC = global i32 0
@EINVAL = global i32 0
@ENOSYS = global i32 0
define i32 @aio_fsync(i32 %0, %struct.aiocb* nocapture readnone %1) {
%3 = load i32, i32* @O_SYNC
%4 = icmp eq i32 %3, %0
%5 = load i32, i32* @O_DSYNC
%6 = icmp eq i32 %5, %0
%7 = select i1 %4, i1 true, i1 %6
%8 = load i32, i32* @ENOSYS
%9 = load i32, i32* @EINVAL
%10 = select i1 %7, i32 %8, i32 %9
%11 = tail call i32 @__set_errno(i32 %10)
ret i32 -1
}
const char *unqlite_lib_copyright(void) {
  return "Copyright (C) Symisc Systems, S.U.A.R.L [Mrad Chems Eddine "
         "<chm@symisc.net>] 2016, http://unqlite.org/";
}


x86 assembly (clang, -O0):
<unqlite_lib_copyright>:
push   %rbp
mov    %rsp,%rbp
lea    0xef5(%rip),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<unqlite_lib_copyright>:
lea    0xef9(%rip),%rax
ret

LLVM IR (-O0):
@.str = [103 x i8] c"Copyright (C) Symisc Systems, S.U.A.R.L [Mrad Chems Eddine <chm@symisc.net>] 2016, http://unqlite.org/\00"
define i8* @unqlite_lib_copyright() {
ret i8* getelementptr inbounds ([103 x i8], [103 x i8]* @.str, i64 0, i64 0)
}

LLVM IR (-O2):
@.str = [103 x i8] c"Copyright (C) Symisc Systems, S.U.A.R.L [Mrad Chems Eddine <chm@symisc.net>] 2016, http://unqlite.org/\00"
define i8* @unqlite_lib_copyright() {
ret i8* getelementptr inbounds ([103 x i8], [103 x i8]* @.str, i64 0, i64 0)
}
void UARTEnable(unsigned long ulBase, unsigned long ulBlock) {
  ;
  ;
  (*((volatile unsigned long *)(ulBase + 0x0000000C))) |=
      ulBlock & (0x00002000 | 0x00000008 | 0x00000004);
}


x86 assembly (clang, -O0):
<UARTEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    -0x10(%rbp),%rdx
and    $0x200c,%rdx
mov    -0x8(%rbp),%rax
mov    0xc(%rax),%rcx
or     %rdx,%rcx
mov    %rcx,0xc(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTEnable>:
and    $0x200c,%esi
or     %rsi,0xc(%rdi)
ret

LLVM IR (-O0):
define void @UARTEnable(i64 %0, i64 %1) {
%3 = alloca i64
%4 = alloca i64
store i64 %0, i64* %3
store i64 %1, i64* %4
%5 = load i64, i64* %4
%6 = and i64 %5, 8204
%7 = load i64, i64* %3
%8 = add i64 %7, 12
%9 = inttoptr i64 %8 to i64*
%10 = load volatile i64, i64* %9
%11 = or i64 %10, %6
store volatile i64 %11, i64* %9
ret void
}

LLVM IR (-O2):
define void @UARTEnable(i64 %0, i64 %1) {
%3 = and i64 %1, 8204
%4 = add i64 %0, 12
%5 = inttoptr i64 %4 to i64*
%6 = load volatile i64, i64* %5
%7 = or i64 %6, %3
store volatile i64 %7, i64* %5
ret void
}
char compbase(char x) {
  if (x == 'A')
    return 'T';
  if (x == 'C')
    return 'G';
  if (x == 'G')
    return 'C';
  if (x == 'T')
    return 'A';
  return x;
}


x86 assembly (clang, -O0):
<compbase>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x2(%rbp)
movsbl -0x2(%rbp),%eax
cmp    $0x41,%eax
jne    1120 <compbase+0x20>
movb   $0x54,-0x1(%rbp)
jmp    1168 <compbase+0x68>
movsbl -0x2(%rbp),%eax
cmp    $0x43,%eax
jne    1136 <compbase+0x36>
movb   $0x47,-0x1(%rbp)
jmp    1168 <compbase+0x68>
movsbl -0x2(%rbp),%eax
cmp    $0x47,%eax
jne    114c <compbase+0x4c>
movb   $0x43,-0x1(%rbp)
jmp    1168 <compbase+0x68>
movsbl -0x2(%rbp),%eax
cmp    $0x54,%eax
jne    1162 <compbase+0x62>
movb   $0x41,-0x1(%rbp)
jmp    1168 <compbase+0x68>
mov    -0x2(%rbp),%al
mov    %al,-0x1(%rbp)
movsbl -0x1(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<compbase>:
lea    -0x41(%rdi),%ecx
cmp    $0x13,%cl
ja     1120 <compbase+0x20>
mov    $0x54,%al
movzbl %cl,%ecx
lea    0xeec(%rip),%rdx
movslq (%rdx,%rcx,4),%rcx
add    %rdx,%rcx
jmp    *%rcx
mov    $0x47,%al
ret
mov    %edi,%eax
ret
mov    $0x43,%al
ret
mov    $0x41,%al
ret

LLVM IR (-O0):
define signext i8 @compbase(i8 signext %0) {
%2 = alloca i8
%3 = alloca i8
store i8 %0, i8* %3
%4 = load i8, i8* %3
%5 = sext i8 %4 to i32
%6 = icmp eq i32 %5, 65
br i1 %6, label %7, label %8
7: ; preds = %1
store i8 84, i8* %2
br label %25
8: ; preds = %1
%9 = load i8, i8* %3
%10 = sext i8 %9 to i32
%11 = icmp eq i32 %10, 67
br i1 %11, label %12, label %13
12: ; preds = %8
store i8 71, i8* %2
br label %25
13: ; preds = %8
%14 = load i8, i8* %3
%15 = sext i8 %14 to i32
%16 = icmp eq i32 %15, 71
br i1 %16, label %17, label %18
17: ; preds = %13
store i8 67, i8* %2
br label %25
18: ; preds = %13
%19 = load i8, i8* %3
%20 = sext i8 %19 to i32
%21 = icmp eq i32 %20, 84
br i1 %21, label %22, label %23
22: ; preds = %18
store i8 65, i8* %2
br label %25
23: ; preds = %18
%24 = load i8, i8* %3
store i8 %24, i8* %2
br label %25
25: ; preds = %23, %22, %17, %12, %7
%26 = load i8, i8* %2
ret i8 %26
}

LLVM IR (-O2):
define signext i8 @compbase(i8 signext %0) {
switch i8 %0, label %5 [
i8 65, label %6
i8 67, label %2
i8 71, label %3
i8 84, label %4
]
2: ; preds = %1
br label %6
3: ; preds = %1
br label %6
4: ; preds = %1
br label %6
5: ; preds = %1
br label %6
6: ; preds = %1, %5, %4, %3, %2
%7 = phi i8 [ 71, %2 ], [ 67, %3 ], [ 65, %4 ], [ %0, %5 ], [ 84, %1 ]
ret i8 %7
}
/* Variables and functions */
char *flu_n_escape(char const *, int /*<<< orphan*/);
int /*<<< orphan*/ strlen(char const *);
char *flu_escape(const char *s) { return flu_n_escape(s, strlen(s)); }


x86 assembly (clang, -O0):
<flu_escape>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    %rax,-0x10(%rbp)
mov    -0x8(%rbp),%rdi
call   1040 <strlen@plt>
mov    -0x10(%rbp),%rdi
mov    %eax,%esi
call   1030 <flu_n_escape@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<flu_escape>:
push   %rbx
mov    %rdi,%rbx
call   1040 <strlen@plt>
mov    %rbx,%rdi
mov    %eax,%esi
pop    %rbx
jmp    1030 <flu_n_escape@plt>

LLVM IR (-O0):
define i8* @flu_escape(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = load i8*, i8** %2
%5 = call i32 @strlen(i8* %4)
%6 = call i8* @flu_n_escape(i8* %3, i32 %5)
ret i8* %6
}

LLVM IR (-O2):
define i8* @flu_escape(i8* %0) {
%2 = tail call i32 @strlen(i8* %0)
%3 = tail call i8* @flu_n_escape(i8* %0, i32 %2)
ret i8* %3
}
int min_zero(int a, int b) {
  if (a < 0) {
    if (b < 0) {
      return 0;
    }
    return b;
  } else {
    if (b < 0) {
      return a;
    }
    if (b > a) {
      return a;
    }
    return b;
  }
}


x86 assembly (clang, -O0):
<min_zero>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
cmpl   $0x0,-0x8(%rbp)
jge    1135 <min_zero+0x35>
cmpl   $0x0,-0xc(%rbp)
jge    112a <min_zero+0x2a>
movl   $0x0,-0x4(%rbp)
jmp    1167 <min_zero+0x67>
mov    -0xc(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    1167 <min_zero+0x67>
cmpl   $0x0,-0xc(%rbp)
jge    114a <min_zero+0x4a>
mov    -0x8(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    1167 <min_zero+0x67>
mov    -0xc(%rbp),%eax
cmp    -0x8(%rbp),%eax
jle    1161 <min_zero+0x61>
mov    -0x8(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    1167 <min_zero+0x67>
mov    -0xc(%rbp),%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<min_zero>:
test   %edi,%edi
js     1110 <min_zero+0x10>
mov    %edi,%eax
test   %esi,%esi
js     110f <min_zero+0xf>
cmp    %eax,%esi
cmovbe %esi,%eax
ret
xor    %eax,%eax
test   %esi,%esi
cmovns %esi,%eax
ret

LLVM IR (-O0):
define i32 @min_zero(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
%6 = load i32, i32* %4
%7 = icmp slt i32 %6, 0
br i1 %7, label %8, label %14
8: ; preds = %2
%9 = load i32, i32* %5
%10 = icmp slt i32 %9, 0
br i1 %10, label %11, label %12
11: ; preds = %8
store i32 0, i32* %3
br label %27
12: ; preds = %8
%13 = load i32, i32* %5
store i32 %13, i32* %3
br label %27
14: ; preds = %2
%15 = load i32, i32* %5
%16 = icmp slt i32 %15, 0
br i1 %16, label %17, label %19
17: ; preds = %14
%18 = load i32, i32* %4
store i32 %18, i32* %3
br label %27
19: ; preds = %14
%20 = load i32, i32* %5
%21 = load i32, i32* %4
%22 = icmp sgt i32 %20, %21
br i1 %22, label %23, label %25
23: ; preds = %19
%24 = load i32, i32* %4
store i32 %24, i32* %3
br label %27
25: ; preds = %19
%26 = load i32, i32* %5
store i32 %26, i32* %3
br label %27
27: ; preds = %25, %23, %17, %12, %11
%28 = load i32, i32* %3
ret i32 %28
}

LLVM IR (-O2):
define i32 @min_zero(i32 %0, i32 %1) {
%3 = icmp slt i32 %0, 0
br i1 %3, label %4, label %7
4: ; preds = %2
%5 = icmp sgt i32 %1, 0
%6 = select i1 %5, i32 %1, i32 0
br label %12
7: ; preds = %2
%8 = icmp slt i32 %1, 0
br i1 %8, label %12, label %9
9: ; preds = %7
%10 = icmp ugt i32 %1, %0
%11 = select i1 %10, i32 %0, i32 %1
br label %12
12: ; preds = %9, %7, %4
%13 = phi i32 [ %6, %4 ], [ %0, %7 ], [ %11, %9 ]
ret i32 %13
}
int recon_get_card_detect2(void) { return 0; }


x86 assembly (clang, -O0):
<recon_get_card_detect2>:
push   %rbp
mov    %rsp,%rbp
xor    %eax,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<recon_get_card_detect2>:
xor    %eax,%eax
ret

LLVM IR (-O0):
define i32 @recon_get_card_detect2() {
ret i32 0
}

LLVM IR (-O2):
define i32 @recon_get_card_detect2() {
ret i32 0
}
/* Forward declarations */
typedef struct TYPE_4__ TYPE_2__;
typedef struct TYPE_3__ TYPE_1__;

/* Type definitions */
struct TYPE_3__ {
  scalar_t__ serial;
};
struct TYPE_4__ {
  TYPE_1__ xdestroywindow;
};
typedef TYPE_2__ XEvent;

/* Variables and functions */
unsigned long get_XEvent_xdestroywindow_serial(void *_p) {
  return (unsigned long)((XEvent *)_p)->xdestroywindow.serial;
}


x86 assembly (clang, -O0):
<get_XEvent_xdestroywindow_serial>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    (%rax),%rax
pop    %rbp
ret

x86 assembly (clang, -O2):
<get_XEvent_xdestroywindow_serial>:
mov    (%rdi),%rax
ret

LLVM IR (-O0):
%struct.TYPE_4__ = type { %struct.TYPE_3__ }
%struct.TYPE_3__ = type { i64 }
define i64 @get_XEvent_xdestroywindow_serial(i8* %0) {
%2 = alloca i8*
store i8* %0, i8** %2
%3 = load i8*, i8** %2
%4 = bitcast i8* %3 to %struct.TYPE_4__*
%5 = getelementptr inbounds %struct.TYPE_4__, %struct.TYPE_4__* %4, i32 0, i32 0
%6 = getelementptr inbounds %struct.TYPE_3__, %struct.TYPE_3__* %5, i32 0, i32 0
%7 = load i64, i64* %6
ret i64 %7
}

LLVM IR (-O2):
define i64 @get_XEvent_xdestroywindow_serial(i8* nocapture %0) {
%2 = bitcast i8* %0 to i64*
%3 = load i64, i64* %2
ret i64 %3
}
/* Variables and functions */
int /*<<< orphan*/ sin(float);
float sqrt(int /*<<< orphan*/);
float f(float y) { return sqrt(sin(y)); }


x86 assembly (clang, -O0):
<f>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
movss  %xmm0,-0x4(%rbp)
movss  -0x4(%rbp),%xmm0
call   1030 <sin@plt>
mov    %eax,%edi
call   1040 <sqrt@plt>
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<f>:
push   %rax
call   1030 <sin@plt>
mov    %eax,%edi
pop    %rax
jmp    1040 <sqrt@plt>

LLVM IR (-O0):
define float @f(float %0) {
%2 = alloca float
store float %0, float* %2
%3 = load float, float* %2
%4 = call i32 @sin(float %3)
%5 = call float @sqrt(i32 %4)
ret float %5
}

LLVM IR (-O2):
define float @f(float %0) {
%2 = tail call i32 @sin(float %0)
%3 = tail call float @sqrt(i32 %2)
ret float %3
}
void ADCTemperatureRefVolEnable(unsigned long ulBase) {
  ;
  (*((volatile unsigned long *)(ulBase + 0x00000008))) |= 0x00800000;
}


x86 assembly (clang, -O0):
<ADCTemperatureRefVolEnable>:
push   %rbp
mov    %rsp,%rbp
mov    %rdi,-0x8(%rbp)
mov    -0x8(%rbp),%rax
mov    0x8(%rax),%rcx
or     $0x800000,%rcx
mov    %rcx,0x8(%rax)
pop    %rbp
ret

x86 assembly (clang, -O2):
<ADCTemperatureRefVolEnable>:
orq    $0x800000,0x8(%rdi)
ret

LLVM IR (-O0):
define void @ADCTemperatureRefVolEnable(i64 %0) {
%2 = alloca i64
store i64 %0, i64* %2
%3 = load i64, i64* %2
%4 = add i64 %3, 8
%5 = inttoptr i64 %4 to i64*
%6 = load volatile i64, i64* %5
%7 = or i64 %6, 8388608
store volatile i64 %7, i64* %5
ret void
}

LLVM IR (-O2):
define void @ADCTemperatureRefVolEnable(i64 %0) {
%2 = add i64 %0, 8
%3 = inttoptr i64 %2 to i64*
%4 = load volatile i64, i64* %3
%5 = or i64 %4, 8388608
store volatile i64 %5, i64* %3
ret void
}
int test_imm_B4int8_reg(signed char val) {
  return ((val) & (-0xB4 << 0)) ? -20 : -40;
}


x86 assembly (clang, -O0):
<test_imm_B4int8_reg>:
push   %rbp
mov    %rsp,%rbp
mov    %dil,%al
mov    %al,-0x1(%rbp)
movsbl -0x1(%rbp),%edx
and    $0xffffff4c,%edx
mov    $0xffffffd8,%eax
mov    $0xffffffec,%ecx
cmp    $0x0,%edx
cmovne %ecx,%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<test_imm_B4int8_reg>:
test   $0xffffff4c,%edi
mov    $0xffffffd8,%ecx
mov    $0xffffffec,%eax
cmove  %ecx,%eax
ret

LLVM IR (-O0):
define i32 @test_imm_B4int8_reg(i8 signext %0) {
%2 = alloca i8
store i8 %0, i8* %2
%3 = load i8, i8* %2
%4 = sext i8 %3 to i32
%5 = and i32 %4, -180
%6 = icmp ne i32 %5, 0
%7 = zext i1 %6 to i64
%8 = select i1 %6, i32 -20, i32 -40
ret i32 %8
}

LLVM IR (-O2):
define i32 @test_imm_B4int8_reg(i8 signext %0) {
%2 = sext i8 %0 to i32
%3 = and i32 %2, -180
%4 = icmp eq i32 %3, 0
%5 = select i1 %4, i32 -40, i32 -20
ret i32 %5
}
/* Variables and functions */
int /*<<< orphan*/ Assert_real(int /*<<< orphan*/, char *, int, char *);
int /*<<< orphan*/ isalpha(int);
void t_isalpha_0x70() {
  Assert_real((isalpha(112)),
              "/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/"
              "2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/"
              "dg/z88dk/test/suites/ctype/test_isalpha.c",
              565, ("isalpha should be 1 for p"));
}


x86 assembly (clang, -O0):
<t_isalpha_0x70>:
push   %rbp
mov    %rsp,%rbp
mov    $0x70,%edi
call   1030 <isalpha@plt>
mov    %eax,%edi
lea    0xec9(%rip),%rsi
mov    $0x235,%edx
lea    0xf65(%rip),%rcx
call   1040 <Assert_real@plt>
pop    %rbp
ret

x86 assembly (clang, -O2):
<t_isalpha_0x70>:
push   %rax
mov    $0x70,%edi
call   1030 <isalpha@plt>
lea    0xece(%rip),%rsi
lea    0xf6f(%rip),%rcx
mov    %eax,%edi
mov    $0x235,%edx
pop    %rax
jmp    1040 <Assert_real@plt>

LLVM IR (-O0):
@.str = [168 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/dg/z88dk/test/suites/ctype/test_isalpha.c\00"
@.str.1 = [26 x i8] c"isalpha should be 1 for p\00"
define void @t_isalpha_0x70() {
%1 = call i32 @isalpha(i32 112)
%2 = call i32 @Assert_real(i32 %1, i8* getelementptr inbounds ([168 x i8], [168 x i8]* @.str, i64 0, i64 0), i32 565, i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str.1, i64 0, i64 0))
ret void
}

LLVM IR (-O2):
@.str = [168 x i8] c"/scratch/repos/new/home/jordi_armengol_estape/c-scraper/outputs/2022-01-22/02-19-57/repos/bitfixer/bitfixer/refs/heads/master/dg/z88dk/test/suites/ctype/test_isalpha.c\00"
@.str.1 = [26 x i8] c"isalpha should be 1 for p\00"
define void @t_isalpha_0x70() {
%1 = tail call i32 @isalpha(i32 112)
%2 = tail call i32 @Assert_real(i32 %1, i8* getelementptr inbounds ([168 x i8], [168 x i8]* @.str, i64 0, i64 0), i32 565, i8* getelementptr inbounds ([26 x i8], [26 x i8]* @.str.1, i64 0, i64 0))
ret void
}
void gdk_drawable_get_visual() {}


x86 assembly (clang, -O0):
<gdk_drawable_get_visual>:
push   %rbp
mov    %rsp,%rbp
pop    %rbp
ret

x86 assembly (clang, -O2):
<gdk_drawable_get_visual>:
ret

LLVM IR (-O0):
define void @gdk_drawable_get_visual() {
ret void
}

LLVM IR (-O2):
define void @gdk_drawable_get_visual() {
ret void
}
/* Variables and functions */
int /*<<< orphan*/ printf(char *);
int printtail() { printf("\n</table>\n</section>\n"); }


x86 assembly (clang, -O0):
<printtail>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
lea    0xee1(%rip),%rdi
call   1030 <printf@plt>
mov    -0x4(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<printtail>:
lea    0xee9(%rip),%rdi
jmp    1030 <puts@plt>

LLVM IR (-O0):
@.str = [22 x i8] c"\0A</table>\0A</section>\0A\00"
define i32 @printtail() {
%1 = alloca i32
%2 = call i32 @printf(i8* getelementptr inbounds ([22 x i8], [22 x i8]* @.str, i64 0, i64 0))
%3 = load i32, i32* %1
ret i32 %3
}

LLVM IR (-O2):
@str = [21 x i8] c"\0A</table>\0A</section>\00"
define i32 @printtail() {
%1 = tail call i32 @puts(i8* dereferenceable(1) getelementptr inbounds ([21 x i8], [21 x i8]* @str, i64 0, i64 0))
ret i32 undef
}