int HSMMCSDBusPower(unsigned int baseAddr, unsigned int pwr) {
  volatile unsigned int timeout = 0xFFFFF;
  (*((volatile unsigned int *)(baseAddr + (0x228)))) =
      ((*((volatile unsigned int *)(baseAddr + (0x228)))) & ~(0x00000100u)) |
      pwr;
  if (pwr == ((0x1u) << (0x00000008u))) {
    do {
      if (((*((volatile unsigned int *)(baseAddr + (0x228)))) &
           (0x00000100u)) != 0) {
        break;
      }
    } while (timeout--);
  }
  if (timeout == 0) {
    return -1;
  } else {
    return 0;
  }
}


x86 assembly (clang, -O0):
<HSMMCSDBusPower>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x8(%rbp)
mov    %esi,-0xc(%rbp)
movl   $0xfffff,-0x10(%rbp)
mov    -0x8(%rbp),%eax
add    $0x228,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xfffffeff,%ecx
or     -0xc(%rbp),%ecx
mov    -0x8(%rbp),%eax
add    $0x228,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
cmpl   $0x100,-0xc(%rbp)
jne    1181 <HSMMCSDBusPower+0x81>
jmp    1144 <HSMMCSDBusPower+0x44>
mov    -0x8(%rbp),%eax
add    $0x228,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x100,%eax
cmp    $0x0,%eax
je     1163 <HSMMCSDBusPower+0x63>
jmp    117c <HSMMCSDBusPower+0x7c>
jmp    1168 <HSMMCSDBusPower+0x68>
mov    -0x10(%rbp),%eax
mov    %eax,%ecx
add    $0xffffffff,%ecx
mov    %ecx,-0x10(%rbp)
cmp    $0x0,%eax
jne    1144 <HSMMCSDBusPower+0x44>
jmp    1181 <HSMMCSDBusPower+0x81>
mov    -0x10(%rbp),%eax
cmp    $0x0,%eax
jne    1199 <HSMMCSDBusPower+0x99>
movl   $0xffffffff,-0x4(%rbp)
jmp    11a0 <HSMMCSDBusPower+0xa0>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<HSMMCSDBusPower>:
movl   $0xfffff,-0x4(%rsp)
add    $0x228,%edi
mov    $0xfffffeff,%eax
and    (%rdi),%eax
or     %esi,%eax
mov    %eax,(%rdi)
cmp    $0x100,%esi
jne    113f <HSMMCSDBusPower+0x3f>
cs nopw 0x0(%rax,%rax,1)
nopl   0x0(%rax,%rax,1)
testl  $0x100,(%rdi)
jne    113f <HSMMCSDBusPower+0x3f>
subl   $0x1,-0x4(%rsp)
jae    1130 <HSMMCSDBusPower+0x30>
mov    -0x4(%rsp),%eax
cmp    $0x1,%eax
sbb    %eax,%eax
ret

LLVM IR (-O0):
define i32 @HSMMCSDBusPower(i32 %0, i32 %1) {
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i32
store i32 %0, i32* %4
store i32 %1, i32* %5
store volatile i32 1048575, i32* %6
%7 = load i32, i32* %4
%8 = add i32 %7, 552
%9 = zext i32 %8 to i64
%10 = inttoptr i64 %9 to i32*
%11 = load volatile i32, i32* %10
%12 = and i32 %11, -257
%13 = load i32, i32* %5
%14 = or i32 %12, %13
%15 = load i32, i32* %4
%16 = add i32 %15, 552
%17 = zext i32 %16 to i64
%18 = inttoptr i64 %17 to i32*
store volatile i32 %14, i32* %18
%19 = load i32, i32* %5
%20 = icmp eq i32 %19, 256
br i1 %20, label %21, label %37
21: ; preds = %2
br label %22
22: ; preds = %32, %21
%23 = load i32, i32* %4
%24 = add i32 %23, 552
%25 = zext i32 %24 to i64
%26 = inttoptr i64 %25 to i32*
%27 = load volatile i32, i32* %26
%28 = and i32 %27, 256
%29 = icmp ne i32 %28, 0
br i1 %29, label %30, label %31
30: ; preds = %22
br label %36
31: ; preds = %22
br label %32
32: ; preds = %31
%33 = load volatile i32, i32* %6
%34 = add i32 %33, -1
store volatile i32 %34, i32* %6
%35 = icmp ne i32 %33, 0
br i1 %35, label %22, label %36
36: ; preds = %32, %30
br label %37
37: ; preds = %36, %2
%38 = load volatile i32, i32* %6
%39 = icmp eq i32 %38, 0
br i1 %39, label %40, label %41
40: ; preds = %37
store i32 -1, i32* %3
br label %42
41: ; preds = %37
store i32 0, i32* %3
br label %42
42: ; preds = %41, %40
%43 = load i32, i32* %3
ret i32 %43
}

LLVM IR (-O2):
define i32 @HSMMCSDBusPower(i32 %0, i32 %1) {
%3 = alloca i32
%4 = bitcast i32* %3 to i8*
store volatile i32 1048575, i32* %3
%5 = add i32 %0, 552
%6 = zext i32 %5 to i64
%7 = inttoptr i64 %6 to i32*
%8 = load volatile i32, i32* %7
%9 = and i32 %8, -257
%10 = or i32 %9, %1
store volatile i32 %10, i32* %7
%11 = icmp eq i32 %1, 256
br i1 %11, label %12, label %20
12: ; preds = %2, %16
%13 = load volatile i32, i32* %7
%14 = and i32 %13, 256
%15 = icmp eq i32 %14, 0
br i1 %15, label %16, label %20
16: ; preds = %12
%17 = load volatile i32, i32* %3
%18 = add i32 %17, -1
store volatile i32 %18, i32* %3
%19 = icmp eq i32 %17, 0
br i1 %19, label %20, label %12
20: ; preds = %16, %12, %2
%21 = load volatile i32, i32* %3
%22 = icmp eq i32 %21, 0
%23 = sext i1 %22 to i32
ret i32 %23
}