#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
unsigned int UARTRegConfigModeEnable(unsigned int, int);
unsigned int UARTSubConfigMSRSPRModeEn(unsigned int baseAdd) {
  unsigned int enhanFnBitVal = 0;
  unsigned int tcrTlrValue = 0;
  unsigned int lcrRegValue = 0;
  lcrRegValue = UARTRegConfigModeEnable(baseAdd, (0x00BF));
  enhanFnBitVal =
      (*((volatile unsigned int *)(baseAdd + (0x8)))) & (0x00000010u);
  (*((volatile unsigned int *)(baseAdd + (0x8)))) |= (0x00000010u);
  UARTRegConfigModeEnable(baseAdd, (0x0080));
  tcrTlrValue =
      ((*((volatile unsigned int *)(baseAdd + (0x10)))) & (0x00000040u));
  (*((volatile unsigned int *)(baseAdd + (0x10)))) &= ~((0x00000040u));
  UARTRegConfigModeEnable(baseAdd, (0x00BF));
  (*((volatile unsigned int *)(baseAdd + (0x8)))) &= ~((0x00000010u));
  (*((volatile unsigned int *)(baseAdd + (0x8)))) |= enhanFnBitVal;
  (*((volatile unsigned int *)(baseAdd + (0xC)))) = lcrRegValue;
  return tcrTlrValue;
}


x86 assembly (clang, -O0):
<UARTSubConfigMSRSPRModeEn>:
push   %rbp
mov    %rsp,%rbp
sub    $0x10,%rsp
mov    %edi,-0x4(%rbp)
movl   $0x0,-0x8(%rbp)
movl   $0x0,-0xc(%rbp)
movl   $0x0,-0x10(%rbp)
mov    -0x4(%rbp),%edi
mov    $0xbf,%esi
call   1030 <UARTRegConfigModeEnable@plt>
mov    %eax,-0x10(%rbp)
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x10,%eax
mov    %eax,-0x8(%rbp)
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     $0x10,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    $0x80,%esi
call   1030 <UARTRegConfigModeEnable@plt>
mov    -0x4(%rbp),%eax
add    $0x10,%eax
mov    %eax,%eax
mov    (%rax),%eax
and    $0x40,%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
add    $0x10,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xffffffbf,%ecx
mov    %ecx,(%rax)
mov    -0x4(%rbp),%edi
mov    $0xbf,%esi
call   1030 <UARTRegConfigModeEnable@plt>
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
and    $0xffffffef,%ecx
mov    %ecx,(%rax)
mov    -0x8(%rbp),%edx
mov    -0x4(%rbp),%eax
add    $0x8,%eax
mov    %eax,%eax
mov    (%rax),%ecx
or     %edx,%ecx
mov    %ecx,(%rax)
mov    -0x10(%rbp),%ecx
mov    -0x4(%rbp),%eax
add    $0xc,%eax
mov    %eax,%eax
mov    %ecx,(%rax)
mov    -0xc(%rbp),%eax
add    $0x10,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<UARTSubConfigMSRSPRModeEn>:
push   %rbp
push   %r15
push   %r14
push   %r12
push   %rbx
mov    %edi,%ebx
mov    $0xbf,%esi
call   1030 <UARTRegConfigModeEnable@plt>
mov    %eax,%r14d
lea    0x8(%rbx),%r15d
mov    (%r15),%r12d
and    $0x10,%r12d
orl    $0x10,(%r15)
mov    %ebx,%edi
mov    $0x80,%esi
call   1030 <UARTRegConfigModeEnable@plt>
lea    0x10(%rbx),%eax
mov    (%rax),%ebp
and    $0x40,%ebp
andl   $0xffffffbf,(%rax)
mov    %ebx,%edi
mov    $0xbf,%esi
call   1030 <UARTRegConfigModeEnable@plt>
andl   $0xffffffef,(%r15)
or     %r12d,(%r15)
add    $0xc,%ebx
mov    %r14d,(%rbx)
mov    %ebp,%eax
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define i32 @UARTSubConfigMSRSPRModeEn(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
store i32 %0, i32* %2
store i32 0, i32* %3
store i32 0, i32* %4
store i32 0, i32* %5
%6 = load i32, i32* %2
%7 = call i32 @UARTRegConfigModeEnable(i32 %6, i32 191)
store i32 %7, i32* %5
%8 = load i32, i32* %2
%9 = add i32 %8, 8
%10 = zext i32 %9 to i64
%11 = inttoptr i64 %10 to i32*
%12 = load volatile i32, i32* %11
%13 = and i32 %12, 16
store i32 %13, i32* %3
%14 = load i32, i32* %2
%15 = add i32 %14, 8
%16 = zext i32 %15 to i64
%17 = inttoptr i64 %16 to i32*
%18 = load volatile i32, i32* %17
%19 = or i32 %18, 16
store volatile i32 %19, i32* %17
%20 = load i32, i32* %2
%21 = call i32 @UARTRegConfigModeEnable(i32 %20, i32 128)
%22 = load i32, i32* %2
%23 = add i32 %22, 16
%24 = zext i32 %23 to i64
%25 = inttoptr i64 %24 to i32*
%26 = load volatile i32, i32* %25
%27 = and i32 %26, 64
store i32 %27, i32* %4
%28 = load i32, i32* %2
%29 = add i32 %28, 16
%30 = zext i32 %29 to i64
%31 = inttoptr i64 %30 to i32*
%32 = load volatile i32, i32* %31
%33 = and i32 %32, -65
store volatile i32 %33, i32* %31
%34 = load i32, i32* %2
%35 = call i32 @UARTRegConfigModeEnable(i32 %34, i32 191)
%36 = load i32, i32* %2
%37 = add i32 %36, 8
%38 = zext i32 %37 to i64
%39 = inttoptr i64 %38 to i32*
%40 = load volatile i32, i32* %39
%41 = and i32 %40, -17
store volatile i32 %41, i32* %39
%42 = load i32, i32* %3
%43 = load i32, i32* %2
%44 = add i32 %43, 8
%45 = zext i32 %44 to i64
%46 = inttoptr i64 %45 to i32*
%47 = load volatile i32, i32* %46
%48 = or i32 %47, %42
store volatile i32 %48, i32* %46
%49 = load i32, i32* %5
%50 = load i32, i32* %2
%51 = add i32 %50, 12
%52 = zext i32 %51 to i64
%53 = inttoptr i64 %52 to i32*
store volatile i32 %49, i32* %53
%54 = load i32, i32* %4
ret i32 %54
}

LLVM IR (-O2):
define i32 @UARTSubConfigMSRSPRModeEn(i32 %0) {
%2 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 191)
%3 = add i32 %0, 8
%4 = zext i32 %3 to i64
%5 = inttoptr i64 %4 to i32*
%6 = load volatile i32, i32* %5
%7 = and i32 %6, 16
%8 = load volatile i32, i32* %5
%9 = or i32 %8, 16
store volatile i32 %9, i32* %5
%10 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 128)
%11 = add i32 %0, 16
%12 = zext i32 %11 to i64
%13 = inttoptr i64 %12 to i32*
%14 = load volatile i32, i32* %13
%15 = and i32 %14, 64
%16 = load volatile i32, i32* %13
%17 = and i32 %16, -65
store volatile i32 %17, i32* %13
%18 = tail call i32 @UARTRegConfigModeEnable(i32 %0, i32 191)
%19 = load volatile i32, i32* %5
%20 = and i32 %19, -17
store volatile i32 %20, i32* %5
%21 = load volatile i32, i32* %5
%22 = or i32 %21, %7
store volatile i32 %22, i32* %5
%23 = add i32 %0, 12
%24 = zext i32 %23 to i64
%25 = inttoptr i64 %24 to i32*
store volatile i32 %2, i32* %25
ret i32 %15
}