#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
int /*<<< orphan*/ DEBUG_ASSERT(int);
int /*<<< orphan*/ IntEnable(unsigned long);
int /*<<< orphan*/ IntRegister(unsigned long, void (*)());
int TimerBaseValid(unsigned long);
unsigned long TimerIntNumberGet(unsigned long);
void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
                      void (*pfnHandler)(void)) {
  DEBUG_ASSERT(TimerBaseValid(ulBase));
  DEBUG_ASSERT((ulTimer == 0x000000ff) || (ulTimer == 0x0000ff00) ||
               (ulTimer == 0x0000ffff));
  ulBase = TimerIntNumberGet(ulBase);
  if (ulTimer & 0x000000ff) {
    IntRegister(ulBase, pfnHandler);
    IntEnable(ulBase);
  }
  if (ulTimer & 0x0000ff00) {
    IntRegister(ulBase + 1, pfnHandler);
    IntEnable(ulBase + 1);
  }
}


x86 assembly (clang, -O0):
<TimerIntRegister>:
push   %rbp
mov    %rsp,%rbp
sub    $0x20,%rsp
mov    %rdi,-0x8(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    -0x8(%rbp),%rdi
call   1050 <TimerBaseValid@plt>
mov    %eax,%edi
call   1070 <DEBUG_ASSERT@plt>
mov    $0x1,%al
cmpq   $0xff,-0x10(%rbp)
mov    %al,-0x19(%rbp)
je     11a8 <TimerIntRegister+0x58>
mov    $0x1,%al
cmpq   $0xff00,-0x10(%rbp)
mov    %al,-0x19(%rbp)
je     11a8 <TimerIntRegister+0x58>
cmpq   $0xffff,-0x10(%rbp)
sete   %al
mov    %al,-0x19(%rbp)
mov    -0x19(%rbp),%al
and    $0x1,%al
movzbl %al,%edi
call   1070 <DEBUG_ASSERT@plt>
mov    -0x8(%rbp),%rdi
call   1030 <TimerIntNumberGet@plt>
mov    %rax,-0x8(%rbp)
mov    -0x10(%rbp),%rax
and    $0xff,%rax
cmp    $0x0,%rax
je     11ec <TimerIntRegister+0x9c>
mov    -0x8(%rbp),%rdi
mov    -0x18(%rbp),%rsi
call   1060 <IntRegister@plt>
mov    -0x8(%rbp),%rdi
call   1040 <IntEnable@plt>
mov    -0x10(%rbp),%rax
and    $0xff00,%rax
cmp    $0x0,%rax
je     121e <TimerIntRegister+0xce>
mov    -0x8(%rbp),%rdi
add    $0x1,%rdi
mov    -0x18(%rbp),%rsi
call   1060 <IntRegister@plt>
mov    -0x8(%rbp),%rdi
add    $0x1,%rdi
call   1040 <IntEnable@plt>
add    $0x20,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<TimerIntRegister>:
push   %r15
push   %r14
push   %r12
push   %rbx
push   %rax
mov    %rdx,%r14
mov    %rsi,%r12
mov    %rdi,%r15
call   1050 <TimerBaseValid@plt>
mov    %eax,%edi
call   1070 <DEBUG_ASSERT@plt>
mov    $0x1,%edi
cmp    $0xff,%r12
je     1191 <TimerIntRegister+0x41>
cmp    $0xff00,%r12
je     1191 <TimerIntRegister+0x41>
xor    %edi,%edi
cmp    $0xffff,%r12
sete   %dil
call   1070 <DEBUG_ASSERT@plt>
mov    %r15,%rdi
call   1030 <TimerIntNumberGet@plt>
mov    %rax,%rbx
test   %r12b,%r12b
je     11b9 <TimerIntRegister+0x69>
mov    %rbx,%rdi
mov    %r14,%rsi
call   1060 <IntRegister@plt>
mov    %rbx,%rdi
call   1040 <IntEnable@plt>
test   $0xff00,%r12d
je     11e4 <TimerIntRegister+0x94>
add    $0x1,%rbx
mov    %rbx,%rdi
mov    %r14,%rsi
call   1060 <IntRegister@plt>
mov    %rbx,%rdi
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
jmp    1040 <IntEnable@plt>
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r14
pop    %r15
ret

LLVM IR (-O0):
define void @TimerIntRegister(i64 %0, i64 %1, void ()* %2) {
%4 = alloca i64
%5 = alloca i64
%6 = alloca void ()*
store i64 %0, i64* %4
store i64 %1, i64* %5
store void ()* %2, void ()** %6
%7 = load i64, i64* %4
%8 = call i32 @TimerBaseValid(i64 %7)
%9 = call i32 @DEBUG_ASSERT(i32 %8)
%10 = load i64, i64* %5
%11 = icmp eq i64 %10, 255
br i1 %11, label %18, label %12
12: ; preds = %3
%13 = load i64, i64* %5
%14 = icmp eq i64 %13, 65280
br i1 %14, label %18, label %15
15: ; preds = %12
%16 = load i64, i64* %5
%17 = icmp eq i64 %16, 65535
br label %18
18: ; preds = %15, %12, %3
%19 = phi i1 [ true, %12 ], [ true, %3 ], [ %17, %15 ]
%20 = zext i1 %19 to i32
%21 = call i32 @DEBUG_ASSERT(i32 %20)
%22 = load i64, i64* %4
%23 = call i64 @TimerIntNumberGet(i64 %22)
store i64 %23, i64* %4
%24 = load i64, i64* %5
%25 = and i64 %24, 255
%26 = icmp ne i64 %25, 0
br i1 %26, label %27, label %34
27: ; preds = %18
%28 = load i64, i64* %4
%29 = load void ()*, void ()** %6
%30 = bitcast void ()* %29 to void (...)*
%31 = call i32 @IntRegister(i64 %28, void (...)* %30)
%32 = load i64, i64* %4
%33 = call i32 @IntEnable(i64 %32)
br label %34
34: ; preds = %27, %18
%35 = load i64, i64* %5
%36 = and i64 %35, 65280
%37 = icmp ne i64 %36, 0
br i1 %37, label %38, label %47
38: ; preds = %34
%39 = load i64, i64* %4
%40 = add i64 %39, 1
%41 = load void ()*, void ()** %6
%42 = bitcast void ()* %41 to void (...)*
%43 = call i32 @IntRegister(i64 %40, void (...)* %42)
%44 = load i64, i64* %4
%45 = add i64 %44, 1
%46 = call i32 @IntEnable(i64 %45)
br label %47
47: ; preds = %38, %34
ret void
}

LLVM IR (-O2):
define void @TimerIntRegister(i64 %0, i64 %1, void ()* %2) {
%4 = tail call i32 @TimerBaseValid(i64 %0)
%5 = tail call i32 @DEBUG_ASSERT(i32 %4)
switch i64 %1, label %6 [
i64 65280, label %9
i64 255, label %9
]
6: ; preds = %3
%7 = icmp eq i64 %1, 65535
%8 = zext i1 %7 to i32
br label %9
9: ; preds = %3, %3, %6
%10 = phi i32 [ 1, %3 ], [ %8, %6 ], [ 1, %3 ]
%11 = tail call i32 @DEBUG_ASSERT(i32 %10)
%12 = tail call i64 @TimerIntNumberGet(i64 %0)
%13 = and i64 %1, 255
%14 = icmp eq i64 %13, 0
br i1 %14, label %19, label %15
15: ; preds = %9
%16 = bitcast void ()* %2 to void (...)*
%17 = tail call i32 @IntRegister(i64 %12, void (...)* %16)
%18 = tail call i32 @IntEnable(i64 %12)
br label %19
19: ; preds = %15, %9
%20 = and i64 %1, 65280
%21 = icmp eq i64 %20, 0
br i1 %21, label %27, label %22
22: ; preds = %19
%23 = add i64 %12, 1
%24 = bitcast void ()* %2 to void (...)*
%25 = tail call i32 @IntRegister(i64 %23, void (...)* %24)
%26 = tail call i32 @IntEnable(i64 %23)
br label %27
27: ; preds = %22, %19
ret void
}