#define NULL ((void *)0)
typedef unsigned long size_t; // Customize by platform.
typedef long intptr_t;
typedef unsigned long uintptr_t;
typedef long scalar_t__; // Either arithmetic or pointer type.
/* By default, we understand bool (as a convenience). */
typedef int bool;
#define false 0
#define true 1

/* Forward declarations */

/* Type definitions */

/* Variables and functions */
unsigned short UxCardPortIoInW(void *, unsigned char *, int);
int /*<<< orphan*/ UxCardPortIoOutW(void *, unsigned char *, int,
                                    unsigned short);
int /*<<< orphan*/ UxPause(int);
int FPGA_Download(unsigned short cardtype, unsigned long RegBase,
                  unsigned char *strbuf, unsigned char FPGA_SRC[],
                  int FPGA_LEN) {
  unsigned short i, j, k;
  unsigned short baseval, Mask_PROGRAM, Mask_DONE, Mask_CCLK, Mask_DIN;
  unsigned long addr;
  unsigned char *pFPGA;
  switch (cardtype) {
  case 5:
    addr = RegBase;
    Mask_PROGRAM = 0x0001;
    Mask_DONE = 0x0002;
    Mask_CCLK = 0x0100;
    Mask_DIN = 0x0400;
    baseval = 0x000d;
    break;
  default:
    (void)0;
    return -1;
  }
  for (j = 0x10, k = 0; j < (0x10 + 12); j++, k++) {
    if (!FPGA_SRC[j])
      break;
    strbuf[k] = FPGA_SRC[j];
  }
  strbuf[k++] = ' ';
  for (j = 0x2c; j < (0x2c + 10); j++, k++) {
    if (!FPGA_SRC[j])
      break;
    strbuf[k] = FPGA_SRC[j];
  }
  strbuf[k] = 0;
  (void)0;
  UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E,
                   baseval & ~Mask_PROGRAM);
  UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E, baseval);
  UxPause(50);
  if (UxCardPortIoInW(((void *)0), (unsigned char *)addr, 0x6E) & Mask_DONE) {
    (void)0;
    return -1;
  }
  pFPGA = FPGA_SRC;
  i = 0;
  while ((FPGA_SRC[i] != 0xFF) && (i < FPGA_LEN)) {
    i++;
  }
  (void)0;
  for (; i < FPGA_LEN; i++) {
    for (j = 0; j < 8; j++) {
      if (FPGA_SRC[i] & (0x80 >> j))
        baseval |= Mask_DIN;
      else
        baseval &= ~Mask_DIN;
      UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E, baseval);
      UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E,
                       baseval | Mask_CCLK);
      UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E, baseval);
    }
  }
  for (i = 0; i < 5; i++) {
    UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E,
                     baseval | Mask_CCLK);
    UxCardPortIoOutW(((void *)0), (unsigned char *)addr, 0x6E, baseval);
  }
  UxPause(100);
  if (UxCardPortIoInW(((void *)0), (unsigned char *)addr, 0x6E) & Mask_DONE) {
    (void)0;
  } else {
    (void)0;
    return -1;
  }
  return 0;
}


x86 assembly (clang, -O0):
<FPGA_Download>:
push   %rbp
mov    %rsp,%rbp
sub    $0x50,%rsp
mov    %di,%ax
mov    %ax,-0x6(%rbp)
mov    %rsi,-0x10(%rbp)
mov    %rdx,-0x18(%rbp)
mov    %rcx,-0x20(%rbp)
mov    %r8d,-0x24(%rbp)
mov    -0x6(%rbp),%ax
sub    $0x5,%ax
jne    118d <FPGA_Download+0x5d>
jmp    1162 <FPGA_Download+0x32>
mov    -0x10(%rbp),%rax
mov    %rax,-0x40(%rbp)
movw   $0x1,-0x2e(%rbp)
movw   $0x2,-0x30(%rbp)
movw   $0x100,-0x32(%rbp)
movw   $0x400,-0x34(%rbp)
movw   $0xd,-0x2c(%rbp)
jmp    1199 <FPGA_Download+0x69>
movl   $0xffffffff,-0x4(%rbp)
jmp    14c8 <FPGA_Download+0x398>
movw   $0x10,-0x28(%rbp)
movw   $0x0,-0x2a(%rbp)
movzwl -0x28(%rbp),%eax
cmp    $0x1c,%eax
jge    11fc <FPGA_Download+0xcc>
mov    -0x20(%rbp),%rax
movzwl -0x28(%rbp),%ecx
cmpb   $0x0,(%rax,%rcx,1)
jne    11c9 <FPGA_Download+0x99>
jmp    11fc <FPGA_Download+0xcc>
mov    -0x20(%rbp),%rax
movzwl -0x28(%rbp),%ecx
mov    (%rax,%rcx,1),%dl
mov    -0x18(%rbp),%rax
movzwl -0x2a(%rbp),%ecx
mov    %dl,(%rax,%rcx,1)
mov    -0x28(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x28(%rbp)
mov    -0x2a(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x2a(%rbp)
jmp    11a5 <FPGA_Download+0x75>
mov    -0x18(%rbp),%rax
mov    -0x2a(%rbp),%cx
mov    %cx,%dx
add    $0x1,%dx
mov    %dx,-0x2a(%rbp)
movzwl %cx,%ecx
movb   $0x20,(%rax,%rcx,1)
movw   $0x2c,-0x28(%rbp)
movzwl -0x28(%rbp),%eax
cmp    $0x36,%eax
jge    1273 <FPGA_Download+0x143>
mov    -0x20(%rbp),%rax
movzwl -0x28(%rbp),%ecx
cmpb   $0x0,(%rax,%rcx,1)
jne    1240 <FPGA_Download+0x110>
jmp    1273 <FPGA_Download+0x143>
mov    -0x20(%rbp),%rax
movzwl -0x28(%rbp),%ecx
mov    (%rax,%rcx,1),%dl
mov    -0x18(%rbp),%rax
movzwl -0x2a(%rbp),%ecx
mov    %dl,(%rax,%rcx,1)
mov    -0x28(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x28(%rbp)
mov    -0x2a(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x2a(%rbp)
jmp    121c <FPGA_Download+0xec>
mov    -0x18(%rbp),%rax
movzwl -0x2a(%rbp),%ecx
movb   $0x0,(%rax,%rcx,1)
mov    -0x40(%rbp),%rsi
movzwl -0x2c(%rbp),%eax
movzwl -0x2e(%rbp),%ecx
xor    $0xffffffff,%ecx
and    %ecx,%eax
xor    %ecx,%ecx
mov    %ecx,%edi
mov    $0x6e,%edx
movzwl %ax,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
movzwl -0x2c(%rbp),%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    $0x32,%edi
call   1030 <UxPause@plt>
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
call   1050 <UxCardPortIoInW@plt>
movzwl %ax,%eax
movzwl -0x30(%rbp),%ecx
and    %ecx,%eax
cmp    $0x0,%eax
je     12f1 <FPGA_Download+0x1c1>
movl   $0xffffffff,-0x4(%rbp)
jmp    14c8 <FPGA_Download+0x398>
mov    -0x20(%rbp),%rax
mov    %rax,-0x48(%rbp)
movw   $0x0,-0x26(%rbp)
mov    -0x20(%rbp),%rax
movzwl -0x26(%rbp),%ecx
movzbl (%rax,%rcx,1),%ecx
xor    %eax,%eax
cmp    $0xff,%ecx
mov    %al,-0x49(%rbp)
je     1329 <FPGA_Download+0x1f9>
movzwl -0x26(%rbp),%eax
cmp    -0x24(%rbp),%eax
setl   %al
mov    %al,-0x49(%rbp)
mov    -0x49(%rbp),%al
test   $0x1,%al
jne    1339 <FPGA_Download+0x209>
jmp    134a <FPGA_Download+0x21a>
mov    -0x26(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x26(%rbp)
jmp    12ff <FPGA_Download+0x1cf>
jmp    134f <FPGA_Download+0x21f>
movzwl -0x26(%rbp),%eax
cmp    -0x24(%rbp),%eax
jge    1429 <FPGA_Download+0x2f9>
movw   $0x0,-0x28(%rbp)
movzwl -0x28(%rbp),%eax
cmp    $0x8,%eax
jge    1413 <FPGA_Download+0x2e3>
mov    -0x20(%rbp),%rax
movzwl -0x26(%rbp),%ecx
movzbl (%rax,%rcx,1),%eax
movzwl -0x28(%rbp),%ecx
mov    $0x80,%edx
sar    %cl,%edx
mov    %edx,%ecx
and    %ecx,%eax
cmp    $0x0,%eax
je     13a6 <FPGA_Download+0x276>
movzwl -0x34(%rbp),%ecx
movzwl -0x2c(%rbp),%eax
or     %ecx,%eax
mov    %ax,-0x2c(%rbp)
jmp    13b7 <FPGA_Download+0x287>
movzwl -0x34(%rbp),%ecx
xor    $0xffffffff,%ecx
movzwl -0x2c(%rbp),%eax
and    %ecx,%eax
mov    %ax,-0x2c(%rbp)
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
movzwl -0x2c(%rbp),%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x40(%rbp),%rsi
movzwl -0x2c(%rbp),%eax
movzwl -0x32(%rbp),%ecx
or     %ecx,%eax
xor    %ecx,%ecx
mov    %ecx,%edi
mov    $0x6e,%edx
movzwl %ax,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
movzwl -0x2c(%rbp),%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x28(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x28(%rbp)
jmp    1362 <FPGA_Download+0x232>
jmp    1418 <FPGA_Download+0x2e8>
mov    -0x26(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x26(%rbp)
jmp    134f <FPGA_Download+0x21f>
movw   $0x0,-0x26(%rbp)
movzwl -0x26(%rbp),%eax
cmp    $0x5,%eax
jge    1482 <FPGA_Download+0x352>
mov    -0x40(%rbp),%rsi
movzwl -0x2c(%rbp),%eax
movzwl -0x32(%rbp),%ecx
or     %ecx,%eax
xor    %ecx,%ecx
mov    %ecx,%edi
mov    $0x6e,%edx
movzwl %ax,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
movzwl -0x2c(%rbp),%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    -0x26(%rbp),%ax
add    $0x1,%ax
mov    %ax,-0x26(%rbp)
jmp    142f <FPGA_Download+0x2ff>
mov    $0x64,%edi
call   1030 <UxPause@plt>
mov    -0x40(%rbp),%rsi
xor    %eax,%eax
mov    %eax,%edi
mov    $0x6e,%edx
call   1050 <UxCardPortIoInW@plt>
movzwl %ax,%eax
movzwl -0x30(%rbp),%ecx
and    %ecx,%eax
cmp    $0x0,%eax
je     14b5 <FPGA_Download+0x385>
jmp    14c1 <FPGA_Download+0x391>
movl   $0xffffffff,-0x4(%rbp)
jmp    14c8 <FPGA_Download+0x398>
movl   $0x0,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x50,%rsp
pop    %rbp
ret

x86 assembly (clang, -O2):
<FPGA_Download>:
push   %rbp
push   %r15
push   %r14
push   %r13
push   %r12
push   %rbx
push   %rax
mov    $0xffffffff,%r15d
cmp    $0x5,%di
jne    14e3 <FPGA_Download+0x3b3>
mov    %r8d,%ebp
mov    %rcx,%r12
mov    %rsi,%r13
mov    0x10(%rcx),%al
test   %al,%al
je     11ef <FPGA_Download+0xbf>
mov    %al,(%rdx)
mov    0x11(%r12),%al
test   %al,%al
je     11f3 <FPGA_Download+0xc3>
mov    %al,0x1(%rdx)
mov    0x12(%r12),%al
test   %al,%al
je     11f9 <FPGA_Download+0xc9>
mov    %al,0x2(%rdx)
mov    0x13(%r12),%al
test   %al,%al
je     11ff <FPGA_Download+0xcf>
mov    %al,0x3(%rdx)
mov    0x14(%r12),%al
test   %al,%al
je     1205 <FPGA_Download+0xd5>
mov    %al,0x4(%rdx)
mov    0x15(%r12),%al
test   %al,%al
je     120b <FPGA_Download+0xdb>
mov    %al,0x5(%rdx)
mov    0x16(%r12),%al
test   %al,%al
je     1211 <FPGA_Download+0xe1>
mov    %al,0x6(%rdx)
mov    0x17(%r12),%al
test   %al,%al
je     1217 <FPGA_Download+0xe7>
mov    %al,0x7(%rdx)
mov    0x18(%r12),%al
test   %al,%al
je     121d <FPGA_Download+0xed>
mov    %al,0x8(%rdx)
mov    0x19(%r12),%al
test   %al,%al
je     1223 <FPGA_Download+0xf3>
mov    %al,0x9(%rdx)
mov    0x1a(%r12),%al
test   %al,%al
je     1229 <FPGA_Download+0xf9>
mov    %al,0xa(%rdx)
mov    0x1b(%r12),%al
test   %al,%al
je     122f <FPGA_Download+0xff>
mov    %al,0xb(%rdx)
mov    $0xc,%ax
jmp    1233 <FPGA_Download+0x103>
xor    %eax,%eax
jmp    1233 <FPGA_Download+0x103>
mov    $0x1,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x2,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x3,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x4,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x5,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x6,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x7,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x8,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0x9,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0xa,%ax
jmp    1233 <FPGA_Download+0x103>
mov    $0xb,%ax
movzwl %ax,%eax
movb   $0x20,(%rdx,%rax,1)
mov    0x2c(%r12),%cl
test   %cl,%cl
je     12c8 <FPGA_Download+0x198>
mov    %cl,0x1(%rdx,%rax,1)
mov    0x2d(%r12),%cl
test   %cl,%cl
je     12cd <FPGA_Download+0x19d>
mov    %cl,0x2(%rdx,%rax,1)
mov    0x2e(%r12),%cl
test   %cl,%cl
je     12d2 <FPGA_Download+0x1a2>
mov    %cl,0x3(%rdx,%rax,1)
mov    0x2f(%r12),%cl
test   %cl,%cl
je     12d7 <FPGA_Download+0x1a7>
mov    %cl,0x4(%rdx,%rax,1)
mov    0x30(%r12),%cl
test   %cl,%cl
je     12dc <FPGA_Download+0x1ac>
mov    %cl,0x5(%rdx,%rax,1)
mov    0x31(%r12),%cl
test   %cl,%cl
je     12e1 <FPGA_Download+0x1b1>
mov    %cl,0x6(%rdx,%rax,1)
mov    0x32(%r12),%cl
test   %cl,%cl
je     12e6 <FPGA_Download+0x1b6>
mov    %cl,0x7(%rdx,%rax,1)
mov    0x33(%r12),%cl
test   %cl,%cl
je     12eb <FPGA_Download+0x1bb>
mov    %cl,0x8(%rdx,%rax,1)
mov    0x34(%r12),%cl
test   %cl,%cl
je     12f0 <FPGA_Download+0x1c0>
mov    %cl,0x9(%rdx,%rax,1)
lea    0xa(%rax),%rcx
mov    0x35(%r12),%bl
test   %bl,%bl
je     12f5 <FPGA_Download+0x1c5>
add    $0xb,%eax
mov    %bl,(%rdx,%rcx,1)
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x1,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x2,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x3,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x4,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x5,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x6,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x7,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x8,%eax
jmp    12f7 <FPGA_Download+0x1c7>
add    $0x9,%eax
jmp    12f7 <FPGA_Download+0x1c7>
mov    %ecx,%eax
movzwl %ax,%eax
movb   $0x0,(%rdx,%rax,1)
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    $0xc,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    $0xd,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    $0x32,%edi
call   1030 <UxPause@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
call   1050 <UxCardPortIoInW@plt>
test   $0x2,%al
jne    14e3 <FPGA_Download+0x3b3>
mov    $0xffff,%r15w
nopl   0x0(%rax)
add    $0x1,%r15d
movzwl %r15w,%eax
cmpb   $0xff,(%r12,%rax,1)
movzwl %r15w,%eax
je     1367 <FPGA_Download+0x237>
cmp    %ebp,%eax
jl     1350 <FPGA_Download+0x220>
mov    $0xd,%r14w
cmp    %ebp,%eax
jge    1405 <FPGA_Download+0x2d5>
mov    $0xd,%r14w
mov    %ebp,0x4(%rsp)
nopl   (%rax)
movzwl %r15w,%r15d
xor    %ebp,%ebp
cs nopw 0x0(%rax,%rax,1)
movzbl (%r12,%r15,1),%eax
mov    %ebp,%ecx
shl    %cl,%eax
and    $0x80,%eax
and    $0xfffffbff,%r14d
lea    (%r14,%rax,8),%r14d
movzwl %r14w,%ebx
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    %r14d,%eax
or     $0x100,%eax
movzwl %ax,%ecx
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
add    $0x1,%ebp
cmp    $0x8,%ebp
jne    1390 <FPGA_Download+0x260>
add    $0x1,%r15d
movzwl %r15w,%eax
mov    0x4(%rsp),%ebp
cmp    %ebp,%eax
jl     1380 <FPGA_Download+0x250>
mov    %r14d,%eax
or     $0x100,%eax
movzwl %ax,%ebx
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
movzwl %r14w,%ebp
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebp,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebp,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebp,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebp,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebx,%ecx
call   1040 <UxCardPortIoOutW@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
mov    %ebp,%ecx
call   1040 <UxCardPortIoOutW@plt>
mov    $0x64,%edi
call   1030 <UxPause@plt>
xor    %edi,%edi
mov    %r13,%rsi
mov    $0x6e,%edx
call   1050 <UxCardPortIoInW@plt>
shr    %eax
and    $0x1,%eax
add    $0xffffffff,%eax
movswl %ax,%r15d
mov    %r15d,%eax
add    $0x8,%rsp
pop    %rbx
pop    %r12
pop    %r13
pop    %r14
pop    %r15
pop    %rbp
ret

LLVM IR (-O0):
define i32 @FPGA_Download(i16 zeroext %0, i64 %1, i8* %2, i8* %3, i32 %4) {
%6 = alloca i32
%7 = alloca i16
%8 = alloca i64
%9 = alloca i8*
%10 = alloca i8*
%11 = alloca i32
%12 = alloca i16
%13 = alloca i16
%14 = alloca i16
%15 = alloca i16
%16 = alloca i16
%17 = alloca i16
%18 = alloca i16
%19 = alloca i16
%20 = alloca i64
%21 = alloca i8*
store i16 %0, i16* %7
store i64 %1, i64* %8
store i8* %2, i8** %9
store i8* %3, i8** %10
store i32 %4, i32* %11
%22 = load i16, i16* %7
%23 = zext i16 %22 to i32
switch i32 %23, label %26 [
i32 5, label %24
]
24: ; preds = %5
%25 = load i64, i64* %8
store i64 %25, i64* %20
store i16 1, i16* %16
store i16 2, i16* %17
store i16 256, i16* %18
store i16 1024, i16* %19
store i16 13, i16* %15
br label %27
26: ; preds = %5
store i32 -1, i32* %6
br label %235
27: ; preds = %24
store i16 16, i16* %13
store i16 0, i16* %14
br label %28
28: ; preds = %50, %27
%29 = load i16, i16* %13
%30 = zext i16 %29 to i32
%31 = icmp slt i32 %30, 28
br i1 %31, label %32, label %55
32: ; preds = %28
%33 = load i8*, i8** %10
%34 = load i16, i16* %13
%35 = zext i16 %34 to i64
%36 = getelementptr inbounds i8, i8* %33, i64 %35
%37 = load i8, i8* %36
%38 = icmp ne i8 %37, 0
br i1 %38, label %40, label %39
39: ; preds = %32
br label %55
40: ; preds = %32
%41 = load i8*, i8** %10
%42 = load i16, i16* %13
%43 = zext i16 %42 to i64
%44 = getelementptr inbounds i8, i8* %41, i64 %43
%45 = load i8, i8* %44
%46 = load i8*, i8** %9
%47 = load i16, i16* %14
%48 = zext i16 %47 to i64
%49 = getelementptr inbounds i8, i8* %46, i64 %48
store i8 %45, i8* %49
br label %50
50: ; preds = %40
%51 = load i16, i16* %13
%52 = add i16 %51, 1
store i16 %52, i16* %13
%53 = load i16, i16* %14
%54 = add i16 %53, 1
store i16 %54, i16* %14
br label %28
55: ; preds = %39, %28
%56 = load i8*, i8** %9
%57 = load i16, i16* %14
%58 = add i16 %57, 1
store i16 %58, i16* %14
%59 = zext i16 %57 to i64
%60 = getelementptr inbounds i8, i8* %56, i64 %59
store i8 32, i8* %60
store i16 44, i16* %13
br label %61
61: ; preds = %83, %55
%62 = load i16, i16* %13
%63 = zext i16 %62 to i32
%64 = icmp slt i32 %63, 54
br i1 %64, label %65, label %88
65: ; preds = %61
%66 = load i8*, i8** %10
%67 = load i16, i16* %13
%68 = zext i16 %67 to i64
%69 = getelementptr inbounds i8, i8* %66, i64 %68
%70 = load i8, i8* %69
%71 = icmp ne i8 %70, 0
br i1 %71, label %73, label %72
72: ; preds = %65
br label %88
73: ; preds = %65
%74 = load i8*, i8** %10
%75 = load i16, i16* %13
%76 = zext i16 %75 to i64
%77 = getelementptr inbounds i8, i8* %74, i64 %76
%78 = load i8, i8* %77
%79 = load i8*, i8** %9
%80 = load i16, i16* %14
%81 = zext i16 %80 to i64
%82 = getelementptr inbounds i8, i8* %79, i64 %81
store i8 %78, i8* %82
br label %83
83: ; preds = %73
%84 = load i16, i16* %13
%85 = add i16 %84, 1
store i16 %85, i16* %13
%86 = load i16, i16* %14
%87 = add i16 %86, 1
store i16 %87, i16* %14
br label %61
88: ; preds = %72, %61
%89 = load i8*, i8** %9
%90 = load i16, i16* %14
%91 = zext i16 %90 to i64
%92 = getelementptr inbounds i8, i8* %89, i64 %91
store i8 0, i8* %92
%93 = load i64, i64* %20
%94 = inttoptr i64 %93 to i8*
%95 = load i16, i16* %15
%96 = zext i16 %95 to i32
%97 = load i16, i16* %16
%98 = zext i16 %97 to i32
%99 = xor i32 %98, -1
%100 = and i32 %96, %99
%101 = trunc i32 %100 to i16
%102 = call i32 @UxCardPortIoOutW(i8* null, i8* %94, i32 110, i16 zeroext %101)
%103 = load i64, i64* %20
%104 = inttoptr i64 %103 to i8*
%105 = load i16, i16* %15
%106 = call i32 @UxCardPortIoOutW(i8* null, i8* %104, i32 110, i16 zeroext %105)
%107 = call i32 @UxPause(i32 50)
%108 = load i64, i64* %20
%109 = inttoptr i64 %108 to i8*
%110 = call zeroext i16 @UxCardPortIoInW(i8* null, i8* %109, i32 110)
%111 = zext i16 %110 to i32
%112 = load i16, i16* %17
%113 = zext i16 %112 to i32
%114 = and i32 %111, %113
%115 = icmp ne i32 %114, 0
br i1 %115, label %116, label %117
116: ; preds = %88
store i32 -1, i32* %6
br label %235
117: ; preds = %88
%118 = load i8*, i8** %10
store i8* %118, i8** %21
store i16 0, i16* %12
br label %119
119: ; preds = %134, %117
%120 = load i8*, i8** %10
%121 = load i16, i16* %12
%122 = zext i16 %121 to i64
%123 = getelementptr inbounds i8, i8* %120, i64 %122
%124 = load i8, i8* %123
%125 = zext i8 %124 to i32
%126 = icmp ne i32 %125, 255
br i1 %126, label %127, label %132
127: ; preds = %119
%128 = load i16, i16* %12
%129 = zext i16 %128 to i32
%130 = load i32, i32* %11
%131 = icmp slt i32 %129, %130
br label %132
132: ; preds = %127, %119
%133 = phi i1 [ false, %119 ], [ %131, %127 ]
br i1 %133, label %134, label %137
134: ; preds = %132
%135 = load i16, i16* %12
%136 = add i16 %135, 1
store i16 %136, i16* %12
br label %119
137: ; preds = %132
br label %138
138: ; preds = %197, %137
%139 = load i16, i16* %12
%140 = zext i16 %139 to i32
%141 = load i32, i32* %11
%142 = icmp slt i32 %140, %141
br i1 %142, label %143, label %200
143: ; preds = %138
store i16 0, i16* %13
br label %144
144: ; preds = %193, %143
%145 = load i16, i16* %13
%146 = zext i16 %145 to i32
%147 = icmp slt i32 %146, 8
br i1 %147, label %148, label %196
148: ; preds = %144
%149 = load i8*, i8** %10
%150 = load i16, i16* %12
%151 = zext i16 %150 to i64
%152 = getelementptr inbounds i8, i8* %149, i64 %151
%153 = load i8, i8* %152
%154 = zext i8 %153 to i32
%155 = load i16, i16* %13
%156 = zext i16 %155 to i32
%157 = ashr i32 128, %156
%158 = and i32 %154, %157
%159 = icmp ne i32 %158, 0
br i1 %159, label %160, label %167
160: ; preds = %148
%161 = load i16, i16* %19
%162 = zext i16 %161 to i32
%163 = load i16, i16* %15
%164 = zext i16 %163 to i32
%165 = or i32 %164, %162
%166 = trunc i32 %165 to i16
store i16 %166, i16* %15
br label %175
167: ; preds = %148
%168 = load i16, i16* %19
%169 = zext i16 %168 to i32
%170 = xor i32 %169, -1
%171 = load i16, i16* %15
%172 = zext i16 %171 to i32
%173 = and i32 %172, %170
%174 = trunc i32 %173 to i16
store i16 %174, i16* %15
br label %175
175: ; preds = %167, %160
%176 = load i64, i64* %20
%177 = inttoptr i64 %176 to i8*
%178 = load i16, i16* %15
%179 = call i32 @UxCardPortIoOutW(i8* null, i8* %177, i32 110, i16 zeroext %178)
%180 = load i64, i64* %20
%181 = inttoptr i64 %180 to i8*
%182 = load i16, i16* %15
%183 = zext i16 %182 to i32
%184 = load i16, i16* %18
%185 = zext i16 %184 to i32
%186 = or i32 %183, %185
%187 = trunc i32 %186 to i16
%188 = call i32 @UxCardPortIoOutW(i8* null, i8* %181, i32 110, i16 zeroext %187)
%189 = load i64, i64* %20
%190 = inttoptr i64 %189 to i8*
%191 = load i16, i16* %15
%192 = call i32 @UxCardPortIoOutW(i8* null, i8* %190, i32 110, i16 zeroext %191)
br label %193
193: ; preds = %175
%194 = load i16, i16* %13
%195 = add i16 %194, 1
store i16 %195, i16* %13
br label %144
196: ; preds = %144
br label %197
197: ; preds = %196
%198 = load i16, i16* %12
%199 = add i16 %198, 1
store i16 %199, i16* %12
br label %138
200: ; preds = %138
store i16 0, i16* %12
br label %201
201: ; preds = %219, %200
%202 = load i16, i16* %12
%203 = zext i16 %202 to i32
%204 = icmp slt i32 %203, 5
br i1 %204, label %205, label %222
205: ; preds = %201
%206 = load i64, i64* %20
%207 = inttoptr i64 %206 to i8*
%208 = load i16, i16* %15
%209 = zext i16 %208 to i32
%210 = load i16, i16* %18
%211 = zext i16 %210 to i32
%212 = or i32 %209, %211
%213 = trunc i32 %212 to i16
%214 = call i32 @UxCardPortIoOutW(i8* null, i8* %207, i32 110, i16 zeroext %213)
%215 = load i64, i64* %20
%216 = inttoptr i64 %215 to i8*
%217 = load i16, i16* %15
%218 = call i32 @UxCardPortIoOutW(i8* null, i8* %216, i32 110, i16 zeroext %217)
br label %219
219: ; preds = %205
%220 = load i16, i16* %12
%221 = add i16 %220, 1
store i16 %221, i16* %12
br label %201
222: ; preds = %201
%223 = call i32 @UxPause(i32 100)
%224 = load i64, i64* %20
%225 = inttoptr i64 %224 to i8*
%226 = call zeroext i16 @UxCardPortIoInW(i8* null, i8* %225, i32 110)
%227 = zext i16 %226 to i32
%228 = load i16, i16* %17
%229 = zext i16 %228 to i32
%230 = and i32 %227, %229
%231 = icmp ne i32 %230, 0
br i1 %231, label %232, label %233
232: ; preds = %222
br label %234
233: ; preds = %222
store i32 -1, i32* %6
br label %235
234: ; preds = %232
store i32 0, i32* %6
br label %235
235: ; preds = %234, %233, %116, %26
%236 = load i32, i32* %6
ret i32 %236
}

LLVM IR (-O2):
define i32 @FPGA_Download(i16 zeroext %0, i64 %1, i8* nocapture writeonly %2, i8* nocapture %3, i32 %4) {
%6 = icmp eq i16 %0, 5
br i1 %6, label %7, label %209
7: ; preds = %5
%8 = getelementptr inbounds i8, i8* %3, i64 16
%9 = load i8, i8* %8
%10 = icmp eq i8 %9, 0
br i1 %10, label %67, label %11
11: ; preds = %7
store i8 %9, i8* %2
%12 = getelementptr inbounds i8, i8* %3, i64 17
%13 = load i8, i8* %12
%14 = icmp eq i8 %13, 0
br i1 %14, label %67, label %15
15: ; preds = %11
%16 = getelementptr inbounds i8, i8* %2, i64 1
store i8 %13, i8* %16
%17 = getelementptr inbounds i8, i8* %3, i64 18
%18 = load i8, i8* %17
%19 = icmp eq i8 %18, 0
br i1 %19, label %67, label %20
20: ; preds = %15
%21 = getelementptr inbounds i8, i8* %2, i64 2
store i8 %18, i8* %21
%22 = getelementptr inbounds i8, i8* %3, i64 19
%23 = load i8, i8* %22
%24 = icmp eq i8 %23, 0
br i1 %24, label %67, label %25
25: ; preds = %20
%26 = getelementptr inbounds i8, i8* %2, i64 3
store i8 %23, i8* %26
%27 = getelementptr inbounds i8, i8* %3, i64 20
%28 = load i8, i8* %27
%29 = icmp eq i8 %28, 0
br i1 %29, label %67, label %30
30: ; preds = %25
%31 = getelementptr inbounds i8, i8* %2, i64 4
store i8 %28, i8* %31
%32 = getelementptr inbounds i8, i8* %3, i64 21
%33 = load i8, i8* %32
%34 = icmp eq i8 %33, 0
br i1 %34, label %67, label %35
35: ; preds = %30
%36 = getelementptr inbounds i8, i8* %2, i64 5
store i8 %33, i8* %36
%37 = getelementptr inbounds i8, i8* %3, i64 22
%38 = load i8, i8* %37
%39 = icmp eq i8 %38, 0
br i1 %39, label %67, label %40
40: ; preds = %35
%41 = getelementptr inbounds i8, i8* %2, i64 6
store i8 %38, i8* %41
%42 = getelementptr inbounds i8, i8* %3, i64 23
%43 = load i8, i8* %42
%44 = icmp eq i8 %43, 0
br i1 %44, label %67, label %45
45: ; preds = %40
%46 = getelementptr inbounds i8, i8* %2, i64 7
store i8 %43, i8* %46
%47 = getelementptr inbounds i8, i8* %3, i64 24
%48 = load i8, i8* %47
%49 = icmp eq i8 %48, 0
br i1 %49, label %67, label %50
50: ; preds = %45
%51 = getelementptr inbounds i8, i8* %2, i64 8
store i8 %48, i8* %51
%52 = getelementptr inbounds i8, i8* %3, i64 25
%53 = load i8, i8* %52
%54 = icmp eq i8 %53, 0
br i1 %54, label %67, label %55
55: ; preds = %50
%56 = getelementptr inbounds i8, i8* %2, i64 9
store i8 %53, i8* %56
%57 = getelementptr inbounds i8, i8* %3, i64 26
%58 = load i8, i8* %57
%59 = icmp eq i8 %58, 0
br i1 %59, label %67, label %60
60: ; preds = %55
%61 = getelementptr inbounds i8, i8* %2, i64 10
store i8 %58, i8* %61
%62 = getelementptr inbounds i8, i8* %3, i64 27
%63 = load i8, i8* %62
%64 = icmp eq i8 %63, 0
br i1 %64, label %67, label %65
65: ; preds = %60
%66 = getelementptr inbounds i8, i8* %2, i64 11
store i8 %63, i8* %66
br label %67
67: ; preds = %65, %60, %55, %50, %45, %40, %35, %30, %25, %20, %15, %11, %7
%68 = phi i16 [ 0, %7 ], [ 1, %11 ], [ 2, %15 ], [ 3, %20 ], [ 4, %25 ], [ 5, %30 ], [ 6, %35 ], [ 7, %40 ], [ 8, %45 ], [ 9, %50 ], [ 10, %55 ], [ 11, %60 ], [ 12, %65 ]
%69 = zext i16 %68 to i64
%70 = getelementptr inbounds i8, i8* %2, i64 %69
store i8 32, i8* %70
%71 = add nuw nsw i64 %69, 1
%72 = add nuw nsw i16 %68, 11
%73 = getelementptr inbounds i8, i8* %3, i64 44
%74 = load i8, i8* %73
%75 = icmp eq i8 %74, 0
%76 = trunc i64 %71 to i16
br i1 %75, label %142, label %77
77: ; preds = %67
%78 = getelementptr inbounds i8, i8* %2, i64 %71
store i8 %74, i8* %78
%79 = add nuw nsw i64 %69, 2
%80 = getelementptr inbounds i8, i8* %3, i64 45
%81 = load i8, i8* %80
%82 = icmp eq i8 %81, 0
%83 = trunc i64 %79 to i16
br i1 %82, label %142, label %84
84: ; preds = %77
%85 = getelementptr inbounds i8, i8* %2, i64 %79
store i8 %81, i8* %85
%86 = add nuw nsw i64 %69, 3
%87 = getelementptr inbounds i8, i8* %3, i64 46
%88 = load i8, i8* %87
%89 = icmp eq i8 %88, 0
%90 = trunc i64 %86 to i16
br i1 %89, label %142, label %91
91: ; preds = %84
%92 = getelementptr inbounds i8, i8* %2, i64 %86
store i8 %88, i8* %92
%93 = add nuw nsw i64 %69, 4
%94 = getelementptr inbounds i8, i8* %3, i64 47
%95 = load i8, i8* %94
%96 = icmp eq i8 %95, 0
%97 = trunc i64 %93 to i16
br i1 %96, label %142, label %98
98: ; preds = %91
%99 = getelementptr inbounds i8, i8* %2, i64 %93
store i8 %95, i8* %99
%100 = add nuw nsw i64 %69, 5
%101 = getelementptr inbounds i8, i8* %3, i64 48
%102 = load i8, i8* %101
%103 = icmp eq i8 %102, 0
%104 = trunc i64 %100 to i16
br i1 %103, label %142, label %105
105: ; preds = %98
%106 = getelementptr inbounds i8, i8* %2, i64 %100
store i8 %102, i8* %106
%107 = add nuw nsw i64 %69, 6
%108 = getelementptr inbounds i8, i8* %3, i64 49
%109 = load i8, i8* %108
%110 = icmp eq i8 %109, 0
%111 = trunc i64 %107 to i16
br i1 %110, label %142, label %112
112: ; preds = %105
%113 = getelementptr inbounds i8, i8* %2, i64 %107
store i8 %109, i8* %113
%114 = add nuw nsw i64 %69, 7
%115 = getelementptr inbounds i8, i8* %3, i64 50
%116 = load i8, i8* %115
%117 = icmp eq i8 %116, 0
%118 = trunc i64 %114 to i16
br i1 %117, label %142, label %119
119: ; preds = %112
%120 = getelementptr inbounds i8, i8* %2, i64 %114
store i8 %116, i8* %120
%121 = add nuw nsw i64 %69, 8
%122 = getelementptr inbounds i8, i8* %3, i64 51
%123 = load i8, i8* %122
%124 = icmp eq i8 %123, 0
%125 = trunc i64 %121 to i16
br i1 %124, label %142, label %126
126: ; preds = %119
%127 = getelementptr inbounds i8, i8* %2, i64 %121
store i8 %123, i8* %127
%128 = add nuw nsw i64 %69, 9
%129 = getelementptr inbounds i8, i8* %3, i64 52
%130 = load i8, i8* %129
%131 = icmp eq i8 %130, 0
%132 = trunc i64 %128 to i16
br i1 %131, label %142, label %133
133: ; preds = %126
%134 = getelementptr inbounds i8, i8* %2, i64 %128
store i8 %130, i8* %134
%135 = add nuw nsw i64 %69, 10
%136 = getelementptr inbounds i8, i8* %3, i64 53
%137 = load i8, i8* %136
%138 = icmp eq i8 %137, 0
%139 = trunc i64 %135 to i16
br i1 %138, label %142, label %140
140: ; preds = %133
%141 = getelementptr inbounds i8, i8* %2, i64 %135
store i8 %137, i8* %141
br label %142
142: ; preds = %140, %133, %126, %119, %112, %105, %98, %91, %84, %77, %67
%143 = phi i16 [ %76, %67 ], [ %83, %77 ], [ %90, %84 ], [ %97, %91 ], [ %104, %98 ], [ %111, %105 ], [ %118, %112 ], [ %125, %119 ], [ %132, %126 ], [ %139, %133 ], [ %72, %140 ]
%144 = zext i16 %143 to i64
%145 = getelementptr inbounds i8, i8* %2, i64 %144
store i8 0, i8* %145
%146 = inttoptr i64 %1 to i8*
%147 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext 12)
%148 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext 13)
%149 = tail call i32 @UxPause(i32 50)
%150 = tail call zeroext i16 @UxCardPortIoInW(i8* null, i8* %146, i32 110)
%151 = and i16 %150, 2
%152 = icmp eq i16 %151, 0
br i1 %152, label %153, label %209
153: ; preds = %142, %153
%154 = phi i16 [ %162, %153 ], [ 0, %142 ]
%155 = zext i16 %154 to i64
%156 = getelementptr inbounds i8, i8* %3, i64 %155
%157 = load i8, i8* %156
%158 = icmp ne i8 %157, -1
%159 = zext i16 %154 to i32
%160 = icmp slt i32 %159, %4
%161 = select i1 %158, i1 %160, i1 false
%162 = add i16 %154, 1
br i1 %161, label %153, label %163
163: ; preds = %153
br i1 %160, label %164, label %169
164: ; preds = %163, %205
%165 = phi i16 [ %206, %205 ], [ %154, %163 ]
%166 = phi i16 [ %198, %205 ], [ 13, %163 ]
%167 = zext i16 %165 to i64
%168 = getelementptr inbounds i8, i8* %3, i64 %167
br label %188
169: ; preds = %205, %163
%170 = phi i16 [ 13, %163 ], [ %198, %205 ]
%171 = or i16 %170, 256
%172 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %171)
%173 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %170)
%174 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %171)
%175 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %170)
%176 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %171)
%177 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %170)
%178 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %171)
%179 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %170)
%180 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %171)
%181 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %170)
%182 = tail call i32 @UxPause(i32 100)
%183 = tail call zeroext i16 @UxCardPortIoInW(i8* null, i8* %146, i32 110)
%184 = lshr i16 %183, 1
%185 = and i16 %184, 1
%186 = add nsw i16 %185, -1
%187 = sext i16 %186 to i32
br label %209
188: ; preds = %164, %188
%189 = phi i32 [ 0, %164 ], [ %203, %188 ]
%190 = phi i16 [ %166, %164 ], [ %198, %188 ]
%191 = load i8, i8* %168
%192 = zext i8 %191 to i32
%193 = lshr i32 128, %189
%194 = and i32 %193, %192
%195 = icmp eq i32 %194, 0
%196 = and i16 %190, -1025
%197 = select i1 %195, i16 0, i16 1024
%198 = or i16 %197, %196
%199 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %198)
%200 = or i16 %198, 256
%201 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %200)
%202 = tail call i32 @UxCardPortIoOutW(i8* null, i8* %146, i32 110, i16 zeroext %198)
%203 = add nuw nsw i32 %189, 1
%204 = icmp eq i32 %203, 8
br i1 %204, label %205, label %188
205: ; preds = %188
%206 = add i16 %165, 1
%207 = zext i16 %206 to i32
%208 = icmp slt i32 %207, %4
br i1 %208, label %164, label %169
209: ; preds = %169, %142, %5
%210 = phi i32 [ -1, %5 ], [ -1, %142 ], [ %187, %169 ]
ret i32 %210
}