int slow_clock_debug() {
  int slow_chks = 0;
  *(volatile unsigned long *)((void *)0xfffffc00 + 0x30) =
      0x00 | (((0) & 7) << 2);
  {
    int i;
    for (i = (1) * 6; i--;) {
    }
  };
  while ((*(volatile unsigned long *)((void *)0xfffffc00 + 0x68) & 0x08) == 0) {
    if (slow_chks++ > 100)
      break;
  }
  return (slow_chks);
}


x86 assembly (clang, -O0):
<slow_clock_debug>:
push   %rbp
mov    %rsp,%rbp
movl   $0x0,-0x4(%rbp)
mov    $0xfffffc00,%eax
movq   $0x0,0x30(%rax)
movl   $0x6,-0x8(%rbp)
mov    -0x8(%rbp),%eax
mov    %eax,%ecx
add    $0xffffffff,%ecx
mov    %ecx,-0x8(%rbp)
cmp    $0x0,%eax
je     1138 <slow_clock_debug+0x38>
jmp    111f <slow_clock_debug+0x1f>
jmp    113d <slow_clock_debug+0x3d>
mov    $0xfffffc00,%eax
mov    0x68(%rax),%rax
and    $0x8,%rax
cmp    $0x0,%rax
jne    1172 <slow_clock_debug+0x72>
mov    -0x4(%rbp),%eax
mov    %eax,%ecx
add    $0x1,%ecx
mov    %ecx,-0x4(%rbp)
cmp    $0x64,%eax
jle    116d <slow_clock_debug+0x6d>
jmp    1172 <slow_clock_debug+0x72>
jmp    113d <slow_clock_debug+0x3d>
mov    -0x4(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<slow_clock_debug>:
mov    $0xfffffc68,%ecx
movq   $0x0,-0x38(%rcx)
xor    %eax,%eax
nop
testq  $0x8,(%rcx)
jne    113c <slow_clock_debug+0x3c>
testq  $0x8,(%rcx)
jne    1139 <slow_clock_debug+0x39>
testq  $0x8,(%rcx)
jne    113d <slow_clock_debug+0x3d>
add    $0x3,%eax
cmp    $0x66,%eax
jne    1110 <slow_clock_debug+0x10>
mov    $0x66,%eax
ret
add    $0x1,%eax
ret
add    $0x2,%eax
ret

LLVM IR (-O0):
define i32 @slow_clock_debug() {
%1 = alloca i32
%2 = alloca i32
store i32 0, i32* %1
store volatile i64 0, i64* bitcast (i8* getelementptr (i8, i8* inttoptr (i64 4294966272 to i8*), i64 48) to i64*)
store i32 6, i32* %2
br label %3
3: ; preds = %7, %0
%4 = load i32, i32* %2
%5 = add nsw i32 %4, -1
store i32 %5, i32* %2
%6 = icmp ne i32 %4, 0
br i1 %6, label %7, label %8
7: ; preds = %3
br label %3
8: ; preds = %3
br label %9
9: ; preds = %18, %8
%10 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* inttoptr (i64 4294966272 to i8*), i64 104) to i64*)
%11 = and i64 %10, 8
%12 = icmp eq i64 %11, 0
br i1 %12, label %13, label %19
13: ; preds = %9
%14 = load i32, i32* %1
%15 = add nsw i32 %14, 1
store i32 %15, i32* %1
%16 = icmp sgt i32 %14, 100
br i1 %16, label %17, label %18
17: ; preds = %13
br label %19
18: ; preds = %13
br label %9
19: ; preds = %17, %9
%20 = load i32, i32* %1
ret i32 %20
}

LLVM IR (-O2):
define i32 @slow_clock_debug() {
store volatile i64 0, i64* inttoptr (i64 4294966320 to i64*)
br label %1
1: ; preds = %14, %0
%2 = phi i32 [ 0, %0 ], [ %15, %14 ]
%3 = load volatile i64, i64* inttoptr (i64 4294966376 to i64*)
%4 = and i64 %3, 8
%5 = icmp eq i64 %4, 0
br i1 %5, label %6, label %21
6: ; preds = %1
%7 = load volatile i64, i64* inttoptr (i64 4294966376 to i64*)
%8 = and i64 %7, 8
%9 = icmp eq i64 %8, 0
br i1 %9, label %10, label %19
10: ; preds = %6
%11 = load volatile i64, i64* inttoptr (i64 4294966376 to i64*)
%12 = and i64 %11, 8
%13 = icmp eq i64 %12, 0
br i1 %13, label %14, label %17
14: ; preds = %10
%15 = add nuw nsw i32 %2, 3
%16 = icmp eq i32 %15, 102
br i1 %16, label %21, label %1
17: ; preds = %10
%18 = add nuw nsw i32 %2, 2
br label %21
19: ; preds = %6
%20 = add nuw nsw i32 %2, 1
br label %21
21: ; preds = %1, %14, %19, %17
%22 = phi i32 [ %18, %17 ], [ %20, %19 ], [ 102, %14 ], [ %2, %1 ]
ret i32 %22
}