unsigned char Slinear2ulaw(int sample) {
  static int exp_lut[256] = {
      0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,
      4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
      5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
      6, 6, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
      7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7};
  int sign, exponent, mantissa;
  unsigned char ulawbyte;
  if (sample < 0) {
    sign = 0x80;
    sample = -sample;
  } else
    sign = 0;
  if (sample > 32635)
    sample = 32635;
  sample = sample + 0x84;
  exponent = exp_lut[(sample >> 7) & 0xFF];
  mantissa = (sample >> (exponent + 3)) & 0x0F;
  ulawbyte = ~(sign | (exponent << 4) | mantissa);
  return (ulawbyte);
}


x86 assembly (clang, -O0):
<Slinear2ulaw>:
push   %rbp
mov    %rsp,%rbp
mov    %edi,-0x4(%rbp)
cmpl   $0x0,-0x4(%rbp)
jge    1125 <Slinear2ulaw+0x25>
movl   $0x80,-0x8(%rbp)
xor    %eax,%eax
sub    -0x4(%rbp),%eax
mov    %eax,-0x4(%rbp)
jmp    112c <Slinear2ulaw+0x2c>
movl   $0x0,-0x8(%rbp)
cmpl   $0x7f7b,-0x4(%rbp)
jle    1140 <Slinear2ulaw+0x40>
movl   $0x7f7b,-0x4(%rbp)
mov    -0x4(%rbp),%eax
add    $0x84,%eax
mov    %eax,-0x4(%rbp)
mov    -0x4(%rbp),%eax
sar    $0x7,%eax
and    $0xff,%eax
movslq %eax,%rcx
lea    0x2ed0(%rip),%rax
mov    (%rax,%rcx,4),%eax
mov    %eax,-0xc(%rbp)
mov    -0x4(%rbp),%eax
mov    -0xc(%rbp),%ecx
add    $0x3,%ecx
sar    %cl,%eax
and    $0xf,%eax
mov    %eax,-0x10(%rbp)
mov    -0x8(%rbp),%eax
mov    -0xc(%rbp),%ecx
shl    $0x4,%ecx
or     %ecx,%eax
or     -0x10(%rbp),%eax
xor    $0xffffffff,%eax
mov    %al,-0x11(%rbp)
movzbl -0x11(%rbp),%eax
pop    %rbp
ret

x86 assembly (clang, -O2):
<Slinear2ulaw>:
mov    %edi,%edx
shr    $0x18,%edx
and    $0xffffff80,%edx
mov    %edi,%eax
neg    %eax
cmovs  %edi,%eax
cmp    $0x7f7b,%eax
mov    $0x7f7b,%esi
cmovb  %eax,%esi
add    $0x84,%esi
mov    %esi,%eax
shr    $0x7,%eax
lea    0xed2(%rip),%rcx
mov    (%rcx,%rax,4),%eax
lea    0x3(%rax),%ecx
shr    %cl,%esi
and    $0xf,%esi
shl    $0x4,%eax
or     %edx,%eax
or     %esi,%eax
not    %al
ret

LLVM IR (-O0):
@Slinear2ulaw.exp_lut = internal global [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @Slinear2ulaw(i32 %0) {
%2 = alloca i32
%3 = alloca i32
%4 = alloca i32
%5 = alloca i32
%6 = alloca i8
store i32 %0, i32* %2
%7 = load i32, i32* %2
%8 = icmp slt i32 %7, 0
br i1 %8, label %9, label %12
9: ; preds = %1
store i32 128, i32* %3
%10 = load i32, i32* %2
%11 = sub nsw i32 0, %10
store i32 %11, i32* %2
br label %13
12: ; preds = %1
store i32 0, i32* %3
br label %13
13: ; preds = %12, %9
%14 = load i32, i32* %2
%15 = icmp sgt i32 %14, 32635
br i1 %15, label %16, label %17
16: ; preds = %13
store i32 32635, i32* %2
br label %17
17: ; preds = %16, %13
%18 = load i32, i32* %2
%19 = add nsw i32 %18, 132
store i32 %19, i32* %2
%20 = load i32, i32* %2
%21 = ashr i32 %20, 7
%22 = and i32 %21, 255
%23 = sext i32 %22 to i64
%24 = getelementptr inbounds [256 x i32], [256 x i32]* @Slinear2ulaw.exp_lut, i64 0, i64 %23
%25 = load i32, i32* %24
store i32 %25, i32* %4
%26 = load i32, i32* %2
%27 = load i32, i32* %4
%28 = add nsw i32 %27, 3
%29 = ashr i32 %26, %28
%30 = and i32 %29, 15
store i32 %30, i32* %5
%31 = load i32, i32* %3
%32 = load i32, i32* %4
%33 = shl i32 %32, 4
%34 = or i32 %31, %33
%35 = load i32, i32* %5
%36 = or i32 %34, %35
%37 = xor i32 %36, -1
%38 = trunc i32 %37 to i8
store i8 %38, i8* %6
%39 = load i8, i8* %6
ret i8 %39
}

LLVM IR (-O2):
@Slinear2ulaw.exp_lut = internal unnamed_addr constant [256 x i32] [i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7]
define zeroext i8 @Slinear2ulaw(i32 %0) {
%2 = lshr i32 %0, 24
%3 = and i32 %2, 128
%4 = tail call i32 @llvm.abs.i32(i32 %0, i1 true)
%5 = icmp ult i32 %4, 32635
%6 = select i1 %5, i32 %4, i32 32635
%7 = add nuw nsw i32 %6, 132
%8 = lshr i32 %7, 7
%9 = zext i32 %8 to i64
%10 = getelementptr inbounds [256 x i32], [256 x i32]* @Slinear2ulaw.exp_lut, i64 0, i64 %9
%11 = load i32, i32* %10
%12 = add nsw i32 %11, 3
%13 = lshr i32 %7, %12
%14 = and i32 %13, 15
%15 = shl i32 %11, 4
%16 = or i32 %15, %3
%17 = or i32 %16, %14
%18 = trunc i32 %17 to i8
%19 = xor i8 %18, -1
ret i8 %19
}