void TimerHalModuleClockConfig(void) {
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x4)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xdc)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0xe0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x12c)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x0)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x0)))) &
          (0x00000003u)) != (0x2u))
    ;
  (*((volatile unsigned int *)(((0x44E00000) + 0) + (0x60)))) = (0x2u);
  while (((*((volatile unsigned int *)(((0x44E00000) + 0) + (0x60)))) &
          (0x00000003u)) != (0x2u))
    ;
}


x86 assembly (clang, -O0):
<TimerHalModuleClockConfig>:
push   %rbp
mov    %rsp,%rbp
mov    $0x44e00004,%eax
movl   $0x2,(%rax)
mov    $0x44e00004,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1127 <TimerHalModuleClockConfig+0x27>
jmp    110f <TimerHalModuleClockConfig+0xf>
mov    $0x44e0000c,%eax
movl   $0x2,(%rax)
mov    $0x44e0000c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     114a <TimerHalModuleClockConfig+0x4a>
jmp    1132 <TimerHalModuleClockConfig+0x32>
mov    $0x44e000dc,%eax
movl   $0x2,(%rax)
mov    $0x44e000dc,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     116d <TimerHalModuleClockConfig+0x6d>
jmp    1155 <TimerHalModuleClockConfig+0x55>
mov    $0x44e000e0,%eax
movl   $0x2,(%rax)
mov    $0x44e000e0,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     1190 <TimerHalModuleClockConfig+0x90>
jmp    1178 <TimerHalModuleClockConfig+0x78>
mov    $0x44e0012c,%eax
movl   $0x2,(%rax)
mov    $0x44e0012c,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11b3 <TimerHalModuleClockConfig+0xb3>
jmp    119b <TimerHalModuleClockConfig+0x9b>
mov    $0x44e00000,%eax
movl   $0x2,(%rax)
mov    $0x44e00000,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11d6 <TimerHalModuleClockConfig+0xd6>
jmp    11be <TimerHalModuleClockConfig+0xbe>
mov    $0x44e00060,%eax
movl   $0x2,(%rax)
mov    $0x44e00060,%eax
mov    (%rax),%eax
and    $0x3,%eax
cmp    $0x2,%eax
je     11f9 <TimerHalModuleClockConfig+0xf9>
jmp    11e1 <TimerHalModuleClockConfig+0xe1>
pop    %rbp
ret

x86 assembly (clang, -O2):
<TimerHalModuleClockConfig>:
movl   $0x2,0x44e00004
nopl   0x0(%rax,%rax,1)
mov    0x44e00004,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1110 <TimerHalModuleClockConfig+0x10>
movl   $0x2,0x44e0000c
nopw   0x0(%rax,%rax,1)
mov    0x44e0000c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1130 <TimerHalModuleClockConfig+0x30>
movl   $0x2,0x44e000dc
nopw   0x0(%rax,%rax,1)
mov    0x44e000dc,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1150 <TimerHalModuleClockConfig+0x50>
movl   $0x2,0x44e000e0
nopw   0x0(%rax,%rax,1)
mov    0x44e000e0,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1170 <TimerHalModuleClockConfig+0x70>
movl   $0x2,0x44e0012c
nopw   0x0(%rax,%rax,1)
mov    0x44e0012c,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    1190 <TimerHalModuleClockConfig+0x90>
movl   $0x2,0x44e00000
nopw   0x0(%rax,%rax,1)
mov    0x44e00000,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11b0 <TimerHalModuleClockConfig+0xb0>
movl   $0x2,0x44e00060
nopw   0x0(%rax,%rax,1)
mov    0x44e00060,%eax
and    $0x3,%eax
cmp    $0x2,%eax
jne    11d0 <TimerHalModuleClockConfig+0xd0>
ret

LLVM IR (-O0):
define void @TimerHalModuleClockConfig() {
store volatile i32 2, i32* inttoptr (i64 1155530756 to i32*)
br label %1
1: ; preds = %5, %0
%2 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%3 = and i32 %2, 3
%4 = icmp ne i32 %3, 2
br i1 %4, label %5, label %6
5: ; preds = %1
br label %1
6: ; preds = %1
store volatile i32 2, i32* inttoptr (i64 1155530764 to i32*)
br label %7
7: ; preds = %11, %6
%8 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%9 = and i32 %8, 3
%10 = icmp ne i32 %9, 2
br i1 %10, label %11, label %12
11: ; preds = %7
br label %7
12: ; preds = %7
store volatile i32 2, i32* inttoptr (i64 1155530972 to i32*)
br label %13
13: ; preds = %17, %12
%14 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%15 = and i32 %14, 3
%16 = icmp ne i32 %15, 2
br i1 %16, label %17, label %18
17: ; preds = %13
br label %13
18: ; preds = %13
store volatile i32 2, i32* inttoptr (i64 1155530976 to i32*)
br label %19
19: ; preds = %23, %18
%20 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%21 = and i32 %20, 3
%22 = icmp ne i32 %21, 2
br i1 %22, label %23, label %24
23: ; preds = %19
br label %19
24: ; preds = %19
store volatile i32 2, i32* inttoptr (i64 1155531052 to i32*)
br label %25
25: ; preds = %29, %24
%26 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%27 = and i32 %26, 3
%28 = icmp ne i32 %27, 2
br i1 %28, label %29, label %30
29: ; preds = %25
br label %25
30: ; preds = %25
store volatile i32 2, i32* inttoptr (i64 1155530752 to i32*)
br label %31
31: ; preds = %35, %30
%32 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%33 = and i32 %32, 3
%34 = icmp ne i32 %33, 2
br i1 %34, label %35, label %36
35: ; preds = %31
br label %31
36: ; preds = %31
store volatile i32 2, i32* inttoptr (i64 1155530848 to i32*)
br label %37
37: ; preds = %41, %36
%38 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%39 = and i32 %38, 3
%40 = icmp ne i32 %39, 2
br i1 %40, label %41, label %42
41: ; preds = %37
br label %37
42: ; preds = %37
ret void
}

LLVM IR (-O2):
define void @TimerHalModuleClockConfig() {
store volatile i32 2, i32* inttoptr (i64 1155530756 to i32*)
br label %1
1: ; preds = %1, %0
%2 = load volatile i32, i32* inttoptr (i64 1155530756 to i32*)
%3 = and i32 %2, 3
%4 = icmp eq i32 %3, 2
br i1 %4, label %5, label %1
5: ; preds = %1
store volatile i32 2, i32* inttoptr (i64 1155530764 to i32*)
br label %6
6: ; preds = %6, %5
%7 = load volatile i32, i32* inttoptr (i64 1155530764 to i32*)
%8 = and i32 %7, 3
%9 = icmp eq i32 %8, 2
br i1 %9, label %10, label %6
10: ; preds = %6
store volatile i32 2, i32* inttoptr (i64 1155530972 to i32*)
br label %11
11: ; preds = %11, %10
%12 = load volatile i32, i32* inttoptr (i64 1155530972 to i32*)
%13 = and i32 %12, 3
%14 = icmp eq i32 %13, 2
br i1 %14, label %15, label %11
15: ; preds = %11
store volatile i32 2, i32* inttoptr (i64 1155530976 to i32*)
br label %16
16: ; preds = %16, %15
%17 = load volatile i32, i32* inttoptr (i64 1155530976 to i32*)
%18 = and i32 %17, 3
%19 = icmp eq i32 %18, 2
br i1 %19, label %20, label %16
20: ; preds = %16
store volatile i32 2, i32* inttoptr (i64 1155531052 to i32*)
br label %21
21: ; preds = %21, %20
%22 = load volatile i32, i32* inttoptr (i64 1155531052 to i32*)
%23 = and i32 %22, 3
%24 = icmp eq i32 %23, 2
br i1 %24, label %25, label %21
25: ; preds = %21
store volatile i32 2, i32* inttoptr (i64 1155530752 to i32*)
br label %26
26: ; preds = %26, %25
%27 = load volatile i32, i32* inttoptr (i64 1155530752 to i32*)
%28 = and i32 %27, 3
%29 = icmp eq i32 %28, 2
br i1 %29, label %30, label %26
30: ; preds = %26
store volatile i32 2, i32* inttoptr (i64 1155530848 to i32*)
br label %31
31: ; preds = %31, %30
%32 = load volatile i32, i32* inttoptr (i64 1155530848 to i32*)
%33 = and i32 %32, 3
%34 = icmp eq i32 %33, 2
br i1 %34, label %35, label %31
35: ; preds = %31
ret void
}