D eep RTL 2: A Versatile Model for RTL -Related Tasks (2025)

Abstract: The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in register transfer level (RTL) code generation and understanding. While previous studies have demonstrated the efficacy of fine-tuning LLMs for these generation-based tasks, embedding-based tasks, which are equally critical to EDA workflows, have been largely overlooked. These tasks, including natural language code search, RTL code functionality equivalence checking, and performance prediction, are essential for accelerating and optimizing the hardware design process. To address this gap, we present \textbf{DeepRTL2} , a family of versatile LLMs that unifies both generation- and embedding-based tasks related to RTL. By simultaneously tackling a broad range of tasks, DeepRTL2 represents the first model to provide a comprehensive solution to the diverse challenges in EDA. Through extensive experiments, we show that DeepRTL2 achieves state-of-the-art performance across all evaluated tasks.

## introduction the rapid advancement of large language models (llms) has had a profound impact on various domains @xcite , including electronic design automation (eda). recently, llms have shown remarkable potential in automating and enhancing tasks related to the generation and understanding of register transfer level (rtl) code @xcite @xcite . these models are capable of generating rtl code from high-level natural language instructions or summarizing the functionality of existing rtl code, thereby substantially improving the efficiency of hardware design workflows. while the application of llms to these generationbased tasks has yielded impressive results, their full potential at the rtl stage remains underexplored, particularly in embedding-based tasks that are equally crucial to the design process. embedding-based tasks like natural language code search, rtl code functionality equivalence checking, and performance prediction are vital for accelerating and optimizing the hardware design process. natural language code search allows designers to quickly query large rtl codebases with simple natural language descriptions, enabling efficient identification and reuse of relevant modules, thus reducing search time. moreover, verification and optimization are two key time-consuming bottlenecks in hardware design. rtl code functionality equivalence checking can significantly reduce the time spent on verification by quickly assessing whether two designs are functionally equivalent. performance prediction tasks, such as power, performance, and area (ppa) estimation, enable early evaluation of rtl design efficiency. accurate performance predictions can guide rtl code optimization, minimizing the need for time-intensive trial-and-error. together, these tasks enhance code reuse, verify functionality, and provide early performance feedback, resulting in a more streamlined and efficient design workflow. previous methods have attempted to apply machine learning solutions for hardware design verification @xcite and performance prediction @xcite , but they are typically design-specific, lack generalizable representations for rtl designs, or do not operate directly at the rtl stage. in this paper, we introduce deeprtl2, a family of versatile llms designed to address both generation-and embedding-based tasks related to rtl. by unifying these tasks in a single model, deeprtl2 offers a comprehensive solution to the multifaceted challenges inherent in eda. unlike previous work, which has primarily focused on generation, deeprtl2 is the first model to provide a unified framework for handling a broad range of critical eda tasks, including code generation, understanding, natural language code search, functionality equivalence checking, and performance prediction. figure 1 provides an overview of our model. to achieve this, we have carefully curated a comprehensive dataset and developed new benchmarks for each task, with a particular focus on the embedding-based tasks, for which no existing datasets or benchmarks are available. we have adopted state-of-the-art decoder-only models, such as llama-3.1 @xcite and @xcite , as our base models for fine-tuning, given their superior performance over other architectures in the open-source llm space. to enable these models to handle both generationand embedding-based tasks, we adapt the generative representational instruction tuning (grit) approach @xcite for fine-tuning, ensuring that deeprtl2 can effectively manage the diverse tasks at the rtl stage. through extensive experimentation, we demonstrate that the deeprtl2 series achieves state-of-the-art performance across all evaluated tasks. ## dataset previous research has predominantly focused on generation-based tasks, resulting in a notable gap in available datasets for the embedding-based tasks considered in this paper. moreover, the availability of rtl code is limited even for generation-based tasks, due to the proprietary nature of hardware designs. to fill this gap, we have curated a comprehensive dataset tailored to support both generationand embedding-based tasks at the rtl stage. furthermore, we have established new benchmarks specifically for the embedding-based tasks, which have been largely neglected in previous work. ## conclusion in this work, we present deeprtl2, a novel family of llms that unifies both generation-and embedding-based tasks at the rtl stage, offering a comprehensive solution to the diverse challenges in eda. by addressing critical tasks including rtl code generation, understanding, natural language code search, functionality equivalence checking, and performance prediction, deep-rtl2 significantly improves the efficiency of hardware design workflows. to develop deeprtl2, we have curated a comprehensive dataset and established new benchmarks specifically designed for these tasks, particularly the embedding-based ones, for which no suitable resources previously existed. furthermore, we adapt the grit approach to fine-tune the model, enabling it to manage both generation-and embedding-based tasks effectively. extensive experimentation demonstrates that deep-rtl2 achieves state-of-the-art performance across all evaluated tasks, advancing the application of llms in hardware design.