Guaranteed Guess: A Language Modeling Approach for CISC -to- RISC Transpilation with Testing Guarantees (2025)

Abstract: The hardware ecosystem is rapidly evolving, with increasing interest in translating low-level programs across different *instruction set architectures* (ISAs) in a quick, flexible, and correct way to enhance the portability and longevity of existing code. A particularly challenging class of this transpilation problem is translating between complex- (CISC) and reduced- (RISC) hardware architectures, due to fundamental differences in instruction complexity, memory models, and execution paradigms. In this work, we introduce GG (**G**uaranteed **G**uess), an ISA-centric transpilation pipeline that combines the translation power of pre-trained large language models (LLMs) with the rigor of established software testing constructs. Our method generates candidate translations using an LLM from one ISA to another, and embeds such translations within a software-testing framework to build quantifiable confidence in the translation. We evaluate our GG approach over two diverse datasets, enforce high code coverage ( > 98%) across unit tests, and achieve functional/semantic correctness of 99% on HumanEval programs and 49% on BringupBench programs, respectively. Further, we compare our approach to the state-of-the-art Rosetta 2 framework on Apple Silicon, showcasing 1.73 \times faster runtime performance, 1.47 \times better energy efficiency, and 2.41 \times better memory usage for our transpiled code, demonstrating the effectiveness of GG for real-world CISC-to-RISC translation tasks. We will open-source our codes, data, models, and benchmarks to establish a common foundation for ISA-level code translation research.

## introduction the modern hardware landscape is undergoing a fundamental transformation. as moore's law slows and dennard scaling ends @xcite we use "transpilation" to describe the task of translating code between assembly languages. 1974; @xcite , the demand for energyefficient, high-performance architectures has accelerated, particularly with the rise of machine learning (ml) applications @xcite . hyperscalers are increasingly constrained by power and thermal limits @xcite , prompting a reevaluation of datacenter infrastructure. a major outcome of this shift is the growing adoption of arm-based processors. historically dominant in mobile and edge devices due to their risc-based low-power design, arm cpus were largely absent from datacenters because of their performance gap with x86 (a cisc architecture) @xcite . however, this gap has narrowed significantly: arm-based chips now match x86 on many benchmarks @xcite and deliver superior energy efficiency @xcite . in 2024, x86 designs dominated over 80% of data center servers @xcite , but arm predicts that its share will reach 50% by the end of 2025 @xcite . industry adoption supports this trend, with arm-based systems like nvidia's grace cpu (nvidia corporation, 2024), amazon's graviton @xcite , and microsoft's arm-compatible os stack (verma, 2024) accelerating deployment. this rapid hardware transition introduces a significant software gap. legacy binaries compiled for x86 often lack source code and cannot be recompiled for arm. while solutions like apple's rosetta 2 (apple inc., 2020) and qemu's emulation service @xcite provide runtime virtualization, they introduce memory and performance overheads. compilers struggle to retarget opaque binaries @xcite , and decompilation-based approaches are fragile or legally restricted @xcite . a scalable, accurate, and architecture-aware binaryto-binary translation solution remains elusive. in this work, we introduce guaranteed guess (gg), an assembly-to-assembly transpiler that trans-lates x86 binaries (cisc) into efficient arm or risc-v (risc) equivalents using a custom-trained large language model (llm). our approach is open-source, avoids the virtualization tax by generating native arm/risc-v assembly, and directly supports legacy binaries without decompilation. transpiling across isas is non-trivial. cisc and risc architectures differ in register-memory semantics, instruction complexity, and binary length. in general, x86 instructions are fewer but more expressive, while risc requires longer, register-centric code sequences. these differences must be learned implicitly by the model, which we achieve by incorporating a hardware-informed design, using tokenizer extensions, and leveraging context-aware training. our approach builds high-accuracy llm-based transpilers by incorporating hardware-aware insights into the training process, enabling the model to better capture the cisc-specific patterns of x86 and generate semantically valid risc targets such as arm. however, unlike high-level language tasks, conventional nlp correctness proxies (e.g., bleu, perplexity) fall short for binary translation where functional correctness is paramount. therefore, we embed our predictions within rigorous software testing infrastructure to provide test-driven guarantees of correctness using software engineering primitives of code coverage criteria. holistically, our paper makes the following key contributions: ## background and related work we describe systems-centric related work with respect to virtualization and emulation, in addition to ml-centric code translation recent work. our approach for gg features a combination of both, by applying ml techniques to a system-level objective of assembly translation, incorporating software testing guarantees for correctness evaluation. ## guaranteed guess in this section, we explore the two primary components of building our gg transpiler: data generation ( §3.1) and model training ( §3.2). we also describe a hardware-software co-designed tokenizer extension ( §3.3), which we used to enhance our models performance. ## experiments and evaluation in this section, we describe our experimental setup, training methodology, evaluation benchmarks, and the metrics used to assess the accuracy and robustness of our cisc-to-risc transpiler. ## results and analysis we evaluate the efficacy of our transpiler for cisc-to-risc assembly translation, focusing on the correctness of the output arm assembly. utilizing the metrics defined above ( §4.2), we compare our approach with state-of-the-art coding llms and evaluate our approach for x86 to arm transpilation ( ## conclusion we introduce guaranteed guess (gg ), a languagemodel-based cisc-to-risc transpiler that unifies pre-trained llms with a test-driven validation framework. gg directly transpiles x86 assembly into efficient arm and risc-v binaries while embedding unit tests to enforce functional correctness. through architectural enhancements, such as tokenizer extension, rope extrapolation, and beam decoding, gg achieves 99.39% accuracy in humaneval and 49.23% in bringupbench, outperforming both existing llms and dynamic virtualization systems like rosetta. our analysis highlights how isa similarity and compiler optimizations affect accuracy, with gg achieving 1.73× faster execution, 1.47× lower energy use, and 2.41× smaller memory footprint than rosetta on real-world binaries. these results position gg as a scalable, test-verified solution for efficient, cross-isa binary translation.