Algorithms with low computational intensity show interesting performance and power consumption behavior on multicore processors. We choose the lattice-Boltzmann method (LBM)  as a prototype for this scenario in order to show if and how single-chip performance and power characteristics can be generalized to the highly parallel case. LBM is an algorithm for CFD simulations that has gained popularity due to its ease of implementation and suitability for complex geometries. In this paper we perform a thorough analysis of a sparse-lattice LBM implementation on the Intel Sandy Bridge processor. Starting from a single-core performance model we can describe the intra-chip saturation characteristics of the code and its optimal operating point in terms of energy to solution as a function of the propagation method, the clock frequency, and the SIMD vectorization. We then show how these findings may be extrapolated to the massively parallel level on a petascale-class machine, and quantify the energy-saving potential of various optimizations. We find that high single-core performance and a correct choice of the number of cores used on the chip are the essential factors for lowest energy to solution with minimal loss of performance . In the highly parallel case, these guidelines are found to be even more important for fixing the optimal performance-energy operating point , especially when taking the system's baseline power consumption and the MPI communication characteristics into account. Simplistic measures often applied by users and computing centers, such as setting a low clock speed for memory-bound applications, have limited impact .
Memory-bound algorithms show complex performance and energy consumption behavior on multicore processors. We choose the lattice-Boltzmann method (LBM) on an Intel Sandy Bridge cluster as a prototype scenario to investigate if and how single-chip performance and power characteristics can be generalized to the highly parallel case. First we perform an analysis of a sparse-lattice LBM implementation for complex geometries. Using a single-core performance model , we predict the intra-chip saturation characteristics and the optimal operating point in terms of energy to solution as a function of implementation details, clock frequency, vectorization, and number of active cores per chip. We show that high single-core performance and a correct choice of the number of active cores per chip are the essential optimizations for lowest energy to solution at minimal performance degradation. Then we extrapolate to the MPI-parallel level and quantify the energy-saving potential of various optimizations and execution modes, where we find these guidelines to be even more important , especially when communication overhead is non-negligible. In our setup we could achieve energy savings of 35\% in this case, compared to a naive approach. We also demonstrate that a simple non-reflective reduction of the clock speed leaves most of the energy saving potential unused .
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Algorithms with low computational intensity show interesting performance and power
Memory-bound algorithms show complex performance and energy
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and the SIMD vectorization. We then show how these findings may be extrapolated to the massively parallel level on a petascale-class machine, and quantify the energy-saving potential of various optimizations. We find
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with minimal loss of performance . In the highly parallel case, these guidelines are found
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for fixing the optimal performance-energy operating point
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taking the system's baseline power consumption and the MPI communication characteristics into account. Simplistic measures often applied by users and computing centers, such as setting a low clock speed for memory-bound applications, have limited impact
communication overhead is non-negligible. In our setup we could achieve energy savings of 35\% in this case, compared to a naive approach. We also demonstrate that a simple non-reflective reduction of the clock speed leaves most of the energy saving potential unused