With aggressively shrinking process technologies , physical design faces severe challenges and early detection of failures is mandated. It may otherwise lead to many iterations and thus impact time-to-market. This has encouraged to devise a feedback mechanism from a lower abstraction level of the design flow towards the higher levels. Some of these efforts include placement driven synthesis, routability (timing) driven placement etc. Motivated by this philosophy , we propose a novel global routing method using monotone staircase routing regions (channels), defined at the floorplanning stage. The intent is to identify the feasibility of a floorplan topology of the given design netlist by estimating routability, routed net length and the number of vias while taking into account global congestion scenario across the layout. This framework works on both unreserved as well as HV reserved layer model for M(\geq 2) metal layers and accommodates different capacity profiles of the routing resources, due to uniform or different cases of metal pitch variation across the metals layers akin to the latest technologies. This algorithm takes O(n^2kt) time for a given design with n blocks and k nets having at most t terminals. Experimental results on MCNC/GSRC floorplanning benchmarks show 100\\%DIF < routability while congestion in the routing regions restricted to 100\\%. The routed net length for all t-terminal (t\geq 2) nets is comparable with the steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles are also obtained.\end{abstract} %DIF > routing completion, with no over-congestion in the routing regions reported. The wirelength for the t-terminal (t\geq 2) nets is comparable with the Steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles is also presented, along with congestion and runtime results.
With aggressively shrinking process nodes , physical design methods face severe challenges due to poor convergence and uncertainty in getting an optimal solution. An early detection of potential failures is thus mandated. This has encouraged to devise a feedback mechanism from a lower abstraction level of the design flow to the higher ones, such as placement driven synthesis, routability (timing) driven placement etc. Motivated by this , we propose an early global routing framework using pattern routing following the floorplanning stage. We assess feasibility of a floorplan topology of a given design by estimating routability, routed wirelength and vias count while addressing the global congestion scenario across the layout. Different capacity profiles for the routing regions, such as uniform or non-uniform different cases of metal pitch variation across the metals layers ensures adaptability to technology scaling. The proposed algorithm STAIRoute takes O(n^2kt) time for a given design with n blocks and k nets having at most t terminals. Experimental results on a set of floorplanning benchmark circuits show 100\\%DIF < routability while congestion in the routing regions restricted to 100\\%. The routed net length for all t-terminal (t\geq 2) nets is comparable with the steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles are also obtained.\end{abstract} %DIF > routing completion, with no over-congestion in the routing regions reported. The wirelength for the t-terminal (t\geq 2) nets is comparable with the Steiner length computed by FLUTE. An estimation on the number of vias for different capacity profiles is also presented, along with congestion and runtime results.
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philosophy
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a novel global routing method using monotone staircase routing regions (channels), defined at
an early global routing framework using pattern routing following
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This framework works on both unreserved as well as HV reserved layer model for M(\geq 2) metal layers and accommodates different capacity profiles of the routing resources, due to uniform or
Different capacity profiles for the routing regions, such as uniform or non-uniform
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MCNC/GSRC floorplanning benchmarks
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