【Intel Core i3处理器列表】
Intel Core i3 是「Core i品牌」四个子系列之一。
从Sandy Bridge微架构开始，Intel把微架构和代号改成相同名字。
== 桌上型处理器 ==
=== Westmere微架构 ===
==== "Clarkdale" (32 nm) ====
=== Sandy Bridge微架构 ===
==== "Sandy Bridge" (32 nm) ====
=== Ivy Bridge微架构 ===
==== "Ivy Bridge" (22 nm) ====
=== Haswell微架构 ===
==== "Haswell-DT" (22 nm) ====
=== Skylake微架构 ===
==== "Skylake-S" (14 nm) ====
=== Kaby Lake微架构 ===
==== "Kaby Lake-S" (14 nm) ====
=== Coffee Lake微架构 ===
==== "Coffee Lake-S" (14 nm) ====
==== "Coffee Lake-H" (14 nm) ====
=== Comet Lake微架构 ===
== 移动型处理器 ==
=== Westmere微架构（第一代） ===
==== "Arrandale" (MCP, 32 nm) ====
*所有型号支援: MMX,SSE,SSE2, SSE3,SSSE3,SSE4.1, SSE4.2, EIST, Intel 64, XD bit, Intel VT-x,超执行绪,Smart Cache.
* 整合Intel HD Graphics
=== Sandy Bridge microarchitecture (2nd generation) ===
==== "Sandy Bridge" (32 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Smart Cache, Intel Insider.
* Core i3-2310E, Core i3-2340UE have support for ECC memory.
* Core i3-2310E, Core i3-2330E and Core i3-2340UE do not have support for Intel Insider
* Transistors: 624 million
* Die size: 149 mm²
=== Ivy Bridge microarchitecture (3rd generation) ===
==== "Ivy Bridge" (22 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Smart Cache, Intel Insider.
* Core i3-3120ME, i3-3217UE have support for ECC memory.
* Core i3-3120ME, i3-3217UE do not have support for Intel Insider.
* Core i3-3229Y supports AES-NI.
* Die size: 94 mm²
=== Haswell microarchitecture (4th generation) ===
==== "Haswell-MB" (22 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Smart Cache.
==== "Haswell-ULT" (SiP, 22 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, AES-NI, Smart Cache.
* Core i3-4010U and higher also support Intel VT-d
* Transistors: 1.3 billion
* Die size: 181 mm²
==== "Haswell-ULX" (SiP, 22 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, AES-NI, Smart Cache.
* Transistors: 1.3 billion
* Die size: 181 mm²
==== "Haswell-H" (22 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Smart Cache.
* Transistors: 1.3 billion
* Die size: 181 mm²
* Embedded models support ECC memory
=== Broadwell microarchitecture (5th generation) ===
==== "Broadwell-U" (14 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, AES-NI, Smart Cache, and configurable TDP (cTDP) down
=== Skylake microarchitecture (6th generation) ===
==== "Skylake-H" (14 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, AES-NI, Smart Cache.
* Transistors: TBD
* Die size: TBD
* Embedded models support ECC memory
==== "Skylake-U" (14 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, AES-NI, Smart Cache, and configurable TDP (cTDP) down (except 6006U)
=== Kaby Lake microarchitecture (7th generation) ===
==== "Kaby Lake-H" (14 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, AES-NI, Smart Cache.
* Transistors: TBD
* Die size: TBD
* Embedded models support ECC memory
==== "Kaby Lake-U" (14 nm) ====
* 全系列支援指令: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, SGX, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel VT-d, Hyper-threading, AES-NI, Smart Cache, and configurable TDP (cTDP) down.
=== Ice Lake microarchitecture (10th generation) ===
=== Comet Lake microarchitecture (10th generation) ===
==== "Comet Lake-U" (dual-core, 14 nm) ====
==== "Comet Lake-Y" (dual-core, 14 nm) ====
=== Ice Lake微架构 ===
==== "Ice Lake-U" (dual-core, 10 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4, AVX, AVX指令集, AVX-512, FMA指令集, 英特尔软件防护扩展, SpeedStep (SST), X86-64, XD bit (an NX位元 implementation), Intel VT-x, X86虚拟化, Intel睿频加速, 超执行绪, AES指令集, CPU缓存, 深度学习, and 热设计功耗 (cTDP).
==== "Ice Lake-Y" (dual-core, 10 nm) ====
* All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4, AVX, AVX指令集, AVX-512, FMA指令集, 英特尔软件防护扩展, SpeedStep (SST), X86-64, XD bit (an NX位元 implementation), Intel VT-x, X86虚拟化, Intel睿频加速, 超执行绪, AES指令集, CPU缓存, 深度学习, and 热设计功耗 (cTDP) (except 1000NG4).
=== Willow Cove microarchitecture (11th generation) ===
==== "Tiger Lake-UP3" (10 nm SuperFin) ====
* All models support: SSE4.1, SSE4.2, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6 (except SRK08), TB4, and configurable TDP (cTDP).
* -RE models support ECC memory.
==== "Tiger Lake-UP4" (10 nm SuperFin) ====
* All models support: SSE4.1, SSE4.2, AVX2, AVX-512, FMA3, Speed Shift Technology (SST), Intel 64, Intel VT-x, Intel VT-d, Turbo Boost, Hyper-threading, AES-NI, Smart Cache, DL Boost, Optane memory, GNA 2.0, IPU6, TB4, and configurable TDP (cTDP).
== 外部连结 ==
*  Intel 产品规格资料库date=20110701192600